summaryrefslogtreecommitdiffstatshomepage
diff options
context:
space:
mode:
author angelosa <salese_corp_ltd@email.it>2017-10-07 00:53:55 +0200
committer angelosa <salese_corp_ltd@email.it>2017-10-07 00:54:36 +0200
commit6460f2bbecddeaec976ec157c5ae12ef18b9bea8 (patch)
treef7abf75738deef847e996c9422757bfb9888c924
parent6c7d397655ad869d1bad5b463d792557306d3a53 (diff)
huc6270.cpp: VRAM is actually only 0-0x7fff, area 0x8000-0xffff is open bus and cannot be written to (fixes MT #06622, #06696, Ruin / Exile / Championship Rally video garbage bugs) (nw)
-rw-r--r--src/devices/video/huc6270.cpp37
1 files changed, 32 insertions, 5 deletions
diff --git a/src/devices/video/huc6270.cpp b/src/devices/video/huc6270.cpp
index 1db4819104a..baa66ae5134 100644
--- a/src/devices/video/huc6270.cpp
+++ b/src/devices/video/huc6270.cpp
@@ -48,6 +48,7 @@ TODO
- Fix timing of VRAM-SATB DMA
- Implement VRAM-VRAM DMA
- DMA speeds differ depending on the dot clock selected in the huc6270
+ - Convert VRAM bus to actual space address (optimization)
**********************************************************************/
@@ -510,9 +511,18 @@ WRITE_LINE_MEMBER( huc6270_device::vsync_changed )
int sour_inc = ( m_dcr & 0x0004 ) ? -1 : +1;
LOG("doing dma sour = %04x, desr = %04x, lenr = %04x\n", m_sour, m_desr, m_lenr );
+
do {
- uint16_t data = m_vram[ m_sour & m_vram_mask ];
- m_vram[ m_desr & m_vram_mask ] = data;
+ uint16_t data;
+
+ // area 0x8000-0xffff cannot be r/w (open bus)
+ if((m_sour & 0x8000) == 0)
+ data = m_vram[ m_sour & m_vram_mask ];
+ else
+ data = 0;
+
+ if((m_desr & 0x8000) == 0)
+ m_vram[ m_desr & m_vram_mask ] = data;
m_sour += sour_inc;
m_desr += desr_inc;
m_lenr -= 1;
@@ -605,7 +615,15 @@ READ8_MEMBER( huc6270_device::read )
if ( m_register_index == VxR )
{
m_marr += vram_increments[ ( m_cr >> 11 ) & 3 ];
- m_vrr = m_vram[ m_marr & m_vram_mask ];
+
+ if((m_marr & 0x8000) == 0)
+ m_vrr = m_vram[ m_marr & m_vram_mask ];
+ else
+ {
+ // TODO: test with real HW
+ m_vrr = 0;
+ logerror("%s Open Bus VRAM read (register read) %04x\n",this->tag(),m_marr);
+ }
}
break;
}
@@ -632,7 +650,14 @@ WRITE8_MEMBER( huc6270_device::write )
case MARR: /* memory address read register LSB */
m_marr = ( m_marr & 0xFF00 ) | data;
- m_vrr = m_vram[ m_marr & m_vram_mask ];
+ if((m_marr & 0x8000) == 0)
+ m_vrr = m_vram[ m_marr & m_vram_mask ];
+ else
+ {
+ // TODO: test with real HW
+ m_vrr = 0;
+ logerror("%s Open Bus VRAM read (memory address) %04x\n",this->tag(),m_marr);
+ }
break;
case VxR: /* vram write data LSB */
@@ -726,7 +751,9 @@ WRITE8_MEMBER( huc6270_device::write )
case VxR: /* vram write data MSB */
m_vwr = ( m_vwr & 0x00FF ) | ( data << 8 );
- m_vram[ m_mawr & m_vram_mask ] = m_vwr;
+ // area 0x8000-0xffff is NOP and cannot be written to.
+ if((m_mawr & 0x8000) == 0)
+ m_vram[ m_mawr & m_vram_mask ] = m_vwr;
m_mawr += vram_increments[ ( m_cr >> 11 ) & 3 ];
break;