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author Miodrag Milanovic <mmicko@gmail.com>2016-06-29 08:34:30 +0200
committer Miodrag Milanovic <mmicko@gmail.com>2016-06-29 08:34:30 +0200
commit63f9a01f8c5d43b9cfe68c2d401a84647d19c10e (patch)
treea1f1874aa84850bddbebd2b0e0bfc3e1c77ce8c4
parent1f6f1bfd6cfb748d9c5e159d6bd014bab8d30944 (diff)
Cleanup and version bumpmame0175
-rw-r--r--android-project/app/src/main/AndroidManifest.xml4
-rw-r--r--hash/bbca_cass.xml2
-rw-r--r--hash/cdi.xml12
-rw-r--r--hash/fmtowns_cd.xml388
-rw-r--r--hash/gba.xml10
-rw-r--r--hash/intv.xml2
-rw-r--r--hash/leapster.xml12
-rw-r--r--hash/megadriv.xml24
-rw-r--r--hash/n64.xml14
-rw-r--r--hash/pc98.xml6
-rw-r--r--hash/pc98_cd.xml102
-rw-r--r--hash/pce_tourvision.xml2
-rw-r--r--hash/pippin.xml48
-rw-r--r--hash/pofo.xml4
-rw-r--r--hash/snes.xml12
-rw-r--r--hash/vsmile_cart.xml22
-rw-r--r--hash/vsmile_cd.xml22
-rw-r--r--makefile4
-rw-r--r--src/devices/bus/electron/exp.cpp2
-rw-r--r--src/devices/bus/electron/exp.h146
-rw-r--r--src/devices/bus/gameboy/mbc.cpp33
-rw-r--r--src/devices/bus/gameboy/mbc.h2
-rw-r--r--src/devices/bus/gba/gba_slot.h2
-rw-r--r--src/devices/bus/gba/rom.cpp73
-rw-r--r--src/devices/bus/gba/rom.h34
-rw-r--r--src/devices/bus/isa/cga.cpp8
-rw-r--r--src/devices/bus/macpds/macpds.h2
-rw-r--r--src/devices/bus/megadrive/rom.cpp2
-rw-r--r--src/devices/bus/megadrive/rom.h2
-rw-r--r--src/devices/bus/nes/bootleg.cpp27
-rw-r--r--src/devices/bus/nes/bootleg.h4
-rw-r--r--src/devices/bus/nes/kaiser.cpp37
-rw-r--r--src/devices/bus/nes/kaiser.h12
-rw-r--r--src/devices/bus/nubus/nubus_image.h2
-rw-r--r--src/devices/bus/pofo/exp.h76
-rw-r--r--src/devices/bus/pofo/hpc101.h6
-rw-r--r--src/devices/bus/pofo/hpc102.h10
-rw-r--r--src/devices/bus/sg1000_exp/fm_unit.cpp3
-rw-r--r--src/devices/bus/sg1000_exp/sk1100.cpp1
-rw-r--r--src/devices/cpu/asap/asapdasm.cpp2
-rw-r--r--src/devices/cpu/avr8/avr8.cpp2
-rw-r--r--src/devices/cpu/drcbex64.cpp1
-rw-r--r--src/devices/cpu/drcbex64.h1
-rw-r--r--src/devices/cpu/m6502/odeco16.lst2
-rw-r--r--src/devices/cpu/mb86235/mb86235d.cpp58
-rw-r--r--src/devices/cpu/nec/v25.h4
-rw-r--r--src/devices/cpu/patinhofeio/patinho_feio.cpp36
-rw-r--r--src/devices/cpu/patinhofeio/patinhofeio_cpu.h38
-rw-r--r--src/devices/cpu/sharc/sharc.cpp8
-rw-r--r--src/devices/cpu/sharc/sharc.h38
-rw-r--r--src/devices/cpu/sharc/sharcdrc.cpp2098
-rw-r--r--src/devices/cpu/sharc/sharcfe.cpp802
-rw-r--r--src/devices/cpu/sparc/mb86901.cpp1175
-rw-r--r--src/devices/cpu/sparc/sparc.h102
-rw-r--r--src/devices/cpu/sparc/sparcdefs.h738
-rw-r--r--src/devices/cpu/tms32010/tms32010.h4
-rw-r--r--src/devices/cpu/tms32025/tms32025.h6
-rw-r--r--src/devices/imagedev/cassette.cpp8
-rw-r--r--src/devices/machine/68230pit.cpp188
-rw-r--r--src/devices/machine/68230pit.h36
-rw-r--r--src/devices/machine/8530scc.cpp16
-rw-r--r--src/devices/machine/eeprom.h2
-rw-r--r--src/devices/machine/ldp1000.cpp28
-rw-r--r--src/devices/machine/ldp1000.h24
-rw-r--r--src/devices/machine/ldv1000.cpp4
-rw-r--r--src/devices/machine/ldv1000.h2
-rw-r--r--src/devices/machine/pci-ide.cpp1
-rw-r--r--src/devices/machine/scnxx562.cpp1079
-rw-r--r--src/devices/machine/scnxx562.h348
-rw-r--r--src/devices/machine/z80scc.h24
-rw-r--r--src/devices/video/zeus2.cpp51
-rw-r--r--src/emu/debug/debugcmd.cpp38
-rw-r--r--src/emu/debug/debugcmd.h6
-rw-r--r--src/emu/debug/debugcon.h8
-rw-r--r--src/emu/debug/debugcpu.cpp62
-rw-r--r--src/emu/debug/debugcpu.h39
-rw-r--r--src/emu/debug/debughlp.cpp2
-rw-r--r--src/emu/debugger.cpp2
-rw-r--r--src/emu/device.cpp12
-rw-r--r--src/emu/emumem.cpp18
-rw-r--r--src/emu/emumem.h6
-rw-r--r--src/emu/emuopts.h2
-rw-r--r--src/emu/hashfile.cpp4
-rw-r--r--src/emu/romload.cpp2
-rw-r--r--src/emu/screen.h76
-rw-r--r--src/frontend/mame/cheat.cpp6
-rw-r--r--src/frontend/mame/cheat.h18
-rw-r--r--src/frontend/mame/ui/auditmenu.cpp1
-rw-r--r--src/frontend/mame/ui/auditmenu.h1
-rw-r--r--src/frontend/mame/ui/barcode.cpp3
-rw-r--r--src/frontend/mame/ui/barcode.h1
-rw-r--r--src/frontend/mame/ui/cheatopt.cpp1
-rw-r--r--src/frontend/mame/ui/cheatopt.h1
-rw-r--r--src/frontend/mame/ui/custmenu.cpp1
-rw-r--r--src/frontend/mame/ui/custmenu.h1
-rw-r--r--src/frontend/mame/ui/custui.cpp1
-rw-r--r--src/frontend/mame/ui/custui.h1
-rw-r--r--src/frontend/mame/ui/datfile.cpp2
-rw-r--r--src/frontend/mame/ui/datmenu.cpp1
-rw-r--r--src/frontend/mame/ui/datmenu.h1
-rw-r--r--src/frontend/mame/ui/devctrl.h1
-rw-r--r--src/frontend/mame/ui/devopt.cpp1
-rw-r--r--src/frontend/mame/ui/devopt.h1
-rw-r--r--src/frontend/mame/ui/dirmenu.cpp1
-rw-r--r--src/frontend/mame/ui/dirmenu.h1
-rw-r--r--src/frontend/mame/ui/filemngr.cpp3
-rw-r--r--src/frontend/mame/ui/filemngr.h1
-rw-r--r--src/frontend/mame/ui/filesel.cpp1
-rw-r--r--src/frontend/mame/ui/filesel.h3
-rw-r--r--src/frontend/mame/ui/floppycntrl.cpp1
-rw-r--r--src/frontend/mame/ui/floppycntrl.h1
-rw-r--r--src/frontend/mame/ui/imgcntrl.cpp1
-rw-r--r--src/frontend/mame/ui/imgcntrl.h1
-rw-r--r--src/frontend/mame/ui/info.cpp1
-rw-r--r--src/frontend/mame/ui/info.h1
-rw-r--r--src/frontend/mame/ui/info_pty.cpp1
-rw-r--r--src/frontend/mame/ui/info_pty.h1
-rw-r--r--src/frontend/mame/ui/inputmap.cpp1
-rw-r--r--src/frontend/mame/ui/inputmap.h1
-rw-r--r--src/frontend/mame/ui/mainmenu.cpp1
-rw-r--r--src/frontend/mame/ui/mainmenu.h1
-rw-r--r--src/frontend/mame/ui/menu.cpp5
-rw-r--r--src/frontend/mame/ui/menu.h1
-rw-r--r--src/frontend/mame/ui/menuitem.h1
-rw-r--r--src/frontend/mame/ui/miscmenu.cpp1
-rw-r--r--src/frontend/mame/ui/miscmenu.h1
-rw-r--r--src/frontend/mame/ui/optsmenu.cpp1
-rw-r--r--src/frontend/mame/ui/optsmenu.h1
-rw-r--r--src/frontend/mame/ui/pluginopt.cpp1
-rw-r--r--src/frontend/mame/ui/pluginopt.h1
-rw-r--r--src/frontend/mame/ui/selector.cpp1
-rw-r--r--src/frontend/mame/ui/selector.h1
-rw-r--r--src/frontend/mame/ui/selgame.cpp9
-rw-r--r--src/frontend/mame/ui/selgame.h1
-rw-r--r--src/frontend/mame/ui/selsoft.cpp1
-rw-r--r--src/frontend/mame/ui/selsoft.h1
-rw-r--r--src/frontend/mame/ui/simpleselgame.cpp1
-rw-r--r--src/frontend/mame/ui/simpleselgame.h1
-rw-r--r--src/frontend/mame/ui/slider.h2
-rw-r--r--src/frontend/mame/ui/sliders.cpp17
-rw-r--r--src/frontend/mame/ui/sliders.h1
-rw-r--r--src/frontend/mame/ui/slotopt.cpp1
-rw-r--r--src/frontend/mame/ui/slotopt.h1
-rw-r--r--src/frontend/mame/ui/sndmenu.cpp1
-rw-r--r--src/frontend/mame/ui/sndmenu.h1
-rw-r--r--src/frontend/mame/ui/submenu.cpp1
-rw-r--r--src/frontend/mame/ui/submenu.h1
-rw-r--r--src/frontend/mame/ui/swlist.cpp1
-rw-r--r--src/frontend/mame/ui/swlist.h1
-rw-r--r--src/frontend/mame/ui/tapectrl.cpp1
-rw-r--r--src/frontend/mame/ui/tapectrl.h1
-rw-r--r--src/frontend/mame/ui/text.cpp9
-rw-r--r--src/frontend/mame/ui/text.h5
-rw-r--r--src/frontend/mame/ui/ui.h55
-rw-r--r--src/frontend/mame/ui/utils.cpp2
-rw-r--r--src/frontend/mame/ui/videoopt.cpp1
-rw-r--r--src/frontend/mame/ui/videoopt.h1
-rw-r--r--src/frontend/mame/ui/viewgfx.cpp2
-rw-r--r--src/lib/netlist/plib/pchrono.h2
-rw-r--r--src/lib/netlist/solver/nld_ms_sm.h4
-rw-r--r--src/lib/netlist/solver/nld_ms_w.h2
-rw-r--r--src/lib/util/timeconv.cpp10
-rw-r--r--src/lib/util/timeconv.h11
-rw-r--r--src/mame/audio/mario.cpp2
-rw-r--r--src/mame/drivers/8080bw.cpp16
-rw-r--r--src/mame/drivers/abc80x.cpp40
-rw-r--r--src/mame/drivers/aerofgt.cpp10
-rw-r--r--src/mame/drivers/alesis_qs.cpp38
-rw-r--r--src/mame/drivers/altair.cpp4
-rw-r--r--src/mame/drivers/aristmk5.cpp3
-rw-r--r--src/mame/drivers/aristmk6.cpp154
-rw-r--r--src/mame/drivers/atarigx2.cpp12
-rw-r--r--src/mame/drivers/atlantis.cpp4
-rw-r--r--src/mame/drivers/bfcobra.cpp2
-rw-r--r--src/mame/drivers/bloodbro.cpp2
-rw-r--r--src/mame/drivers/cclimber.cpp28
-rw-r--r--src/mame/drivers/chihiro.cpp2
-rw-r--r--src/mame/drivers/deco_ld.cpp4
-rwxr-xr-xsrc/mame/drivers/divebomb.cpp222
-rw-r--r--src/mame/drivers/dlair.cpp8
-rw-r--r--src/mame/drivers/esh.cpp31
-rw-r--r--src/mame/drivers/fccpu30.cpp491
-rw-r--r--src/mame/drivers/fidel6502.cpp6
-rw-r--r--src/mame/drivers/funkball.cpp4
-rw-r--r--src/mame/drivers/galaxian.cpp2
-rw-r--r--src/mame/drivers/galivan.cpp10
-rw-r--r--src/mame/drivers/gba.cpp4
-rw-r--r--src/mame/drivers/go2000.cpp2
-rw-r--r--src/mame/drivers/goldnpkr.cpp20
-rw-r--r--src/mame/drivers/goldstar.cpp64
-rw-r--r--src/mame/drivers/halleys.cpp8
-rw-r--r--src/mame/drivers/hh_cop400.cpp2
-rw-r--r--src/mame/drivers/hh_tms1k.cpp10
-rw-r--r--src/mame/drivers/holeland.cpp8
-rw-r--r--src/mame/drivers/homedata.cpp74
-rw-r--r--src/mame/drivers/kickgoal.cpp2
-rw-r--r--src/mame/drivers/leland.cpp1
-rw-r--r--src/mame/drivers/lgp.cpp8
-rw-r--r--src/mame/drivers/m63.cpp2
-rw-r--r--src/mame/drivers/magicfly.cpp4
-rw-r--r--src/mame/drivers/megasys1.cpp136
-rw-r--r--src/mame/drivers/metlfrzr.cpp27
-rw-r--r--src/mame/drivers/mgames.cpp2
-rw-r--r--src/mame/drivers/naomi.cpp4
-rw-r--r--src/mame/drivers/neogeo.cpp4
-rw-r--r--src/mame/drivers/pasopia7.cpp4
-rw-r--r--src/mame/drivers/patinho_feio.cpp32
-rw-r--r--src/mame/drivers/pc9801.cpp2
-rw-r--r--src/mame/drivers/rainbow.cpp2
-rw-r--r--src/mame/drivers/sg1000.cpp4
-rw-r--r--src/mame/drivers/sun2.cpp256
-rw-r--r--src/mame/drivers/sun3.cpp266
-rw-r--r--src/mame/drivers/sun4.cpp164
-rw-r--r--src/mame/drivers/system16.cpp18
-rwxr-xr-xsrc/mame/drivers/tek440x.cpp86
-rw-r--r--src/mame/drivers/toaplan1.cpp2
-rw-r--r--src/mame/drivers/toaplan2.cpp24
-rw-r--r--src/mame/drivers/toratora.cpp24
-rw-r--r--src/mame/drivers/vegas.cpp8
-rw-r--r--src/mame/drivers/vsmilepro.cpp10
-rw-r--r--src/mame/drivers/x1.cpp2
-rw-r--r--src/mame/includes/aerofgt.h2
-rw-r--r--src/mame/includes/atarigx2.h8
-rw-r--r--src/mame/includes/divebomb.h140
-rw-r--r--src/mame/includes/gameplan.h2
-rw-r--r--src/mame/includes/megasys1.h2
-rw-r--r--src/mame/includes/namconb1.h2
-rw-r--r--src/mame/includes/nmk16.h2
-rw-r--r--src/mame/includes/plygonet.h2
-rw-r--r--src/mame/includes/sg1000.h2
-rw-r--r--src/mame/includes/tsamurai.h2
-rw-r--r--src/mame/layout/patinho.lay260
-rw-r--r--src/mame/machine/atarixga.h62
-rw-r--r--src/mame/machine/dccons.cpp12
-rw-r--r--src/mame/machine/dec_lk201.cpp36
-rw-r--r--src/mame/machine/dec_lk201.h8
-rw-r--r--src/mame/machine/fd1094.cpp2
-rw-r--r--src/mame/machine/kaneko_toybox.cpp2
-rw-r--r--src/mame/machine/m2comm.cpp6
-rw-r--r--src/mame/machine/namcoic.cpp4
-rw-r--r--src/mame/machine/pcecommn.h2
-rw-r--r--src/mame/machine/seibucop/seibucop.cpp128
-rw-r--r--src/mame/machine/seibucop/seibucop.h24
-rw-r--r--src/mame/machine/sms.cpp4
-rw-r--r--src/mame/machine/xbox.cpp22
-rw-r--r--src/mame/mame.lst6
-rw-r--r--src/mame/video/chihiro.cpp2
-rw-r--r--src/mame/video/divebomb.cpp172
-rw-r--r--src/mame/video/exerion.cpp4
-rw-r--r--src/mame/video/gotya.cpp6
-rw-r--r--src/mame/video/homedata.cpp10
-rw-r--r--src/mame/video/megasys1.cpp2
-rw-r--r--src/mame/video/model3.cpp82
-rw-r--r--src/mame/video/namconb1.cpp4
-rw-r--r--src/mame/video/namcos2.cpp2
-rw-r--r--src/mame/video/powervr2.cpp2
-rw-r--r--src/mame/video/seibu_crtc.cpp2
-rw-r--r--src/mame/video/vtvideo.cpp6
-rw-r--r--src/osd/modules/debugger/debugimgui.cpp10
-rw-r--r--src/osd/modules/diagnostics/diagnostics_win32.cpp2
-rw-r--r--src/osd/modules/file/posixdir.cpp10
-rw-r--r--src/osd/modules/file/windir.cpp2
-rw-r--r--src/osd/modules/font/font_dwrite.cpp2
-rw-r--r--src/osd/modules/input/input_sdl.cpp2
-rw-r--r--src/osd/modules/input/input_windows.cpp4
-rw-r--r--src/osd/modules/input/input_xinput.cpp2
-rw-r--r--src/osd/modules/lib/osdlib.h1
-rw-r--r--src/osd/modules/lib/osdlib_macosx.cpp5
-rw-r--r--src/osd/modules/lib/osdlib_unix.cpp5
-rw-r--r--src/osd/modules/lib/osdlib_win32.cpp5
-rw-r--r--src/osd/modules/netdev/pcap.cpp2
-rw-r--r--src/osd/modules/output/output_module.h2
-rw-r--r--src/osd/modules/render/bgfx/chain.cpp50
-rw-r--r--src/osd/modules/render/bgfx/chain.h6
-rw-r--r--src/osd/modules/render/bgfx/chainmanager.cpp46
-rw-r--r--src/osd/modules/render/bgfx/targetmanager.cpp4
-rw-r--r--src/osd/modules/render/d3d/d3dhlsl.cpp2
-rw-r--r--src/osd/modules/render/drawd3d.cpp22
-rw-r--r--src/osd/modules/render/winglcontext.h2
-rwxr-xr-xsrc/osd/modules/sound/xaudio2_sound.cpp4
-rw-r--r--src/osd/osdcore.h20
-rw-r--r--src/osd/sdl/window.h4
-rw-r--r--src/osd/windows/window.cpp2
283 files changed, 6074 insertions, 6164 deletions
diff --git a/android-project/app/src/main/AndroidManifest.xml b/android-project/app/src/main/AndroidManifest.xml
index b1984995b6b..2397b5e01e8 100644
--- a/android-project/app/src/main/AndroidManifest.xml
+++ b/android-project/app/src/main/AndroidManifest.xml
@@ -4,8 +4,8 @@
-->
<manifest xmlns:android="http://schemas.android.com/apk/res/android"
package="org.mamedev.mame"
- android:versionCode="174"
- android:versionName="0.174"
+ android:versionCode="175"
+ android:versionName="0.175"
android:installLocation="auto">
<!-- Android 4.0 -->
diff --git a/hash/bbca_cass.xml b/hash/bbca_cass.xml
index a463cf8c40d..a8e593716e3 100644
--- a/hash/bbca_cass.xml
+++ b/hash/bbca_cass.xml
@@ -61,7 +61,7 @@
</dataarea>
</part>
</software>
-
+
<software name="beebtrek">
<description>Beebtrek</description>
<year>1982</year>
diff --git a/hash/cdi.xml b/hash/cdi.xml
index 18243f3c8b7..d796e9e6314 100644
--- a/hash/cdi.xml
+++ b/hash/cdi.xml
@@ -2,9 +2,9 @@
<!DOCTYPE softwarelist SYSTEM "softwarelist.dtd">
<softwarelist name="cdi" description="CD-i CD-ROMs">
-<!--
- These are converted from old TOSEC set (I think v2009-04-05), but a double check is being performed, at
- least for discs that can still be found for this set
+<!--
+ These are converted from old TOSEC set (I think v2009-04-05), but a double check is being performed, at
+ least for discs that can still be found for this set
-->
<software name="3degree">
@@ -10591,7 +10591,7 @@
<!--
- These are converted from rips released on the web
+ These are converted from rips released on the web
-->
<software name="frogfeas">
@@ -10647,7 +10647,7 @@
Origin: Unknown
<rom name="voyeur ii (v1.04)(11-06-96)(testing-beta)(access code 3333) (disc1).bin" size="601528704" crc="0a337e76" sha1="10c15630f7cbcfc7751e7ae1948947cad48850b2" offset="0" />
<rom name="voyeur ii (v1.04)(11-06-96)(testing-beta)(access code 3333) (disc1).cue" size="133" crc="7d9bbe3f" sha1="fc746593b61ac9d3d24296a0c1ab7101b25db49d" offset="0" />
-
+
<rom name="voyeur ii (v1.04)(11-06-96)(testing-beta)(access code 3333) (disc2).bin" size="595354704" crc="8024edf4" sha1="ba86e8850304afb918e2a4c7411e8648b3f90a4a" offset="0" />
<rom name="voyeur ii (v1.04)(11-06-96)(testing-beta)(access code 3333) (disc2).cue" size="133" crc="7cc698ee" sha1="3622939d9c37f43749907cc964cc4738e58ad3b7" offset="0" />
-->
@@ -10670,7 +10670,7 @@
<!--
- These are non-tosec sourced, and could be bad
+ These are non-tosec sourced, and could be bad
-->
diff --git a/hash/fmtowns_cd.xml b/hash/fmtowns_cd.xml
index b63da2e8367..e637afc8f29 100644
--- a/hash/fmtowns_cd.xml
+++ b/hash/fmtowns_cd.xml
@@ -6,7 +6,7 @@
Known undumped discs (possibly more exist, and some CDs marked as FMT could actually be for Marty and vice versa), based on Blitzkrieg's researches
-
+
FM-Towns Marty CDs
==================
? 0 Hoshi Uranai Jutsu Dai Rei Gen Feb-90 Victor (CDx1)
@@ -100,186 +100,186 @@
High School War Sep-94 I.S.C. (CDx1)
Hiouden 2 Mar-94 Telenet Japan (CDx1)
If Jun-93 Active (CDx1)
- If 2 Nov-93 Active (CDx1)
- If 3 Apr-95 Active (CDx1)
+ If 2 Nov-93 Active (CDx1)
+ If 3 Apr-95 Active (CDx1)
Igo Doujou Shodan Kaigan! Kyuu Karadane no Chousen May-91 Fujitsu (CDx1)
Igo Doujou Yaburi Menkyokaiden!! Mezase 7-Kyuu Oct-90 Fujitsu (CDx1)
- Inindou: Datou Nobunaga Feb-92 Koei (CDx1)
- Introduction to Go Dojo Jun-91 GAM (CDx1)
- Intruder: Sakura Yashiki no Tansaku XXX-89 Alice Soft (CDx1)
- Irisu-tei Sayokyoku Nov-92 Agumix (CDx1)
- Ishin no Arashi Mar-90 Koei (CDx1)
- J-League Professional Soccer 1994 Sep-94 Victor (CDx1)
- Jinmon Yuugi Aug-95 Fairytale - Red Zone (CDx1)
- Joker Towns Jul-92 Birdy Soft (CDx1)
- Joshikou Seifuku Monogatari Apr-95 KSS (CDx1)
- JYB Apr-93 Cocktail Soft (CDx1)
- Kamigami No Daichi: Kojiki Gaiden Oct-93 Koei (CDx1)
+ Inindou: Datou Nobunaga Feb-92 Koei (CDx1)
+ Introduction to Go Dojo Jun-91 GAM (CDx1)
+ Intruder: Sakura Yashiki no Tansaku XXX-89 Alice Soft (CDx1)
+ Irisu-tei Sayokyoku Nov-92 Agumix (CDx1)
+ Ishin no Arashi Mar-90 Koei (CDx1)
+ J-League Professional Soccer 1994 Sep-94 Victor (CDx1)
+ Jinmon Yuugi Aug-95 Fairytale - Red Zone (CDx1)
+ Joker Towns Jul-92 Birdy Soft (CDx1)
+ Joshikou Seifuku Monogatari Apr-95 KSS (CDx1)
+ JYB Apr-93 Cocktail Soft (CDx1)
+ Kamigami No Daichi: Kojiki Gaiden Oct-93 Koei (CDx1)
Kero Kero Keroppi to Origami no Tabibito Jul-95 Fujitsu (CDx1)
- Kikou Shidan 2 Mar-93 Artdink (CDx1)
- Kouryuuki Oct-93 Koei (CDx1)
- Kousoku Choujin Aug-96 Foster Japan (CDx1)
- KU2++ Nov-93 Panther Software (CDx1)
- Kusuriyubi no Kyoukasho Apr-96 Active (CDx1)
- Kyouko no Ijiwaru! Oct-94 Ponytail Soft (CDx1)
- L'Empereur Jan-91 Koei (CDx1)
- Leading Company Apr-92 Koei (CDx1)
- Lemon Cocktail Collection Mar-93 Cocktail Soft (CDx1)
- Lipstick Adventure 3 May-93 Fairytale (CDx1)
- Little Big Adventure Dec-95 Electronic Arts (CDx1)
- Lord of the Rings 2: The Two Towers Apr-93 Star Craft (CDx1)
+ Kikou Shidan 2 Mar-93 Artdink (CDx1)
+ Kouryuuki Oct-93 Koei (CDx1)
+ Kousoku Choujin Aug-96 Foster Japan (CDx1)
+ KU2++ Nov-93 Panther Software (CDx1)
+ Kusuriyubi no Kyoukasho Apr-96 Active (CDx1)
+ Kyouko no Ijiwaru! Oct-94 Ponytail Soft (CDx1)
+ L'Empereur Jan-91 Koei (CDx1)
+ Leading Company Apr-92 Koei (CDx1)
+ Lemon Cocktail Collection Mar-93 Cocktail Soft (CDx1)
+ Lipstick Adventure 3 May-93 Fairytale (CDx1)
+ Little Big Adventure Dec-95 Electronic Arts (CDx1)
+ Lord of the Rings 2: The Two Towers Apr-93 Star Craft (CDx1)
Lord of the Rings: The Fellowship of the Ring Mar-92 Star Craft (CDx1)
- Lua Jun-93 Inter Heart (CDx1)
- Mahjong Bishoujo Den Rippuru Feb-95 Foresight (CDx1)
- Mahjong Fantasia 2 Sep-93 Active (CDx1)
- Mahjong Fantasia 3 Nov-95 Active (CDx1)
- Mahjong Goku Apr-89 ASCII (CDx1)
- Mahjong Musashi XXX-89 Computer Cosmos (CDx1)
- Manami no Doko made Iku no May-95 Wendy Magazine (CDx1)
+ Lua Jun-93 Inter Heart (CDx1)
+ Mahjong Bishoujo Den Rippuru Feb-95 Foresight (CDx1)
+ Mahjong Fantasia 2 Sep-93 Active (CDx1)
+ Mahjong Fantasia 3 Nov-95 Active (CDx1)
+ Mahjong Goku Apr-89 ASCII (CDx1)
+ Mahjong Musashi XXX-89 Computer Cosmos (CDx1)
+ Manami no Doko made Iku no May-95 Wendy Magazine (CDx1)
Manami no Doko made Iku no 2: Return of the Kuro Pack May-95 Wendy Magazine (CDx1)
- Manami: Ai to Koukan no Hibi XXX-95 Fairytale - Red Zone (CDx1)
- Marionette Mind Mar-94 Studio Milk (CDx1)
- Mega Lo Mania Mar-93 Imagineer (CDx1)
- Meisou Toshi Dec-95 Tiare (CDx1)
- Might & Magic: World of Xeen Oct-92 Star Craft (CDx1)
- Mirage 2 Dec-94 Discovery (CDx1)
- Misato-chan no Yume Nikki Apr-97 Active (CDx1)
- Moeru Asoko no Pai Pai Yuugi Dec-93 Illusion (CDx1)
- Mokkori Man RPG Jun-94 Illusion (CDx1)
- Monoshiri ji Yuugaku Hyakunin Ichishuhen Oct-94 Shinko Human Request (CDx1)
- Moonlight Energy Dec-92 Inter Heart (CDx1)
- Murder Club DX May-92 Riverhill Soft (CDx1)
- Naru Mahjong Apr-95 Libido (CDx1)
- Nemurenu Yoru no Chisana Ohanashi Dec-93 Amuse (CDx1)
- Never Land Mar-96 Tips (CDx1)
- NHK Hitori de Dekiru Mon! Mar-95 Rei (CDx1)
- Niko 2 Nov-91 Telenet Japan (CDx1)
- Nippon Mukashibanashi Nov-90 Gyosei (CDx1)
- Nippon Mukashibanashi 2 Jul-91 Gyosei (CDx1)
- Nippon Mukashibanashi 3 Dec-93 Gyosei (CDx1)
- Nippon Mukashibanashi 4 Dec-93 Gyosei (CDx1)
- Nippon Mukashibanashi 5 Mar-94 Gyosei (CDx1)
- Nobunaga no Yabou: Bushou Fuunroku Jul-91 Koei (CDx1)
- Nobunaga no Yabou: Sengoku Gunyuu Den Dec-89 Koei (CDx1)
- Nostalgia 1907 May-92 Sur de Wave (CDx1)
- Obachan no Chiebukuro Nov-91 Gyosei (CDx1)
- Oku man Choja 2 Jul-91 Computer Cosmos (CDx1)
- Only You: Juliet of the Century Jan-96 Alice Soft (CDx1)
- Orient Express Dec-94 Gyosei (CDx1)
- Palamedes XXX-91 Ving (CDx1)
- Para Para Paradise Dec-95 Family Soft (CDx2)
- Phobos Aug-95 Himeya Soft, Inc (CDx1)
- Pocky & Ponyon Jun-94 Ponytail Soft (CDx1)
- Populous 2 Feb-93 Imagineer (CDx1)
- Presence Dec-92 Sur de Wave (CDx1)
- Private Slave Aug-93 Raccoon (CDx1)
- ProYakyuu Family Stadium '90 Sep-90 Game Arts (CDx1)
- Reijou Monogatari Apr-95 Inter Heart (CDx1)
- Rinkan Gakkou Feb-96 Foster Japan (CDx1)
- Royal Blood May-92 Koei (CDx1)
- Ryuutatakaden Jun-94 Fujitsu (CDx1)
- Sakura no Mori XXX-95 Active (CDx1)
- Sangokushi 2 Jun-90 Koei (CDx1)
- Sangokushi 3 Jun-92 Koei (CDx1)
- Sargon 5 Nov-92 GAM (CDx1)
- Sayonara no Mukougawa Aug-97 Foster Japan (CDx1)
- Seikatsu Simulation Watashi no Machi May-95 Cocktail Soft (CDx1)
- Sekai no o Hanashi May-92 Gyosei (CDx1)
- Sekigahara Apr-92 Artdink (CDx1)
- Sensual Angels Jan-94 JHV (CDx1)
- Sexy P/K Part 2: World Cup Hen May-95 Birdy Soft (CDx1)
- Sexy P/K Part Nihon Apr-95 Birdy Soft (CDx1)
- Shanghai Dec-90 ASCII (CDx1)
- Shanghai: Great Wall Sep-95 Electronic Arts (CDx1)
- Shooting Towns Mar-90 Amorphous (CDx1)
- SL o mitai! Uruwashi no Joki Kikan-sha Jul-95 Gyosei (CDx1)
- Soft de Hard na Monogatari Apr-89 System Sacom (CDx1)
- Soft de Hard na Monogatari 2 Jul-89 System Sacom (CDx1)
- Sokoban Perfect Jul-90 Thinking Rabbit (CDx1)
- Space Odyssey Galaxy Mar-91 Fujitsu (CDx1)
- Space Odyssey Galaxy 2 Apr-92 Fujitsu (CDx1)
- Steepia Jun-93 Fujitsu (CDx1)
- Steepia Lite Mar-93 Fujitsu (CDx1)
- Suikoden: Tenmei no Chikai Feb-90 Koei (CDx1)
- Super Real Mahjong P2 & P3 + Mar-93 Ving (CDx1)
- Suzaku Oct-92 Wolf Team (CDx1)
- Tactical Tank Corps DX Feb-95 GAM (CDx1)
- Tamashi no Mon: Dante Shinkyoku Yori Jun-93 Koei (CDx1)
- Tania Nov-96 Tips (CDx1)
- Teito Taisen Dec-89 Supersonic (CDx1)
- Teitoku no Ketsudan Apr-90 Koei (CDx1)
- Tenshi-Tachi no Gogo Collection 2 Nov-95 Jast (CDx1)
- Tenshin Ranma May-92 Elf (CDx1)
- Teo: Another Earth Sep-95 Fujitsu (CDx1)
- Teo: Another Earth 2 Jul-96 Fujitsu (CDx1)
- The Playroom Feb-95 Fujitsu (CDx1)
- The Queen of Duellist Alpha Mar-94 Agumix (CDx1)
- The Queen of Duellist Alpha Light Apr-94 Agumix (CDx1)
- Theme Park Sep-95 Electronic Arts (CDx1)
- Time Stripper Mako-chan Jan-96 Foster Japan (CDx1)
- Tokyo Sexy Ave. Jul-94 HOP (CDx1)
- Tokyo-to Dai 24-Ku Dec-92 Artdink (CDx1)
- Tom Snyder's Puppy Love Jul-89 Fujitsu (CDx1)
- Tom Snyder's Puppy Love 2 Mar-93 Fujitsu (CDx1)
- Toushin Toshi Apr-95 Alice Soft (CDx1)
- Trigger Jun-94 ZyX (CDx1)
- Trigger 2 Sep-95 ZyX (CDx1)
- Vampire High School Jun-93 Inter Heart (CDx1)
- Vanishing Point XXX-95 Tiare (CDx1)
- Viper GTS Nov-95 Sogna (CDx1)
- Viper V12 Dec-95 Sogna (CDx1)
- Viper V8 Turbo RS Jun-95 Sogna (CDx1)
- Winning Post May-93 Koei (CDx1)
- Yayo 1-2-3 Jul-93 Hado (CDx1)
- Yayo 4 Feb-93 Hado (CDx1)
- Yes! HG Dec-95 Himeya Soft, Inc (CDx1)
- Youjuu Senki 2 Reimei no Senshi Feb-94 D.O. (CDx1)
- Youjuu Senki: Sajin no Mokushiroku Feb-94 D.O. (CDx1)
- Yume Utsutsu: Dreamy May-92 Megami (CDx1)
- Zan 3 Apr-94 Telenet Japan (CDx1)
- Zenith Feb-95 Himeya Soft, Inc 1
+ Manami: Ai to Koukan no Hibi XXX-95 Fairytale - Red Zone (CDx1)
+ Marionette Mind Mar-94 Studio Milk (CDx1)
+ Mega Lo Mania Mar-93 Imagineer (CDx1)
+ Meisou Toshi Dec-95 Tiare (CDx1)
+ Might & Magic: World of Xeen Oct-92 Star Craft (CDx1)
+ Mirage 2 Dec-94 Discovery (CDx1)
+ Misato-chan no Yume Nikki Apr-97 Active (CDx1)
+ Moeru Asoko no Pai Pai Yuugi Dec-93 Illusion (CDx1)
+ Mokkori Man RPG Jun-94 Illusion (CDx1)
+ Monoshiri ji Yuugaku Hyakunin Ichishuhen Oct-94 Shinko Human Request (CDx1)
+ Moonlight Energy Dec-92 Inter Heart (CDx1)
+ Murder Club DX May-92 Riverhill Soft (CDx1)
+ Naru Mahjong Apr-95 Libido (CDx1)
+ Nemurenu Yoru no Chisana Ohanashi Dec-93 Amuse (CDx1)
+ Never Land Mar-96 Tips (CDx1)
+ NHK Hitori de Dekiru Mon! Mar-95 Rei (CDx1)
+ Niko 2 Nov-91 Telenet Japan (CDx1)
+ Nippon Mukashibanashi Nov-90 Gyosei (CDx1)
+ Nippon Mukashibanashi 2 Jul-91 Gyosei (CDx1)
+ Nippon Mukashibanashi 3 Dec-93 Gyosei (CDx1)
+ Nippon Mukashibanashi 4 Dec-93 Gyosei (CDx1)
+ Nippon Mukashibanashi 5 Mar-94 Gyosei (CDx1)
+ Nobunaga no Yabou: Bushou Fuunroku Jul-91 Koei (CDx1)
+ Nobunaga no Yabou: Sengoku Gunyuu Den Dec-89 Koei (CDx1)
+ Nostalgia 1907 May-92 Sur de Wave (CDx1)
+ Obachan no Chiebukuro Nov-91 Gyosei (CDx1)
+ Oku man Choja 2 Jul-91 Computer Cosmos (CDx1)
+ Only You: Juliet of the Century Jan-96 Alice Soft (CDx1)
+ Orient Express Dec-94 Gyosei (CDx1)
+ Palamedes XXX-91 Ving (CDx1)
+ Para Para Paradise Dec-95 Family Soft (CDx2)
+ Phobos Aug-95 Himeya Soft, Inc (CDx1)
+ Pocky & Ponyon Jun-94 Ponytail Soft (CDx1)
+ Populous 2 Feb-93 Imagineer (CDx1)
+ Presence Dec-92 Sur de Wave (CDx1)
+ Private Slave Aug-93 Raccoon (CDx1)
+ ProYakyuu Family Stadium '90 Sep-90 Game Arts (CDx1)
+ Reijou Monogatari Apr-95 Inter Heart (CDx1)
+ Rinkan Gakkou Feb-96 Foster Japan (CDx1)
+ Royal Blood May-92 Koei (CDx1)
+ Ryuutatakaden Jun-94 Fujitsu (CDx1)
+ Sakura no Mori XXX-95 Active (CDx1)
+ Sangokushi 2 Jun-90 Koei (CDx1)
+ Sangokushi 3 Jun-92 Koei (CDx1)
+ Sargon 5 Nov-92 GAM (CDx1)
+ Sayonara no Mukougawa Aug-97 Foster Japan (CDx1)
+ Seikatsu Simulation Watashi no Machi May-95 Cocktail Soft (CDx1)
+ Sekai no o Hanashi May-92 Gyosei (CDx1)
+ Sekigahara Apr-92 Artdink (CDx1)
+ Sensual Angels Jan-94 JHV (CDx1)
+ Sexy P/K Part 2: World Cup Hen May-95 Birdy Soft (CDx1)
+ Sexy P/K Part Nihon Apr-95 Birdy Soft (CDx1)
+ Shanghai Dec-90 ASCII (CDx1)
+ Shanghai: Great Wall Sep-95 Electronic Arts (CDx1)
+ Shooting Towns Mar-90 Amorphous (CDx1)
+ SL o mitai! Uruwashi no Joki Kikan-sha Jul-95 Gyosei (CDx1)
+ Soft de Hard na Monogatari Apr-89 System Sacom (CDx1)
+ Soft de Hard na Monogatari 2 Jul-89 System Sacom (CDx1)
+ Sokoban Perfect Jul-90 Thinking Rabbit (CDx1)
+ Space Odyssey Galaxy Mar-91 Fujitsu (CDx1)
+ Space Odyssey Galaxy 2 Apr-92 Fujitsu (CDx1)
+ Steepia Jun-93 Fujitsu (CDx1)
+ Steepia Lite Mar-93 Fujitsu (CDx1)
+ Suikoden: Tenmei no Chikai Feb-90 Koei (CDx1)
+ Super Real Mahjong P2 & P3 + Mar-93 Ving (CDx1)
+ Suzaku Oct-92 Wolf Team (CDx1)
+ Tactical Tank Corps DX Feb-95 GAM (CDx1)
+ Tamashi no Mon: Dante Shinkyoku Yori Jun-93 Koei (CDx1)
+ Tania Nov-96 Tips (CDx1)
+ Teito Taisen Dec-89 Supersonic (CDx1)
+ Teitoku no Ketsudan Apr-90 Koei (CDx1)
+ Tenshi-Tachi no Gogo Collection 2 Nov-95 Jast (CDx1)
+ Tenshin Ranma May-92 Elf (CDx1)
+ Teo: Another Earth Sep-95 Fujitsu (CDx1)
+ Teo: Another Earth 2 Jul-96 Fujitsu (CDx1)
+ The Playroom Feb-95 Fujitsu (CDx1)
+ The Queen of Duellist Alpha Mar-94 Agumix (CDx1)
+ The Queen of Duellist Alpha Light Apr-94 Agumix (CDx1)
+ Theme Park Sep-95 Electronic Arts (CDx1)
+ Time Stripper Mako-chan Jan-96 Foster Japan (CDx1)
+ Tokyo Sexy Ave. Jul-94 HOP (CDx1)
+ Tokyo-to Dai 24-Ku Dec-92 Artdink (CDx1)
+ Tom Snyder's Puppy Love Jul-89 Fujitsu (CDx1)
+ Tom Snyder's Puppy Love 2 Mar-93 Fujitsu (CDx1)
+ Toushin Toshi Apr-95 Alice Soft (CDx1)
+ Trigger Jun-94 ZyX (CDx1)
+ Trigger 2 Sep-95 ZyX (CDx1)
+ Vampire High School Jun-93 Inter Heart (CDx1)
+ Vanishing Point XXX-95 Tiare (CDx1)
+ Viper GTS Nov-95 Sogna (CDx1)
+ Viper V12 Dec-95 Sogna (CDx1)
+ Viper V8 Turbo RS Jun-95 Sogna (CDx1)
+ Winning Post May-93 Koei (CDx1)
+ Yayo 1-2-3 Jul-93 Hado (CDx1)
+ Yayo 4 Feb-93 Hado (CDx1)
+ Yes! HG Dec-95 Himeya Soft, Inc (CDx1)
+ Youjuu Senki 2 Reimei no Senshi Feb-94 D.O. (CDx1)
+ Youjuu Senki: Sajin no Mokushiroku Feb-94 D.O. (CDx1)
+ Yume Utsutsu: Dreamy May-92 Megami (CDx1)
+ Zan 3 Apr-94 Telenet Japan (CDx1)
+ Zenith Feb-95 Himeya Soft, Inc 1
FM-Towns Marty CDs
==================
- 4D Boxing Jul-93 Electronic Arts (CDx1)
- 4D Driving Jul-93 Electronic Arts (CDx1)
- Psychic Detective Vol.1: Invitation Nov-93 Data West (CDx1)
- Psychic Detective Vol.2: Memories Apr-94 Data West (CDx1)
- Psychic Detective Vol.3: Aya Jul-94 Data West (CDx1)
- Psychic Detective Vol.4: Orgel Dec-94 Data West (CDx1)
- Psychic Detective Vol.5: Nightmare Apr-95 Data West (CDx1)
- Bible Master 2 Jan-95 Glodia (CDx1)
- Custom Mate Dec-94 Cocktail Soft (CDx1)
- Demon City Mar-94 Cocktail Soft (CDx1)
- Dengeki Nurse 2: More Sexy Dec-94 Cocktail Soft (CDx1)
- Doki Doki Vacation Mar-95 Cocktail Soft (CDx1)
- DOR Best Collection Chapter 1 Apr-93 D.O. (CDx2)
- DOR Best Collection Chapter 2 May-93 D.O. (CDx2)
- Dracula Hakushaku Mar-93 Fairytale (CDx1)
- Emit Vol.1 Mar-94 Koei (CDx1)
- Emit Vol.2 Jul-94 Koei (CDx1)
- Emit Vol.3 Sep-94 Koei (CDx1)
- Fujitsu Habitat 2 May-94 Fujitsu (CDx1)
- Gokko Vol.1: Doctor Nov-94 Mink (CDx1)
- Gokko Vol.2: School Gals Dec-94 Mink (CDx1)
- Gokko Vol.3: Etcetera Dec-94 Mink (CDx1)
- Gokuraku Mandala Feb-94 Fairytale (CDx1)
- Joshikousei Shoujo Densetsu Apr-94 Byakuya Shobou (CDx1)
- Ms. Detective XXX-93 Data West (CDx1)
- Nijiiro Denshoku Musume Aug-94 I.S.C. (CDx1)
- Noushuku Angel 120% Apr-95 Cocktail Soft (CDx1)
- Record of Lodoss War 2 Jun-94 MAC (CDx1)
- Sangokushi 4 Jun-94 Koei (CDx1)
- Shamhat: The Holy Circlet Apr-93 Data West (CDx1)
- Shinjuku Labyrinth ==== Tokuma Shoten (CDx1)
- Teitoku no Ketsudan 2 Jun-94 Koei (CDx1)
- Tokyo Labyrinth Dec-94 Tokuma Shoten (CDx1)
- True Heart Feb-95 Cocktail Soft (CDx1)
- Two Shot Diary Oct-94 Mink 1
- URM Dec-94 JHV (CDx1)
- Virtuacall 2 Dec-95 Fairytale (CDx1)
- Wonpara Wars Feb-95 Mink (CDx1)
- Wonpara Wars 2 Apr-95 Mink (CDx1)
+ 4D Boxing Jul-93 Electronic Arts (CDx1)
+ 4D Driving Jul-93 Electronic Arts (CDx1)
+ Psychic Detective Vol.1: Invitation Nov-93 Data West (CDx1)
+ Psychic Detective Vol.2: Memories Apr-94 Data West (CDx1)
+ Psychic Detective Vol.3: Aya Jul-94 Data West (CDx1)
+ Psychic Detective Vol.4: Orgel Dec-94 Data West (CDx1)
+ Psychic Detective Vol.5: Nightmare Apr-95 Data West (CDx1)
+ Bible Master 2 Jan-95 Glodia (CDx1)
+ Custom Mate Dec-94 Cocktail Soft (CDx1)
+ Demon City Mar-94 Cocktail Soft (CDx1)
+ Dengeki Nurse 2: More Sexy Dec-94 Cocktail Soft (CDx1)
+ Doki Doki Vacation Mar-95 Cocktail Soft (CDx1)
+ DOR Best Collection Chapter 1 Apr-93 D.O. (CDx2)
+ DOR Best Collection Chapter 2 May-93 D.O. (CDx2)
+ Dracula Hakushaku Mar-93 Fairytale (CDx1)
+ Emit Vol.1 Mar-94 Koei (CDx1)
+ Emit Vol.2 Jul-94 Koei (CDx1)
+ Emit Vol.3 Sep-94 Koei (CDx1)
+ Fujitsu Habitat 2 May-94 Fujitsu (CDx1)
+ Gokko Vol.1: Doctor Nov-94 Mink (CDx1)
+ Gokko Vol.2: School Gals Dec-94 Mink (CDx1)
+ Gokko Vol.3: Etcetera Dec-94 Mink (CDx1)
+ Gokuraku Mandala Feb-94 Fairytale (CDx1)
+ Joshikousei Shoujo Densetsu Apr-94 Byakuya Shobou (CDx1)
+ Ms. Detective XXX-93 Data West (CDx1)
+ Nijiiro Denshoku Musume Aug-94 I.S.C. (CDx1)
+ Noushuku Angel 120% Apr-95 Cocktail Soft (CDx1)
+ Record of Lodoss War 2 Jun-94 MAC (CDx1)
+ Sangokushi 4 Jun-94 Koei (CDx1)
+ Shamhat: The Holy Circlet Apr-93 Data West (CDx1)
+ Shinjuku Labyrinth ==== Tokuma Shoten (CDx1)
+ Teitoku no Ketsudan 2 Jun-94 Koei (CDx1)
+ Tokyo Labyrinth Dec-94 Tokuma Shoten (CDx1)
+ True Heart Feb-95 Cocktail Soft (CDx1)
+ Two Shot Diary Oct-94 Mink 1
+ URM Dec-94 JHV (CDx1)
+ Virtuacall 2 Dec-95 Fairytale (CDx1)
+ Wonpara Wars Feb-95 Mink (CDx1)
+ Wonpara Wars 2 Apr-95 Mink (CDx1)
-->
@@ -326,7 +326,7 @@ User/save disks that can be created from the game itself are not included.
</diskarea>
</part>
</software>
-
+
<software name="fbas2110">
<!--
Origin: Neo Kobe Collection
@@ -344,7 +344,7 @@ User/save disks that can be created from the game itself are not included.
</diskarea>
</part>
</software>
-
+
<software name="gnutowns">
<!--
Origin: Neo Kobe Collection
@@ -362,13 +362,13 @@ User/save disks that can be created from the game itself are not included.
</diskarea>
</part>
</software>
-
+
<software name="linuxje3">
<!--
Origin: Neo Kobe Collection
<rom name="[OS] Linux + JE3.mdf" size="760707360" crc="2c93db2b" sha1="992b0e991a6bde293edf059e529ee2321ab6469b"/>
<rom name="[OS] Linux + JE3.mds" size="486" crc="9f8751b3" sha1="bea414de9da5a391b5256855d1ec4beee60e677d"/>
-
+
*after conversion with IsoBuster+EAC *
<rom name="[os] linux + je3.bin" size="760707360" crc="2c93db2b" sha1="992b0e991a6bde293edf059e529ee2321ab6469b"/>
<rom name="[os] linux + je3.cue" size="77" crc="6f8db5a8" sha1="987a7967fd60cba6f61cc3a4246881b2c4119deb"/>
@@ -382,7 +382,7 @@ User/save disks that can be created from the game itself are not included.
</diskarea>
</part>
</software>
-
+
<software name="linuxje4">
<!--
Origin: Neo Kobe Collection
@@ -390,12 +390,12 @@ User/save disks that can be created from the game itself are not included.
<rom name="[OS] Linux + JE4 1995-12 (Disc 1).cue" size="97" crc="7a4e430d" sha1="07ae5837929038f79dfe589f03d264fb88c1f631"/>
<rom name="[OS] Linux + JE4 1995-12 (Disc 1).img" size="577110240" crc="cb8e970c" sha1="8598c7f6c5493c27a2a9b9dcacce04eafcea266d"/>
<rom name="[OS] Linux + JE4 1995-12 (Disc 1).sub" size="23555520" crc="08f228a2" sha1="3c3805ed5ad7567b2c812c30534d3f5906b7c017"/>
-
+
<rom name="[OS] Linux + JE4 1995-12 (Disc 2).ccd" size="772" crc="d0c4f348" sha1="ecf9a17f635112709cff2243b3311508b4b376ed"/>
<rom name="[OS] Linux + JE4 1995-12 (Disc 2).cue" size="97" crc="fe4bd6dd" sha1="93a497c59463ba022523475d4f9b228570086bbf"/>
<rom name="[OS] Linux + JE4 1995-12 (Disc 2).img" size="621911136" crc="4b4045cc" sha1="b88837ead4cdafff6830de34e10cc85994d6957a"/>
<rom name="[OS] Linux + JE4 1995-12 (Disc 2).sub" size="25384128" crc="b2994c95" sha1="7f53ee98031a618a7a06f5f4ba3d51857a6f41a7"/>
-
+
<rom name="[OS] Linux + JE4 1995-12 (Disc 3).ccd" size="772" crc="477cf66e" sha1="cbfe790b5e67fe104bd787f5a654270f75e5ce9b"/>
<rom name="[OS] Linux + JE4 1995-12 (Disc 3).cue" size="97" crc="34985852" sha1="019d58702b954623ff7832e46aebf4d43c38e134"/>
<rom name="[OS] Linux + JE4 1995-12 (Disc 3).img" size="631723680" crc="5c9440f4" sha1="8ee8a9cebe00a45c908bba88ef453e3d426d6260"/>
@@ -420,7 +420,7 @@ User/save disks that can be created from the game itself are not included.
</diskarea>
</part>
</software>
-
+
<software name="oasyswin">
<!--
Origin: Neo Kobe Collection
@@ -436,7 +436,7 @@ User/save disks that can be created from the game itself are not included.
</diskarea>
</part>
</software>
-
+
<software name="tss1110">
<!--
Origin: Neo Kobe Collection
@@ -452,7 +452,7 @@ User/save disks that can be created from the game itself are not included.
</diskarea>
</part>
</software>
-
+
<software name="tss1120">
<!--
Origin: Neo Kobe Collection
@@ -488,7 +488,7 @@ User/save disks that can be created from the game itself are not included.
</diskarea>
</part>
</software>
-
+
<software name="tss1130">
<!--
Origin: Neo Kobe Collection
@@ -504,7 +504,7 @@ User/save disks that can be created from the game itself are not included.
</diskarea>
</part>
</software>
-
+
<software name="tss2110a">
<!--
Origin: Neo Kobe Collection
@@ -530,7 +530,7 @@ User/save disks that can be created from the game itself are not included.
</diskarea>
</part>
</software>
-
+
<software name="tss2151">
<!--
Origin: Neo Kobe Collection
@@ -548,7 +548,7 @@ User/save disks that can be created from the game itself are not included.
</diskarea>
</part>
</software>
-
+
<!-- Missing a floppy disk -->
<software name="win31">
<!--
@@ -572,7 +572,7 @@ User/save disks that can be created from the game itself are not included.
</diskarea>
</part>
</software>
-
+
<software name="win95">
<!--
Origin: Neo Kobe Collection
@@ -588,12 +588,12 @@ User/save disks that can be created from the game itself are not included.
</diskarea>
</part>
</software>
-
-
-
+
+
+
<!-- Game (& Utility) Disks -->
-
-
+
+
<software name="100isshu">
<!--
Origin: Neo Kobe Collection
@@ -5148,7 +5148,7 @@ User/save disks that can be created from the game itself are not included.
Origin: Tokugawa Corporate Forums (yukin)
<rom name="MM3.mdf" size="15523200" crc="926d169b" sha1="107090bdd34e831f27ea979e3fd6a24c86aa418a"/>
<rom name="MM3.mds" size="500" crc="99adcc2f" sha1="1d6b9f2257f821d06d0f85a021e5be5a2f448f03"/>
-
+
CUE file used for CHD conversion:
<rom name="MM3.cue" size="64" crc="5c30fa2b" sha1="7b53d089cbc4fb4fa0d517adafd8f74f8c94a652"/>
-->
diff --git a/hash/gba.xml b/hash/gba.xml
index a28a781dd93..c75e18f84c7 100644
--- a/hash/gba.xml
+++ b/hash/gba.xml
@@ -12327,7 +12327,7 @@
</dataarea>
</part>
</software>
-
+
<software name="v_sharkt" supported="no">
<description>Game Boy Advance Video - Shark Tale (USA, Rev. 6)</description>
<year>2004?</year>
@@ -12340,7 +12340,7 @@
</dataarea>
</part>
</software>
-
+
<software name="v_sharkta" cloneof="v_sharkt" supported="no">
<description>Game Boy Advance Video - Shark Tale (USA, Rev. 5)</description>
<year>2004?</year>
@@ -12379,7 +12379,7 @@
</dataarea>
</part>
</software>
-
+
<software name="v_2shrst" supported="no">
<description>Game Boy Advance Video - Shrek + Shark Tale (USA)</description>
<year>2004?</year>
@@ -30364,7 +30364,7 @@
<publisher>Infogrames</publisher>
<info name="serial" value="AGB-ASOP-(EUR,UKV)"/>
<part name="cart" interface="gba_cart">
- <feature name="pcb" value="AGB-E02-30" /> <!-- Also found on AGB-E02-20 -->
+ <feature name="pcb" value="AGB-E02-30" /> <!-- Also found on AGB-E02-20 -->
<feature name="u1" value="U1 GPIO MASKROM" />
<feature name="u2" value="U2 512K/1M FLASH [39VF512]" />
<feature name="slot" value="gba_flash" />
@@ -32407,7 +32407,7 @@ The cart also contained a non-empty SRAM save which we currently include in the
<publisher>Nintendo</publisher>
<info name="serial" value="AGB-AMAE-USA, AGB-AMAP"/>
<part name="cart" interface="gba_cart">
- <feature name="pcb" value="AGB-E03-01" /> <!-- Also found on AGB-E03-10 -->
+ <feature name="pcb" value="AGB-E03-01" /> <!-- Also found on AGB-E03-10 -->
<feature name="u1" value="U1 MASK ROM" />
<feature name="u2" value="U2 4K/64K EEPROM [9853]" />
<feature name="slot" value="gba_eeprom_4k" />
diff --git a/hash/intv.xml b/hash/intv.xml
index 5156c513b6b..7eb10395850 100644
--- a/hash/intv.xml
+++ b/hash/intv.xml
@@ -958,7 +958,7 @@
</dataarea>
</part>
</software>
-
+
<software name="mspacman" supported="no">
<description>Ms. Pac-Man</description>
<year>1986</year>
diff --git a/hash/leapster.xml b/hash/leapster.xml
index fcbe2c23210..9716b87bc51 100644
--- a/hash/leapster.xml
+++ b/hash/leapster.xml
@@ -188,7 +188,7 @@
</dataarea>
</part>
</software>
-
+
<software name="princwen">
<description>Disney Princess - Worlds of Enchantment (USA)</description>
<year>2007?</year>
@@ -212,7 +212,7 @@
</dataarea>
</part>
</software>
-
+
<software name="findnemo">
<description>Finding Nemo (USA)</description>
<year>2005?</year>
@@ -260,7 +260,7 @@
</dataarea>
</part>
</software>
-
+
<software name="diegogo">
<description>Go Diego Go! - Animal Rescuer (USA)</description>
<year>2007?</year>
@@ -320,7 +320,7 @@
</dataarea>
</part>
</software>
-
+
<software name="brunobls">
<description>Lernst du Malen &amp; Schreiben - Mit Bruno Bleistift (Ger)</description>
<year>2004?</year>
@@ -440,7 +440,7 @@
</dataarea>
</part>
</software>
-
+
<software name="spidermn">
<description>Spider-Man - The Case of the Sinister Speller (USA)</description>
<year>2003</year>
@@ -488,7 +488,7 @@
</dataarea>
</part>
</software>
-
+
<software name="toystor3">
<description>Toy Story 3 (USA)</description>
<year>2010?</year>
diff --git a/hash/megadriv.xml b/hash/megadriv.xml
index c0ac8aac745..1d9703a2736 100644
--- a/hash/megadriv.xml
+++ b/hash/megadriv.xml
@@ -9761,7 +9761,7 @@ but dumps still have to be confirmed.
</dataarea>
</part>
</software>
-
+
<software name="16mj2">
<description>Shi Liu Zhang Ma Jiang II</description>
<year>199?</year>
@@ -13806,7 +13806,7 @@ but dumps still have to be confirmed.
</dataarea>
</part>
</software>
-
+
<software name="deathdlp" cloneof="deathdl">
<description>Death Duel (USA, Prototype 19920506)</description>
<year>1992</year>
@@ -16602,7 +16602,7 @@ but dumps still have to be confirmed.
</dataarea>
</part>
</software>
-
+
<!-- This is the same as the final, but without the padding up to 512Kb and with different checksum in the internal header -->
<software name="homea2p" cloneof="homea2">
<description>Home Alone 2 - Lost in New York (USA, Prototype 19930929)</description>
@@ -21462,7 +21462,7 @@ Notice that these are not working on real hardware due to bugged code with VDP i
</dataarea>
</part>
</software>
-
+
<software name="paperboyp" cloneof="paperboy">
<description>Paperboy (USA, Prototype 19911028)</description>
<year>1992</year>
@@ -22861,7 +22861,7 @@ Notice that these are not working on real hardware due to bugged code with VDP i
</dataarea>
</part>
</software>
-
+
<!-- This is the same as the final, but without the padding up to 1Mb and with no checksum in the internal header -->
<software name="renstimp" cloneof="renstim">
<description>Stimpy's Invention Starring Starring Ren Hoëk &amp; Stimpy (Euro, Prototype 19931209)</description>
@@ -23248,7 +23248,7 @@ Notice that these are not working on real hardware due to bugged code with VDP i
</dataarea>
</part>
</software>
-
+
<software name="roadblstp" cloneof="roadblst">
<description>RoadBlasters (USA, Prototype 19910627)</description>
<year>1992</year>
@@ -25222,7 +25222,7 @@ Notice that these are not working on real hardware due to bugged code with VDP i
</dataarea>
</part>
</software>
-
+
<software name="speedbl2up" cloneof="speedbl2">
<description>Speedball 2 - Brutal Deluxe (USA, Prototype 19910607)</description>
<year>1991</year>
@@ -26377,7 +26377,7 @@ Notice that these are not working on real hardware due to bugged code with VDP i
</dataarea>
</part>
</software>
-
+
<software name="lasordap" cloneof="suprleag">
<description>Tommy Lasorda Baseball (USA, Prototype 19890430)</description>
<year>1989</year>
@@ -27537,7 +27537,7 @@ Notice that these are not working on real hardware due to bugged code with VDP i
</dataarea>
</part>
</software>
-
+
<!-- This is the same as the final, but with "Sega_Channel" XORed at the end. -->
<software name="toejam2p2" cloneof="toejam2">
<description>Toe Jam &amp; Earl in Panic on Funkotron (Prototype 19930911)</description>
@@ -30378,7 +30378,7 @@ Notice that these are not working on real hardware due to bugged code with VDP i
</dataarea>
</part>
</software>
-
+
<software name="xinqig1" cloneof="beggarp">
<description>Xin Qi Gai Wang Zi (Chi, Alt)</description>
<year>1996</year>
@@ -31285,7 +31285,7 @@ Notice that these are not working on real hardware due to bugged code with VDP i
</dataarea>
</part>
</software>
-
+
<software name="cjmjclub">
<description>Chaoji Majiang Club (Tw)</description>
<year>1995</year>
@@ -31360,7 +31360,7 @@ Notice that these are not working on real hardware due to bugged code with VDP i
</dataarea>
</part>
</software>
-
+
<software name="jujimj2">
<description>Ju Ji Ma Jiang II</description>
<year>199?</year>
diff --git a/hash/n64.xml b/hash/n64.xml
index 97c620f58dc..79bfc6a0bfe 100644
--- a/hash/n64.xml
+++ b/hash/n64.xml
@@ -2510,7 +2510,7 @@ patched out (+ a fix for internal checksum)
</part>
</software>
-<!--
+<!--
This cart features a RTC, currently unemulated
-->
<software name="doubutsu">
@@ -5745,7 +5745,7 @@ This cart features a RTC, currently unemulated
</part>
</software>
-<!--
+<!--
This cart features two SmartMedia slots to import pictures to manipulate in the game, currently unemulated
-->
<software name="mariopho">
@@ -6281,7 +6281,7 @@ This cart features two SmartMedia slots to import pictures to manipulate in the
</part>
</software>
-<!--
+<!--
This cart features a built-in RJ-42 Modem Connection port to play online, currently unemulated
-->
<software name="moritash">
@@ -9874,7 +9874,7 @@ patched out (+ a fix for internal checksum)
<part name="cart" interface="n64_cart">
<feature name="pcb" value="NUS-01A-01" />
<feature name="u1" value="NUS-NSMP-0" />
- <feature name="u2" value="BU9850" /> <!-- also found with BK4D-NUS -->
+ <feature name="u2" value="BU9850" /> <!-- also found with BK4D-NUS -->
<feature name="u3" value="CIC-NUS-7101" />
<feature name="cart_model" value="NUS-006(EUR)" />
<feature name="cart_back_label" value="NUS-EUR" />
@@ -10211,9 +10211,9 @@ patched out (+ a fix for internal checksum)
</part>
</software>
-<!--
-The game came with the Nintendo-Seta Bio Sensor, a special controller with a clip on the end, to measure
-user's heart beat. One end of the sensor plugs into the extension port on the controller, and the other end
+<!--
+The game came with the Nintendo-Seta Bio Sensor, a special controller with a clip on the end, to measure
+user's heart beat. One end of the sensor plugs into the extension port on the controller, and the other end
clips onto the player's ear.
-->
<software name="tetris64">
diff --git a/hash/pc98.xml b/hash/pc98.xml
index 77d64bcb512..22b43270c4d 100644
--- a/hash/pc98.xml
+++ b/hash/pc98.xml
@@ -27836,7 +27836,7 @@ Requires MS-DOS 5.00H plus an unknown procedure (HDD install?)
</dataarea>
</part>
</software>
-
+
<!-- confirmed as good by peter_j -->
<software name="3dgolfb" cloneof="3dgolf">
<description>New 3D Golf Simulation - Harukanaru Augusta (Alt Format)</description>
@@ -27872,7 +27872,7 @@ Requires MS-DOS 5.00H plus an unknown procedure (HDD install?)
</dataarea>
</part>
</software>
-
+
<!-- confirmed as good by peter_j -->
<software name="3dgolf8la" cloneof="3dgolf">
<description>New 3D Golf Simulation - Eight Lakes G.C. (Alt Format)</description>
@@ -27917,7 +27917,7 @@ Requires MS-DOS 5.00H plus an unknown procedure (HDD install?)
</dataarea>
</part>
</software>
-
+
<!-- confirmed as good by peter_j -->
<software name="3dgolfwka" cloneof="3dgolf">
<description>New 3D Golf Simulation - Waialae no Kiseki (Alt Format)</description>
diff --git a/hash/pc98_cd.xml b/hash/pc98_cd.xml
index d98f8e69456..ad359b9d292 100644
--- a/hash/pc98_cd.xml
+++ b/hash/pc98_cd.xml
@@ -2,15 +2,15 @@
<!DOCTYPE softwarelist SYSTEM "softwarelist.dtd">
<softwarelist name="pc98_cd" description="NEC PC-9801 CD-ROMs">
- <!--
+ <!--
Partial list of PC-9801/PC-9821 CD-ROMs.
-
+
Floppy disks are also included where needed. They are attached to the floppy_5_25 interface
for convenience, as the PC-98x1 driver always emulates 5.25" drives. This isn't realistic,
though, as CD-ROM software was generally released very late in the life of the plaform,
when 3.5" floppies were much more common.
-
+
-->
<!-- OS disks -->
@@ -20,9 +20,9 @@
<!--
Origin: Unknown
<rom name="Windows 2000 Professional (PC-9821) - W2PCCP_JA.iso" size="409946112" crc="ffffffff" sha1="f0ad97e933a8fe835fdb7211ef9034862b68d7f9"/>
-
+
CUE file used for conversion:
- <rom name="Windows 2000 Professional (PC-9821) - W2PCCP_JA.cue" size="108" crc="5e4281a4" sha1="60b45b2155b2bce7d550f7ed99d4b95247e2c786"/>
+ <rom name="Windows 2000 Professional (PC-9821) - W2PCCP_JA.cue" size="108" crc="5e4281a4" sha1="60b45b2155b2bce7d550f7ed99d4b95247e2c786"/>
-->
<description>Windows 2000 Professional (Upgrade, W2PCCP)</description>
<year>2000</year>
@@ -38,7 +38,7 @@
<!--
Origin: Unknown
<rom name="Windows 2000 Professional (PC-9821) - W2PFPP_JA.iso" size="409946112" crc="ffffffff" sha1="ef5035b8c6b566552eba9f16e085272632e259b4"/>
-
+
CUE file used for conversion:
<rom name="Windows 2000 Professional (PC-9821) - W2PFPP_JA.cue" size="108" crc="90edbbcd" sha1="a2b214d641906d27172e10d35094e652647d4194"/>
-->
@@ -56,7 +56,7 @@
<!--
Origin: Unknown
<rom name="Windows 2000 Professional (PC-9821) - W2PSEL_JA.iso" size="409946112" crc="ffffffff" sha1="b48ebce2da480ab8a7e7b1e82b33bb01543b2b21"/>
-
+
CUE file used for conversion:
<rom name="Windows 2000 Professional (PC-9821) - W2PSEL_JA.cue" size="108" crc="9c9e146b" sha1="0be47b35ebfa297868cadc79bb77bdd56f3aa1ef"/>
-->
@@ -74,7 +74,7 @@
<!--
Origin: Unknown
<rom name="Windows 2000 Professional with SP4 (PC-9821) - ZRMPFPP_JA.iso" size="420202496" crc="ffffffff" sha1="8bf88f199b4919c8d340cd40a80bfb9b6e001f49"/>
-
+
CUE file used for conversion:
<rom name="Windows 2000 Professional with SP4 (PC-9821) - ZRMPFPP_JA.cue" size="118" crc="f4714a5e" sha1="b1890c27ba93ac56e4e7bed741c5323f3695da58"/>
-->
@@ -92,7 +92,7 @@
<!--
Origin: Unknown
<rom name="Windows 2000 Server (PC-9821) - W2SFPP_JA.iso" size="479168512" crc="ffffffff" sha1="57ec6c59bf0d5918031e5e4aa115743616fc5200"/>
-
+
CUE file used for conversion:
<rom name="Windows 2000 Server (PC-9821) - W2SFPP_JA.cue" size="102" crc="a2b02fad" sha1="3086c000c75d4a3a254caa867f7adab8b74ad09f"/>
-->
@@ -110,7 +110,7 @@
<!--
Origin: Unknown
<rom name="Windows 2000 Server (PC-9821) - W2SSEL_JA.iso" size="479168512" crc="ffffffff" sha1="325e1f718981603fc21b88f34643efb71e0ee7e1"/>
-
+
CUE file used for conversion:
<rom name="Windows 2000 Server (PC-9821) - W2SSEL_JA.cue" size="102" crc="aec3800b" sha1="6a64d6297d6906ce672ce77967d3bde940202eac"/>
-->
@@ -128,7 +128,7 @@
<!--
Origin: Unknown
<rom name="Windows 2000 Server with SP4 (PC-9821) - ZRMSFPP_JA.iso" size="488269824" crc="ffffffff" sha1="f43c06cfa45289228ce47f815aa96efb8b9d1574"/>
-
+
CUE file used for conversion:
<rom name="Windows 2000 Server with SP4 (PC-9821) - ZRMSFPP_JA.cue" size="112" crc="6b01db5c" sha1="8b58fb3e2bbfc31d201b4c58e905075da7eb8031"/>
-->
@@ -148,7 +148,7 @@
Origin: Unknown
<rom name="disc2.ISO" size="434356224" crc="ffffffff" sha1="e2db9d9e3aab1401979d103d2d6109bfe3eff3ed"/>
<rom name="image.ISO" size="531824640" crc="ffffffff" sha1="e906c512ec2ab1e6244eec85388551a993bee0a7"/>
-
+
CUE files used for conversion:
<rom name="disc2.cue" size="66" crc="2cabba7b" sha1="38cfe76167cf3065478036c386c69693fa0bf5f3"/>
<rom name="image.cue" size="66" crc="3f846e22" sha1="d3d798255e5d26cd8485a5c5f7aa086a51368ebe"/>
@@ -172,7 +172,7 @@
<!--
Origin: Unknown
<rom name="Microsoft Windows 95 PC-98 (JPN).iso" size="81395712" crc="d402c155" sha1="14d10f62db11397ea46bdf02d1619f1b8e1ff345"/>
-
+
CUE file used for conversion:
<rom name="Microsoft Windows 95 PC-98 (JPN).cue" size="93" crc="c4113669" sha1="3ee6d0113b8efe9cf0ee19fe6054165233fa9906"/>
-->
@@ -191,7 +191,7 @@
<!--
Origin: Unknown
<rom name="Microsoft Windows 98 x86 &amp; PC-98 (JPN).iso" size="508647424" crc="f82c51a9" sha1="3607d2cc8fea57ca915954e9ff2e2cbc82a02fff"/>
-
+
CUE file used for conversion:
<rom name="Microsoft Windows 98 x86 &amp; PC-98 (JPN).cue" size="99" crc="1229745f" sha1="5181dc844bf7f7d5acd3e2fad4ad2e2c8af70297"/>
-->
@@ -309,7 +309,7 @@
</diskarea>
</part>
</software>
-
+
<software name="akikogld">
<!--
Origin: peter_j (Super Lonely Terminal)
@@ -361,13 +361,13 @@
<rom name="Image.cue" size="1488" crc="5585f53a" sha1="ab10e702dcca182e12a551b0fa11c419704dccae"/>
<rom name="Image.img" size="658393008" crc="f3b99e90" sha1="9fcdc50989886636f074354745bbf16bbed24b67"/>
<rom name="Image.sub" size="26873184" crc="eed944ab" sha1="1b486d3f029634da68bd1a2465b6a8a43e75b6c5"/>
-
+
The original CUE indicates MODE1/2352 for the data track, but this seems to be wrong, as all the data
sectors in track 1 are actually mode 2, and MS-DOS doesn't recognize the file system. To avoid this, the
CHD was converted through a modified CUE with MODE2/2352.
-
+
Also, this disc has a PlayStation header in sector 16. Bad dump or just a mastering mistake?
-
+
<rom name="Image_mode2.cue" size="1488" crc="2f235ede" sha1="ecc220ebebb859889406b95d5538f025321e4991"/>
-->
<description>Appare-den - Fukuryuu no Shou</description>
@@ -422,9 +422,9 @@
<!--
Origin: P2P
<rom name="br1.iso" size="4431168" crc="28ca5237" sha1="6de45ad7c24195e9eed8b3f578305698150671aa"/>
-
+
CUE file used for conversion:
- <rom name="br1.cue" size="64" crc="55b42ab8" sha1="f1f3e6612d5c205bbe3c771506ac3a95febe6067"/>
+ <rom name="br1.cue" size="64" crc="55b42ab8" sha1="f1f3e6612d5c205bbe3c771506ac3a95febe6067"/>
-->
<description>Brandish Campaign-ban</description>
<year>1996</year>
@@ -473,9 +473,9 @@
<!--
Origin: P2P
<rom name="br3.iso" size="11275488" crc="8cdbb15b" sha1="692df1bae5459c16469e79b581fb5deb212665e3"/>
-
+
CUE file used for conversion:
- <rom name="br3.cue" size="64" crc="6e9e0d16" sha1="f17c32e361745b7a93fc231826a9af4160692fb4"/>
+ <rom name="br3.cue" size="64" crc="6e9e0d16" sha1="f17c32e361745b7a93fc231826a9af4160692fb4"/>
-->
<description>Brandish 3 - Spirit of Balcan - Campaign-ban</description>
<year>1996</year>
@@ -548,9 +548,9 @@
<!--
Origin: P2P
<rom name="美少女パソコンソフト大全 デジ・パラ Vol.1.iso" size="219504640" crc="e92a4b2a" sha1="10c86cd519a28fc583fd01473eed9d9b3baee789"/>
-
+
CUE file used for conversion:
- <rom name="美少女パソコンソフト大全 デジ・パラ Vol.1.cue" size="119" crc="91bd2775" sha1="ee1f59ef736d2243a75ef86e5c471a72ba9fa222"/>
+ <rom name="美少女パソコンソフト大全 デジ・パラ Vol.1.cue" size="119" crc="91bd2775" sha1="ee1f59ef736d2243a75ef86e5c471a72ba9fa222"/>
-->
<description>Bishoujo Pasocom Soft Taizen - Digi-para - Digital Paradise - Vol. 1</description>
<year>1996</year>
@@ -644,7 +644,7 @@
</diskarea>
</part>
</software>
-
+
<software name="emit1">
<!--
Origin: peter_j (Super Lonely Terminal)
@@ -675,7 +675,7 @@
</diskarea>
</part>
</software>
-
+
<software name="emit2">
<!--
Origin: peter_j (Super Lonely Terminal)
@@ -698,7 +698,7 @@
</diskarea>
</part>
</software>
-
+
<software name="emit3">
<!--
Origin: peter_j (Super Lonely Terminal)
@@ -784,7 +784,7 @@
<rom name="galpani (1995)(kaneko - creo i).ccd" size="3120" crc="788eda2a" sha1="12dd368e864857dc3d206dae6890621536d322da"/>
<rom name="galpani (1995)(kaneko - creo i).img" size="497229264" crc="8b3ce23e" sha1="9bd91b2e62d5847cc65bd363e7a59bd7bda15613"/>
<rom name="galpani (1995)(kaneko - creo i).sub" size="20295072" crc="c2670009" sha1="c0cf2725384ef328682d5c28f017f9dddbc6f28b"/>
-
+
After conversion with IsoBuster + EAC:
<rom name="galpani.cue" size="1725" crc="17aa363e" sha1="4cb40d4ec35eff243114029f3ddc90d81eb646d3"/>
<rom name="track01.bin" size="103473888" crc="18ce00b3" sha1="3d6ed2ff296d77ad8df3e76c2765f1cc5ca69115"/>
@@ -816,7 +816,7 @@
<!--
Origin: P2P
<rom name="GIRI GIRI PARADISE (1996)(May-Be Soft).ISO" size="75416880" crc="881e38b6" sha1="a836803d3af8d9554edfa304d9007bf9176a92db"/>
-
+
CUE file used for conversion:
<rom name="GIRI GIRI PARADISE (1996)(May-Be Soft).cue" size="99" crc="bdb48d15" sha1="f52ce65cbb8f7ee719a6c7874b45149f1a9ac5cd"/>
-->
@@ -866,7 +866,7 @@
</diskarea>
</part>
</software>
-
+
<software name="inhearth">
<!--
Origin unknwon
@@ -941,7 +941,7 @@
</diskarea>
</part>
</software>
-
+
<software name="lodoss">
<!--
Origin unknwon
@@ -1161,9 +1161,9 @@
<!--
Origin: P2P
<rom name="Ponytail Anthology vol.1 (1996)(Ponytail Soft).iso" size="16652288" crc="0c2af0dc" sha1="392fdfdf0de6bc0d469f802b207b38fbd7fef9f6"/>
-
+
CUE file used for conversion:
- <rom name="Ponytail Anthology vol.1 (1996)(Ponytail Soft).cue" size="107" crc="1a019c62" sha1="0ad502b5a8be7e178c05de19d8a74a4542a588e3"/>
+ <rom name="Ponytail Anthology vol.1 (1996)(Ponytail Soft).cue" size="107" crc="1a019c62" sha1="0ad502b5a8be7e178c05de19d8a74a4542a588e3"/>
-->
<description>Ponytail Anthology Vol. 1</description>
<year>1996</year>
@@ -1180,9 +1180,9 @@
<!--
Origin: P2P
<rom name="Ponytail Anthology vol.2 (1996)(Ponytail Soft).iso" size="12025856" crc="216080b4" sha1="42402615993baea8b09987463c6c2ebe08ff93d0"/>
-
+
CUE file used for conversion:
- <rom name="Ponytail Anthology vol.2 (1996)(Ponytail Soft).cue" size="107" crc="c795a04c" sha1="4fef4206c9ee3bb2cae2207313aebbdc21369b39"/>
+ <rom name="Ponytail Anthology vol.2 (1996)(Ponytail Soft).cue" size="107" crc="c795a04c" sha1="4fef4206c9ee3bb2cae2207313aebbdc21369b39"/>
-->
<description>Ponytail Anthology Vol. 2</description>
<year>1996</year>
@@ -1199,9 +1199,9 @@
<!--
Origin: P2P
<rom name="Ponytail Anthology vol.3 (1996)(Ponytail Soft).iso" size="19972096" crc="798581ae" sha1="52b663b863017e21e25c8855ad0da39a89a382d9"/>
-
+
CUE file used for conversion:
- <rom name="Ponytail Anthology vol.3 (1996)(Ponytail Soft).cue" size="107" crc="3a36b669" sha1="9b446abf11350f2d0ea8640f43a3f93784f1e2ce"/>
+ <rom name="Ponytail Anthology vol.3 (1996)(Ponytail Soft).cue" size="107" crc="3a36b669" sha1="9b446abf11350f2d0ea8640f43a3f93784f1e2ce"/>
-->
<description>Ponytail Anthology Vol. 3</description>
<year>1996</year>
@@ -1221,11 +1221,11 @@
<rom name="Image.cue" size="1611" crc="426e02ab" sha1="b41aca944329184740ae31642d209e13123132d7"/>
<rom name="Image.img" size="333958128" crc="26163a8c" sha1="b18171ceba72e72d23ca502e05173158c4de5538"/>
<rom name="Image.sub" size="13630944" crc="5c783df4" sha1="f17dd7023dc4ffad27e4741ba000326e49329bc9"/>
-
+
The original CUE indicates MODE1/2352 for the data track, but this seems to be wrong, as all the data
sectors in track 1 are actually mode 2, and MS-DOS doesn't recognize the file system. To avoid this, the
CHD was converted through a modified CUE with MODE2/2352.
-
+
<rom name="Image_mode2.cue" size="1611" crc="6071e32b" sha1="be8aaa23a63272e7a5b7f3f5972d982345c1d65d"/>
-->
<description>Professional Baseball 1996</description>
@@ -1332,9 +1332,9 @@
<!--
Origin: P2P
<rom name="Ryouki no Ori 1 (1996)(PLANTECH-ZEROSYSTEM).ISO" size="119138304" crc="193e09d1" sha1="caffe3f19e618cc10af3fcbe6df7c48ab717a928"/>
-
+
CUE file used for conversion:
- <rom name="Ryouki no Ori 1 (1996)(PLANTECH-ZEROSYSTEM).cue" size="104" crc="176f9e3f" sha1="22080c96d5566c7de03beb349c5fa026c677fa94"/>
+ <rom name="Ryouki no Ori 1 (1996)(PLANTECH-ZEROSYSTEM).cue" size="104" crc="176f9e3f" sha1="22080c96d5566c7de03beb349c5fa026c677fa94"/>
-->
<description>Ryouki no Ori</description>
<year>1995</year>
@@ -1352,9 +1352,9 @@
<!--
Origin: P2P
<rom name="Ryouki no Ori 2 (1997)(PLANTECH-ZEROSYSTEM).ISO" size="119138304" crc="193e09d1" sha1="caffe3f19e618cc10af3fcbe6df7c48ab717a928"/>
-
+
CUE file used for conversion:
- <rom name="Ryouki no Ori 2 (1997)(PLANTECH-ZEROSYSTEM).cue" size="104" crc="50b6c537" sha1="b64354c20cddc43c21c9e406320e1fd673ee5912"/>
+ <rom name="Ryouki no Ori 2 (1997)(PLANTECH-ZEROSYSTEM).cue" size="104" crc="50b6c537" sha1="b64354c20cddc43c21c9e406320e1fd673ee5912"/>
-->
<description>Ryouki no Ori Dai-2-Shou</description>
<year>1996</year>
@@ -1488,12 +1488,12 @@
</diskarea>
</part>
</software>
-
+
<software name="sela">
<!--
Origin: peter_j (Super Lonely Terminal)
<rom name="sela_cd.iso" size="198440960" crc="82598cf7" sha1="366f4c38b16d865c1e826b447dc566d94633aa7b"/>
-
+
<rom name="sela_music_cd.bin" size="511383600" crc="53c9cd59" sha1="9955790be92eb99d54c449b808e0ccc5e42111d7"/>
<rom name="sela_music_cd.cue" size="714" crc="e92f82d0" sha1="e0d88a3d6d36b69268e0f471db540508e708f26c"/>
-->
@@ -1556,7 +1556,7 @@
</diskarea>
</part>
</software>
-
+
<software name="srmp4f">
<!--
Origin unknwon
@@ -1580,7 +1580,7 @@
<!--
Origin: Unknown
<rom name="strike commander plus.iso" size="86388960" crc="d8953dae" sha1="80f27e2682f41ee5d82a3c8cad59bb5aeb7e9817"/>
-
+
CUE file used for conversion:
<rom name="strike commander plus.cue" size="82" crc="0f9a2f59" sha1="90970d4595d29c7efd90f39e07dea9e46b5e297f"/>
-->
@@ -1595,7 +1595,7 @@
</diskarea>
</part>
</software>
-
+
<!-- This contains some doujin games for PC-98 and some for Windows3.1/95 -->
<software name="takerud1">
<!--
@@ -1712,7 +1712,7 @@
</diskarea>
</part>
</software>
-
+
<software name="usnf">
<!--
Origin: peter_j (Super Lonely Terminal)
@@ -1803,9 +1803,9 @@
<!--
Origin: Unknown
<rom name="ZAI_METAJO CD (1996)(ANJIN).ISO" size="40092192" crc="c41f199f" sha1="08aae335ff1fff2a674a1012be423720f3273535"/>
-
+
CUE file used for conversion:
- <rom name="ZAI_METAJO CD (1996)(ANJIN).cue" size="88" crc="3c3cbf79" sha1="504effcd208f11f867c340d2bc046d46f5519ab5"/>
+ <rom name="ZAI_METAJO CD (1996)(ANJIN).cue" size="88" crc="3c3cbf79" sha1="504effcd208f11f867c340d2bc046d46f5519ab5"/>
-->
<description>Zai Metajo</description>
<year>1996</year>
diff --git a/hash/pce_tourvision.xml b/hash/pce_tourvision.xml
index 1900535d47e..6c3d736309c 100644
--- a/hash/pce_tourvision.xml
+++ b/hash/pce_tourvision.xml
@@ -553,7 +553,7 @@ Notes:
</part>
</software>
-
+
<!--Override -->
<software name="override">
<description>Override (Tourvision PCE bootleg)</description>
diff --git a/hash/pippin.xml b/hash/pippin.xml
index 1f32db3bcb8..80b13e46ad2 100644
--- a/hash/pippin.xml
+++ b/hash/pippin.xml
@@ -106,7 +106,7 @@ NOTE: This list is here only to document available dumps and it's not used (yet)
<software name="hanshind">
<description>1995.1.17 Hanshin Daishinsai (Jpn)</description>
<year>1996</year>
- <publisher>Keikakudo</publisher> <!-- 計画堂 -->
+ <publisher>Keikakudo</publisher> <!-- 計画堂 -->
<info name="serial" value="BDS-20005" />
<info name="alt_title" value="1995.1.17 阪神大震ç½" />
<part name="cdrom" interface="pippin_cdrom">
@@ -236,7 +236,7 @@ NOTE: This list is here only to document available dumps and it's not used (yet)
<software name="chisatom">
<description>Chisato Moritaka CD-Rom Watarase Bashi (Jpn)</description>
<year>1996</year>
- <publisher>Oracion</publisher> <!-- オラシオン -->
+ <publisher>Oracion</publisher> <!-- オラシオン -->
<info name="serial" value="BDE-10007" />
<info name="alt_title" value="森高åƒé‡ŒCD-ROM 渡良瀬橋" />
<part name="cdrom" interface="pippin_cdrom">
@@ -249,7 +249,7 @@ NOTE: This list is here only to document available dumps and it's not used (yet)
<software name="circus">
<description>Circus! (Jpn)</description>
<year>1996</year>
- <publisher>Voyager</publisher> <!-- ボイジャー -->
+ <publisher>Voyager</publisher> <!-- ボイジャー -->
<info name="serial" value="BDS-20031" />
<info name="alt_title" value="サーカスï¼" />
<part name="cdrom" interface="pippin_cdrom">
@@ -274,7 +274,7 @@ NOTE: This list is here only to document available dumps and it's not used (yet)
<software name="dazzloid">
<description>Dazzeloids (Jpn)</description>
<year>1996</year>
- <publisher>Voyager</publisher> <!-- ボイジャー -->
+ <publisher>Voyager</publisher> <!-- ボイジャー -->
<info name="serial" value="BDS-20030" />
<info name="alt_title" value="ダズロイド" />
<part name="cdrom" interface="pippin_cdrom">
@@ -336,7 +336,7 @@ NOTE: This list is here only to document available dumps and it's not used (yet)
<software name="ffaliens">
<description>Funky Funny Aliens (Jpn)</description>
<year>1996</year>
- <publisher>Amuse</publisher> <!-- アミューズ -->
+ <publisher>Amuse</publisher> <!-- アミューズ -->
<info name="serial" value="BDS-20014" />
<info name="alt_title" value="ファンキー ファニー エイリアンズ" />
<part name="cdrom" interface="pippin_cdrom">
@@ -349,7 +349,7 @@ NOTE: This list is here only to document available dumps and it's not used (yet)
<software name="gadget">
<description>Gadget (Jpn)</description>
<year>1996</year>
- <publisher>Synergy Ikunangaku</publisher> <!-- シナジー幾何学 -->
+ <publisher>Synergy Ikunangaku</publisher> <!-- シナジー幾何学 -->
<info name="serial" value="BDS-20033" />
<part name="cdrom" interface="pippin_cdrom">
<diskarea name="cdrom">
@@ -361,7 +361,7 @@ NOTE: This list is here only to document available dumps and it's not used (yet)
<software name="gakkoku">
<description>Gakko no Kowai Uwasa - Hanako-san ga Kita!! (Jpn)</description>
<year>1996</year>
- <publisher>Amuse</publisher> <!-- アミューズ -->
+ <publisher>Amuse</publisher> <!-- アミューズ -->
<info name="serial" value="BDS-20012" />
<info name="alt_title" value="学校ã®ã‚³ãƒ¯ã‚¤ã†ã‚ã•ã€€èŠ±å­ã•ã‚“ãŒããŸ!!" />
<part name="cdrom" interface="pippin_cdrom">
@@ -425,7 +425,7 @@ NOTE: This list is here only to document available dumps and it's not used (yet)
<software name="kidsbox">
<description>Kids Box (Jpn)</description>
<year>1996</year>
- <publisher>Ask Kodansha</publisher> <!-- アスク講談社 -->
+ <publisher>Ask Kodansha</publisher> <!-- アスク講談社 -->
<info name="serial" value="BDS-20003" />
<info name="alt_title" value="キッズ・ボックス" />
<part name="cdrom" interface="pippin_cdrom">
@@ -475,7 +475,7 @@ NOTE: This list is here only to document available dumps and it's not used (yet)
<software name="lzone">
<description>L-Zone (Jpn)</description>
<year>1996</year>
- <publisher>Synergy Ikunangaku</publisher> <!-- シナジー幾何学 -->
+ <publisher>Synergy Ikunangaku</publisher> <!-- シナジー幾何学 -->
<info name="serial" value="BDS-20017" />
<part name="cdrom" interface="pippin_cdrom">
<diskarea name="cdrom">
@@ -561,7 +561,7 @@ NOTE: This list is here only to document available dumps and it's not used (yet)
<software name="music1">
<description>Music Island Vol. 1 (Prokofiev Peter &amp; the Wolf) (Jpn)</description>
<year>1996</year>
- <publisher>Oracion</publisher> <!-- オラシオン -->
+ <publisher>Oracion</publisher> <!-- オラシオン -->
<info name="serial" value="BDS-20007" />
<info name="alt_title" value="MUSIC ISLAND プロコフィエフ ピーターã¨ç‹¼ PETER AND THE WOLF" />
<part name="cdrom" interface="pippin_cdrom">
@@ -574,7 +574,7 @@ NOTE: This list is here only to document available dumps and it's not used (yet)
<software name="music2">
<description>Music Island Vol. 2 (Tchaikovsky The Nutcracker) (Jpn)</description>
<year>1996</year>
- <publisher>Oracion</publisher> <!-- オラシオン -->
+ <publisher>Oracion</publisher> <!-- オラシオン -->
<info name="serial" value="BDS-20027" />
<info name="alt_title" value="MUSIC ISLAND ãƒãƒ£ã‚¤ã‚³ãƒ•ã‚¹ã‚­ãƒ¼ã€€ãã‚‹ã¿ã‚り人形 The Nutcracker" />
<part name="cdrom" interface="pippin_cdrom">
@@ -587,7 +587,7 @@ NOTE: This list is here only to document available dumps and it's not used (yet)
<software name="music3">
<description>Music Island Vol. 3 (Vivaldi The Four Seasons) (Jpn)</description>
<year>1996</year>
- <publisher>Oracion</publisher> <!-- オラシオン -->
+ <publisher>Oracion</publisher> <!-- オラシオン -->
<info name="serial" value="BDS-20028" />
<info name="alt_title" value="MUSIC ISLAND ヴィヴァルディ 四季 The Four Seasons" />
<part name="cdrom" interface="pippin_cdrom">
@@ -600,7 +600,7 @@ NOTE: This list is here only to document available dumps and it's not used (yet)
<software name="music4">
<description>Music Island Vol. 4 (Saint-Saens Carnival of the Animals) (Jpn)</description>
<year>1996</year>
- <publisher>Oracion</publisher> <!-- オラシオン -->
+ <publisher>Oracion</publisher> <!-- オラシオン -->
<info name="serial" value="BDS-20029" />
<info name="alt_title" value="MUSIC ISLAND サン=サーンス 動物ã®è¬è‚‰ç¥­ Carnival of the Animals" />
<part name="cdrom" interface="pippin_cdrom">
@@ -613,7 +613,7 @@ NOTE: This list is here only to document available dumps and it's not used (yet)
<software name="nemuyoru">
<description>Nemurenu Yoru no Chiisana Ohanashi (Jpn)</description>
<year>1996</year>
- <publisher>Amuse</publisher> <!-- アミューズ -->
+ <publisher>Amuse</publisher> <!-- アミューズ -->
<info name="serial" value="BDS-20015" />
<info name="alt_title" value="眠れã¬å¤œã®å°ã•ãªãŠè©±" />
<part name="cdrom" interface="pippin_cdrom">
@@ -809,7 +809,7 @@ NOTE: This list is here only to document available dumps and it's not used (yet)
<software name="seesawc1">
<description>SeesawC 1 - My favorite things - Sukinamonodake Eitango 120 (Jpn)</description>
<year>1996</year>
- <publisher>Aigaareba Daijoubu</publisher> <!-- æ„›ãŒã‚ã‚Œã°å¤§ä¸ˆå¤« -->
+ <publisher>Aigaareba Daijoubu</publisher> <!-- æ„›ãŒã‚ã‚Œã°å¤§ä¸ˆå¤« -->
<info name="serial" value="BDE-10006" />
<info name="alt_title" value="シーソーシー1" />
<part name="cdrom" interface="pippin_cdrom">
@@ -822,7 +822,7 @@ NOTE: This list is here only to document available dumps and it's not used (yet)
<software name="seesawc2">
<description>SeesawC 2 - My favorite places - Sukinatokorode Eitango 400 (Jpn)</description>
<year>1996</year>
- <publisher>Aigaareba Daijoubu</publisher> <!-- æ„›ãŒã‚ã‚Œã°å¤§ä¸ˆå¤« -->
+ <publisher>Aigaareba Daijoubu</publisher> <!-- æ„›ãŒã‚ã‚Œã°å¤§ä¸ˆå¤« -->
<info name="serial" value="BDE-10023" />
<info name="alt_title" value="シーソーシー2" />
<part name="cdrom" interface="pippin_cdrom">
@@ -835,7 +835,7 @@ NOTE: This list is here only to document available dumps and it's not used (yet)
<software name="shichiso">
<description>Shichisokusen (Jpn)</description>
<year>1996</year>
- <publisher>Media Five</publisher> <!-- メディアファイブ -->
+ <publisher>Media Five</publisher> <!-- メディアファイブ -->
<info name="serial" value="BDS-20019" />
<info name="alt_title" value="死地則戦 ビジãƒã‚¹ã‚¨ãƒ‡ãƒ¥ãƒ†ã‚¤ãƒ¡ãƒ³ãƒˆã‚½ãƒ•ãƒˆ" />
<part name="cdrom" interface="pippin_cdrom">
@@ -885,7 +885,7 @@ NOTE: This list is here only to document available dumps and it's not used (yet)
<software name="tbreak">
<description>T-Break (Jpn)</description>
<year>1996</year>
- <publisher>Infocity</publisher> <!-- インフォシティ -->
+ <publisher>Infocity</publisher> <!-- インフォシティ -->
<info name="serial" value="BDS-20026" />
<info name="alt_title" value="ティ・ブレイク" />
<part name="cdrom" interface="pippin_cdrom">
@@ -912,7 +912,7 @@ NOTE: This list is here only to document available dumps and it's not used (yet)
<software name="tropicis">
<description>Tropic Island (Jpn)</description>
<year>1996</year>
- <publisher>Momoderazu Brand</publisher> <!-- モモデラーズブランド -->
+ <publisher>Momoderazu Brand</publisher> <!-- モモデラーズブランド -->
<info name="serial" value="BDS-20011" />
<info name="alt_title" value="トロピック アイランド" />
<part name="cdrom" interface="pippin_cdrom">
@@ -1069,7 +1069,7 @@ NOTE: This list is here only to document available dumps and it's not used (yet)
<software name="yellow1">
<description>Yellow Brick Road I (Jpn)</description>
<year>1996</year>
- <publisher>Synergy Ikunangaku</publisher> <!-- シナジー幾何学 -->
+ <publisher>Synergy Ikunangaku</publisher> <!-- シナジー幾何学 -->
<info name="serial" value="BDS-20022" />
<info name="alt_title" value="イエロー・ブリック・ロード I" />
<part name="cdrom" interface="pippin_cdrom">
@@ -1082,7 +1082,7 @@ NOTE: This list is here only to document available dumps and it's not used (yet)
<software name="yellow2">
<description>Yellow Brick Road II - Glinda to Nishi no Majo (Jpn)</description>
<year>1996</year>
- <publisher>Synergy Ikunangaku</publisher> <!-- シナジー幾何学 -->
+ <publisher>Synergy Ikunangaku</publisher> <!-- シナジー幾何学 -->
<info name="serial" value="BDS-20023" />
<info name="alt_title" value="イエロー・ブリック・ロード II グリンダã¨è¥¿ã®é­”女" />
<part name="cdrom1" interface="scd_cdrom">
@@ -1102,7 +1102,7 @@ NOTE: This list is here only to document available dumps and it's not used (yet)
<software name="yellows">
<description>Yellows - Akira Gomi Photographs (Jpn)</description>
<year>1996</year>
- <publisher>Digitalogue</publisher> <!-- デジタローグ -->
+ <publisher>Digitalogue</publisher> <!-- デジタローグ -->
<info name="serial" value="BDS-20001" />
<part name="cdrom" interface="pippin_cdrom">
<diskarea name="cdrom">
@@ -1114,7 +1114,7 @@ NOTE: This list is here only to document available dumps and it's not used (yet)
<software name="yellws2">
<description>Yellows 2.0 - Tokyo 1993 Akira Gomi Photographs (Jpn)</description>
<year>1996</year>
- <publisher>Digitalogue</publisher> <!-- デジタローグ -->
+ <publisher>Digitalogue</publisher> <!-- デジタローグ -->
<info name="serial" value="BDS-20002" />
<info name="alt_title" value="イエローズ 2.0" />
<part name="cdrom" interface="pippin_cdrom">
@@ -1127,7 +1127,7 @@ NOTE: This list is here only to document available dumps and it's not used (yet)
<software name="yokumite">
<description>Yoku Mite Goran! (Jpn)</description>
<year>1996</year>
- <publisher>Voyager</publisher> <!-- ボイジャー -->
+ <publisher>Voyager</publisher> <!-- ボイジャー -->
<info name="serial" value="BDS-20018" />
<info name="alt_title" value="よã見ã¦ã”らんï¼ç¾Žè¡“館ã¸è¡Œã“ã†" />
<part name="cdrom" interface="pippin_cdrom">
diff --git a/hash/pofo.xml b/hash/pofo.xml
index 3255a1aaaba..e12a0b04cdc 100644
--- a/hash/pofo.xml
+++ b/hash/pofo.xml
@@ -21,8 +21,8 @@
Undumped 3rd party cartridges:
- Adcalc AAC-1000
- Alpha Paging Interface SAMpage
+ Adcalc AAC-1000
+ Alpha Paging Interface SAMpage
Business Contacts and Information Manager BCIM
Checkwriter
Colossal Cave Adventure
diff --git a/hash/snes.xml b/hash/snes.xml
index 8f4b5efaafd..056e738dd60 100644
--- a/hash/snes.xml
+++ b/hash/snes.xml
@@ -1357,7 +1357,7 @@ Beyond that last category are the roms waiting to be classified.
<feature name="u1" value="U1 EPROM" />
<feature name="u2" value="U2 EPROM" />
<feature name="u3" value="U3 EPROM" />
- <feature name="u4" value="U4 EPROM" /> <!-- empty socket -->
+ <feature name="u4" value="U4 EPROM" /> <!-- empty socket -->
<feature name="u5" value="U5 SRAM" />
<feature name="u6" value="U6 PLD" />
<feature name="u7" value="U7 74LS157" />
@@ -34238,7 +34238,7 @@ List of unclassified roms
</dataarea>
</part>
</software>
-
+
<software name="arabianp" cloneof="arabian">
<description>Arabian Nights - Sabaku no Seirei Ou (Jpn, Prototype)</description>
<year>1996</year>
@@ -37664,7 +37664,7 @@ List of unclassified roms
</dataarea>
</part>
</software>
-
+
<software name="downwrldd" cloneof="downwrld">
<description>Down the World - Mervil's Ambition (Jpn, Rolling Demo)</description>
<year>1994</year>
@@ -40283,7 +40283,7 @@ List of unclassified roms
</dataarea>
</part>
</software>
-
+
<software name="ganpurup" cloneof="ganpuru">
<description>Ganpuru - Gunman's Proof (Jpn, Prototype)</description>
<year>1997</year>
@@ -61015,7 +61015,7 @@ to ensure nothing has been touched in the Retro Quest cart production in 2013/20
</dataarea>
</part>
</software>
-
+
<software name="tougedenp" cloneof="tougeden">
<description>Touge Densetsu - Saisoku Battle (Jpn, Prototype)</description>
<year>1996</year>
@@ -61911,7 +61911,7 @@ to ensure nothing has been touched in the Retro Quest cart production in 2013/20
</dataarea>
</part>
</software>
-
+
<software name="umizurimp" cloneof="umizurim">
<description>Umizuri Meijin - Suzuki Hen (Jpn, Prototype)</description>
<year>1994</year>
diff --git a/hash/vsmile_cart.xml b/hash/vsmile_cart.xml
index a5d13ac1ac3..fea4e6a5dda 100644
--- a/hash/vsmile_cart.xml
+++ b/hash/vsmile_cart.xml
@@ -901,7 +901,7 @@ V.Baby (NOT V.Smile Baby)
</dataarea>
</part>
</software>
-
+
<software name="cinderlaa" cloneof="cinderla" supported="no">
<description>Cinderella - Cinderella's Magic Wishes (USA, Alt)</description>
<year>200?</year>
@@ -912,7 +912,7 @@ V.Baby (NOT V.Smile Baby)
</dataarea>
</part>
</software>
-
+
<software name="cinderlaf" cloneof="cinderla" supported="no">
<description>Cendrillon - Le Rêve Enchanté de Cendrillon (Fra)</description>
<year>200?</year>
@@ -1056,7 +1056,7 @@ V.Baby (NOT V.Smile Baby)
</dataarea>
</part>
</software>
-
+
<software name="kleinstn" supported="no">
<description>Kleine Einsteins (Ger)</description>
<year>200?</year>
@@ -1122,7 +1122,7 @@ V.Baby (NOT V.Smile Baby)
</dataarea>
</part>
</software>
-
+
<software name="mickymag" supported="no">
<description>Disney's Mickey Mouse - Mickey's Magical Adventure (USA)</description>
<year>200?</year>
@@ -1342,7 +1342,7 @@ V.Baby (NOT V.Smile Baby)
</dataarea>
</part>
</software>
-
+
<software name="shrekf" cloneof="shrek" supported="no">
<description>Shrek - Le Rhume de Dragonne (Fra)</description>
<year>200?</year>
@@ -1463,7 +1463,7 @@ V.Baby (NOT V.Smile Baby)
</dataarea>
</part>
</software>
-
+
<software name="tingelng" supported="no">
<description>Tingeling (Swe)</description>
<year>200?</year>
@@ -1474,7 +1474,7 @@ V.Baby (NOT V.Smile Baby)
</dataarea>
</part>
</software>
-
+
<software name="toystor2" supported="no">
<description>Toy Story 2 - Operation: Rescue Woody! (USA)</description>
<year>2005</year>
@@ -1540,7 +1540,7 @@ V.Baby (NOT V.Smile Baby)
</dataarea>
</part>
</software>
-
+
<software name="pooh1" cloneof="pooh" supported="no">
<description>My Friends Tigger &amp; Pooh - Die Honigjagd (Ger)</description>
<year>200?</year>
@@ -1617,7 +1617,7 @@ V.Baby (NOT V.Smile Baby)
</dataarea>
</part>
</software>
-
+
<software name="zayzoo" supported="no">
<description>Zayzoo - My Alien Classmate (USA)</description>
<year>200?</year>
@@ -1665,7 +1665,7 @@ V.Baby (NOT V.Smile Baby)
</dataarea>
</part>
</software>
-
+
<software name="poohhawa" supported="no">
<description>Pooh's Hundred Acre Wood Adventure (USA) (V.Smile Baby)</description>
<year>2007</year>
@@ -1713,7 +1713,7 @@ V.Baby (NOT V.Smile Baby)
</dataarea>
</part>
</software>
-
+
<software name="kleinsvm" supported="no">
<description>Kleine Einsteins (Ger) (V.Smile Motion)</description>
<year>200?</year>
diff --git a/hash/vsmile_cd.xml b/hash/vsmile_cd.xml
index e079d2b8543..adc7d683f47 100644
--- a/hash/vsmile_cd.xml
+++ b/hash/vsmile_cd.xml
@@ -117,7 +117,7 @@ Language:
</diskarea>
</part>
</software>
-
+
<software name="bratz" supported="no">
<!--
Original files:
@@ -135,7 +135,7 @@ Language:
</diskarea>
</part>
</software>
-
+
<software name="cars" supported="no">
<!--
Original files:
@@ -153,7 +153,7 @@ Language:
</diskarea>
</part>
</software>
-
+
<software name="carsg" cloneof="cars" supported="no">
<!--
Original files (from TeamEurope)
@@ -170,7 +170,7 @@ Language:
</diskarea>
</part>
</software>
-
+
<software name="princess" supported="no">
<!--
Original files:
@@ -188,7 +188,7 @@ Language:
</diskarea>
</part>
</software>
-
+
<software name="princessg" cloneof="princess" supported="no">
<!--
Original files (from TeamEurope)
@@ -225,7 +225,7 @@ Language:
</diskarea>
</part>
</software>
-
+
<software name="incredibg" cloneof="incredib" supported="no">
<!--
Original files (from TeamEurope)
@@ -242,7 +242,7 @@ Language:
</diskarea>
</part>
</software>
-
+
<software name="msportg" supported="no">
<!--
Original files (from TeamEurope)
@@ -279,7 +279,7 @@ Language:
</diskarea>
</part>
</software>
-
+
<software name="shrek3" supported="no">
<!--
Original files:
@@ -297,7 +297,7 @@ Language:
</diskarea>
</part>
</software>
-
+
<software name="shrek3g" cloneof="shrek3" supported="no">
<!--
Original files (from TeamEurope)
@@ -314,7 +314,7 @@ Language:
</diskarea>
</part>
</software>
-
+
<software name="spongeis" supported="no">
<!--
Original files:
@@ -349,7 +349,7 @@ Language:
</diskarea>
</part>
</software>
-
+
<!-- disk mounted as 93120_003 -->
<software name="wackyrac" supported="no">
<!--
diff --git a/makefile b/makefile
index ecb7995e7fa..d3c8c1d6a17 100644
--- a/makefile
+++ b/makefile
@@ -1486,14 +1486,14 @@ endif
ifeq (posix,$(SHELLTYPE))
$(GENDIR)/version.cpp: $(GENDIR)/git_desc | $(GEN_FOLDERS)
- @echo '#define BARE_BUILD_VERSION "0.174"' > $@
+ @echo '#define BARE_BUILD_VERSION "0.175"' > $@
@echo 'extern const char bare_build_version[];' >> $@
@echo 'extern const char build_version[];' >> $@
@echo 'const char bare_build_version[] = BARE_BUILD_VERSION;' >> $@
@echo 'const char build_version[] = BARE_BUILD_VERSION " ($(NEW_GIT_VERSION))";' >> $@
else
$(GENDIR)/version.cpp: $(GENDIR)/git_desc
- @echo #define BARE_BUILD_VERSION "0.174" > $@
+ @echo #define BARE_BUILD_VERSION "0.175" > $@
@echo extern const char bare_build_version[]; >> $@
@echo extern const char build_version[]; >> $@
@echo const char bare_build_version[] = BARE_BUILD_VERSION; >> $@
diff --git a/src/devices/bus/electron/exp.cpp b/src/devices/bus/electron/exp.cpp
index b13f6534002..ced8056d2eb 100644
--- a/src/devices/bus/electron/exp.cpp
+++ b/src/devices/bus/electron/exp.cpp
@@ -2,7 +2,7 @@
// copyright-holders:Nigel Barnes
/**********************************************************************
- Electron Expansion Port emulation
+ Electron Expansion Port emulation
**********************************************************************/
diff --git a/src/devices/bus/electron/exp.h b/src/devices/bus/electron/exp.h
index cfcb7478a10..2f59faec38a 100644
--- a/src/devices/bus/electron/exp.h
+++ b/src/devices/bus/electron/exp.h
@@ -2,84 +2,84 @@
// copyright-holders:Nigel Barnes
/**********************************************************************
- Electron Expansion Port emulation
+ Electron Expansion Port emulation
**********************************************************************
- Pinout:
-
- 18V AC 2 1 18V AC
- AC RETURN 4 3 AC RETURN
- -5V 6 5 -5V
- 0V 8 7 0V
- +5V 10 9 +5V
- 16MHz 12 11 SOUND O/P
- PHI OUT 14 13 ÷13 IN
- NMI 16 15 RST
- R/W 18 17 IRQ
- D6 20 19 D7
- D4 22 21 D5
- D2 24 23 D3
- D0 26 25 D1
- NC 28 27 RDY
- SLOT 30 29 SLOT
- A14 32 31 A15
- A12 34 33 A13
- A10 36 35 A11
- A0 38 37 A9
- A2 40 39 A1
- A4 42 41 A3
- A6 44 43 A5
- A8 46 45 A7
- 0V 48 47 0V
- +5V 50 49 +5V
-
- Signal Definitions:
-
- 18V AC (pins 1,2) - These lines are connected directly to the output from the Electron mains power
+ Pinout:
+
+ 18V AC 2 1 18V AC
+ AC RETURN 4 3 AC RETURN
+ -5V 6 5 -5V
+ 0V 8 7 0V
+ +5V 10 9 +5V
+ 16MHz 12 11 SOUND O/P
+ PHI OUT 14 13 13 IN
+ NMI 16 15 RST
+ R/W 18 17 IRQ
+ D6 20 19 D7
+ D4 22 21 D5
+ D2 24 23 D3
+ D0 26 25 D1
+ NC 28 27 RDY
+ SLOT 30 29 SLOT
+ A14 32 31 A15
+ A12 34 33 A13
+ A10 36 35 A11
+ A0 38 37 A9
+ A2 40 39 A1
+ A4 42 41 A3
+ A6 44 43 A5
+ A8 46 45 A7
+ 0V 48 47 0V
+ +5V 50 49 +5V
+
+ Signal Definitions:
+
+ 18V AC (pins 1,2) - These lines are connected directly to the output from the Electron mains power
AC RETURNS (pins 3,4) - adaptor. A total of 6W may be drawn from these lines as long as no power is
- taken from +5V (pins 9,10,49,50). For safety reasons these lines must never
- be used as an AC input to the Electron.
- -5V (pins 5,6) - A -5V supply from the Electron. Up to 20mA (total) may safely be drawn
- from this line by expansion modules.
- 0V (pins 7,8,47,48) - Ground. Expansion modules with their own power supply must have the 0V
- lines commoned with the Electron.
+ taken from +5V (pins 9,10,49,50). For safety reasons these lines must never
+ be used as an AC input to the Electron.
+ -5V (pins 5,6) - A -5V supply from the Electron. Up to 20mA (total) may safely be drawn
+ from this line by expansion modules.
+ 0V (pins 7,8,47,48) - Ground. Expansion modules with their own power supply must have the 0V
+ lines commoned with the Electron.
+5V (pins 9,10,49,50) - A +5V supply from the Electron. Up to 500mA (total) may safely be drawn
- from this line by expansion modules as long as no power is taken from 18V
- AC (pins 1,2,3,4).
- SOUND O/P (pin 11) - Sound output. A 3V peak to peak source via a 1K series resistor from the
- Electron ULA.
- 16 MHz (pin 12) - 16 Megahertz from the Electron main oscillator. This output may be used
- for clock generation within an expansion module.
- /13 IN (pin 13) - 16 Megahertz divided by 13. This output may be used for baud rate
- generation. If divided by 1024 it will give approximately 1200Hz.
- PHI OUT (pin 14) - The 6502 input clock. The low time is nominally 250ns. The high time may
- be 250ns (2MHz operation when reading ROMs) or 750ns or 1250ns
- (stretched clock for a 1MHz access, the length depending on the phase of the
- 2MHz clock) or up to 40us (if in modes 0-3)
- RST (pin 15) - Reset (active low). This is an OUTPUT ONLY for the system reset line. It
- may be used to initialise expansion modules on power up and when the
- BREAK key is pressed.
- NMI (pin 16) - Non-Maskable Interrupt (negative edge triggered). This is the system NMI
- line which is open collector (wire-OR) and may be asserted by an expansion
- module. The pull-up resistor on this line inside the ULA is 3k3. Care must
- be taken to avoid masking other interrupts by holding the line low. Using
- NMI on the Electron requires knowledge of operating system protocols.
- IRQ (pin 17) - Interrupt Request (active low). This is the system IRQ line which is open
- collector (wire-OR) and may be asserted by an expansion module. The pull-
- up resistor on this line inside the ULA is 3k3. It is essential for the correct
- operation of the machine that interrupts to not occur until the software is
- capable of dealing with them. Interrupts on the Electron expansion bus should
- therefore be disabled on power-up and reset. Significant use of interrupt
- service time may affect other machine functions, eg the real time clock.
- R/W (pin 18) - The system read/write line from the 6502.
- D7-D0 (pins 19-26) - Bi-directional data bus. The direction of data is determined by R/W.
- RDY (pin 27) - 6502 ready line (active low). May be asserted by an expansion module to
- stop the processor when reading slow memory. This line works on read only
- (R/W=1).
- (pin 28) - No connection
- (pins 29,30) - Polarising key connector.
- A0-A15 (pins 31-46) - 6502 address bus.
+ from this line by expansion modules as long as no power is taken from 18V
+ AC (pins 1,2,3,4).
+ SOUND O/P (pin 11) - Sound output. A 3V peak to peak source via a 1K series resistor from the
+ Electron ULA.
+ 16 MHz (pin 12) - 16 Megahertz from the Electron main oscillator. This output may be used
+ for clock generation within an expansion module.
+ /13 IN (pin 13) - 16 Megahertz divided by 13. This output may be used for baud rate
+ generation. If divided by 1024 it will give approximately 1200Hz.
+ PHI OUT (pin 14) - The 6502 input clock. The low time is nominally 250ns. The high time may
+ be 250ns (2MHz operation when reading ROMs) or 750ns or 1250ns
+ (stretched clock for a 1MHz access, the length depending on the phase of the
+ 2MHz clock) or up to 40us (if in modes 0-3)
+ RST (pin 15) - Reset (active low). This is an OUTPUT ONLY for the system reset line. It
+ may be used to initialise expansion modules on power up and when the
+ BREAK key is pressed.
+ NMI (pin 16) - Non-Maskable Interrupt (negative edge triggered). This is the system NMI
+ line which is open collector (wire-OR) and may be asserted by an expansion
+ module. The pull-up resistor on this line inside the ULA is 3k3. Care must
+ be taken to avoid masking other interrupts by holding the line low. Using
+ NMI on the Electron requires knowledge of operating system protocols.
+ IRQ (pin 17) - Interrupt Request (active low). This is the system IRQ line which is open
+ collector (wire-OR) and may be asserted by an expansion module. The pull-
+ up resistor on this line inside the ULA is 3k3. It is essential for the correct
+ operation of the machine that interrupts to not occur until the software is
+ capable of dealing with them. Interrupts on the Electron expansion bus should
+ therefore be disabled on power-up and reset. Significant use of interrupt
+ service time may affect other machine functions, eg the real time clock.
+ R/W (pin 18) - The system read/write line from the 6502.
+ D7-D0 (pins 19-26) - Bi-directional data bus. The direction of data is determined by R/W.
+ RDY (pin 27) - 6502 ready line (active low). May be asserted by an expansion module to
+ stop the processor when reading slow memory. This line works on read only
+ (R/W=1).
+ (pin 28) - No connection
+ (pins 29,30) - Polarising key connector.
+ A0-A15 (pins 31-46) - 6502 address bus.
**********************************************************************/
diff --git a/src/devices/bus/gameboy/mbc.cpp b/src/devices/bus/gameboy/mbc.cpp
index 3192bcda9ce..cf5a6f44a98 100644
--- a/src/devices/bus/gameboy/mbc.cpp
+++ b/src/devices/bus/gameboy/mbc.cpp
@@ -452,7 +452,7 @@ void gb_rom_mbc3_device::update_rtc()
{
system_time curtime;
machine().current_datetime(curtime);
-
+
m_rtc_regs[0] = curtime.local_time.second;
m_rtc_regs[1] = curtime.local_time.minute;
m_rtc_regs[2] = curtime.local_time.hour;
@@ -700,7 +700,7 @@ WRITE8_MEMBER(gb_rom_m161_device::write_bank)
{
// the mapper (74HC161A) only has data lines D2..D0
data &= 0x07;
-
+
// A15 is connected to #LOAD and overwritten by QD (m_load_disable)
switch (offset & 0x8000)
{
@@ -719,31 +719,30 @@ WRITE8_MEMBER(gb_rom_m161_device::write_bank)
READ8_MEMBER(gb_rom_mmm01_device::read_rom)
{
-
UINT16 romb = m_romb & ~m_romb_nwe;
UINT16 romb_base = m_romb & (0x1e0 | m_romb_nwe);
UINT8 ramb_masked = ((offset & 0x4000) | m_mode ? m_ramb : m_ramb & ~0x03);
-
+
// zero-adjust RA18..RA14
romb = (romb ? romb : 0x01);
// if unmapped, force
romb = (m_map ? romb : 0x01);
-
+
// RB 0 logic
if (!(offset & 0x4000))
romb = 0x00;
-
+
// combine with base
romb |= romb_base;
-
+
// multiplex with AA14..AA13
if (m_mux)
romb = (romb & ~0x60) | ((ramb_masked & 0x03) << 5);
-
+
// if unmapped, force
if (!m_map)
romb |= 0x1fe;
-
+
return m_rom[rom_bank_map[romb] * 0x4000 + (offset & 0x3fff)];
}
@@ -751,7 +750,7 @@ WRITE8_MEMBER(gb_rom_mmm01_device::write_bank)
{
// the mapper only has data lines D6..D0
data &= 0x7f;
-
+
// the mapper only uses inputs A15..A13
switch (offset & 0xe000)
{
@@ -765,7 +764,7 @@ WRITE8_MEMBER(gb_rom_mmm01_device::write_bank)
case 0x2000: // RA20..RA19 RA18..RA14
if (!m_map)
m_romb = (m_romb & ~0x60) | (data & 0x60);
-
+
m_romb = (m_romb & (~0x1f | m_romb_nwe)) | (data & (0x1f & ~m_romb_nwe));
break;
case 0x4000: // Mode #WE, RA22..RA21, AA16..AA15, AA14..AA13
@@ -774,7 +773,7 @@ WRITE8_MEMBER(gb_rom_mmm01_device::write_bank)
m_romb = (m_romb & ~0x180) | ((data & 0x30) << 3);
m_ramb = (m_ramb & ~0x0c) | (data & 0x0c);
}
-
+
m_ramb = (m_ramb & (~0x03 | m_ramb_nwe)) | (data & (0x03 & ~m_ramb_nwe));
break;
case 0x6000: // Mux, RA18..RA15 #WE/Mask, ???, MBC1 Mode
@@ -783,7 +782,7 @@ WRITE8_MEMBER(gb_rom_mmm01_device::write_bank)
// m_romb_nwe is aligned to RA14, hence >> 1 instead of >> 2
m_romb_nwe = (data & 0x3c) >> 1;
}
-
+
if (!m_mode_nwe)
m_mode = data & 0x01;
break;
@@ -796,11 +795,11 @@ READ8_MEMBER(gb_rom_mmm01_device::read_ram)
{
UINT8 ramb_masked = ((offset & 0x4000) | m_mode ? m_ramb : m_ramb & ~0x03);
UINT8 ramb = ramb_masked;
-
+
// multiplex with RA20..RA19
if (m_mux)
ramb = (ramb & ~0x03) | ((m_romb & 0x60) >> 5);
-
+
if (!m_ram.empty() && m_ram_enable)
{
return m_ram[ram_bank_map[ramb] * 0x2000 + (offset & 0x1fff)];
@@ -813,11 +812,11 @@ WRITE8_MEMBER(gb_rom_mmm01_device::write_ram)
{
UINT8 ramb_masked = ((offset & 0x4000) | m_mode ? m_ramb : m_ramb & ~0x03);
UINT8 ramb = ramb_masked;
-
+
// multiplex with RA20..RA19
if (m_mux)
ramb = (ramb & ~0x03) | ((m_romb & 0x60) >> 5);
-
+
if (!m_ram.empty() && m_ram_enable)
{
m_ram[ram_bank_map[ramb] * 0x2000 + (offset & 0x1fff)] = data;
diff --git a/src/devices/bus/gameboy/mbc.h b/src/devices/bus/gameboy/mbc.h
index 1dcc43875bd..827d42c392d 100644
--- a/src/devices/bus/gameboy/mbc.h
+++ b/src/devices/bus/gameboy/mbc.h
@@ -195,7 +195,7 @@ public:
virtual DECLARE_WRITE8_MEMBER(write_bank) override;
virtual DECLARE_READ8_MEMBER(read_ram) override;
virtual DECLARE_WRITE8_MEMBER(write_ram) override;
-
+
UINT16 m_romb;
UINT8 m_romb_nwe;
UINT8 m_ramb;
diff --git a/src/devices/bus/gba/gba_slot.h b/src/devices/bus/gba/gba_slot.h
index 03b9ca4f653..62c25bc6674 100644
--- a/src/devices/bus/gba/gba_slot.h
+++ b/src/devices/bus/gba/gba_slot.h
@@ -607,7 +607,7 @@ static const gba_chip_fix_item gba_chip_fix_rumble_list[] =
{ "KYGP" }, // Yoshi's Universal Gravitation (EUR)
{ "KYGE" }, // Yoshi - Topsy-Turvy (USA)
{ "KYGJ" }, // Yoshi no Banyuuinryoku (JPN)
- { "KHPJ" } // Koro Koro Puzzle - Happy Panechu! (JPN)
+ { "KHPJ" } // Koro Koro Puzzle - Happy Panechu! (JPN)
};
diff --git a/src/devices/bus/gba/rom.cpp b/src/devices/bus/gba/rom.cpp
index 5fc4798f1d7..4f10bbb0733 100644
--- a/src/devices/bus/gba/rom.cpp
+++ b/src/devices/bus/gba/rom.cpp
@@ -268,7 +268,7 @@ void gba_rom_3dmatrix_device::device_reset()
This is a preliminary implementation of the
General Purpose I/O Port embedded in the GBA PCBs
as described at : http://problemkaputt.de/gbatek.htm#gbacartioportgpio
-
+
Functions read_gpio/write_gpio only give the
I/O interface while the actual on-cart devices
are read and written through gpio_dev_read/gpio_dev_write
@@ -400,7 +400,7 @@ void gba_rom_wariotws_device::gpio_dev_write(UINT16 data, int gpio_dirs)
if (data & 1)
m_counter = 15;
-
+
m_last_val = data & 0x0b;
}
}
@@ -586,19 +586,19 @@ WRITE32_MEMBER(gba_rom_eeprom64_device::write_ram)
/*-------------------------------------------------
Carts with EEPROM + Tilt Sensor
-
- Note about the calibration: this can seem a bit
+
+ Note about the calibration: this can seem a bit
tricky at first, because the emulated screen
does not turn as the GBA would...
In order to properly calibrate the sensor, just
keep pressed right for a few seconds when requested
- to calibrate right inclination (first calibration
- screen in Yoshi Universal Gravitation) so to get the
- full right range; then keep pressed for left for a
+ to calibrate right inclination (first calibration
+ screen in Yoshi Universal Gravitation) so to get the
+ full right range; then keep pressed for left for a
few seconds when requested to calibrate left
- inclination (second calibration screen in Yoshi
+ inclination (second calibration screen in Yoshi
Universal Gravitation) so to get the full left range
-
+
-------------------------------------------------*/
static INPUT_PORTS_START( yoshiug_tilt )
@@ -700,14 +700,14 @@ void gba_rom_boktai_device::gpio_dev_write(UINT16 data, int gpio_dirs)
{
if (data & 2)
m_counter = 0;
-
+
if ((data & 1) && !(m_last_val & 1))
{
m_counter++;
if (m_counter == 0x100)
m_counter = 0;
}
-
+
m_last_val = data & 7;
}
}
@@ -775,7 +775,7 @@ WRITE32_MEMBER(gba_rom_3dmatrix_device::write_mapper)
/*-------------------------------------------------
Seiko S-3511 RTC implementation
-
+
TODO: transform this into a separate device, using
also dirtc.cpp!
-------------------------------------------------*/
@@ -789,7 +789,7 @@ gba_s3511_device::gba_s3511_device(running_machine &machine) :
m_command = 0;
m_data_len = 1;
m_data[0] = 0;
-
+
m_machine.save().save_item(m_phase, "GBA_RTC/m_phase");
m_machine.save().save_item(m_data, "GBA_RTC/m_data");
m_machine.save().save_item(m_last_val, "GBA_RTC/m_last_val");
@@ -808,7 +808,7 @@ void gba_s3511_device::update_time(int len)
{
system_time curtime;
m_machine.current_datetime(curtime);
-
+
if (len == 7)
{
m_data[0] = convert_to_bcd(curtime.local_time.year);
@@ -840,7 +840,7 @@ int gba_s3511_device::read_line()
if (m_bits == 8 * m_data_len)
{
//for (int i = 0; i < m_data_len; i++)
- // printf("RTC DATA OUT COMPLETE %X (reg %d) \n", m_data[i], i);
+ // printf("RTC DATA OUT COMPLETE %X (reg %d) \n", m_data[i], i);
m_bits = 0;
m_phase = S3511_RTC_IDLE;
}
@@ -852,7 +852,7 @@ int gba_s3511_device::read_line()
void gba_s3511_device::write(UINT16 data, int gpio_dirs)
{
-// printf("gpio_dev_write data %X\n", data);
+// printf("gpio_dev_write data %X\n", data);
if (m_phase == S3511_RTC_IDLE && (m_last_val & 5) == 1 && (data & 5) == 5)
{
m_phase = S3511_RTC_COMMAND;
@@ -861,8 +861,8 @@ void gba_s3511_device::write(UINT16 data, int gpio_dirs)
}
else
{
-// if (m_phase == 3)
-// printf("RTC command OK\n");
+// if (m_phase == 3)
+// printf("RTC command OK\n");
if (!(m_last_val & 1) && (data & 1))
{
// bit transfer
@@ -877,7 +877,7 @@ void gba_s3511_device::write(UINT16 data, int gpio_dirs)
if (m_bits == 8 * m_data_len)
{
//for (int i = 0; i < m_data_len; i++)
- // printf("RTC DATA IN COMPLETE %X (reg %d) \n", m_data[i], i);
+ // printf("RTC DATA IN COMPLETE %X (reg %d) \n", m_data[i], i);
m_bits = 0;
m_phase = S3511_RTC_IDLE;
}
@@ -940,7 +940,7 @@ void gba_s3511_device::write(UINT16 data, int gpio_dirs)
/*-------------------------------------------------
GBA EEPROM Device
-
+
TODO: can this sketchy EEPROM device be merged
with the core implementation?
-------------------------------------------------*/
@@ -954,7 +954,7 @@ gba_eeprom_device::gba_eeprom_device(running_machine &machine, UINT8 *eeprom, UI
m_data = eeprom;
m_data_size = size;
m_addr_bits = addr_bits;
-
+
m_machine.save().save_item(m_state, "GBA_EEPROM/m_state");
m_machine.save().save_item(m_command, "GBA_EEPROM/m_command");
m_machine.save().save_item(m_count, "GBA_EEPROM/m_count");
@@ -966,16 +966,16 @@ gba_eeprom_device::gba_eeprom_device(running_machine &machine, UINT8 *eeprom, UI
UINT32 gba_eeprom_device::read()
{
UINT32 out;
-
+
switch (m_state)
{
case EEP_IDLE:
// printf("eeprom_r: @ %x, mask %08x (state %d) (PC=%x) = %d\n", offset, ~mem_mask, m_state, activecpu_get_pc(), 1);
return 0x00010001; // "ready"
-
+
case EEP_READFIRST:
m_count--;
-
+
if (!m_count)
{
m_count = 64;
@@ -996,19 +996,19 @@ UINT32 gba_eeprom_device::read()
m_addr++;
m_bits = 8;
}
-
+
out = (m_eep_data & 0x80) ? 1 : 0;
out |= (out<<16);
m_eep_data <<= 1;
-
+
m_bits--;
m_count--;
-
+
if (!m_count)
{
m_state = EEP_IDLE;
}
-
+
// printf("out = %08x\n", out);
// printf("eeprom_r: @ %x, mask %08x (state %d) (PC=%x) = %08x\n", offset, ~mem_mask, m_state, activecpu_get_pc(), out);
return out;
@@ -1026,7 +1026,7 @@ void gba_eeprom_device::write(UINT32 data)
if (data == 1)
m_state++;
break;
-
+
case EEP_COMMAND:
if (data == 1)
m_command = EEP_READFIRST;
@@ -1036,7 +1036,7 @@ void gba_eeprom_device::write(UINT32 data)
m_count = m_addr_bits;
m_addr = 0;
break;
-
+
case EEP_ADDR:
m_addr <<= 1;
m_addr |= (data & 1);
@@ -1055,7 +1055,7 @@ void gba_eeprom_device::write(UINT32 data)
}
}
break;
-
+
case EEP_AFTERADDR:
m_state = m_command;
m_count = 64;
@@ -1064,32 +1064,31 @@ void gba_eeprom_device::write(UINT32 data)
if (m_state == EEP_READFIRST)
m_count = 4;
break;
-
+
case EEP_WRITE:
m_eep_data <<= 1;
m_eep_data |= (data & 1);
m_bits--;
m_count--;
-
+
if (m_bits == 0)
{
osd_printf_verbose("%08x: EEPROM: %02x to %x\n", machine().device("maincpu")->safe_pc(), m_eep_data, m_addr);
if (m_addr >= m_data_size)
fatalerror("eeprom: invalid address (%x)\n", m_addr);
-
+
m_data[m_addr] = m_eep_data;
m_addr++;
m_eep_data = 0;
m_bits = 8;
}
-
+
if (!m_count)
m_state = EEP_AFTERWRITE;
break;
-
+
case EEP_AFTERWRITE:
m_state = EEP_IDLE;
break;
}
}
-
diff --git a/src/devices/bus/gba/rom.h b/src/devices/bus/gba/rom.h
index 4a1850c5fa2..13a69c44a65 100644
--- a/src/devices/bus/gba/rom.h
+++ b/src/devices/bus/gba/rom.h
@@ -20,19 +20,19 @@ class gba_s3511_device
public:
gba_s3511_device(running_machine &machine);
running_machine &machine() const { return m_machine; }
-
+
void update_time(int len);
UINT8 convert_to_bcd(int val);
-
+
int read_line();
void write(UINT16 data, int gpio_dirs);
-
+
protected:
int m_phase;
UINT8 m_last_val, m_bits, m_command;
int m_data_len;
UINT8 m_data[7];
-
+
running_machine& m_machine;
};
@@ -58,10 +58,10 @@ class gba_eeprom_device
public:
gba_eeprom_device(running_machine &machine, UINT8 *eeprom, UINT32 size, int addr_bits);
running_machine &machine() const { return m_machine; }
-
+
UINT32 read();
void write(UINT32 data);
-
+
protected:
UINT8 *m_data;
UINT32 m_data_size;
@@ -72,7 +72,7 @@ protected:
int m_bits;
int m_addr_bits;
UINT8 m_eep_data;
-
+
running_machine& m_machine;
};
@@ -97,7 +97,7 @@ public:
virtual DECLARE_READ32_MEMBER(read_gpio) override;
virtual DECLARE_WRITE32_MEMBER(write_gpio) override;
-
+
virtual UINT16 gpio_dev_read(int gpio_dirs) { return 0; }
virtual void gpio_dev_write(UINT16 data, int gpio_dirs) {}
@@ -129,7 +129,7 @@ class gba_rom_drilldoz_device : public gba_rom_sram_device
public:
// construction/destruction
gba_rom_drilldoz_device(const machine_config &mconfig, const char *tag, device_t *owner, UINT32 clock);
-
+
// device-level overrides
virtual void gpio_dev_write(UINT16 data, int gpio_dirs) override;
};
@@ -190,12 +190,12 @@ class gba_rom_flash_rtc_device : public gba_rom_flash_device
public:
// construction/destruction
gba_rom_flash_rtc_device(const machine_config &mconfig, const char *tag, device_t *owner, UINT32 clock);
-
+
// device-level overrides
virtual void device_start() override;
virtual UINT16 gpio_dev_read(int gpio_dirs) override;
virtual void gpio_dev_write(UINT16 data, int gpio_dirs) override;
-
+
private:
std::unique_ptr<gba_s3511_device> m_rtc;
};
@@ -232,7 +232,7 @@ class gba_rom_flash1m_rtc_device : public gba_rom_flash1m_device
public:
// construction/destruction
gba_rom_flash1m_rtc_device(const machine_config &mconfig, const char *tag, device_t *owner, UINT32 clock);
-
+
// device-level overrides
virtual void device_start() override;
virtual UINT16 gpio_dev_read(int gpio_dirs) override;
@@ -271,16 +271,16 @@ class gba_rom_yoshiug_device : public gba_rom_eeprom_device
public:
// construction/destruction
gba_rom_yoshiug_device(const machine_config &mconfig, const char *tag, device_t *owner, UINT32 clock);
-
+
// device-level overrides
virtual void device_start() override;
virtual void device_reset() override;
virtual ioport_constructor device_input_ports() const override;
-
+
// reading and writing
virtual DECLARE_READ32_MEMBER(read_tilt) override;
virtual DECLARE_WRITE32_MEMBER(write_tilt) override;
-
+
private:
int m_tilt_ready;
UINT16 m_xpos, m_ypos;
@@ -317,7 +317,7 @@ class gba_rom_boktai_device : public gba_rom_eeprom64_device
public:
// construction/destruction
gba_rom_boktai_device(const machine_config &mconfig, const char *tag, device_t *owner, UINT32 clock);
-
+
// device-level overrides
virtual void device_start() override;
virtual void device_reset() override;
@@ -325,7 +325,7 @@ public:
virtual UINT16 gpio_dev_read(int gpio_dirs) override;
virtual void gpio_dev_write(UINT16 data, int gpio_dirs) override;
-
+
private:
std::unique_ptr<gba_s3511_device> m_rtc;
required_ioport m_sensor;
diff --git a/src/devices/bus/isa/cga.cpp b/src/devices/bus/isa/cga.cpp
index 2dc3a5cd300..71e924dab84 100644
--- a/src/devices/bus/isa/cga.cpp
+++ b/src/devices/bus/isa/cga.cpp
@@ -1814,12 +1814,12 @@ WRITE8_MEMBER( isa8_ec1841_0002_device::io_write )
m_p3df = data;
if (data & 1) {
m_isa->install_memory(0xb8000, 0xb9fff,
- read8_delegate( FUNC(isa8_ec1841_0002_device::char_ram_read), this),
- write8_delegate(FUNC(isa8_ec1841_0002_device::char_ram_write), this) );
+ read8_delegate( FUNC(isa8_ec1841_0002_device::char_ram_read), this),
+ write8_delegate(FUNC(isa8_ec1841_0002_device::char_ram_write), this) );
if(m_vram_size == 0x4000)
m_isa->install_memory(0xbc000, 0xbdfff,
- read8_delegate( FUNC(isa8_ec1841_0002_device::char_ram_read), this),
- write8_delegate(FUNC(isa8_ec1841_0002_device::char_ram_write), this) );
+ read8_delegate( FUNC(isa8_ec1841_0002_device::char_ram_read), this),
+ write8_delegate(FUNC(isa8_ec1841_0002_device::char_ram_write), this) );
} else {
m_isa->install_bank(0xb8000, 0xb8000 + MIN(0x8000,m_vram_size) - 1, "bank_cga", &m_vram[0]);
if(m_vram_size == 0x4000)
diff --git a/src/devices/bus/macpds/macpds.h b/src/devices/bus/macpds/macpds.h
index 511355f6e42..9e42e47b3c1 100644
--- a/src/devices/bus/macpds/macpds.h
+++ b/src/devices/bus/macpds/macpds.h
@@ -83,7 +83,7 @@ public:
void add_macpds_card(device_macpds_card_interface *card);
void install_device(offs_t start, offs_t end, read8_delegate rhandler, write8_delegate whandler, UINT32 mask=0xffffffff);
void install_device(offs_t start, offs_t end, read16_delegate rhandler, write16_delegate whandler, UINT32 mask=0xffffffff);
- void install_bank(offs_t start, offs_t end, const char *tag, UINT8 *data);
+ void install_bank(offs_t start, offs_t end, const char *tag, UINT8 *data);
void set_irq_line(int line, int state);
protected:
diff --git a/src/devices/bus/megadrive/rom.cpp b/src/devices/bus/megadrive/rom.cpp
index ed17cfff044..039574487ca 100644
--- a/src/devices/bus/megadrive/rom.cpp
+++ b/src/devices/bus/megadrive/rom.cpp
@@ -930,7 +930,7 @@ READ16_MEMBER(md_rom_cjmjclub_device::read)
{
if (offset == 0x400000/2) return 0x9000;
if (offset == 0x400002/2) return 0xd300;
-
+
// non-protection accesses
if (offset < 0x400000/2)
return m_rom[MD_ADDR(offset)];
diff --git a/src/devices/bus/megadrive/rom.h b/src/devices/bus/megadrive/rom.h
index 3bafead4346..d640242ff3c 100644
--- a/src/devices/bus/megadrive/rom.h
+++ b/src/devices/bus/megadrive/rom.h
@@ -270,7 +270,7 @@ class md_rom_cjmjclub_device : public md_std_rom_device
public:
// construction/destruction
md_rom_cjmjclub_device(const machine_config &mconfig, const char *tag, device_t *owner, UINT32 clock);
-
+
// reading and writing
virtual DECLARE_READ16_MEMBER(read) override;
};
diff --git a/src/devices/bus/nes/bootleg.cpp b/src/devices/bus/nes/bootleg.cpp
index fbd00b7fadf..f21db4454ff 100644
--- a/src/devices/bus/nes/bootleg.cpp
+++ b/src/devices/bus/nes/bootleg.cpp
@@ -1238,7 +1238,7 @@ READ8_MEMBER(nes_lh32_device::read_m)
READ8_MEMBER(nes_lh32_device::read_h)
{
-// LOG_MMC(("lh32 read_h, offset: %04x\n", offset));
+// LOG_MMC(("lh32 read_h, offset: %04x\n", offset));
if (offset >= 0x4000 && offset < 0x6000)
return m_prgram[offset & 0x1fff];
@@ -1294,7 +1294,7 @@ READ8_MEMBER(nes_lh10_device::read_m)
READ8_MEMBER(nes_lh10_device::read_h)
{
-// LOG_MMC(("lh10 read_h, offset: %04x\n", offset));
+// LOG_MMC(("lh10 read_h, offset: %04x\n", offset));
if (offset >= 0x4000 && offset < 0x6000)
return m_prgram[offset & 0x1fff];
@@ -1363,7 +1363,7 @@ READ8_MEMBER(nes_lh53_device::read_m)
READ8_MEMBER(nes_lh53_device::read_h)
{
-// LOG_MMC(("lh53 read_h, offset: %04x\n", offset));
+// LOG_MMC(("lh53 read_h, offset: %04x\n", offset));
if (offset >= 0x3800 && offset < 0x5800)
return m_battery[offset & 0x1fff];
@@ -1431,7 +1431,7 @@ WRITE8_MEMBER(nes_2708_device::write_m)
READ8_MEMBER(nes_2708_device::read_h)
{
-// LOG_MMC(("btl-2708 read_h, offset: %04x\n", offset));
+// LOG_MMC(("btl-2708 read_h, offset: %04x\n", offset));
if (offset >= 0x3800 && offset < 0x5800 && !m_reg[1])
return m_prgram[0x2000 + ((offset - 0x3800) & 0x1fff)]; // higher 8K of WRAM
@@ -1656,30 +1656,29 @@ READ8_MEMBER(nes_shuiguan_device::read_m)
/*-------------------------------------------------
-
+
RT-01
-
+
Games: Russian test cart
-
- The PRG EPROM has copy protected areas with
+
+ The PRG EPROM has copy protected areas with
"weak bits", which is tested at some points (info
from Cah4e3).
-
+
iNES:
-
+
In MESS:
-
+
-------------------------------------------------*/
READ8_MEMBER(nes_rt01_device::read_h)
{
-// LOG_MMC(("rt01 read_h, offset: %04x\n", offset));
+// LOG_MMC(("rt01 read_h, offset: %04x\n", offset));
if ((offset >= 0x4e80) && (offset < 0x4f00))
return 0xf2 | (machine().rand() & 0x0d);
if ((offset >= 0x7e80) && (offset < 0x7f00))
return 0xf2 | (machine().rand() & 0x0d);
-
+
return hi_access_rom(offset);
}
-
diff --git a/src/devices/bus/nes/bootleg.h b/src/devices/bus/nes/bootleg.h
index 30b40b589a4..59f02a476a5 100644
--- a/src/devices/bus/nes/bootleg.h
+++ b/src/devices/bus/nes/bootleg.h
@@ -460,11 +460,11 @@ class nes_rt01_device : public nes_nrom_device
public:
// construction/destruction
nes_rt01_device(const machine_config &mconfig, const char *tag, device_t *owner, UINT32 clock);
-
+
// device-level overrides
virtual void device_start() override;
virtual DECLARE_READ8_MEMBER(read_h) override;
-
+
virtual void pcb_reset() override;
};
diff --git a/src/devices/bus/nes/kaiser.cpp b/src/devices/bus/nes/kaiser.cpp
index 340aca500cc..e335681157d 100644
--- a/src/devices/bus/nes/kaiser.cpp
+++ b/src/devices/bus/nes/kaiser.cpp
@@ -252,7 +252,7 @@ void nes_ks7016_device::pcb_reset()
prg8_cd(0xe);
prg8_ef(0xf);
chr8(0, CHRRAM);
-
+
m_reg = 4;
}
@@ -270,7 +270,7 @@ void nes_ks7037_device::pcb_reset()
prg8_cd(0);
prg8_ef(0x1f);
chr8(0, CHRRAM);
-
+
memset(m_reg, 0, sizeof(m_reg));
m_latch = 0;
}
@@ -637,15 +637,15 @@ WRITE8_MEMBER(nes_ks7031_device::write_h)
/*-------------------------------------------------
-
+
Kaiser Board KS7016
-
+
Games: Exciting Basket FDS Conversion
-
+
iNES:
-
+
In MESS: Unsupported.
-
+
-------------------------------------------------*/
READ8_MEMBER(nes_ks7016_device::read_m)
@@ -666,20 +666,20 @@ WRITE8_MEMBER(nes_ks7016_device::write_h)
/*-------------------------------------------------
-
+
Kaiser Board KS7037
-
+
Games: Metroid (FDS conversion)
-
+
This PCB maps PRG in 0x7000-0x7fff in a very
similar fashion to LH10 (see bootleg.cpp)
but with WRAM split between 0x6000-0x6fff
and 0xb000-0xbfff.
-
+
iNES:
-
+
In MESS: Unsupported.
-
+
-------------------------------------------------*/
void nes_ks7037_device::update_prg()
@@ -696,7 +696,7 @@ void nes_ks7037_device::update_prg()
READ8_MEMBER(nes_ks7037_device::read_m)
{
-// LOG_MMC(("ks7037 read_m, offset: %04x\n", offset));
+// LOG_MMC(("ks7037 read_m, offset: %04x\n", offset));
if (offset < 0x1000)
return m_prgram[offset & 0x0fff];
else
@@ -712,18 +712,18 @@ WRITE8_MEMBER(nes_ks7037_device::write_m)
READ8_MEMBER(nes_ks7037_device::read_h)
{
-// LOG_MMC(("ks7037 read_h, offset: %04x\n", offset));
-
+// LOG_MMC(("ks7037 read_h, offset: %04x\n", offset));
+
if (offset >= 0x3000 && offset < 0x4000)
return m_prgram[0x1000 + (offset & 0x0fff)];
-
+
return hi_access_rom(offset);
}
WRITE8_MEMBER(nes_ks7037_device::write_h)
{
LOG_MMC(("ks7037 write_h, offset: %04x, data: %02x\n", offset, data));
-
+
if (offset >= 0x3000 && offset < 0x4000)
m_prgram[0x1000 + (offset & 0x0fff)] = data;
else
@@ -740,4 +740,3 @@ WRITE8_MEMBER(nes_ks7037_device::write_h)
}
}
}
-
diff --git a/src/devices/bus/nes/kaiser.h b/src/devices/bus/nes/kaiser.h
index e5ad8628436..6d58ff134fe 100644
--- a/src/devices/bus/nes/kaiser.h
+++ b/src/devices/bus/nes/kaiser.h
@@ -177,14 +177,14 @@ class nes_ks7016_device : public nes_nrom_device
public:
// construction/destruction
nes_ks7016_device(const machine_config &mconfig, const char *tag, device_t *owner, UINT32 clock);
-
+
// device-level overrides
virtual void device_start() override;
virtual DECLARE_READ8_MEMBER(read_m) override;
virtual DECLARE_WRITE8_MEMBER(write_h) override;
-
+
virtual void pcb_reset() override;
-
+
private:
UINT8 m_reg;
};
@@ -196,16 +196,16 @@ class nes_ks7037_device : public nes_nrom_device
public:
// construction/destruction
nes_ks7037_device(const machine_config &mconfig, const char *tag, device_t *owner, UINT32 clock);
-
+
// device-level overrides
virtual void device_start() override;
virtual DECLARE_READ8_MEMBER(read_m) override;
virtual DECLARE_READ8_MEMBER(read_h) override;
virtual DECLARE_WRITE8_MEMBER(write_m) override;
virtual DECLARE_WRITE8_MEMBER(write_h) override;
-
+
virtual void pcb_reset() override;
-
+
private:
void update_prg();
UINT8 m_latch;
diff --git a/src/devices/bus/nubus/nubus_image.h b/src/devices/bus/nubus/nubus_image.h
index 6badecd4f0d..54fe5dbb39b 100644
--- a/src/devices/bus/nubus/nubus_image.h
+++ b/src/devices/bus/nubus/nubus_image.h
@@ -18,7 +18,7 @@ struct nbfilectx {
UINT32 curcmd;
UINT8 filename[128];
UINT8 curdir[1024];
- osd::directory::ptr dirp;
+ osd::directory::ptr dirp;
osd_file::ptr fd;
UINT64 filelen;
UINT32 bytecount;
diff --git a/src/devices/bus/pofo/exp.h b/src/devices/bus/pofo/exp.h
index 3b1e936dca5..81777cf9852 100644
--- a/src/devices/bus/pofo/exp.h
+++ b/src/devices/bus/pofo/exp.h
@@ -65,16 +65,16 @@
MCFG_DEVICE_SLOT_INTERFACE(_slot_intf, _def_slot, false)
#define MCFG_PORTFOLIO_EXPANSION_SLOT_IINT_CALLBACK(_write) \
- devcb = &portfolio_expansion_slot_t::set_iint_wr_callback(*device, DEVCB_##_write);
+ devcb = &portfolio_expansion_slot_t::set_iint_wr_callback(*device, DEVCB_##_write);
#define MCFG_PORTFOLIO_EXPANSION_SLOT_EINT_CALLBACK(_write) \
- devcb = &portfolio_expansion_slot_t::set_eint_wr_callback(*device, DEVCB_##_write);
+ devcb = &portfolio_expansion_slot_t::set_eint_wr_callback(*device, DEVCB_##_write);
#define MCFG_PORTFOLIO_EXPANSION_SLOT_NMIO_CALLBACK(_write) \
- devcb = &portfolio_expansion_slot_t::set_nmio_wr_callback(*device, DEVCB_##_write);
+ devcb = &portfolio_expansion_slot_t::set_nmio_wr_callback(*device, DEVCB_##_write);
#define MCFG_PORTFOLIO_EXPANSION_SLOT_WAKE_CALLBACK(_write) \
- devcb = &portfolio_expansion_slot_t::set_wake_wr_callback(*device, DEVCB_##_write);
+ devcb = &portfolio_expansion_slot_t::set_wake_wr_callback(*device, DEVCB_##_write);
@@ -89,71 +89,71 @@ class portfolio_expansion_slot_t;
class device_portfolio_expansion_slot_interface : public device_slot_card_interface
{
public:
- // construction/destruction
- device_portfolio_expansion_slot_interface(const machine_config &mconfig, device_t &device);
- virtual ~device_portfolio_expansion_slot_interface() { }
+ // construction/destruction
+ device_portfolio_expansion_slot_interface(const machine_config &mconfig, device_t &device);
+ virtual ~device_portfolio_expansion_slot_interface() { }
- virtual bool nmd1() { return 1; }
- virtual bool pdet() { return 0; }
- virtual bool cdet() { return 1; }
+ virtual bool nmd1() { return 1; }
+ virtual bool pdet() { return 0; }
+ virtual bool cdet() { return 1; }
- virtual UINT8 iack_r() { return 0xff; }
- virtual UINT8 eack_r() { return 0xff; }
+ virtual UINT8 iack_r() { return 0xff; }
+ virtual UINT8 eack_r() { return 0xff; }
- virtual UINT8 nrdi_r(address_space &space, offs_t offset, UINT8 data, bool iom, bool bcom, bool ncc1) { return data; };
- virtual void nwri_w(address_space &space, offs_t offset, UINT8 data, bool iom, bool bcom, bool ncc1) { };
+ virtual UINT8 nrdi_r(address_space &space, offs_t offset, UINT8 data, bool iom, bool bcom, bool ncc1) { return data; };
+ virtual void nwri_w(address_space &space, offs_t offset, UINT8 data, bool iom, bool bcom, bool ncc1) { };
- DECLARE_WRITE_LINE_MEMBER( iint_w );
- DECLARE_WRITE_LINE_MEMBER( eint_w );
- DECLARE_WRITE_LINE_MEMBER( nmio_w );
- DECLARE_WRITE_LINE_MEMBER( wake_w );
+ DECLARE_WRITE_LINE_MEMBER( iint_w );
+ DECLARE_WRITE_LINE_MEMBER( eint_w );
+ DECLARE_WRITE_LINE_MEMBER( nmio_w );
+ DECLARE_WRITE_LINE_MEMBER( wake_w );
protected:
- portfolio_expansion_slot_t *m_slot;
+ portfolio_expansion_slot_t *m_slot;
};
// ======================> portfolio_expansion_slot_t
class portfolio_expansion_slot_t : public device_t,
- public device_slot_interface
+ public device_slot_interface
{
public:
// construction/destruction
portfolio_expansion_slot_t(const machine_config &mconfig, const char *tag, device_t *owner, UINT32 clock);
virtual ~portfolio_expansion_slot_t() { }
- template<class _Object> static devcb_base &set_iint_wr_callback(device_t &device, _Object object) { return downcast<portfolio_expansion_slot_t &>(device).m_write_iint.set_callback(object); }
- template<class _Object> static devcb_base &set_eint_wr_callback(device_t &device, _Object object) { return downcast<portfolio_expansion_slot_t &>(device).m_write_eint.set_callback(object); }
- template<class _Object> static devcb_base &set_nmio_wr_callback(device_t &device, _Object object) { return downcast<portfolio_expansion_slot_t &>(device).m_write_nmio.set_callback(object); }
- template<class _Object> static devcb_base &set_wake_wr_callback(device_t &device, _Object object) { return downcast<portfolio_expansion_slot_t &>(device).m_write_wake.set_callback(object); }
+ template<class _Object> static devcb_base &set_iint_wr_callback(device_t &device, _Object object) { return downcast<portfolio_expansion_slot_t &>(device).m_write_iint.set_callback(object); }
+ template<class _Object> static devcb_base &set_eint_wr_callback(device_t &device, _Object object) { return downcast<portfolio_expansion_slot_t &>(device).m_write_eint.set_callback(object); }
+ template<class _Object> static devcb_base &set_nmio_wr_callback(device_t &device, _Object object) { return downcast<portfolio_expansion_slot_t &>(device).m_write_nmio.set_callback(object); }
+ template<class _Object> static devcb_base &set_wake_wr_callback(device_t &device, _Object object) { return downcast<portfolio_expansion_slot_t &>(device).m_write_wake.set_callback(object); }
// computer interface
- bool nmd1_r() { return (m_card != nullptr) ? m_card->nmd1() : 1; }
- bool pdet_r() { return (m_card != nullptr) ? m_card->pdet() : 0; }
- bool cdet_r() { return (m_card != nullptr) ? m_card->cdet() : 1; }
+ bool nmd1_r() { return (m_card != nullptr) ? m_card->nmd1() : 1; }
+ bool pdet_r() { return (m_card != nullptr) ? m_card->pdet() : 0; }
+ bool cdet_r() { return (m_card != nullptr) ? m_card->cdet() : 1; }
- UINT8 iack_r() { return (m_card != nullptr) ? m_card->iack_r() : 0xff; };
- UINT8 eack_r() { return (m_card != nullptr) ? m_card->eack_r() : 0xff; };
+ UINT8 iack_r() { return (m_card != nullptr) ? m_card->iack_r() : 0xff; };
+ UINT8 eack_r() { return (m_card != nullptr) ? m_card->eack_r() : 0xff; };
UINT8 nrdi_r(address_space &space, offs_t offset, UINT8 data, bool iom, bool bcom, bool ncc1) { return (m_card != nullptr) ? m_card->nrdi_r(space, offset, data, iom, bcom, ncc1) : data; }
void nwri_w(address_space &space, offs_t offset, UINT8 data, bool iom, bool bcom, bool ncc1) { if (m_card != nullptr) m_card->nwri_w(space, offset, data, iom, bcom, ncc1); }
- // peripheral interface
- WRITE_LINE_MEMBER( iint_w ) { m_write_iint(state); }
- WRITE_LINE_MEMBER( eint_w ) { m_write_eint(state); }
- WRITE_LINE_MEMBER( nmio_w ) { m_write_nmio(state); }
- WRITE_LINE_MEMBER( wake_w ) { m_write_wake(state); }
+ // peripheral interface
+ WRITE_LINE_MEMBER( iint_w ) { m_write_iint(state); }
+ WRITE_LINE_MEMBER( eint_w ) { m_write_eint(state); }
+ WRITE_LINE_MEMBER( nmio_w ) { m_write_nmio(state); }
+ WRITE_LINE_MEMBER( wake_w ) { m_write_wake(state); }
protected:
// device-level overrides
virtual void device_start() override;
virtual void device_reset() override;
- devcb_write_line m_write_iint;
- devcb_write_line m_write_eint;
- devcb_write_line m_write_nmio;
- devcb_write_line m_write_wake;
+ devcb_write_line m_write_iint;
+ devcb_write_line m_write_eint;
+ devcb_write_line m_write_nmio;
+ devcb_write_line m_write_wake;
device_portfolio_expansion_slot_interface *m_card;
};
diff --git a/src/devices/bus/pofo/hpc101.h b/src/devices/bus/pofo/hpc101.h
index 36b4129049b..7fbdd58a1a9 100644
--- a/src/devices/bus/pofo/hpc101.h
+++ b/src/devices/bus/pofo/hpc101.h
@@ -25,7 +25,7 @@
// ======================> hpc101_t
class hpc101_t : public device_t,
- public device_portfolio_expansion_slot_interface
+ public device_portfolio_expansion_slot_interface
{
public:
// construction/destruction
@@ -42,8 +42,8 @@ protected:
// device_portfolio_expansion_slot_interface overrides
bool pdet() override { return 1; }
- virtual UINT8 nrdi_r(address_space &space, offs_t offset, UINT8 data, bool iom, bool bcom, bool ncc1) override;
- virtual void nwri_w(address_space &space, offs_t offset, UINT8 data, bool iom, bool bcom, bool ncc1) override;
+ virtual UINT8 nrdi_r(address_space &space, offs_t offset, UINT8 data, bool iom, bool bcom, bool ncc1) override;
+ virtual void nwri_w(address_space &space, offs_t offset, UINT8 data, bool iom, bool bcom, bool ncc1) override;
private:
required_device<i8255_device> m_ppi;
diff --git a/src/devices/bus/pofo/hpc102.h b/src/devices/bus/pofo/hpc102.h
index c1fb91305af..fc251b2e87b 100644
--- a/src/devices/bus/pofo/hpc102.h
+++ b/src/devices/bus/pofo/hpc102.h
@@ -25,7 +25,7 @@
// ======================> hpc102_t
class hpc102_t : public device_t,
- public device_portfolio_expansion_slot_interface
+ public device_portfolio_expansion_slot_interface
{
public:
// construction/destruction
@@ -42,10 +42,10 @@ protected:
// device_portfolio_expansion_slot_interface overrides
bool pdet() override { return 1; }
- virtual UINT8 eack_r() override;
+ virtual UINT8 eack_r() override;
- virtual UINT8 nrdi_r(address_space &space, offs_t offset, UINT8 data, bool iom, bool bcom, bool ncc1) override;
- virtual void nwri_w(address_space &space, offs_t offset, UINT8 data, bool iom, bool bcom, bool ncc1) override;
+ virtual UINT8 nrdi_r(address_space &space, offs_t offset, UINT8 data, bool iom, bool bcom, bool ncc1) override;
+ virtual void nwri_w(address_space &space, offs_t offset, UINT8 data, bool iom, bool bcom, bool ncc1) override;
private:
required_device<ins8250_device> m_uart;
@@ -63,4 +63,4 @@ extern const device_type HPC102;
/*
-*/ \ No newline at end of file
+*/
diff --git a/src/devices/bus/sg1000_exp/fm_unit.cpp b/src/devices/bus/sg1000_exp/fm_unit.cpp
index 935346e17de..46e7b036704 100644
--- a/src/devices/bus/sg1000_exp/fm_unit.cpp
+++ b/src/devices/bus/sg1000_exp/fm_unit.cpp
@@ -74,7 +74,7 @@ READ8_MEMBER(sega_fm_unit_device::peripheral_r)
return m_audio_control & 0x01;
}
// will not be called for other offsets.
- return 0xff;
+ return 0xff;
}
//-------------------------------------------------
@@ -116,4 +116,3 @@ bool sega_fm_unit_device::is_writeable(UINT8 offset)
{
return (offset <= 2) ? true : false;
}
-
diff --git a/src/devices/bus/sg1000_exp/sk1100.cpp b/src/devices/bus/sg1000_exp/sk1100.cpp
index 3c5726f96dc..aee9e3c09f7 100644
--- a/src/devices/bus/sg1000_exp/sk1100.cpp
+++ b/src/devices/bus/sg1000_exp/sk1100.cpp
@@ -334,4 +334,3 @@ WRITE8_MEMBER( sega_sk1100_device::ppi_pc_w )
/* TODO printer */
}
-
diff --git a/src/devices/cpu/asap/asapdasm.cpp b/src/devices/cpu/asap/asapdasm.cpp
index fd204c68a94..ded3a24e17b 100644
--- a/src/devices/cpu/asap/asapdasm.cpp
+++ b/src/devices/cpu/asap/asapdasm.cpp
@@ -91,7 +91,7 @@ CPU_DISASSEMBLE( asap )
sprintf(buffer, "mov%s %s,%s", setcond[cond], reg[rsrc1], reg[rdst]);
else
sprintf(buffer, "add%s %s,%s,%s", setcond[cond], reg[rsrc1], src2(op,0), reg[rdst]);
- break;
+ break;
case 0x09: sprintf(buffer, "sub%s %s,%s,%s", setcond[cond], reg[rsrc1], src2(op,0), reg[rdst]); break;
case 0x0a: sprintf(buffer, "addc%s %s,%s,%s", setcond[cond], reg[rsrc1], src2(op,0), reg[rdst]); break;
case 0x0b: sprintf(buffer, "subc%s %s,%s,%s", setcond[cond], reg[rsrc1], src2(op,0), reg[rdst]); break;
diff --git a/src/devices/cpu/avr8/avr8.cpp b/src/devices/cpu/avr8/avr8.cpp
index 2d2dd04824d..f0e790083f7 100644
--- a/src/devices/cpu/avr8/avr8.cpp
+++ b/src/devices/cpu/avr8/avr8.cpp
@@ -2915,7 +2915,7 @@ READ8_MEMBER( avr8_device::regs_r )
default:
printf("[%08X] AVR8: Unknown Register Read: 0x%03X\n", m_shifted_pc, offset);
-// machine().debug_break();
+// machine().debug_break();
return 0;
}
}
diff --git a/src/devices/cpu/drcbex64.cpp b/src/devices/cpu/drcbex64.cpp
index e1d41783a25..df5fc335599 100644
--- a/src/devices/cpu/drcbex64.cpp
+++ b/src/devices/cpu/drcbex64.cpp
@@ -175,7 +175,6 @@
// This is a trick to make it build on Android where the ARM SDK declares ::REG_Rn
namespace drc {
-
using namespace uml;
using namespace x64emit;
diff --git a/src/devices/cpu/drcbex64.h b/src/devices/cpu/drcbex64.h
index 2dcca934ddd..fc8b3cae1af 100644
--- a/src/devices/cpu/drcbex64.h
+++ b/src/devices/cpu/drcbex64.h
@@ -22,7 +22,6 @@
namespace drc {
-
//**************************************************************************
// TYPE DEFINITIONS
//**************************************************************************
diff --git a/src/devices/cpu/m6502/odeco16.lst b/src/devices/cpu/m6502/odeco16.lst
index 3fbc2409789..367f1c00704 100644
--- a/src/devices/cpu/m6502/odeco16.lst
+++ b/src/devices/cpu/m6502/odeco16.lst
@@ -92,7 +92,7 @@ vbl_zpg
TMP2 = read_pc();
A = io->read_byte(0);
//if(DECO16_VERBOSE)
- // logerror("%s: VBL %02x (%04x)\n", tag(), NPC, TMP2);
+ // logerror("%s: VBL %02x (%04x)\n", tag(), NPC, TMP2);
prefetch();
# exceptions
diff --git a/src/devices/cpu/mb86235/mb86235d.cpp b/src/devices/cpu/mb86235/mb86235d.cpp
index 34771cd346e..58dcfc047b6 100644
--- a/src/devices/cpu/mb86235/mb86235d.cpp
+++ b/src/devices/cpu/mb86235/mb86235d.cpp
@@ -6,14 +6,14 @@
static const char *regname[128] =
{
- "MA0", "MA1", "MA2", "MA3", "MA4", "MA5", "MA6", "MA7",
- "AA0", "AA1", "AA2", "AA3", "AA4", "AA5", "AA6", "AA7",
- "EB", "EBU", "EBL", "EO", "SP", "ST", "MOD", "LRPC",
- "AR0", "AR1", "AR2", "AR3", "AR4", "AR5", "AR6", "AR7",
- "MB0", "MB1", "MB2", "MB3", "MB4", "MB5", "MB6", "MB7",
- "AB0", "AB1", "AB2", "AB3", "AB4", "AB5", "AB6", "AB7",
- "PR", "FI", "FO0", "FO1", "PDR", "DDR", "PRP", "PWP",
- "???", "???", "???", "???", "???", "???", "???", "???"
+ "MA0", "MA1", "MA2", "MA3", "MA4", "MA5", "MA6", "MA7",
+ "AA0", "AA1", "AA2", "AA3", "AA4", "AA5", "AA6", "AA7",
+ "EB", "EBU", "EBL", "EO", "SP", "ST", "MOD", "LRPC",
+ "AR0", "AR1", "AR2", "AR3", "AR4", "AR5", "AR6", "AR7",
+ "MB0", "MB1", "MB2", "MB3", "MB4", "MB5", "MB6", "MB7",
+ "AB0", "AB1", "AB2", "AB3", "AB4", "AB5", "AB6", "AB7",
+ "PR", "FI", "FO0", "FO1", "PDR", "DDR", "PRP", "PWP",
+ "???", "???", "???", "???", "???", "???", "???", "???"
};
static const char *db_mnemonic[64] =
@@ -69,22 +69,22 @@ static const char *mi1_field[16] =
static const char *mi2_field[32] =
{ "MA0", "MA1", "MA2", "MA3", "MA4", "MA5", "MA6", "MA7", "MB0", "MB1", "MB2", "MB3", "MB4", "MB5", "MB6", "MB7",
- "PR", "PR++", "PR--", "PR#0", "???", "???", "???", "???", "-1.0E+0", "0.0E+0", "0.5E+0", "1.0E+0", "1.5E+0", "2.0E+0", "3.0E+0", "5.0E+0" };
+ "PR", "PR++", "PR--", "PR#0", "???", "???", "???", "???", "-1.0E+0", "0.0E+0", "0.5E+0", "1.0E+0", "1.5E+0", "2.0E+0", "3.0E+0", "5.0E+0" };
-static const char *mo_field[32] =
+static const char *mo_field[32] =
{ "MA0", "MA1", "MA2", "MA3", "MA4", "MA5", "MA6", "MA7", "MB0", "MB1", "MB2", "MB3", "MB4", "MB5", "MB6", "MB7",
- "AA0", "AA1", "AA2", "AA3", "AA4", "AA5", "AA6", "AA7", "AB0", "AB1", "AB2", "AB3", "AB4", "AB5", "AB6", "AB7" };
+ "AA0", "AA1", "AA2", "AA3", "AA4", "AA5", "AA6", "AA7", "AB0", "AB1", "AB2", "AB3", "AB4", "AB5", "AB6", "AB7" };
-static const char *ai1_field[16] =
+static const char *ai1_field[16] =
{ "AA0", "AA1", "AA2", "AA3", "AA4", "AA5", "AA6", "AA7", "AB0", "AB1", "AB2", "AB3", "AB4", "AB5", "AB6", "AB7" };
static const char *ai2_field[32] =
{ "AA0", "AA1", "AA2", "AA3", "AA4", "AA5", "AA6", "AA7", "AB0", "AB1", "AB2", "AB3", "AB4", "AB5", "AB6", "AB7",
- "PR", "PR++", "PR--", "PR#0", "???", "???", "???", "???", "0", "1", "-1", "???", "???", "???", "???", "???" };
+ "PR", "PR++", "PR--", "PR#0", "???", "???", "???", "???", "0", "1", "-1", "???", "???", "???", "???", "???" };
static const char *ai2f_field[32] =
{ "AA0", "AA1", "AA2", "AA3", "AA4", "AA5", "AA6", "AA7", "AB0", "AB1", "AB2", "AB3", "AB4", "AB5", "AB6", "AB7",
- "PR", "PR++", "PR--", "PR#0", "???", "???", "???", "???", "-1.0E+0", "0.0E+0", "0.5E+0", "1.0E+0", "1.5E+0", "2.0E+0", "3.0E+0", "5.0E+0" };
+ "PR", "PR++", "PR--", "PR#0", "???", "???", "???", "???", "-1.0E+0", "0.0E+0", "0.5E+0", "1.0E+0", "1.5E+0", "2.0E+0", "3.0E+0", "5.0E+0" };
static char* get_ea(int md, int arx, int ary, int disp)
{
@@ -196,7 +196,7 @@ static char* dasm_alu_mul(UINT64 opcode, bool twoop)
break;
}
}
-
+
// multiplication
if (twoop)
{
@@ -211,7 +211,7 @@ static char* dasm_alu_mul(UINT64 opcode, bool twoop)
else
{
if (ma == 0)
- {
+ {
if (opcode & ((UINT64)(1) << 56))
p += sprintf(p, "FMUL %s, %s, %s", mi1_field[i1], mi2_field[i2], mo_field[o]);
else
@@ -296,12 +296,12 @@ static char* dasm_control(UINT32 pc, UINT64 opcode)
p += sprintf(p, "DRET");
break;
- case 0x10: // DBcc
- case 0x11: // DBNcc
- case 0x18: // DCcc
- case 0x19: // DCNcc
- case 0x1a: // DCALL
- case 0x12: // DJMP
+ case 0x10: // DBcc
+ case 0x11: // DBNcc
+ case 0x18: // DCcc
+ case 0x19: // DCNcc
+ case 0x1a: // DCALL
+ case 0x12: // DJMP
{
if (cop == 0x10)
p += sprintf(p, "%s ", db_mnemonic[ef1]);
@@ -798,25 +798,25 @@ static unsigned dasm_mb86235(char *buffer, UINT32 pc, UINT64 opcode)
switch ((opcode >> 61) & 7)
{
- case 0: // ALU / MUL / double transfer (type 1)
+ case 0: // ALU / MUL / double transfer (type 1)
p += sprintf(p, "%s : %s", dasm_alu_mul(opcode, true), dasm_double_xfer1(opcode));
break;
- case 1: // ALU / MYL / transfer (type 1)
+ case 1: // ALU / MYL / transfer (type 1)
p += sprintf(p, "%s : %s", dasm_alu_mul(opcode, true), dasm_xfer1(opcode));
break;
- case 2: // ALU / MUL / control
+ case 2: // ALU / MUL / control
p += sprintf(p, "%s : %s", dasm_alu_mul(opcode, true), dasm_control(pc, opcode));
break;
- case 4: // ALU or MUL / double transfer (type 2)
+ case 4: // ALU or MUL / double transfer (type 2)
p += sprintf(p, "%s : %s", dasm_alu_mul(opcode, false), dasm_double_xfer2(opcode));
break;
- case 5: // ALU or MUL / transfer (type 2)
+ case 5: // ALU or MUL / transfer (type 2)
p += sprintf(p, "%s : %s", dasm_alu_mul(opcode, false), dasm_xfer2(opcode));
break;
- case 6: // ALU or MUL / control
+ case 6: // ALU or MUL / control
p += sprintf(p, "%s : %s", dasm_alu_mul(opcode, false), dasm_control(pc, opcode));
break;
- case 7: // transfer (type 3)
+ case 7: // transfer (type 3)
p += sprintf(p, "%s", dasm_xfer3(opcode));
break;
diff --git a/src/devices/cpu/nec/v25.h b/src/devices/cpu/nec/v25.h
index 6f0fa25eeb6..f170ad03b8f 100644
--- a/src/devices/cpu/nec/v25.h
+++ b/src/devices/cpu/nec/v25.h
@@ -31,7 +31,7 @@ enum
#define MCFG_V25_PORT_P1_READ_CB(_devcb) \
devcb = &v25_common_device::set_p1_in_cb(*device, DEVCB_##_devcb);
-
+
#define MCFG_V25_PORT_P2_READ_CB(_devcb) \
devcb = &v25_common_device::set_p2_in_cb(*device, DEVCB_##_devcb);
@@ -53,7 +53,7 @@ public:
// static configuration helpers
static void set_decryption_table(device_t &device, const UINT8 *decryption_table) { downcast<v25_common_device &>(device).m_v25v35_decryptiontable = decryption_table; }
-
+
template<class _Object> static devcb_base & set_pt_in_cb(device_t &device, _Object object) { return downcast<v25_common_device &>(device).m_pt_in.set_callback(object); }
template<class _Object> static devcb_base & set_p0_in_cb(device_t &device, _Object object) { return downcast<v25_common_device &>(device).m_p0_in.set_callback(object); }
template<class _Object> static devcb_base & set_p1_in_cb(device_t &device, _Object object) { return downcast<v25_common_device &>(device).m_p1_in.set_callback(object); }
diff --git a/src/devices/cpu/patinhofeio/patinho_feio.cpp b/src/devices/cpu/patinhofeio/patinho_feio.cpp
index 8482db59c41..a040d243916 100644
--- a/src/devices/cpu/patinhofeio/patinho_feio.cpp
+++ b/src/devices/cpu/patinhofeio/patinho_feio.cpp
@@ -1,7 +1,7 @@
// license:GPL-2.0+
// copyright-holders:Felipe Sanches
/*
- CPU emulation for Patinho Feio, the first computer designed and manufactured in Brazil
+ CPU emulation for Patinho Feio, the first computer designed and manufactured in Brazil
*/
#include "emu.h"
@@ -91,11 +91,11 @@ void patinho_feio_cpu_device::device_start()
//TODO: implement handling of these special purpose registers
// which are also mapped to the first few main memory positions:
//
-// ERI: "Endereço de Retorno de Interrupção"
+// ERI: "Endereco de Retorno de Interrupcao"
// "Interrupt Return Address"
// stored at addresses 002 and 003
//
-// ETI: "início de uma rotina de tratamento de interrupção (se houver)"
+// ETI: "inicio de uma rotina de tratamento de interrupcao (se houver)"
// "start of an interrupt service routine (if any)"
// stored at address 004 (and 005 as well?)
//
@@ -333,7 +333,7 @@ void patinho_feio_cpu_device::execute_instruction()
case 0x90:
//ST 0 = "Se T=0, Pula"
// If T is zero, skip the next instruction
- if ((FLAGS & T) == 0)
+ if ((FLAGS & T) == 0)
INCREMENT_PC_4K; //skip
return;
case 0x91:
@@ -348,7 +348,7 @@ void patinho_feio_cpu_device::execute_instruction()
case 0x92:
//ST 1 = "Se T=1, Pula"
// If T is one, skip the next instruction
- if ((FLAGS & T) == 1)
+ if ((FLAGS & T) == 1)
INCREMENT_PC_4K; //skip
return;
case 0x93:
@@ -363,7 +363,7 @@ void patinho_feio_cpu_device::execute_instruction()
case 0x94:
//SV 0 = "Se V=0, Pula"
// If V is zero, skip the next instruction
- if ((FLAGS & V) == 0)
+ if ((FLAGS & V) == 0)
INCREMENT_PC_4K; //skip
return;
case 0x95:
@@ -378,7 +378,7 @@ void patinho_feio_cpu_device::execute_instruction()
case 0x96:
//SV 1 = "Se V=1, Pula"
// If V is one, skip the next instruction
- if ((FLAGS & V) == 1)
+ if ((FLAGS & V) == 1)
INCREMENT_PC_4K; //skip
return;
case 0x97:
@@ -391,17 +391,17 @@ void patinho_feio_cpu_device::execute_instruction()
}
return;
case 0x98:
- //PUL="Pula para /002 a limpa estado de interrupção"
+ //PUL="Pula para /002 a limpa estado de interrupcao"
// Jump to address /002 and disables interrupts
- PC = 0x002;
+ PC = 0x002;
m_interrupts_enabled = false;
return;
case 0x99:
- //TRE="Troca conteúdos de ACC e EXT"
+ //TRE="Troca conteudos de ACC e EXT"
// Exchange the value of the accumulator with the ACC extension register
- value = ACC;
- ACC = READ_ACC_EXTENSION_REG();
- WRITE_ACC_EXTENSION_REG(value);
+ value = ACC;
+ ACC = READ_ACC_EXTENSION_REG();
+ WRITE_ACC_EXTENSION_REG(value);
return;
case 0x9A:
//INIB="Inibe"
@@ -621,7 +621,7 @@ void patinho_feio_cpu_device::execute_instruction()
{
case 0:
// FNC /n0: Desliga flip-flop PERMITE/IMPEDE para
- // o dispositivo n (isto é, impede inter-
+ // o dispositivo n (isto e, impede inter-
// -rupcao do dispositivo n).
//
// Turns off the interrupt ENABLE/DISABLE
@@ -654,7 +654,7 @@ void patinho_feio_cpu_device::execute_instruction()
break;
case 5:
// FNC /n5: Liga flip-flop PERMITE/IMPEDE para o
- // dispositivo n (isto é, permite inter-
+ // dispositivo n (isto e, permite inter-
// -rupcao do dispositivo n).
//
// Turns on the interrupt ENABLE/DISABLE
@@ -681,7 +681,7 @@ void patinho_feio_cpu_device::execute_instruction()
m_iodev_control[channel] = NO_REQUEST;
break;
case 8:
- // FNC /n8: Só funciona na leitora de fita, ca-
+ // FNC /n8: So funciona na leitora de fita, ca-
// nal /E. Ignora todos os "feed-fra-
// -mes" ("bytes" nulos) da fita, ate' a
// proxima perfuracao (1o "byte" nao
@@ -695,7 +695,7 @@ void patinho_feio_cpu_device::execute_instruction()
//TODO: Implement-me!
} else {
printf("Function 8 of the /FNC instruction can only be used with"\
- "the papertape reader device at channel /E.\n");
+ "the papertape reader device at channel /E.\n");
}
break;
default:
@@ -705,7 +705,7 @@ void patinho_feio_cpu_device::execute_instruction()
case 0x20:
//SAL="Salta"
// Skips a couple bytes if a condition is met
- skip = false;
+ skip = false;
switch(function)
{
case 1:
diff --git a/src/devices/cpu/patinhofeio/patinhofeio_cpu.h b/src/devices/cpu/patinhofeio/patinhofeio_cpu.h
index b8e6919273d..5d3a1745f53 100644
--- a/src/devices/cpu/patinhofeio/patinhofeio_cpu.h
+++ b/src/devices/cpu/patinhofeio/patinhofeio_cpu.h
@@ -35,18 +35,18 @@ enum
#define REQUEST true
#define NO_REQUEST false
-#define BUTTON_NORMAL (1 << 0) /* normal CPU execution */
-#define BUTTON_CICLO_UNICO (1 << 1) /* single-cycle step */
-#define BUTTON_INSTRUCAO_UNICA (1 << 2) /* single-instruction step */
-#define BUTTON_ENDERECAMENTO (1 << 3) /* addressing action */
-#define BUTTON_ARMAZENAMENTO (1 << 4) /* storage action */
-#define BUTTON_EXPOSICAO (1 << 5) /* memory viewing action */
-#define BUTTON_ESPERA (1 << 6) /* wait */
-#define BUTTON_INTERRUPCAO (1 << 7) /* interrupt */
-#define BUTTON_PARTIDA (1 << 8) /* startup */
-#define BUTTON_PREPARACAO (1 << 9) /* reset */
-#define BUTTON_TIPO_DE_ENDERECAMENTO (1 << 10) /* Addressing mode (0: Fixed / 1: Sequential) */
-#define BUTTON_PROTECAO_DE_MEMORIA (1 << 11) /* Memory protection (in the address range 0xF80-0xFFF (1: write-only / 0: read-write) */
+#define BUTTON_NORMAL (1 << 0) /* normal CPU execution */
+#define BUTTON_CICLO_UNICO (1 << 1) /* single-cycle step */
+#define BUTTON_INSTRUCAO_UNICA (1 << 2) /* single-instruction step */
+#define BUTTON_ENDERECAMENTO (1 << 3) /* addressing action */
+#define BUTTON_ARMAZENAMENTO (1 << 4) /* storage action */
+#define BUTTON_EXPOSICAO (1 << 5) /* memory viewing action */
+#define BUTTON_ESPERA (1 << 6) /* wait */
+#define BUTTON_INTERRUPCAO (1 << 7) /* interrupt */
+#define BUTTON_PARTIDA (1 << 8) /* startup */
+#define BUTTON_PREPARACAO (1 << 9) /* reset */
+#define BUTTON_TIPO_DE_ENDERECAMENTO (1 << 10) /* Addressing mode (0: Fixed / 1: Sequential) */
+#define BUTTON_PROTECAO_DE_MEMORIA (1 << 11) /* Memory protection (in the address range 0xF80-0xFFF (1: write-only / 0: read-write) */
class patinho_feio_cpu_device : public cpu_device {
public:
@@ -76,14 +76,14 @@ protected:
/* processor registers */
unsigned char m_acc; /* accumulator (8 bits) */
unsigned int m_pc; /* program counter (12 bits)
- * Actual register name is CI, which
- * stands for "Contador de Instrucao"
- * or "instructions counter".
- */
+ * Actual register name is CI, which
+ * stands for "Contador de Instrucao"
+ * or "instructions counter".
+ */
unsigned int m_rc; /* RC = "Registrador de Chaves" (Keys Register)
- * It represents the 12 bits of input data
- * from toggle switches in the computer panel
- */
+ * It represents the 12 bits of input data
+ * from toggle switches in the computer panel
+ */
unsigned char m_idx; /* IDX = Index Register */
unsigned char m_ext; /* EXT = Accumulator Extension Register */
diff --git a/src/devices/cpu/sharc/sharc.cpp b/src/devices/cpu/sharc/sharc.cpp
index 4123da67594..44a7c650d7d 100644
--- a/src/devices/cpu/sharc/sharc.cpp
+++ b/src/devices/cpu/sharc/sharc.cpp
@@ -11,7 +11,7 @@
#include "sharcfe.h"
-#define DISABLE_FAST_REGISTERS 1
+#define DISABLE_FAST_REGISTERS 1
@@ -336,7 +336,7 @@ void adsp21062_device::external_dma_write(UINT32 address, UINT64 data)
void adsp21062_device::device_start()
{
int saveindex;
-
+
m_core = (sharc_internal_state *)m_cache.alloc_near(sizeof(sharc_internal_state));
memset(m_core, 0, sizeof(sharc_internal_state));
@@ -356,7 +356,7 @@ void adsp21062_device::device_start()
// add UML symbols
m_drcuml->symbol_add(&m_core->pc, sizeof(m_core->pc), "pc");
m_drcuml->symbol_add(&m_core->icount, sizeof(m_core->icount), "icount");
-
+
for (int i=0; i < 16; i++)
{
char buf[10];
@@ -412,7 +412,7 @@ void adsp21062_device::device_start()
m_drcuml->symbol_add(&m_core->astat_drc.sz, sizeof(m_core->astat_drc.sz), "astat_sz");
m_drcuml->symbol_add(&m_core->astat_drc.sv, sizeof(m_core->astat_drc.sv), "astat_sv");
m_drcuml->symbol_add(&m_core->astat_drc.ss, sizeof(m_core->astat_drc.ss), "astat_ss");
-
+
m_drcuml->symbol_add(&m_core->arg0, sizeof(m_core->arg0), "arg0");
m_drcuml->symbol_add(&m_core->arg1, sizeof(m_core->arg1), "arg1");
m_drcuml->symbol_add(&m_core->arg2, sizeof(m_core->arg2), "arg2");
diff --git a/src/devices/cpu/sharc/sharc.h b/src/devices/cpu/sharc/sharc.h
index 215135390e0..1eb2dc8972b 100644
--- a/src/devices/cpu/sharc/sharc.h
+++ b/src/devices/cpu/sharc/sharc.h
@@ -111,25 +111,25 @@ struct SHARC_DMA_OP
#define MODE2_CAFRZ 0x80000 /* Cache freeze */
-#define SIGN_EXTEND6(x) (((x) & 0x20) ? (0xffffffc0 | (x)) : (x))
-#define SIGN_EXTEND24(x) (((x) & 0x800000) ? (0xff000000 | (x)) : (x))
+#define SIGN_EXTEND6(x) (((x) & 0x20) ? (0xffffffc0 | (x)) : (x))
+#define SIGN_EXTEND24(x) (((x) & 0x800000) ? (0xff000000 | (x)) : (x))
#define MAKE_EXTRACT_MASK(start_bit, length) ((0xffffffff << start_bit) & (((UINT32)0xffffffff) >> (32 - (start_bit + length))))
-#define OP_USERFLAG_COUNTER_LOOP 0x00000001
-#define OP_USERFLAG_COND_LOOP 0x00000002
-#define OP_USERFLAG_COND_FIELD 0x000003fc
-#define OP_USERFLAG_COND_FIELD_SHIFT 2
-#define OP_USERFLAG_ASTAT_DELAY_COPY_AZ 0x00001000
-#define OP_USERFLAG_ASTAT_DELAY_COPY_AN 0x00002000
-#define OP_USERFLAG_ASTAT_DELAY_COPY_AC 0x00004000
-#define OP_USERFLAG_ASTAT_DELAY_COPY_AV 0x00008000
-#define OP_USERFLAG_ASTAT_DELAY_COPY_MV 0x00010000
-#define OP_USERFLAG_ASTAT_DELAY_COPY_MN 0x00020000
-#define OP_USERFLAG_ASTAT_DELAY_COPY_SV 0x00040000
-#define OP_USERFLAG_ASTAT_DELAY_COPY_SZ 0x00080000
-#define OP_USERFLAG_ASTAT_DELAY_COPY_BTF 0x00100000
-#define OP_USERFLAG_ASTAT_DELAY_COPY 0x001ff000
-#define OP_USERFLAG_CALL 0x10000000
+#define OP_USERFLAG_COUNTER_LOOP 0x00000001
+#define OP_USERFLAG_COND_LOOP 0x00000002
+#define OP_USERFLAG_COND_FIELD 0x000003fc
+#define OP_USERFLAG_COND_FIELD_SHIFT 2
+#define OP_USERFLAG_ASTAT_DELAY_COPY_AZ 0x00001000
+#define OP_USERFLAG_ASTAT_DELAY_COPY_AN 0x00002000
+#define OP_USERFLAG_ASTAT_DELAY_COPY_AC 0x00004000
+#define OP_USERFLAG_ASTAT_DELAY_COPY_AV 0x00008000
+#define OP_USERFLAG_ASTAT_DELAY_COPY_MV 0x00010000
+#define OP_USERFLAG_ASTAT_DELAY_COPY_MN 0x00020000
+#define OP_USERFLAG_ASTAT_DELAY_COPY_SV 0x00040000
+#define OP_USERFLAG_ASTAT_DELAY_COPY_SZ 0x00080000
+#define OP_USERFLAG_ASTAT_DELAY_COPY_BTF 0x00100000
+#define OP_USERFLAG_ASTAT_DELAY_COPY 0x001ff000
+#define OP_USERFLAG_CALL 0x10000000
#define MCFG_SHARC_BOOT_MODE(boot_mode) \
@@ -439,7 +439,7 @@ private:
uml::code_handle *m_pop_loop;
uml::code_handle *m_push_status;
uml::code_handle *m_pop_status;
- uml::code_handle *m_exception[EXCEPTION_COUNT]; // exception handlers
+ uml::code_handle *m_exception[EXCEPTION_COUNT]; // exception handlers
uml::code_handle *m_swap_dag1_0_3;
uml::code_handle *m_swap_dag1_4_7;
uml::code_handle *m_swap_dag2_0_3;
@@ -596,7 +596,7 @@ private:
{
UINT32 cycles; /* accumulated cycles */
UINT8 checkints; /* need to check interrupts before next instruction */
- uml::code_label labelnum; /* index for local labels */
+ uml::code_label labelnum; /* index for local labels */
struct
{
int counter;
diff --git a/src/devices/cpu/sharc/sharcdrc.cpp b/src/devices/cpu/sharc/sharcdrc.cpp
index 2850f91da67..a40586cac23 100644
--- a/src/devices/cpu/sharc/sharcdrc.cpp
+++ b/src/devices/cpu/sharc/sharcdrc.cpp
@@ -17,7 +17,7 @@
using namespace uml;
-#define USE_SWAPDQ 0
+#define USE_SWAPDQ 0
#define WRITE_SNOOP 0
@@ -25,85 +25,85 @@ using namespace uml;
#define MAPVAR_PC M0
#define MAPVAR_CYCLES M1
-// exit codes
+// exit codes
#define EXECUTE_OUT_OF_CYCLES 0
#define EXECUTE_MISSING_CODE 1
#define EXECUTE_UNMAPPED_CODE 2
#define EXECUTE_RESET_CACHE 3
-#define REG(reg) m_regmap[reg]
-#define DM_I(reg) mem(&m_core->dag1.i[reg])
-#define DM_M(reg) mem(&m_core->dag1.m[reg])
-#define DM_L(reg) mem(&m_core->dag1.l[reg])
-#define DM_B(reg) mem(&m_core->dag1.b[reg])
-#define PM_I(reg) mem(&m_core->dag2.i[reg])
-#define PM_M(reg) mem(&m_core->dag2.m[reg])
-#define PM_L(reg) mem(&m_core->dag2.l[reg])
-#define PM_B(reg) mem(&m_core->dag2.b[reg])
-#define ASTAT_AZ mem(&m_core->astat_drc.az)
-#define ASTAT_AV mem(&m_core->astat_drc.av)
-#define ASTAT_AN mem(&m_core->astat_drc.an)
-#define ASTAT_AC mem(&m_core->astat_drc.ac)
-#define ASTAT_AS mem(&m_core->astat_drc.as)
-#define ASTAT_AI mem(&m_core->astat_drc.ai)
-#define ASTAT_AF mem(&m_core->astat_drc.af)
-#define ASTAT_MN mem(&m_core->astat_drc.mn)
-#define ASTAT_MV mem(&m_core->astat_drc.mv)
-#define ASTAT_MU mem(&m_core->astat_drc.mu)
-#define ASTAT_MI mem(&m_core->astat_drc.mi)
-#define ASTAT_SV mem(&m_core->astat_drc.sv)
-#define ASTAT_SZ mem(&m_core->astat_drc.sz)
-#define ASTAT_SS mem(&m_core->astat_drc.ss)
-#define ASTAT_BTF mem(&m_core->astat_drc.btf)
-#define FLAG0 mem(&m_core->flag[0])
-#define FLAG1 mem(&m_core->flag[1])
-#define FLAG2 mem(&m_core->flag[2])
-#define FLAG3 mem(&m_core->flag[3])
-#define CURLCNTR mem(&m_core->curlcntr)
-#define LCNTR mem(&m_core->lcntr)
-#define PCSTK mem(&m_core->pcstk)
-#define PCSTKP mem(&m_core->pcstkp)
-#define STKY mem(&m_core->stky)
-#define LSTKP mem(&m_core->lstkp)
-#define USTAT1 mem(&m_core->ustat1)
-#define USTAT2 mem(&m_core->ustat2)
-#define IRPTL mem(&m_core->irptl)
-#define MODE1 mem(&m_core->mode1)
-#define MODE2 mem(&m_core->mode2)
-#define IMASK mem(&m_core->imask)
-#define IMASKP mem(&m_core->imaskp)
-#define MRF mem(&m_core->mrf)
-#define MRB mem(&m_core->mrb)
-
-#define AZ_CALC_REQUIRED ((desc->regreq[0] & 0x00010000) || desc->flags & OPFLAG_IN_DELAY_SLOT)
-#define AV_CALC_REQUIRED ((desc->regreq[0] & 0x00020000) || desc->flags & OPFLAG_IN_DELAY_SLOT)
-#define AN_CALC_REQUIRED ((desc->regreq[0] & 0x00040000) || desc->flags & OPFLAG_IN_DELAY_SLOT)
-#define AC_CALC_REQUIRED ((desc->regreq[0] & 0x00080000) || desc->flags & OPFLAG_IN_DELAY_SLOT)
-#define AS_CALC_REQUIRED ((desc->regreq[0] & 0x00100000) || desc->flags & OPFLAG_IN_DELAY_SLOT)
-#define AI_CALC_REQUIRED ((desc->regreq[0] & 0x00200000) || desc->flags & OPFLAG_IN_DELAY_SLOT)
-#define MN_CALC_REQUIRED ((desc->regreq[0] & 0x00400000) || desc->flags & OPFLAG_IN_DELAY_SLOT)
-#define MV_CALC_REQUIRED ((desc->regreq[0] & 0x00800000) || desc->flags & OPFLAG_IN_DELAY_SLOT)
-#define MU_CALC_REQUIRED ((desc->regreq[0] & 0x01000000) || desc->flags & OPFLAG_IN_DELAY_SLOT)
-#define MI_CALC_REQUIRED ((desc->regreq[0] & 0x02000000) || desc->flags & OPFLAG_IN_DELAY_SLOT)
-#define SV_CALC_REQUIRED ((desc->regreq[0] & 0x04000000) || desc->flags & OPFLAG_IN_DELAY_SLOT)
-#define SZ_CALC_REQUIRED ((desc->regreq[0] & 0x08000000) || desc->flags & OPFLAG_IN_DELAY_SLOT)
-#define SS_CALC_REQUIRED ((desc->regreq[0] & 0x10000000) || desc->flags & OPFLAG_IN_DELAY_SLOT)
-#define BTF_CALC_REQUIRED ((desc->regreq[0] & 0x20000000) || desc->flags & OPFLAG_IN_DELAY_SLOT)
-#define AF_CALC_REQUIRED ((desc->regreq[0] & 0x40000000) || desc->flags & OPFLAG_IN_DELAY_SLOT)
-
-
-#define IRAM_BLOCK0_START 0x20000
-#define IRAM_BLOCK0_END 0x27fff
-#define IRAM_BLOCK1_START 0x28000
-#define IRAM_BLOCK1_END 0x3ffff
-#define IRAM_SHORT_BLOCK0_START 0x40000
-#define IRAM_SHORT_BLOCK0_END 0x4ffff
-#define IRAM_SHORT_BLOCK1_START 0x50000
-#define IRAM_SHORT_BLOCK1_END 0x7ffff
-#define IOP_REGISTER_START 0x00000
-#define IOP_REGISTER_END 0x000ff
-#define IRAM_END 0x7ffff
+#define REG(reg) m_regmap[reg]
+#define DM_I(reg) mem(&m_core->dag1.i[reg])
+#define DM_M(reg) mem(&m_core->dag1.m[reg])
+#define DM_L(reg) mem(&m_core->dag1.l[reg])
+#define DM_B(reg) mem(&m_core->dag1.b[reg])
+#define PM_I(reg) mem(&m_core->dag2.i[reg])
+#define PM_M(reg) mem(&m_core->dag2.m[reg])
+#define PM_L(reg) mem(&m_core->dag2.l[reg])
+#define PM_B(reg) mem(&m_core->dag2.b[reg])
+#define ASTAT_AZ mem(&m_core->astat_drc.az)
+#define ASTAT_AV mem(&m_core->astat_drc.av)
+#define ASTAT_AN mem(&m_core->astat_drc.an)
+#define ASTAT_AC mem(&m_core->astat_drc.ac)
+#define ASTAT_AS mem(&m_core->astat_drc.as)
+#define ASTAT_AI mem(&m_core->astat_drc.ai)
+#define ASTAT_AF mem(&m_core->astat_drc.af)
+#define ASTAT_MN mem(&m_core->astat_drc.mn)
+#define ASTAT_MV mem(&m_core->astat_drc.mv)
+#define ASTAT_MU mem(&m_core->astat_drc.mu)
+#define ASTAT_MI mem(&m_core->astat_drc.mi)
+#define ASTAT_SV mem(&m_core->astat_drc.sv)
+#define ASTAT_SZ mem(&m_core->astat_drc.sz)
+#define ASTAT_SS mem(&m_core->astat_drc.ss)
+#define ASTAT_BTF mem(&m_core->astat_drc.btf)
+#define FLAG0 mem(&m_core->flag[0])
+#define FLAG1 mem(&m_core->flag[1])
+#define FLAG2 mem(&m_core->flag[2])
+#define FLAG3 mem(&m_core->flag[3])
+#define CURLCNTR mem(&m_core->curlcntr)
+#define LCNTR mem(&m_core->lcntr)
+#define PCSTK mem(&m_core->pcstk)
+#define PCSTKP mem(&m_core->pcstkp)
+#define STKY mem(&m_core->stky)
+#define LSTKP mem(&m_core->lstkp)
+#define USTAT1 mem(&m_core->ustat1)
+#define USTAT2 mem(&m_core->ustat2)
+#define IRPTL mem(&m_core->irptl)
+#define MODE1 mem(&m_core->mode1)
+#define MODE2 mem(&m_core->mode2)
+#define IMASK mem(&m_core->imask)
+#define IMASKP mem(&m_core->imaskp)
+#define MRF mem(&m_core->mrf)
+#define MRB mem(&m_core->mrb)
+
+#define AZ_CALC_REQUIRED ((desc->regreq[0] & 0x00010000) || desc->flags & OPFLAG_IN_DELAY_SLOT)
+#define AV_CALC_REQUIRED ((desc->regreq[0] & 0x00020000) || desc->flags & OPFLAG_IN_DELAY_SLOT)
+#define AN_CALC_REQUIRED ((desc->regreq[0] & 0x00040000) || desc->flags & OPFLAG_IN_DELAY_SLOT)
+#define AC_CALC_REQUIRED ((desc->regreq[0] & 0x00080000) || desc->flags & OPFLAG_IN_DELAY_SLOT)
+#define AS_CALC_REQUIRED ((desc->regreq[0] & 0x00100000) || desc->flags & OPFLAG_IN_DELAY_SLOT)
+#define AI_CALC_REQUIRED ((desc->regreq[0] & 0x00200000) || desc->flags & OPFLAG_IN_DELAY_SLOT)
+#define MN_CALC_REQUIRED ((desc->regreq[0] & 0x00400000) || desc->flags & OPFLAG_IN_DELAY_SLOT)
+#define MV_CALC_REQUIRED ((desc->regreq[0] & 0x00800000) || desc->flags & OPFLAG_IN_DELAY_SLOT)
+#define MU_CALC_REQUIRED ((desc->regreq[0] & 0x01000000) || desc->flags & OPFLAG_IN_DELAY_SLOT)
+#define MI_CALC_REQUIRED ((desc->regreq[0] & 0x02000000) || desc->flags & OPFLAG_IN_DELAY_SLOT)
+#define SV_CALC_REQUIRED ((desc->regreq[0] & 0x04000000) || desc->flags & OPFLAG_IN_DELAY_SLOT)
+#define SZ_CALC_REQUIRED ((desc->regreq[0] & 0x08000000) || desc->flags & OPFLAG_IN_DELAY_SLOT)
+#define SS_CALC_REQUIRED ((desc->regreq[0] & 0x10000000) || desc->flags & OPFLAG_IN_DELAY_SLOT)
+#define BTF_CALC_REQUIRED ((desc->regreq[0] & 0x20000000) || desc->flags & OPFLAG_IN_DELAY_SLOT)
+#define AF_CALC_REQUIRED ((desc->regreq[0] & 0x40000000) || desc->flags & OPFLAG_IN_DELAY_SLOT)
+
+
+#define IRAM_BLOCK0_START 0x20000
+#define IRAM_BLOCK0_END 0x27fff
+#define IRAM_BLOCK1_START 0x28000
+#define IRAM_BLOCK1_END 0x3ffff
+#define IRAM_SHORT_BLOCK0_START 0x40000
+#define IRAM_SHORT_BLOCK0_END 0x4ffff
+#define IRAM_SHORT_BLOCK1_START 0x50000
+#define IRAM_SHORT_BLOCK1_END 0x7ffff
+#define IOP_REGISTER_START 0x00000
+#define IOP_REGISTER_END 0x000ff
+#define IRAM_END 0x7ffff
inline void adsp21062_device::alloc_handle(drcuml_state *drcuml, code_handle **handleptr, const char *name)
@@ -267,26 +267,26 @@ UINT32 adsp21062_device::do_condition_astat_bits(int condition)
UINT32 r = 0;
switch (condition)
{
- case 0x00: r = AZ; break; // EQ
- case 0x01: r = AZ | AN; break; // LT
- case 0x02: r = AZ | AN; break; // LE
- case 0x03: r = AC; break; // AC
- case 0x04: r = AV; break; // AV
- case 0x05: r = MV; break; // MV
- case 0x06: r = MN; break; // MS
- case 0x07: r = SV; break; // SV
- case 0x08: r = SZ; break; // SZ
- case 0x0d: r = BTF; break; // TF
- case 0x10: r = AZ; break; // NOT EQUAL
- case 0x11: r = AZ | AN; break; // GE
- case 0x12: r = AZ | AN; break; // GT
- case 0x13: r = AC; break; // NOT AC
- case 0x14: r = AV; break; // NOT AV
- case 0x15: r = MV; break; // NOT MV
- case 0x16: r = MN; break; // NOT MS
- case 0x17: r = SV; break; // NOT SV
- case 0x18: r = SZ; break; // NOT SZ
- case 0x1d: r = BTF; break; // NOT TF
+ case 0x00: r = AZ; break; // EQ
+ case 0x01: r = AZ | AN; break; // LT
+ case 0x02: r = AZ | AN; break; // LE
+ case 0x03: r = AC; break; // AC
+ case 0x04: r = AV; break; // AV
+ case 0x05: r = MV; break; // MV
+ case 0x06: r = MN; break; // MS
+ case 0x07: r = SV; break; // SV
+ case 0x08: r = SZ; break; // SZ
+ case 0x0d: r = BTF; break; // TF
+ case 0x10: r = AZ; break; // NOT EQUAL
+ case 0x11: r = AZ | AN; break; // GE
+ case 0x12: r = AZ | AN; break; // GT
+ case 0x13: r = AC; break; // NOT AC
+ case 0x14: r = AV; break; // NOT AV
+ case 0x15: r = MV; break; // NOT MV
+ case 0x16: r = MN; break; // NOT MS
+ case 0x17: r = SV; break; // NOT SV
+ case 0x18: r = SZ; break; // NOT SZ
+ case 0x1d: r = BTF; break; // NOT TF
}
return r;
@@ -354,220 +354,220 @@ void adsp21062_device::static_generate_memory_accessor(MEM_ACCESSOR_TYPE type, c
switch (type)
{
case MEM_ACCESSOR_PM_READ48:
- UML_CMP(block, I1, IRAM_BLOCK0_START); // cmp i1,IRAM_BLOCK0_START
- UML_JMPc(block, COND_B, label); // jb label1
- UML_CMP(block, I1, IRAM_BLOCK0_END); // cmp i1,IRAM_BLOCK0_END
- UML_JMPc(block, COND_A, label); // ja label1
-
+ UML_CMP(block, I1, IRAM_BLOCK0_START); // cmp i1,IRAM_BLOCK0_START
+ UML_JMPc(block, COND_B, label); // jb label1
+ UML_CMP(block, I1, IRAM_BLOCK0_END); // cmp i1,IRAM_BLOCK0_END
+ UML_JMPc(block, COND_A, label); // ja label1
+
// 0x20000 ... 0x27fff
- UML_AND(block, I1, I1, 0x7fff); // and i1,i1,0x7fff
- UML_MULS(block, I1, I1, I1, 3); // muls i1,3
- UML_DLOAD(block, I0, block0, I1, SIZE_WORD, SCALE_x2); // dload i0,[block0],i1,word,scale_x2
- UML_DSHL(block, I0, I0, 32); // dshl i0,i0,32
- UML_DLOAD(block, I2, block0_1, I1, SIZE_WORD, SCALE_x2); // dload i2,[block0_1],i1,word,scale_x2
- UML_DSHL(block, I2, I2, 16); // dshl i2,i2,16
- UML_DOR(block, I0, I0, I2); // dor i0,i0,i2
- UML_DLOAD(block, I2, block0_2, I1, SIZE_WORD, SCALE_x2); // dload i2,[block0_2],i1,word,scale_x2
- UML_DOR(block, I0, I0, I2); // dor i0,i0,i2
- UML_RET(block); // ret
-
- UML_LABEL(block, label++); // label1:
- UML_CMP(block, I1, IRAM_BLOCK1_START); // cmp i1,IRAM_BLOCK1_START
- UML_JMPc(block, COND_B, label); // jb label2
- UML_CMP(block, I1, IRAM_BLOCK1_END); // cmp i1,IRAM_BLOCK1_END
- UML_JMPc(block, COND_A, label); // ja label2
+ UML_AND(block, I1, I1, 0x7fff); // and i1,i1,0x7fff
+ UML_MULS(block, I1, I1, I1, 3); // muls i1,3
+ UML_DLOAD(block, I0, block0, I1, SIZE_WORD, SCALE_x2); // dload i0,[block0],i1,word,scale_x2
+ UML_DSHL(block, I0, I0, 32); // dshl i0,i0,32
+ UML_DLOAD(block, I2, block0_1, I1, SIZE_WORD, SCALE_x2); // dload i2,[block0_1],i1,word,scale_x2
+ UML_DSHL(block, I2, I2, 16); // dshl i2,i2,16
+ UML_DOR(block, I0, I0, I2); // dor i0,i0,i2
+ UML_DLOAD(block, I2, block0_2, I1, SIZE_WORD, SCALE_x2); // dload i2,[block0_2],i1,word,scale_x2
+ UML_DOR(block, I0, I0, I2); // dor i0,i0,i2
+ UML_RET(block); // ret
+
+ UML_LABEL(block, label++); // label1:
+ UML_CMP(block, I1, IRAM_BLOCK1_START); // cmp i1,IRAM_BLOCK1_START
+ UML_JMPc(block, COND_B, label); // jb label2
+ UML_CMP(block, I1, IRAM_BLOCK1_END); // cmp i1,IRAM_BLOCK1_END
+ UML_JMPc(block, COND_A, label); // ja label2
// 0x28000 ... 0x3ffff
- UML_AND(block, I1, I1, 0x7fff); // and i1,i1,0x7fff (block 1 is mirrored in 0x28000...2ffff, 0x30000...0x37fff and 0x38000...3ffff)
- UML_MULS(block, I1, I1, I1, 3); // muls i1,3
- UML_DLOAD(block, I0, block1, I1, SIZE_WORD, SCALE_x2); // dload i0,[block1],i1,word,scale_x2
- UML_DSHL(block, I0, I0, 32); // dshl i0,i0,32
- UML_DLOAD(block, I2, block1_1, I1, SIZE_WORD, SCALE_x2); // dload i2,[block1_1],i1,word,scale_x2
- UML_DSHL(block, I2, I2, 16); // dshl i2,i2,16
- UML_DOR(block, I0, I0, I2); // dor i0,i0,i2
- UML_DLOAD(block, I2, block1_2, I1, SIZE_WORD, SCALE_x2); // dload i2,[block1_2],i1,word,scale_x2
- UML_DOR(block, I0, I0, I2); // dor i0,i0,i2
- UML_RET(block); // ret
-
- UML_LABEL(block, label++); // label2:
+ UML_AND(block, I1, I1, 0x7fff); // and i1,i1,0x7fff (block 1 is mirrored in 0x28000...2ffff, 0x30000...0x37fff and 0x38000...3ffff)
+ UML_MULS(block, I1, I1, I1, 3); // muls i1,3
+ UML_DLOAD(block, I0, block1, I1, SIZE_WORD, SCALE_x2); // dload i0,[block1],i1,word,scale_x2
+ UML_DSHL(block, I0, I0, 32); // dshl i0,i0,32
+ UML_DLOAD(block, I2, block1_1, I1, SIZE_WORD, SCALE_x2); // dload i2,[block1_1],i1,word,scale_x2
+ UML_DSHL(block, I2, I2, 16); // dshl i2,i2,16
+ UML_DOR(block, I0, I0, I2); // dor i0,i0,i2
+ UML_DLOAD(block, I2, block1_2, I1, SIZE_WORD, SCALE_x2); // dload i2,[block1_2],i1,word,scale_x2
+ UML_DOR(block, I0, I0, I2); // dor i0,i0,i2
+ UML_RET(block); // ret
+
+ UML_LABEL(block, label++); // label2:
break;
case MEM_ACCESSOR_PM_WRITE48:
- UML_CMP(block, I1, IRAM_BLOCK0_START); // cmp i1,IRAM_BLOCK0_START
- UML_JMPc(block, COND_B, label); // jb label1
- UML_CMP(block, I1, IRAM_BLOCK0_END); // cmp i1,IRAM_BLOCK0_END
- UML_JMPc(block, COND_A, label); // ja label1
+ UML_CMP(block, I1, IRAM_BLOCK0_START); // cmp i1,IRAM_BLOCK0_START
+ UML_JMPc(block, COND_B, label); // jb label1
+ UML_CMP(block, I1, IRAM_BLOCK0_END); // cmp i1,IRAM_BLOCK0_END
+ UML_JMPc(block, COND_A, label); // ja label1
// 0x20000 ... 0x27fff
- UML_AND(block, I1, I1, 0x7fff); // and i1,i1,0x7fff
- UML_MULS(block, I1, I1, I1, 3); // muls i1,3
- UML_DSTORE(block, block0_2, I1, I0, SIZE_WORD, SCALE_x2); // dstore [block0_2],i1,i0,word,scale_x2
- UML_DSHR(block, I0, I0, 16); // dshr i0,i0,16
- UML_DSTORE(block, block0_1, I1, I0, SIZE_WORD, SCALE_x2); // dstore [block0_1],i1,i0,word,scale_x2
- UML_DSHR(block, I0, I0, 16); // dshr i0,i0,16
- UML_DSTORE(block, block0, I1, I0, SIZE_WORD, SCALE_x2); // dstore [block0],i1,i0,word,scale_x2
+ UML_AND(block, I1, I1, 0x7fff); // and i1,i1,0x7fff
+ UML_MULS(block, I1, I1, I1, 3); // muls i1,3
+ UML_DSTORE(block, block0_2, I1, I0, SIZE_WORD, SCALE_x2); // dstore [block0_2],i1,i0,word,scale_x2
+ UML_DSHR(block, I0, I0, 16); // dshr i0,i0,16
+ UML_DSTORE(block, block0_1, I1, I0, SIZE_WORD, SCALE_x2); // dstore [block0_1],i1,i0,word,scale_x2
+ UML_DSHR(block, I0, I0, 16); // dshr i0,i0,16
+ UML_DSTORE(block, block0, I1, I0, SIZE_WORD, SCALE_x2); // dstore [block0],i1,i0,word,scale_x2
UML_MOV(block, mem(&m_core->force_recompile), 1);
- UML_RET(block); // ret
+ UML_RET(block); // ret
- UML_LABEL(block, label++); // label1:
- UML_CMP(block, I1, IRAM_BLOCK1_START); // cmp i1,IRAM_BLOCK1_START
- UML_JMPc(block, COND_B, label); // jb label2
- UML_CMP(block, I1, IRAM_BLOCK1_END); // cmp i1,IRAM_BLOCK1_END
- UML_JMPc(block, COND_A, label); // ja label2
+ UML_LABEL(block, label++); // label1:
+ UML_CMP(block, I1, IRAM_BLOCK1_START); // cmp i1,IRAM_BLOCK1_START
+ UML_JMPc(block, COND_B, label); // jb label2
+ UML_CMP(block, I1, IRAM_BLOCK1_END); // cmp i1,IRAM_BLOCK1_END
+ UML_JMPc(block, COND_A, label); // ja label2
// 0x28000 ... 0x3ffff
- UML_AND(block, I1, I1, 0x7fff); // and i1,i1,0x7fff (block 1 is mirrored in 0x28000...2ffff, 0x30000...0x37fff and 0x38000...3ffff)
- UML_MULS(block, I1, I1, I1, 3); // muls i1,3
- UML_DSTORE(block, block1_2, I1, I0, SIZE_WORD, SCALE_x2); // dstore [block1_2],i1,i0,word,scale_x2
- UML_DSHR(block, I0, I0, 16); // dshr i0,i0,16
- UML_DSTORE(block, block1_1, I1, I0, SIZE_WORD, SCALE_x2); // dstore [block1_1],i1,i0,word,scale_x2
- UML_DSHR(block, I0, I0, 16); // dshr i0,i0,16
- UML_DSTORE(block, block1, I1, I0, SIZE_WORD, SCALE_x2); // dstore [block1],i1,i0,word,scale_x2
- UML_RET(block); // ret
-
- UML_LABEL(block, label++); // label2:
+ UML_AND(block, I1, I1, 0x7fff); // and i1,i1,0x7fff (block 1 is mirrored in 0x28000...2ffff, 0x30000...0x37fff and 0x38000...3ffff)
+ UML_MULS(block, I1, I1, I1, 3); // muls i1,3
+ UML_DSTORE(block, block1_2, I1, I0, SIZE_WORD, SCALE_x2); // dstore [block1_2],i1,i0,word,scale_x2
+ UML_DSHR(block, I0, I0, 16); // dshr i0,i0,16
+ UML_DSTORE(block, block1_1, I1, I0, SIZE_WORD, SCALE_x2); // dstore [block1_1],i1,i0,word,scale_x2
+ UML_DSHR(block, I0, I0, 16); // dshr i0,i0,16
+ UML_DSTORE(block, block1, I1, I0, SIZE_WORD, SCALE_x2); // dstore [block1],i1,i0,word,scale_x2
+ UML_RET(block); // ret
+
+ UML_LABEL(block, label++); // label2:
break;
case MEM_ACCESSOR_PM_READ32:
- UML_CMP(block, I1, IRAM_BLOCK0_START); // cmp i1,IRAM_BLOCK0_START
- UML_JMPc(block, COND_B, label); // jb label1
- UML_CMP(block, I1, IRAM_BLOCK0_END); // cmp i1,IRAM_BLOCK0_END
- UML_JMPc(block, COND_A, label); // ja label1
-
+ UML_CMP(block, I1, IRAM_BLOCK0_START); // cmp i1,IRAM_BLOCK0_START
+ UML_JMPc(block, COND_B, label); // jb label1
+ UML_CMP(block, I1, IRAM_BLOCK0_END); // cmp i1,IRAM_BLOCK0_END
+ UML_JMPc(block, COND_A, label); // ja label1
+
// 0x20000 ... 0x27fff
- UML_AND(block, I1, I1, 0x7fff); // and i1,i1,0x7fff
- UML_MULS(block, I1, I1, I1, 3); // muls i1,3
- UML_LOAD(block, I0, block0, I1, SIZE_WORD, SCALE_x2); // load i0,[block0],i1,word,scale_x2
- UML_SHL(block, I0, I0, 16); // shl i0,i0,16
- UML_LOAD(block, I2, block0_1, I1, SIZE_WORD, SCALE_x2); // load i2,[block0_1],i1,word,scale_x2
- UML_OR(block, I0, I0, I2); // or i0,i0,i2
- UML_RET(block); // ret
-
- UML_LABEL(block, label++); // label1:
- UML_CMP(block, I1, IRAM_BLOCK1_START); // cmp i1,IRAM_BLOCK1_START
- UML_JMPc(block, COND_B, label); // jb label2
- UML_CMP(block, I1, IRAM_BLOCK1_END); // cmp i1,IRAM_BLOCK1_END
- UML_JMPc(block, COND_A, label); // ja label2
+ UML_AND(block, I1, I1, 0x7fff); // and i1,i1,0x7fff
+ UML_MULS(block, I1, I1, I1, 3); // muls i1,3
+ UML_LOAD(block, I0, block0, I1, SIZE_WORD, SCALE_x2); // load i0,[block0],i1,word,scale_x2
+ UML_SHL(block, I0, I0, 16); // shl i0,i0,16
+ UML_LOAD(block, I2, block0_1, I1, SIZE_WORD, SCALE_x2); // load i2,[block0_1],i1,word,scale_x2
+ UML_OR(block, I0, I0, I2); // or i0,i0,i2
+ UML_RET(block); // ret
+
+ UML_LABEL(block, label++); // label1:
+ UML_CMP(block, I1, IRAM_BLOCK1_START); // cmp i1,IRAM_BLOCK1_START
+ UML_JMPc(block, COND_B, label); // jb label2
+ UML_CMP(block, I1, IRAM_BLOCK1_END); // cmp i1,IRAM_BLOCK1_END
+ UML_JMPc(block, COND_A, label); // ja label2
// 0x28000 ... 0x3ffff
- UML_AND(block, I1, I1, 0x7fff); // and i1,i1,0x7fff (block 1 is mirrored in 0x28000...2ffff, 0x30000...0x37fff and 0x38000...3ffff)
- UML_MULS(block, I1, I1, I1, 3); // muls i1,3
- UML_LOAD(block, I0, block1, I1, SIZE_WORD, SCALE_x2); // load i0,[block1],i1,word,scale_x2
- UML_SHL(block, I0, I0, 16); // shl i0,i0,16
- UML_LOAD(block, I2, block1_1, I1, SIZE_WORD, SCALE_x2); // load i2,[block1_1],i1,word,scale_x2
- UML_OR(block, I0, I0, I2); // or i0,i0,i2
- UML_RET(block); // ret
-
- UML_LABEL(block, label++); // label2:
+ UML_AND(block, I1, I1, 0x7fff); // and i1,i1,0x7fff (block 1 is mirrored in 0x28000...2ffff, 0x30000...0x37fff and 0x38000...3ffff)
+ UML_MULS(block, I1, I1, I1, 3); // muls i1,3
+ UML_LOAD(block, I0, block1, I1, SIZE_WORD, SCALE_x2); // load i0,[block1],i1,word,scale_x2
+ UML_SHL(block, I0, I0, 16); // shl i0,i0,16
+ UML_LOAD(block, I2, block1_1, I1, SIZE_WORD, SCALE_x2); // load i2,[block1_1],i1,word,scale_x2
+ UML_OR(block, I0, I0, I2); // or i0,i0,i2
+ UML_RET(block); // ret
+
+ UML_LABEL(block, label++); // label2:
break;
case MEM_ACCESSOR_PM_WRITE32:
- UML_CMP(block, I1, IRAM_BLOCK0_START); // cmp i1,IRAM_BLOCK0_START
- UML_JMPc(block, COND_B, label); // jb label1
- UML_CMP(block, I1, IRAM_BLOCK0_END); // cmp i1,IRAM_BLOCK0_END
- UML_JMPc(block, COND_A, label); // ja label1
+ UML_CMP(block, I1, IRAM_BLOCK0_START); // cmp i1,IRAM_BLOCK0_START
+ UML_JMPc(block, COND_B, label); // jb label1
+ UML_CMP(block, I1, IRAM_BLOCK0_END); // cmp i1,IRAM_BLOCK0_END
+ UML_JMPc(block, COND_A, label); // ja label1
// 0x20000 ... 0x27fff
- UML_AND(block, I1, I1, 0x7fff); // and i1,i1,0x7fff
- UML_MULS(block, I1, I1, I1, 3); // muls i1,3
- UML_STORE(block, block0_1, I1, I0, SIZE_WORD, SCALE_x2); // store [block0_1],i1,i0,word,scale_x2
- UML_SHR(block, I0, I0, 16); // shr i0,i0,16
- UML_STORE(block, block0, I1, I0, SIZE_WORD, SCALE_x2); // store [block0],i1,i0,word,scale_x2
- UML_RET(block); // ret
-
- UML_LABEL(block, label++); // label1:
- UML_CMP(block, I1, IRAM_BLOCK1_START); // cmp i1,IRAM_BLOCK1_START
- UML_JMPc(block, COND_B, label); // jb label2
- UML_CMP(block, I1, IRAM_BLOCK1_END); // cmp i1,IRAM_BLOCK1_END
- UML_JMPc(block, COND_A, label); // ja label2
+ UML_AND(block, I1, I1, 0x7fff); // and i1,i1,0x7fff
+ UML_MULS(block, I1, I1, I1, 3); // muls i1,3
+ UML_STORE(block, block0_1, I1, I0, SIZE_WORD, SCALE_x2); // store [block0_1],i1,i0,word,scale_x2
+ UML_SHR(block, I0, I0, 16); // shr i0,i0,16
+ UML_STORE(block, block0, I1, I0, SIZE_WORD, SCALE_x2); // store [block0],i1,i0,word,scale_x2
+ UML_RET(block); // ret
+
+ UML_LABEL(block, label++); // label1:
+ UML_CMP(block, I1, IRAM_BLOCK1_START); // cmp i1,IRAM_BLOCK1_START
+ UML_JMPc(block, COND_B, label); // jb label2
+ UML_CMP(block, I1, IRAM_BLOCK1_END); // cmp i1,IRAM_BLOCK1_END
+ UML_JMPc(block, COND_A, label); // ja label2
// 0x28000 ... 0x3ffff
- UML_AND(block, I1, I1, 0x7fff); // and i1,i1,0x7fff (block 1 is mirrored in 0x28000...2ffff, 0x30000...0x37fff and 0x38000...3ffff)
- UML_MULS(block, I1, I1, I1, 3); // muls i1,3
- UML_STORE(block, block1_1, I1, I0, SIZE_WORD, SCALE_x2); // store [block1_1],i1,i0,word,scale_x2
- UML_SHR(block, I0, I0, 16); // shr i0,i0,16
- UML_STORE(block, block1, I1, I0, SIZE_WORD, SCALE_x2); // store [block1],i1,i0,word,scale_x2
- UML_RET(block); // ret
-
- UML_LABEL(block, label++); // label2:
+ UML_AND(block, I1, I1, 0x7fff); // and i1,i1,0x7fff (block 1 is mirrored in 0x28000...2ffff, 0x30000...0x37fff and 0x38000...3ffff)
+ UML_MULS(block, I1, I1, I1, 3); // muls i1,3
+ UML_STORE(block, block1_1, I1, I0, SIZE_WORD, SCALE_x2); // store [block1_1],i1,i0,word,scale_x2
+ UML_SHR(block, I0, I0, 16); // shr i0,i0,16
+ UML_STORE(block, block1, I1, I0, SIZE_WORD, SCALE_x2); // store [block1],i1,i0,word,scale_x2
+ UML_RET(block); // ret
+
+ UML_LABEL(block, label++); // label2:
break;
case MEM_ACCESSOR_DM_READ32:
- UML_CMP(block, I1, IRAM_END); // cmp i1,IRAM_END
- UML_JMPc(block, COND_BE, label); // jbe label1
+ UML_CMP(block, I1, IRAM_END); // cmp i1,IRAM_END
+ UML_JMPc(block, COND_BE, label); // jbe label1
// 0x80000 ...
- UML_SHL(block, I1, I1, 2); // shl i1,i1,2
- UML_READ(block, I0, I1, SIZE_DWORD, SPACE_DATA); // read i0,i1,dword,SPACE_DATA
+ UML_SHL(block, I1, I1, 2); // shl i1,i1,2
+ UML_READ(block, I0, I1, SIZE_DWORD, SPACE_DATA); // read i0,i1,dword,SPACE_DATA
UML_RET(block);
- UML_LABEL(block, label++); // label1:
- UML_CMP(block, I1, IRAM_BLOCK0_START); // cmp i1,IRAM_BLOCK0_START
- UML_JMPc(block, COND_B, label); // jb label2
- UML_CMP(block, I1, IRAM_BLOCK0_END); // cmp i1,IRAM_BLOCK0_END
- UML_JMPc(block, COND_A, label); // ja label2
+ UML_LABEL(block, label++); // label1:
+ UML_CMP(block, I1, IRAM_BLOCK0_START); // cmp i1,IRAM_BLOCK0_START
+ UML_JMPc(block, COND_B, label); // jb label2
+ UML_CMP(block, I1, IRAM_BLOCK0_END); // cmp i1,IRAM_BLOCK0_END
+ UML_JMPc(block, COND_A, label); // ja label2
// 0x20000 ... 0x27fff
- UML_AND(block, I1, I1, 0x7fff); // and i1,i1,0x7fff
- UML_LOAD(block, I0, block0, I1, SIZE_WORD, SCALE_x4); // load i0,[block0],i1,word,scale_x4
- UML_SHL(block, I0, I0, 16); // shl i0,i0,16
- UML_LOAD(block, I2, block0_1, I1, SIZE_WORD, SCALE_x4); // load i2,[block0_1],i1,word,scale_x4
- UML_OR(block, I0, I0, I2); // or i0,i0,i2
+ UML_AND(block, I1, I1, 0x7fff); // and i1,i1,0x7fff
+ UML_LOAD(block, I0, block0, I1, SIZE_WORD, SCALE_x4); // load i0,[block0],i1,word,scale_x4
+ UML_SHL(block, I0, I0, 16); // shl i0,i0,16
+ UML_LOAD(block, I2, block0_1, I1, SIZE_WORD, SCALE_x4); // load i2,[block0_1],i1,word,scale_x4
+ UML_OR(block, I0, I0, I2); // or i0,i0,i2
UML_RET(block);
- UML_LABEL(block, label++); // label2:
- UML_CMP(block, I1, IRAM_BLOCK1_START); // cmp i1,IRAM_BLOCK1_START
- UML_JMPc(block, COND_B, label); // jb label3
- UML_CMP(block, I1, IRAM_BLOCK1_END); // cmp i1,IRAM_BLOCK1_END
- UML_JMPc(block, COND_A, label); // ja label3
+ UML_LABEL(block, label++); // label2:
+ UML_CMP(block, I1, IRAM_BLOCK1_START); // cmp i1,IRAM_BLOCK1_START
+ UML_JMPc(block, COND_B, label); // jb label3
+ UML_CMP(block, I1, IRAM_BLOCK1_END); // cmp i1,IRAM_BLOCK1_END
+ UML_JMPc(block, COND_A, label); // ja label3
// 0x28000 ... 0x3ffff
- UML_AND(block, I1, I1, 0x7fff); // and i1,i1,0x7fff
- UML_LOAD(block, I0, block1, I1, SIZE_WORD, SCALE_x4); // load i0,[block1],i1,word,scale_x4
- UML_SHL(block, I0, I0, 16); // shl i0,i0,16
- UML_LOAD(block, I2, block1_1, I1, SIZE_WORD, SCALE_x4); // load i2,[block1_1],i1,word,scale_x4
- UML_OR(block, I0, I0, I2); // or i0,i0,i2
+ UML_AND(block, I1, I1, 0x7fff); // and i1,i1,0x7fff
+ UML_LOAD(block, I0, block1, I1, SIZE_WORD, SCALE_x4); // load i0,[block1],i1,word,scale_x4
+ UML_SHL(block, I0, I0, 16); // shl i0,i0,16
+ UML_LOAD(block, I2, block1_1, I1, SIZE_WORD, SCALE_x4); // load i2,[block1_1],i1,word,scale_x4
+ UML_OR(block, I0, I0, I2); // or i0,i0,i2
UML_RET(block);
- UML_LABEL(block, label++); // Label3:
- UML_CMP(block, I1, IOP_REGISTER_END); // cmp i1,IOP_REGISTER_END
- UML_JMPc(block, COND_A, label); // ja label4
+ UML_LABEL(block, label++); // Label3:
+ UML_CMP(block, I1, IOP_REGISTER_END); // cmp i1,IOP_REGISTER_END
+ UML_JMPc(block, COND_A, label); // ja label4
// IOP registers
- UML_MOV(block, mem(&m_core->arg0), I1); // mov [m_core->arg0],i1
- UML_CALLC(block, cfunc_read_iop, this); // callc cfunc_read_iop
- UML_MOV(block, I0, mem(&m_core->arg1)); // mov i0,[m_core->arg1]
+ UML_MOV(block, mem(&m_core->arg0), I1); // mov [m_core->arg0],i1
+ UML_CALLC(block, cfunc_read_iop, this); // callc cfunc_read_iop
+ UML_MOV(block, I0, mem(&m_core->arg1)); // mov i0,[m_core->arg1]
UML_RET(block);
- UML_LABEL(block, label++); // label4:
- UML_CMP(block, I1, IRAM_SHORT_BLOCK0_START); // cmp i1,IRAM_SHORT_BLOCK0_START
- UML_JMPc(block, COND_B, label+1); // jb label6
- UML_CMP(block, I1, IRAM_SHORT_BLOCK0_END); // cmp i1,IRAM_SHORT_BLOCK0_END
- UML_JMPc(block, COND_A, label+1); // ja label6
+ UML_LABEL(block, label++); // label4:
+ UML_CMP(block, I1, IRAM_SHORT_BLOCK0_START); // cmp i1,IRAM_SHORT_BLOCK0_START
+ UML_JMPc(block, COND_B, label+1); // jb label6
+ UML_CMP(block, I1, IRAM_SHORT_BLOCK0_END); // cmp i1,IRAM_SHORT_BLOCK0_END
+ UML_JMPc(block, COND_A, label+1); // ja label6
// 0x40000 ... 0x4ffff
- UML_AND(block, I1, I1, 0xffff); // and i1,i1,0xffff
- UML_XOR(block, I1, I1, 1); // xor i1,i1,1
- UML_TEST(block, mem(&m_core->mode1), 0x4000); // test [m_core->mode1],0x4000
- UML_JMPc(block, COND_Z, label); // jz label5
- UML_LOADS(block, I0, block0, I1, SIZE_WORD, SCALE_x2); // loads i0,[block0],i1,word,scale_x2
+ UML_AND(block, I1, I1, 0xffff); // and i1,i1,0xffff
+ UML_XOR(block, I1, I1, 1); // xor i1,i1,1
+ UML_TEST(block, mem(&m_core->mode1), 0x4000); // test [m_core->mode1],0x4000
+ UML_JMPc(block, COND_Z, label); // jz label5
+ UML_LOADS(block, I0, block0, I1, SIZE_WORD, SCALE_x2); // loads i0,[block0],i1,word,scale_x2
UML_RET(block);
- UML_LABEL(block, label++); // label5:
- UML_LOAD(block, I0, block0, I1, SIZE_WORD, SCALE_x2); // load i0,[block0],i1,word,scale_x2
+ UML_LABEL(block, label++); // label5:
+ UML_LOAD(block, I0, block0, I1, SIZE_WORD, SCALE_x2); // load i0,[block0],i1,word,scale_x2
UML_RET(block);
- UML_LABEL(block, label++); // label6:
- UML_CMP(block, I1, IRAM_SHORT_BLOCK1_START); // cmp i1,IRAM_SHORT_BLOCK1_START
- UML_JMPc(block, COND_B, label+1); // jb label8
- UML_CMP(block, I1, IRAM_SHORT_BLOCK1_END); // cmp i1,IRAM_SHORT_BLOCK1_END
- UML_JMPc(block, COND_A, label+1); // ja label8
+ UML_LABEL(block, label++); // label6:
+ UML_CMP(block, I1, IRAM_SHORT_BLOCK1_START); // cmp i1,IRAM_SHORT_BLOCK1_START
+ UML_JMPc(block, COND_B, label+1); // jb label8
+ UML_CMP(block, I1, IRAM_SHORT_BLOCK1_END); // cmp i1,IRAM_SHORT_BLOCK1_END
+ UML_JMPc(block, COND_A, label+1); // ja label8
// 0x50000 ... 0x7ffff
- UML_AND(block, I1, I1, 0xffff); // and i1,i1,0xffff
- UML_XOR(block, I1, I1, 1); // xor i1,i1,1
- UML_TEST(block, mem(&m_core->mode1), 0x4000); // test [m_core->mode1],0x4000
- UML_JMPc(block, COND_Z, label); // jz label7
- UML_LOADS(block, I0, block1, I1, SIZE_WORD, SCALE_x2); // loads i0,[block1],i1,word,scale_x2
+ UML_AND(block, I1, I1, 0xffff); // and i1,i1,0xffff
+ UML_XOR(block, I1, I1, 1); // xor i1,i1,1
+ UML_TEST(block, mem(&m_core->mode1), 0x4000); // test [m_core->mode1],0x4000
+ UML_JMPc(block, COND_Z, label); // jz label7
+ UML_LOADS(block, I0, block1, I1, SIZE_WORD, SCALE_x2); // loads i0,[block1],i1,word,scale_x2
UML_RET(block);
- UML_LABEL(block, label++); // label7:
- UML_LOAD(block, I0, block1, I1, SIZE_WORD, SCALE_x2); // load i0,[block1],i1,word,scale_x2
+ UML_LABEL(block, label++); // label7:
+ UML_LOAD(block, I0, block1, I1, SIZE_WORD, SCALE_x2); // load i0,[block1],i1,word,scale_x2
UML_RET(block);
- UML_LABEL(block, label++); // label8:
+ UML_LABEL(block, label++); // label8:
break;
case MEM_ACCESSOR_DM_WRITE32:
@@ -583,69 +583,69 @@ void adsp21062_device::static_generate_memory_accessor(MEM_ACCESSOR_TYPE type, c
#endif
- UML_CMP(block, I1, IRAM_END); // cmp i1,IRAM_END
- UML_JMPc(block, COND_BE, label); // jbe label1
+ UML_CMP(block, I1, IRAM_END); // cmp i1,IRAM_END
+ UML_JMPc(block, COND_BE, label); // jbe label1
// 0x80000 ...
- UML_SHL(block, I1, I1, 2); // shl i1,i1,2
- UML_WRITE(block, I1, I0, SIZE_DWORD, SPACE_DATA); // write i1,i0,dword,SPACE_DATA
+ UML_SHL(block, I1, I1, 2); // shl i1,i1,2
+ UML_WRITE(block, I1, I0, SIZE_DWORD, SPACE_DATA); // write i1,i0,dword,SPACE_DATA
UML_RET(block);
- UML_LABEL(block, label++); // label1:
- UML_CMP(block, I1, IRAM_BLOCK0_START); // cmp i1,IRAM_BLOCK0_START
- UML_JMPc(block, COND_B, label); // jb label2
- UML_CMP(block, I1, IRAM_BLOCK0_END); // cmp i1,IRAM_BLOCK0_END
- UML_JMPc(block, COND_A, label); // ja label2
+ UML_LABEL(block, label++); // label1:
+ UML_CMP(block, I1, IRAM_BLOCK0_START); // cmp i1,IRAM_BLOCK0_START
+ UML_JMPc(block, COND_B, label); // jb label2
+ UML_CMP(block, I1, IRAM_BLOCK0_END); // cmp i1,IRAM_BLOCK0_END
+ UML_JMPc(block, COND_A, label); // ja label2
// 0x20000 ... 0x27fff
- UML_AND(block, I1, I1, 0x7fff); // and i1,i1,0x7fff
- UML_STORE(block, block0_1, I1, I0, SIZE_WORD, SCALE_x4); // store [block0_1],i1,i0,word,scale_x4
- UML_SHR(block, I0, I0, 16); // shr i0,i0,16
- UML_STORE(block, block0, I1, I0, SIZE_WORD, SCALE_x4); // store [block0],i1,i0,word,scale_x4
+ UML_AND(block, I1, I1, 0x7fff); // and i1,i1,0x7fff
+ UML_STORE(block, block0_1, I1, I0, SIZE_WORD, SCALE_x4); // store [block0_1],i1,i0,word,scale_x4
+ UML_SHR(block, I0, I0, 16); // shr i0,i0,16
+ UML_STORE(block, block0, I1, I0, SIZE_WORD, SCALE_x4); // store [block0],i1,i0,word,scale_x4
UML_RET(block);
- UML_LABEL(block, label++); // label2:
- UML_CMP(block, I1, IRAM_BLOCK1_START); // cmp i1,IRAM_BLOCK1_START
- UML_JMPc(block, COND_B, label); // jb label3
- UML_CMP(block, I1, IRAM_BLOCK1_END); // cmp i1,IRAM_BLOCK1_END
- UML_JMPc(block, COND_A, label); // ja label3
+ UML_LABEL(block, label++); // label2:
+ UML_CMP(block, I1, IRAM_BLOCK1_START); // cmp i1,IRAM_BLOCK1_START
+ UML_JMPc(block, COND_B, label); // jb label3
+ UML_CMP(block, I1, IRAM_BLOCK1_END); // cmp i1,IRAM_BLOCK1_END
+ UML_JMPc(block, COND_A, label); // ja label3
// 0x28000 ... 0x3ffff
- UML_AND(block, I1, I1, 0x7fff); // and i1,i1,0x7fff
- UML_STORE(block, block1_1, I1, I0, SIZE_WORD, SCALE_x4); // store [block1_1],i1,i0,word,scale_x4
- UML_SHR(block, I0, I0, 16); // shr i0,i0,16
- UML_STORE(block, block1, I1, I0, SIZE_WORD, SCALE_x4); // store [block1],i1,i0,word,scale_x4
+ UML_AND(block, I1, I1, 0x7fff); // and i1,i1,0x7fff
+ UML_STORE(block, block1_1, I1, I0, SIZE_WORD, SCALE_x4); // store [block1_1],i1,i0,word,scale_x4
+ UML_SHR(block, I0, I0, 16); // shr i0,i0,16
+ UML_STORE(block, block1, I1, I0, SIZE_WORD, SCALE_x4); // store [block1],i1,i0,word,scale_x4
UML_RET(block);
- UML_LABEL(block, label++); // Label3:
- UML_CMP(block, I1, IOP_REGISTER_END); // cmp i1,IOP_REGISTER_END
- UML_JMPc(block, COND_A, label); // ja label4
+ UML_LABEL(block, label++); // Label3:
+ UML_CMP(block, I1, IOP_REGISTER_END); // cmp i1,IOP_REGISTER_END
+ UML_JMPc(block, COND_A, label); // ja label4
// IOP registers
- UML_MOV(block, mem(&m_core->arg0), I1); // mov [m_core->arg0],i1
- UML_MOV(block, mem(&m_core->arg1), I0); // mov [m_core->arg1],i0
- UML_CALLC(block, cfunc_write_iop, this); // callc cfunc_write_iop
+ UML_MOV(block, mem(&m_core->arg0), I1); // mov [m_core->arg0],i1
+ UML_MOV(block, mem(&m_core->arg1), I0); // mov [m_core->arg1],i0
+ UML_CALLC(block, cfunc_write_iop, this); // callc cfunc_write_iop
UML_RET(block);
- UML_LABEL(block, label++); // label4:
- UML_CMP(block, I1, IRAM_SHORT_BLOCK0_START); // cmp i1,IRAM_SHORT_BLOCK0_START
- UML_JMPc(block, COND_B, label); // jb label5
- UML_CMP(block, I1, IRAM_SHORT_BLOCK0_END); // cmp i1,IRAM_SHORT_BLOCK0_END
- UML_JMPc(block, COND_A, label); // ja label5
+ UML_LABEL(block, label++); // label4:
+ UML_CMP(block, I1, IRAM_SHORT_BLOCK0_START); // cmp i1,IRAM_SHORT_BLOCK0_START
+ UML_JMPc(block, COND_B, label); // jb label5
+ UML_CMP(block, I1, IRAM_SHORT_BLOCK0_END); // cmp i1,IRAM_SHORT_BLOCK0_END
+ UML_JMPc(block, COND_A, label); // ja label5
// 0x40000 ... 0x4ffff
- UML_AND(block, I1, I1, 0xffff); // and i1,i1,0xffff
- UML_XOR(block, I1, I1, 1); // xor i1,i1,1
- UML_STORE(block, block0, I1, I0, SIZE_WORD, SCALE_x2); // store [block0],i1,i0,word,scale_x2
+ UML_AND(block, I1, I1, 0xffff); // and i1,i1,0xffff
+ UML_XOR(block, I1, I1, 1); // xor i1,i1,1
+ UML_STORE(block, block0, I1, I0, SIZE_WORD, SCALE_x2); // store [block0],i1,i0,word,scale_x2
UML_RET(block);
- UML_LABEL(block, label++); // label5:
- UML_CMP(block, I1, IRAM_SHORT_BLOCK1_START); // cmp i1,IRAM_SHORT_BLOCK1_START
- UML_JMPc(block, COND_B, label); // jb label6
- UML_CMP(block, I1, IRAM_SHORT_BLOCK1_END); // cmp i1,IRAM_SHORT_BLOCK1_END
- UML_JMPc(block, COND_A, label); // ja label6
+ UML_LABEL(block, label++); // label5:
+ UML_CMP(block, I1, IRAM_SHORT_BLOCK1_START); // cmp i1,IRAM_SHORT_BLOCK1_START
+ UML_JMPc(block, COND_B, label); // jb label6
+ UML_CMP(block, I1, IRAM_SHORT_BLOCK1_END); // cmp i1,IRAM_SHORT_BLOCK1_END
+ UML_JMPc(block, COND_A, label); // ja label6
// 0x50000 ... 0x7ffff
- UML_AND(block, I1, I1, 0xffff); // and i1,i1,0xffff
- UML_XOR(block, I1, I1, 1); // xor i1,i1,1
- UML_STORE(block, block1, I1, I0, SIZE_WORD, SCALE_x2); // store [block1],i1,i0,word,scale_x2
+ UML_AND(block, I1, I1, 0xffff); // and i1,i1,0xffff
+ UML_XOR(block, I1, I1, 1); // xor i1,i1,1
+ UML_STORE(block, block1, I1, I0, SIZE_WORD, SCALE_x2); // store [block1],i1,i0,word,scale_x2
UML_RET(block);
- UML_LABEL(block, label++); // label6:
+ UML_LABEL(block, label++); // label6:
break;
}
@@ -664,26 +664,26 @@ void adsp21062_device::static_generate_push_pc()
// add a global entry for this
alloc_handle(m_drcuml.get(), &m_push_pc, "push_pc");
- UML_HANDLE(block, *m_push_pc); // handle *m_push_pc
-
- UML_MOV(block, I1, PCSTKP); // mov i1,PCSTKP
- UML_ADD(block, I1, I1, 1); // add i1,i1,1
- UML_CMP(block, I1, 32); // cmp i1,32
- UML_JMPc(block, COND_L,label); // jl label1
- UML_CALLC(block, cfunc_pcstack_overflow, this); // callc cfunc_pcstack_overflow
-
- UML_LABEL(block, label++); // label1:
- UML_CMP(block, I1, 0); // cmp i1,0
- UML_JMPc(block, COND_E, label); // je label2
- UML_AND(block, STKY, STKY, ~0x400000); // and STKY,~0x400000
- UML_JMP(block, label + 1); // jmp label3
- UML_LABEL(block, label++); // label2:
- UML_OR(block, STKY, STKY, 0x400000); // or STKY,0x400000
-
- UML_LABEL(block, label++); // label3:
- UML_MOV(block, PCSTK, I0); // mov PCSTK,pc
- UML_STORE(block, &m_core->pcstack, I1, I0, SIZE_DWORD, SCALE_x4); // store [m_core->pcstack],i1,i0,dword,scale_x4
- UML_MOV(block, PCSTKP, I1); // mov PCSTKP,i1
+ UML_HANDLE(block, *m_push_pc); // handle *m_push_pc
+
+ UML_MOV(block, I1, PCSTKP); // mov i1,PCSTKP
+ UML_ADD(block, I1, I1, 1); // add i1,i1,1
+ UML_CMP(block, I1, 32); // cmp i1,32
+ UML_JMPc(block, COND_L,label); // jl label1
+ UML_CALLC(block, cfunc_pcstack_overflow, this); // callc cfunc_pcstack_overflow
+
+ UML_LABEL(block, label++); // label1:
+ UML_CMP(block, I1, 0); // cmp i1,0
+ UML_JMPc(block, COND_E, label); // je label2
+ UML_AND(block, STKY, STKY, ~0x400000); // and STKY,~0x400000
+ UML_JMP(block, label + 1); // jmp label3
+ UML_LABEL(block, label++); // label2:
+ UML_OR(block, STKY, STKY, 0x400000); // or STKY,0x400000
+
+ UML_LABEL(block, label++); // label3:
+ UML_MOV(block, PCSTK, I0); // mov PCSTK,pc
+ UML_STORE(block, &m_core->pcstack, I1, I0, SIZE_DWORD, SCALE_x4); // store [m_core->pcstack],i1,i0,dword,scale_x4
+ UML_MOV(block, PCSTKP, I1); // mov PCSTKP,i1
UML_RET(block);
@@ -700,26 +700,26 @@ void adsp21062_device::static_generate_pop_pc()
// add a global entry for this
alloc_handle(m_drcuml.get(), &m_pop_pc, "pop_pc");
- UML_HANDLE(block, *m_pop_pc); // handle *m_pop_pc
-
- UML_MOV(block, I1, PCSTKP); // mov i0,PCSTKP
- UML_LOAD(block, I0, &m_core->pcstack, I1, SIZE_DWORD, SCALE_x4); // load i1,[m_core->pcstack],i0,dword,scale_x4
- UML_CMP(block, I1, 0); // cmp i1,0
- UML_JMPc(block, COND_NE, label); // jne label1
- UML_CALLC(block, cfunc_pcstack_underflow, this); // callc cfunc_pcstack_underflow
-
- UML_LABEL(block, label++); // label1:
- UML_SUB(block, I1, I1, 1); // sub i1,i1,1
- UML_CMP(block, I1, 0); // cmp i1,0
- UML_JMPc(block, COND_E, label); // je label2
- UML_AND(block, STKY, STKY, ~0x400000); // and STKY,~0x400000
- UML_JMP(block, label + 1); // jmp label3
- UML_LABEL(block, label++); // label2:
- UML_OR(block, STKY, STKY, 0x400000); // or STKY,0x400000
-
- UML_LABEL(block, label++); // label3:
- UML_MOV(block, PCSTKP, I1); // mov PCSTKP,i1
- UML_MOV(block, PCSTK, I0); // mov PCSTK,i0
+ UML_HANDLE(block, *m_pop_pc); // handle *m_pop_pc
+
+ UML_MOV(block, I1, PCSTKP); // mov i0,PCSTKP
+ UML_LOAD(block, I0, &m_core->pcstack, I1, SIZE_DWORD, SCALE_x4); // load i1,[m_core->pcstack],i0,dword,scale_x4
+ UML_CMP(block, I1, 0); // cmp i1,0
+ UML_JMPc(block, COND_NE, label); // jne label1
+ UML_CALLC(block, cfunc_pcstack_underflow, this); // callc cfunc_pcstack_underflow
+
+ UML_LABEL(block, label++); // label1:
+ UML_SUB(block, I1, I1, 1); // sub i1,i1,1
+ UML_CMP(block, I1, 0); // cmp i1,0
+ UML_JMPc(block, COND_E, label); // je label2
+ UML_AND(block, STKY, STKY, ~0x400000); // and STKY,~0x400000
+ UML_JMP(block, label + 1); // jmp label3
+ UML_LABEL(block, label++); // label2:
+ UML_OR(block, STKY, STKY, 0x400000); // or STKY,0x400000
+
+ UML_LABEL(block, label++); // label3:
+ UML_MOV(block, PCSTKP, I1); // mov PCSTKP,i1
+ UML_MOV(block, PCSTK, I0); // mov PCSTK,i0
UML_RET(block);
@@ -737,28 +737,28 @@ void adsp21062_device::static_generate_push_loop()
// add a global entry for this
alloc_handle(m_drcuml.get(), &m_push_loop, "push_loop");
- UML_HANDLE(block, *m_push_loop); // handle *m_push_loop
+ UML_HANDLE(block, *m_push_loop); // handle *m_push_loop
- UML_MOV(block, I2, LSTKP); // mov i2,LSTKP
- UML_ADD(block, I2, I2, 1); // add i2,1
- UML_CMP(block, I2, 6); // cmp i2,6
- UML_JMPc(block, COND_L, label); // jl label1
- UML_CALLC(block, cfunc_loopstack_overflow, this); // callc cfunc_loopstack_overflow
+ UML_MOV(block, I2, LSTKP); // mov i2,LSTKP
+ UML_ADD(block, I2, I2, 1); // add i2,1
+ UML_CMP(block, I2, 6); // cmp i2,6
+ UML_JMPc(block, COND_L, label); // jl label1
+ UML_CALLC(block, cfunc_loopstack_overflow, this); // callc cfunc_loopstack_overflow
- UML_LABEL(block, label++); // label1:
- UML_CMP(block, I2, 0); // cmp i2,0
- UML_JMPc(block, COND_E, label); // je label2
- UML_AND(block, STKY, STKY, ~0x4000000); // and STKY,~0x4000000
- UML_JMP(block, label + 1); // jmp label3
- UML_LABEL(block, label++); // label2:
- UML_OR(block, STKY, STKY, 0x4000000); // or STKY,0x4000000
+ UML_LABEL(block, label++); // label1:
+ UML_CMP(block, I2, 0); // cmp i2,0
+ UML_JMPc(block, COND_E, label); // je label2
+ UML_AND(block, STKY, STKY, ~0x4000000); // and STKY,~0x4000000
+ UML_JMP(block, label + 1); // jmp label3
+ UML_LABEL(block, label++); // label2:
+ UML_OR(block, STKY, STKY, 0x4000000); // or STKY,0x4000000
- UML_LABEL(block, label++); // label3:
+ UML_LABEL(block, label++); // label3:
- UML_STORE(block, m_core->lcstack, I2, I0, SIZE_DWORD, SCALE_x4); // store m_core->lcstack,i2,i0,dword,scale_x4
- UML_STORE(block, m_core->lastack, I2, I1, SIZE_DWORD, SCALE_x4); // store m_core->lastack,i2,i1,dword,scale_x4
- UML_MOV(block, CURLCNTR, I0); // mov CURLCNTR,i0
- UML_MOV(block, LSTKP, I2); // mov LSTKP,i2
+ UML_STORE(block, m_core->lcstack, I2, I0, SIZE_DWORD, SCALE_x4); // store m_core->lcstack,i2,i0,dword,scale_x4
+ UML_STORE(block, m_core->lastack, I2, I1, SIZE_DWORD, SCALE_x4); // store m_core->lastack,i2,i1,dword,scale_x4
+ UML_MOV(block, CURLCNTR, I0); // mov CURLCNTR,i0
+ UML_MOV(block, LSTKP, I2); // mov LSTKP,i2
UML_RET(block);
@@ -774,26 +774,26 @@ void adsp21062_device::static_generate_pop_loop()
// add a global entry for this
alloc_handle(m_drcuml.get(), &m_pop_loop, "pop_loop");
- UML_HANDLE(block, *m_pop_loop); // handle *m_pop_loop
-
- UML_MOV(block, I2, LSTKP); // mov i2,LSTKP
- UML_CMP(block, I2, 0); // cmp i2,0
- UML_JMPc(block, COND_NE, label); // jne label1
- UML_CALLC(block, cfunc_loopstack_underflow, this); // callc cfunc_loopstack_underflow
-
- UML_LABEL(block, label++); // label1:
- UML_SUB(block, I2, I2, 1); // sub i2,i2,1
- UML_CMP(block, I2, 0); // cmp i2,0
- UML_JMPc(block, COND_E, label); // je label2
- UML_AND(block, STKY, STKY, ~0x4000000); // and STKY,~0x4000000
- UML_JMP(block, label + 1); // jmp label3
- UML_LABEL(block, label++); // label2:
- UML_OR(block, STKY, STKY, 0x4000000); // or STKY,0x4000000
-
- UML_LABEL(block, label++); // label3:
- UML_LOAD(block, I0, m_core->lcstack, I2, SIZE_DWORD, SCALE_x4); // load i0,m_core->lcstack,i2,dword,scale_x4
- UML_MOV(block, CURLCNTR, I0); // mov CURLCNTR,i0
- UML_MOV(block, LSTKP, I2); // mov LSTKP,i2
+ UML_HANDLE(block, *m_pop_loop); // handle *m_pop_loop
+
+ UML_MOV(block, I2, LSTKP); // mov i2,LSTKP
+ UML_CMP(block, I2, 0); // cmp i2,0
+ UML_JMPc(block, COND_NE, label); // jne label1
+ UML_CALLC(block, cfunc_loopstack_underflow, this); // callc cfunc_loopstack_underflow
+
+ UML_LABEL(block, label++); // label1:
+ UML_SUB(block, I2, I2, 1); // sub i2,i2,1
+ UML_CMP(block, I2, 0); // cmp i2,0
+ UML_JMPc(block, COND_E, label); // je label2
+ UML_AND(block, STKY, STKY, ~0x4000000); // and STKY,~0x4000000
+ UML_JMP(block, label + 1); // jmp label3
+ UML_LABEL(block, label++); // label2:
+ UML_OR(block, STKY, STKY, 0x4000000); // or STKY,0x4000000
+
+ UML_LABEL(block, label++); // label3:
+ UML_LOAD(block, I0, m_core->lcstack, I2, SIZE_DWORD, SCALE_x4); // load i0,m_core->lcstack,i2,dword,scale_x4
+ UML_MOV(block, CURLCNTR, I0); // mov CURLCNTR,i0
+ UML_MOV(block, LSTKP, I2); // mov LSTKP,i2
UML_RET(block);
@@ -809,24 +809,24 @@ void adsp21062_device::static_generate_push_status()
// add a global entry for this
alloc_handle(m_drcuml.get(), &m_push_status, "push_status");
- UML_HANDLE(block, *m_push_status); // handle *m_push_status
+ UML_HANDLE(block, *m_push_status); // handle *m_push_status
- UML_MOV(block, I2, mem(&m_core->status_stkp)); // mov i2,[status_stkp]
- UML_ADD(block, I2, I2, 1); // add i2,1
- UML_CMP(block, I2, 5); // cmp i2,5
- UML_JMPc(block, COND_L, label); // jl label1
- UML_CALLC(block, cfunc_statusstack_overflow, this); // callc cfunc_statusstack_overflow
+ UML_MOV(block, I2, mem(&m_core->status_stkp)); // mov i2,[status_stkp]
+ UML_ADD(block, I2, I2, 1); // add i2,1
+ UML_CMP(block, I2, 5); // cmp i2,5
+ UML_JMPc(block, COND_L, label); // jl label1
+ UML_CALLC(block, cfunc_statusstack_overflow, this); // callc cfunc_statusstack_overflow
- UML_LABEL(block, label++); // label1:
- UML_CMP(block, I2, 0); // cmp i2,0
- UML_JMPc(block, COND_E, label); // je label2
- UML_AND(block, STKY, STKY, ~0x1000000); // and STKY,~0x1000000
- UML_JMP(block, label + 1); // jmp label3
- UML_LABEL(block, label++); // label2:
- UML_OR(block, STKY, STKY, 0x1000000); // or STKY,0x1000000
+ UML_LABEL(block, label++); // label1:
+ UML_CMP(block, I2, 0); // cmp i2,0
+ UML_JMPc(block, COND_E, label); // je label2
+ UML_AND(block, STKY, STKY, ~0x1000000); // and STKY,~0x1000000
+ UML_JMP(block, label + 1); // jmp label3
+ UML_LABEL(block, label++); // label2:
+ UML_OR(block, STKY, STKY, 0x1000000); // or STKY,0x1000000
- UML_LABEL(block, label++); // label3:
- UML_MOV(block, mem(&m_core->status_stkp), I2); // mov [status_stkp],i2
+ UML_LABEL(block, label++); // label3:
+ UML_MOV(block, mem(&m_core->status_stkp), I2); // mov [status_stkp],i2
//TODO: load MODE1
//TODO: load ASTAT
@@ -845,27 +845,27 @@ void adsp21062_device::static_generate_pop_status()
// add a global entry for this
alloc_handle(m_drcuml.get(), &m_pop_status, "pop_status");
- UML_HANDLE(block, *m_pop_status); // handle *m_pop_status
+ UML_HANDLE(block, *m_pop_status); // handle *m_pop_status
//TODO: store MODE1
//TODO: store ASTAT
-
- UML_MOV(block, I2, mem(&m_core->status_stkp)); // mov i2,[status_stkp]
- UML_CMP(block, I2, 0); // cmp i2,0
- UML_JMPc(block, COND_NE, label); // jl label1
- UML_CALLC(block, cfunc_statusstack_underflow, this); // callc cfunc_statusstack_underflow
-
- UML_LABEL(block, label++); // label1:
- UML_SUB(block, I2, I2, 1); // sub i2,1
- UML_CMP(block, I2, 0); // cmp i2,0
- UML_JMPc(block, COND_E, label); // je label2
- UML_AND(block, STKY, STKY, ~0x1000000); // and STKY,~0x1000000
- UML_JMP(block, label + 1); // jmp label3
- UML_LABEL(block, label++); // label2:
- UML_OR(block, STKY, STKY, 0x1000000); // or STKY,0x1000000
-
- UML_LABEL(block, label++); // label3:
- UML_MOV(block, mem(&m_core->status_stkp), I2); // mov [status_stkp],i2
+
+ UML_MOV(block, I2, mem(&m_core->status_stkp)); // mov i2,[status_stkp]
+ UML_CMP(block, I2, 0); // cmp i2,0
+ UML_JMPc(block, COND_NE, label); // jl label1
+ UML_CALLC(block, cfunc_statusstack_underflow, this); // callc cfunc_statusstack_underflow
+
+ UML_LABEL(block, label++); // label1:
+ UML_SUB(block, I2, I2, 1); // sub i2,1
+ UML_CMP(block, I2, 0); // cmp i2,0
+ UML_JMPc(block, COND_E, label); // je label2
+ UML_AND(block, STKY, STKY, ~0x1000000); // and STKY,~0x1000000
+ UML_JMP(block, label + 1); // jmp label3
+ UML_LABEL(block, label++); // label2:
+ UML_OR(block, STKY, STKY, 0x1000000); // or STKY,0x1000000
+
+ UML_LABEL(block, label++); // label3:
+ UML_MOV(block, mem(&m_core->status_stkp), I2); // mov [status_stkp],i2
UML_RET(block);
@@ -886,30 +886,30 @@ void adsp21062_device::static_generate_exception(UINT8 exception, const char *na
/* add a global entry for this */
alloc_handle(m_drcuml.get(), &exception_handle, name);
- UML_HANDLE(block, *exception_handle); // handle name
+ UML_HANDLE(block, *exception_handle); // handle name
- UML_AND(block, I3, mem(&m_core->irq_pending), IMASK); // and i3,[irq_pending],IMASK
- UML_TZCNT(block, I3, I3); // tzcnt i3,i3
+ UML_AND(block, I3, mem(&m_core->irq_pending), IMASK); // and i3,[irq_pending],IMASK
+ UML_TZCNT(block, I3, I3); // tzcnt i3,i3
- UML_MOV(block, I2, 1); // mov i2,1
- UML_SHL(block, I2, I2, I3); // shl i2,i2,i3
- UML_OR(block, IRPTL, IRPTL, I2); // or IRPTL,i2
+ UML_MOV(block, I2, 1); // mov i2,1
+ UML_SHL(block, I2, I2, I3); // shl i2,i2,i3
+ UML_OR(block, IRPTL, IRPTL, I2); // or IRPTL,i2
UML_XOR(block, mem(&m_core->irq_pending), mem(&m_core->irq_pending), I2); // xor [irq_pending],i2
- UML_MOV(block, mem(&m_core->active_irq_num), I3); // mov [active_irq_num],i3
- UML_MOV(block, mem(&m_core->interrupt_active), 1); // mov [interrupt_active],1
+ UML_MOV(block, mem(&m_core->active_irq_num), I3); // mov [active_irq_num],i3
+ UML_MOV(block, mem(&m_core->interrupt_active), 1); // mov [interrupt_active],1
- UML_CALLH(block, *m_push_pc); // callh m_push_pc
+ UML_CALLH(block, *m_push_pc); // callh m_push_pc
- UML_CMP(block, I3, 6); // cmp i3,6
- UML_JMPc(block, COND_L, label_nopush); // jl label_nopush
- UML_CMP(block, I3, 8); // cmp i3,8
- UML_JMPc(block, COND_G, label_nopush); // jg label_nopush
- UML_CALLH(block, *m_push_status); // callh m_push_status
+ UML_CMP(block, I3, 6); // cmp i3,6
+ UML_JMPc(block, COND_L, label_nopush); // jl label_nopush
+ UML_CMP(block, I3, 8); // cmp i3,8
+ UML_JMPc(block, COND_G, label_nopush); // jg label_nopush
+ UML_CALLH(block, *m_push_status); // callh m_push_status
- UML_LABEL(block, label_nopush); // label_nopush:
- UML_SHL(block, I0, I3, 2); // shl i0,i3,2
- UML_ADD(block, I0, I0, 0x20000); // add i0,0x20000
- UML_HASHJMP(block, 0, I0, *m_nocode); // hashjmp i0,m_nocode
+ UML_LABEL(block, label_nopush); // label_nopush:
+ UML_SHL(block, I0, I3, 2); // shl i0,i3,2
+ UML_ADD(block, I0, I0, 0x20000); // add i0,0x20000
+ UML_HASHJMP(block, 0, I0, *m_nocode); // hashjmp i0,m_nocode
block->end();
}
@@ -924,7 +924,7 @@ void adsp21062_device::static_generate_mode1_ops()
block = m_drcuml->begin_block(128);
alloc_handle(m_drcuml.get(), &m_swap_dag1_0_3, "swap_dag1_0_3");
- UML_HANDLE(block, *m_swap_dag1_0_3); // handle name
+ UML_HANDLE(block, *m_swap_dag1_0_3); // handle name
#if !USE_SWAPDQ
for (int i = 0; i < 4; i++)
{
@@ -956,7 +956,7 @@ void adsp21062_device::static_generate_mode1_ops()
block = m_drcuml->begin_block(128);
alloc_handle(m_drcuml.get(), &m_swap_dag1_4_7, "swap_dag1_4_7");
- UML_HANDLE(block, *m_swap_dag1_4_7); // handle name
+ UML_HANDLE(block, *m_swap_dag1_4_7); // handle name
#if !USE_SWAPDQ
for (int i = 4; i < 8; i++)
{
@@ -988,7 +988,7 @@ void adsp21062_device::static_generate_mode1_ops()
block = m_drcuml->begin_block(128);
alloc_handle(m_drcuml.get(), &m_swap_dag2_0_3, "swap_dag2_0_3");
- UML_HANDLE(block, *m_swap_dag2_0_3); // handle name
+ UML_HANDLE(block, *m_swap_dag2_0_3); // handle name
#if !USE_SWAPDQ
for (int i = 0; i < 4; i++)
{
@@ -1020,7 +1020,7 @@ void adsp21062_device::static_generate_mode1_ops()
block = m_drcuml->begin_block(128);
alloc_handle(m_drcuml.get(), &m_swap_dag2_4_7, "swap_dag2_4_7");
- UML_HANDLE(block, *m_swap_dag2_4_7); // handle name
+ UML_HANDLE(block, *m_swap_dag2_4_7); // handle name
#if !USE_SWAPDQ
for (int i = 4; i < 8; i++)
{
@@ -1052,7 +1052,7 @@ void adsp21062_device::static_generate_mode1_ops()
block = m_drcuml->begin_block(64);
alloc_handle(m_drcuml.get(), &m_swap_r0_7, "swap_r0_7");
- UML_HANDLE(block, *m_swap_r0_7); // handle name
+ UML_HANDLE(block, *m_swap_r0_7); // handle name
#if !USE_SWAPDQ
for (int i = 0; i < 8; i++)
{
@@ -1070,7 +1070,7 @@ void adsp21062_device::static_generate_mode1_ops()
block = m_drcuml->begin_block(64);
alloc_handle(m_drcuml.get(), &m_swap_r8_15, "swap_r8_15");
- UML_HANDLE(block, *m_swap_r8_15); // handle name
+ UML_HANDLE(block, *m_swap_r8_15); // handle name
#if !USE_SWAPDQ
for (int i = 8; i < 16; i++)
{
@@ -1095,8 +1095,8 @@ void adsp21062_device::execute_run_drc()
drcuml_state *drcuml = m_drcuml.get();
int execute_result;
-// if (m_cache_dirty)
-// printf("SHARC cache reset\n");
+// if (m_cache_dirty)
+// printf("SHARC cache reset\n");
/* reset the cache if dirty */
if (m_cache_dirty)
@@ -1173,7 +1173,7 @@ void adsp21062_device::compile_block(offs_t pc)
else
{
UML_LABEL(block, seqhead->pc | 0x80000000); // label seqhead->pc
- UML_HASHJMP(block, 0, seqhead->pc, *m_nocode); // hashjmp <0>,seqhead->pc,nocode
+ UML_HASHJMP(block, 0, seqhead->pc, *m_nocode); // hashjmp <0>,seqhead->pc,nocode
continue;
}
@@ -1202,10 +1202,10 @@ void adsp21062_device::compile_block(offs_t pc)
/* count off cycles and go there */
- generate_update_cycles(block, &compiler, nextpc, TRUE); // <subtract cycles>
+ generate_update_cycles(block, &compiler, nextpc, TRUE); // <subtract cycles>
if (seqlast->next() == nullptr || seqlast->next()->pc != nextpc)
- UML_HASHJMP(block, 0, nextpc, *m_nocode); // hashjmp <mode>,nextpc,nocode
+ UML_HASHJMP(block, 0, nextpc, *m_nocode); // hashjmp <mode>,nextpc,nocode
}
block->end();
@@ -1271,23 +1271,23 @@ void adsp21062_device::static_generate_entry_point()
alloc_handle(m_drcuml.get(), &m_exception[EXCEPTION_INTERRUPT], "exception_interrupt");
alloc_handle(m_drcuml.get(), &m_entry, "entry");
- UML_HANDLE(block, *m_entry); // handle entry
+ UML_HANDLE(block, *m_entry); // handle entry
- load_fast_iregs(block); // <load fastregs>
+ load_fast_iregs(block); // <load fastregs>
- /* check for interrupts */
- UML_CMP(block, mem(&m_core->irq_pending), 0); // cmp [irq_pending],0
- UML_JMPc(block, COND_E, skip); // je skip
- UML_CMP(block, mem(&m_core->interrupt_active), 0); // cmp [interrupt_active],0
- UML_JMPc(block, COND_NE, skip); // jne skip
- UML_TEST(block, mem(&m_core->irq_pending), IMASK); // test [irq_pending],IMASK
- UML_JMPc(block, COND_Z, skip); // jz skip
- UML_TEST(block, mem(&m_core->mode1), MODE1_IRPTEN); // test MODE1,MODE1_IRPTEN
- UML_JMPc(block, COND_Z, skip); // jz skip
+ /* check for interrupts */
+ UML_CMP(block, mem(&m_core->irq_pending), 0); // cmp [irq_pending],0
+ UML_JMPc(block, COND_E, skip); // je skip
+ UML_CMP(block, mem(&m_core->interrupt_active), 0); // cmp [interrupt_active],0
+ UML_JMPc(block, COND_NE, skip); // jne skip
+ UML_TEST(block, mem(&m_core->irq_pending), IMASK); // test [irq_pending],IMASK
+ UML_JMPc(block, COND_Z, skip); // jz skip
+ UML_TEST(block, mem(&m_core->mode1), MODE1_IRPTEN); // test MODE1,MODE1_IRPTEN
+ UML_JMPc(block, COND_Z, skip); // jz skip
- UML_MOV(block, I0, mem(&m_core->pc)); // mov i0,nextpc
- UML_MOV(block, I1, 0); // mov i1,0
- UML_CALLH(block, *m_exception[EXCEPTION_INTERRUPT]); // callh m_exception[EXCEPTION_INTERRUPT]
+ UML_MOV(block, I0, mem(&m_core->pc)); // mov i0,nextpc
+ UML_MOV(block, I1, 0); // mov i1,0
+ UML_CALLH(block, *m_exception[EXCEPTION_INTERRUPT]); // callh m_exception[EXCEPTION_INTERRUPT]
UML_LABEL(block, skip);
@@ -1307,11 +1307,11 @@ void adsp21062_device::static_generate_nocode_handler()
/* generate a hash jump via the current mode and PC */
alloc_handle(m_drcuml.get(), &m_nocode, "nocode");
- UML_HANDLE(block, *m_nocode); // handle nocode
- UML_GETEXP(block, I0); // getexp i0
- UML_MOV(block, mem(&m_core->pc), I0); // mov [pc],i0
- save_fast_iregs(block); // <save fastregs>
- UML_EXIT(block, EXECUTE_MISSING_CODE); // exit EXECUTE_MISSING_CODE
+ UML_HANDLE(block, *m_nocode); // handle nocode
+ UML_GETEXP(block, I0); // getexp i0
+ UML_MOV(block, mem(&m_core->pc), I0); // mov [pc],i0
+ save_fast_iregs(block); // <save fastregs>
+ UML_EXIT(block, EXECUTE_MISSING_CODE); // exit EXECUTE_MISSING_CODE
block->end();
}
@@ -1325,11 +1325,11 @@ void adsp21062_device::static_generate_out_of_cycles()
/* generate a hash jump via the current mode and PC */
alloc_handle(m_drcuml.get(), &m_out_of_cycles, "out_of_cycles");
- UML_HANDLE(block, *m_out_of_cycles); // handle out_of_cycles
- UML_GETEXP(block, I0); // getexp i0
- UML_MOV(block, mem(&m_core->pc), I0); // mov <pc>,i0
- save_fast_iregs(block); // <save fastregs>
- UML_EXIT(block, EXECUTE_OUT_OF_CYCLES); // exit EXECUTE_OUT_OF_CYCLES
+ UML_HANDLE(block, *m_out_of_cycles); // handle out_of_cycles
+ UML_GETEXP(block, I0); // getexp i0
+ UML_MOV(block, mem(&m_core->pc), I0); // mov <pc>,i0
+ save_fast_iregs(block); // <save fastregs>
+ UML_EXIT(block, EXECUTE_OUT_OF_CYCLES); // exit EXECUTE_OUT_OF_CYCLES
block->end();
}
@@ -1338,8 +1338,8 @@ void adsp21062_device::static_generate_out_of_cycles()
void adsp21062_device::generate_sequence_instruction(drcuml_block *block, compiler_state *compiler, const opcode_desc *desc, bool last_delayslot)
{
/* add an entry for the log */
-// if (m_drcuml->logging() && !(desc->flags & OPFLAG_VIRTUAL_NOOP))
-// log_add_disasm_comment(block, desc->pc, desc->opptr.l[0]);
+// if (m_drcuml->logging() && !(desc->flags & OPFLAG_VIRTUAL_NOOP))
+// log_add_disasm_comment(block, desc->pc, desc->opptr.l[0]);
/* set the PC map variable */
UML_MAPVAR(block, MAPVAR_PC, desc->pc); // mapvar PC,desc->pc
@@ -1353,17 +1353,17 @@ void adsp21062_device::generate_sequence_instruction(drcuml_block *block, compil
/* if we are debugging, call the debugger */
if ((machine().debug_flags & DEBUG_FLAG_ENABLED) != 0)
{
- UML_MOV(block, mem(&m_core->pc), desc->pc); // mov [pc],desc->pc
- save_fast_iregs(block); // <save fastregs>
- UML_DEBUG(block, desc->pc); // debug desc->pc
+ UML_MOV(block, mem(&m_core->pc), desc->pc); // mov [pc],desc->pc
+ save_fast_iregs(block); // <save fastregs>
+ UML_DEBUG(block, desc->pc); // debug desc->pc
}
/* if we hit an unmapped address, fatal error */
if (desc->flags & OPFLAG_COMPILER_UNMAPPED)
{
- UML_MOV(block, mem(&m_core->pc), desc->pc); // mov [pc],desc->pc
- save_fast_iregs(block); // <save fastregs>
- UML_EXIT(block, EXECUTE_UNMAPPED_CODE); // exit EXECUTE_UNMAPPED_CODE
+ UML_MOV(block, mem(&m_core->pc), desc->pc); // mov [pc],desc->pc
+ save_fast_iregs(block); // <save fastregs>
+ UML_EXIT(block, EXECUTE_UNMAPPED_CODE); // exit EXECUTE_UNMAPPED_CODE
}
// handle a special case where call is used as the last operation in a loop
@@ -1377,19 +1377,19 @@ void adsp21062_device::generate_sequence_instruction(drcuml_block *block, compil
UML_JMPc(block, COND_NE, end);
code_label label_expire = compiler->labelnum++;
- UML_MOV(block, I1, mem(&m_core->lstkp)); // mov i1,[m_core->lstkp]
- UML_LOAD(block, I0, m_core->lcstack, I1, SIZE_DWORD, SCALE_x4); // load i0,m_core->lcstack,i1,dword,scale_x4
- UML_SUB(block, I0, I0, 1); // sub i0,1
- UML_STORE(block, m_core->lcstack, I1, I0, SIZE_DWORD, SCALE_x4); // store m_core->lcstack,i1,i0,dword,scale_x4
- UML_SUB(block, CURLCNTR, CURLCNTR, 1); // sub CURLCNTR,1
- UML_JMPc(block, COND_E, label_expire); // jne label_expire
+ UML_MOV(block, I1, mem(&m_core->lstkp)); // mov i1,[m_core->lstkp]
+ UML_LOAD(block, I0, m_core->lcstack, I1, SIZE_DWORD, SCALE_x4); // load i0,m_core->lcstack,i1,dword,scale_x4
+ UML_SUB(block, I0, I0, 1); // sub i0,1
+ UML_STORE(block, m_core->lcstack, I1, I0, SIZE_DWORD, SCALE_x4); // store m_core->lcstack,i1,i0,dword,scale_x4
+ UML_SUB(block, CURLCNTR, CURLCNTR, 1); // sub CURLCNTR,1
+ UML_JMPc(block, COND_E, label_expire); // jne label_expire
UML_MOV(block, mem(&m_core->temp_return), desc->userdata0);
UML_JMP(block, end);
- UML_LABEL(block, label_expire); // label_expire:
- UML_CALLH(block, *m_pop_pc); // callh m_pop_pc
- UML_CALLH(block, *m_pop_loop); // callh m_pop_loop
+ UML_LABEL(block, label_expire); // label_expire:
+ UML_CALLH(block, *m_pop_pc); // callh m_pop_pc
+ UML_CALLH(block, *m_pop_loop); // callh m_pop_loop
UML_MOV(block, mem(&m_core->temp_return), desc->pc + 1);
UML_LABEL(block, end);
@@ -1418,8 +1418,8 @@ void adsp21062_device::generate_sequence_instruction(drcuml_block *block, compil
}
/* if this is an invalid opcode, generate the exception now */
-// if (desc->flags & OPFLAG_INVALID_OPCODE)
-// UML_EXH(block, *m_exception[EXCEPTION_PROGRAM], 0x80000); // exh exception_program,0x80000
+// if (desc->flags & OPFLAG_INVALID_OPCODE)
+// UML_EXH(block, *m_exception[EXCEPTION_PROGRAM], 0x80000); // exh exception_program,0x80000
/* unless this is a virtual no-op, it's a regular instruction */
if (!(desc->flags & OPFLAG_VIRTUAL_NOOP))
@@ -1427,9 +1427,9 @@ void adsp21062_device::generate_sequence_instruction(drcuml_block *block, compil
/* compile the instruction */
if (!generate_opcode(block, compiler, desc))
{
- UML_MOV(block, mem(&m_core->pc), desc->pc); // mov [pc],desc->pc
- UML_DMOV(block, mem(&m_core->arg64), desc->opptr.q[0]); // dmov [arg64],*desc->opptr.q
- UML_CALLC(block, cfunc_unimplemented, this); // callc cfunc_unimplemented,ppc
+ UML_MOV(block, mem(&m_core->pc), desc->pc); // mov [pc],desc->pc
+ UML_DMOV(block, mem(&m_core->arg64), desc->opptr.q[0]); // dmov [arg64],*desc->opptr.q
+ UML_CALLC(block, cfunc_unimplemented, this); // callc cfunc_unimplemented,ppc
}
}
@@ -1438,7 +1438,7 @@ void adsp21062_device::generate_sequence_instruction(drcuml_block *block, compil
if (compiler->mode1_delay.counter > 0)
{
compiler->mode1_delay.counter--;
-
+
// delayed operation in the last delay slot needs to be done before the branch is taken
if (last_delayslot)
compiler->mode1_delay.counter = 0;
@@ -1467,7 +1467,7 @@ void adsp21062_device::generate_sequence_instruction(drcuml_block *block, compil
}
- // insert loop check at this instruction if needed
+ // insert loop check at this instruction if needed
if (desc->userflags & OP_USERFLAG_COUNTER_LOOP)
{
code_label label_skip_loop = compiler->labelnum++;
@@ -1476,18 +1476,18 @@ void adsp21062_device::generate_sequence_instruction(drcuml_block *block, compil
UML_JMPc(block, COND_NE, label_skip_loop);
code_label label_expire = compiler->labelnum++;
- UML_MOV(block, I1, mem(&m_core->lstkp)); // mov i1,[m_core->lstkp]
- UML_LOAD(block, I0, m_core->lcstack, I1, SIZE_DWORD, SCALE_x4); // load i0,m_core->lcstack,i1,dword,scale_x4
- UML_SUB(block, I0, I0, 1); // sub i0,1
- UML_STORE(block, m_core->lcstack, I1, I0, SIZE_DWORD, SCALE_x4); // store m_core->lcstack,i1,i0,dword,scale_x4
- UML_SUB(block, CURLCNTR, CURLCNTR, 1); // sub CURLCNTR,1
- UML_JMPc(block, COND_E, label_expire); // jne label_expire
+ UML_MOV(block, I1, mem(&m_core->lstkp)); // mov i1,[m_core->lstkp]
+ UML_LOAD(block, I0, m_core->lcstack, I1, SIZE_DWORD, SCALE_x4); // load i0,m_core->lcstack,i1,dword,scale_x4
+ UML_SUB(block, I0, I0, 1); // sub i0,1
+ UML_STORE(block, m_core->lcstack, I1, I0, SIZE_DWORD, SCALE_x4); // store m_core->lcstack,i1,i0,dword,scale_x4
+ UML_SUB(block, CURLCNTR, CURLCNTR, 1); // sub CURLCNTR,1
+ UML_JMPc(block, COND_E, label_expire); // jne label_expire
generate_loop_jump(block, compiler, desc);
- UML_LABEL(block, label_expire); // label_expire:
- UML_CALLH(block, *m_pop_pc); // callh m_pop_pc
- UML_CALLH(block, *m_pop_loop); // callh m_pop_loop
+ UML_LABEL(block, label_expire); // label_expire:
+ UML_CALLH(block, *m_pop_pc); // callh m_pop_pc
+ UML_CALLH(block, *m_pop_loop); // callh m_pop_loop
UML_LABEL(block, label_skip_loop);
}
@@ -1544,18 +1544,18 @@ void adsp21062_device::generate_update_cycles(drcuml_block *block, compiler_stat
code_label skip = compiler->labelnum++;
compiler->checkints = FALSE;
- UML_CMP(block, mem(&m_core->irq_pending), 0); // cmp [irq_pending],0
- UML_JMPc(block, COND_E, skip); // je skip
- UML_CMP(block, mem(&m_core->interrupt_active), 0); // cmp [interrupt_active],0
- UML_JMPc(block, COND_NE, skip); // jne skip
- UML_TEST(block, mem(&m_core->irq_pending), IMASK); // test [irq_pending],IMASK
- UML_JMPc(block, COND_Z, skip); // jz skip
- UML_TEST(block, mem(&m_core->mode1), MODE1_IRPTEN); // test MODE1,MODE1_IRPTEN
- UML_JMPc(block, COND_Z, skip); // jz skip
+ UML_CMP(block, mem(&m_core->irq_pending), 0); // cmp [irq_pending],0
+ UML_JMPc(block, COND_E, skip); // je skip
+ UML_CMP(block, mem(&m_core->interrupt_active), 0); // cmp [interrupt_active],0
+ UML_JMPc(block, COND_NE, skip); // jne skip
+ UML_TEST(block, mem(&m_core->irq_pending), IMASK); // test [irq_pending],IMASK
+ UML_JMPc(block, COND_Z, skip); // jz skip
+ UML_TEST(block, mem(&m_core->mode1), MODE1_IRPTEN); // test MODE1,MODE1_IRPTEN
+ UML_JMPc(block, COND_Z, skip); // jz skip
- UML_MOV(block, I0, param); // mov i0,nextpc
- UML_MOV(block, I1, compiler->cycles); // mov i1,cycles
- UML_CALLH(block, *m_exception[EXCEPTION_INTERRUPT]); // callh m_exception[EXCEPTION_INTERRUPT]
+ UML_MOV(block, I0, param); // mov i0,nextpc
+ UML_MOV(block, I1, compiler->cycles); // mov i1,cycles
+ UML_CALLH(block, *m_exception[EXCEPTION_INTERRUPT]); // callh m_exception[EXCEPTION_INTERRUPT]
UML_LABEL(block, skip);
}
@@ -1563,10 +1563,10 @@ void adsp21062_device::generate_update_cycles(drcuml_block *block, compiler_stat
/* account for cycles */
if (compiler->cycles > 0)
{
- UML_SUB(block, mem(&m_core->icount), mem(&m_core->icount), MAPVAR_CYCLES); // sub icount,icount,cycles
- UML_MAPVAR(block, MAPVAR_CYCLES, 0); // mapvar cycles,0
+ UML_SUB(block, mem(&m_core->icount), mem(&m_core->icount), MAPVAR_CYCLES); // sub icount,icount,cycles
+ UML_MAPVAR(block, MAPVAR_CYCLES, 0); // mapvar cycles,0
if (allow_exception)
- UML_EXHc(block, COND_S, *m_out_of_cycles, param); // exh out_of_cycles,nextpc
+ UML_EXHc(block, COND_S, *m_out_of_cycles, param); // exh out_of_cycles,nextpc
}
compiler->cycles = 0;
}
@@ -1586,42 +1586,42 @@ void adsp21062_device::generate_write_mode1_imm(drcuml_block *block, compiler_st
// DAG1 regs 4-7
skip = compiler->labelnum++;
UML_TEST(block, MODE1, 0x8);
- UML_JMPc(block, (data & 0x8) ? COND_NZ : COND_Z, skip); // don't swap if the bits are same
+ UML_JMPc(block, (data & 0x8) ? COND_NZ : COND_Z, skip); // don't swap if the bits are same
UML_CALLH(block, *m_swap_dag1_4_7);
UML_LABEL(block, skip);
// DAG1 regs 0-3
skip = compiler->labelnum++;
UML_TEST(block, MODE1, 0x10);
- UML_JMPc(block, (data & 0x10) ? COND_NZ : COND_Z, skip); // don't swap if the bits are same
+ UML_JMPc(block, (data & 0x10) ? COND_NZ : COND_Z, skip); // don't swap if the bits are same
UML_CALLH(block, *m_swap_dag1_0_3);
UML_LABEL(block, skip);
// DAG2 regs 4-7
skip = compiler->labelnum++;
UML_TEST(block, MODE1, 0x20);
- UML_JMPc(block, (data & 0x20) ? COND_NZ : COND_Z, skip); // don't swap if the bits are same
+ UML_JMPc(block, (data & 0x20) ? COND_NZ : COND_Z, skip); // don't swap if the bits are same
UML_CALLH(block, *m_swap_dag2_4_7);
UML_LABEL(block, skip);
// DAG2 regs 0-3
skip = compiler->labelnum++;
UML_TEST(block, MODE1, 0x40);
- UML_JMPc(block, (data & 0x40) ? COND_NZ : COND_Z, skip); // don't swap if the bits are same
+ UML_JMPc(block, (data & 0x40) ? COND_NZ : COND_Z, skip); // don't swap if the bits are same
UML_CALLH(block, *m_swap_dag2_0_3);
UML_LABEL(block, skip);
// REG 8-15
skip = compiler->labelnum++;
UML_TEST(block, MODE1, 0x80);
- UML_JMPc(block, (data & 0x80) ? COND_NZ : COND_Z, skip); // don't swap if the bits are same
+ UML_JMPc(block, (data & 0x80) ? COND_NZ : COND_Z, skip); // don't swap if the bits are same
UML_CALLH(block, *m_swap_r8_15);
UML_LABEL(block, skip);
// REG 0-7
skip = compiler->labelnum++;
UML_TEST(block, MODE1, 0x400);
- UML_JMPc(block, (data & 0x400) ? COND_NZ : COND_Z, skip); // don't swap if the bits are same
+ UML_JMPc(block, (data & 0x400) ? COND_NZ : COND_Z, skip); // don't swap if the bits are same
UML_CALLH(block, *m_swap_r0_7);
UML_LABEL(block, skip);
@@ -1636,51 +1636,51 @@ void adsp21062_device::generate_set_mode1_imm(drcuml_block *block, compiler_stat
fatalerror("generate_set_mode1_imm: tried to enable I0 bit reversing");
if (data & 0x4)
fatalerror("generate_set_mode1_imm: tried to enable MR alternate");
- if (data & 0x8) // DAG1 regs 4-7
+ if (data & 0x8) // DAG1 regs 4-7
{
code_label skip = compiler->labelnum++;
UML_TEST(block, MODE1, 0x8);
- UML_JMPc(block, COND_NZ, skip); // don't swap if the bit is already 1
+ UML_JMPc(block, COND_NZ, skip); // don't swap if the bit is already 1
UML_CALLH(block, *m_swap_dag1_4_7);
UML_LABEL(block, skip);
}
- if (data & 0x10) // DAG1 regs 0-3
+ if (data & 0x10) // DAG1 regs 0-3
{
code_label skip = compiler->labelnum++;
UML_TEST(block, MODE1, 0x10);
- UML_JMPc(block, COND_NZ, skip); // don't swap if the bit is already 1
+ UML_JMPc(block, COND_NZ, skip); // don't swap if the bit is already 1
UML_CALLH(block, *m_swap_dag1_0_3);
UML_LABEL(block, skip);
}
- if (data & 0x20) // DAG2 regs 4-7
+ if (data & 0x20) // DAG2 regs 4-7
{
code_label skip = compiler->labelnum++;
UML_TEST(block, MODE1, 0x20);
- UML_JMPc(block, COND_NZ, skip); // don't swap if the bit is already 1
+ UML_JMPc(block, COND_NZ, skip); // don't swap if the bit is already 1
UML_CALLH(block, *m_swap_dag2_4_7);
UML_LABEL(block, skip);
}
- if (data & 0x40) // DAG1 regs 0-3
+ if (data & 0x40) // DAG1 regs 0-3
{
code_label skip = compiler->labelnum++;
UML_TEST(block, MODE1, 0x40);
- UML_JMPc(block, COND_NZ, skip); // don't swap if the bit is already 1
+ UML_JMPc(block, COND_NZ, skip); // don't swap if the bit is already 1
UML_CALLH(block, *m_swap_dag2_0_3);
UML_LABEL(block, skip);
}
- if (data & 0x80) // REG 8-15
+ if (data & 0x80) // REG 8-15
{
code_label skip = compiler->labelnum++;
UML_TEST(block, MODE1, 0x80);
- UML_JMPc(block, COND_NZ, skip); // don't swap if the bit is already 1
+ UML_JMPc(block, COND_NZ, skip); // don't swap if the bit is already 1
UML_CALLH(block, *m_swap_r8_15);
UML_LABEL(block, skip);
}
- if (data & 0x400) // REG 0-7
+ if (data & 0x400) // REG 0-7
{
code_label skip = compiler->labelnum++;
UML_TEST(block, MODE1, 0x400);
- UML_JMPc(block, COND_NZ, skip); // don't swap if the bit is already 1
+ UML_JMPc(block, COND_NZ, skip); // don't swap if the bit is already 1
UML_CALLH(block, *m_swap_r0_7);
UML_LABEL(block, skip);
}
@@ -1696,51 +1696,51 @@ void adsp21062_device::generate_clear_mode1_imm(drcuml_block *block, compiler_st
fatalerror("generate_clear_mode1_imm: tried to disable I0 bit reversing");
if (data & 0x4)
fatalerror("generate_clear_mode1_imm: tried to disable MR alternate");
- if (data & 0x8) // DAG1 regs 4-7
+ if (data & 0x8) // DAG1 regs 4-7
{
code_label skip = compiler->labelnum++;
UML_TEST(block, MODE1, 0x8);
- UML_JMPc(block, COND_Z, skip); // don't swap if the bit is already 0
+ UML_JMPc(block, COND_Z, skip); // don't swap if the bit is already 0
UML_CALLH(block, *m_swap_dag1_4_7);
UML_LABEL(block, skip);
}
- if (data & 0x10) // DAG1 regs 0-3
+ if (data & 0x10) // DAG1 regs 0-3
{
code_label skip = compiler->labelnum++;
UML_TEST(block, MODE1, 0x10);
- UML_JMPc(block, COND_Z, skip); // don't swap if the bit is already 0
+ UML_JMPc(block, COND_Z, skip); // don't swap if the bit is already 0
UML_CALLH(block, *m_swap_dag1_0_3);
UML_LABEL(block, skip);
}
- if (data & 0x20) // DAG2 regs 4-7
+ if (data & 0x20) // DAG2 regs 4-7
{
code_label skip = compiler->labelnum++;
UML_TEST(block, MODE1, 0x20);
- UML_JMPc(block, COND_Z, skip); // don't swap if the bit is already 0
+ UML_JMPc(block, COND_Z, skip); // don't swap if the bit is already 0
UML_CALLH(block, *m_swap_dag2_4_7);
UML_LABEL(block, skip);
}
- if (data & 0x40) // DAG1 regs 0-3
+ if (data & 0x40) // DAG1 regs 0-3
{
code_label skip = compiler->labelnum++;
UML_TEST(block, MODE1, 0x40);
- UML_JMPc(block, COND_Z, skip); // don't swap if the bit is already 0
+ UML_JMPc(block, COND_Z, skip); // don't swap if the bit is already 0
UML_CALLH(block, *m_swap_dag2_0_3);
UML_LABEL(block, skip);
}
- if (data & 0x80) // REG 8-15
+ if (data & 0x80) // REG 8-15
{
code_label skip = compiler->labelnum++;
UML_TEST(block, MODE1, 0x80);
- UML_JMPc(block, COND_Z, skip); // don't swap if the bit is already 0
+ UML_JMPc(block, COND_Z, skip); // don't swap if the bit is already 0
UML_CALLH(block, *m_swap_r8_15);
UML_LABEL(block, skip);
}
- if (data & 0x400) // REG 0-7
+ if (data & 0x400) // REG 0-7
{
code_label skip = compiler->labelnum++;
UML_TEST(block, MODE1, 0x400);
- UML_JMPc(block, COND_Z, skip); // don't swap if the bit is already 0
+ UML_JMPc(block, COND_Z, skip); // don't swap if the bit is already 0
UML_CALLH(block, *m_swap_r0_7);
UML_LABEL(block, skip);
}
@@ -1827,7 +1827,7 @@ void adsp21062_device::generate_call(drcuml_block *block, compiler_state *compil
// save branch target
if (desc->targetpc == BRANCH_TARGET_DYNAMIC)
{
- UML_MOV(block, mem(&m_core->jmpdest), I0); // mov [jmpdest],i0
+ UML_MOV(block, mem(&m_core->jmpdest), I0); // mov [jmpdest],i0
}
// compile delay slots if needed
@@ -1847,7 +1847,7 @@ void adsp21062_device::generate_call(drcuml_block *block, compiler_state *compil
if (delayslot)
UML_MOV(block, I0, desc->pc + 3);
else
- UML_MOV(block, I0, desc->pc + 1);
+ UML_MOV(block, I0, desc->pc + 1);
}
UML_CALLH(block, *m_push_pc);
@@ -1856,14 +1856,14 @@ void adsp21062_device::generate_call(drcuml_block *block, compiler_state *compil
{
generate_update_cycles(block, &compiler_temp, desc->targetpc, TRUE);
if (desc->flags & OPFLAG_INTRABLOCK_BRANCH)
- UML_JMP(block, desc->targetpc | 0x80000000); // jmp targetpc | 0x80000000
+ UML_JMP(block, desc->targetpc | 0x80000000); // jmp targetpc | 0x80000000
else
- UML_HASHJMP(block, 0, desc->targetpc, *m_nocode); // hashjmp 0,targetpc,nocode
+ UML_HASHJMP(block, 0, desc->targetpc, *m_nocode); // hashjmp 0,targetpc,nocode
}
else
{
generate_update_cycles(block, &compiler_temp, mem(&m_core->jmpdest), TRUE);
- UML_HASHJMP(block, 0, mem(&m_core->jmpdest), *m_nocode); // hashjmp 0,jmpdest,nocode
+ UML_HASHJMP(block, 0, mem(&m_core->jmpdest), *m_nocode); // hashjmp 0,jmpdest,nocode
}
// update compiler label
@@ -1871,7 +1871,7 @@ void adsp21062_device::generate_call(drcuml_block *block, compiler_state *compil
/* reset the mapvar to the current cycles and account for skipped slots */
compiler->cycles += desc->skipslots;
- UML_MAPVAR(block, MAPVAR_CYCLES, compiler->cycles); // mapvar CYCLES,compiler->cycles
+ UML_MAPVAR(block, MAPVAR_CYCLES, compiler->cycles); // mapvar CYCLES,compiler->cycles
}
void adsp21062_device::generate_jump(drcuml_block *block, compiler_state *compiler, const opcode_desc *desc, bool delayslot, bool loopabort, bool clearint)
@@ -1883,7 +1883,7 @@ void adsp21062_device::generate_jump(drcuml_block *block, compiler_state *compil
// save branch target
if (desc->targetpc == BRANCH_TARGET_DYNAMIC)
{
- UML_MOV(block, mem(&m_core->jmpdest), I0); // mov [jmpdest],i0
+ UML_MOV(block, mem(&m_core->jmpdest), I0); // mov [jmpdest],i0
}
// compile delay slots if needed
@@ -1898,13 +1898,13 @@ void adsp21062_device::generate_jump(drcuml_block *block, compiler_state *compil
{
code_label skip_pop = compiler_temp.labelnum++;
- UML_MOV(block, mem(&m_core->interrupt_active), 0); // mov [interrupt_active],0
- UML_SHL(block, I1, 1, mem(&m_core->active_irq_num)); // shl i1,1,[active_irq_num]
- UML_XOR(block, IRPTL, IRPTL, I1); // xor IRPTL,i1
- UML_CMP(block, mem(&m_core->status_stkp), 0); // cmp [status_stkp],0
- UML_JMPc(block, COND_Z, skip_pop); // jz skip_pop
- UML_CALLH(block, *m_pop_status); // callh m_pop_status
- UML_LABEL(block, skip_pop); // skip_pop:
+ UML_MOV(block, mem(&m_core->interrupt_active), 0); // mov [interrupt_active],0
+ UML_SHL(block, I1, 1, mem(&m_core->active_irq_num)); // shl i1,1,[active_irq_num]
+ UML_XOR(block, IRPTL, IRPTL, I1); // xor IRPTL,i1
+ UML_CMP(block, mem(&m_core->status_stkp), 0); // cmp [status_stkp],0
+ UML_JMPc(block, COND_Z, skip_pop); // jz skip_pop
+ UML_CALLH(block, *m_pop_status); // callh m_pop_status
+ UML_LABEL(block, skip_pop); // skip_pop:
}
// loop abort
@@ -1919,14 +1919,14 @@ void adsp21062_device::generate_jump(drcuml_block *block, compiler_state *compil
{
generate_update_cycles(block, &compiler_temp, desc->targetpc, TRUE);
if (desc->flags & OPFLAG_INTRABLOCK_BRANCH)
- UML_JMP(block, desc->targetpc | 0x80000000); // jmp targetpc | 0x80000000
+ UML_JMP(block, desc->targetpc | 0x80000000); // jmp targetpc | 0x80000000
else
- UML_HASHJMP(block, 0, desc->targetpc, *m_nocode); // hashjmp 0,targetpc,nocode
+ UML_HASHJMP(block, 0, desc->targetpc, *m_nocode); // hashjmp 0,targetpc,nocode
}
else
{
generate_update_cycles(block, &compiler_temp, mem(&m_core->jmpdest), TRUE);
- UML_HASHJMP(block, 0, mem(&m_core->jmpdest), *m_nocode); // hashjmp 0,jmpdest,nocode
+ UML_HASHJMP(block, 0, mem(&m_core->jmpdest), *m_nocode); // hashjmp 0,jmpdest,nocode
}
// update compiler label
@@ -1934,7 +1934,7 @@ void adsp21062_device::generate_jump(drcuml_block *block, compiler_state *compil
/* reset the mapvar to the current cycles and account for skipped slots */
compiler->cycles += desc->skipslots;
- UML_MAPVAR(block, MAPVAR_CYCLES, compiler->cycles); // mapvar CYCLES,compiler->cycles
+ UML_MAPVAR(block, MAPVAR_CYCLES, compiler->cycles); // mapvar CYCLES,compiler->cycles
}
void adsp21062_device::generate_loop_jump(drcuml_block *block, compiler_state *compiler, const opcode_desc *desc)
@@ -1943,15 +1943,15 @@ void adsp21062_device::generate_loop_jump(drcuml_block *block, compiler_state *c
generate_update_cycles(block, compiler, desc->userdata0, TRUE);
/*
if (desc->flags & OPFLAG_INTRABLOCK_BRANCH)
- UML_JMP(block, desc->targetpc | 0x80000000); // jmp targetpc | 0x80000000
+ UML_JMP(block, desc->targetpc | 0x80000000); // jmp targetpc | 0x80000000
else
- UML_HASHJMP(block, 0, desc->targetpc, *m_nocode); // hashjmp 0,targetpc,nocode
- */
+ UML_HASHJMP(block, 0, desc->targetpc, *m_nocode); // hashjmp 0,targetpc,nocode
+ */
UML_HASHJMP(block, 0, desc->userdata0, *m_nocode);
/* reset the mapvar to the current cycles and account for skipped slots */
compiler->cycles += desc->skipslots;
- UML_MAPVAR(block, MAPVAR_CYCLES, compiler->cycles); // mapvar CYCLES,compiler->cycles
+ UML_MAPVAR(block, MAPVAR_CYCLES, compiler->cycles); // mapvar CYCLES,compiler->cycles
}
/*-------------------------------------------------
@@ -2002,25 +2002,25 @@ void adsp21062_device::generate_read_ureg(drcuml_block *block, compiler_state *c
UML_MOV(block, I0, mem(&m_core->dag2.b[ureg & 7]));
break;
- case 0x64: // PCSTK
+ case 0x64: // PCSTK
UML_LOAD(block, I0, &m_core->pcstack, PCSTKP, SIZE_DWORD, SCALE_x4);
break;
- case 0x70: // USTAT1
+ case 0x70: // USTAT1
UML_MOV(block, I0, mem(&m_core->ustat1));
break;
- case 0x71: // USTAT2
+ case 0x71: // USTAT2
UML_MOV(block, I0, mem(&m_core->ustat2));
break;
- case 0x79: // IRPTL
+ case 0x79: // IRPTL
UML_MOV(block, I0, mem(&m_core->irptl));
break;
- case 0x7a: // MODE2
+ case 0x7a: // MODE2
UML_MOV(block, I0, mem(&m_core->mode2));
break;
- case 0x7b: // MODE1
+ case 0x7b: // MODE1
UML_MOV(block, I0, mem(&m_core->mode1));
break;
- case 0x7c: // ASTAT
+ case 0x7c: // ASTAT
// construct from bits
if (!has_compute)
{
@@ -2111,20 +2111,20 @@ void adsp21062_device::generate_read_ureg(drcuml_block *block, compiler_state *c
UML_OR(block, I0, I0, I1);
}
break;
- case 0x7d: // IMASK
+ case 0x7d: // IMASK
UML_MOV(block, I0, mem(&m_core->imask));
break;
- case 0x7e: // STKY
+ case 0x7e: // STKY
UML_MOV(block, I0, mem(&m_core->stky));
break;
- case 0xdb: // PX
- UML_DMOV(block, I0, mem(&m_core->px)); // NOTE: this returns 64 bits
+ case 0xdb: // PX
+ UML_DMOV(block, I0, mem(&m_core->px)); // NOTE: this returns 64 bits
break;
- case 0xdc: // PX1 (bits 0-15 of PX)
+ case 0xdc: // PX1 (bits 0-15 of PX)
UML_MOV(block, I0, mem(&m_core->px));
UML_AND(block, I0, I0, 0xffff);
break;
- case 0xdd: // PX2 (bits 16-47 of PX)
+ case 0xdd: // PX2 (bits 16-47 of PX)
UML_DMOV(block, I0, mem(&m_core->px));
UML_DSHR(block, I0, I0, 16);
UML_DAND(block, I0, I0, 0xffffffff);
@@ -2138,7 +2138,7 @@ void adsp21062_device::generate_read_ureg(drcuml_block *block, compiler_state *c
/*-------------------------------------------------
- generate_write_ureg - contents of register I0 or 32-bit immediate data are written into UREG
+ generate_write_ureg - contents of register I0 or 32-bit immediate data are written into UREG
-------------------------------------------------*/
void adsp21062_device::generate_write_ureg(drcuml_block *block, compiler_state *compiler, const opcode_desc *desc, int ureg, bool imm, UINT32 data)
@@ -2187,31 +2187,31 @@ void adsp21062_device::generate_write_ureg(drcuml_block *block, compiler_state *
UML_MOV(block, PM_B(ureg & 7), imm ? data : I0);
break;
- case 0x64: // PCSTK
+ case 0x64: // PCSTK
fatalerror("generate_write_ureg: PCSTK");
break;
- case 0x65: // PCSTKP
+ case 0x65: // PCSTKP
UML_MOV(block, PCSTKP, imm ? data : I0);
break;
- case 0x67: // CURLCNTR
+ case 0x67: // CURLCNTR
UML_MOV(block, CURLCNTR, imm ? data : I0);
break;
- case 0x68: // LCNTR
+ case 0x68: // LCNTR
UML_MOV(block, LCNTR, imm ? data : I0);
break;
- case 0x70: // USTAT1
+ case 0x70: // USTAT1
UML_MOV(block, mem(&m_core->ustat1), imm ? data : I0);
break;
- case 0x71: // USTAT2
+ case 0x71: // USTAT2
UML_MOV(block, mem(&m_core->ustat2), imm ? data : I0);
break;
- case 0x79: // IRPTL
+ case 0x79: // IRPTL
UML_MOV(block, mem(&m_core->irptl), imm ? data : I0);
break;
- case 0x7a: // MODE2
+ case 0x7a: // MODE2
UML_MOV(block, mem(&m_core->mode2), imm ? data : I0);
break;
- case 0x7b: // MODE1
+ case 0x7b: // MODE1
// MODE1 needs to be written delayed
if (imm)
{
@@ -2226,17 +2226,17 @@ void adsp21062_device::generate_write_ureg(drcuml_block *block, compiler_state *
UML_MOV(block, mem(&m_core->mode1_delay_data), I0);
}
break;
- case 0x7c: // ASTAT
+ case 0x7c: // ASTAT
// TODO: needs bit break up
fatalerror("generate_write_ureg: ASTAT");
break;
- case 0x7d: // IMASK
+ case 0x7d: // IMASK
UML_MOV(block, mem(&m_core->imask), imm ? data : I0);
break;
- case 0x7e: // STKY
+ case 0x7e: // STKY
UML_MOV(block, mem(&m_core->stky), imm ? data : I0);
break;
- case 0xdb: // PX
+ case 0xdb: // PX
if (imm)
{
fatalerror("generate_write_ureg %02X with immediate!", ureg);
@@ -2246,7 +2246,7 @@ void adsp21062_device::generate_write_ureg(drcuml_block *block, compiler_state *
UML_DMOV(block, mem(&m_core->px), I0);
}
break;
- case 0xdc: // PX1 (bits 0-15 of PX)
+ case 0xdc: // PX1 (bits 0-15 of PX)
if (imm)
{
UML_DAND(block, mem(&m_core->px), mem(&m_core->px), ~0xffff);
@@ -2260,7 +2260,7 @@ void adsp21062_device::generate_write_ureg(drcuml_block *block, compiler_state *
UML_DOR(block, mem(&m_core->px), mem(&m_core->px), I1);
}
break;
- case 0xdd: // PX2 (bits 16-47 of PX)
+ case 0xdd: // PX2 (bits 16-47 of PX)
if (imm)
{
UML_DAND(block, mem(&m_core->px), mem(&m_core->px), 0xffff);
@@ -2268,7 +2268,7 @@ void adsp21062_device::generate_write_ureg(drcuml_block *block, compiler_state *
}
else
{
- UML_DAND(block, mem(&m_core->px), mem(&m_core->px), 0xffff);
+ UML_DAND(block, mem(&m_core->px), mem(&m_core->px), 0xffff);
UML_DSHL(block, I0, I0, 16);
UML_DOR(block, mem(&m_core->px), mem(&m_core->px), I0);
}
@@ -2286,12 +2286,12 @@ int adsp21062_device::generate_opcode(drcuml_block *block, compiler_state *compi
switch ((opcode >> 45) & 7)
{
- case 0: // subops
+ case 0: // subops
{
UINT32 subop = (opcode >> 40) & 0x1f;
switch (subop)
{
- case 0x00: // NOP / idle |000|00000|
+ case 0x00: // NOP / idle |000|00000|
if (opcode & U64(0x008000000000))
{
// IDLE
@@ -2306,7 +2306,7 @@ int adsp21062_device::generate_opcode(drcuml_block *block, compiler_state *compi
}
break;
- case 0x01: // compute |000|00001|
+ case 0x01: // compute |000|00001|
{
int cond = (opcode >> 33) & 0x1f;
@@ -2326,7 +2326,7 @@ int adsp21062_device::generate_opcode(drcuml_block *block, compiler_state *compi
return TRUE;
}
- case 0x02: // immediate shift |000|00010|
+ case 0x02: // immediate shift |000|00010|
{
int shiftop = (opcode >> 16) & 0x3f;
int rn = (opcode >> 4) & 0xf;
@@ -2342,15 +2342,15 @@ int adsp21062_device::generate_opcode(drcuml_block *block, compiler_state *compi
skip_label = compiler->labelnum++;
generate_if_condition(block, compiler, desc, cond, skip_label);
}
-
+
generate_shift_imm(block, compiler, desc, data, shiftop, rn, rx);
-
- if (has_condition)
- UML_LABEL(block, skip_label);
+
+ if (has_condition)
+ UML_LABEL(block, skip_label);
return TRUE;
}
- case 0x04: // compute / modify |000|00100|
+ case 0x04: // compute / modify |000|00100|
{
int cond = (opcode >> 33) & 0x1f;
int g = (opcode >> 38) & 0x1;
@@ -2387,7 +2387,7 @@ int adsp21062_device::generate_opcode(drcuml_block *block, compiler_state *compi
return TRUE;
}
- case 0x06: // direct jump|call |000|00110|
+ case 0x06: // direct jump|call |000|00110|
{
int b = (opcode >> 39) & 0x1;
int j = (opcode >> 26) & 0x1;
@@ -2405,7 +2405,7 @@ int adsp21062_device::generate_opcode(drcuml_block *block, compiler_state *compi
}
if (b) // call
{
- generate_call(block, compiler, desc, j != 0);
+ generate_call(block, compiler, desc, j != 0);
}
else // jump
{
@@ -2416,7 +2416,7 @@ int adsp21062_device::generate_opcode(drcuml_block *block, compiler_state *compi
return TRUE;
}
- case 0x07: // direct jump|call |000|00111|
+ case 0x07: // direct jump|call |000|00111|
{
int b = (opcode >> 39) & 0x1;
int j = (opcode >> 26) & 0x1;
@@ -2445,7 +2445,7 @@ int adsp21062_device::generate_opcode(drcuml_block *block, compiler_state *compi
return TRUE;
}
- case 0x08: // indirect jump|call / compute |000|01000|
+ case 0x08: // indirect jump|call / compute |000|01000|
{
int la = (opcode >> 38) & 0x1;
int ci = (opcode >> 24) & 0x1;
@@ -2508,7 +2508,7 @@ int adsp21062_device::generate_opcode(drcuml_block *block, compiler_state *compi
return TRUE;
}
- case 0x09: // indirect jump|call / compute |000|01001|
+ case 0x09: // indirect jump|call / compute |000|01001|
{
int la = (opcode >> 38) & 0x1;
int ci = (opcode >> 24) & 0x1;
@@ -2532,7 +2532,7 @@ int adsp21062_device::generate_opcode(drcuml_block *block, compiler_state *compi
{
generate_jump(block, compiler, desc, j != 0, la != 0, ci != 0);
}
-
+
UML_LABEL(block, label_else);
generate_compute(block, compiler, desc);
}
@@ -2565,12 +2565,12 @@ int adsp21062_device::generate_opcode(drcuml_block *block, compiler_state *compi
return TRUE;
}
- case 0x0a: // return from subroutine / compute |000|01010|
+ case 0x0a: // return from subroutine / compute |000|01010|
{
int cond = (opcode >> 33) & 0x1f;
int j = (opcode >> 26) & 0x1;
int e = (opcode >> 25) & 0x1;
- //int lr = (opcode >> 24) & 0x1;
+ //int lr = (opcode >> 24) & 0x1;
// TODO: loop re-entry
@@ -2583,7 +2583,7 @@ int adsp21062_device::generate_opcode(drcuml_block *block, compiler_state *compi
UML_CALLH(block, *m_pop_pc);
generate_jump(block, compiler, desc, j != 0, false, false);
-
+
UML_LABEL(block, label_else);
generate_compute(block, compiler, desc);
}
@@ -2610,7 +2610,7 @@ int adsp21062_device::generate_opcode(drcuml_block *block, compiler_state *compi
return TRUE;
}
- case 0x0b: // return from interrupt / compute |000|01011|
+ case 0x0b: // return from interrupt / compute |000|01011|
{
int cond = (opcode >> 33) & 0x1f;
int j = (opcode >> 26) & 0x1;
@@ -2619,15 +2619,15 @@ int adsp21062_device::generate_opcode(drcuml_block *block, compiler_state *compi
code_label skip_pop = compiler->labelnum++;
- UML_MOV(block, mem(&m_core->interrupt_active), 0); // mov [interrupt_active],0
- UML_MOV(block, I0, 1); // mov i0,1
- UML_SHL(block, I0, I0, mem(&m_core->active_irq_num)); // shl i0,[active_irq_num]
- UML_XOR(block, IRPTL, IRPTL, I0); // xor IRPTL,i0
- UML_CMP(block, mem(&m_core->status_stkp), 0); // cmp [status_stkp],0
- UML_JMPc(block, COND_Z, skip_pop); // jz skip_pop
- UML_CALLH(block, *m_pop_status); // callh m_pop_status
+ UML_MOV(block, mem(&m_core->interrupt_active), 0); // mov [interrupt_active],0
+ UML_MOV(block, I0, 1); // mov i0,1
+ UML_SHL(block, I0, I0, mem(&m_core->active_irq_num)); // shl i0,[active_irq_num]
+ UML_XOR(block, IRPTL, IRPTL, I0); // xor IRPTL,i0
+ UML_CMP(block, mem(&m_core->status_stkp), 0); // cmp [status_stkp],0
+ UML_JMPc(block, COND_Z, skip_pop); // jz skip_pop
+ UML_CALLH(block, *m_pop_status); // callh m_pop_status
- UML_LABEL(block, skip_pop); // skip_pop:
+ UML_LABEL(block, skip_pop); // skip_pop:
// TODO: check interrupts
@@ -2667,7 +2667,7 @@ int adsp21062_device::generate_opcode(drcuml_block *block, compiler_state *compi
return TRUE;
}
- case 0x0c: // do until counter expired |000|01100|
+ case 0x0c: // do until counter expired |000|01100|
{
UINT16 data = (UINT16)(opcode >> 24);
int offset = SIGN_EXTEND24(opcode & 0xffffff);
@@ -2680,7 +2680,7 @@ int adsp21062_device::generate_opcode(drcuml_block *block, compiler_state *compi
UML_MOV(block, I0, desc->pc + 1);
UML_CALLH(block, *m_push_pc);
- // push loop
+ // push loop
UML_MOV(block, I0, data);
UML_MOV(block, I1, address);
UML_CALLH(block, *m_push_loop);
@@ -2688,7 +2688,7 @@ int adsp21062_device::generate_opcode(drcuml_block *block, compiler_state *compi
return TRUE;
}
- case 0x0d: // do until counter expired |000|01101|
+ case 0x0d: // do until counter expired |000|01101|
{
int ureg = (opcode >> 32) & 0xff;
int offset = SIGN_EXTEND24(opcode & 0xffffff);
@@ -2703,14 +2703,14 @@ int adsp21062_device::generate_opcode(drcuml_block *block, compiler_state *compi
UML_MOV(block, I0, desc->pc + 1);
UML_CALLH(block, *m_push_pc);
- // push loop
+ // push loop
UML_MOV(block, I0, I3);
UML_MOV(block, I1, address);
UML_CALLH(block, *m_push_loop);
return TRUE;
}
- case 0x0e: // do until |000|01110|
+ case 0x0e: // do until |000|01110|
{
int offset = SIGN_EXTEND24(opcode & 0xffffff);
UINT32 address = desc->pc + offset;
@@ -2726,7 +2726,7 @@ int adsp21062_device::generate_opcode(drcuml_block *block, compiler_state *compi
return TRUE;
}
- case 0x0f: // immediate data -> ureg |000|01111|
+ case 0x0f: // immediate data -> ureg |000|01111|
{
int ureg = (opcode >> 32) & 0xff;
UINT32 data = (UINT32)opcode;
@@ -2735,7 +2735,7 @@ int adsp21062_device::generate_opcode(drcuml_block *block, compiler_state *compi
return TRUE;
}
- case 0x10: // ureg <-> DM|PM (direct) |000|100|G|D|
+ case 0x10: // ureg <-> DM|PM (direct) |000|100|G|D|
case 0x11:
case 0x12:
case 0x13:
@@ -2754,7 +2754,7 @@ int adsp21062_device::generate_opcode(drcuml_block *block, compiler_state *compi
if (g)
{
// PM
- if (ureg == 0xdb) // PX is 48-bit
+ if (ureg == 0xdb) // PX is 48-bit
UML_CALLH(block, *m_pm_write48);
else
UML_CALLH(block, *m_pm_write32);
@@ -2771,7 +2771,7 @@ int adsp21062_device::generate_opcode(drcuml_block *block, compiler_state *compi
if (g)
{
// PM
- if (ureg == 0xdb) // PX is 48-bit
+ if (ureg == 0xdb) // PX is 48-bit
UML_CALLH(block, *m_pm_read48);
else
UML_CALLH(block, *m_pm_read32);
@@ -2787,7 +2787,7 @@ int adsp21062_device::generate_opcode(drcuml_block *block, compiler_state *compi
return TRUE;
}
- case 0x14: // system register bit manipulation |000|10100|
+ case 0x14: // system register bit manipulation |000|10100|
{
int bop = (opcode >> 37) & 0x7;
int sreg = (opcode >> 32) & 0xf;
@@ -2795,7 +2795,7 @@ int adsp21062_device::generate_opcode(drcuml_block *block, compiler_state *compi
switch (bop)
{
- case 0: // SET
+ case 0: // SET
{
switch (sreg)
{
@@ -2816,7 +2816,7 @@ int adsp21062_device::generate_opcode(drcuml_block *block, compiler_state *compi
compiler->mode1_delay.data = data;
compiler->mode1_delay.mode = MODE1_SET;
break;
- case 0xc: // ASTAT
+ case 0xc: // ASTAT
// TODO: does this need delay?
if (data & ASTAT_FLAGS::AZ)
UML_MOV(block, ASTAT_AZ, 1);
@@ -2876,7 +2876,7 @@ int adsp21062_device::generate_opcode(drcuml_block *block, compiler_state *compi
}
return TRUE;
}
- case 1: // CLEAR
+ case 1: // CLEAR
{
switch (sreg)
{
@@ -2957,7 +2957,7 @@ int adsp21062_device::generate_opcode(drcuml_block *block, compiler_state *compi
}
return TRUE;
}
- case 2: // TOGGLE
+ case 2: // TOGGLE
{
switch (sreg)
{
@@ -2995,7 +2995,7 @@ int adsp21062_device::generate_opcode(drcuml_block *block, compiler_state *compi
}
return TRUE;
}
- case 4: // TEST
+ case 4: // TEST
{
switch (sreg)
{
@@ -3047,7 +3047,7 @@ int adsp21062_device::generate_opcode(drcuml_block *block, compiler_state *compi
}
return TRUE;
}
- case 5: // XOR
+ case 5: // XOR
{
return FALSE;
}
@@ -3058,13 +3058,13 @@ int adsp21062_device::generate_opcode(drcuml_block *block, compiler_state *compi
return TRUE;
}
- case 0x16: // I register modify / bit-reverse |000|10110|
+ case 0x16: // I register modify / bit-reverse |000|10110|
{
- if (opcode & U64(0x008000000000)) // bit reverse
+ if (opcode & U64(0x008000000000)) // bit reverse
{
return FALSE;
}
- else // modify
+ else // modify
{
int g = (opcode >> 38) & 0x1;
int i = (opcode >> 32) & 0x7;
@@ -3085,7 +3085,7 @@ int adsp21062_device::generate_opcode(drcuml_block *block, compiler_state *compi
}
}
- case 0x17: // push|pop stacks / flush cache |000|10111|
+ case 0x17: // push|pop stacks / flush cache |000|10111|
{
if (opcode & U64(0x008000000000))
{
@@ -3115,10 +3115,10 @@ int adsp21062_device::generate_opcode(drcuml_block *block, compiler_state *compi
return TRUE;
}
- case 0x18: // cjump |000|11000|
+ case 0x18: // cjump |000|11000|
return FALSE;
- case 0x19: // rframe |000|11001|
+ case 0x19: // rframe |000|11001|
return FALSE;
default:
@@ -3127,7 +3127,7 @@ int adsp21062_device::generate_opcode(drcuml_block *block, compiler_state *compi
break;
}
- case 1: // compute / dreg <-> DM / dreg <-> PM |001|
+ case 1: // compute / dreg <-> DM / dreg <-> PM |001|
{
int pm_dreg = (opcode >> 23) & 0xf;
int pmm = (opcode >> 27) & 0x7;
@@ -3202,7 +3202,7 @@ int adsp21062_device::generate_opcode(drcuml_block *block, compiler_state *compi
return TRUE;
}
- case 2: // compute / ureg <-> DM|PM, register modify |010|
+ case 2: // compute / ureg <-> DM|PM, register modify |010|
{
int u = (opcode >> 44) & 0x1;
int i = (opcode >> 41) & 0x7;
@@ -3245,18 +3245,18 @@ int adsp21062_device::generate_opcode(drcuml_block *block, compiler_state *compi
generate_compute(block, compiler, desc);
// transfer
- UML_MOV(block, I1, (g) ? PM_I(i) : DM_I(i)); // mov i1,dm|pm[i]
- if (u == 0) // pre-modify without update
- UML_ADD(block, I1, I1, (g) ? PM_M(m) : DM_M(m)); // add i1,i1,dm|pm[m]
+ UML_MOV(block, I1, (g) ? PM_I(i) : DM_I(i)); // mov i1,dm|pm[i]
+ if (u == 0) // pre-modify without update
+ UML_ADD(block, I1, I1, (g) ? PM_M(m) : DM_M(m)); // add i1,i1,dm|pm[m]
if (temp_ureg)
- UML_MOV(block, I0, mem(&m_core->dreg_temp)); // mov i0,[m_core->dreg_temp]
+ UML_MOV(block, I0, mem(&m_core->dreg_temp)); // mov i0,[m_core->dreg_temp]
else
generate_read_ureg(block, compiler, desc, ureg, ureg_is_astat);
- if (ureg == 0xdb && (g)) // PX is 48-bit when writing to PM
- UML_CALLH(block, *m_pm_write48); // callh pm_write48
+ if (ureg == 0xdb && (g)) // PX is 48-bit when writing to PM
+ UML_CALLH(block, *m_pm_write48); // callh pm_write48
else
- UML_CALLH(block, (g) ? *m_pm_write32 : *m_dm_write32); // callh dm|pm_write32
+ UML_CALLH(block, (g) ? *m_pm_write32 : *m_dm_write32); // callh dm|pm_write32
}
else
{
@@ -3266,23 +3266,23 @@ int adsp21062_device::generate_opcode(drcuml_block *block, compiler_state *compi
generate_compute(block, compiler, desc);
// transfer
- UML_MOV(block, I1, (g) ? PM_I(i) : DM_I(i)); // mov i1,dm|pm[i]
- if (u == 0) // pre-modify without update
- UML_ADD(block, I1, I1, (g) ? PM_M(m) : DM_M(m)); // add i1,i1,dm|pm[m]
+ UML_MOV(block, I1, (g) ? PM_I(i) : DM_I(i)); // mov i1,dm|pm[i]
+ if (u == 0) // pre-modify without update
+ UML_ADD(block, I1, I1, (g) ? PM_M(m) : DM_M(m)); // add i1,i1,dm|pm[m]
- if (ureg == 0xdb && (g)) // PX is 48-bit when reading from PM
- UML_CALLH(block, *m_pm_read48); // callh pm_read48
+ if (ureg == 0xdb && (g)) // PX is 48-bit when reading from PM
+ UML_CALLH(block, *m_pm_read48); // callh pm_read48
else
- UML_CALLH(block, (g) ? *m_pm_read32 : *m_dm_read32); // callh dm|pm_read32
+ UML_CALLH(block, (g) ? *m_pm_read32 : *m_dm_read32); // callh dm|pm_read32
generate_write_ureg(block, compiler, desc, ureg, false, 0);
}
- if (u != 0) // post-modify with update
+ if (u != 0) // post-modify with update
{
if (g)
- UML_ADD(block, PM_I(i), PM_I(i), PM_M(m)); // add pm[i],pm[m]
+ UML_ADD(block, PM_I(i), PM_I(i), PM_M(m)); // add pm[i],pm[m]
else
- UML_ADD(block, DM_I(i), DM_I(i), DM_M(m)); // add dm[i],dm[m]
+ UML_ADD(block, DM_I(i), DM_I(i), DM_M(m)); // add dm[i],dm[m]
generate_update_circular_buffer(block, compiler, desc, g, i);
}
@@ -3295,7 +3295,7 @@ int adsp21062_device::generate_opcode(drcuml_block *block, compiler_state *compi
case 3:
{
- if (opcode & U64(0x100000000000)) // compute / ureg <-> ureg |011|1|
+ if (opcode & U64(0x100000000000)) // compute / ureg <-> ureg |011|1|
{
int src_ureg = (opcode >> 36) & 0xff;
int dst_ureg = (opcode >> 23) & 0xff;
@@ -3343,7 +3343,7 @@ int adsp21062_device::generate_opcode(drcuml_block *block, compiler_state *compi
return TRUE;
}
- else // compute / dreg <-> DM|PM, immediate modify |011|0|
+ else // compute / dreg <-> DM|PM, immediate modify |011|0|
{
int cond = (opcode >> 33) & 0x1f;
int u = (opcode >> 38) & 0x1;
@@ -3362,7 +3362,7 @@ int adsp21062_device::generate_opcode(drcuml_block *block, compiler_state *compi
skip_label = compiler->labelnum++;
generate_if_condition(block, compiler, desc, cond, skip_label);
}
- if (d)
+ if (d)
{
// DREG -> DM|PM
bool temp_dreg = false;
@@ -3377,14 +3377,14 @@ int adsp21062_device::generate_opcode(drcuml_block *block, compiler_state *compi
generate_compute(block, compiler, desc);
// transfer
- UML_MOV(block, I1, (g) ? PM_I(i) : DM_I(i)); // mov i1,dm|pm[i]
- if (u == 0) // pre-modify without update
- UML_ADD(block, I1, I1, mod); // add i1,i1,mod
+ UML_MOV(block, I1, (g) ? PM_I(i) : DM_I(i)); // mov i1,dm|pm[i]
+ if (u == 0) // pre-modify without update
+ UML_ADD(block, I1, I1, mod); // add i1,i1,mod
if (temp_dreg)
- UML_MOV(block, I0, mem(&m_core->dreg_temp)); // mov i0,[m_core->dreg_temp]
+ UML_MOV(block, I0, mem(&m_core->dreg_temp)); // mov i0,[m_core->dreg_temp]
else
- UML_MOV(block, I0, REG(dreg)); // mov i0,reg[dreg]
- UML_CALLH(block, (g) ? *m_pm_write32 : *m_dm_write32); // callh dm|pm_write32
+ UML_MOV(block, I0, REG(dreg)); // mov i0,reg[dreg]
+ UML_CALLH(block, (g) ? *m_pm_write32 : *m_dm_write32); // callh dm|pm_write32
}
else
{
@@ -3394,19 +3394,19 @@ int adsp21062_device::generate_opcode(drcuml_block *block, compiler_state *compi
generate_compute(block, compiler, desc);
// transfer
- UML_MOV(block, I1, (g) ? PM_I(i) : DM_I(i)); // mov i1,dm|pm[i]
- if (u == 0) // pre-modify without update
- UML_ADD(block, I1, I1, mod); // add i1,i1,mod
- UML_CALLH(block, (g) ? *m_pm_read32 : *m_dm_read32); // callh dm|pm_read32
- UML_MOV(block, REG(dreg), I0); // mov reg[dreg],i0
+ UML_MOV(block, I1, (g) ? PM_I(i) : DM_I(i)); // mov i1,dm|pm[i]
+ if (u == 0) // pre-modify without update
+ UML_ADD(block, I1, I1, mod); // add i1,i1,mod
+ UML_CALLH(block, (g) ? *m_pm_read32 : *m_dm_read32); // callh dm|pm_read32
+ UML_MOV(block, REG(dreg), I0); // mov reg[dreg],i0
}
- if (u != 0) // post-modify with update
+ if (u != 0) // post-modify with update
{
if (g)
- UML_ADD(block, PM_I(i), PM_I(i), mod); // add pm[i],mod
+ UML_ADD(block, PM_I(i), PM_I(i), mod); // add pm[i],mod
else
- UML_ADD(block, DM_I(i), DM_I(i), mod); // add dm[i],mod
+ UML_ADD(block, DM_I(i), DM_I(i), mod); // add dm[i],mod
generate_update_circular_buffer(block, compiler, desc, g, i);
}
@@ -3420,7 +3420,7 @@ int adsp21062_device::generate_opcode(drcuml_block *block, compiler_state *compi
case 4:
{
- if (opcode & U64(0x100000000000)) // immediate data -> DM|PM |100|1|
+ if (opcode & U64(0x100000000000)) // immediate data -> DM|PM |100|1|
{
int i = (opcode >> 41) & 0x7;
int m = (opcode >> 38) & 0x7;
@@ -3441,14 +3441,14 @@ int adsp21062_device::generate_opcode(drcuml_block *block, compiler_state *compi
UML_MOV(block, I0, data);
UML_MOV(block, I1, DM_I(i));
UML_CALLH(block, *m_dm_write32);
- UML_ADD(block, DM_I(i), DM_I(i), DM_M(m));
+ UML_ADD(block, DM_I(i), DM_I(i), DM_M(m));
}
generate_update_circular_buffer(block, compiler, desc, g, i);
return TRUE;
}
- else // immediate shift / dreg <-> DM|PM |100|0|
+ else // immediate shift / dreg <-> DM|PM |100|0|
{
int i = (opcode >> 41) & 0x7;
int m = (opcode >> 38) & 0x7;
@@ -3484,12 +3484,12 @@ int adsp21062_device::generate_opcode(drcuml_block *block, compiler_state *compi
generate_shift_imm(block, compiler, desc, data, shiftop, rn, rx);
// transfer
- UML_MOV(block, I1, (g) ? PM_I(i) : DM_I(i)); // mov i1,dm|pm[i]
+ UML_MOV(block, I1, (g) ? PM_I(i) : DM_I(i)); // mov i1,dm|pm[i]
if (temp_dreg)
- UML_MOV(block, I0, mem(&m_core->dreg_temp)); // mov i0,[m_core->dreg_temp]
+ UML_MOV(block, I0, mem(&m_core->dreg_temp)); // mov i0,[m_core->dreg_temp]
else
- UML_MOV(block, I0, REG(dreg)); // mov i0,reg[dreg]
- UML_CALLH(block, (g) ? *m_pm_write32 : *m_dm_write32); // callh dm|pm_write32
+ UML_MOV(block, I0, REG(dreg)); // mov i0,reg[dreg]
+ UML_CALLH(block, (g) ? *m_pm_write32 : *m_dm_write32); // callh dm|pm_write32
}
else
{
@@ -3499,9 +3499,9 @@ int adsp21062_device::generate_opcode(drcuml_block *block, compiler_state *compi
generate_shift_imm(block, compiler, desc, data, shiftop, rn, rx);
// transfer
- UML_MOV(block, I1, (g) ? PM_I(i) : DM_I(i)); // mov i1,dm|pm[i]
- UML_CALLH(block, (g) ? *m_pm_read32 : *m_dm_read32); // callh dm|pm_read32
- UML_MOV(block, REG(dreg), I0); // mov reg[dreg],i0
+ UML_MOV(block, I1, (g) ? PM_I(i) : DM_I(i)); // mov i1,dm|pm[i]
+ UML_CALLH(block, (g) ? *m_pm_read32 : *m_dm_read32); // callh dm|pm_read32
+ UML_MOV(block, REG(dreg), I0); // mov reg[dreg],i0
}
// update I
@@ -3520,42 +3520,42 @@ int adsp21062_device::generate_opcode(drcuml_block *block, compiler_state *compi
break;
}
- case 5: // ureg <-> DM|PM (indirect) |101|
+ case 5: // ureg <-> DM|PM (indirect) |101|
{
int g = (opcode >> 44) & 1;
int d = (opcode >> 40) & 1;
int i = (opcode >> 41) & 0x7;
int ureg = (opcode >> 32) & 0xff;
UINT32 offset = (UINT32)opcode;
-
+
if (d)
{
// UREG -> DM|PM
- UML_ADD(block, I1, (g) ? PM_I(i) : DM_I(i), offset); // add i1,dm|pm[i],offset
+ UML_ADD(block, I1, (g) ? PM_I(i) : DM_I(i), offset); // add i1,dm|pm[i],offset
generate_read_ureg(block, compiler, desc, ureg, false);
- if (ureg == 0xdb && (g)) // PX is 48-bit when writing to PM
- UML_CALLH(block, *m_pm_write48); // callh pm_write48
+ if (ureg == 0xdb && (g)) // PX is 48-bit when writing to PM
+ UML_CALLH(block, *m_pm_write48); // callh pm_write48
else
- UML_CALLH(block, (g) ? *m_pm_write32 : *m_dm_write32); // callh dm|pm_write32
+ UML_CALLH(block, (g) ? *m_pm_write32 : *m_dm_write32); // callh dm|pm_write32
}
else
{
// DM|PM -> UREG
- UML_ADD(block, I1, (g) ? PM_I(i) : DM_I(i), offset); // add i1,dm|pm[i],offset
+ UML_ADD(block, I1, (g) ? PM_I(i) : DM_I(i), offset); // add i1,dm|pm[i],offset
- if (ureg == 0xdb && (g)) // PX is 48-bit when reading from PM
- UML_CALLH(block, *m_pm_read48); // callh pm_read48
+ if (ureg == 0xdb && (g)) // PX is 48-bit when reading from PM
+ UML_CALLH(block, *m_pm_read48); // callh pm_read48
else
- UML_CALLH(block, (g) ? *m_pm_read32 : *m_dm_read32); // callh dm|pm_read32
+ UML_CALLH(block, (g) ? *m_pm_read32 : *m_dm_read32); // callh dm|pm_read32
generate_write_ureg(block, compiler, desc, ureg, false, 0);
}
return TRUE;
}
- case 6: // indirect jump / compute / dreg <-> DM |110|
+ case 6: // indirect jump / compute / dreg <-> DM |110|
{
int d = (opcode >> 44) & 0x1;
int dmi = (opcode >> 41) & 0x7;
@@ -3616,7 +3616,7 @@ int adsp21062_device::generate_opcode(drcuml_block *block, compiler_state *compi
return TRUE;
}
- case 7: // indirect jump / compute / dreg <-> DM |111|
+ case 7: // indirect jump / compute / dreg <-> DM |111|
{
int d = (opcode >> 44) & 0x1;
int dmi = (opcode >> 41) & 0x7;
@@ -3698,7 +3698,7 @@ void adsp21062_device::generate_compute(drcuml_block *block, compiler_state *com
int ry = (opcode >> 0) & 0xf;
int ps = (opcode >> 16) & 0xf;
- if (opcode & 0x400000) // multi-function operation
+ if (opcode & 0x400000) // multi-function operation
{
UINT32 multiop = (opcode >> 16) & 0x3f;
int fm = rs;
@@ -3710,65 +3710,65 @@ void adsp21062_device::generate_compute(drcuml_block *block, compiler_state *com
switch (multiop)
{
- case 0x00: // Rn = MRxx
- {
+ case 0x00: // Rn = MRxx
+ {
generate_unimplemented_compute(block, compiler, desc);
return;
}
- case 0x01: // MRxx = Rn
+ case 0x01: // MRxx = Rn
{
int ai = rs;
switch (ai)
{
- case 0x00: // MR0F
+ case 0x00: // MR0F
UML_DAND(block, MRF, MRF, U64(0xffffffff00000000));
UML_AND(block, I0, REG(rn), 0xffffffff);
UML_DOR(block, MRF, MRF, I0);
break;
- case 0x01: // MR1F
+ case 0x01: // MR1F
UML_DAND(block, MRF, MRF, U64(0x00000000ffffffff));
UML_DSHL(block, I0, REG(rn), 32);
UML_DOR(block, MRF, MRF, I0);
- break;
- case 0x04: // MR0B
+ break;
+ case 0x04: // MR0B
UML_DAND(block, MRB, MRB, U64(0xffffffff00000000));
UML_AND(block, I0, REG(rn), 0xffffffff);
UML_DOR(block, MRB, MRB, I0);
break;
- case 0x05: // MR1B
+ case 0x05: // MR1B
UML_DAND(block, MRB, MRB, U64(0x00000000ffffffff));
UML_DSHL(block, I0, REG(rn), 32);
UML_DOR(block, MRB, MRB, I0);
break;
- case 0x02: // MR2F
- case 0x06: // MR2B
+ case 0x02: // MR2F
+ case 0x06: // MR2B
generate_unimplemented_compute(block, compiler, desc);
return;
}
return;
}
- case 0x07: // Ra = Rx + Ry, Rs = Rx - Ry
- case 0x0f: // Fa = Fx + Fy, Fs = Fx - Fy
- case 0x06: // Rm = R3-0 * R7-4 (SSFR), Ra = (R11-8 + R15-12) / 2
- case 0x08: // MRF = MRF + R3-0 * R7-4 (SSF), Ra = R11-8 + R15-12
- case 0x09: // MRF = MRF + R3-0 * R7-4 (SSF), Ra = R11-8 - R15-12
- case 0x0a: // MRF = MRF + R3-0 * R7-4 (SSF), Ra = (R11-8 + R15-12) / 2
- case 0x0c: // Rm = MRF + R3-0 * R7-4 (SSFR), Ra = R11-8 + R15-12
- case 0x0d: // Rm = MRF + R3-0 * R7-4 (SSFR), Ra = R11-8 - R15-12
- case 0x0e: // Rm = MRF + R3-0 * R7-4 (SSFR), Ra = (R11-8 + R15-12) / 2
- case 0x10: // MRF = MRF - R3-0 * R7-4 (SSF), Ra = R11-8 + R15-12
- case 0x11: // MRF = MRF - R3-0 * R7-4 (SSF), Ra = R11-8 - R15-12
- case 0x12: // MRF = MRF - R3-0 * R7-4 (SSF), Ra = (R11-8 + R15-12) / 2
- case 0x14: // Rm = MRF - R3-0 * R7-4 (SSFR), Ra = R11-8 + R15-12
- case 0x15: // Rm = MRF - R3-0 * R7-4 (SSFR), Ra = R11-8 - R15-12
- case 0x16: // Rm = MRF - R3-0 * R7-4 (SSFR), Ra = (R11-8 + R15-12) / 2
+ case 0x07: // Ra = Rx + Ry, Rs = Rx - Ry
+ case 0x0f: // Fa = Fx + Fy, Fs = Fx - Fy
+ case 0x06: // Rm = R3-0 * R7-4 (SSFR), Ra = (R11-8 + R15-12) / 2
+ case 0x08: // MRF = MRF + R3-0 * R7-4 (SSF), Ra = R11-8 + R15-12
+ case 0x09: // MRF = MRF + R3-0 * R7-4 (SSF), Ra = R11-8 - R15-12
+ case 0x0a: // MRF = MRF + R3-0 * R7-4 (SSF), Ra = (R11-8 + R15-12) / 2
+ case 0x0c: // Rm = MRF + R3-0 * R7-4 (SSFR), Ra = R11-8 + R15-12
+ case 0x0d: // Rm = MRF + R3-0 * R7-4 (SSFR), Ra = R11-8 - R15-12
+ case 0x0e: // Rm = MRF + R3-0 * R7-4 (SSFR), Ra = (R11-8 + R15-12) / 2
+ case 0x10: // MRF = MRF - R3-0 * R7-4 (SSF), Ra = R11-8 + R15-12
+ case 0x11: // MRF = MRF - R3-0 * R7-4 (SSF), Ra = R11-8 - R15-12
+ case 0x12: // MRF = MRF - R3-0 * R7-4 (SSF), Ra = (R11-8 + R15-12) / 2
+ case 0x14: // Rm = MRF - R3-0 * R7-4 (SSFR), Ra = R11-8 + R15-12
+ case 0x15: // Rm = MRF - R3-0 * R7-4 (SSFR), Ra = R11-8 - R15-12
+ case 0x16: // Rm = MRF - R3-0 * R7-4 (SSFR), Ra = (R11-8 + R15-12) / 2
generate_unimplemented_compute(block, compiler, desc);
return;
- case 0x1c: // Fm = F3-0 * F7-4, Fa = (F11-8 + F15-12) / 2
+ case 0x1c: // Fm = F3-0 * F7-4, Fa = (F11-8 + F15-12) / 2
generate_unimplemented_compute(block, compiler, desc);
return;
@@ -3802,10 +3802,10 @@ void adsp21062_device::generate_compute(drcuml_block *block, compiler_state *com
if (AZ_CALC_REQUIRED) UML_OR(block, ASTAT_AZ, ASTAT_AZ, I0);
if (AN_CALC_REQUIRED) UML_OR(block, ASTAT_AN, ASTAT_AN, I1);
- if (AV_CALC_REQUIRED) UML_MOV(block, ASTAT_AV, 0); // TODO
+ if (AV_CALC_REQUIRED) UML_MOV(block, ASTAT_AV, 0); // TODO
if (AC_CALC_REQUIRED) UML_MOV(block, ASTAT_AC, 0);
if (AS_CALC_REQUIRED) UML_MOV(block, ASTAT_AS, 0);
- if (AI_CALC_REQUIRED) UML_MOV(block, ASTAT_AI, 0); // TODO
+ if (AI_CALC_REQUIRED) UML_MOV(block, ASTAT_AI, 0); // TODO
if (MN_CALC_REQUIRED)
UML_FSCMP(block, F0, mem(&m_core->fp0));
@@ -3817,7 +3817,7 @@ void adsp21062_device::generate_compute(drcuml_block *block, compiler_state *com
UML_ICOPYFS(block, REG(ps), F5);
return;
- case 0x04: // Rm = R3-0 * R7-4 (SSFR), Ra = R11-8 + R15-12
+ case 0x04: // Rm = R3-0 * R7-4 (SSFR), Ra = R11-8 + R15-12
UML_DSEXT(block, I0, REG(fxm), SIZE_DWORD);
UML_DSEXT(block, I1, REG(fym), SIZE_DWORD);
UML_DMULS(block, I0, I0, I0, I1);
@@ -3837,7 +3837,7 @@ void adsp21062_device::generate_compute(drcuml_block *block, compiler_state *com
UML_MOV(block, REG(fa), I2);
return;
- case 0x05: // Rm = R3-0 * R7-4 (SSFR), Ra = R11-8 - R15-12
+ case 0x05: // Rm = R3-0 * R7-4 (SSFR), Ra = R11-8 - R15-12
UML_DSEXT(block, I0, REG(fxm), SIZE_DWORD);
UML_DSEXT(block, I1, REG(fym), SIZE_DWORD);
UML_DMULS(block, I0, I0, I0, I1);
@@ -3857,7 +3857,7 @@ void adsp21062_device::generate_compute(drcuml_block *block, compiler_state *com
UML_MOV(block, REG(fa), I2);
return;
- case 0x18: // Fm = F3-0 * F7-4, Fa = F11-8 + F15-12
+ case 0x18: // Fm = F3-0 * F7-4, Fa = F11-8 + F15-12
// TODO: denormals
UML_FSCOPYI(block, F0, REG(fxm));
UML_FSCOPYI(block, F1, REG(fym));
@@ -3870,11 +3870,11 @@ void adsp21062_device::generate_compute(drcuml_block *block, compiler_state *com
UML_FSCMP(block, F2, mem(&m_core->fp0));
if (AZ_CALC_REQUIRED) UML_SETc(block, COND_Z, ASTAT_AZ);
if (AN_CALC_REQUIRED) UML_SETc(block, COND_C, ASTAT_AN);
- if (AV_CALC_REQUIRED) UML_MOV(block, ASTAT_AV, 0); // TODO
+ if (AV_CALC_REQUIRED) UML_MOV(block, ASTAT_AV, 0); // TODO
if (AC_CALC_REQUIRED) UML_MOV(block, ASTAT_AC, 0);
if (AS_CALC_REQUIRED) UML_MOV(block, ASTAT_AS, 0);
- if (AI_CALC_REQUIRED) UML_MOV(block, ASTAT_AI, 0); // TODO
-
+ if (AI_CALC_REQUIRED) UML_MOV(block, ASTAT_AI, 0); // TODO
+
if (MN_CALC_REQUIRED)
UML_FSCMP(block, F0, mem(&m_core->fp0));
if (MN_CALC_REQUIRED) UML_SETc(block, COND_C, ASTAT_MN);
@@ -3884,7 +3884,7 @@ void adsp21062_device::generate_compute(drcuml_block *block, compiler_state *com
UML_ICOPYFS(block, REG(fa), F2);
return;
- case 0x19: // Fm = F3-0 * F7-4, Fa = F11-8 - F15-12
+ case 0x19: // Fm = F3-0 * F7-4, Fa = F11-8 - F15-12
// TODO: denormals
UML_FSCOPYI(block, F0, REG(fxm));
UML_FSCOPYI(block, F1, REG(fym));
@@ -3897,10 +3897,10 @@ void adsp21062_device::generate_compute(drcuml_block *block, compiler_state *com
UML_FSCMP(block, F2, mem(&m_core->fp0));
if (AZ_CALC_REQUIRED) UML_SETc(block, COND_Z, ASTAT_AZ);
if (AN_CALC_REQUIRED) UML_SETc(block, COND_C, ASTAT_AN);
- if (AV_CALC_REQUIRED) UML_MOV(block, ASTAT_AV, 0); // TODO
+ if (AV_CALC_REQUIRED) UML_MOV(block, ASTAT_AV, 0); // TODO
if (AC_CALC_REQUIRED) UML_MOV(block, ASTAT_AC, 0);
if (AS_CALC_REQUIRED) UML_MOV(block, ASTAT_AS, 0);
- if (AI_CALC_REQUIRED) UML_MOV(block, ASTAT_AI, 0); // TODO
+ if (AI_CALC_REQUIRED) UML_MOV(block, ASTAT_AI, 0); // TODO
if (MN_CALC_REQUIRED)
UML_FSCMP(block, F0, mem(&m_core->fp0));
@@ -3911,7 +3911,7 @@ void adsp21062_device::generate_compute(drcuml_block *block, compiler_state *com
UML_ICOPYFS(block, REG(fa), F2);
return;
- case 0x1a: // Fm = F3-0 * F7-4, Fa = FLOAT F11-8 BY R15-12
+ case 0x1a: // Fm = F3-0 * F7-4, Fa = FLOAT F11-8 BY R15-12
{
code_label denormal = compiler->labelnum++;
code_label end = compiler->labelnum++;
@@ -3937,7 +3937,7 @@ void adsp21062_device::generate_compute(drcuml_block *block, compiler_state *com
UML_OR(block, I0, I0, I1);
if (AZ_CALC_REQUIRED) UML_SETc(block, COND_Z, ASTAT_AZ);
if (AN_CALC_REQUIRED) UML_SETc(block, COND_S, ASTAT_AN);
- if (AV_CALC_REQUIRED) UML_MOV(block, ASTAT_AV, 0); // TODO
+ if (AV_CALC_REQUIRED) UML_MOV(block, ASTAT_AV, 0); // TODO
if (AC_CALC_REQUIRED) UML_MOV(block, ASTAT_AC, 0);
if (AS_CALC_REQUIRED) UML_MOV(block, ASTAT_AS, 0);
if (AI_CALC_REQUIRED) UML_MOV(block, ASTAT_AI, 0);
@@ -3947,7 +3947,7 @@ void adsp21062_device::generate_compute(drcuml_block *block, compiler_state *com
UML_AND(block, I0, I1, 0x80000000);
if (AZ_CALC_REQUIRED) UML_MOV(block, ASTAT_AZ, 1);
if (AN_CALC_REQUIRED) UML_MOV(block, ASTAT_AN, 0);
- if (AV_CALC_REQUIRED) UML_MOV(block, ASTAT_AV, 0); // TODO
+ if (AV_CALC_REQUIRED) UML_MOV(block, ASTAT_AV, 0); // TODO
if (AC_CALC_REQUIRED) UML_MOV(block, ASTAT_AC, 0);
if (AS_CALC_REQUIRED) UML_MOV(block, ASTAT_AS, 0);
if (AI_CALC_REQUIRED) UML_MOV(block, ASTAT_AI, 0);
@@ -3964,7 +3964,7 @@ void adsp21062_device::generate_compute(drcuml_block *block, compiler_state *com
return;
}
- case 0x1b: // Fm = F3-0 * F7-4, Fa = FIX F11-8 BY R15-12
+ case 0x1b: // Fm = F3-0 * F7-4, Fa = FIX F11-8 BY R15-12
{
code_label denormal = compiler->labelnum++;
code_label end = compiler->labelnum++;
@@ -3989,7 +3989,7 @@ void adsp21062_device::generate_compute(drcuml_block *block, compiler_state *com
UML_OR(block, I0, I0, I1);
if (AZ_CALC_REQUIRED) UML_SETc(block, COND_Z, ASTAT_AZ);
if (AN_CALC_REQUIRED) UML_SETc(block, COND_S, ASTAT_AN);
- if (AV_CALC_REQUIRED) UML_MOV(block, ASTAT_AV, 0); // TODO
+ if (AV_CALC_REQUIRED) UML_MOV(block, ASTAT_AV, 0); // TODO
if (AC_CALC_REQUIRED) UML_MOV(block, ASTAT_AC, 0);
if (AS_CALC_REQUIRED) UML_MOV(block, ASTAT_AS, 0);
if (AI_CALC_REQUIRED) UML_MOV(block, ASTAT_AI, 0);
@@ -3999,7 +3999,7 @@ void adsp21062_device::generate_compute(drcuml_block *block, compiler_state *com
UML_AND(block, I0, I1, 0x80000000);
if (AZ_CALC_REQUIRED) UML_MOV(block, ASTAT_AZ, 1);
if (AN_CALC_REQUIRED) UML_MOV(block, ASTAT_AN, 0);
- if (AV_CALC_REQUIRED) UML_MOV(block, ASTAT_AV, 0); // TODO
+ if (AV_CALC_REQUIRED) UML_MOV(block, ASTAT_AV, 0); // TODO
if (AC_CALC_REQUIRED) UML_MOV(block, ASTAT_AC, 0);
if (AS_CALC_REQUIRED) UML_MOV(block, ASTAT_AS, 0);
if (AI_CALC_REQUIRED) UML_MOV(block, ASTAT_AI, 0);
@@ -4025,18 +4025,18 @@ void adsp21062_device::generate_compute(drcuml_block *block, compiler_state *com
return;
}
- case 0x1d: // Fm = F3-0 * F7-4, Fa = ABS F11-8
+ case 0x1d: // Fm = F3-0 * F7-4, Fa = ABS F11-8
UML_FSCOPYI(block, F0, REG(fxm));
UML_FSCOPYI(block, F1, REG(fym));
UML_AND(block, I0, REG(fxa), 0x7fffffff);
UML_FSMUL(block, F0, F0, F1);
- if (AZ_CALC_REQUIRED) UML_MOV(block, ASTAT_AZ, 0); // TODO
+ if (AZ_CALC_REQUIRED) UML_MOV(block, ASTAT_AZ, 0); // TODO
if (AN_CALC_REQUIRED) UML_MOV(block, ASTAT_AN, 0);
if (AV_CALC_REQUIRED) UML_MOV(block, ASTAT_AV, 0);
if (AC_CALC_REQUIRED) UML_MOV(block, ASTAT_AC, 0);
- if (AS_CALC_REQUIRED) UML_MOV(block, ASTAT_AS, 0); // TODO
- if (AI_CALC_REQUIRED) UML_MOV(block, ASTAT_AI, 0); // TODO
+ if (AS_CALC_REQUIRED) UML_MOV(block, ASTAT_AS, 0); // TODO
+ if (AI_CALC_REQUIRED) UML_MOV(block, ASTAT_AI, 0); // TODO
if (MN_CALC_REQUIRED)
UML_FSCMP(block, F0, mem(&m_core->fp0));
@@ -4047,7 +4047,7 @@ void adsp21062_device::generate_compute(drcuml_block *block, compiler_state *com
UML_MOV(block, REG(fa), I0);
return;
- case 0x1e: // Fm = F3-0 * F7-4, Fa = MAX(F11-8, F15-12)
+ case 0x1e: // Fm = F3-0 * F7-4, Fa = MAX(F11-8, F15-12)
// TODO: denormals
UML_FSCOPYI(block, F0, REG(fxm));
UML_FSCOPYI(block, F1, REG(fym));
@@ -4063,10 +4063,10 @@ void adsp21062_device::generate_compute(drcuml_block *block, compiler_state *com
UML_FSCMP(block, F4, mem(&m_core->fp0));
if (AZ_CALC_REQUIRED) UML_SETc(block, COND_Z, ASTAT_AZ);
if (AN_CALC_REQUIRED) UML_SETc(block, COND_C, ASTAT_AN);
- if (AV_CALC_REQUIRED) UML_MOV(block, ASTAT_AV, 0); // TODO
+ if (AV_CALC_REQUIRED) UML_MOV(block, ASTAT_AV, 0); // TODO
if (AC_CALC_REQUIRED) UML_MOV(block, ASTAT_AC, 0);
if (AS_CALC_REQUIRED) UML_MOV(block, ASTAT_AS, 0);
- if (AI_CALC_REQUIRED) UML_MOV(block, ASTAT_AI, 0); // TODO
+ if (AI_CALC_REQUIRED) UML_MOV(block, ASTAT_AI, 0); // TODO
if (MN_CALC_REQUIRED)
UML_FSCMP(block, F0, mem(&m_core->fp0));
@@ -4077,7 +4077,7 @@ void adsp21062_device::generate_compute(drcuml_block *block, compiler_state *com
UML_ICOPYFS(block, REG(fa), F4);
return;
- case 0x1f: // Fm = F3-0 * F7-4, Fa = MIN(F11-8, F15-12)
+ case 0x1f: // Fm = F3-0 * F7-4, Fa = MIN(F11-8, F15-12)
// TODO: denormals
UML_FSCOPYI(block, F0, REG(fxm));
UML_FSCOPYI(block, F1, REG(fym));
@@ -4093,10 +4093,10 @@ void adsp21062_device::generate_compute(drcuml_block *block, compiler_state *com
UML_FSCMP(block, F4, mem(&m_core->fp0));
if (AZ_CALC_REQUIRED) UML_SETc(block, COND_Z, ASTAT_AZ);
if (AN_CALC_REQUIRED) UML_SETc(block, COND_C, ASTAT_AN);
- if (AV_CALC_REQUIRED) UML_MOV(block, ASTAT_AV, 0); // TODO
+ if (AV_CALC_REQUIRED) UML_MOV(block, ASTAT_AV, 0); // TODO
if (AC_CALC_REQUIRED) UML_MOV(block, ASTAT_AC, 0);
if (AS_CALC_REQUIRED) UML_MOV(block, ASTAT_AS, 0);
- if (AI_CALC_REQUIRED) UML_MOV(block, ASTAT_AI, 0); // TODO
+ if (AI_CALC_REQUIRED) UML_MOV(block, ASTAT_AI, 0); // TODO
if (MN_CALC_REQUIRED)
UML_FSCMP(block, F0, mem(&m_core->fp0));
@@ -4112,35 +4112,35 @@ void adsp21062_device::generate_compute(drcuml_block *block, compiler_state *com
return;
}
}
- else // single-function operation
+ else // single-function operation
{
UINT32 operation = (opcode >> 12) & 0xff;
switch ((opcode >> 20) & 3)
{
- case 0: // ALU operations
+ case 0: // ALU operations
{
switch (operation)
{
- case 0x09: // Rn = (Rx + Ry) / 2
- case 0x63: // Rn = CLIP Rx BY Ry
- case 0x92: // Fn = ABS(Fx - Fy)
- case 0x89: // Fn = (Fx + Fy) / 2
- case 0xdd: // Rn = TRUNC Fx BY Ry
- case 0xe0: // Fn = Fx COPYSIGN Fy
- case 0x05: // Rn = Rx + Ry + CI
- case 0x06: // Rn = Rx - Ry + CI - 1
- case 0x25: // Rn = Rx + CI
- case 0x26: // Rn = Rx + CI - 1
- case 0x30: // Rn = ABS Rx
- case 0x43: // Rn = NOT Rx
- case 0xa5: // Fn = RND Fx
- case 0xad: // Rn = MANT Fx
- case 0xcd: // Rn = TRUNC Fx
+ case 0x09: // Rn = (Rx + Ry) / 2
+ case 0x63: // Rn = CLIP Rx BY Ry
+ case 0x92: // Fn = ABS(Fx - Fy)
+ case 0x89: // Fn = (Fx + Fy) / 2
+ case 0xdd: // Rn = TRUNC Fx BY Ry
+ case 0xe0: // Fn = Fx COPYSIGN Fy
+ case 0x05: // Rn = Rx + Ry + CI
+ case 0x06: // Rn = Rx - Ry + CI - 1
+ case 0x25: // Rn = Rx + CI
+ case 0x26: // Rn = Rx + CI - 1
+ case 0x30: // Rn = ABS Rx
+ case 0x43: // Rn = NOT Rx
+ case 0xa5: // Fn = RND Fx
+ case 0xad: // Rn = MANT Fx
+ case 0xcd: // Rn = TRUNC Fx
generate_unimplemented_compute(block, compiler, desc);
return;
- case 0x01: // Rn = Rx + Ry
+ case 0x01: // Rn = Rx + Ry
UML_ADD(block, REG(rn), REG(rx), REG(ry));
if (AZ_CALC_REQUIRED) UML_SETc(block, COND_Z, ASTAT_AZ);
if (AN_CALC_REQUIRED) UML_SETc(block, COND_S, ASTAT_AN);
@@ -4150,7 +4150,7 @@ void adsp21062_device::generate_compute(drcuml_block *block, compiler_state *com
if (AI_CALC_REQUIRED) UML_MOV(block, ASTAT_AI, 0);
return;
- case 0x02: // Rn = Rx - Ry
+ case 0x02: // Rn = Rx - Ry
UML_SUB(block, REG(rn), REG(rx), REG(ry));
if (AZ_CALC_REQUIRED) UML_SETc(block, COND_Z, ASTAT_AZ);
if (AN_CALC_REQUIRED) UML_SETc(block, COND_S, ASTAT_AN);
@@ -4160,7 +4160,7 @@ void adsp21062_device::generate_compute(drcuml_block *block, compiler_state *com
if (AI_CALC_REQUIRED) UML_MOV(block, ASTAT_AI, 0);
return;
- case 0x0a: // COMP(Rx, Ry)
+ case 0x0a: // COMP(Rx, Ry)
UML_CMP(block, REG(rx), REG(ry));
UML_SETc(block, COND_Z, I0);
UML_SETc(block, COND_L, I1);
@@ -4182,7 +4182,7 @@ void adsp21062_device::generate_compute(drcuml_block *block, compiler_state *com
if (AI_CALC_REQUIRED) UML_MOV(block, ASTAT_AI, 0);
return;
- case 0x21: // Rn = PASS Rx
+ case 0x21: // Rn = PASS Rx
UML_MOV(block, REG(rn), REG(rx));
if (AZ_CALC_REQUIRED || AN_CALC_REQUIRED)
UML_CMP(block, REG(rn), 0);
@@ -4194,7 +4194,7 @@ void adsp21062_device::generate_compute(drcuml_block *block, compiler_state *com
if (AI_CALC_REQUIRED) UML_MOV(block, ASTAT_AI, 0);
return;
- case 0x22: // Rn = -Rx
+ case 0x22: // Rn = -Rx
UML_SUB(block, REG(rn), 0, REG(rx));
if (AZ_CALC_REQUIRED) UML_SETc(block, COND_Z, ASTAT_AZ);
if (AN_CALC_REQUIRED) UML_SETc(block, COND_S, ASTAT_AN);
@@ -4204,7 +4204,7 @@ void adsp21062_device::generate_compute(drcuml_block *block, compiler_state *com
if (AI_CALC_REQUIRED) UML_MOV(block, ASTAT_AI, 0);
return;
- case 0x29: // Rn = Rx + 1
+ case 0x29: // Rn = Rx + 1
UML_ADD(block, REG(rn), REG(rx), 1);
if (AZ_CALC_REQUIRED) UML_SETc(block, COND_Z, ASTAT_AZ);
if (AN_CALC_REQUIRED) UML_SETc(block, COND_S, ASTAT_AN);
@@ -4214,7 +4214,7 @@ void adsp21062_device::generate_compute(drcuml_block *block, compiler_state *com
if (AI_CALC_REQUIRED) UML_MOV(block, ASTAT_AI, 0);
return;
- case 0x2a: // Rn = Rx - 1
+ case 0x2a: // Rn = Rx - 1
UML_SUB(block, REG(rn), REG(rx), 1);
if (AZ_CALC_REQUIRED) UML_SETc(block, COND_Z, ASTAT_AZ);
if (AN_CALC_REQUIRED) UML_SETc(block, COND_S, ASTAT_AN);
@@ -4224,7 +4224,7 @@ void adsp21062_device::generate_compute(drcuml_block *block, compiler_state *com
if (AI_CALC_REQUIRED) UML_MOV(block, ASTAT_AI, 0);
return;
- case 0x40: // Rn = Rx AND Ry
+ case 0x40: // Rn = Rx AND Ry
UML_AND(block, REG(rn), REG(rx), REG(ry));
if (AZ_CALC_REQUIRED) UML_SETc(block, COND_Z, ASTAT_AZ);
if (AN_CALC_REQUIRED) UML_SETc(block, COND_S, ASTAT_AN);
@@ -4234,7 +4234,7 @@ void adsp21062_device::generate_compute(drcuml_block *block, compiler_state *com
if (AI_CALC_REQUIRED) UML_MOV(block, ASTAT_AI, 0);
return;
- case 0x41: // Rn = Rx OR Ry
+ case 0x41: // Rn = Rx OR Ry
UML_OR(block, REG(rn), REG(rx), REG(ry));
if (AZ_CALC_REQUIRED) UML_SETc(block, COND_Z, ASTAT_AZ);
if (AN_CALC_REQUIRED) UML_SETc(block, COND_S, ASTAT_AN);
@@ -4244,7 +4244,7 @@ void adsp21062_device::generate_compute(drcuml_block *block, compiler_state *com
if (AI_CALC_REQUIRED) UML_MOV(block, ASTAT_AI, 0);
return;
- case 0x42: // Rn = Rx XOR Ry
+ case 0x42: // Rn = Rx XOR Ry
UML_XOR(block, REG(rn), REG(rx), REG(ry));
if (AZ_CALC_REQUIRED) UML_SETc(block, COND_Z, ASTAT_AZ);
if (AN_CALC_REQUIRED) UML_SETc(block, COND_S, ASTAT_AN);
@@ -4254,7 +4254,7 @@ void adsp21062_device::generate_compute(drcuml_block *block, compiler_state *com
if (AI_CALC_REQUIRED) UML_MOV(block, ASTAT_AI, 0);
return;
- case 0x61: // Rn = MIN(Rx, Ry)
+ case 0x61: // Rn = MIN(Rx, Ry)
UML_MOV(block, REG(rn), REG(rx));
UML_CMP(block, REG(rx), REG(ry));
UML_MOVc(block, COND_G, REG(rn), REG(ry));
@@ -4268,7 +4268,7 @@ void adsp21062_device::generate_compute(drcuml_block *block, compiler_state *com
if (AI_CALC_REQUIRED) UML_MOV(block, ASTAT_AI, 0);
return;
- case 0x62: // Rn = MAX(Rx, Ry)
+ case 0x62: // Rn = MAX(Rx, Ry)
UML_MOV(block, REG(rn), REG(rx));
UML_CMP(block, REG(rx), REG(ry));
UML_MOVc(block, COND_L, REG(rn), REG(ry));
@@ -4286,7 +4286,7 @@ void adsp21062_device::generate_compute(drcuml_block *block, compiler_state *com
case 0x78: case 0x79: case 0x7a: case 0x7b: case 0x7c: case 0x7d: case 0x7e: case 0x7f:
{
/* Fixed-point Dual Add/Subtract */
- UML_ADD(block, I0, REG(rx), REG(ry));
+ UML_ADD(block, I0, REG(rx), REG(ry));
if (AZ_CALC_REQUIRED) UML_SETc(block, COND_Z, ASTAT_AZ);
if (AN_CALC_REQUIRED) UML_SETc(block, COND_S, ASTAT_AN);
if (AV_CALC_REQUIRED) UML_SETc(block, COND_V, ASTAT_AV);
@@ -4307,7 +4307,7 @@ void adsp21062_device::generate_compute(drcuml_block *block, compiler_state *com
return;
}
- case 0x81: // Fn = Fx + Fy
+ case 0x81: // Fn = Fx + Fy
// TODO: denormals
UML_FSCOPYI(block, F0, REG(rx));
UML_FSCOPYI(block, F1, REG(ry));
@@ -4316,14 +4316,14 @@ void adsp21062_device::generate_compute(drcuml_block *block, compiler_state *com
UML_FSCMP(block, F0, mem(&m_core->fp0));
if (AZ_CALC_REQUIRED) UML_SETc(block, COND_Z, ASTAT_AZ);
if (AN_CALC_REQUIRED) UML_SETc(block, COND_C, ASTAT_AN);
- if (AV_CALC_REQUIRED) UML_MOV(block, ASTAT_AV, 0); // TODO
+ if (AV_CALC_REQUIRED) UML_MOV(block, ASTAT_AV, 0); // TODO
if (AC_CALC_REQUIRED) UML_MOV(block, ASTAT_AC, 0);
if (AS_CALC_REQUIRED) UML_MOV(block, ASTAT_AS, 0);
- if (AI_CALC_REQUIRED) UML_MOV(block, ASTAT_AI, 0); // TODO
+ if (AI_CALC_REQUIRED) UML_MOV(block, ASTAT_AI, 0); // TODO
UML_ICOPYFS(block, REG(rn), F0);
return;
- case 0x82: // Fn = Fx - Fy
+ case 0x82: // Fn = Fx - Fy
// TODO: denormals
UML_FSCOPYI(block, F0, REG(rx));
UML_FSCOPYI(block, F1, REG(ry));
@@ -4332,14 +4332,14 @@ void adsp21062_device::generate_compute(drcuml_block *block, compiler_state *com
UML_FSCMP(block, F0, mem(&m_core->fp0));
if (AZ_CALC_REQUIRED) UML_SETc(block, COND_Z, ASTAT_AZ);
if (AN_CALC_REQUIRED) UML_SETc(block, COND_C, ASTAT_AN);
- if (AV_CALC_REQUIRED) UML_MOV(block, ASTAT_AV, 0); // TODO
+ if (AV_CALC_REQUIRED) UML_MOV(block, ASTAT_AV, 0); // TODO
if (AC_CALC_REQUIRED) UML_MOV(block, ASTAT_AC, 0);
if (AS_CALC_REQUIRED) UML_MOV(block, ASTAT_AS, 0);
- if (AI_CALC_REQUIRED) UML_MOV(block, ASTAT_AI, 0); // TODO
+ if (AI_CALC_REQUIRED) UML_MOV(block, ASTAT_AI, 0); // TODO
UML_ICOPYFS(block, REG(rn), F0);
return;
- case 0x8a: // COMP(Fx, Fy)
+ case 0x8a: // COMP(Fx, Fy)
UML_FSCOPYI(block, F0, REG(rx));
UML_FSCOPYI(block, F1, REG(ry));
UML_FSCMP(block, F0, F1);
@@ -4356,29 +4356,29 @@ void adsp21062_device::generate_compute(drcuml_block *block, compiler_state *com
UML_SHR(block, I2, I2, 1);
UML_OR(block, I2, I2, I0);
UML_MOV(block, mem(&m_core->astat_drc.cacc), I2);
-
+
if (AV_CALC_REQUIRED) UML_MOV(block, ASTAT_AV, 0);
if (AC_CALC_REQUIRED) UML_MOV(block, ASTAT_AC, 0);
if (AS_CALC_REQUIRED) UML_MOV(block, ASTAT_AS, 0);
- if (AI_CALC_REQUIRED) UML_MOV(block, ASTAT_AI, 0); // TODO
+ if (AI_CALC_REQUIRED) UML_MOV(block, ASTAT_AI, 0); // TODO
return;
- case 0x91: // Fn = ABS(Fx + Fy)
+ case 0x91: // Fn = ABS(Fx + Fy)
// TODO: denormals
UML_FSCOPYI(block, F0, REG(rx));
UML_FSCOPYI(block, F1, REG(ry));
UML_FSADD(block, F0, F0, F1);
UML_FSABS(block, F0, F0);
UML_ICOPYFS(block, REG(rn), F0);
- if (AZ_CALC_REQUIRED) UML_MOV(block, ASTAT_AZ, 0); // TODO
+ if (AZ_CALC_REQUIRED) UML_MOV(block, ASTAT_AZ, 0); // TODO
if (AN_CALC_REQUIRED) UML_MOV(block, ASTAT_AN, 0);
- if (AV_CALC_REQUIRED) UML_MOV(block, ASTAT_AV, 0); // TODO
+ if (AV_CALC_REQUIRED) UML_MOV(block, ASTAT_AV, 0); // TODO
if (AC_CALC_REQUIRED) UML_MOV(block, ASTAT_AC, 0);
if (AS_CALC_REQUIRED) UML_MOV(block, ASTAT_AS, 0);
- if (AI_CALC_REQUIRED) UML_MOV(block, ASTAT_AI, 0); // TODO
+ if (AI_CALC_REQUIRED) UML_MOV(block, ASTAT_AI, 0); // TODO
return;
- case 0xa1: // Fn = PASS Fx
+ case 0xa1: // Fn = PASS Fx
UML_MOV(block, REG(rn), REG(rx));
if (AZ_CALC_REQUIRED || AN_CALC_REQUIRED)
{
@@ -4390,10 +4390,10 @@ void adsp21062_device::generate_compute(drcuml_block *block, compiler_state *com
if (AV_CALC_REQUIRED) UML_MOV(block, ASTAT_AV, 0);
if (AC_CALC_REQUIRED) UML_MOV(block, ASTAT_AC, 0);
if (AS_CALC_REQUIRED) UML_MOV(block, ASTAT_AS, 0);
- if (AI_CALC_REQUIRED) UML_MOV(block, ASTAT_AI, 0); // TODO
+ if (AI_CALC_REQUIRED) UML_MOV(block, ASTAT_AI, 0); // TODO
return;
- case 0xa2: // Fn = -Fx
+ case 0xa2: // Fn = -Fx
UML_FSCOPYI(block, F0, REG(rx));
UML_FSNEG(block, F0, F0);
UML_ICOPYFS(block, REG(rn), F0);
@@ -4404,23 +4404,23 @@ void adsp21062_device::generate_compute(drcuml_block *block, compiler_state *com
if (AV_CALC_REQUIRED) UML_MOV(block, ASTAT_AV, 0);
if (AC_CALC_REQUIRED) UML_MOV(block, ASTAT_AC, 0);
if (AS_CALC_REQUIRED) UML_MOV(block, ASTAT_AS, 0);
- if (AI_CALC_REQUIRED) UML_MOV(block, ASTAT_AI, 0); // TODO
+ if (AI_CALC_REQUIRED) UML_MOV(block, ASTAT_AI, 0); // TODO
return;
- case 0xb0: // Fn = ABS(Fx)
+ case 0xb0: // Fn = ABS(Fx)
UML_FSCOPYI(block, F0, REG(rx));
UML_FSABS(block, F0, F0);
UML_ICOPYFS(block, REG(rn), F0);
- if (AZ_CALC_REQUIRED) UML_MOV(block, ASTAT_AZ, 0); // TODO
+ if (AZ_CALC_REQUIRED) UML_MOV(block, ASTAT_AZ, 0); // TODO
if (AN_CALC_REQUIRED) UML_MOV(block, ASTAT_AN, 0);
if (AV_CALC_REQUIRED) UML_MOV(block, ASTAT_AV, 0);
if (AC_CALC_REQUIRED) UML_MOV(block, ASTAT_AC, 0);
- if (AS_CALC_REQUIRED) UML_MOV(block, ASTAT_AS, 0); // TODO
- if (AI_CALC_REQUIRED) UML_MOV(block, ASTAT_AI, 0); // TODO
+ if (AS_CALC_REQUIRED) UML_MOV(block, ASTAT_AS, 0); // TODO
+ if (AI_CALC_REQUIRED) UML_MOV(block, ASTAT_AI, 0); // TODO
return;
- case 0xbd: // Fn = SCALB Fx BY Ry
+ case 0xbd: // Fn = SCALB Fx BY Ry
// TODO: source = nan, result = denormal
UML_MOV(block, I1, REG(rx));
UML_AND(block, I0, I1, 0x7f800000);
@@ -4434,26 +4434,26 @@ void adsp21062_device::generate_compute(drcuml_block *block, compiler_state *com
UML_OR(block, REG(rn), I0, I1);
if (AZ_CALC_REQUIRED) UML_SETc(block, COND_Z, ASTAT_AZ);
if (AN_CALC_REQUIRED) UML_SETc(block, COND_S, ASTAT_AN);
- if (AV_CALC_REQUIRED) UML_MOV(block, ASTAT_AV, 0); // TODO
+ if (AV_CALC_REQUIRED) UML_MOV(block, ASTAT_AV, 0); // TODO
if (AC_CALC_REQUIRED) UML_MOV(block, ASTAT_AC, 0);
if (AS_CALC_REQUIRED) UML_MOV(block, ASTAT_AS, 0);
- if (AI_CALC_REQUIRED) UML_MOV(block, ASTAT_AI, 0); // TODO
+ if (AI_CALC_REQUIRED) UML_MOV(block, ASTAT_AI, 0); // TODO
return;
- case 0xc1: // Rn = LOGB Fx
+ case 0xc1: // Rn = LOGB Fx
// TODO: source = zero, infinity, nan
UML_SHR(block, I0, REG(rx), 23);
UML_AND(block, I0, I0, 0xff);
UML_SUB(block, REG(rn), I0, 127);
if (AZ_CALC_REQUIRED) UML_SETc(block, COND_Z, ASTAT_AZ);
if (AN_CALC_REQUIRED) UML_SETc(block, COND_S, ASTAT_AN);
- if (AV_CALC_REQUIRED) UML_MOV(block, ASTAT_AV, 0); // TODO
+ if (AV_CALC_REQUIRED) UML_MOV(block, ASTAT_AV, 0); // TODO
if (AC_CALC_REQUIRED) UML_MOV(block, ASTAT_AC, 0);
if (AS_CALC_REQUIRED) UML_MOV(block, ASTAT_AS, 0);
if (AI_CALC_REQUIRED) UML_MOV(block, ASTAT_AI, 0);
return;
- case 0xc4: // Fn = RECIPS Fx
+ case 0xc4: // Fn = RECIPS Fx
// TODO: denormals
// TODO: use the bit accurate method from interpreter?
UML_FSCOPYI(block, F0, REG(rx));
@@ -4470,11 +4470,11 @@ void adsp21062_device::generate_compute(drcuml_block *block, compiler_state *com
if (AZ_CALC_REQUIRED) UML_SETc(block, COND_Z, ASTAT_AZ);
if (AC_CALC_REQUIRED) UML_MOV(block, ASTAT_AC, 0);
if (AS_CALC_REQUIRED) UML_MOV(block, ASTAT_AS, 0);
- if (AI_CALC_REQUIRED) UML_MOV(block, ASTAT_AI, 0); // TODO
+ if (AI_CALC_REQUIRED) UML_MOV(block, ASTAT_AI, 0); // TODO
UML_ICOPYFS(block, REG(rn), F0);
return;
- case 0xc5: // Fn = RSQRTS Fx
+ case 0xc5: // Fn = RSQRTS Fx
// TODO: denormals
// TODO: use the bit accurate method from interpreter?
UML_FSCOPYI(block, F0, REG(rx));
@@ -4488,7 +4488,7 @@ void adsp21062_device::generate_compute(drcuml_block *block, compiler_state *com
if (AS_CALC_REQUIRED) UML_MOV(block, ASTAT_AS, 0);
return;
- case 0xca: // Fn = FLOAT Rx
+ case 0xca: // Fn = FLOAT Rx
UML_FSFRINT(block, F0, REG(rx), SIZE_DWORD);
UML_ICOPYFS(block, REG(rn), F0);
if (AZ_CALC_REQUIRED)
@@ -4500,7 +4500,7 @@ void adsp21062_device::generate_compute(drcuml_block *block, compiler_state *com
if (AI_CALC_REQUIRED) UML_MOV(block, ASTAT_AI, 0);
return;
- case 0xc9: // Rn = FIX Fx
+ case 0xc9: // Rn = FIX Fx
UML_FSCOPYI(block, F0, REG(rx));
UML_TEST(block, MODE1, MODE1_TRUNCATE);
UML_JMPc(block, COND_Z, compiler->labelnum);
@@ -4514,14 +4514,14 @@ void adsp21062_device::generate_compute(drcuml_block *block, compiler_state *com
UML_CMP(block, I0, 0);
if (AZ_CALC_REQUIRED) UML_SETc(block, COND_Z, ASTAT_AZ);
if (AN_CALC_REQUIRED) UML_SETc(block, COND_S, ASTAT_AN);
- if (AV_CALC_REQUIRED) UML_MOV(block, ASTAT_AV, 0); // TODO
+ if (AV_CALC_REQUIRED) UML_MOV(block, ASTAT_AV, 0); // TODO
if (AC_CALC_REQUIRED) UML_MOV(block, ASTAT_AC, 0);
if (AS_CALC_REQUIRED) UML_MOV(block, ASTAT_AS, 0);
- if (AI_CALC_REQUIRED) UML_MOV(block, ASTAT_AI, 0); // TODO
+ if (AI_CALC_REQUIRED) UML_MOV(block, ASTAT_AI, 0); // TODO
UML_MOV(block, REG(rn), I0);
- return;
+ return;
- case 0xd9: // Rn = FIX Fx BY Ry
+ case 0xd9: // Rn = FIX Fx BY Ry
{
code_label denormal = compiler->labelnum++;
code_label end = compiler->labelnum++;
@@ -4553,10 +4553,10 @@ void adsp21062_device::generate_compute(drcuml_block *block, compiler_state *com
UML_CMP(block, I0, 0);
if (AZ_CALC_REQUIRED) UML_SETc(block, COND_Z, ASTAT_AZ);
if (AN_CALC_REQUIRED) UML_SETc(block, COND_S, ASTAT_AN);
- if (AV_CALC_REQUIRED) UML_MOV(block, ASTAT_AV, 0); // TODO
+ if (AV_CALC_REQUIRED) UML_MOV(block, ASTAT_AV, 0); // TODO
if (AC_CALC_REQUIRED) UML_MOV(block, ASTAT_AC, 0);
if (AS_CALC_REQUIRED) UML_MOV(block, ASTAT_AS, 0);
- if (AI_CALC_REQUIRED) UML_MOV(block, ASTAT_AI, 0); // TODO
+ if (AI_CALC_REQUIRED) UML_MOV(block, ASTAT_AI, 0); // TODO
UML_MOV(block, REG(rn), I0);
UML_JMP(block, end);
@@ -4564,7 +4564,7 @@ void adsp21062_device::generate_compute(drcuml_block *block, compiler_state *com
UML_AND(block, I0, I1, 0x80000000);
if (AZ_CALC_REQUIRED) UML_MOV(block, ASTAT_AZ, 1);
if (AN_CALC_REQUIRED) UML_MOV(block, ASTAT_AN, 0);
- if (AV_CALC_REQUIRED) UML_MOV(block, ASTAT_AV, 0); // TODO
+ if (AV_CALC_REQUIRED) UML_MOV(block, ASTAT_AV, 0); // TODO
if (AC_CALC_REQUIRED) UML_MOV(block, ASTAT_AC, 0);
if (AS_CALC_REQUIRED) UML_MOV(block, ASTAT_AS, 0);
if (AI_CALC_REQUIRED) UML_MOV(block, ASTAT_AI, 0);
@@ -4574,7 +4574,7 @@ void adsp21062_device::generate_compute(drcuml_block *block, compiler_state *com
return;
}
- case 0xda: // Fn = FLOAT Rx BY Ry
+ case 0xda: // Fn = FLOAT Rx BY Ry
{
code_label denormal = compiler->labelnum++;
code_label end = compiler->labelnum++;
@@ -4594,27 +4594,27 @@ void adsp21062_device::generate_compute(drcuml_block *block, compiler_state *com
UML_OR(block, REG(rn), I0, I1);
if (AZ_CALC_REQUIRED) UML_SETc(block, COND_Z, ASTAT_AZ);
if (AN_CALC_REQUIRED) UML_SETc(block, COND_S, ASTAT_AN);
- if (AV_CALC_REQUIRED) UML_MOV(block, ASTAT_AV, 0); // TODO
+ if (AV_CALC_REQUIRED) UML_MOV(block, ASTAT_AV, 0); // TODO
if (AC_CALC_REQUIRED) UML_MOV(block, ASTAT_AC, 0);
if (AS_CALC_REQUIRED) UML_MOV(block, ASTAT_AS, 0);
if (AI_CALC_REQUIRED) UML_MOV(block, ASTAT_AI, 0);
UML_JMP(block, end);
-
+
UML_LABEL(block, denormal);
UML_AND(block, I0, I1, 0x80000000);
if (AZ_CALC_REQUIRED) UML_MOV(block, ASTAT_AZ, 1);
if (AN_CALC_REQUIRED) UML_MOV(block, ASTAT_AN, 0);
- if (AV_CALC_REQUIRED) UML_MOV(block, ASTAT_AV, 0); // TODO
+ if (AV_CALC_REQUIRED) UML_MOV(block, ASTAT_AV, 0); // TODO
if (AC_CALC_REQUIRED) UML_MOV(block, ASTAT_AC, 0);
if (AS_CALC_REQUIRED) UML_MOV(block, ASTAT_AS, 0);
if (AI_CALC_REQUIRED) UML_MOV(block, ASTAT_AI, 0);
UML_MOV(block, REG(rn), I0);
-
+
UML_LABEL(block, end);
return;
}
- case 0xe1: // Fn = MIN(Fx, Fy)
+ case 0xe1: // Fn = MIN(Fx, Fy)
UML_FSCOPYI(block, F2, REG(rx));
UML_FSCOPYI(block, F3, REG(ry));
UML_FSMOV(block, F4, F2);
@@ -4625,14 +4625,14 @@ void adsp21062_device::generate_compute(drcuml_block *block, compiler_state *com
UML_FSCMP(block, F4, mem(&m_core->fp0));
if (AZ_CALC_REQUIRED) UML_SETc(block, COND_Z, ASTAT_AZ);
if (AN_CALC_REQUIRED) UML_SETc(block, COND_C, ASTAT_AN);
- if (AV_CALC_REQUIRED) UML_MOV(block, ASTAT_AV, 0); // TODO
+ if (AV_CALC_REQUIRED) UML_MOV(block, ASTAT_AV, 0); // TODO
if (AC_CALC_REQUIRED) UML_MOV(block, ASTAT_AC, 0);
if (AS_CALC_REQUIRED) UML_MOV(block, ASTAT_AS, 0);
- if (AI_CALC_REQUIRED) UML_MOV(block, ASTAT_AI, 0); // TODO
+ if (AI_CALC_REQUIRED) UML_MOV(block, ASTAT_AI, 0); // TODO
UML_ICOPYFS(block, REG(rn), F4);
return;
- case 0xe2: // Fn = MAX(Fx, Fy)
+ case 0xe2: // Fn = MAX(Fx, Fy)
UML_FSCOPYI(block, F2, REG(rx));
UML_FSCOPYI(block, F3, REG(ry));
UML_FSMOV(block, F4, F2);
@@ -4643,14 +4643,14 @@ void adsp21062_device::generate_compute(drcuml_block *block, compiler_state *com
UML_FSCMP(block, F4, mem(&m_core->fp0));
if (AZ_CALC_REQUIRED) UML_SETc(block, COND_Z, ASTAT_AZ);
if (AN_CALC_REQUIRED) UML_SETc(block, COND_C, ASTAT_AN);
- if (AV_CALC_REQUIRED) UML_MOV(block, ASTAT_AV, 0); // TODO
+ if (AV_CALC_REQUIRED) UML_MOV(block, ASTAT_AV, 0); // TODO
if (AC_CALC_REQUIRED) UML_MOV(block, ASTAT_AC, 0);
if (AS_CALC_REQUIRED) UML_MOV(block, ASTAT_AS, 0);
- if (AI_CALC_REQUIRED) UML_MOV(block, ASTAT_AI, 0); // TODO
+ if (AI_CALC_REQUIRED) UML_MOV(block, ASTAT_AI, 0); // TODO
UML_ICOPYFS(block, REG(rn), F4);
return;
- case 0xe3: // Fn = CLIP Fx BY Fy
+ case 0xe3: // Fn = CLIP Fx BY Fy
{
code_label label_1 = compiler->labelnum++;
code_label label_2 = compiler->labelnum++;
@@ -4675,7 +4675,7 @@ void adsp21062_device::generate_compute(drcuml_block *block, compiler_state *com
if (AV_CALC_REQUIRED) UML_MOV(block, ASTAT_AV, 0);
if (AC_CALC_REQUIRED) UML_MOV(block, ASTAT_AC, 0);
if (AS_CALC_REQUIRED) UML_MOV(block, ASTAT_AS, 0);
- if (AI_CALC_REQUIRED) UML_MOV(block, ASTAT_AI, 0); // TODO
+ if (AI_CALC_REQUIRED) UML_MOV(block, ASTAT_AI, 0); // TODO
UML_ICOPYFS(block, REG(rn), F0);
return;
}
@@ -4698,10 +4698,10 @@ void adsp21062_device::generate_compute(drcuml_block *block, compiler_state *com
if (AN_CALC_REQUIRED) UML_SETc(block, COND_C, I1);
if (AZ_CALC_REQUIRED) UML_OR(block, ASTAT_AZ, ASTAT_AZ, I0);
if (AN_CALC_REQUIRED) UML_OR(block, ASTAT_AN, ASTAT_AN, I1);
- if (AV_CALC_REQUIRED) UML_MOV(block, ASTAT_AV, 0); // TODO
+ if (AV_CALC_REQUIRED) UML_MOV(block, ASTAT_AV, 0); // TODO
if (AC_CALC_REQUIRED) UML_MOV(block, ASTAT_AC, 0);
if (AS_CALC_REQUIRED) UML_MOV(block, ASTAT_AS, 0);
- if (AI_CALC_REQUIRED) UML_MOV(block, ASTAT_AI, 0); // TODO
+ if (AI_CALC_REQUIRED) UML_MOV(block, ASTAT_AI, 0); // TODO
UML_ICOPYFS(block, REG(ra), F2);
UML_ICOPYFS(block, REG(rs), F3);
return;
@@ -4714,166 +4714,166 @@ void adsp21062_device::generate_compute(drcuml_block *block, compiler_state *com
break;
}
- case 1: // multiplier operations
+ case 1: // multiplier operations
{
switch (operation)
{
- case 0x48: // Rn = Rx * Ry (UUF)
- case 0x49: // Rn = Rx * Ry (UUFR)
- case 0x50: // Rn = Rx * Ry (SUI)
- case 0x58: // Rn = Rx * Ry (SUF)
- case 0x59: // Rn = Rx * Ry (SUFR)
- case 0x60: // Rn = Rx * Ry (USI)
- case 0x68: // Rn = Rx * Ry (USF)
- case 0x69: // Rn = Rx * Ry (USFR)
- case 0x78: // Rn = Rx * Ry (SSF)
- case 0x79: // Rn = Rx * Ry (SSFR)
- case 0x44: // MRF = Rx * Ry (UUI)
- case 0x4c: // MRF = Rx * Ry (UUF)
- case 0x4d: // MRF = Rx * Ry (UUFR)
- case 0x54: // MRF = Rx * Ry (SUI)
- case 0x5c: // MRF = Rx * Ry (SUF)
- case 0x5d: // MRF = Rx * Ry (SUFR)
- case 0x64: // MRF = Rx * Ry (USI)
- case 0x6c: // MRF = Rx * Ry (USF)
- case 0x6d: // MRF = Rx * Ry (USFR)
- case 0x74: // MRF = Rx * Ry (SSI)
- case 0x7c: // MRF = Rx * Ry (SSF)
- case 0x7d: // MRF = Rx * Ry (SSFR)
- case 0x46: // MRB = Rx * Ry (UUI)
- case 0x4e: // MRB = Rx * Ry (UUF)
- case 0x4f: // MRB = Rx * Ry (UUFR)
- case 0x56: // MRB = Rx * Ry (SUI)
- case 0x5e: // MRB = Rx * Ry (SUF)
- case 0x5f: // MRB = Rx * Ry (SUFR)
- case 0x66: // MRB = Rx * Ry (USI)
- case 0x6e: // MRB = Rx * Ry (USF)
- case 0x6f: // MRB = Rx * Ry (USFR)
- case 0x76: // MRB = Rx * Ry (SSI)
- case 0x7e: // MRB = Rx * Ry (SSF)
- case 0x7f: // MRB = Rx * Ry (SSFR)
- case 0x80: // Rn = MRF + Rx * Ry (UUI)
- case 0x88: // Rn = MRF + Rx * Ry (UUF)
- case 0x89: // Rn = MRF + Rx * Ry (UUFR)
- case 0x90: // Rn = MRF + Rx * Ry (SUI)
- case 0x98: // Rn = MRF + Rx * Ry (SUF)
- case 0x99: // Rn = MRF + Rx * Ry (SUFR)
- case 0xa0: // Rn = MRF + Rx * Ry (USI)
- case 0xa8: // Rn = MRF + Rx * Ry (USF)
- case 0xa9: // Rn = MRF + Rx * Ry (USFR)
- case 0xb8: // Rn = MRF + Rx * Ry (SSF)
- case 0xb9: // Rn = MRF + Rx * Ry (SSFR)
- case 0x82: // Rn = MRB + Rx * Ry (UUI)
- case 0x8a: // Rn = MRB + Rx * Ry (UUF)
- case 0x8b: // Rn = MRB + Rx * Ry (UUFR)
- case 0x92: // Rn = MRB + Rx * Ry (SUI)
- case 0x9a: // Rn = MRB + Rx * Ry (SUF)
- case 0x9b: // Rn = MRB + Rx * Ry (SUFR)
- case 0xa2: // Rn = MRB + Rx * Ry (USI)
- case 0xaa: // Rn = MRB + Rx * Ry (USF)
- case 0xab: // Rn = MRB + Rx * Ry (USFR)
- case 0xba: // Rn = MRB + Rx * Ry (SSF)
- case 0xbb: // Rn = MRB + Rx * Ry (SSFR)
- case 0x84: // MRF = MRF + Rx * Ry (UUI)
- case 0x8c: // MRF = MRF + Rx * Ry (UUF)
- case 0x8d: // MRF = MRF + Rx * Ry (UUFR)
- case 0x94: // MRF = MRF + Rx * Ry (SUI)
- case 0x9c: // MRF = MRF + Rx * Ry (SUF)
- case 0x9d: // MRF = MRF + Rx * Ry (SUFR)
- case 0xa4: // MRF = MRF + Rx * Ry (USI)
- case 0xac: // MRF = MRF + Rx * Ry (USF)
- case 0xad: // MRF = MRF + Rx * Ry (USFR)
- case 0xb4: // MRF = MRF + Rx * Ry (SSI)
- case 0xbc: // MRF = MRF + Rx * Ry (SSF)
- case 0xbd: // MRF = MRF + Rx * Ry (SSFR)
- case 0x86: // MRB = MRB + Rx * Ry (UUI)
- case 0x8e: // MRB = MRB + Rx * Ry (UUF)
- case 0x8f: // MRB = MRB + Rx * Ry (UUFR)
- case 0x96: // MRB = MRB + Rx * Ry (SUI)
- case 0x9e: // MRB = MRB + Rx * Ry (SUF)
- case 0x9f: // MRB = MRB + Rx * Ry (SUFR)
- case 0xa6: // MRB = MRB + Rx * Ry (USI)
- case 0xae: // MRB = MRB + Rx * Ry (USF)
- case 0xaf: // MRB = MRB + Rx * Ry (USFR)
- case 0xb6: // MRB = MRB + Rx * Ry (SSI)
- case 0xbe: // MRB = MRB + Rx * Ry (SSF)
- case 0xbf: // MRB = MRB + Rx * Ry (SSFR)
- case 0xc0: // Rn = MRF - Rx * Ry (UUI)
- case 0xc8: // Rn = MRF - Rx * Ry (UUF)
- case 0xc9: // Rn = MRF - Rx * Ry (UUFR)
- case 0xd0: // Rn = MRF - Rx * Ry (SUI)
- case 0xd8: // Rn = MRF - Rx * Ry (SUF)
- case 0xd9: // Rn = MRF - Rx * Ry (SUFR)
- case 0xe0: // Rn = MRF - Rx * Ry (USI)
- case 0xe8: // Rn = MRF - Rx * Ry (USF)
- case 0xe9: // Rn = MRF - Rx * Ry (USFR)
- case 0xf0: // Rn = MRF - Rx * Ry (SSI)
- case 0xf8: // Rn = MRF - Rx * Ry (SSF)
- case 0xf9: // Rn = MRF - Rx * Ry (SSFR)
- case 0xc2: // Rn = MRB - Rx * Ry (UUI)
- case 0xca: // Rn = MRB - Rx * Ry (UUF)
- case 0xcb: // Rn = MRB - Rx * Ry (UUFR)
- case 0xd2: // Rn = MRB - Rx * Ry (SUI)
- case 0xda: // Rn = MRB - Rx * Ry (SUF)
- case 0xdb: // Rn = MRB - Rx * Ry (SUFR)
- case 0xe2: // Rn = MRB - Rx * Ry (USI)
- case 0xea: // Rn = MRB - Rx * Ry (USF)
- case 0xeb: // Rn = MRB - Rx * Ry (USFR)
- case 0xf2: // Rn = MRB - Rx * Ry (SSI)
- case 0xfa: // Rn = MRB - Rx * Ry (SSF)
- case 0xfb: // Rn = MRB - Rx * Ry (SSFR)
- case 0xc4: // MRF = MRF - Rx * Ry (UUI)
- case 0xcc: // MRF = MRF - Rx * Ry (UUF)
- case 0xcd: // MRF = MRF - Rx * Ry (UUFR)
- case 0xd4: // MRF = MRF - Rx * Ry (SUI)
- case 0xdc: // MRF = MRF - Rx * Ry (SUF)
- case 0xdd: // MRF = MRF - Rx * Ry (SUFR)
- case 0xe4: // MRF = MRF - Rx * Ry (USI)
- case 0xec: // MRF = MRF - Rx * Ry (USF)
- case 0xed: // MRF = MRF - Rx * Ry (USFR)
- case 0xf4: // MRF = MRF - Rx * Ry (SSI)
- case 0xfc: // MRF = MRF - Rx * Ry (SSF)
- case 0xfd: // MRF = MRF - Rx * Ry (SSFR)
- case 0xc6: // MRB = MRB - Rx * Ry (UUI)
- case 0xce: // MRB = MRB - Rx * Ry (UUF)
- case 0xcf: // MRB = MRB - Rx * Ry (UUFR)
- case 0xd6: // MRB = MRB - Rx * Ry (SUI)
- case 0xde: // MRB = MRB - Rx * Ry (SUF)
- case 0xdf: // MRB = MRB - Rx * Ry (SUFR)
- case 0xe6: // MRB = MRB - Rx * Ry (USI)
- case 0xee: // MRB = MRB - Rx * Ry (USF)
- case 0xef: // MRB = MRB - Rx * Ry (USFR)
- case 0xf6: // MRB = MRB - Rx * Ry (SSI)
- case 0xfe: // MRB = MRB - Rx * Ry (SSF)
- case 0xff: // MRB = MRB - Rx * Ry (SSFR)
- case 0x00: // Rn = SAT MRF (UI)
- case 0x01: // Rn = SAT MRF (SI)
- case 0x08: // Rn = SAT MRF (UF)
- case 0x09: // Rn = SAT MRF (SF)
- case 0x02: // Rn = SAT MRB (UI)
- case 0x03: // Rn = SAT MRB (SI)
- case 0x0a: // Rn = SAT MRB (UF)
- case 0x0b: // Rn = SAT MRB (SF)
- case 0x04: // MRF = SAT MRF (UI)
- case 0x05: // MRF = SAT MRF (SI)
- case 0x0c: // MRF = SAT MRF (UF)
- case 0x0d: // MRF = SAT MRF (SF)
- case 0x06: // MRB = SAT MRB (UI)
- case 0x07: // MRB = SAT MRB (SI)
- case 0x0e: // MRB = SAT MRB (UF)
- case 0x0f: // MRB = SAT MRB (SF)
- case 0x18: // Rn = RND MRF (U)
- case 0x19: // Rn = RND MRF (S)
- case 0x1a: // Rn = RND MRB (U)
- case 0x1b: // Rn = RND MRB (S)
- case 0x1c: // MRF = RND MRF (U)
- case 0x1d: // MRF = RND MRF (S)
- case 0x1e: // MRB = RND MRB (U)
- case 0x1f: // MRB = RND MRB (S)
+ case 0x48: // Rn = Rx * Ry (UUF)
+ case 0x49: // Rn = Rx * Ry (UUFR)
+ case 0x50: // Rn = Rx * Ry (SUI)
+ case 0x58: // Rn = Rx * Ry (SUF)
+ case 0x59: // Rn = Rx * Ry (SUFR)
+ case 0x60: // Rn = Rx * Ry (USI)
+ case 0x68: // Rn = Rx * Ry (USF)
+ case 0x69: // Rn = Rx * Ry (USFR)
+ case 0x78: // Rn = Rx * Ry (SSF)
+ case 0x79: // Rn = Rx * Ry (SSFR)
+ case 0x44: // MRF = Rx * Ry (UUI)
+ case 0x4c: // MRF = Rx * Ry (UUF)
+ case 0x4d: // MRF = Rx * Ry (UUFR)
+ case 0x54: // MRF = Rx * Ry (SUI)
+ case 0x5c: // MRF = Rx * Ry (SUF)
+ case 0x5d: // MRF = Rx * Ry (SUFR)
+ case 0x64: // MRF = Rx * Ry (USI)
+ case 0x6c: // MRF = Rx * Ry (USF)
+ case 0x6d: // MRF = Rx * Ry (USFR)
+ case 0x74: // MRF = Rx * Ry (SSI)
+ case 0x7c: // MRF = Rx * Ry (SSF)
+ case 0x7d: // MRF = Rx * Ry (SSFR)
+ case 0x46: // MRB = Rx * Ry (UUI)
+ case 0x4e: // MRB = Rx * Ry (UUF)
+ case 0x4f: // MRB = Rx * Ry (UUFR)
+ case 0x56: // MRB = Rx * Ry (SUI)
+ case 0x5e: // MRB = Rx * Ry (SUF)
+ case 0x5f: // MRB = Rx * Ry (SUFR)
+ case 0x66: // MRB = Rx * Ry (USI)
+ case 0x6e: // MRB = Rx * Ry (USF)
+ case 0x6f: // MRB = Rx * Ry (USFR)
+ case 0x76: // MRB = Rx * Ry (SSI)
+ case 0x7e: // MRB = Rx * Ry (SSF)
+ case 0x7f: // MRB = Rx * Ry (SSFR)
+ case 0x80: // Rn = MRF + Rx * Ry (UUI)
+ case 0x88: // Rn = MRF + Rx * Ry (UUF)
+ case 0x89: // Rn = MRF + Rx * Ry (UUFR)
+ case 0x90: // Rn = MRF + Rx * Ry (SUI)
+ case 0x98: // Rn = MRF + Rx * Ry (SUF)
+ case 0x99: // Rn = MRF + Rx * Ry (SUFR)
+ case 0xa0: // Rn = MRF + Rx * Ry (USI)
+ case 0xa8: // Rn = MRF + Rx * Ry (USF)
+ case 0xa9: // Rn = MRF + Rx * Ry (USFR)
+ case 0xb8: // Rn = MRF + Rx * Ry (SSF)
+ case 0xb9: // Rn = MRF + Rx * Ry (SSFR)
+ case 0x82: // Rn = MRB + Rx * Ry (UUI)
+ case 0x8a: // Rn = MRB + Rx * Ry (UUF)
+ case 0x8b: // Rn = MRB + Rx * Ry (UUFR)
+ case 0x92: // Rn = MRB + Rx * Ry (SUI)
+ case 0x9a: // Rn = MRB + Rx * Ry (SUF)
+ case 0x9b: // Rn = MRB + Rx * Ry (SUFR)
+ case 0xa2: // Rn = MRB + Rx * Ry (USI)
+ case 0xaa: // Rn = MRB + Rx * Ry (USF)
+ case 0xab: // Rn = MRB + Rx * Ry (USFR)
+ case 0xba: // Rn = MRB + Rx * Ry (SSF)
+ case 0xbb: // Rn = MRB + Rx * Ry (SSFR)
+ case 0x84: // MRF = MRF + Rx * Ry (UUI)
+ case 0x8c: // MRF = MRF + Rx * Ry (UUF)
+ case 0x8d: // MRF = MRF + Rx * Ry (UUFR)
+ case 0x94: // MRF = MRF + Rx * Ry (SUI)
+ case 0x9c: // MRF = MRF + Rx * Ry (SUF)
+ case 0x9d: // MRF = MRF + Rx * Ry (SUFR)
+ case 0xa4: // MRF = MRF + Rx * Ry (USI)
+ case 0xac: // MRF = MRF + Rx * Ry (USF)
+ case 0xad: // MRF = MRF + Rx * Ry (USFR)
+ case 0xb4: // MRF = MRF + Rx * Ry (SSI)
+ case 0xbc: // MRF = MRF + Rx * Ry (SSF)
+ case 0xbd: // MRF = MRF + Rx * Ry (SSFR)
+ case 0x86: // MRB = MRB + Rx * Ry (UUI)
+ case 0x8e: // MRB = MRB + Rx * Ry (UUF)
+ case 0x8f: // MRB = MRB + Rx * Ry (UUFR)
+ case 0x96: // MRB = MRB + Rx * Ry (SUI)
+ case 0x9e: // MRB = MRB + Rx * Ry (SUF)
+ case 0x9f: // MRB = MRB + Rx * Ry (SUFR)
+ case 0xa6: // MRB = MRB + Rx * Ry (USI)
+ case 0xae: // MRB = MRB + Rx * Ry (USF)
+ case 0xaf: // MRB = MRB + Rx * Ry (USFR)
+ case 0xb6: // MRB = MRB + Rx * Ry (SSI)
+ case 0xbe: // MRB = MRB + Rx * Ry (SSF)
+ case 0xbf: // MRB = MRB + Rx * Ry (SSFR)
+ case 0xc0: // Rn = MRF - Rx * Ry (UUI)
+ case 0xc8: // Rn = MRF - Rx * Ry (UUF)
+ case 0xc9: // Rn = MRF - Rx * Ry (UUFR)
+ case 0xd0: // Rn = MRF - Rx * Ry (SUI)
+ case 0xd8: // Rn = MRF - Rx * Ry (SUF)
+ case 0xd9: // Rn = MRF - Rx * Ry (SUFR)
+ case 0xe0: // Rn = MRF - Rx * Ry (USI)
+ case 0xe8: // Rn = MRF - Rx * Ry (USF)
+ case 0xe9: // Rn = MRF - Rx * Ry (USFR)
+ case 0xf0: // Rn = MRF - Rx * Ry (SSI)
+ case 0xf8: // Rn = MRF - Rx * Ry (SSF)
+ case 0xf9: // Rn = MRF - Rx * Ry (SSFR)
+ case 0xc2: // Rn = MRB - Rx * Ry (UUI)
+ case 0xca: // Rn = MRB - Rx * Ry (UUF)
+ case 0xcb: // Rn = MRB - Rx * Ry (UUFR)
+ case 0xd2: // Rn = MRB - Rx * Ry (SUI)
+ case 0xda: // Rn = MRB - Rx * Ry (SUF)
+ case 0xdb: // Rn = MRB - Rx * Ry (SUFR)
+ case 0xe2: // Rn = MRB - Rx * Ry (USI)
+ case 0xea: // Rn = MRB - Rx * Ry (USF)
+ case 0xeb: // Rn = MRB - Rx * Ry (USFR)
+ case 0xf2: // Rn = MRB - Rx * Ry (SSI)
+ case 0xfa: // Rn = MRB - Rx * Ry (SSF)
+ case 0xfb: // Rn = MRB - Rx * Ry (SSFR)
+ case 0xc4: // MRF = MRF - Rx * Ry (UUI)
+ case 0xcc: // MRF = MRF - Rx * Ry (UUF)
+ case 0xcd: // MRF = MRF - Rx * Ry (UUFR)
+ case 0xd4: // MRF = MRF - Rx * Ry (SUI)
+ case 0xdc: // MRF = MRF - Rx * Ry (SUF)
+ case 0xdd: // MRF = MRF - Rx * Ry (SUFR)
+ case 0xe4: // MRF = MRF - Rx * Ry (USI)
+ case 0xec: // MRF = MRF - Rx * Ry (USF)
+ case 0xed: // MRF = MRF - Rx * Ry (USFR)
+ case 0xf4: // MRF = MRF - Rx * Ry (SSI)
+ case 0xfc: // MRF = MRF - Rx * Ry (SSF)
+ case 0xfd: // MRF = MRF - Rx * Ry (SSFR)
+ case 0xc6: // MRB = MRB - Rx * Ry (UUI)
+ case 0xce: // MRB = MRB - Rx * Ry (UUF)
+ case 0xcf: // MRB = MRB - Rx * Ry (UUFR)
+ case 0xd6: // MRB = MRB - Rx * Ry (SUI)
+ case 0xde: // MRB = MRB - Rx * Ry (SUF)
+ case 0xdf: // MRB = MRB - Rx * Ry (SUFR)
+ case 0xe6: // MRB = MRB - Rx * Ry (USI)
+ case 0xee: // MRB = MRB - Rx * Ry (USF)
+ case 0xef: // MRB = MRB - Rx * Ry (USFR)
+ case 0xf6: // MRB = MRB - Rx * Ry (SSI)
+ case 0xfe: // MRB = MRB - Rx * Ry (SSF)
+ case 0xff: // MRB = MRB - Rx * Ry (SSFR)
+ case 0x00: // Rn = SAT MRF (UI)
+ case 0x01: // Rn = SAT MRF (SI)
+ case 0x08: // Rn = SAT MRF (UF)
+ case 0x09: // Rn = SAT MRF (SF)
+ case 0x02: // Rn = SAT MRB (UI)
+ case 0x03: // Rn = SAT MRB (SI)
+ case 0x0a: // Rn = SAT MRB (UF)
+ case 0x0b: // Rn = SAT MRB (SF)
+ case 0x04: // MRF = SAT MRF (UI)
+ case 0x05: // MRF = SAT MRF (SI)
+ case 0x0c: // MRF = SAT MRF (UF)
+ case 0x0d: // MRF = SAT MRF (SF)
+ case 0x06: // MRB = SAT MRB (UI)
+ case 0x07: // MRB = SAT MRB (SI)
+ case 0x0e: // MRB = SAT MRB (UF)
+ case 0x0f: // MRB = SAT MRB (SF)
+ case 0x18: // Rn = RND MRF (U)
+ case 0x19: // Rn = RND MRF (S)
+ case 0x1a: // Rn = RND MRB (U)
+ case 0x1b: // Rn = RND MRB (S)
+ case 0x1c: // MRF = RND MRF (U)
+ case 0x1d: // MRF = RND MRF (S)
+ case 0x1e: // MRB = RND MRB (U)
+ case 0x1f: // MRB = RND MRB (S)
generate_unimplemented_compute(block, compiler, desc);
return;
- case 0x14: // MRF = 0
+ case 0x14: // MRF = 0
UML_DMOV(block, mem(&m_core->mrf), 0);
if (MN_CALC_REQUIRED) UML_MOV(block, ASTAT_MN, 0);
if (MV_CALC_REQUIRED) UML_MOV(block, ASTAT_MV, 0);
@@ -4881,7 +4881,7 @@ void adsp21062_device::generate_compute(drcuml_block *block, compiler_state *com
if (MI_CALC_REQUIRED) UML_MOV(block, ASTAT_MI, 0);
return;
- case 0x16: // MRB = 0
+ case 0x16: // MRB = 0
UML_DMOV(block, mem(&m_core->mrb), 0);
if (MN_CALC_REQUIRED) UML_MOV(block, ASTAT_MN, 0);
if (MV_CALC_REQUIRED) UML_MOV(block, ASTAT_MV, 0);
@@ -4889,7 +4889,7 @@ void adsp21062_device::generate_compute(drcuml_block *block, compiler_state *com
if (MI_CALC_REQUIRED) UML_MOV(block, ASTAT_MI, 0);
return;
- case 0x30: // Fn = Fx * Fy
+ case 0x30: // Fn = Fx * Fy
UML_FSCOPYI(block, F0, REG(rx));
UML_FSCOPYI(block, F1, REG(ry));
UML_FSMUL(block, F0, F0, F1);
@@ -4900,19 +4900,19 @@ void adsp21062_device::generate_compute(drcuml_block *block, compiler_state *com
// TODO: MV, MU, MI flags
return;
- case 0x40: // Rn = Rx * Ry (UUI)
+ case 0x40: // Rn = Rx * Ry (UUI)
UML_MULU(block, I0, I0, REG(rx), REG(ry));
UML_MOV(block, REG(rn), I0);
// TODO: flags
return;
- case 0x70: // Rn = Rx * Ry (SSI)
+ case 0x70: // Rn = Rx * Ry (SSI)
UML_MULS(block, I0, I0, REG(rx), REG(ry));
UML_MOV(block, REG(rn), I0);
// TODO: flags
return;
- case 0xb0: // Rn = MRF + Rx * Ry (SSI)
+ case 0xb0: // Rn = MRF + Rx * Ry (SSI)
UML_DSEXT(block, I0, REG(rx), SIZE_DWORD);
UML_DSEXT(block, I1, REG(ry), SIZE_DWORD);
UML_DMULS(block, I0, I0, I0, I1);
@@ -4921,7 +4921,7 @@ void adsp21062_device::generate_compute(drcuml_block *block, compiler_state *com
// TODO: flags!
return;
- case 0xb2: // Rn = MRB + Rx * Ry (SSI)
+ case 0xb2: // Rn = MRB + Rx * Ry (SSI)
UML_DSEXT(block, I0, REG(rx), SIZE_DWORD);
UML_DSEXT(block, I1, REG(ry), SIZE_DWORD);
UML_DMULS(block, I0, I0, I0, I1);
@@ -4937,25 +4937,25 @@ void adsp21062_device::generate_compute(drcuml_block *block, compiler_state *com
break;
}
- case 2: // shifter operations
+ case 2: // shifter operations
{
switch (operation)
{
- case 0x04: // Rn = ASHIFT Rx BY Ry | <data8>
- case 0x44: // Rn = FDEP Rx BY Ry | <bit6>:<len6>
- case 0x4c: // Rn = FDEP Rx BY Ry | <bit6>:<len6> (SE)
- case 0x24: // Rn = Rn OR ASHIFT Rx BY Ry | <data8>
- case 0x6c: // Rn = Rn OR FDEP Rx BY Ry | <bit6>:<len6> (SE)
- case 0x80: // Rn = EXP Rx
- case 0x84: // Rn = EXP Rx (EX)
- case 0x88: // Rn = LEFTZ Rx
- case 0x8c: // Rn = LEFTO Rx
- case 0x90: // Rn = FPACK Fx
- case 0x94: // Fn = FUNPACK Rx
+ case 0x04: // Rn = ASHIFT Rx BY Ry | <data8>
+ case 0x44: // Rn = FDEP Rx BY Ry | <bit6>:<len6>
+ case 0x4c: // Rn = FDEP Rx BY Ry | <bit6>:<len6> (SE)
+ case 0x24: // Rn = Rn OR ASHIFT Rx BY Ry | <data8>
+ case 0x6c: // Rn = Rn OR FDEP Rx BY Ry | <bit6>:<len6> (SE)
+ case 0x80: // Rn = EXP Rx
+ case 0x84: // Rn = EXP Rx (EX)
+ case 0x88: // Rn = LEFTZ Rx
+ case 0x8c: // Rn = LEFTO Rx
+ case 0x90: // Rn = FPACK Fx
+ case 0x94: // Fn = FUNPACK Rx
generate_unimplemented_compute(block, compiler, desc);
return;
- case 0x00: // Rn = LSHIFT Rx BY Ry | <data8>
+ case 0x00: // Rn = LSHIFT Rx BY Ry | <data8>
{
code_label shift_neg = compiler->labelnum++;
code_label shift_end = compiler->labelnum++;
@@ -4980,7 +4980,7 @@ void adsp21062_device::generate_compute(drcuml_block *block, compiler_state *com
return;
}
- case 0x08: // Rn = ROT Rx BY Ry | <data8>
+ case 0x08: // Rn = ROT Rx BY Ry | <data8>
{
code_label shift_neg = compiler->labelnum++;
code_label shift_end = compiler->labelnum++;
@@ -5001,7 +5001,7 @@ void adsp21062_device::generate_compute(drcuml_block *block, compiler_state *com
return;
}
- case 0x20: // Rn = Rn OR LSHIFT Rx BY Ry | <data8>
+ case 0x20: // Rn = Rn OR LSHIFT Rx BY Ry | <data8>
{
code_label shift_neg = compiler->labelnum++;
code_label shift_end = compiler->labelnum++;
@@ -5027,12 +5027,12 @@ void adsp21062_device::generate_compute(drcuml_block *block, compiler_state *com
return;
}
- case 0x40: // Rn = FEXT Rx BY Ry | <bit6>:<len6>
+ case 0x40: // Rn = FEXT Rx BY Ry | <bit6>:<len6>
// extraction mask
UML_MOV(block, I0, REG(ry));
UML_SHR(block, I1, I0, 6);
- UML_AND(block, I1, I1, 0x3f); // i1 = len6
- UML_AND(block, I0, I0, 0x3f); // i0 = bit6
+ UML_AND(block, I1, I1, 0x3f); // i1 = len6
+ UML_AND(block, I0, I0, 0x3f); // i0 = bit6
UML_MOV(block, I3, 0xffffffff);
UML_SUB(block, I2, 32, I1);
UML_SHR(block, I3, I3, I2);
@@ -5050,12 +5050,12 @@ void adsp21062_device::generate_compute(drcuml_block *block, compiler_state *com
if (SS_CALC_REQUIRED) UML_MOV(block, ASTAT_SS, 0);
return;
- case 0x48: // Rn = FEXT Rx BY Ry | <bit6>:<len6> (SE)
+ case 0x48: // Rn = FEXT Rx BY Ry | <bit6>:<len6> (SE)
// extraction mask
UML_MOV(block, I0, REG(ry));
UML_SHR(block, I1, I0, 6);
- UML_AND(block, I1, I1, 0x3f); // i1 = len6
- UML_AND(block, I0, I0, 0x3f); // i0 = bit6
+ UML_AND(block, I1, I1, 0x3f); // i1 = len6
+ UML_AND(block, I0, I0, 0x3f); // i0 = bit6
UML_MOV(block, I3, 0xffffffff);
UML_SUB(block, I2, 32, I1);
UML_SHR(block, I3, I3, I2);
@@ -5079,12 +5079,12 @@ void adsp21062_device::generate_compute(drcuml_block *block, compiler_state *com
if (SS_CALC_REQUIRED) UML_MOV(block, ASTAT_SS, 0);
return;
- case 0x64: // Rn = Rn OR FDEP Rx BY Ry | <bit6>:<len6>
+ case 0x64: // Rn = Rn OR FDEP Rx BY Ry | <bit6>:<len6>
// extraction mask
UML_MOV(block, I0, REG(ry));
UML_SHR(block, I1, I0, 6);
- UML_AND(block, I1, I1, 0x3f); // i1 = len6
- UML_AND(block, I0, I0, 0x3f); // i0 = bit6
+ UML_AND(block, I1, I1, 0x3f); // i1 = len6
+ UML_AND(block, I0, I0, 0x3f); // i0 = bit6
UML_MOV(block, I3, 0xffffffff);
UML_SUB(block, I2, 32, I1);
UML_SHR(block, I3, I3, I2);
@@ -5102,7 +5102,7 @@ void adsp21062_device::generate_compute(drcuml_block *block, compiler_state *com
if (SS_CALC_REQUIRED) UML_MOV(block, ASTAT_SS, 0);
return;
- case 0xc0: // Rn = BSET Rx BY Ry | <data8>
+ case 0xc0: // Rn = BSET Rx BY Ry | <data8>
{
UML_MOV(block, I0, REG(ry));
UML_SHL(block, I1, 1, I0);
@@ -5117,7 +5117,7 @@ void adsp21062_device::generate_compute(drcuml_block *block, compiler_state *com
return;
}
- case 0xc4: // Rn = BCLR Rx BY Ry | <data8>
+ case 0xc4: // Rn = BCLR Rx BY Ry | <data8>
{
UML_MOV(block, I0, REG(ry));
UML_SHL(block, I1, 1, I0);
@@ -5133,14 +5133,14 @@ void adsp21062_device::generate_compute(drcuml_block *block, compiler_state *com
return;
}
- case 0xcc: // BTST Rx BY Ry | <data8>
+ case 0xcc: // BTST Rx BY Ry | <data8>
{
UML_MOV(block, I0, REG(ry));
UML_SHL(block, I1, 1, I0);
UML_TEST(block, REG(rx), I1);
if (SZ_CALC_REQUIRED) UML_SETc(block, COND_Z, ASTAT_SZ);
- if (SV_CALC_REQUIRED)
- UML_CMP(block, I0, 31);
+ if (SV_CALC_REQUIRED)
+ UML_CMP(block, I0, 31);
if (SV_CALC_REQUIRED) UML_SETc(block, COND_G, ASTAT_SV);
if (SS_CALC_REQUIRED) UML_MOV(block, ASTAT_SS, 0);
return;
@@ -5383,7 +5383,7 @@ void adsp21062_device::generate_do_condition(drcuml_block *block, compiler_state
// infinite loop
break;
case 0x0f: /* LCE */
- fatalerror("generate_do_condition 0x0f"); // this should only be used with counter loops
+ fatalerror("generate_do_condition 0x0f"); // this should only be used with counter loops
break;
case 0x10: /* NOT EQUAL */
UML_TEST(block, mem(&m_core->astat_delay_copy.az), 1);
@@ -5465,16 +5465,16 @@ void adsp21062_device::generate_shift_imm(drcuml_block *block, compiler_state *c
int len = (data >> 6) & 0x3f;
switch (shiftop)
- {
- case 0x11: // FDEP Rx BY <bit6>:<len6>
- case 0x13: // FDEP Rx BY <bit6>:<len6> (SE)
- case 0x1b: // Rn = Rn OR FDEP Rx BY <bit6>:<len6> (SE)
+ {
+ case 0x11: // FDEP Rx BY <bit6>:<len6>
+ case 0x13: // FDEP Rx BY <bit6>:<len6> (SE)
+ case 0x1b: // Rn = Rn OR FDEP Rx BY <bit6>:<len6> (SE)
UML_MOV(block, mem(&m_core->pc), desc->pc);
UML_DMOV(block, mem(&m_core->arg64), desc->opptr.q[0]);
UML_CALLC(block, cfunc_unimplemented_shiftimm, this);
break;
- case 0x00: // LSHIFT Rx BY <data8>
+ case 0x00: // LSHIFT Rx BY <data8>
if (abs(shift) >= 32)
{
UML_MOV(block, REG(rn), 0);
@@ -5495,7 +5495,7 @@ void adsp21062_device::generate_shift_imm(drcuml_block *block, compiler_state *c
}
return;
- case 0x01: // ASHIFT Rx BY <data8>
+ case 0x01: // ASHIFT Rx BY <data8>
if (abs(shift) >= 32)
{
UML_MOV(block, REG(rn), 0);
@@ -5518,7 +5518,7 @@ void adsp21062_device::generate_shift_imm(drcuml_block *block, compiler_state *c
}
return;
- case 0x02: // ROT Rx BY <data8>
+ case 0x02: // ROT Rx BY <data8>
if (shift < 0)
UML_ROR(block, REG(rn), REG(rx), (-shift) & 0x1f);
else
@@ -5528,7 +5528,7 @@ void adsp21062_device::generate_shift_imm(drcuml_block *block, compiler_state *c
if (SS_CALC_REQUIRED) UML_MOV(block, ASTAT_SS, 0);
return;
- case 0x08: // Rn = Rn OR LSHIFT Rx BY <data8>
+ case 0x08: // Rn = Rn OR LSHIFT Rx BY <data8>
if (abs(shift) >= 32)
{
UML_MOV(block, I0, 0);
@@ -5551,7 +5551,7 @@ void adsp21062_device::generate_shift_imm(drcuml_block *block, compiler_state *c
}
return;
- case 0x10: // FEXT Rx BY <bit6>:<len6>
+ case 0x10: // FEXT Rx BY <bit6>:<len6>
if (bit == 0)
{
UML_AND(block, REG(rn), REG(rx), MAKE_EXTRACT_MASK(bit, len));
@@ -5567,7 +5567,7 @@ void adsp21062_device::generate_shift_imm(drcuml_block *block, compiler_state *c
if (SS_CALC_REQUIRED) UML_MOV(block, ASTAT_SS, 0);
return;
- case 0x12: // FEXT Rx BY <bit6>:<len6> (SE)
+ case 0x12: // FEXT Rx BY <bit6>:<len6> (SE)
UML_AND(block, I0, REG(rx), MAKE_EXTRACT_MASK(bit, len));
UML_SHL(block, I0, I0, 32 - (bit + len));
UML_SAR(block, REG(rn), I0, 32 - (bit + len) + bit);
@@ -5577,7 +5577,7 @@ void adsp21062_device::generate_shift_imm(drcuml_block *block, compiler_state *c
if (SS_CALC_REQUIRED) UML_MOV(block, ASTAT_SS, 0);
return;
- case 0x19: // Rn = Rn OR FDEP Rx BY <bit6>:<len6>
+ case 0x19: // Rn = Rn OR FDEP Rx BY <bit6>:<len6>
UML_AND(block, I0, REG(rx), MAKE_EXTRACT_MASK(0, len));
if (bit > 0)
UML_SHL(block, I0, I0, bit);
@@ -5586,10 +5586,10 @@ void adsp21062_device::generate_shift_imm(drcuml_block *block, compiler_state *c
if (SZ_CALC_REQUIRED) UML_SETc(block, COND_Z, ASTAT_SZ);
if (SV_CALC_REQUIRED && (bit + len) > 32) UML_MOV(block, ASTAT_SV, 1);
if (SV_CALC_REQUIRED && (bit + len) <= 32) UML_MOV(block, ASTAT_SV, 0);
- if (SS_CALC_REQUIRED) UML_MOV(block, ASTAT_SS, 0);
+ if (SS_CALC_REQUIRED) UML_MOV(block, ASTAT_SS, 0);
return;
- case 0x30: // BSET Rx BY <data8>
+ case 0x30: // BSET Rx BY <data8>
UML_OR(block, REG(rn), REG(rx), 1 << data);
if (SZ_CALC_REQUIRED) UML_SETc(block, COND_Z, ASTAT_SZ);
if (SV_CALC_REQUIRED && data > 31) UML_MOV(block, ASTAT_SV, 1);
@@ -5597,7 +5597,7 @@ void adsp21062_device::generate_shift_imm(drcuml_block *block, compiler_state *c
if (SS_CALC_REQUIRED) UML_MOV(block, ASTAT_SS, 0);
return;
- case 0x31: // BCLR Rx By <data8>
+ case 0x31: // BCLR Rx By <data8>
UML_AND(block, REG(rn), REG(rx), ~(1 << data));
if (SZ_CALC_REQUIRED) UML_SETc(block, COND_Z, ASTAT_SZ);
if (SV_CALC_REQUIRED && data > 31) UML_MOV(block, ASTAT_SV, 1);
@@ -5605,7 +5605,7 @@ void adsp21062_device::generate_shift_imm(drcuml_block *block, compiler_state *c
if (SS_CALC_REQUIRED) UML_MOV(block, ASTAT_SS, 0);
return;
- case 0x32: // BTGL Rx BY <data8>
+ case 0x32: // BTGL Rx BY <data8>
UML_XOR(block, REG(rn), REG(rx), 1 << data);
if (SZ_CALC_REQUIRED) UML_SETc(block, COND_Z, ASTAT_SZ);
if (SV_CALC_REQUIRED && data > 31) UML_MOV(block, ASTAT_SV, 1);
@@ -5613,8 +5613,8 @@ void adsp21062_device::generate_shift_imm(drcuml_block *block, compiler_state *c
if (SS_CALC_REQUIRED) UML_MOV(block, ASTAT_SS, 0);
return;
- case 0x33: // BTST Rx BY <data8>
- UML_TEST(block, REG(rx), 1 << data);
+ case 0x33: // BTST Rx BY <data8>
+ UML_TEST(block, REG(rx), 1 << data);
if (SZ_CALC_REQUIRED) UML_SETc(block, COND_Z, ASTAT_SZ);
if (SV_CALC_REQUIRED && data > 31) UML_MOV(block, ASTAT_SV, 1);
if (SV_CALC_REQUIRED && data <= 31) UML_MOV(block, ASTAT_SV, 0);
@@ -5627,4 +5627,4 @@ void adsp21062_device::generate_shift_imm(drcuml_block *block, compiler_state *c
UML_CALLC(block, cfunc_unimplemented_compute, this);
return;
}
-} \ No newline at end of file
+}
diff --git a/src/devices/cpu/sharc/sharcfe.cpp b/src/devices/cpu/sharc/sharcfe.cpp
index bae9014ee33..105eea6c66c 100644
--- a/src/devices/cpu/sharc/sharcfe.cpp
+++ b/src/devices/cpu/sharc/sharcfe.cpp
@@ -10,62 +10,62 @@
#include "emu.h"
#include "sharcfe.h"
-#define REG_USED(desc,x) do { (desc).regin[0] |= 1 << (x); } while(0)
-#define REG_MODIFIED(desc,x) do { (desc).regout[0] |= 1 << (x); } while(0)
-
-#define AZ_USED(desc) do { (desc).regin[0] |= 1 << 16; } while(0)
-#define AZ_MODIFIED(desc) do { (desc).regout[0] |= 1 << 16; } while(0)
-#define AV_USED(desc) do { (desc).regin[0] |= 1 << 17; } while(0)
-#define AV_MODIFIED(desc) do { (desc).regout[0] |= 1 << 17; } while(0)
-#define AN_USED(desc) do { (desc).regin[0] |= 1 << 18; } while(0)
-#define AN_MODIFIED(desc) do { (desc).regout[0] |= 1 << 18; } while(0)
-#define AC_USED(desc) do { (desc).regin[0] |= 1 << 19; } while(0)
-#define AC_MODIFIED(desc) do { (desc).regout[0] |= 1 << 19; } while(0)
-#define AS_USED(desc) do { (desc).regin[0] |= 1 << 20; } while(0)
-#define AS_MODIFIED(desc) do { (desc).regout[0] |= 1 << 20; } while(0)
-#define AI_USED(desc) do { (desc).regin[0] |= 1 << 21; } while(0)
-#define AI_MODIFIED(desc) do { (desc).regout[0] |= 1 << 21; } while(0)
-#define MN_USED(desc) do { (desc).regin[0] |= 1 << 22; } while(0)
-#define MN_MODIFIED(desc) do { (desc).regout[0] |= 1 << 22; } while(0)
-#define MV_USED(desc) do { (desc).regin[0] |= 1 << 23; } while(0)
-#define MV_MODIFIED(desc) do { (desc).regout[0] |= 1 << 23; } while(0)
-#define MU_USED(desc) do { (desc).regin[0] |= 1 << 24; } while(0)
-#define MU_MODIFIED(desc) do { (desc).regout[0] |= 1 << 24; } while(0)
-#define MI_USED(desc) do { (desc).regin[0] |= 1 << 25; } while(0)
-#define MI_MODIFIED(desc) do { (desc).regout[0] |= 1 << 25; } while(0)
-#define SV_USED(desc) do { (desc).regin[0] |= 1 << 26; } while(0)
-#define SV_MODIFIED(desc) do { (desc).regout[0] |= 1 << 26; } while(0)
-#define SZ_USED(desc) do { (desc).regin[0] |= 1 << 27; } while(0)
-#define SZ_MODIFIED(desc) do { (desc).regout[0] |= 1 << 27; } while(0)
-#define SS_USED(desc) do { (desc).regin[0] |= 1 << 28; } while(0)
-#define SS_MODIFIED(desc) do { (desc).regout[0] |= 1 << 28; } while(0)
-#define BTF_USED(desc) do { (desc).regin[0] |= 1 << 29; } while(0)
-#define BTF_MODIFIED(desc) do { (desc).regout[0] |= 1 << 29; } while(0)
-#define AF_USED(desc) do { (desc).regin[0] |= 1 << 30; } while(0)
-#define AF_MODIFIED(desc) do { (desc).regout[0] |= 1 << 30; } while(0)
-
-#define ALU_FLAGS_MODIFIED(desc) do { AZ_MODIFIED(desc);AN_MODIFIED(desc);AV_MODIFIED(desc);AC_MODIFIED(desc);AS_MODIFIED(desc);AI_MODIFIED(desc); } while(0)
-#define MULT_FLAGS_MODIFIED(desc) do { MN_MODIFIED(desc);MV_MODIFIED(desc);MU_MODIFIED(desc);MI_MODIFIED(desc); } while(0)
-#define SHIFT_FLAGS_MODIFIED(desc) do { SZ_MODIFIED(desc);SV_MODIFIED(desc);SS_MODIFIED(desc); } while(0)
-
-
-#define PM_I_USED(desc,x) do { (desc).regin[1] |= 1 << (x); } while(0)
-#define PM_I_MODIFIED(desc,x) do { (desc).regout[1] |= 1 << (x); } while(0)
-#define PM_M_USED(desc,x) do { (desc).regin[1] |= 1 << ((x) + 8); } while(0)
-#define PM_M_MODIFIED(desc,x) do { (desc).regout[1] |= 1 << ((x) + 8); } while(0)
-#define PM_B_USED(desc,x) do { (desc).regin[1] |= 1 << ((x) + 16); } while(0)
-#define PM_B_MODIFIED(desc,x) do { (desc).regout[1] |= 1 << ((x) + 16); } while(0)
-#define PM_L_USED(desc,x) do { (desc).regin[1] |= 1 << ((x) + 24); } while(0)
-#define PM_L_MODIFIED(desc,x) do { (desc).regout[1] |= 1 << ((x) + 24); } while(0)
-
-#define DM_I_USED(desc,x) do { (desc).regin[2] |= 1 << (x); } while(0)
-#define DM_I_MODIFIED(desc,x) do { (desc).regout[2] |= 1 << (x); } while(0)
-#define DM_M_USED(desc,x) do { (desc).regin[2] |= 1 << ((x) + 8); } while(0)
-#define DM_M_MODIFIED(desc,x) do { (desc).regout[2] |= 1 << ((x) + 8); } while(0)
-#define DM_B_USED(desc,x) do { (desc).regin[2] |= 1 << ((x) + 16); } while(0)
-#define DM_B_MODIFIED(desc,x) do { (desc).regout[2] |= 1 << ((x) + 16); } while(0)
-#define DM_L_USED(desc,x) do { (desc).regin[2] |= 1 << ((x) + 24); } while(0)
-#define DM_L_MODIFIED(desc,x) do { (desc).regout[2] |= 1 << ((x) + 24); } while(0)
+#define REG_USED(desc,x) do { (desc).regin[0] |= 1 << (x); } while(0)
+#define REG_MODIFIED(desc,x) do { (desc).regout[0] |= 1 << (x); } while(0)
+
+#define AZ_USED(desc) do { (desc).regin[0] |= 1 << 16; } while(0)
+#define AZ_MODIFIED(desc) do { (desc).regout[0] |= 1 << 16; } while(0)
+#define AV_USED(desc) do { (desc).regin[0] |= 1 << 17; } while(0)
+#define AV_MODIFIED(desc) do { (desc).regout[0] |= 1 << 17; } while(0)
+#define AN_USED(desc) do { (desc).regin[0] |= 1 << 18; } while(0)
+#define AN_MODIFIED(desc) do { (desc).regout[0] |= 1 << 18; } while(0)
+#define AC_USED(desc) do { (desc).regin[0] |= 1 << 19; } while(0)
+#define AC_MODIFIED(desc) do { (desc).regout[0] |= 1 << 19; } while(0)
+#define AS_USED(desc) do { (desc).regin[0] |= 1 << 20; } while(0)
+#define AS_MODIFIED(desc) do { (desc).regout[0] |= 1 << 20; } while(0)
+#define AI_USED(desc) do { (desc).regin[0] |= 1 << 21; } while(0)
+#define AI_MODIFIED(desc) do { (desc).regout[0] |= 1 << 21; } while(0)
+#define MN_USED(desc) do { (desc).regin[0] |= 1 << 22; } while(0)
+#define MN_MODIFIED(desc) do { (desc).regout[0] |= 1 << 22; } while(0)
+#define MV_USED(desc) do { (desc).regin[0] |= 1 << 23; } while(0)
+#define MV_MODIFIED(desc) do { (desc).regout[0] |= 1 << 23; } while(0)
+#define MU_USED(desc) do { (desc).regin[0] |= 1 << 24; } while(0)
+#define MU_MODIFIED(desc) do { (desc).regout[0] |= 1 << 24; } while(0)
+#define MI_USED(desc) do { (desc).regin[0] |= 1 << 25; } while(0)
+#define MI_MODIFIED(desc) do { (desc).regout[0] |= 1 << 25; } while(0)
+#define SV_USED(desc) do { (desc).regin[0] |= 1 << 26; } while(0)
+#define SV_MODIFIED(desc) do { (desc).regout[0] |= 1 << 26; } while(0)
+#define SZ_USED(desc) do { (desc).regin[0] |= 1 << 27; } while(0)
+#define SZ_MODIFIED(desc) do { (desc).regout[0] |= 1 << 27; } while(0)
+#define SS_USED(desc) do { (desc).regin[0] |= 1 << 28; } while(0)
+#define SS_MODIFIED(desc) do { (desc).regout[0] |= 1 << 28; } while(0)
+#define BTF_USED(desc) do { (desc).regin[0] |= 1 << 29; } while(0)
+#define BTF_MODIFIED(desc) do { (desc).regout[0] |= 1 << 29; } while(0)
+#define AF_USED(desc) do { (desc).regin[0] |= 1 << 30; } while(0)
+#define AF_MODIFIED(desc) do { (desc).regout[0] |= 1 << 30; } while(0)
+
+#define ALU_FLAGS_MODIFIED(desc) do { AZ_MODIFIED(desc);AN_MODIFIED(desc);AV_MODIFIED(desc);AC_MODIFIED(desc);AS_MODIFIED(desc);AI_MODIFIED(desc); } while(0)
+#define MULT_FLAGS_MODIFIED(desc) do { MN_MODIFIED(desc);MV_MODIFIED(desc);MU_MODIFIED(desc);MI_MODIFIED(desc); } while(0)
+#define SHIFT_FLAGS_MODIFIED(desc) do { SZ_MODIFIED(desc);SV_MODIFIED(desc);SS_MODIFIED(desc); } while(0)
+
+
+#define PM_I_USED(desc,x) do { (desc).regin[1] |= 1 << (x); } while(0)
+#define PM_I_MODIFIED(desc,x) do { (desc).regout[1] |= 1 << (x); } while(0)
+#define PM_M_USED(desc,x) do { (desc).regin[1] |= 1 << ((x) + 8); } while(0)
+#define PM_M_MODIFIED(desc,x) do { (desc).regout[1] |= 1 << ((x) + 8); } while(0)
+#define PM_B_USED(desc,x) do { (desc).regin[1] |= 1 << ((x) + 16); } while(0)
+#define PM_B_MODIFIED(desc,x) do { (desc).regout[1] |= 1 << ((x) + 16); } while(0)
+#define PM_L_USED(desc,x) do { (desc).regin[1] |= 1 << ((x) + 24); } while(0)
+#define PM_L_MODIFIED(desc,x) do { (desc).regout[1] |= 1 << ((x) + 24); } while(0)
+
+#define DM_I_USED(desc,x) do { (desc).regin[2] |= 1 << (x); } while(0)
+#define DM_I_MODIFIED(desc,x) do { (desc).regout[2] |= 1 << (x); } while(0)
+#define DM_M_USED(desc,x) do { (desc).regin[2] |= 1 << ((x) + 8); } while(0)
+#define DM_M_MODIFIED(desc,x) do { (desc).regout[2] |= 1 << ((x) + 8); } while(0)
+#define DM_B_USED(desc,x) do { (desc).regin[2] |= 1 << ((x) + 16); } while(0)
+#define DM_B_MODIFIED(desc,x) do { (desc).regout[2] |= 1 << ((x) + 16); } while(0)
+#define DM_L_USED(desc,x) do { (desc).regin[2] |= 1 << ((x) + 24); } while(0)
+#define DM_L_MODIFIED(desc,x) do { (desc).regout[2] |= 1 << ((x) + 24); } while(0)
sharc_frontend::sharc_frontend(adsp21062_device *sharc, UINT32 window_start, UINT32 window_end, UINT32 max_sequence)
@@ -221,12 +221,12 @@ bool sharc_frontend::describe(opcode_desc &desc, const opcode_desc *prev)
switch ((opcode >> 45) & 7)
{
- case 0: // subops
+ case 0: // subops
{
UINT32 subop = (opcode >> 40) & 0x1f;
switch (subop)
{
- case 0x00: // NOP / idle |000|00000|
+ case 0x00: // NOP / idle |000|00000|
if (opcode & U64(0x008000000000))
{
// IDLE
@@ -236,9 +236,9 @@ bool sharc_frontend::describe(opcode_desc &desc, const opcode_desc *prev)
{
// NOP
}
- break;
+ break;
- case 0x01: // compute |000|00001|
+ case 0x01: // compute |000|00001|
{
int cond = (opcode >> 33) & 0x1f;
describe_if_condition(desc, cond);
@@ -248,7 +248,7 @@ bool sharc_frontend::describe(opcode_desc &desc, const opcode_desc *prev)
break;
}
- case 0x02: // immediate shift |000|00010|
+ case 0x02: // immediate shift |000|00010|
{
int shiftop = (opcode >> 16) & 0x3f;
int rn = (opcode >> 4) & 0xf;
@@ -261,8 +261,8 @@ bool sharc_frontend::describe(opcode_desc &desc, const opcode_desc *prev)
return false;
break;
}
-
- case 0x04: // compute / modify |000|00100|
+
+ case 0x04: // compute / modify |000|00100|
{
int g = (opcode >> 38) & 0x1;
int m = (opcode >> 27) & 0x7;
@@ -291,8 +291,8 @@ bool sharc_frontend::describe(opcode_desc &desc, const opcode_desc *prev)
break;
}
- case 0x06: // direct jump|call |000|00110|
- {
+ case 0x06: // direct jump|call |000|00110|
+ {
int j = (opcode >> 26) & 0x1;
int b = (opcode >> 39) & 0x1;
int cond = (opcode >> 33) & 0x1f;
@@ -312,7 +312,7 @@ bool sharc_frontend::describe(opcode_desc &desc, const opcode_desc *prev)
break;
}
- case 0x07: // direct jump|call |000|00111|
+ case 0x07: // direct jump|call |000|00111|
{
int j = (opcode >> 26) & 0x1;
int b = (opcode >> 39) & 0x1;
@@ -333,8 +333,8 @@ bool sharc_frontend::describe(opcode_desc &desc, const opcode_desc *prev)
break;
}
- case 0x08: // indirect jump|call / compute |000|01000|
- {
+ case 0x08: // indirect jump|call / compute |000|01000|
+ {
int j = (opcode >> 26) & 0x1;
int b = (opcode >> 39) & 0x1;
int pmi = (opcode >> 30) & 0x7;
@@ -361,12 +361,12 @@ bool sharc_frontend::describe(opcode_desc &desc, const opcode_desc *prev)
break;
}
- case 0x09: // indirect jump|call / compute |000|01001|
+ case 0x09: // indirect jump|call / compute |000|01001|
{
int j = (opcode >> 26) & 0x1;
int b = (opcode >> 39) & 0x1;
int cond = (opcode >> 33) & 0x1f;
-
+
if (!describe_compute(desc, opcode))
return false;
@@ -384,7 +384,7 @@ bool sharc_frontend::describe(opcode_desc &desc, const opcode_desc *prev)
break;
}
- case 0x0a: // return from subroutine / compute |000|01010|
+ case 0x0a: // return from subroutine / compute |000|01010|
{
int cond = (opcode >> 33) & 0x1f;
int j = (opcode >> 26) & 0x1;
@@ -404,7 +404,7 @@ bool sharc_frontend::describe(opcode_desc &desc, const opcode_desc *prev)
break;
}
- case 0x0b: // return from interrupt / compute |000|01011|
+ case 0x0b: // return from interrupt / compute |000|01011|
{
int cond = (opcode >> 33) & 0x1f;
int j = (opcode >> 26) & 0x1;
@@ -424,7 +424,7 @@ bool sharc_frontend::describe(opcode_desc &desc, const opcode_desc *prev)
break;
}
- case 0x0c: // do until counter expired |000|01100|
+ case 0x0c: // do until counter expired |000|01100|
{
int offset = SIGN_EXTEND24(opcode & 0xffffff);
@@ -439,7 +439,7 @@ bool sharc_frontend::describe(opcode_desc &desc, const opcode_desc *prev)
break;
}
- case 0x0d: // do until counter expired |000|01101|
+ case 0x0d: // do until counter expired |000|01101|
{
int ureg = (opcode >> 32) & 0xff;
if (!describe_ureg_access(desc, ureg, UREG_READ))
@@ -458,7 +458,7 @@ bool sharc_frontend::describe(opcode_desc &desc, const opcode_desc *prev)
break;
}
- case 0x0e: // do until |000|01110|
+ case 0x0e: // do until |000|01110|
{
int offset = SIGN_EXTEND24(opcode & 0xffffff);
int cond = (opcode >> 33) & 0x1f;
@@ -472,8 +472,8 @@ bool sharc_frontend::describe(opcode_desc &desc, const opcode_desc *prev)
/*
loop.astat_check_pc = loop.end_pc - 2;
if (loop.astat_check_pc < loop.start_pc)
- fatalerror("describe_compute: conditional loop < 2 at %08X", desc.pc);
- */
+ fatalerror("describe_compute: conditional loop < 2 at %08X", desc.pc);
+ */
int jump_diff = loop.end_pc - loop.start_pc;
if (jump_diff >= 2)
@@ -488,7 +488,7 @@ bool sharc_frontend::describe(opcode_desc &desc, const opcode_desc *prev)
break;
}
- case 0x0f: // immediate data -> ureg |000|01111|
+ case 0x0f: // immediate data -> ureg |000|01111|
{
int ureg = (opcode >> 32) & 0xff;
if (!describe_ureg_access(desc, ureg, UREG_WRITE))
@@ -496,7 +496,7 @@ bool sharc_frontend::describe(opcode_desc &desc, const opcode_desc *prev)
break;
}
- case 0x10: // ureg <-> DM|PM (direct) |000|100|G|D|
+ case 0x10: // ureg <-> DM|PM (direct) |000|100|G|D|
case 0x11:
case 0x12:
case 0x13:
@@ -518,7 +518,7 @@ bool sharc_frontend::describe(opcode_desc &desc, const opcode_desc *prev)
break;
}
- case 0x14: // system register bit manipulation |000|10100|
+ case 0x14: // system register bit manipulation |000|10100|
{
int bop = (opcode >> 37) & 0x7;
int sreg = (opcode >> 32) & 0xf;
@@ -526,10 +526,10 @@ bool sharc_frontend::describe(opcode_desc &desc, const opcode_desc *prev)
switch (bop)
{
- case 0: // SET
- case 1: // CLEAR
- case 2: // TOGGLE
- if (sreg == 0x7c) // ASTAT
+ case 0: // SET
+ case 1: // CLEAR
+ case 2: // TOGGLE
+ if (sreg == 0x7c) // ASTAT
{
if (data & adsp21062_device::AZ)
{
@@ -594,8 +594,8 @@ bool sharc_frontend::describe(opcode_desc &desc, const opcode_desc *prev)
}
break;
- case 4: // TEST
- case 5: // XOR
+ case 4: // TEST
+ case 5: // XOR
BTF_MODIFIED(desc);
break;
@@ -606,13 +606,13 @@ bool sharc_frontend::describe(opcode_desc &desc, const opcode_desc *prev)
break;
}
- case 0x16: // I register modify / bit-reverse |000|10110|
+ case 0x16: // I register modify / bit-reverse |000|10110|
{
- if (opcode & U64(0x008000000000)) // bit reverse
+ if (opcode & U64(0x008000000000)) // bit reverse
{
fatalerror("sharc_frontend::describe: bit reverse unimplemented");
}
- else // modify
+ else // modify
{
int g = (opcode >> 38) & 0x1;
int i = (opcode >> 32) & 0x7;
@@ -625,17 +625,17 @@ bool sharc_frontend::describe(opcode_desc &desc, const opcode_desc *prev)
break;
}
- case 0x17: // push|pop stacks / flush cache |000|10111|
+ case 0x17: // push|pop stacks / flush cache |000|10111|
break;
- case 0x18: // cjump |000|11000|
+ case 0x18: // cjump |000|11000|
fatalerror("sharc_frontend::describe: cjump unimplemented");
break;
- case 0x19: // rframe |000|11001|
+ case 0x19: // rframe |000|11001|
fatalerror("sharc_frontend::describe: rframe unimplemented");
break;
-
+
default:
fatalerror("sharc_frontend::describe: unknown subop %02X in opcode %04X%08X", subop, (UINT16)(opcode >> 32), (UINT32)(opcode));
return false;
@@ -643,7 +643,7 @@ bool sharc_frontend::describe(opcode_desc &desc, const opcode_desc *prev)
break;
}
- case 1: // compute / dreg <-> DM / dreg <-> PM |001|
+ case 1: // compute / dreg <-> DM / dreg <-> PM |001|
{
if (!describe_compute(desc, opcode))
return false;
@@ -689,7 +689,7 @@ bool sharc_frontend::describe(opcode_desc &desc, const opcode_desc *prev)
break;
}
- case 2: // compute / ureg <-> DM|PM, register modify |010|
+ case 2: // compute / ureg <-> DM|PM, register modify |010|
{
if (!describe_compute(desc, opcode))
return false;
@@ -737,7 +737,7 @@ bool sharc_frontend::describe(opcode_desc &desc, const opcode_desc *prev)
if (!describe_compute(desc, opcode))
return false;
- if (opcode & U64(0x100000000000)) // compute / ureg <-> ureg |011|1|
+ if (opcode & U64(0x100000000000)) // compute / ureg <-> ureg |011|1|
{
int src_ureg = (opcode >> 36) & 0xff;
int dst_ureg = (opcode >> 23) & 0xff;
@@ -750,7 +750,7 @@ bool sharc_frontend::describe(opcode_desc &desc, const opcode_desc *prev)
if (!describe_ureg_access(desc, dst_ureg, UREG_WRITE))
return false;
}
- else // compute / dreg <-> DM|PM, immediate modify |011|0|
+ else // compute / dreg <-> DM|PM, immediate modify |011|0|
{
int u = (opcode >> 38) & 0x1;
int d = (opcode >> 39) & 0x1;
@@ -771,13 +771,13 @@ bool sharc_frontend::describe(opcode_desc &desc, const opcode_desc *prev)
REG_MODIFIED(desc, dreg);
desc.flags |= OPFLAG_READS_MEMORY;
}
-
+
if (g)
{
// PM
PM_I_USED(desc, i);
- if (u) // post-modify with update
+ if (u) // post-modify with update
{
PM_I_MODIFIED(desc, i);
}
@@ -787,7 +787,7 @@ bool sharc_frontend::describe(opcode_desc &desc, const opcode_desc *prev)
// DM
DM_I_USED(desc, i);
- if (u) // post-modify with update
+ if (u) // post-modify with update
{
DM_I_MODIFIED(desc, i);
}
@@ -798,7 +798,7 @@ bool sharc_frontend::describe(opcode_desc &desc, const opcode_desc *prev)
case 4:
{
- if (opcode & U64(0x100000000000)) // immediate data -> DM|PM |100|1|
+ if (opcode & U64(0x100000000000)) // immediate data -> DM|PM |100|1|
{
int i = (opcode >> 41) & 0x7;
int m = (opcode >> 38) & 0x7;
@@ -821,7 +821,7 @@ bool sharc_frontend::describe(opcode_desc &desc, const opcode_desc *prev)
DM_M_USED(desc, m);
}
}
- else // immediate shift / dreg <-> DM|PM |100|0|
+ else // immediate shift / dreg <-> DM|PM |100|0|
{
int i = (opcode >> 41) & 0x7;
int m = (opcode >> 38) & 0x7;
@@ -867,7 +867,7 @@ bool sharc_frontend::describe(opcode_desc &desc, const opcode_desc *prev)
break;
}
- case 5: // ureg <-> DM|PM (indirect) |101|
+ case 5: // ureg <-> DM|PM (indirect) |101|
{
int ureg = (opcode >> 32) & 0xff;
int d = (opcode >> 40) & 1;
@@ -890,11 +890,11 @@ bool sharc_frontend::describe(opcode_desc &desc, const opcode_desc *prev)
if (g)
PM_I_USED(desc, i);
else
- DM_I_USED(desc, i);
+ DM_I_USED(desc, i);
break;
}
- case 6: // indirect jump / compute / dreg <-> DM |110|
+ case 6: // indirect jump / compute / dreg <-> DM |110|
{
int d = (opcode >> 44) & 0x1;
int dmi = (opcode >> 41) & 0x7;
@@ -936,7 +936,7 @@ bool sharc_frontend::describe(opcode_desc &desc, const opcode_desc *prev)
break;
}
- case 7: // indirect jump / compute / dreg <-> DM |111|
+ case 7: // indirect jump / compute / dreg <-> DM |111|
{
int d = (opcode >> 44) & 0x1;
int dmi = (opcode >> 41) & 0x7;
@@ -990,7 +990,7 @@ bool sharc_frontend::describe_compute(opcode_desc &desc, UINT64 opcode)
int rx = (opcode >> 4) & 0xf;
int ry = (opcode >> 0) & 0xf;
- if (opcode & 0x400000) // multi-function operation
+ if (opcode & 0x400000) // multi-function operation
{
UINT32 multiop = (opcode >> 16) & 0x3f;
int fm = rs;
@@ -1002,15 +1002,15 @@ bool sharc_frontend::describe_compute(opcode_desc &desc, UINT64 opcode)
switch (multiop)
{
- case 0x00: // Rn = MRxx
+ case 0x00: // Rn = MRxx
REG_MODIFIED(desc, rn);
break;
- case 0x01: // MRxx = Rn
+ case 0x01: // MRxx = Rn
REG_USED(desc, rn);
break;
- case 0x07: // Ra = Rx + Ry, Rs = Rx - Ry
- case 0x0f: // Fa = Fx + Fy, Fs = Fx - Fy
+ case 0x07: // Ra = Rx + Ry, Rs = Rx - Ry
+ case 0x0f: // Fa = Fx + Fy, Fs = Fx - Fy
REG_USED(desc, rx);
REG_USED(desc, ry);
REG_MODIFIED(desc, ra);
@@ -1018,9 +1018,9 @@ bool sharc_frontend::describe_compute(opcode_desc &desc, UINT64 opcode)
ALU_FLAGS_MODIFIED(desc);
break;
- case 0x04: // Rm = R3-0 * R7-4 (SSFR), Ra = R11-8 + R15-12
- case 0x05: // Rm = R3-0 * R7-4 (SSFR), Ra = R11-8 - R15-12
- case 0x06: // Rm = R3-0 * R7-4 (SSFR), Ra = (R11-8 + R15-12) / 2
+ case 0x04: // Rm = R3-0 * R7-4 (SSFR), Ra = R11-8 + R15-12
+ case 0x05: // Rm = R3-0 * R7-4 (SSFR), Ra = R11-8 - R15-12
+ case 0x06: // Rm = R3-0 * R7-4 (SSFR), Ra = (R11-8 + R15-12) / 2
REG_USED(desc, fxm);
REG_USED(desc, fym);
REG_USED(desc, fxa);
@@ -1031,9 +1031,9 @@ bool sharc_frontend::describe_compute(opcode_desc &desc, UINT64 opcode)
MULT_FLAGS_MODIFIED(desc);
break;
- case 0x08: // MRF = MRF + R3-0 * R7-4 (SSF), Ra = R11-8 + R15-12
- case 0x09: // MRF = MRF + R3-0 * R7-4 (SSF), Ra = R11-8 - R15-12
- case 0x0a: // MRF = MRF + R3-0 * R7-4 (SSF), Ra = (R11-8 + R15-12) / 2
+ case 0x08: // MRF = MRF + R3-0 * R7-4 (SSF), Ra = R11-8 + R15-12
+ case 0x09: // MRF = MRF + R3-0 * R7-4 (SSF), Ra = R11-8 - R15-12
+ case 0x0a: // MRF = MRF + R3-0 * R7-4 (SSF), Ra = (R11-8 + R15-12) / 2
REG_USED(desc, fxm);
REG_USED(desc, fym);
REG_USED(desc, fxa);
@@ -1042,9 +1042,9 @@ bool sharc_frontend::describe_compute(opcode_desc &desc, UINT64 opcode)
MULT_FLAGS_MODIFIED(desc);
break;
- case 0x0c: // Rm = MRF + R3-0 * R7-4 (SSFR), Ra = R11-8 + R15-12
- case 0x0d: // Rm = MRF + R3-0 * R7-4 (SSFR), Ra = R11-8 - R15-12
- case 0x0e: // Rm = MRF + R3-0 * R7-4 (SSFR), Ra = (R11-8 + R15-12) / 2
+ case 0x0c: // Rm = MRF + R3-0 * R7-4 (SSFR), Ra = R11-8 + R15-12
+ case 0x0d: // Rm = MRF + R3-0 * R7-4 (SSFR), Ra = R11-8 - R15-12
+ case 0x0e: // Rm = MRF + R3-0 * R7-4 (SSFR), Ra = (R11-8 + R15-12) / 2
REG_USED(desc, fxm);
REG_USED(desc, fym);
REG_USED(desc, fxa);
@@ -1055,9 +1055,9 @@ bool sharc_frontend::describe_compute(opcode_desc &desc, UINT64 opcode)
MULT_FLAGS_MODIFIED(desc);
break;
- case 0x10: // MRF = MRF - R3-0 * R7-4 (SSF), Ra = R11-8 + R15-12
- case 0x11: // MRF = MRF - R3-0 * R7-4 (SSF), Ra = R11-8 - R15-12
- case 0x12: // MRF = MRF - R3-0 * R7-4 (SSF), Ra = (R11-8 + R15-12) / 2
+ case 0x10: // MRF = MRF - R3-0 * R7-4 (SSF), Ra = R11-8 + R15-12
+ case 0x11: // MRF = MRF - R3-0 * R7-4 (SSF), Ra = R11-8 - R15-12
+ case 0x12: // MRF = MRF - R3-0 * R7-4 (SSF), Ra = (R11-8 + R15-12) / 2
REG_USED(desc, fxm);
REG_USED(desc, fym);
REG_USED(desc, fxa);
@@ -1066,9 +1066,9 @@ bool sharc_frontend::describe_compute(opcode_desc &desc, UINT64 opcode)
MULT_FLAGS_MODIFIED(desc);
break;
- case 0x14: // Rm = MRF - R3-0 * R7-4 (SSFR), Ra = R11-8 + R15-12
- case 0x15: // Rm = MRF - R3-0 * R7-4 (SSFR), Ra = R11-8 - R15-12
- case 0x16: // Rm = MRF - R3-0 * R7-4 (SSFR), Ra = (R11-8 + R15-12) / 2
+ case 0x14: // Rm = MRF - R3-0 * R7-4 (SSFR), Ra = R11-8 + R15-12
+ case 0x15: // Rm = MRF - R3-0 * R7-4 (SSFR), Ra = R11-8 - R15-12
+ case 0x16: // Rm = MRF - R3-0 * R7-4 (SSFR), Ra = (R11-8 + R15-12) / 2
REG_USED(desc, fxm);
REG_USED(desc, fym);
REG_USED(desc, fxa);
@@ -1079,13 +1079,13 @@ bool sharc_frontend::describe_compute(opcode_desc &desc, UINT64 opcode)
MULT_FLAGS_MODIFIED(desc);
break;
- case 0x18: // Fm = F3-0 * F7-4, Fa = F11-8 + F15-12
- case 0x19: // Fm = F3-0 * F7-4, Fa = F11-8 - F15-12
- case 0x1a: // Fm = F3-0 * F7-4, Fa = FLOAT F11-8 BY R15-12
- case 0x1b: // Fm = F3-0 * F7-4, Fa = FIX F11-8 BY R15-12
- case 0x1c: // Fm = F3-0 * F7-4, Fa = (F11-8 + F15-12) / 2
- case 0x1e: // Fm = F3-0 * F7-4, Fa = MAX(F11-8, F15-12)
- case 0x1f: // Fm = F3-0 * F7-4, Fa = MIN(F11-8, F15-12)
+ case 0x18: // Fm = F3-0 * F7-4, Fa = F11-8 + F15-12
+ case 0x19: // Fm = F3-0 * F7-4, Fa = F11-8 - F15-12
+ case 0x1a: // Fm = F3-0 * F7-4, Fa = FLOAT F11-8 BY R15-12
+ case 0x1b: // Fm = F3-0 * F7-4, Fa = FIX F11-8 BY R15-12
+ case 0x1c: // Fm = F3-0 * F7-4, Fa = (F11-8 + F15-12) / 2
+ case 0x1e: // Fm = F3-0 * F7-4, Fa = MAX(F11-8, F15-12)
+ case 0x1f: // Fm = F3-0 * F7-4, Fa = MIN(F11-8, F15-12)
REG_USED(desc, fxm);
REG_USED(desc, fym);
REG_USED(desc, fxa);
@@ -1096,7 +1096,7 @@ bool sharc_frontend::describe_compute(opcode_desc &desc, UINT64 opcode)
MULT_FLAGS_MODIFIED(desc);
break;
- case 0x1d: // Fm = F3-0 * F7-4, Fa = ABS F11-8
+ case 0x1d: // Fm = F3-0 * F7-4, Fa = ABS F11-8
REG_USED(desc, fxm);
REG_USED(desc, fym);
REG_USED(desc, fxa);
@@ -1139,48 +1139,48 @@ bool sharc_frontend::describe_compute(opcode_desc &desc, UINT64 opcode)
return false;
}
}
- else // single-function operation
+ else // single-function operation
{
UINT32 operation = (opcode >> 12) & 0xff;
switch ((opcode >> 20) & 3)
{
- case 0: // ALU operations
+ case 0: // ALU operations
{
switch (operation)
{
- case 0x01: // Rn = Rx + Ry
- case 0x02: // Rn = Rx - Ry
- case 0x09: // Rn = (Rx + Ry) / 2
- case 0x40: // Rn = Rx AND Ry
- case 0x41: // Rn = Rx OR Ry
- case 0x42: // Rn = Rx XOR Ry
- case 0x61: // Rn = MIN(Rx, Ry)
- case 0x62: // Rn = MAX(Rx, Ry)
- case 0x63: // Rn = CLIP Rx BY Ry
- case 0x81: // Fn = Fx + Fy
- case 0x82: // Fn = Fx - Fy
- case 0x91: // Fn = ABS(Fx + Fy)
- case 0x92: // Fn = ABS(Fx - Fy)
- case 0x89: // Fn = (Fx + Fy) / 2
- case 0xbd: // Fn = SCALB Fx BY Ry
- case 0xd9: // Rn = FIX Fx BY Ry
- case 0xdd: // Rn = TRUNC Fx BY Ry
- case 0xda: // Fn = FLOAT Rx BY Ry
- case 0xe1: // Fn = MIN(Fx, Fy)
- case 0xe2: // Fn = MAX(Fx, Fy)
- case 0xe3: // Fn = CLIP Fx BY Fy
- case 0xe0: // Fn = Fx COPYSIGN Fy
+ case 0x01: // Rn = Rx + Ry
+ case 0x02: // Rn = Rx - Ry
+ case 0x09: // Rn = (Rx + Ry) / 2
+ case 0x40: // Rn = Rx AND Ry
+ case 0x41: // Rn = Rx OR Ry
+ case 0x42: // Rn = Rx XOR Ry
+ case 0x61: // Rn = MIN(Rx, Ry)
+ case 0x62: // Rn = MAX(Rx, Ry)
+ case 0x63: // Rn = CLIP Rx BY Ry
+ case 0x81: // Fn = Fx + Fy
+ case 0x82: // Fn = Fx - Fy
+ case 0x91: // Fn = ABS(Fx + Fy)
+ case 0x92: // Fn = ABS(Fx - Fy)
+ case 0x89: // Fn = (Fx + Fy) / 2
+ case 0xbd: // Fn = SCALB Fx BY Ry
+ case 0xd9: // Rn = FIX Fx BY Ry
+ case 0xdd: // Rn = TRUNC Fx BY Ry
+ case 0xda: // Fn = FLOAT Rx BY Ry
+ case 0xe1: // Fn = MIN(Fx, Fy)
+ case 0xe2: // Fn = MAX(Fx, Fy)
+ case 0xe3: // Fn = CLIP Fx BY Fy
+ case 0xe0: // Fn = Fx COPYSIGN Fy
REG_USED(desc, rx);
REG_USED(desc, ry);
REG_MODIFIED(desc, rn);
ALU_FLAGS_MODIFIED(desc);
break;
- case 0x05: // Rn = Rx + Ry + CI
- case 0x06: // Rn = Rx - Ry + CI - 1
- case 0x25: // Rn = Rx + CI
- case 0x26: // Rn = Rx + CI - 1
+ case 0x05: // Rn = Rx + Ry + CI
+ case 0x06: // Rn = Rx - Ry + CI - 1
+ case 0x25: // Rn = Rx + CI
+ case 0x26: // Rn = Rx + CI - 1
REG_USED(desc, rx);
REG_USED(desc, ry);
REG_MODIFIED(desc, rn);
@@ -1188,30 +1188,30 @@ bool sharc_frontend::describe_compute(opcode_desc &desc, UINT64 opcode)
ALU_FLAGS_MODIFIED(desc);
break;
- case 0x0a: // COMP(Rx, Ry)
- case 0x8a: // COMP(Fx, Fy)
+ case 0x0a: // COMP(Rx, Ry)
+ case 0x8a: // COMP(Fx, Fy)
REG_USED(desc, rx);
REG_USED(desc, ry);
ALU_FLAGS_MODIFIED(desc);
break;
- case 0x29: // Rn = Rx + 1
- case 0x2a: // Rn = Rx - 1
- case 0x22: // Rn = -Rx
- case 0x30: // Rn = ABS Rx
- case 0x21: // Rn = PASS Rx
- case 0x43: // Rn = NOT Rx
- case 0xb0: // Fn = ABS(Fx)
- case 0xa1: // Fn = PASS Fx
- case 0xa2: // Fn = -Fx
- case 0xa5: // Fn = RND Fx
- case 0xad: // Rn = MANT Fx
- case 0xc1: // Rn = LOGB Fx
- case 0xc9: // Rn = FIX Fx
- case 0xcd: // Rn = TRUNC Fx
- case 0xca: // Fn = FLOAT Rx
- case 0xc4: // Fn = RECIPS Fx
- case 0xc5: // Fn = RSQRTS Fx
+ case 0x29: // Rn = Rx + 1
+ case 0x2a: // Rn = Rx - 1
+ case 0x22: // Rn = -Rx
+ case 0x30: // Rn = ABS Rx
+ case 0x21: // Rn = PASS Rx
+ case 0x43: // Rn = NOT Rx
+ case 0xb0: // Fn = ABS(Fx)
+ case 0xa1: // Fn = PASS Fx
+ case 0xa2: // Fn = -Fx
+ case 0xa5: // Fn = RND Fx
+ case 0xad: // Rn = MANT Fx
+ case 0xc1: // Rn = LOGB Fx
+ case 0xc9: // Rn = FIX Fx
+ case 0xcd: // Rn = TRUNC Fx
+ case 0xca: // Fn = FLOAT Rx
+ case 0xc4: // Fn = RECIPS Fx
+ case 0xc5: // Fn = RSQRTS Fx
REG_USED(desc, rx);
REG_MODIFIED(desc, rn);
ALU_FLAGS_MODIFIED(desc);
@@ -1248,76 +1248,76 @@ bool sharc_frontend::describe_compute(opcode_desc &desc, UINT64 opcode)
break;
}
- case 1: // multiplier operations
+ case 1: // multiplier operations
{
switch (operation)
{
- case 0x40: // Rn = Rx * Ry (UUI)
- case 0x48: // Rn = Rx * Ry (UUF)
- case 0x49: // Rn = Rx * Ry (UUFR)
- case 0x50: // Rn = Rx * Ry (SUI)
- case 0x58: // Rn = Rx * Ry (SUF)
- case 0x59: // Rn = Rx * Ry (SUFR)
- case 0x60: // Rn = Rx * Ry (USI)
- case 0x68: // Rn = Rx * Ry (USF)
- case 0x69: // Rn = Rx * Ry (USFR)
- case 0x70: // Rn = Rx * Ry (SSI)
- case 0x78: // Rn = Rx * Ry (SSF)
- case 0x79: // Rn = Rx * Ry (SSFR)
+ case 0x40: // Rn = Rx * Ry (UUI)
+ case 0x48: // Rn = Rx * Ry (UUF)
+ case 0x49: // Rn = Rx * Ry (UUFR)
+ case 0x50: // Rn = Rx * Ry (SUI)
+ case 0x58: // Rn = Rx * Ry (SUF)
+ case 0x59: // Rn = Rx * Ry (SUFR)
+ case 0x60: // Rn = Rx * Ry (USI)
+ case 0x68: // Rn = Rx * Ry (USF)
+ case 0x69: // Rn = Rx * Ry (USFR)
+ case 0x70: // Rn = Rx * Ry (SSI)
+ case 0x78: // Rn = Rx * Ry (SSF)
+ case 0x79: // Rn = Rx * Ry (SSFR)
REG_USED(desc, rx);
REG_USED(desc, ry);
REG_MODIFIED(desc, rn);
MULT_FLAGS_MODIFIED(desc);
break;
- case 0x44: // MRF = Rx * Ry (UUI)
- case 0x4c: // MRF = Rx * Ry (UUF)
- case 0x4d: // MRF = Rx * Ry (UUFR)
- case 0x54: // MRF = Rx * Ry (SUI)
- case 0x5c: // MRF = Rx * Ry (SUF)
- case 0x5d: // MRF = Rx * Ry (SUFR)
- case 0x64: // MRF = Rx * Ry (USI)
- case 0x6c: // MRF = Rx * Ry (USF)
- case 0x6d: // MRF = Rx * Ry (USFR)
- case 0x74: // MRF = Rx * Ry (SSI)
- case 0x7c: // MRF = Rx * Ry (SSF)
- case 0x7d: // MRF = Rx * Ry (SSFR)
+ case 0x44: // MRF = Rx * Ry (UUI)
+ case 0x4c: // MRF = Rx * Ry (UUF)
+ case 0x4d: // MRF = Rx * Ry (UUFR)
+ case 0x54: // MRF = Rx * Ry (SUI)
+ case 0x5c: // MRF = Rx * Ry (SUF)
+ case 0x5d: // MRF = Rx * Ry (SUFR)
+ case 0x64: // MRF = Rx * Ry (USI)
+ case 0x6c: // MRF = Rx * Ry (USF)
+ case 0x6d: // MRF = Rx * Ry (USFR)
+ case 0x74: // MRF = Rx * Ry (SSI)
+ case 0x7c: // MRF = Rx * Ry (SSF)
+ case 0x7d: // MRF = Rx * Ry (SSFR)
// TODO: track MRF?
REG_USED(desc, rx);
REG_USED(desc, ry);
MULT_FLAGS_MODIFIED(desc);
break;
- case 0x46: // MRB = Rx * Ry (UUI)
- case 0x4e: // MRB = Rx * Ry (UUF)
- case 0x4f: // MRB = Rx * Ry (UUFR)
- case 0x56: // MRB = Rx * Ry (SUI)
- case 0x5e: // MRB = Rx * Ry (SUF)
- case 0x5f: // MRB = Rx * Ry (SUFR)
- case 0x66: // MRB = Rx * Ry (USI)
- case 0x6e: // MRB = Rx * Ry (USF)
- case 0x6f: // MRB = Rx * Ry (USFR)
- case 0x76: // MRB = Rx * Ry (SSI)
- case 0x7e: // MRB = Rx * Ry (SSF)
- case 0x7f: // MRB = Rx * Ry (SSFR)
+ case 0x46: // MRB = Rx * Ry (UUI)
+ case 0x4e: // MRB = Rx * Ry (UUF)
+ case 0x4f: // MRB = Rx * Ry (UUFR)
+ case 0x56: // MRB = Rx * Ry (SUI)
+ case 0x5e: // MRB = Rx * Ry (SUF)
+ case 0x5f: // MRB = Rx * Ry (SUFR)
+ case 0x66: // MRB = Rx * Ry (USI)
+ case 0x6e: // MRB = Rx * Ry (USF)
+ case 0x6f: // MRB = Rx * Ry (USFR)
+ case 0x76: // MRB = Rx * Ry (SSI)
+ case 0x7e: // MRB = Rx * Ry (SSF)
+ case 0x7f: // MRB = Rx * Ry (SSFR)
// TODO: track MRB?
REG_USED(desc, rx);
REG_USED(desc, ry);
MULT_FLAGS_MODIFIED(desc);
break;
- case 0x80: // Rn = MRF + Rx * Ry (UUI)
- case 0x88: // Rn = MRF + Rx * Ry (UUF)
- case 0x89: // Rn = MRF + Rx * Ry (UUFR)
- case 0x90: // Rn = MRF + Rx * Ry (SUI)
- case 0x98: // Rn = MRF + Rx * Ry (SUF)
- case 0x99: // Rn = MRF + Rx * Ry (SUFR)
- case 0xa0: // Rn = MRF + Rx * Ry (USI)
- case 0xa8: // Rn = MRF + Rx * Ry (USF)
- case 0xa9: // Rn = MRF + Rx * Ry (USFR)
- case 0xb0: // Rn = MRF + Rx * Ry (SSI)
- case 0xb8: // Rn = MRF + Rx * Ry (SSF)
- case 0xb9: // Rn = MRF + Rx * Ry (SSFR)
+ case 0x80: // Rn = MRF + Rx * Ry (UUI)
+ case 0x88: // Rn = MRF + Rx * Ry (UUF)
+ case 0x89: // Rn = MRF + Rx * Ry (UUFR)
+ case 0x90: // Rn = MRF + Rx * Ry (SUI)
+ case 0x98: // Rn = MRF + Rx * Ry (SUF)
+ case 0x99: // Rn = MRF + Rx * Ry (SUFR)
+ case 0xa0: // Rn = MRF + Rx * Ry (USI)
+ case 0xa8: // Rn = MRF + Rx * Ry (USF)
+ case 0xa9: // Rn = MRF + Rx * Ry (USFR)
+ case 0xb0: // Rn = MRF + Rx * Ry (SSI)
+ case 0xb8: // Rn = MRF + Rx * Ry (SSF)
+ case 0xb9: // Rn = MRF + Rx * Ry (SSFR)
// TODO: track MRF?
REG_USED(desc, rx);
REG_USED(desc, ry);
@@ -1325,18 +1325,18 @@ bool sharc_frontend::describe_compute(opcode_desc &desc, UINT64 opcode)
MULT_FLAGS_MODIFIED(desc);
break;
- case 0x82: // Rn = MRB + Rx * Ry (UUI)
- case 0x8a: // Rn = MRB + Rx * Ry (UUF)
- case 0x8b: // Rn = MRB + Rx * Ry (UUFR)
- case 0x92: // Rn = MRB + Rx * Ry (SUI)
- case 0x9a: // Rn = MRB + Rx * Ry (SUF)
- case 0x9b: // Rn = MRB + Rx * Ry (SUFR)
- case 0xa2: // Rn = MRB + Rx * Ry (USI)
- case 0xaa: // Rn = MRB + Rx * Ry (USF)
- case 0xab: // Rn = MRB + Rx * Ry (USFR)
- case 0xb2: // Rn = MRB + Rx * Ry (SSI)
- case 0xba: // Rn = MRB + Rx * Ry (SSF)
- case 0xbb: // Rn = MRB + Rx * Ry (SSFR)
+ case 0x82: // Rn = MRB + Rx * Ry (UUI)
+ case 0x8a: // Rn = MRB + Rx * Ry (UUF)
+ case 0x8b: // Rn = MRB + Rx * Ry (UUFR)
+ case 0x92: // Rn = MRB + Rx * Ry (SUI)
+ case 0x9a: // Rn = MRB + Rx * Ry (SUF)
+ case 0x9b: // Rn = MRB + Rx * Ry (SUFR)
+ case 0xa2: // Rn = MRB + Rx * Ry (USI)
+ case 0xaa: // Rn = MRB + Rx * Ry (USF)
+ case 0xab: // Rn = MRB + Rx * Ry (USFR)
+ case 0xb2: // Rn = MRB + Rx * Ry (SSI)
+ case 0xba: // Rn = MRB + Rx * Ry (SSF)
+ case 0xbb: // Rn = MRB + Rx * Ry (SSFR)
// TODO: track MRB?
REG_USED(desc, rx);
REG_USED(desc, ry);
@@ -1344,55 +1344,55 @@ bool sharc_frontend::describe_compute(opcode_desc &desc, UINT64 opcode)
MULT_FLAGS_MODIFIED(desc);
break;
- case 0x84: // MRF = MRF + Rx * Ry (UUI)
- case 0x8c: // MRF = MRF + Rx * Ry (UUF)
- case 0x8d: // MRF = MRF + Rx * Ry (UUFR)
- case 0x94: // MRF = MRF + Rx * Ry (SUI)
- case 0x9c: // MRF = MRF + Rx * Ry (SUF)
- case 0x9d: // MRF = MRF + Rx * Ry (SUFR)
- case 0xa4: // MRF = MRF + Rx * Ry (USI)
- case 0xac: // MRF = MRF + Rx * Ry (USF)
- case 0xad: // MRF = MRF + Rx * Ry (USFR)
- case 0xb4: // MRF = MRF + Rx * Ry (SSI)
- case 0xbc: // MRF = MRF + Rx * Ry (SSF)
- case 0xbd: // MRF = MRF + Rx * Ry (SSFR)
+ case 0x84: // MRF = MRF + Rx * Ry (UUI)
+ case 0x8c: // MRF = MRF + Rx * Ry (UUF)
+ case 0x8d: // MRF = MRF + Rx * Ry (UUFR)
+ case 0x94: // MRF = MRF + Rx * Ry (SUI)
+ case 0x9c: // MRF = MRF + Rx * Ry (SUF)
+ case 0x9d: // MRF = MRF + Rx * Ry (SUFR)
+ case 0xa4: // MRF = MRF + Rx * Ry (USI)
+ case 0xac: // MRF = MRF + Rx * Ry (USF)
+ case 0xad: // MRF = MRF + Rx * Ry (USFR)
+ case 0xb4: // MRF = MRF + Rx * Ry (SSI)
+ case 0xbc: // MRF = MRF + Rx * Ry (SSF)
+ case 0xbd: // MRF = MRF + Rx * Ry (SSFR)
// TODO: track MRF?
REG_USED(desc, rx);
REG_USED(desc, ry);
MULT_FLAGS_MODIFIED(desc);
break;
- case 0x86: // MRB = MRB + Rx * Ry (UUI)
- case 0x8e: // MRB = MRB + Rx * Ry (UUF)
- case 0x8f: // MRB = MRB + Rx * Ry (UUFR)
- case 0x96: // MRB = MRB + Rx * Ry (SUI)
- case 0x9e: // MRB = MRB + Rx * Ry (SUF)
- case 0x9f: // MRB = MRB + Rx * Ry (SUFR)
- case 0xa6: // MRB = MRB + Rx * Ry (USI)
- case 0xae: // MRB = MRB + Rx * Ry (USF)
- case 0xaf: // MRB = MRB + Rx * Ry (USFR)
- case 0xb6: // MRB = MRB + Rx * Ry (SSI)
- case 0xbe: // MRB = MRB + Rx * Ry (SSF)
- case 0xbf: // MRB = MRB + Rx * Ry (SSFR)
+ case 0x86: // MRB = MRB + Rx * Ry (UUI)
+ case 0x8e: // MRB = MRB + Rx * Ry (UUF)
+ case 0x8f: // MRB = MRB + Rx * Ry (UUFR)
+ case 0x96: // MRB = MRB + Rx * Ry (SUI)
+ case 0x9e: // MRB = MRB + Rx * Ry (SUF)
+ case 0x9f: // MRB = MRB + Rx * Ry (SUFR)
+ case 0xa6: // MRB = MRB + Rx * Ry (USI)
+ case 0xae: // MRB = MRB + Rx * Ry (USF)
+ case 0xaf: // MRB = MRB + Rx * Ry (USFR)
+ case 0xb6: // MRB = MRB + Rx * Ry (SSI)
+ case 0xbe: // MRB = MRB + Rx * Ry (SSF)
+ case 0xbf: // MRB = MRB + Rx * Ry (SSFR)
break;
// TODO: track MRB?
REG_USED(desc, rx);
REG_USED(desc, ry);
MULT_FLAGS_MODIFIED(desc);
break;
-
- case 0xc0: // Rn = MRF - Rx * Ry (UUI)
- case 0xc8: // Rn = MRF - Rx * Ry (UUF)
- case 0xc9: // Rn = MRF - Rx * Ry (UUFR)
- case 0xd0: // Rn = MRF - Rx * Ry (SUI)
- case 0xd8: // Rn = MRF - Rx * Ry (SUF)
- case 0xd9: // Rn = MRF - Rx * Ry (SUFR)
- case 0xe0: // Rn = MRF - Rx * Ry (USI)
- case 0xe8: // Rn = MRF - Rx * Ry (USF)
- case 0xe9: // Rn = MRF - Rx * Ry (USFR)
- case 0xf0: // Rn = MRF - Rx * Ry (SSI)
- case 0xf8: // Rn = MRF - Rx * Ry (SSF)
- case 0xf9: // Rn = MRF - Rx * Ry (SSFR)
+
+ case 0xc0: // Rn = MRF - Rx * Ry (UUI)
+ case 0xc8: // Rn = MRF - Rx * Ry (UUF)
+ case 0xc9: // Rn = MRF - Rx * Ry (UUFR)
+ case 0xd0: // Rn = MRF - Rx * Ry (SUI)
+ case 0xd8: // Rn = MRF - Rx * Ry (SUF)
+ case 0xd9: // Rn = MRF - Rx * Ry (SUFR)
+ case 0xe0: // Rn = MRF - Rx * Ry (USI)
+ case 0xe8: // Rn = MRF - Rx * Ry (USF)
+ case 0xe9: // Rn = MRF - Rx * Ry (USFR)
+ case 0xf0: // Rn = MRF - Rx * Ry (SSI)
+ case 0xf8: // Rn = MRF - Rx * Ry (SSF)
+ case 0xf9: // Rn = MRF - Rx * Ry (SSFR)
// TODO: track MRF?
REG_USED(desc, rx);
REG_USED(desc, ry);
@@ -1400,18 +1400,18 @@ bool sharc_frontend::describe_compute(opcode_desc &desc, UINT64 opcode)
MULT_FLAGS_MODIFIED(desc);
break;
- case 0xc2: // Rn = MRB - Rx * Ry (UUI)
- case 0xca: // Rn = MRB - Rx * Ry (UUF)
- case 0xcb: // Rn = MRB - Rx * Ry (UUFR)
- case 0xd2: // Rn = MRB - Rx * Ry (SUI)
- case 0xda: // Rn = MRB - Rx * Ry (SUF)
- case 0xdb: // Rn = MRB - Rx * Ry (SUFR)
- case 0xe2: // Rn = MRB - Rx * Ry (USI)
- case 0xea: // Rn = MRB - Rx * Ry (USF)
- case 0xeb: // Rn = MRB - Rx * Ry (USFR)
- case 0xf2: // Rn = MRB - Rx * Ry (SSI)
- case 0xfa: // Rn = MRB - Rx * Ry (SSF)
- case 0xfb: // Rn = MRB - Rx * Ry (SSFR)
+ case 0xc2: // Rn = MRB - Rx * Ry (UUI)
+ case 0xca: // Rn = MRB - Rx * Ry (UUF)
+ case 0xcb: // Rn = MRB - Rx * Ry (UUFR)
+ case 0xd2: // Rn = MRB - Rx * Ry (SUI)
+ case 0xda: // Rn = MRB - Rx * Ry (SUF)
+ case 0xdb: // Rn = MRB - Rx * Ry (SUFR)
+ case 0xe2: // Rn = MRB - Rx * Ry (USI)
+ case 0xea: // Rn = MRB - Rx * Ry (USF)
+ case 0xeb: // Rn = MRB - Rx * Ry (USFR)
+ case 0xf2: // Rn = MRB - Rx * Ry (SSI)
+ case 0xfa: // Rn = MRB - Rx * Ry (SSF)
+ case 0xfb: // Rn = MRB - Rx * Ry (SSFR)
// TODO: track MRB?
REG_USED(desc, rx);
REG_USED(desc, ry);
@@ -1419,106 +1419,106 @@ bool sharc_frontend::describe_compute(opcode_desc &desc, UINT64 opcode)
MULT_FLAGS_MODIFIED(desc);
break;
- case 0xc4: // MRF = MRF - Rx * Ry (UUI)
- case 0xcc: // MRF = MRF - Rx * Ry (UUF)
- case 0xcd: // MRF = MRF - Rx * Ry (UUFR)
- case 0xd4: // MRF = MRF - Rx * Ry (SUI)
- case 0xdc: // MRF = MRF - Rx * Ry (SUF)
- case 0xdd: // MRF = MRF - Rx * Ry (SUFR)
- case 0xe4: // MRF = MRF - Rx * Ry (USI)
- case 0xec: // MRF = MRF - Rx * Ry (USF)
- case 0xed: // MRF = MRF - Rx * Ry (USFR)
- case 0xf4: // MRF = MRF - Rx * Ry (SSI)
- case 0xfc: // MRF = MRF - Rx * Ry (SSF)
- case 0xfd: // MRF = MRF - Rx * Ry (SSFR)
+ case 0xc4: // MRF = MRF - Rx * Ry (UUI)
+ case 0xcc: // MRF = MRF - Rx * Ry (UUF)
+ case 0xcd: // MRF = MRF - Rx * Ry (UUFR)
+ case 0xd4: // MRF = MRF - Rx * Ry (SUI)
+ case 0xdc: // MRF = MRF - Rx * Ry (SUF)
+ case 0xdd: // MRF = MRF - Rx * Ry (SUFR)
+ case 0xe4: // MRF = MRF - Rx * Ry (USI)
+ case 0xec: // MRF = MRF - Rx * Ry (USF)
+ case 0xed: // MRF = MRF - Rx * Ry (USFR)
+ case 0xf4: // MRF = MRF - Rx * Ry (SSI)
+ case 0xfc: // MRF = MRF - Rx * Ry (SSF)
+ case 0xfd: // MRF = MRF - Rx * Ry (SSFR)
// TODO: track MRF?
REG_USED(desc, rx);
REG_USED(desc, ry);
MULT_FLAGS_MODIFIED(desc);
break;
- case 0xc6: // MRB = MRB - Rx * Ry (UUI)
- case 0xce: // MRB = MRB - Rx * Ry (UUF)
- case 0xcf: // MRB = MRB - Rx * Ry (UUFR)
- case 0xd6: // MRB = MRB - Rx * Ry (SUI)
- case 0xde: // MRB = MRB - Rx * Ry (SUF)
- case 0xdf: // MRB = MRB - Rx * Ry (SUFR)
- case 0xe6: // MRB = MRB - Rx * Ry (USI)
- case 0xee: // MRB = MRB - Rx * Ry (USF)
- case 0xef: // MRB = MRB - Rx * Ry (USFR)
- case 0xf6: // MRB = MRB - Rx * Ry (SSI)
- case 0xfe: // MRB = MRB - Rx * Ry (SSF)
- case 0xff: // MRB = MRB - Rx * Ry (SSFR)
+ case 0xc6: // MRB = MRB - Rx * Ry (UUI)
+ case 0xce: // MRB = MRB - Rx * Ry (UUF)
+ case 0xcf: // MRB = MRB - Rx * Ry (UUFR)
+ case 0xd6: // MRB = MRB - Rx * Ry (SUI)
+ case 0xde: // MRB = MRB - Rx * Ry (SUF)
+ case 0xdf: // MRB = MRB - Rx * Ry (SUFR)
+ case 0xe6: // MRB = MRB - Rx * Ry (USI)
+ case 0xee: // MRB = MRB - Rx * Ry (USF)
+ case 0xef: // MRB = MRB - Rx * Ry (USFR)
+ case 0xf6: // MRB = MRB - Rx * Ry (SSI)
+ case 0xfe: // MRB = MRB - Rx * Ry (SSF)
+ case 0xff: // MRB = MRB - Rx * Ry (SSFR)
// TODO: track MRB?
REG_USED(desc, rx);
REG_USED(desc, ry);
MULT_FLAGS_MODIFIED(desc);
break;
-
- case 0x00: // Rn = SAT MRF (UI)
- case 0x01: // Rn = SAT MRF (SI)
- case 0x08: // Rn = SAT MRF (UF)
- case 0x09: // Rn = SAT MRF (SF)
+
+ case 0x00: // Rn = SAT MRF (UI)
+ case 0x01: // Rn = SAT MRF (SI)
+ case 0x08: // Rn = SAT MRF (UF)
+ case 0x09: // Rn = SAT MRF (SF)
// TODO: track MRF?
REG_MODIFIED(desc, rn);
MULT_FLAGS_MODIFIED(desc);
break;
- case 0x02: // Rn = SAT MRB (UI)
- case 0x03: // Rn = SAT MRB (SI)
- case 0x0a: // Rn = SAT MRB (UF)
- case 0x0b: // Rn = SAT MRB (SF)
+ case 0x02: // Rn = SAT MRB (UI)
+ case 0x03: // Rn = SAT MRB (SI)
+ case 0x0a: // Rn = SAT MRB (UF)
+ case 0x0b: // Rn = SAT MRB (SF)
// TODO: track MRB?
REG_MODIFIED(desc, rn);
MULT_FLAGS_MODIFIED(desc);
break;
- case 0x04: // MRF = SAT MRF (UI)
- case 0x05: // MRF = SAT MRF (SI)
- case 0x0c: // MRF = SAT MRF (UF)
- case 0x0d: // MRF = SAT MRF (SF)
+ case 0x04: // MRF = SAT MRF (UI)
+ case 0x05: // MRF = SAT MRF (SI)
+ case 0x0c: // MRF = SAT MRF (UF)
+ case 0x0d: // MRF = SAT MRF (SF)
// TODO: track MRF?
MULT_FLAGS_MODIFIED(desc);
break;
- case 0x06: // MRB = SAT MRB (UI)
- case 0x07: // MRB = SAT MRB (SI)
- case 0x0e: // MRB = SAT MRB (UF)
- case 0x0f: // MRB = SAT MRB (SF)
+ case 0x06: // MRB = SAT MRB (UI)
+ case 0x07: // MRB = SAT MRB (SI)
+ case 0x0e: // MRB = SAT MRB (UF)
+ case 0x0f: // MRB = SAT MRB (SF)
// TODO: track MRB?
MULT_FLAGS_MODIFIED(desc);
break;
- case 0x18: // Rn = RND MRF (U)
- case 0x19: // Rn = RND MRF (S)
+ case 0x18: // Rn = RND MRF (U)
+ case 0x19: // Rn = RND MRF (S)
REG_MODIFIED(desc, rn);
MULT_FLAGS_MODIFIED(desc);
break;
- case 0x1a: // Rn = RND MRB (U)
- case 0x1b: // Rn = RND MRB (S)
+ case 0x1a: // Rn = RND MRB (U)
+ case 0x1b: // Rn = RND MRB (S)
REG_MODIFIED(desc, rn);
MULT_FLAGS_MODIFIED(desc);
break;
- case 0x1c: // MRF = RND MRF (U)
- case 0x1d: // MRF = RND MRF (S)
+ case 0x1c: // MRF = RND MRF (U)
+ case 0x1d: // MRF = RND MRF (S)
MULT_FLAGS_MODIFIED(desc);
break;
- case 0x1e: // MRB = RND MRB (U)
- case 0x1f: // MRB = RND MRB (S)
+ case 0x1e: // MRB = RND MRB (U)
+ case 0x1f: // MRB = RND MRB (S)
MULT_FLAGS_MODIFIED(desc);
break;
- case 0x14: // MRF = 0
+ case 0x14: // MRF = 0
MULT_FLAGS_MODIFIED(desc);
break;
- case 0x16: // MRB = 0
+ case 0x16: // MRB = 0
MULT_FLAGS_MODIFIED(desc);
break;
- case 0x30: // Fn = Fx * Fy
+ case 0x30: // Fn = Fx * Fy
REG_USED(desc, rx);
REG_USED(desc, ry);
REG_MODIFIED(desc, rn);
@@ -1531,48 +1531,48 @@ bool sharc_frontend::describe_compute(opcode_desc &desc, UINT64 opcode)
break;
}
- case 2: // shifter operations
+ case 2: // shifter operations
{
switch (operation)
{
- case 0x00: // Rn = LSHIFT Rx BY Ry | <data8>
- case 0x04: // Rn = ASHIFT Rx BY Ry | <data8>
- case 0x08: // Rn = ROT Rx BY Ry | <data8>
- case 0xc4: // Rn = BCLR Rx BY Ry | <data8>
- case 0xc0: // Rn = BSET Rx BY Ry | <data8>
- case 0x44: // Rn = FDEP Rx BY Ry | <bit6>:<len6>
- case 0x4c: // Rn = FDEP Rx BY Ry | <bit6>:<len6> (SE)
- case 0x40: // Rn = FEXT Rx BY Ry | <bit6>:<len6>
- case 0x48: // Rn = FEXT Rx BY Ry | <bit6>:<len6> (SE)
+ case 0x00: // Rn = LSHIFT Rx BY Ry | <data8>
+ case 0x04: // Rn = ASHIFT Rx BY Ry | <data8>
+ case 0x08: // Rn = ROT Rx BY Ry | <data8>
+ case 0xc4: // Rn = BCLR Rx BY Ry | <data8>
+ case 0xc0: // Rn = BSET Rx BY Ry | <data8>
+ case 0x44: // Rn = FDEP Rx BY Ry | <bit6>:<len6>
+ case 0x4c: // Rn = FDEP Rx BY Ry | <bit6>:<len6> (SE)
+ case 0x40: // Rn = FEXT Rx BY Ry | <bit6>:<len6>
+ case 0x48: // Rn = FEXT Rx BY Ry | <bit6>:<len6> (SE)
REG_USED(desc, rx);
REG_USED(desc, ry);
REG_MODIFIED(desc, rn);
SHIFT_FLAGS_MODIFIED(desc);
break;
- case 0x20: // Rn = Rn OR LSHIFT Rx BY Ry | <data8>
- case 0x24: // Rn = Rn OR ASHIFT Rx BY Ry | <data8>
- case 0x64: // Rn = Rn OR FDEP Rx BY Ry | <bit6>:<len6>
- case 0x6c: // Rn = Rn OR FDEP Rx BY Ry | <bit6>:<len6> (SE)
+ case 0x20: // Rn = Rn OR LSHIFT Rx BY Ry | <data8>
+ case 0x24: // Rn = Rn OR ASHIFT Rx BY Ry | <data8>
+ case 0x64: // Rn = Rn OR FDEP Rx BY Ry | <bit6>:<len6>
+ case 0x6c: // Rn = Rn OR FDEP Rx BY Ry | <bit6>:<len6> (SE)
REG_USED(desc, rx);
REG_USED(desc, ry);
REG_USED(desc, rn);
REG_MODIFIED(desc, rn);
SHIFT_FLAGS_MODIFIED(desc);
break;
-
- case 0xcc: // BTST Rx BY Ry | <data8>
+
+ case 0xcc: // BTST Rx BY Ry | <data8>
REG_USED(desc, rx);
REG_USED(desc, ry);
SHIFT_FLAGS_MODIFIED(desc);
break;
-
- case 0x80: // Rn = EXP Rx
- case 0x84: // Rn = EXP Rx (EX)
- case 0x88: // Rn = LEFTZ Rx
- case 0x8c: // Rn = LEFTO Rx
- case 0x90: // Rn = FPACK Fx
- case 0x94: // Fn = FUNPACK Rx
+
+ case 0x80: // Rn = EXP Rx
+ case 0x84: // Rn = EXP Rx (EX)
+ case 0x88: // Rn = LEFTZ Rx
+ case 0x8c: // Rn = LEFTO Rx
+ case 0x90: // Rn = FPACK Fx
+ case 0x94: // Fn = FUNPACK Rx
REG_USED(desc, rx);
REG_MODIFIED(desc, rn);
SHIFT_FLAGS_MODIFIED(desc);
@@ -1657,34 +1657,34 @@ bool sharc_frontend::describe_ureg_access(opcode_desc &desc, int reg, UREG_ACCES
PM_B_MODIFIED(desc, reg & 7);
break;
- case 0x60: // FADDR
+ case 0x60: // FADDR
break;
- case 0x61: // DADDR
+ case 0x61: // DADDR
break;
- case 0x63: // PC
+ case 0x63: // PC
break;
- case 0x64: // PCSTK
+ case 0x64: // PCSTK
break;
- case 0x65: // PCSTKP
+ case 0x65: // PCSTKP
break;
- case 0x66: // LADDR
+ case 0x66: // LADDR
break;
- case 0x67: // CURLCNTR
+ case 0x67: // CURLCNTR
break;
- case 0x68: // LCNTR
+ case 0x68: // LCNTR
break;
- case 0x70: // USTAT1
+ case 0x70: // USTAT1
break;
- case 0x71: // USTAT2
+ case 0x71: // USTAT2
break;
- case 0x79: // IRPTL
+ case 0x79: // IRPTL
break;
- case 0x7a: // MODE1
+ case 0x7a: // MODE1
break;
- case 0x7b: // MODE2
+ case 0x7b: // MODE2
break;
- case 0x7c: // ASTAT
+ case 0x7c: // ASTAT
if (access == UREG_READ)
{
AZ_USED(desc);
@@ -1713,17 +1713,17 @@ bool sharc_frontend::describe_ureg_access(opcode_desc &desc, int reg, UREG_ACCES
}
break;
- case 0x7d: // IMASK
+ case 0x7d: // IMASK
break;
- case 0x7e: // STKY
+ case 0x7e: // STKY
break;
- case 0x7f: // IMASKP
+ case 0x7f: // IMASKP
break;
- case 0xdb: // PX
+ case 0xdb: // PX
break;
- case 0xdc: // PX1
+ case 0xdc: // PX1
break;
- case 0xdd: // PX2
+ case 0xdd: // PX2
break;
default:
@@ -1738,31 +1738,31 @@ bool sharc_frontend::describe_shiftop_imm(opcode_desc &desc, int shiftop, int rn
{
switch (shiftop)
{
- case 0x00: // LSHIFT Rx BY <data8>
- case 0x01: // ASHIFT Rx BY <data8>
- case 0x02: // ROT Rx BY <data8>
- case 0x10: // FEXT Rx BY <data8>
- case 0x11: // FDEP Rx BY <data8>
- case 0x12: // FEXT Rx BY <bit6>:<len6> (SE)
- case 0x13: // FDEP Rx BY <bit6>:<len6> (SE)
- case 0x30: // BSET Rx BY <data8>
- case 0x31: // BCLR Rx By <data8>
- case 0x32: // BTGL Rx BY <data8>
+ case 0x00: // LSHIFT Rx BY <data8>
+ case 0x01: // ASHIFT Rx BY <data8>
+ case 0x02: // ROT Rx BY <data8>
+ case 0x10: // FEXT Rx BY <data8>
+ case 0x11: // FDEP Rx BY <data8>
+ case 0x12: // FEXT Rx BY <bit6>:<len6> (SE)
+ case 0x13: // FDEP Rx BY <bit6>:<len6> (SE)
+ case 0x30: // BSET Rx BY <data8>
+ case 0x31: // BCLR Rx By <data8>
+ case 0x32: // BTGL Rx BY <data8>
REG_USED(desc, rx);
REG_MODIFIED(desc, rn);
SHIFT_FLAGS_MODIFIED(desc);
break;
- case 0x08: // Rn = Rn OR LSHIFT Rx BY <data8>
- case 0x19: // Rn = Rn OR FDEP Rx BY <bit6>:<len6>
- case 0x1b: // Rn = Rn OR FDEP Rx BY <bit6>:<len6> (SE)
+ case 0x08: // Rn = Rn OR LSHIFT Rx BY <data8>
+ case 0x19: // Rn = Rn OR FDEP Rx BY <bit6>:<len6>
+ case 0x1b: // Rn = Rn OR FDEP Rx BY <bit6>:<len6> (SE)
REG_USED(desc, rx);
REG_USED(desc, rn);
REG_MODIFIED(desc, rn);
SHIFT_FLAGS_MODIFIED(desc);
break;
- case 0x33: // BTST Rx BY <data8>
+ case 0x33: // BTST Rx BY <data8>
REG_USED(desc, rx);
SHIFT_FLAGS_MODIFIED(desc);
break;
@@ -1800,4 +1800,4 @@ void sharc_frontend::describe_if_condition(opcode_desc &desc, int condition)
case 0x18: SZ_USED(desc); break; /* NOT SZ */
case 0x1d: BTF_USED(desc); break; /* NOT TF */
}
-} \ No newline at end of file
+}
diff --git a/src/devices/cpu/sparc/mb86901.cpp b/src/devices/cpu/sparc/mb86901.cpp
index 0a1bf03938b..2bf8e1ba284 100644
--- a/src/devices/cpu/sparc/mb86901.cpp
+++ b/src/devices/cpu/sparc/mb86901.cpp
@@ -10,8 +10,8 @@
//
// To-Do:
// - Ops: FBFcc, LDF, STF
-// - Test: SPARCv8 ops are untested
-// - Test: Traps are untested
+// - Test: SPARCv8 ops are untested
+// - Test: Traps are untested
// - FPU support
// - Coprocessor support
//
@@ -155,17 +155,17 @@ void mb86901_device::device_start()
#endif
// register our state for the debugger
- state_add(STATE_GENPC, "GENPC", m_pc).noshow();
- state_add(STATE_GENFLAGS, "GENFLAGS", m_psr).callimport().callexport().formatstr("%6s").noshow();
- state_add(SPARC_PC, "PC", m_pc).formatstr("%08X");
- state_add(SPARC_NPC, "nPC", m_npc).formatstr("%08X");
- state_add(SPARC_PSR, "PSR", m_psr).formatstr("%08X");
- state_add(SPARC_WIM, "WIM", m_wim).formatstr("%08X");
- state_add(SPARC_TBR, "TBR", m_tbr).formatstr("%08X");
- state_add(SPARC_Y, "Y", m_y).formatstr("%08X");
- state_add(SPARC_ANNUL, "ANNUL", m_annul).formatstr("%01d");
- state_add(SPARC_ICC, "icc", m_icc).formatstr("%4s");
- state_add(SPARC_CWP, "CWP", m_cwp).formatstr("%2d");
+ state_add(STATE_GENPC, "GENPC", m_pc).noshow();
+ state_add(STATE_GENFLAGS, "GENFLAGS", m_psr).callimport().callexport().formatstr("%6s").noshow();
+ state_add(SPARC_PC, "PC", m_pc).formatstr("%08X");
+ state_add(SPARC_NPC, "nPC", m_npc).formatstr("%08X");
+ state_add(SPARC_PSR, "PSR", m_psr).formatstr("%08X");
+ state_add(SPARC_WIM, "WIM", m_wim).formatstr("%08X");
+ state_add(SPARC_TBR, "TBR", m_tbr).formatstr("%08X");
+ state_add(SPARC_Y, "Y", m_y).formatstr("%08X");
+ state_add(SPARC_ANNUL, "ANNUL", m_annul).formatstr("%01d");
+ state_add(SPARC_ICC, "icc", m_icc).formatstr("%4s");
+ state_add(SPARC_CWP, "CWP", m_cwp).formatstr("%2d");
char regname[3] = "g0";
for (int i = 0; i < 8; i++)
{
@@ -192,12 +192,12 @@ void mb86901_device::device_start()
state_add(SPARC_I0 + i, regname, m_dbgregs[16+i]).formatstr("%08X");
}
- state_add(SPARC_EC, "EC", m_ec).formatstr("%1d");
- state_add(SPARC_EF, "EF", m_ef).formatstr("%1d");
- state_add(SPARC_ET, "ET", m_et).formatstr("%1d");
- state_add(SPARC_PIL, "PIL", m_pil).formatstr("%2d");
- state_add(SPARC_S, "S", m_s).formatstr("%1d");
- state_add(SPARC_PS, "PS", m_ps).formatstr("%1d");
+ state_add(SPARC_EC, "EC", m_ec).formatstr("%1d");
+ state_add(SPARC_EF, "EF", m_ef).formatstr("%1d");
+ state_add(SPARC_ET, "ET", m_et).formatstr("%1d");
+ state_add(SPARC_PIL, "PIL", m_pil).formatstr("%2d");
+ state_add(SPARC_S, "S", m_s).formatstr("%1d");
+ state_add(SPARC_PS, "PS", m_ps).formatstr("%1d");
char rname[5];
for (int i = 0; i < 120; i++)
@@ -415,13 +415,13 @@ void mb86901_device::state_string_export(const device_state_entry &entry, std::s
case SPARC_ICC:
str = string_format("%c%c%c%c", ICC_N_SET ? 'n' : ' ', ICC_Z_SET ? 'z' : ' ', ICC_V_SET ? 'v' : ' ', ICC_C_SET ? 'c' : ' ');
break;
- case SPARC_O0: case SPARC_O1: case SPARC_O2: case SPARC_O3: case SPARC_O4: case SPARC_O5: case SPARC_O6: case SPARC_O7:
+ case SPARC_O0: case SPARC_O1: case SPARC_O2: case SPARC_O3: case SPARC_O4: case SPARC_O5: case SPARC_O6: case SPARC_O7:
str = string_format("%08X", m_dbgregs[entry.index() - SPARC_O0]);
break;
- case SPARC_L0: case SPARC_L1: case SPARC_L2: case SPARC_L3: case SPARC_L4: case SPARC_L5: case SPARC_L6: case SPARC_L7:
+ case SPARC_L0: case SPARC_L1: case SPARC_L2: case SPARC_L3: case SPARC_L4: case SPARC_L5: case SPARC_L6: case SPARC_L7:
str = string_format("%08X", m_dbgregs[8 + (entry.index() - SPARC_L0)]);
break;
- case SPARC_I0: case SPARC_I1: case SPARC_I2: case SPARC_I3: case SPARC_I4: case SPARC_I5: case SPARC_I6: case SPARC_I7:
+ case SPARC_I0: case SPARC_I1: case SPARC_I2: case SPARC_I3: case SPARC_I4: case SPARC_I5: case SPARC_I6: case SPARC_I7:
str = string_format("%08X", m_dbgregs[16 + (entry.index() - SPARC_I0)]);
break;
}
@@ -524,21 +524,21 @@ void mb86901_device::execute_add(UINT32 op)
operand2 := if (i = 0) then r[rs2] else sign_extend(simm13);
if (ADD or ADDcc) then
- result <- r[rs1] + operand2;
+ result <- r[rs1] + operand2;
else if (ADDX or ADDXcc) then
- result <= r[rs1] + operand2 + C;
+ result <= r[rs1] + operand2 + C;
next;
if (rd != 0) then
- r[rd] <- result;
+ r[rd] <- result;
if (ADDcc or ADDXcc) then (
- N <- result<31>;
- Z <- if (result = 0) then 1 else 0;
- V <- (r[rs1]<31> and operand2<31> and (not result<31>)) or
- ((not r[rs1]<31>) and (not operand2<31>) and result<31>);
- C <- (r[rs1]<31> and operand2<31>) or
- ((not result<31>) and (r[rs1]<31> or operand2<31>))
+ N <- result<31>;
+ Z <- if (result = 0) then 1 else 0;
+ V <- (r[rs1]<31> and operand2<31> and (not result<31>)) or
+ ((not r[rs1]<31>) and (not operand2<31>) and result<31>);
+ C <- (r[rs1]<31> and operand2<31>) or
+ ((not result<31>) and (r[rs1]<31> or operand2<31>))
);
*/
UINT32 operand2 = USEIMM ? SIMM13 : RS2REG;
@@ -559,9 +559,9 @@ void mb86901_device::execute_add(UINT32 op)
PSR |= (BIT31(result)) ? PSR_N_MASK : 0;
PSR |= (result == 0) ? PSR_Z_MASK : 0;
PSR |= ((BIT31(RS1REG) && BIT31(operand2) && !BIT31(result)) ||
- (!BIT31(RS1REG) && !BIT31(operand2) && BIT31(result))) ? PSR_V_MASK : 0;
+ (!BIT31(RS1REG) && !BIT31(operand2) && BIT31(result))) ? PSR_V_MASK : 0;
PSR |= ((BIT31(RS1REG) && BIT31(operand2)) ||
- (!BIT31(result) && (BIT31(RS1REG) || BIT31(operand2)))) ? PSR_C_MASK : 0;
+ (!BIT31(result) && (BIT31(RS1REG) || BIT31(operand2)))) ? PSR_C_MASK : 0;
}
}
@@ -586,16 +586,16 @@ void mb86901_device::execute_taddcc(UINT32 op)
next;
if (TADDccTV and (temp_V = 1)) then (
- trap <- 1;
- tag_overflow <- 1
+ trap <- 1;
+ tag_overflow <- 1
) else (
- N <- result<31>;
- Z <- if (result = 0) then 1 else 0;
- V <- temp_V;
- C <- (r[rs1]<31> and operand2<31>) or
- ((not result<31>) and (r[rs1]<31> or operand2<31>));
- if (rd != 0) then
- r[rd] <- result;
+ N <- result<31>;
+ Z <- if (result = 0) then 1 else 0;
+ V <- temp_V;
+ C <- (r[rs1]<31> and operand2<31>) or
+ ((not result<31>) and (r[rs1]<31> or operand2<31>));
+ if (rd != 0) then
+ r[rd] <- result;
);
*/
UINT32 operand2 = USEIMM ? SIMM13 : RS2REG;
@@ -603,8 +603,8 @@ void mb86901_device::execute_taddcc(UINT32 op)
UINT32 result = RS1REG + operand2;
bool temp_v = (BIT31(RS1REG) && BIT31(operand2) && !BIT31(result)) ||
- (!BIT31(RS1REG) && !BIT31(operand2) && BIT31(result)) ||
- ((RS1REG & 3) != 0 || (RS1REG & 3) != 0) ? true : false;
+ (!BIT31(RS1REG) && !BIT31(operand2) && BIT31(result)) ||
+ ((RS1REG & 3) != 0 || (RS1REG & 3) != 0) ? true : false;
if (TADDCCTV && temp_v)
{
@@ -618,7 +618,7 @@ void mb86901_device::execute_taddcc(UINT32 op)
PSR |= (result == 0) ? PSR_Z_MASK : 0;
PSR |= temp_v ? PSR_V_MASK : 0;
PSR |= ((BIT31(RS1REG) && BIT31(operand2)) ||
- (!BIT31(result) && (BIT31(RS1REG) || BIT31(operand2)))) ? PSR_C_MASK : 0;
+ (!BIT31(result) && (BIT31(RS1REG) || BIT31(operand2)))) ? PSR_C_MASK : 0;
if (RD != 0)
RDREG = result;
@@ -638,21 +638,21 @@ void mb86901_device::execute_sub(UINT32 op)
operand2 := if (i = 0) then r[rs2] else sign_extend(simm13);
if (SUB or SUBcc) then
- result <- r[rs1] - operand2;
+ result <- r[rs1] - operand2;
else if (SUBX or SUBXcc) then
- result <= r[rs1] - operand2 - C;
+ result <= r[rs1] - operand2 - C;
next;
if (rd != 0) then
- r[rd] <- result;
+ r[rd] <- result;
if (SUBcc or SUBXcc) then (
- N <- result<31>;
- Z <- if (result = 0) then 1 else 0;
- V <- (r[rs1]<31> and (not operand2<31>) and (not result<31>)) or
- ((not r[rs1]<31>) and operand2<31> and result<31>);
- C <- ((not r[rs1]<31>) and operand2<31>) or
- (result<31> and ((not r[rs1]<31>) or operand2<31>))
+ N <- result<31>;
+ Z <- if (result = 0) then 1 else 0;
+ V <- (r[rs1]<31> and (not operand2<31>) and (not result<31>)) or
+ ((not r[rs1]<31>) and operand2<31> and result<31>);
+ C <- ((not r[rs1]<31>) and operand2<31>) or
+ (result<31> and ((not r[rs1]<31>) or operand2<31>))
);
*/
UINT32 operand2 = USEIMM ? SIMM13 : RS2REG;
@@ -672,9 +672,9 @@ void mb86901_device::execute_sub(UINT32 op)
PSR |= (BIT31(result)) ? PSR_N_MASK : 0;
PSR |= (result == 0) ? PSR_Z_MASK : 0;
PSR |= ((BIT31(RS1REG) && !BIT31(operand2) && !BIT31(result)) ||
- (!BIT31(RS1REG) && BIT31(operand2) && BIT31(result))) ? PSR_V_MASK : 0;
+ (!BIT31(RS1REG) && BIT31(operand2) && BIT31(result))) ? PSR_V_MASK : 0;
PSR |= ((!BIT31(RS1REG) && BIT31(operand2)) ||
- (BIT31(result) && (!BIT31(RS1REG) || BIT31(operand2)))) ? PSR_C_MASK : 0;
+ (BIT31(result) && (!BIT31(RS1REG) || BIT31(operand2)))) ? PSR_C_MASK : 0;
}
}
@@ -699,16 +699,16 @@ void mb86901_device::execute_tsubcc(UINT32 op)
next;
if (TSUBccTV and (temp_V = 1)) then (
- trap <- 1;
- tag_overflow <- 1
+ trap <- 1;
+ tag_overflow <- 1
) else (
- N <- result<31>;
- Z <- if (result = 0) then 1 else 0;
- V <- temp_V;
- C <- ((not r[rs1]<31>) and operand2<31>) or
- (result<31> and ((not r[rs1]<31>) or operand2<31>));
- if (rd != 0) then
- r[rd] <- result;
+ N <- result<31>;
+ Z <- if (result = 0) then 1 else 0;
+ V <- temp_V;
+ C <- ((not r[rs1]<31>) and operand2<31>) or
+ (result<31> and ((not r[rs1]<31>) or operand2<31>));
+ if (rd != 0) then
+ r[rd] <- result;
);
*/
@@ -717,8 +717,8 @@ void mb86901_device::execute_tsubcc(UINT32 op)
UINT32 result = RS1REG - operand2;
bool temp_v = (BIT31(RS1REG) && !BIT31(operand2) && !BIT31(result)) ||
- (!BIT31(RS1REG) && BIT31(operand2) && BIT31(result)) ||
- ((RS1REG & 3) != 0 || (RS1REG & 3) != 0) ? true : false;
+ (!BIT31(RS1REG) && BIT31(operand2) && BIT31(result)) ||
+ ((RS1REG & 3) != 0 || (RS1REG & 3) != 0) ? true : false;
if (TSUBCCTV && temp_v)
{
@@ -732,7 +732,7 @@ void mb86901_device::execute_tsubcc(UINT32 op)
PSR |= (result == 0) ? PSR_Z_MASK : 0;
PSR |= temp_v ? PSR_V_MASK : 0;
PSR |= ((!BIT31(RS1REG) && BIT31(operand2)) ||
- (BIT31(result) && (!BIT31(RS1REG) || BIT31(operand2)))) ? PSR_C_MASK : 0;
+ (BIT31(result) && (!BIT31(RS1REG) || BIT31(operand2)))) ? PSR_C_MASK : 0;
if (RD != 0)
RDREG = result;
@@ -762,10 +762,10 @@ void mb86901_device::execute_logical(UINT32 op)
if (rd != 0) then r[rd] <- result;
if (ANDcccc or ANDNcc or ORcc or ORNcc or XORcc or XNORcc) then (
- N <- result<31>;
- Z <- if (result = 0) then 1 else 0;
- V <- 0
- C <- 0
+ N <- result<31>;
+ Z <- if (result = 0) then 1 else 0;
+ V <- 0
+ C <- 0
);
*/
@@ -824,11 +824,11 @@ void mb86901_device::execute_shift(UINT32 op)
shift_count := if (i = 0) then r[rs2]<4:0> else shcnt;
if (SLL and (rd != 0) ) then
- r[rd] <- shift_left_logical(r[rs1], shift_count)
+ r[rd] <- shift_left_logical(r[rs1], shift_count)
else if (SRL and (rd != 0) ) then
- r[rd] <- shift_right_logical(r[rs1], shift_count)
+ r[rd] <- shift_right_logical(r[rs1], shift_count)
else if (SRA and (rd != 0) ) then
- r[rd] <- shift_right_arithmetic(r[rs1], shift_count)
+ r[rd] <- shift_right_arithmetic(r[rs1], shift_count)
*/
UINT32 shift_count = USEIMM ? (SIMM13 & 31) : (RS2REG & 31);
@@ -852,8 +852,8 @@ void mb86901_device::execute_mulscc(UINT32 op)
operand1 := (N xor V) [] (r[rs1]<31:1>);
operand2 := (
- if (Y<0> = 0) then 0
- else if (i = 0) then r[rs2] else sign_extend(simm13)
+ if (Y<0> = 0) then 0
+ else if (i = 0) then r[rs2] else sign_extend(simm13)
);
result <- operand1 + operand2;
@@ -861,7 +861,7 @@ void mb86901_device::execute_mulscc(UINT32 op)
next;
if (rd != 0) then (
- r[rd] <- result;
+ r[rd] <- result;
)
N <- result<31>;
Z <- if (result = 0) then 1 else 0;
@@ -884,9 +884,9 @@ void mb86901_device::execute_mulscc(UINT32 op)
PSR |= (BIT31(result)) ? PSR_N_MASK : 0;
PSR |= (result == 0) ? PSR_Z_MASK : 0;
PSR |= ((BIT31(operand1) && BIT31(operand2) && !BIT31(result)) ||
- (!BIT31(operand1) && !BIT31(operand2) && BIT31(result))) ? PSR_V_MASK : 0;
+ (!BIT31(operand1) && !BIT31(operand2) && BIT31(result))) ? PSR_V_MASK : 0;
PSR |= ((BIT31(operand1) && BIT31(operand2)) ||
- (!BIT31(result) && (BIT31(operand1) || BIT31(operand2)))) ? PSR_C_MASK : 0;
+ (!BIT31(result) && (BIT31(operand1) || BIT31(operand2)))) ? PSR_C_MASK : 0;
}
@@ -901,17 +901,17 @@ void mb86901_device::execute_rdsr(UINT32 op)
if ((RDPSR or RDWIM or RDBTR
or (RDASR and (privileged_ASR(rs1) = 1))) and (S = 0)) then (
- trap <- 1;
- privileged_instruction <- 1;
+ trap <- 1;
+ privileged_instruction <- 1;
else if (illegal_instruction_ASR(rs1) = 1) then (
- trap <- 1;
- illegal_instruction <- 1
+ trap <- 1;
+ illegal_instruction <- 1
else if (rd != 0) then (
- if (RDY) then r[rd] <- Y
- else if (RDASR) then r[rd] <- ASR[rs1]
- else if (RDPSR) then r[rd] <- PSR
- else if (RDWIM) then r[rd] <- WIM
- else if (RDTBR) then r[rd] <- TBR;
+ if (RDY) then r[rd] <- Y
+ else if (RDASR) then r[rd] <- ASR[rs1]
+ else if (RDPSR) then r[rd] <- PSR
+ else if (RDWIM) then r[rd] <- WIM
+ else if (RDTBR) then r[rd] <- TBR;
);
*/
@@ -957,41 +957,41 @@ void mb86901_device::execute_wrsr(UINT32 op)
result := r[rs1] xor operand2;
if (WRY) then (
- Y'''' <- result
+ Y'''' <- result
) else if (WRASR) then (
- if ( (privileged_ASR(rd) = 1) and (S = 0) ) then (
- trap <- 1;
- privileged_instruction <- 1
- ) else if (illegal_instruction_ASR(rd) = 1) then (
- trap <- 1;
- illegal_instruction <- 1
- ) else (
- ASR[rd]'''' <- result
- )
+ if ( (privileged_ASR(rd) = 1) and (S = 0) ) then (
+ trap <- 1;
+ privileged_instruction <- 1
+ ) else if (illegal_instruction_ASR(rd) = 1) then (
+ trap <- 1;
+ illegal_instruction <- 1
+ ) else (
+ ASR[rd]'''' <- result
+ )
) else if (WRPSR) then (
- if (S = 0) then (
- trap <- 1;
- privileged_instruction <- 1
- ) else if (result<4:0> >= NWINDOWS) then (
- trap <- 1;
- illegal_instruction <- 1
- ) else (
- PSR'''' <- result
- )
+ if (S = 0) then (
+ trap <- 1;
+ privileged_instruction <- 1
+ ) else if (result<4:0> >= NWINDOWS) then (
+ trap <- 1;
+ illegal_instruction <- 1
+ ) else (
+ PSR'''' <- result
+ )
) else if (WRWIM) then (
- if (S = 0) then (
- trap <- 1;
- privileged_instruction <- 1
- ) else (
- WIM'''' <- result
- )
+ if (S = 0) then (
+ trap <- 1;
+ privileged_instruction <- 1
+ ) else (
+ WIM'''' <- result
+ )
) else if (WRBTR) then (
- if (S = 0) then (
- trap <- 1;
- privileged_instruction <- 1
- ) else (
- WIM'''' <- result
- )
+ if (S = 0) then (
+ trap <- 1;
+ privileged_instruction <- 1
+ ) else (
+ WIM'''' <- result
+ )
);
*/
UINT32 operand2 = USEIMM ? SIMM13 : RS2REG;
@@ -1009,8 +1009,8 @@ void mb86901_device::execute_wrsr(UINT32 op)
m_trap = 1;
m_privileged_instruction = 1;
}
- else if (m_illegal_instruction_asr[RD])
- {
+ else if (m_illegal_instruction_asr[RD])
+ {
m_trap = 1;
m_illegal_instruction = 1;
}
@@ -1043,8 +1043,8 @@ void mb86901_device::execute_wrsr(UINT32 op)
m_trap = 1;
m_privileged_instruction = 1;
}
- else
- {
+ else
+ {
WIM = result & 0x7f;
}
}
@@ -1055,8 +1055,8 @@ void mb86901_device::execute_wrsr(UINT32 op)
m_trap = 1;
m_privileged_instruction = 1;
}
- else
- {
+ else
+ {
TBR = result & 0xfffff000;
}
}
@@ -1076,33 +1076,33 @@ void mb86901_device::execute_rett(UINT32 op)
address <- r[rs1] + (if (i = 0) then r[rs2] else sign_extend(simm13));
next;
if (ET = 1) then (
- trap <- 1;
- if (S = 0) then privileged_instruction <- 1
- else if (S != 0) then illegal_instruction <- 1
+ trap <- 1;
+ if (S = 0) then privileged_instruction <- 1
+ else if (S != 0) then illegal_instruction <- 1
) else if (S = 0) then (
- trap <- 1;
- privileged_instruction <- 1
- tt <- 00000011; { trap type for privileged_instruction }
- execute_mode <- 0;
- error_mode = 1
+ trap <- 1;
+ privileged_instruction <- 1
+ tt <- 00000011; { trap type for privileged_instruction }
+ execute_mode <- 0;
+ error_mode = 1
) else if ((WIM and (1 << new_cwp)) != 0) then (
- trap <- 1;
- window_underflow <- 1;
- tt <- 00000110; { trap type for window_underflow }
- execute_mode = 0;
- error_mode = 1
+ trap <- 1;
+ window_underflow <- 1;
+ tt <- 00000110; { trap type for window_underflow }
+ execute_mode = 0;
+ error_mode = 1
) else if (address<1:0> != 0) then (
- trap = 1;
- mem_address_not_aligned = 1;
- tt = 7; { trap type for mem_address_not_aligned }
- execute_mode = 0;
- error_mode = 1
+ trap = 1;
+ mem_address_not_aligned = 1;
+ tt = 7; { trap type for mem_address_not_aligned }
+ execute_mode = 0;
+ error_mode = 1
) else (
- ET <- 1;
- PC <- nPC;
- nPC <- address;
- CWP <- new_cwp;
- S <- PS
+ ET <- 1;
+ PC <- nPC;
+ nPC <- address;
+ CWP <- new_cwp;
+ S <- PS
)
*/
@@ -1166,29 +1166,29 @@ void mb86901_device::execute_saverestore(UINT32 op)
operand2 := if (i = 0) then r[rs2] else sign_extend(simm13);
if (SAVE) then (
- new_cwp <- (CWP - 1) modulo NWINDOWS;
- next;
- if ((WIM and (1 << new_cwp)) != 0) then (
- trap <- 1;
- window_overflow <- 1
- ) else (
- result <- r[rs1] + operand2; { operands from old window }
- CWP <- new_cwp
- )
+ new_cwp <- (CWP - 1) modulo NWINDOWS;
+ next;
+ if ((WIM and (1 << new_cwp)) != 0) then (
+ trap <- 1;
+ window_overflow <- 1
+ ) else (
+ result <- r[rs1] + operand2; { operands from old window }
+ CWP <- new_cwp
+ )
) else if (RESTORE) then (
- new_cwp <- (CWP + 1) modulo NWINDOWS;
- next;
- if ((WIM and (1 << new_cwp)) != 0) then (
- trap <- 1;
- window_overflow <- 1
- ) else (
- result <- r[rs1] + operand2; { operands from old window }
- CWP <- new_cwp
- )
+ new_cwp <- (CWP + 1) modulo NWINDOWS;
+ next;
+ if ((WIM and (1 << new_cwp)) != 0) then (
+ trap <- 1;
+ window_overflow <- 1
+ ) else (
+ result <- r[rs1] + operand2; { operands from old window }
+ CWP <- new_cwp
+ )
);
next;
if ((trap = 0) and (rd != 0)) then
- r[rd] <- result { destination in new window }
+ r[rd] <- result { destination in new window }
*/
UINT32 rs1 = RS1REG;
@@ -1243,12 +1243,12 @@ void mb86901_device::execute_jmpl(UINT32 op)
jump_address <- r[rs1] + (if (i = 0) then r[rs2] else sign_extend(simm13));
next;
if (jump_address<1:0> != 0) then (
- trap <- 1;
- mem_address_not_aligned <- 1
+ trap <- 1;
+ mem_address_not_aligned <- 1
) else (
- if (rd != 0) then r[rd] <- PC;
- PC <- nPC;
- nPC <- jump_address
+ if (rd != 0) then r[rd] <- PC;
+ PC <- nPC;
+ nPC <- jump_address
)
*/
@@ -1417,119 +1417,119 @@ void mb86901_device::execute_store(UINT32 op)
/* The SPARC Instruction Manual: Version 8, page 165, "Appendix C - ISP Descriptions - Store Instructions" (SPARCv8.pdf, pg. 162)
if ( (S = 0) and (STDA or STA or STHA or STBA or STDFQ or STDCQ) ) then (
- trap <- 1;
- privileged_instruction <- 1
+ trap <- 1;
+ privileged_instruction <- 1
) else if ((i = 1) and (STDA or STA or STHA or STBA)) then (
- trap <- 1;
- illegal_instruction <- 1
+ trap <- 1;
+ illegal_instruction <- 1
);
next;
if (trap = 0) then (
- if (STD or ST or STH or STB or STF or STDF or STFSR or STDFQ or STCSR or STC or STDC or STDCQ) then (
- address <- r[rs1] + (if (i = 0) then r[rs2] else sign_extend(simm13));
- addr_space <- (if (S = 0) then 10 else 11)
- ) else if (STDA or STA or STHA or STBA) then (
- address <- r[rs1] + r[rs2];
- addr_space <- asi
- );
- if ((STF or STDF or STFSR or STDFQ) and
- ((EF = 0) or (bp_FPU_present = 0)) ) then (
- trap <- 1;
- fp_disabled <- 1;
- );
- if ((STC or STDC or STCSR or STDCQ) and
- ((EC = 0) or (bp_CP_present = 0)) ) then (
- trap <- 1;
- cp_disabled <- 1;
- )
+ if (STD or ST or STH or STB or STF or STDF or STFSR or STDFQ or STCSR or STC or STDC or STDCQ) then (
+ address <- r[rs1] + (if (i = 0) then r[rs2] else sign_extend(simm13));
+ addr_space <- (if (S = 0) then 10 else 11)
+ ) else if (STDA or STA or STHA or STBA) then (
+ address <- r[rs1] + r[rs2];
+ addr_space <- asi
+ );
+ if ((STF or STDF or STFSR or STDFQ) and
+ ((EF = 0) or (bp_FPU_present = 0)) ) then (
+ trap <- 1;
+ fp_disabled <- 1;
+ );
+ if ((STC or STDC or STCSR or STDCQ) and
+ ((EC = 0) or (bp_CP_present = 0)) ) then (
+ trap <- 1;
+ cp_disabled <- 1;
+ )
);
next;
if (trap = 0) then (
- if ((STH or STHA) and (address<0> != 0)) then (
- trap <- 1;
- mem_address_not_aligned <- 1
- ) else if ((ST or STA or STF or STFSR or STC or STCSR) and (address<1:0> != 0)) then (
- trap <- 1;
- mem_address_not_aligned <- 1
- ) else if ((STD or STDA or STDF or STDFQ or STDC or STDCQ) and (address<2:0> != 0)) then (
- trap <- 1;
- mem_address_not_aligned <- 1
- ) else (
- if (STDFQ and ((implementation has no floating-point queue) or (FSR.qne = 0))) then (
- trap <- 1;
- fp_exception <- 1;
- ftt <- sequence_error;
- );
- if (STDCQ and ((implementation has no coprocessor queue)) then (
- trap <- 1;
- cp_exception <- 1;
- { possibly additional implementation-dependent actions }
- );
- if (STDF and (rd<0> != 0)) then (
- trap <- 1;
- fp_exception <- 1;
- ftt <- invalid_fp_register;
- )
- )
+ if ((STH or STHA) and (address<0> != 0)) then (
+ trap <- 1;
+ mem_address_not_aligned <- 1
+ ) else if ((ST or STA or STF or STFSR or STC or STCSR) and (address<1:0> != 0)) then (
+ trap <- 1;
+ mem_address_not_aligned <- 1
+ ) else if ((STD or STDA or STDF or STDFQ or STDC or STDCQ) and (address<2:0> != 0)) then (
+ trap <- 1;
+ mem_address_not_aligned <- 1
+ ) else (
+ if (STDFQ and ((implementation has no floating-point queue) or (FSR.qne = 0))) then (
+ trap <- 1;
+ fp_exception <- 1;
+ ftt <- sequence_error;
+ );
+ if (STDCQ and ((implementation has no coprocessor queue)) then (
+ trap <- 1;
+ cp_exception <- 1;
+ { possibly additional implementation-dependent actions }
+ );
+ if (STDF and (rd<0> != 0)) then (
+ trap <- 1;
+ fp_exception <- 1;
+ ftt <- invalid_fp_register;
+ )
+ )
);
next;
if (trap = 0) then (
- if (STF) then ( byte_mask <- 1111; data0 <- f[rd] )
- else if (STC) then ( byte_mask <- 1111; data0 <- implementation_dependent_value )
- else if (STDF) then ( byte_mask <- 1111; data0 <- f[rd & 0x1e] )
- else if (STDC) then ( byte_mask <- 1111; data0 <- implementation_dependent_value )
- else if (STD or STDA) then ( byte_mask <- 1111; data0 <- r[rd & 0x1e] )
- else if (STDFQ) then ( byte_mask <- 1111; data0 <- implementation_dependent_value )
- else if (STDCQ) then ( byte_mask <- 1111; data0 <- implementation_dependent_value )
- else if (STFSR) then (
- while ((FSR.qne = 1) and (trap = 0)) (
- // wait for pending floating-point instructions to complete
- )
- next;
- byte_mask <- 1111; data0 <- FSR
- ) else if (STCSR) then (
- { implementation-dependent actions }
- byte_mask <- 1111; data0 <- CSR
- ) else if (ST or STA) then ( byte_mask <- 1111; data0 = r[rd] )
- else if (STH or STHA) then (
- if (address<1:0> = 0) then (
- byte_mask <- 1100; data0 <- shift_left_logical(r[rd], 16) )
- else if (address<1:0> = 2) then (
- byte_mask <- 0011; data0 <- r[rd] )
- ) else if (STB or STBA) then (
- if (address<1:0> = 0) then (
- byte_mask <- 1000; data0 <- shift_left_logical(r[rd], 24) )
- ) else if (address<1:0> = 1) then (
- byte_mask <- 0100; data0 <- shift_left_logical(r[rd], 16) )
- ) else if (address<1:0> = 2) then (
- byte_mask <- 0010; data0 <- shift_left_logical(r[rd], 8) )
- ) else if (address<1:0> = 3) then (
- byte_mask <- 0001; data0 <- r[rd] )
- )
- );
+ if (STF) then ( byte_mask <- 1111; data0 <- f[rd] )
+ else if (STC) then ( byte_mask <- 1111; data0 <- implementation_dependent_value )
+ else if (STDF) then ( byte_mask <- 1111; data0 <- f[rd & 0x1e] )
+ else if (STDC) then ( byte_mask <- 1111; data0 <- implementation_dependent_value )
+ else if (STD or STDA) then ( byte_mask <- 1111; data0 <- r[rd & 0x1e] )
+ else if (STDFQ) then ( byte_mask <- 1111; data0 <- implementation_dependent_value )
+ else if (STDCQ) then ( byte_mask <- 1111; data0 <- implementation_dependent_value )
+ else if (STFSR) then (
+ while ((FSR.qne = 1) and (trap = 0)) (
+ // wait for pending floating-point instructions to complete
+ )
+ next;
+ byte_mask <- 1111; data0 <- FSR
+ ) else if (STCSR) then (
+ { implementation-dependent actions }
+ byte_mask <- 1111; data0 <- CSR
+ ) else if (ST or STA) then ( byte_mask <- 1111; data0 = r[rd] )
+ else if (STH or STHA) then (
+ if (address<1:0> = 0) then (
+ byte_mask <- 1100; data0 <- shift_left_logical(r[rd], 16) )
+ else if (address<1:0> = 2) then (
+ byte_mask <- 0011; data0 <- r[rd] )
+ ) else if (STB or STBA) then (
+ if (address<1:0> = 0) then (
+ byte_mask <- 1000; data0 <- shift_left_logical(r[rd], 24) )
+ ) else if (address<1:0> = 1) then (
+ byte_mask <- 0100; data0 <- shift_left_logical(r[rd], 16) )
+ ) else if (address<1:0> = 2) then (
+ byte_mask <- 0010; data0 <- shift_left_logical(r[rd], 8) )
+ ) else if (address<1:0> = 3) then (
+ byte_mask <- 0001; data0 <- r[rd] )
+ )
+ );
);
next;
if (trap = 0) then (
- MAE <- memory_write(addr_space, address, byte_mask, data1);
- next;
- if (MAE = 1) then (
- trap <- 1;
- data_access_exception <- 1
- )
+ MAE <- memory_write(addr_space, address, byte_mask, data1);
+ next;
+ if (MAE = 1) then (
+ trap <- 1;
+ data_access_exception <- 1
+ )
);
if ((trap = 0) and (STD or STDA or STDF or STDC or STDFQ or STDCQ)) then (
- if (STD or STDA) then ( data1 <- r[rd or 00001] )
- else if (STDF) then ( data1 <- f[rd or 00001] )
- else if (STDC) then ( data1 <- implementation_dependent_value }
- else if (STDFQ) then ( data1 <- implementation_dependent_value }
- else if (STDCQ) then ( data1 <- implementation_dependent_value }
- next;
- MAE <- memory_write(addr_space, address + 4, 1111, data1);
- next;
- if (MAE = 1) then ( { MAE = 1 only due to a "non-resumable machine-check error" }
- trap <- 1;
- data_access_exception <- 1
- )
+ if (STD or STDA) then ( data1 <- r[rd or 00001] )
+ else if (STDF) then ( data1 <- f[rd or 00001] )
+ else if (STDC) then ( data1 <- implementation_dependent_value }
+ else if (STDFQ) then ( data1 <- implementation_dependent_value }
+ else if (STDCQ) then ( data1 <- implementation_dependent_value }
+ next;
+ MAE <- memory_write(addr_space, address + 4, 1111, data1);
+ next;
+ if (MAE = 1) then ( { MAE = 1 only due to a "non-resumable machine-check error" }
+ trap <- 1;
+ data_access_exception <- 1
+ )
);
*/
@@ -1760,100 +1760,100 @@ void mb86901_device::execute_load(UINT32 op)
/* The SPARC Instruction Manual: Version 8, page 163, "Appendix C - ISP Descriptions - C.9. Instruction Defintions - Load Instructions" (SPARCv8.pdf, pg. 160)
if (LDD or LD or LDSH or LDUH or LDSB or LDUB or LDDF or LDF or LDFSR or LDDC or LDC or LDCSR) then (
- address <- r[rs1] + (if (i = 0) then r[rs2] else sign_extend(simm13));
- addr_space <- (if (S = 0) then 10 else 11)
+ address <- r[rs1] + (if (i = 0) then r[rs2] else sign_extend(simm13));
+ addr_space <- (if (S = 0) then 10 else 11)
) else if (LDDA or LDA or LDSHA or LDUHA or LDSBA or LDUBA) then (
- if (S = 0) then (
- trap <- 1;
- privileged_instruction <- 1
- ) else if (i = 1) then (
- trap <- 1;
- illegal_instruction <- 1
- ) else (
- address <- r[rs1] + r[rs2];
- addr_space <- asi
- )
+ if (S = 0) then (
+ trap <- 1;
+ privileged_instruction <- 1
+ ) else if (i = 1) then (
+ trap <- 1;
+ illegal_instruction <- 1
+ ) else (
+ address <- r[rs1] + r[rs2];
+ addr_space <- asi
+ )
)
next;
if (trap = 0) then (
- if ( (LDF or LDDF or LDFSR) and ((EF = 0) or (bp_FPU_present = 0)) then (
- trap <- 1;
- fp_disabled <- 1
- ) else if ( (LDC or LDDC or LDCSR) and ((EC = 0) or (bp_CP_present = 0)) then (
- trap <- 1;
- cp_disabled <- 1
- ) else if ( ( (LDD or LDDA or LDDF or LDDC) and (address<2:0> != 0)) or
- ((LD or LDA or LDF or LDFSR or LDC or LDCSR) and (address<1:0> != 0)) or
- ((LDSH or LDSHA or LDUH or LDUHA) and address<0> != 0) ) then (
- trap <- 1;
- mem_address_not_aligned <- 1
- ) else if (LDDF and (rd<0> != 0)) then (
- trap <- 1;
- fp_exception <- 1;
- ftt <- invalid_fpr_register
- ) else if ((LDF or LDDF or LDFSR) and (an FPU sequence error is detected)) then (
- trap <- 1;
- fp_exception <- 1;
- ftt <- sequence_error
- ) else if ((LDC or LDDC or LDCSR) and (a CP sequence error is detected)) then (
- trap <- 1;
- cp_exception <- 1;
- { possibly additional implementation-dependent actions }
- )
+ if ( (LDF or LDDF or LDFSR) and ((EF = 0) or (bp_FPU_present = 0)) then (
+ trap <- 1;
+ fp_disabled <- 1
+ ) else if ( (LDC or LDDC or LDCSR) and ((EC = 0) or (bp_CP_present = 0)) then (
+ trap <- 1;
+ cp_disabled <- 1
+ ) else if ( ( (LDD or LDDA or LDDF or LDDC) and (address<2:0> != 0)) or
+ ((LD or LDA or LDF or LDFSR or LDC or LDCSR) and (address<1:0> != 0)) or
+ ((LDSH or LDSHA or LDUH or LDUHA) and address<0> != 0) ) then (
+ trap <- 1;
+ mem_address_not_aligned <- 1
+ ) else if (LDDF and (rd<0> != 0)) then (
+ trap <- 1;
+ fp_exception <- 1;
+ ftt <- invalid_fpr_register
+ ) else if ((LDF or LDDF or LDFSR) and (an FPU sequence error is detected)) then (
+ trap <- 1;
+ fp_exception <- 1;
+ ftt <- sequence_error
+ ) else if ((LDC or LDDC or LDCSR) and (a CP sequence error is detected)) then (
+ trap <- 1;
+ cp_exception <- 1;
+ { possibly additional implementation-dependent actions }
+ )
);
next;
if (trap = 0) then {
- (data, MAE) <- memory_read(addr_space, address);
- next;
- if (MAE = 1) then (
- trap <- 1;
- data_access_exception <- 1;
- ) else (
- if (LDSB or LDSBA or LDUB or LDUBA) then (
- if (address<1:0> = 0) then byte <- data<31:24>
- else if (address<1:0> = 1) then byte <- data<23:16>
- else if (address<1:0> = 2) then byte <- data<15: 8>
- else if (address<1:0> = 3) then byte <- data< 7: 0>
- next;
- if (LDSB or LDSBA) then
- word0 <- sign_extend_byte(byte)
- else
- word0 <- zero_extend_byte(byte)
- ) else if (LDSH or LDSHA or LDUH or LDUHA) then (
- if (address<1:0> = 0) then halfword <- data<31:16>
- else if (address<1:0> = 2) then halfword <- data<15: 0>
- next;
- if (LDSH or LDSHA) then
- word0 <- sign_extend_halfword(halfword)
- else
- word0 <- zero_extend_halfword(halfword)
- ) else
- word0 <- data
- )
+ (data, MAE) <- memory_read(addr_space, address);
+ next;
+ if (MAE = 1) then (
+ trap <- 1;
+ data_access_exception <- 1;
+ ) else (
+ if (LDSB or LDSBA or LDUB or LDUBA) then (
+ if (address<1:0> = 0) then byte <- data<31:24>
+ else if (address<1:0> = 1) then byte <- data<23:16>
+ else if (address<1:0> = 2) then byte <- data<15: 8>
+ else if (address<1:0> = 3) then byte <- data< 7: 0>
+ next;
+ if (LDSB or LDSBA) then
+ word0 <- sign_extend_byte(byte)
+ else
+ word0 <- zero_extend_byte(byte)
+ ) else if (LDSH or LDSHA or LDUH or LDUHA) then (
+ if (address<1:0> = 0) then halfword <- data<31:16>
+ else if (address<1:0> = 2) then halfword <- data<15: 0>
+ next;
+ if (LDSH or LDSHA) then
+ word0 <- sign_extend_halfword(halfword)
+ else
+ word0 <- zero_extend_halfword(halfword)
+ ) else
+ word0 <- data
+ )
);
next;
if (trap = 0) then (
- if ( (rd != 0) and (LD or LDA or LDSH or LDSHA
- or LDUHA or LDUH or LDSB or LDSBA or LDUB or LDUBA) ) then
- r[rd] <- word0
- else if (LDF) then f[rd] <- word0
- else if (LDC) then { implementation-dependent actions }
- else if (LDFSR) then FSR <- word0
- else if (LDCSR) then CSR <- word0
- else if (LDD or LDDA) then r[rd and 11110] <- word0
- else if (LDDF) then f[rd and 11110] <- word0
- else if (LDDC) then { implementation-dependent actions }
+ if ( (rd != 0) and (LD or LDA or LDSH or LDSHA
+ or LDUHA or LDUH or LDSB or LDSBA or LDUB or LDUBA) ) then
+ r[rd] <- word0
+ else if (LDF) then f[rd] <- word0
+ else if (LDC) then { implementation-dependent actions }
+ else if (LDFSR) then FSR <- word0
+ else if (LDCSR) then CSR <- word0
+ else if (LDD or LDDA) then r[rd and 11110] <- word0
+ else if (LDDF) then f[rd and 11110] <- word0
+ else if (LDDC) then { implementation-dependent actions }
);
next;
if (((trap = 0) and (LDD or LDDA or LDDF or LDDC)) then (
- (word1, MAE) <- memory_read(addr_space, address + 4);
- next;
- if (MAE = 1) then ( { MAE = 1 only due to a "non-resumable machine-check error" }
- trap <- 1;
- data_access_exception <- 1 )
- else if (LDD or LDDA) then r[rd or 1] <- word1
- else if (LDDF) then f[rd or 1] <- word1
- else if (LDDC) then { implementation-dependent actions }
+ (word1, MAE) <- memory_read(addr_space, address + 4);
+ next;
+ if (MAE = 1) then ( { MAE = 1 only due to a "non-resumable machine-check error" }
+ trap <- 1;
+ data_access_exception <- 1 )
+ else if (LDD or LDDA) then r[rd or 1] <- word1
+ else if (LDDF) then f[rd or 1] <- word1
+ else if (LDDC) then { implementation-dependent actions }
);
*/
@@ -2008,59 +2008,59 @@ void mb86901_device::execute_ldstub(UINT32 op)
/* The SPARC Instruction Manual: Version 8, page 169, "Appendix C - ISP Descriptions - Atomic Load-Store Unsigned Byte Instructions" (SPARCv8.pdf, pg. 166)
if (LDSTUB) then (
- address <- r[rs1] + (if (i = 0) then r[rs2] else sign_extend(simm13));
- addr_space <- (if (S = 0) then 10 else 11)
+ address <- r[rs1] + (if (i = 0) then r[rs2] else sign_extend(simm13));
+ addr_space <- (if (S = 0) then 10 else 11)
} else if (LDSTUBA) then (
- if (S = 0) then (
- trap <- 1;
- privileged_instruction <- 1
- ) else if (i = 1) then (
- trap <- 1;
- illegal_instruction <- 1
- ) else (
- address <- r[rs1] + r[rs2];
- addr_space <- asi
- )
+ if (S = 0) then (
+ trap <- 1;
+ privileged_instruction <- 1
+ ) else if (i = 1) then (
+ trap <- 1;
+ illegal_instruction <- 1
+ ) else (
+ address <- r[rs1] + r[rs2];
+ addr_space <- asi
+ )
);
next;
if (trap = 0) then (
- while ( (pb_block_ldst_byte = 1) or (pb_block_ldst_word = 1) ) then (
- { wait for lock(s) to be lifted }
- { an implementation actually need only block when another LDSTUB or SWAP
- is pending on the same byte in memory as the one addressed by this LDSTUB }
- };
- next;
- pb_block_ldst_byte <- 1;
- next;
- (data, MAE) <- memory_read(addr_space, address);
- next;
- if (MAE = 1) then (
- trap <- 1;
- data_access_exception <- 1
- )
+ while ( (pb_block_ldst_byte = 1) or (pb_block_ldst_word = 1) ) then (
+ { wait for lock(s) to be lifted }
+ { an implementation actually need only block when another LDSTUB or SWAP
+ is pending on the same byte in memory as the one addressed by this LDSTUB }
+ };
+ next;
+ pb_block_ldst_byte <- 1;
+ next;
+ (data, MAE) <- memory_read(addr_space, address);
+ next;
+ if (MAE = 1) then (
+ trap <- 1;
+ data_access_exception <- 1
+ )
)
next;
if (trap = 0) then (
- if (address<1:0> = 0) then ( byte_mask <- 1000 )
- else if (address<1:0> = 1) then ( byte_mask <- 0100 )
- else if (address<1:0> = 2) then ( byte_mask <- 0010 )
- else if (address<1:0> = 3) then ( byte_mask <- 0001 )
- ;
- next;
- MAE <- memory_write(addr_space, address, byte_mask, FFFFFFFF);
- next;
- pb_block_ldst_byte <- 0;
- if (MAE = 1) then ( { MAE = 1 only due to a "non-resumable machine-check error" }
- trap <- 1;
- data_access_exception <- 1
- ) else (
- if (address<1:0> = 0) then word <- zero_extend_byte(data<31:24>)
- else if (address<1:0> = 1) then word <- zero_extend_byte(data<23:24>)
- else if (address<1:0> = 2) then word <- zero_extend_byte(data<15: 8>)
- else if (address<1:0> = 3) then word <- zero_extend_byte(data< 7: 0>)
- next;
- if (rd != 0) then r[rd] <- word
- )
+ if (address<1:0> = 0) then ( byte_mask <- 1000 )
+ else if (address<1:0> = 1) then ( byte_mask <- 0100 )
+ else if (address<1:0> = 2) then ( byte_mask <- 0010 )
+ else if (address<1:0> = 3) then ( byte_mask <- 0001 )
+ ;
+ next;
+ MAE <- memory_write(addr_space, address, byte_mask, FFFFFFFF);
+ next;
+ pb_block_ldst_byte <- 0;
+ if (MAE = 1) then ( { MAE = 1 only due to a "non-resumable machine-check error" }
+ trap <- 1;
+ data_access_exception <- 1
+ ) else (
+ if (address<1:0> = 0) then word <- zero_extend_byte(data<31:24>)
+ else if (address<1:0> = 1) then word <- zero_extend_byte(data<23:24>)
+ else if (address<1:0> = 2) then word <- zero_extend_byte(data<15: 8>)
+ else if (address<1:0> = 3) then word <- zero_extend_byte(data< 7: 0>)
+ next;
+ if (rd != 0) then r[rd] <- word
+ )
);
*/
@@ -2258,16 +2258,16 @@ bool mb86901_device::evaluate_condition(UINT32 op)
bool v = ICC_V_SET;
bool c = ICC_C_SET;
- switch(COND & 7) // COND & 8
- { // 0 8
- case 0: take = false; break; // bn ba
- case 1: take = z; break; // bz bne
- case 2: take = z | (n ^ z); break; // ble bg
- case 3: take = n ^ v; break; // bl bge
- case 4: take = c | z; break; // bleu bgu
- case 5: take = c; break; // bcs bcc
- case 6: take = n; break; // bneg bpos
- case 7: take = v; break; // bvs bvc
+ switch(COND & 7) // COND & 8
+ { // 0 8
+ case 0: take = false; break; // bn ba
+ case 1: take = z; break; // bz bne
+ case 2: take = z | (n ^ z); break; // ble bg
+ case 3: take = n ^ v; break; // bl bge
+ case 4: take = c | z; break; // bleu bgu
+ case 5: take = c; break; // bcs bcc
+ case 6: take = n; break; // bneg bpos
+ case 7: take = v; break; // bvs bvc
}
if (COND & 8)
@@ -2286,32 +2286,32 @@ void mb86901_device::execute_bicc(UINT32 op)
/* The SPARC Instruction Manual: Version 8, page 178, "Appendix C - ISP Descriptions - Branch on Integer Condition Instructions" (SPARCv8.pdf, pg. 175)
eval_icc := (
- if (BNE) then (if (Z = 0) then 1 else 0);
- if (BE) then (if (Z = 1) then 1 else 0);
- if (BG) then (if ((Z or (N xor V)) = 0) then 1 else 0);
- if (BLE) then (if ((Z or (N xor V)) = 1) then 1 else 0);
- if (BGE) then (if ((N xor V) = 0) then 1 else 0);
- if (BL) then (if ((N xor V) = 1) then 1 else 0);
- if (BGU) then (if ((C = 0) and (Z = 0)) then 1 else 0);
- if (BLEU) then (if ((C = 1) or (Z = 1)) then 1 else 0);
- if (BCC) then (if (C = 0) then 1 else 0);
- if (BCS) then (if (C = 1) then 1 else 0);
- if (BPOS) then (if (N = 0) then 1 else 0);
- if (BNEG) then (if (N = 1) then 1 else 0);
- if (BVC) then (if (V = 0) then 1 else 0);
- if (BVS) then (if (V = 1) then 1 else 0);
- if (BA) then 1;
- if (BN) then 0;
+ if (BNE) then (if (Z = 0) then 1 else 0);
+ if (BE) then (if (Z = 1) then 1 else 0);
+ if (BG) then (if ((Z or (N xor V)) = 0) then 1 else 0);
+ if (BLE) then (if ((Z or (N xor V)) = 1) then 1 else 0);
+ if (BGE) then (if ((N xor V) = 0) then 1 else 0);
+ if (BL) then (if ((N xor V) = 1) then 1 else 0);
+ if (BGU) then (if ((C = 0) and (Z = 0)) then 1 else 0);
+ if (BLEU) then (if ((C = 1) or (Z = 1)) then 1 else 0);
+ if (BCC) then (if (C = 0) then 1 else 0);
+ if (BCS) then (if (C = 1) then 1 else 0);
+ if (BPOS) then (if (N = 0) then 1 else 0);
+ if (BNEG) then (if (N = 1) then 1 else 0);
+ if (BVC) then (if (V = 0) then 1 else 0);
+ if (BVS) then (if (V = 1) then 1 else 0);
+ if (BA) then 1;
+ if (BN) then 0;
)
PC <- nPC;
if (eval_icc = 1) then (
- nPC <- PC + sign_extend(disp22[]00);
- if (BA and (a = 1)) then
- annul <- 1 { only for annulling Branch-Always }
+ nPC <- PC + sign_extend(disp22[]00);
+ if (BA and (a = 1)) then
+ annul <- 1 { only for annulling Branch-Always }
) else (
- nPC <- nPC + 4;
- if (a = 1) then
- annul <- 1 { only for annulling branches other than BA }
+ nPC <- nPC + 4;
+ if (a = 1) then
+ annul <- 1 { only for annulling branches other than BA }
)
*/
@@ -2342,35 +2342,35 @@ void mb86901_device::execute_ticc(UINT32 op)
/* The SPARC Instruction Manual: Version 8, page 182, "Appendix C - ISP Descriptions - Trap on Integer Condition Instructions" (SPARCv8.pdf, pg. 179)
trap_eval_icc := (
- if (TNE) then (if (Z = 0) then 1 else 0);
- if (TE) then (if (Z = 1) then 1 else 0);
- if (TG) then (if ((Z or (N xor V)) = 0) then 1 else 0);
- if (TLE) then (if ((Z or (N xor V)) = 1) then 1 else 0);
- if (TGE) then (if ((N xor V) = 0) then 1 else 0);
- if (TL) then (if ((N xor V) = 1) then 1 else 0);
- if (TGU) then (if ((C = 0) and (Z = 0)) then 1 else 0);
- if (TLEU) then (if ((C = 1) or (Z = 1)) then 1 else 0);
- if (TCC) then (if (C = 0) then 1 else 0);
- if (TCS) then (if (C = 1) then 1 else 0);
- if (TPOS) then (if (N = 0) then 1 else 0);
- if (TNEG) then (if (N = 1) then 1 else 0);
- if (TVC) then (if (V = 0) then 1 else 0);
- if (TVS) then (if (V = 1) then 1 else 0);
- if (TA) then 1;
- if (TN) then 0;
+ if (TNE) then (if (Z = 0) then 1 else 0);
+ if (TE) then (if (Z = 1) then 1 else 0);
+ if (TG) then (if ((Z or (N xor V)) = 0) then 1 else 0);
+ if (TLE) then (if ((Z or (N xor V)) = 1) then 1 else 0);
+ if (TGE) then (if ((N xor V) = 0) then 1 else 0);
+ if (TL) then (if ((N xor V) = 1) then 1 else 0);
+ if (TGU) then (if ((C = 0) and (Z = 0)) then 1 else 0);
+ if (TLEU) then (if ((C = 1) or (Z = 1)) then 1 else 0);
+ if (TCC) then (if (C = 0) then 1 else 0);
+ if (TCS) then (if (C = 1) then 1 else 0);
+ if (TPOS) then (if (N = 0) then 1 else 0);
+ if (TNEG) then (if (N = 1) then 1 else 0);
+ if (TVC) then (if (V = 0) then 1 else 0);
+ if (TVS) then (if (V = 1) then 1 else 0);
+ if (TA) then 1;
+ if (TN) then 0;
)
trap_number := r[rs1] + (if (i = 0) then r[rs2] else sign_extend(software_trap#));
if (Ticc) then (
- if (trap_eval_icc = 1) then (
- trap <- 1;
- trap_instruction <- 1;
- ticc_trap_type <- trap_number<6:0>
- ) else (
- PC <- nPC;
- nPC <- nPC + 4;
- )
+ if (trap_eval_icc = 1) then (
+ trap <- 1;
+ trap_instruction <- 1;
+ ticc_trap_type <- trap_number<6:0>
+ ) else (
+ PC <- nPC;
+ nPC <- nPC + 4;
+ )
);
*/
@@ -2489,76 +2489,76 @@ void mb86901_device::execute_trap()
next;
if (error_mode = 0) then (
- ET <- 0;
- PS <- S;
- CWP <- (CWP - 1) modulo NWINDOWS;
-
- next;
- if (annul = 0) then (
- r[17] <- PC;
- r[18] <- nPC;
- ) else { annul != 0) } (
- r[17] <- nPC;
- r[18] <- nPC + 4;
- annul <- 0;
- )
-
- next;
- S <- 1;
- if (reset_trap = 0) then (
- PC <- TBR;
- nPC <- TBR + 4;
- ) else { reset_trap = 1 } (
- PC <- 0;
- nPC <- 4;
- reset_trap <- 0;
- )
+ ET <- 0;
+ PS <- S;
+ CWP <- (CWP - 1) modulo NWINDOWS;
+
+ next;
+ if (annul = 0) then (
+ r[17] <- PC;
+ r[18] <- nPC;
+ ) else { annul != 0) } (
+ r[17] <- nPC;
+ r[18] <- nPC + 4;
+ annul <- 0;
+ )
+
+ next;
+ S <- 1;
+ if (reset_trap = 0) then (
+ PC <- TBR;
+ nPC <- TBR + 4;
+ ) else { reset_trap = 1 } (
+ PC <- 0;
+ nPC <- 4;
+ reset_trap <- 0;
+ )
);
select_trap := (
- if (reset_trap = 1) then { ignore ET, and leave tt unchanged }
- else if (ET = 0) then (
- execute_mode <- 0;
- error_mode <- 1 )
- else if (data_store_error = 1) then tt <- 00101011
- else if (instruction_access_error = 1) then tt <- 00100001
- else if (r_register_access_error = 1) then tt <- 00100000
- else if (instruction_access_exception = 1) then tt <- 00000001
- else if (privileged_instruction = 1) then tt <- 00000011
- else if (illegal_instruction = 1) then tt <- 00000010
- else if (fp_disabled = 1) then tt <- 00000100
- else if (cp_disabled = 1) then tt <- 00100100
- else if (unimplemented_FLUSH = 1) then tt <- 00100101
- else if (window_overflow = 1) then tt <- 00000101
- else if (window_underflow = 1) then tt <- 00000110
- else if (mem_address_not_aligned = 1) then tt <- 00000111
- else if (fp_exception = 1) then tt <- 00001000
- else if (cp_exception = 1) then tt <- 00101000
- else if (data_access_error = 1) then tt <- 00101001
- else if (data_access_exception = 1) then tt <- 00001001
- else if (tag_overflow = 1) then tt <- 00001010
- else if (division_by_zero = 1) then tt <- 00101010
- else if (trap_instruction = 1) then tt <- 1[]ticc_trap_type
- else if (interrupt_level > 0) then tt <- 0001[]interrupt_level;
-
- next;
-
- trap <- 0;
- instruction_access_exception <- 0;
- illegal_instruction <- 0;
- privileged_instruction <- 0;
- fp_disabled <- 0;
- cp_disabled <- 0;
- window_overflow <- 0;
- window_underflow <- 0;
- mem_address_not_aligned <- 0;
- fp_exception <- 0;
- cp_exception <- 0;
- data_access_exception <- 0;
- tag_overflow <- 0;
- division_by_zero <- 0;
- trap_instruction <- 0;
- interrupt_level <- 0;
+ if (reset_trap = 1) then { ignore ET, and leave tt unchanged }
+ else if (ET = 0) then (
+ execute_mode <- 0;
+ error_mode <- 1 )
+ else if (data_store_error = 1) then tt <- 00101011
+ else if (instruction_access_error = 1) then tt <- 00100001
+ else if (r_register_access_error = 1) then tt <- 00100000
+ else if (instruction_access_exception = 1) then tt <- 00000001
+ else if (privileged_instruction = 1) then tt <- 00000011
+ else if (illegal_instruction = 1) then tt <- 00000010
+ else if (fp_disabled = 1) then tt <- 00000100
+ else if (cp_disabled = 1) then tt <- 00100100
+ else if (unimplemented_FLUSH = 1) then tt <- 00100101
+ else if (window_overflow = 1) then tt <- 00000101
+ else if (window_underflow = 1) then tt <- 00000110
+ else if (mem_address_not_aligned = 1) then tt <- 00000111
+ else if (fp_exception = 1) then tt <- 00001000
+ else if (cp_exception = 1) then tt <- 00101000
+ else if (data_access_error = 1) then tt <- 00101001
+ else if (data_access_exception = 1) then tt <- 00001001
+ else if (tag_overflow = 1) then tt <- 00001010
+ else if (division_by_zero = 1) then tt <- 00101010
+ else if (trap_instruction = 1) then tt <- 1[]ticc_trap_type
+ else if (interrupt_level > 0) then tt <- 0001[]interrupt_level;
+
+ next;
+
+ trap <- 0;
+ instruction_access_exception <- 0;
+ illegal_instruction <- 0;
+ privileged_instruction <- 0;
+ fp_disabled <- 0;
+ cp_disabled <- 0;
+ window_overflow <- 0;
+ window_underflow <- 0;
+ mem_address_not_aligned <- 0;
+ fp_exception <- 0;
+ cp_exception <- 0;
+ data_access_exception <- 0;
+ tag_overflow <- 0;
+ division_by_zero <- 0;
+ trap_instruction <- 0;
+ interrupt_level <- 0;
);
*/
@@ -2615,7 +2615,7 @@ void mb86901_device::complete_instruction_execution(UINT32 op)
{
switch (OP)
{
- case OP_TYPE0: // Bicc, SETHI, FBfcc
+ case OP_TYPE0: // Bicc, SETHI, FBfcc
switch (OP2)
{
case OP2_UNIMP: // unimp
@@ -2624,7 +2624,7 @@ void mb86901_device::complete_instruction_execution(UINT32 op)
case OP2_BICC: // branch on integer condition codes
execute_bicc(op);
break;
- case OP2_SETHI: // sethi
+ case OP2_SETHI: // sethi
SET_RDREG(IMM22);
break;
case OP2_FBFCC: // branch on floating-point condition codes
@@ -2674,26 +2674,26 @@ void mb86901_device::dispatch_instruction(UINT32 op)
/* The SPARC Instruction Manual: Version 8, page 159, "Appendix C - ISP Descriptions - C.6. Instruction Dispatch" (SPARCv8.pdf, pg. 156)
illegal_IU_instr :- (
- if ( ( (op == 00) and (op2 == 000) ) { UNIMP instruction }
- or
+ if ( ( (op == 00) and (op2 == 000) ) { UNIMP instruction }
+ or
( ((op=11) or (op=10)) and (op3=unassigned) )
- then 1 else 0
+ then 1 else 0
if (illegal_IU_instr = 1) then (
- trap <- 1
- illegal_instruction <- 1
+ trap <- 1
+ illegal_instruction <- 1
);
if ((FPop1 or FPop2 or FBfcc) and ((EF = 0) or (bp_FPU_present = 0))) then (
- trap <- 1;
- fp_disabled <- 1
+ trap <- 1;
+ fp_disabled <- 1
);
if (CPop1 or CPop2 or CBccc) and ((EC = 0) or (bp_CP_present = 0))) then (
- trap <- 1;
- cp_disabled <- 1
+ trap <- 1;
+ cp_disabled <- 1
);
next;
if (trap = 0) then (
- { code for specific instruction, defined below }
+ { code for specific instruction, defined below }
);
*/
bool illegal_IU_instr = (OP == 0 && OP2 == 0) || ((OP == 3 && !m_ldst_op3_assigned[OP3]) || (OP == 2 && !m_alu_op3_assigned[OP3]));
@@ -2742,12 +2742,12 @@ void mb86901_device::execute_step()
/* The SPARC Instruction Manual: Version 8, page 156, "Appendix C - ISP Descriptions - C.5. Processor States and Instruction Dispatch" (SPARCv8.pdf, pg. 153)
if (bp_reset_in = 1) then (
- execute_mode <- 0;
- reset_mode <- 1;
- break { out of while (execute_mode = 1) loop }
+ execute_mode <- 0;
+ reset_mode <- 1;
+ break { out of while (execute_mode = 1) loop }
) else if ((ET = 1) and ((bp_IRL = 15) or (bp_IRL > PIL))) then (
- trap <- 1;
- interrupt_level <- bp_IRL
+ trap <- 1;
+ interrupt_level <- bp_IRL
);
next;
@@ -2755,40 +2755,40 @@ void mb86901_device::execute_step()
if (execute_mode = 1) then ( { execute_trap may have set execute_mode to 0 }
- { the following code emulates the delayed nature of the write-state-register instructions.
- PSR <- PSR'; PSR' <- PSR''; PSR'' <- PSR'''; PSR''' <- PSR'''';
- ASR <- ASR'; ASR' <- ASR''; ASR'' <- ASR'''; ASR''' <- ASR'''';
- TBR <- TBR'; TBR' <- TBR''; TBR'' <- TBR'''; TBR''' <- TBR'''';
- WIM <- WIM'; WIM' <- WIM''; WIM'' <- WIM'''; WIM''' <- WIM'''';
- Y <- Y'; Y' <- Y''; Y'' <- Y'''; Y''' <- Y'''';
- next;
-
- addr_space := (if (S = 0) then 8 else 9);
- (instruction, MAE) <- memory_read(addr_space, PC);
- next;
-
- if ( (MAE = 1) and (annul = 0) ) then (
- trap <- 1;
- instruction_access_exception <- 1
- ) else (
- if (annul = 0) then (
- dispatch_instruction ; { See Section C.6 }
- next;
- if (FPop1 or FPop2) then (
- complete_fp_execution { See Section C.7 }
- )
- next;
- if ( (trap = 0) and
- not (CALL or RETT or JMPL or Bicc or FBfcc or CBccc or Ticc) ) then (
- PC <- nPC;
- nPC <- nPC + 4
- )
- ) else { annul != 0 } (
- annul <- 0;
- PC <- nPC;
- nPC <- nPC + 4
- )
- )
+ { the following code emulates the delayed nature of the write-state-register instructions.
+ PSR <- PSR'; PSR' <- PSR''; PSR'' <- PSR'''; PSR''' <- PSR'''';
+ ASR <- ASR'; ASR' <- ASR''; ASR'' <- ASR'''; ASR''' <- ASR'''';
+ TBR <- TBR'; TBR' <- TBR''; TBR'' <- TBR'''; TBR''' <- TBR'''';
+ WIM <- WIM'; WIM' <- WIM''; WIM'' <- WIM'''; WIM''' <- WIM'''';
+ Y <- Y'; Y' <- Y''; Y'' <- Y'''; Y''' <- Y'''';
+ next;
+
+ addr_space := (if (S = 0) then 8 else 9);
+ (instruction, MAE) <- memory_read(addr_space, PC);
+ next;
+
+ if ( (MAE = 1) and (annul = 0) ) then (
+ trap <- 1;
+ instruction_access_exception <- 1
+ ) else (
+ if (annul = 0) then (
+ dispatch_instruction ; { See Section C.6 }
+ next;
+ if (FPop1 or FPop2) then (
+ complete_fp_execution { See Section C.7 }
+ )
+ next;
+ if ( (trap = 0) and
+ not (CALL or RETT or JMPL or Bicc or FBfcc or CBccc or Ticc) ) then (
+ PC <- nPC;
+ nPC <- nPC + 4
+ )
+ ) else { annul != 0 } (
+ annul <- 0;
+ PC <- nPC;
+ nPC <- nPC + 4
+ )
+ )
)
*/
if (m_bp_reset_in)
@@ -2898,7 +2898,7 @@ void mb86901_device::execute_step()
printf("Opcode at %08x: %04x, handler is at %08x // add 32-bit word (%08x) from handler table to result (%08x + %08x = %08x)\n", REG(5), opcode, handler_offset, value, REG(4), value, REG(4) + value);
}
else if (opcode == 0x003f || opcode == 0x0066 || opcode == 0x0099 || opcode == 0x0121 || opcode == 0x0136 || opcode == 0x014f || opcode == 0x0155 || opcode == 0x01c7 || opcode == 0x01cd ||
- opcode == 0x0217 || opcode == 0x0289 || opcode == 0x0296 || opcode == 0x029d || opcode == 0x02f2 || opcode == 0x0334 || opcode == 0x0381 || opcode == 0x3d38)
+ opcode == 0x0217 || opcode == 0x0289 || opcode == 0x0296 || opcode == 0x029d || opcode == 0x02f2 || opcode == 0x0334 || opcode == 0x0381 || opcode == 0x3d38)
{
switch(opcode)
{
@@ -3093,7 +3093,6 @@ void mb86901_device::execute_step()
}
else
{
-
m_annul = 0;
PC = nPC;
nPC = nPC + 4;
@@ -3112,12 +3111,12 @@ void mb86901_device::reset_step()
/* The SPARC Instruction Manual: Version 8, page 156, "Appendix C - ISP Descriptions - C.5. Processor States and Instruction Dispatch" (SPARCv8.pdf, pg. 153)
while (reset_mode = 1) (
- if (bp_reset_in = 0) then (
- reset_mode <- 0;
- execute_mode <- 1;
- trap <- 1;
- reset_trap <- 1;
- )
+ if (bp_reset_in = 0) then (
+ reset_mode <- 0;
+ execute_mode <- 1;
+ trap <- 1;
+ reset_trap <- 1;
+ )
);
*/
@@ -3140,11 +3139,11 @@ void mb86901_device::error_step()
/* The SPARC Instruction Manual: Version 8, page 157, "Appendix C - ISP Descriptions - C.5. Processor States and Instruction Dispatch" (SPARCv8.pdf, pg. 154)
while (error_mode = 1) (
- if (bp_reset_in = 1) then (
- error_mode <- 0;
- reset_mode <- 1;
- pb_error <- 0
- )
+ if (bp_reset_in = 1) then (
+ error_mode <- 0;
+ reset_mode <- 1;
+ pb_error <- 0
+ )
);
*/
@@ -3193,9 +3192,9 @@ void mb86901_device::execute_run()
{
for (int i = 0; i < 8; i++)
{
- m_dbgregs[i] = *m_regs[8 + i];
- m_dbgregs[8 + i] = *m_regs[16 + i];
- m_dbgregs[16 + i] = *m_regs[24 + i];
+ m_dbgregs[i] = *m_regs[8 + i];
+ m_dbgregs[8 + i] = *m_regs[16 + i];
+ m_dbgregs[16 + i] = *m_regs[24 + i];
}
}
--m_icount;
diff --git a/src/devices/cpu/sparc/sparc.h b/src/devices/cpu/sparc/sparc.h
index da2d0bc7c82..1acc2263854 100644
--- a/src/devices/cpu/sparc/sparc.h
+++ b/src/devices/cpu/sparc/sparc.h
@@ -11,36 +11,36 @@
#include "sparcdasm.h"
-#define SPARCV8 (0)
-
-#define SPARC_NO_TRAP 256
-#define SPARC_RESET 0
-#define SPARC_INSTRUCTION_ACCESS_EXCEPTION 1
-#define SPARC_ILLEGAL_INSTRUCTION 2
-#define SPARC_PRIVILEGED_INSTRUCTION 3
-#define SPARC_FP_DISABLED 4
-#define SPARC_WINDOW_OVERFLOW 5
-#define SPARC_WINDOW_UNDERFLOW 6
-#define SPARC_MEM_ADDRESS_NOT_ALIGNED 7
-#define SPARC_FLOATING_POINT_EXCEPTION 8
-#define SPARC_DATA_ACCESS_EXCEPTION 9
-#define SPARC_TAG_OVERFLOW 10
-#define SPARC_INT1 17
-#define SPARC_INT2 18
-#define SPARC_INT3 19
-#define SPARC_INT4 20
-#define SPARC_INT5 21
-#define SPARC_INT6 22
-#define SPARC_INT7 23
-#define SPARC_INT8 24
-#define SPARC_INT9 25
-#define SPARC_INT10 26
-#define SPARC_INT11 27
-#define SPARC_INT12 28
-#define SPARC_INT13 29
-#define SPARC_INT14 30
-#define SPARC_INT15 31
-#define SPARC_TRAP_INSTRUCTION 128
+#define SPARCV8 (0)
+
+#define SPARC_NO_TRAP 256
+#define SPARC_RESET 0
+#define SPARC_INSTRUCTION_ACCESS_EXCEPTION 1
+#define SPARC_ILLEGAL_INSTRUCTION 2
+#define SPARC_PRIVILEGED_INSTRUCTION 3
+#define SPARC_FP_DISABLED 4
+#define SPARC_WINDOW_OVERFLOW 5
+#define SPARC_WINDOW_UNDERFLOW 6
+#define SPARC_MEM_ADDRESS_NOT_ALIGNED 7
+#define SPARC_FLOATING_POINT_EXCEPTION 8
+#define SPARC_DATA_ACCESS_EXCEPTION 9
+#define SPARC_TAG_OVERFLOW 10
+#define SPARC_INT1 17
+#define SPARC_INT2 18
+#define SPARC_INT3 19
+#define SPARC_INT4 20
+#define SPARC_INT5 21
+#define SPARC_INT6 22
+#define SPARC_INT7 23
+#define SPARC_INT8 24
+#define SPARC_INT9 25
+#define SPARC_INT10 26
+#define SPARC_INT11 27
+#define SPARC_INT12 28
+#define SPARC_INT13 29
+#define SPARC_INT14 30
+#define SPARC_INT15 31
+#define SPARC_TRAP_INSTRUCTION 128
#define SPARC_FPU_SEQUENCE_ERROR
// TODO: when there are more SPARC CPUs, move setter to a base class
@@ -200,16 +200,16 @@ protected:
UINT8 m_cp_sequence_err;
// fields separated out from PSR (Processor State Register)
- UINT8 m_impl; // implementation (always 0 in MB86901)
- UINT8 m_ver; // version (always 0 in MB86901)
- UINT8 m_icc; // integer condition codes
- bool m_ec; // enable coprocessor
- bool m_ef; // enable FPU
- UINT8 m_pil; // processor interrupt level
- bool m_s; // supervisor mode
- bool m_ps; // prior S state
- bool m_et; // enable traps
- UINT8 m_cwp; // current window pointer
+ UINT8 m_impl; // implementation (always 0 in MB86901)
+ UINT8 m_ver; // version (always 0 in MB86901)
+ UINT8 m_icc; // integer condition codes
+ bool m_ec; // enable coprocessor
+ bool m_ef; // enable FPU
+ UINT8 m_pil; // processor interrupt level
+ bool m_s; // supervisor mode
+ bool m_ps; // prior S state
+ bool m_et; // enable traps
+ UINT8 m_cwp; // current window pointer
bool m_alu_op3_assigned[64];
bool m_ldst_op3_assigned[64];
@@ -259,10 +259,10 @@ enum
SPARC_ICC,
SPARC_CWP,
- SPARC_G0, SPARC_G1, SPARC_G2, SPARC_G3, SPARC_G4, SPARC_G5, SPARC_G6, SPARC_G7,
- SPARC_O0, SPARC_O1, SPARC_O2, SPARC_O3, SPARC_O4, SPARC_O5, SPARC_O6, SPARC_O7,
- SPARC_L0, SPARC_L1, SPARC_L2, SPARC_L3, SPARC_L4, SPARC_L5, SPARC_L6, SPARC_L7,
- SPARC_I0, SPARC_I1, SPARC_I2, SPARC_I3, SPARC_I4, SPARC_I5, SPARC_I6, SPARC_I7,
+ SPARC_G0, SPARC_G1, SPARC_G2, SPARC_G3, SPARC_G4, SPARC_G5, SPARC_G6, SPARC_G7,
+ SPARC_O0, SPARC_O1, SPARC_O2, SPARC_O3, SPARC_O4, SPARC_O5, SPARC_O6, SPARC_O7,
+ SPARC_L0, SPARC_L1, SPARC_L2, SPARC_L3, SPARC_L4, SPARC_L5, SPARC_L6, SPARC_L7,
+ SPARC_I0, SPARC_I1, SPARC_I2, SPARC_I3, SPARC_I4, SPARC_I5, SPARC_I6, SPARC_I7,
SPARC_EC,
SPARC_EF,
@@ -271,13 +271,13 @@ enum
SPARC_S,
SPARC_PS,
- SPARC_R0, SPARC_R1, SPARC_R2, SPARC_R3, SPARC_R4, SPARC_R5, SPARC_R6, SPARC_R7, SPARC_R8, SPARC_R9, SPARC_R10, SPARC_R11, SPARC_R12, SPARC_R13, SPARC_R14, SPARC_R15,
- SPARC_R16, SPARC_R17, SPARC_R18, SPARC_R19, SPARC_R20, SPARC_R21, SPARC_R22, SPARC_R23, SPARC_R24, SPARC_R25, SPARC_R26, SPARC_R27, SPARC_R28, SPARC_R29, SPARC_R30, SPARC_R31,
- SPARC_R32, SPARC_R33, SPARC_R34, SPARC_R35, SPARC_R36, SPARC_R37, SPARC_R38, SPARC_R39, SPARC_R40, SPARC_R41, SPARC_R42, SPARC_R43, SPARC_R44, SPARC_R45, SPARC_R46, SPARC_R47,
- SPARC_R48, SPARC_R49, SPARC_R50, SPARC_R51, SPARC_R52, SPARC_R53, SPARC_R54, SPARC_R55, SPARC_R56, SPARC_R57, SPARC_R58, SPARC_R59, SPARC_R60, SPARC_R61, SPARC_R62, SPARC_R63,
- SPARC_R64, SPARC_R65, SPARC_R66, SPARC_R67, SPARC_R68, SPARC_R69, SPARC_R70, SPARC_R71, SPARC_R72, SPARC_R73, SPARC_R74, SPARC_R75, SPARC_R76, SPARC_R77, SPARC_R78, SPARC_R79,
- SPARC_R80, SPARC_R81, SPARC_R82, SPARC_R83, SPARC_R84, SPARC_R85, SPARC_R86, SPARC_R87, SPARC_R88, SPARC_R89, SPARC_R90, SPARC_R91, SPARC_R92, SPARC_R93, SPARC_R94, SPARC_R95,
- SPARC_R96, SPARC_R97, SPARC_R98, SPARC_R99, SPARC_R100, SPARC_R101, SPARC_R102, SPARC_R103, SPARC_R104, SPARC_R105, SPARC_R106, SPARC_R107, SPARC_R108, SPARC_R109, SPARC_R110, SPARC_R111
+ SPARC_R0, SPARC_R1, SPARC_R2, SPARC_R3, SPARC_R4, SPARC_R5, SPARC_R6, SPARC_R7, SPARC_R8, SPARC_R9, SPARC_R10, SPARC_R11, SPARC_R12, SPARC_R13, SPARC_R14, SPARC_R15,
+ SPARC_R16, SPARC_R17, SPARC_R18, SPARC_R19, SPARC_R20, SPARC_R21, SPARC_R22, SPARC_R23, SPARC_R24, SPARC_R25, SPARC_R26, SPARC_R27, SPARC_R28, SPARC_R29, SPARC_R30, SPARC_R31,
+ SPARC_R32, SPARC_R33, SPARC_R34, SPARC_R35, SPARC_R36, SPARC_R37, SPARC_R38, SPARC_R39, SPARC_R40, SPARC_R41, SPARC_R42, SPARC_R43, SPARC_R44, SPARC_R45, SPARC_R46, SPARC_R47,
+ SPARC_R48, SPARC_R49, SPARC_R50, SPARC_R51, SPARC_R52, SPARC_R53, SPARC_R54, SPARC_R55, SPARC_R56, SPARC_R57, SPARC_R58, SPARC_R59, SPARC_R60, SPARC_R61, SPARC_R62, SPARC_R63,
+ SPARC_R64, SPARC_R65, SPARC_R66, SPARC_R67, SPARC_R68, SPARC_R69, SPARC_R70, SPARC_R71, SPARC_R72, SPARC_R73, SPARC_R74, SPARC_R75, SPARC_R76, SPARC_R77, SPARC_R78, SPARC_R79,
+ SPARC_R80, SPARC_R81, SPARC_R82, SPARC_R83, SPARC_R84, SPARC_R85, SPARC_R86, SPARC_R87, SPARC_R88, SPARC_R89, SPARC_R90, SPARC_R91, SPARC_R92, SPARC_R93, SPARC_R94, SPARC_R95,
+ SPARC_R96, SPARC_R97, SPARC_R98, SPARC_R99, SPARC_R100, SPARC_R101, SPARC_R102, SPARC_R103, SPARC_R104, SPARC_R105, SPARC_R106, SPARC_R107, SPARC_R108, SPARC_R109, SPARC_R110, SPARC_R111
};
#endif /* __SPARC_H__ */
diff --git a/src/devices/cpu/sparc/sparcdefs.h b/src/devices/cpu/sparc/sparcdefs.h
index 7fab760e06b..c59282ffa85 100644
--- a/src/devices/cpu/sparc/sparcdefs.h
+++ b/src/devices/cpu/sparc/sparcdefs.h
@@ -12,375 +12,375 @@
#ifndef __MB86901_DEFS_H__
#define __MB86901_DEFS_H__
-#define PSR_CWP_MASK 0x0000001f
-#define PSR_ET_SHIFT 5
-#define PSR_ET_MASK 0x00000020
-#define PSR_PS_SHIFT 6
-#define PSR_PS_MASK 0x00000040
-#define PSR_S_SHIFT 7
-#define PSR_S_MASK 0x00000080
-#define PSR_PIL_SHIFT 8
-#define PSR_PIL_MASK 0x00000f00
-#define PSR_EF_SHIFT 12
-#define PSR_EF_MASK 0x00001000
-#define PSR_EC_SHIFT 13
-#define PSR_EC_MASK 0x00002000
-#define PSR_ICC_SHIFT 20
-#define PSR_RES_MASK 0x000fc000
-#define PSR_ICC_MASK 0x00f00000
-#define PSR_N_MASK 0x00800000
-#define PSR_Z_MASK 0x00400000
-#define PSR_V_MASK 0x00200000
-#define PSR_C_MASK 0x00100000
-#define PSR_VER_SHIFT 24
-#define PSR_VER_MASK 0x0f000000
-#define PSR_VER 0
-#define PSR_IMPL_SHIFT 28
-#define PSR_IMPL_MASK 0xf0000000
-#define PSR_IMPL 0
-#define PSR_ZERO_MASK (PSR_IMPL_MASK | PSR_VER_MASK | PSR_RES_MASK)
-
-#define ICC_N_SET (m_psr & PSR_N_MASK)
-#define ICC_N (ICC_N_SET ? 1 : 0)
-#define ICC_N_CLEAR (!ICC_N_SET)
-#define SET_ICC_N_FLAG do { m_psr |= PSR_N_MASK; } while(0)
-#define CLEAR_ICC_N_FLAG do { m_psr &= ~PSR_N_MASK; } while(0)
-
-#define ICC_Z_SET (m_psr & PSR_Z_MASK)
-#define ICC_Z (ICC_Z_SET ? 1 : 0)
-#define ICC_Z_CLEAR (!ICC_Z_SET)
-#define SET_ICC_Z_FLAG do { m_psr |= PSR_Z_MASK; } while(0)
-#define CLEAR_ICC_Z_FLAG do { m_psr &= ~PSR_Z_MASK; } while(0)
-
-#define ICC_V_SET (m_psr & PSR_V_MASK)
-#define ICC_V (ICC_V_SET ? 1 : 0)
-#define ICC_V_CLEAR (!ICC_V_SET)
-#define SET_ICC_V_FLAG do { m_psr |= PSR_V_MASK; } while(0)
-#define CLEAR_ICC_V_FLAG do { m_psr &= ~PSR_V_MASK; } while(0)
-
-#define ICC_C_SET (m_psr & PSR_C_MASK)
-#define ICC_C (ICC_C_SET ? 1 : 0)
-#define ICC_C_CLEAR (!ICC_C_SET)
-#define SET_ICC_C_FLAG do { m_psr |= PSR_C_MASK; } while(0)
-#define CLEAR_ICC_C_FLAG do { m_psr &= ~PSR_C_MASK; } while(0)
-
-#define CLEAR_ICC do { m_psr &= ~PSR_ICC_MASK; } while(0)
-
-#define TEST_ICC_NZ(x) do { m_psr &= ~PSR_ICC_MASK; m_psr |= (x & 0x80000000) ? PSR_N_MASK : 0; m_psr |= (x == 0) ? PSR_Z_MASK : 0; } while (0)
-
-#define MAKE_PSR do { m_psr = (m_impl << PSR_IMPL_SHIFT) | (m_ver << PSR_VER_SHIFT) | (m_icc << PSR_ICC_SHIFT) | (m_ec ? PSR_EC_MASK : 0) | (m_ef ? PSR_EF_MASK : 0) | (m_pil << PSR_PIL_SHIFT) | (m_s ? PSR_S_MASK : 0) | (m_ps ? PSR_PS_MASK : 0) | (m_et ? PSR_ET_MASK : 0) | m_cwp; } while(0)
-#define BREAK_PSR do { m_icc = (m_psr & PSR_ICC_MASK) >> PSR_ICC_SHIFT; m_ec = m_psr & PSR_EC_MASK; m_ef = m_psr & PSR_EF_MASK; m_pil = (m_psr & PSR_PIL_MASK) >> PSR_PIL_SHIFT; m_s = m_psr & PSR_S_MASK; m_ps = m_psr & PSR_PS_MASK; m_et = m_psr & PSR_ET_MASK; m_cwp = m_psr & PSR_CWP_MASK; } while(0)
-#define MAKE_ICC do { m_icc = (m_psr & PSR_ICC_MASK) >> PSR_ICC_SHIFT; } while(0)
-
-#define CWP m_cwp
-#define S m_s
-#define PS m_ps
-
-#define IS_SUPERVISOR (m_psr & PSR_S_MASK)
-#define IS_USER (!IS_SUPERVISOR)
-
-#define TRAPS_ENABLED (m_psr & PSR_ET_MASK)
-#define TRAPS_DISABLED (!TRAPS_ENABLED)
-
-#define PSR m_psr
-#define WIM m_wim
-#define TBR m_tbr
-
-#define OP (op >> 30) // gangnam style
-#define OP2 ((op >> 22) & 7)
-#define OP3 ((op >> 19) & 63)
-#define OPF ((op >> 5) & 0x1ff)
-#define OPC ((op >> 5) & 0x1ff)
-#define OPFLOW ((op >> 5) & 0x3f)
-
-#define DISP30 (INT32(op << 2))
-#define DISP22 (INT32(op << 10) >> 8)
-#define DISP19 (INT32(op << 13) >> 11)
-#define DISP16 (INT32(((op << 10) & 0xc0000000) | ((op << 16) & 0x3fff0000)) >> 14)
-#define IMM22 (op << 10)
+#define PSR_CWP_MASK 0x0000001f
+#define PSR_ET_SHIFT 5
+#define PSR_ET_MASK 0x00000020
+#define PSR_PS_SHIFT 6
+#define PSR_PS_MASK 0x00000040
+#define PSR_S_SHIFT 7
+#define PSR_S_MASK 0x00000080
+#define PSR_PIL_SHIFT 8
+#define PSR_PIL_MASK 0x00000f00
+#define PSR_EF_SHIFT 12
+#define PSR_EF_MASK 0x00001000
+#define PSR_EC_SHIFT 13
+#define PSR_EC_MASK 0x00002000
+#define PSR_ICC_SHIFT 20
+#define PSR_RES_MASK 0x000fc000
+#define PSR_ICC_MASK 0x00f00000
+#define PSR_N_MASK 0x00800000
+#define PSR_Z_MASK 0x00400000
+#define PSR_V_MASK 0x00200000
+#define PSR_C_MASK 0x00100000
+#define PSR_VER_SHIFT 24
+#define PSR_VER_MASK 0x0f000000
+#define PSR_VER 0
+#define PSR_IMPL_SHIFT 28
+#define PSR_IMPL_MASK 0xf0000000
+#define PSR_IMPL 0
+#define PSR_ZERO_MASK (PSR_IMPL_MASK | PSR_VER_MASK | PSR_RES_MASK)
+
+#define ICC_N_SET (m_psr & PSR_N_MASK)
+#define ICC_N (ICC_N_SET ? 1 : 0)
+#define ICC_N_CLEAR (!ICC_N_SET)
+#define SET_ICC_N_FLAG do { m_psr |= PSR_N_MASK; } while(0)
+#define CLEAR_ICC_N_FLAG do { m_psr &= ~PSR_N_MASK; } while(0)
+
+#define ICC_Z_SET (m_psr & PSR_Z_MASK)
+#define ICC_Z (ICC_Z_SET ? 1 : 0)
+#define ICC_Z_CLEAR (!ICC_Z_SET)
+#define SET_ICC_Z_FLAG do { m_psr |= PSR_Z_MASK; } while(0)
+#define CLEAR_ICC_Z_FLAG do { m_psr &= ~PSR_Z_MASK; } while(0)
+
+#define ICC_V_SET (m_psr & PSR_V_MASK)
+#define ICC_V (ICC_V_SET ? 1 : 0)
+#define ICC_V_CLEAR (!ICC_V_SET)
+#define SET_ICC_V_FLAG do { m_psr |= PSR_V_MASK; } while(0)
+#define CLEAR_ICC_V_FLAG do { m_psr &= ~PSR_V_MASK; } while(0)
+
+#define ICC_C_SET (m_psr & PSR_C_MASK)
+#define ICC_C (ICC_C_SET ? 1 : 0)
+#define ICC_C_CLEAR (!ICC_C_SET)
+#define SET_ICC_C_FLAG do { m_psr |= PSR_C_MASK; } while(0)
+#define CLEAR_ICC_C_FLAG do { m_psr &= ~PSR_C_MASK; } while(0)
+
+#define CLEAR_ICC do { m_psr &= ~PSR_ICC_MASK; } while(0)
+
+#define TEST_ICC_NZ(x) do { m_psr &= ~PSR_ICC_MASK; m_psr |= (x & 0x80000000) ? PSR_N_MASK : 0; m_psr |= (x == 0) ? PSR_Z_MASK : 0; } while (0)
+
+#define MAKE_PSR do { m_psr = (m_impl << PSR_IMPL_SHIFT) | (m_ver << PSR_VER_SHIFT) | (m_icc << PSR_ICC_SHIFT) | (m_ec ? PSR_EC_MASK : 0) | (m_ef ? PSR_EF_MASK : 0) | (m_pil << PSR_PIL_SHIFT) | (m_s ? PSR_S_MASK : 0) | (m_ps ? PSR_PS_MASK : 0) | (m_et ? PSR_ET_MASK : 0) | m_cwp; } while(0)
+#define BREAK_PSR do { m_icc = (m_psr & PSR_ICC_MASK) >> PSR_ICC_SHIFT; m_ec = m_psr & PSR_EC_MASK; m_ef = m_psr & PSR_EF_MASK; m_pil = (m_psr & PSR_PIL_MASK) >> PSR_PIL_SHIFT; m_s = m_psr & PSR_S_MASK; m_ps = m_psr & PSR_PS_MASK; m_et = m_psr & PSR_ET_MASK; m_cwp = m_psr & PSR_CWP_MASK; } while(0)
+#define MAKE_ICC do { m_icc = (m_psr & PSR_ICC_MASK) >> PSR_ICC_SHIFT; } while(0)
+
+#define CWP m_cwp
+#define S m_s
+#define PS m_ps
+
+#define IS_SUPERVISOR (m_psr & PSR_S_MASK)
+#define IS_USER (!IS_SUPERVISOR)
+
+#define TRAPS_ENABLED (m_psr & PSR_ET_MASK)
+#define TRAPS_DISABLED (!TRAPS_ENABLED)
+
+#define PSR m_psr
+#define WIM m_wim
+#define TBR m_tbr
+
+#define OP (op >> 30) // gangnam style
+#define OP2 ((op >> 22) & 7)
+#define OP3 ((op >> 19) & 63)
+#define OPF ((op >> 5) & 0x1ff)
+#define OPC ((op >> 5) & 0x1ff)
+#define OPFLOW ((op >> 5) & 0x3f)
+
+#define DISP30 (INT32(op << 2))
+#define DISP22 (INT32(op << 10) >> 8)
+#define DISP19 (INT32(op << 13) >> 11)
+#define DISP16 (INT32(((op << 10) & 0xc0000000) | ((op << 16) & 0x3fff0000)) >> 14)
+#define IMM22 (op << 10)
#define CONST22 (op & 0x3fffff)
-#define SIMM13 (INT32(op << 19) >> 19)
-#define SIMM11 (INT32(op << 21) >> 21)
-#define SIMM10 (INT32(op << 22) >> 22)
-#define SIMM8 (INT32(op << 24) >> 24)
-#define IMM7 (op & 0x7f)
-#define SIMM7 (INT32(op << 25) >> 25)
-#define SHCNT32 (op & 31)
+#define SIMM13 (INT32(op << 19) >> 19)
+#define SIMM11 (INT32(op << 21) >> 21)
+#define SIMM10 (INT32(op << 22) >> 22)
+#define SIMM8 (INT32(op << 24) >> 24)
+#define IMM7 (op & 0x7f)
+#define SIMM7 (INT32(op << 25) >> 25)
+#define SHCNT32 (op & 31)
#define SHCNT64 (op & 63)
#define IAMODE (op & 0x7)
-#define USEIMM ((op >> 13) & 1)
-#define USEEXT ((op >> 12) & 1)
-
-
-#define COND ((op >> 25) & 15)
-#define RCOND ((op >> 10) & 7)
-#define MOVCOND ((op >> 14) & 15)
-#define PRED ((op >> 19) & 1)
-#define ANNUL ((op >> 29) & 1)
-#define BRCC ((op >> 20) & 3)
-#define MOVCC (((op >> 11) & 3) | ((op >> 16) & 4))
-#define OPFCC ((op >> 11) & 7)
-#define TCCCC ((op >> 11) & 3)
-#define ASI ((op >> 5) & 255)
-#define MMASK (op & 15)
-#define CMASK ((op >> 4) & 7)
-
-#define RD ((op >> 25) & 31)
-#define RS1 ((op >> 14) & 31)
-#define RS2 (op & 31)
-
-#define FREG(x) m_fpr[(x)]
-#define FDREG m_fpr[RD]
-#define FSR m_fsr
-
-#define REG(x) *m_regs[(x)]
-#define RDREG *m_regs[RD]
-#define RS1REG *m_regs[RS1]
-#define RS2REG *m_regs[RS2]
-#define SET_RDREG(x) do { if(RD) { RDREG = (x); } } while (0)
-#define ADDRESS (USEIMM ? (RS1REG + SIMM13) : (RS1REG + RS2REG))
-
-#define PC m_pc
-#define nPC m_npc
-
-#define Y m_y
-
-#define ET m_et
-#define EF m_ef
-#define EC m_ec
-#define PIL m_pil
-
-#define MAE m_mae
-#define HOLD_BUS m_hold_bus
-
-#define BIT31(x) ((x) & 0x80000000)
-
-#define UPDATE_PC true
-#define PC_UPDATED false
-
-#define OP_TYPE0 0
-#define OP_CALL 1
-#define OP_ALU 2
-#define OP_LDST 3
-
-#define OP2_UNIMP 0
-#define OP2_BICC 2
-#define OP2_SETHI 4
-#define OP2_FBFCC 6
-#define OP2_CBCCC 7
-
-#define OP3_ADD 0
-#define OP3_AND 1
-#define OP3_OR 2
-#define OP3_XOR 3
-#define OP3_SUB 4
-#define OP3_ANDN 5
-#define OP3_ORN 6
-#define OP3_XNOR 7
-#define OP3_ADDX 8
-#define OP3_UMUL 10
-#define OP3_SMUL 11
-#define OP3_SUBX 12
-#define OP3_UDIV 14
-#define OP3_SDIV 15
-#define OP3_ADDCC 16
-#define OP3_ANDCC 17
-#define OP3_ORCC 18
-#define OP3_XORCC 19
-#define OP3_SUBCC 20
-#define OP3_ANDNCC 21
-#define OP3_ORNCC 22
-#define OP3_XNORCC 23
-#define OP3_ADDXCC 24
-#define OP3_UMULCC 26
-#define OP3_SMULCC 27
-#define OP3_SUBXCC 28
-#define OP3_UDIVCC 30
-#define OP3_SDIVCC 31
-#define OP3_TADDCC 32
-#define OP3_TSUBCC 33
-#define OP3_TADDCCTV 34
-#define OP3_TSUBCCTV 35
-#define OP3_MULSCC 36
-#define OP3_SLL 37
-#define OP3_SRL 38
-#define OP3_SRA 39
-#define OP3_RDASR 40
-#define OP3_RDPSR 41
-#define OP3_RDWIM 42
-#define OP3_RDTBR 43
-#define OP3_WRASR 48
-#define OP3_WRPSR 49
-#define OP3_WRWIM 50
-#define OP3_WRTBR 51
-#define OP3_FPOP1 52
-#define OP3_FPOP2 53
-#define OP3_JMPL 56
-#define OP3_RETT 57
-#define OP3_TICC 58
-#define OP3_SAVE 60
-#define OP3_RESTORE 61
-
-#define OP3_LD 0
-#define OP3_LDUB 1
-#define OP3_LDUH 2
-#define OP3_LDD 3
-#define OP3_ST 4
-#define OP3_STB 5
-#define OP3_STH 6
-#define OP3_STD 7
-#define OP3_LDSB 9
-#define OP3_LDSH 10
-#define OP3_LDSTUB 13
-#define OP3_SWAP 15
-#define OP3_LDA 16
-#define OP3_LDUBA 17
-#define OP3_LDUHA 18
-#define OP3_LDDA 19
-#define OP3_STA 20
-#define OP3_STBA 21
-#define OP3_STHA 22
-#define OP3_STDA 23
-#define OP3_LDSBA 25
-#define OP3_LDSHA 26
-#define OP3_LDSTUBA 29
-#define OP3_SWAPA 31
-#define OP3_LDFPR 32
-#define OP3_LDFSR 33
-#define OP3_LDDFPR 35
-#define OP3_STFPR 36
-#define OP3_STFSR 37
-#define OP3_STDFQ 38
-#define OP3_STDFPR 39
-#define OP3_LDCPR 40
-#define OP3_LDCSR 41
-#define OP3_LDDCPR 43
-#define OP3_STCPR 44
-#define OP3_STCSR 45
-#define OP3_STDCQ 46
-#define OP3_STDCPR 47
-#define OP3_CPOP1 54
-#define OP3_CPOP2 55
-
-#define COND_BN 0
-#define COND_BE 1
-#define COND_BLE 2
-#define COND_BL 3
-#define COND_BLEU 4
-#define COND_BCS 5
-#define COND_BNEG 6
-#define COND_BVS 7
-#define COND_BA 8
-#define COND_BNE 9
-#define COND_BG 10
-#define COND_BGE 11
-#define COND_BGU 12
-#define COND_BCC 13
-#define COND_BPOS 14
-#define COND_BVC 15
-
-#define LDD (OP3 == OP3_LDD)
-#define LD (OP3 == OP3_LD)
-#define LDSH (OP3 == OP3_LDSH)
-#define LDUH (OP3 == OP3_LDUH)
-#define LDSB (OP3 == OP3_LDSB)
-#define LDUB (OP3 == OP3_LDUB)
-#define LDDF (OP3 == OP3_LDDFPR)
-#define LDF (OP3 == OP3_LDFPR)
-#define LDFSR (OP3 == OP3_LDFSR)
-#define LDDC (OP3 == OP3_LDDCPR)
-#define LDC (OP3 == OP3_LDCPR)
-#define LDCSR (OP3 == OP3_LDCSR)
-#define LDDA (OP3 == OP3_LDDA)
-#define LDA (OP3 == OP3_LDA)
-#define LDSHA (OP3 == OP3_LDSHA)
-#define LDUHA (OP3 == OP3_LDUHA)
-#define LDSBA (OP3 == OP3_LDSBA)
-#define LDUBA (OP3 == OP3_LDUBA)
-
-#define STD (OP3 == OP3_STD)
-#define ST (OP3 == OP3_ST)
-#define STH (OP3 == OP3_STH)
-#define STB (OP3 == OP3_STB)
-#define STDA (OP3 == OP3_STDA)
-#define STA (OP3 == OP3_STA)
-#define STHA (OP3 == OP3_STHA)
-#define STBA (OP3 == OP3_STBA)
-#define STF (OP3 == OP3_STFPR)
-#define STFSR (OP3 == OP3_STFSR)
-#define STDFQ (OP3 == OP3_STDFQ)
-#define STDF (OP3 == OP3_STDFPR)
-#define STC (OP3 == OP3_STCPR)
-#define STCSR (OP3 == OP3_STCSR)
-#define STDCQ (OP3 == OP3_STDCQ)
-#define STDC (OP3 == OP3_STDCPR)
-
-#define JMPL (OP3 == OP3_JMPL)
-#define TICC (OP3 == OP3_TICC)
-#define RETT (OP3 == OP3_RETT)
-
-#define SWAP (OP3 == OP3_SWAP)
-#define SWAPA (OP3 == OP3_SWAPA)
-
-#define FPOP1 (OP3 == OP3_FPOP1)
-#define FPOP2 (OP3 == OP3_FPOP2)
-#define CPOP1 (OP3 == OP3_CPOP1)
-#define CPOP2 (OP3 == OP3_CPOP2)
-
-#define LDSTUB (OP3 == OP3_LDSTUB)
-#define LDSTUBA (OP3 == OP3_LDSTUBA)
-
-#define ADD (OP3 == OP3_ADD)
-#define ADDX (OP3 == OP3_ADDX)
-#define ADDCC (OP3 == OP3_ADDCC)
-#define ADDXCC (OP3 == OP3_ADDXCC)
-
-#define SUB (OP3 == OP3_SUB)
-#define SUBX (OP3 == OP3_SUBX)
-#define SUBCC (OP3 == OP3_SUBCC)
-#define SUBXCC (OP3 == OP3_SUBXCC)
-
-#define TADDCCTV (OP3 == OP3_TADDCCTV)
-#define TSUBCCTV (OP3 == OP3_TSUBCCTV)
-
-#define AND (OP3 == OP3_AND)
-#define OR (OP3 == OP3_OR)
-#define XOR (OP3 == OP3_XOR)
-#define ANDN (OP3 == OP3_ANDN)
-#define ORN (OP3 == OP3_ORN)
-#define XNOR (OP3 == OP3_XNOR)
-#define ANDCC (OP3 == OP3_ANDCC)
-#define ORCC (OP3 == OP3_ORCC)
-#define XORCC (OP3 == OP3_XORCC)
-#define ANDNCC (OP3 == OP3_ANDNCC)
-#define ORNCC (OP3 == OP3_ORNCC)
-#define XNORCC (OP3 == OP3_XNORCC)
-
-#define SLL (OP3 == OP3_SLL)
-#define SRL (OP3 == OP3_SRL)
-#define SRA (OP3 == OP3_SRA)
-
-#define RDASR (OP3 == OP3_RDASR)
-#define RDPSR (OP3 == OP3_RDPSR)
-#define RDWIM (OP3 == OP3_RDWIM)
-#define RDTBR (OP3 == OP3_RDTBR)
-
-#define WRASR (OP3 == OP3_WRASR)
-#define WRPSR (OP3 == OP3_WRPSR)
-#define WRWIM (OP3 == OP3_WRWIM)
-#define WRTBR (OP3 == OP3_WRTBR)
-
-#define SAVE (OP3 == OP3_SAVE)
-#define RESTORE (OP3 == OP3_RESTORE)
-
-#define UMUL (OP3 == OP3_UMUL)
-#define UMULCC (OP3 == OP3_UMULCC)
-#define SMUL (OP3 == OP3_SMUL)
-#define SMULCC (OP3 == OP3_SMULCC)
-
-#define UDIV (OP3 == OP3_UDIV)
-#define UDIVCC (OP3 == OP3_UDIVCC)
-#define SDIV (OP3 == OP3_SDIV)
-#define SDIVCC (OP3 == OP3_SDIVCC)
-
-#endif // __MB86901_DEFS_H__ \ No newline at end of file
+#define USEIMM ((op >> 13) & 1)
+#define USEEXT ((op >> 12) & 1)
+
+
+#define COND ((op >> 25) & 15)
+#define RCOND ((op >> 10) & 7)
+#define MOVCOND ((op >> 14) & 15)
+#define PRED ((op >> 19) & 1)
+#define ANNUL ((op >> 29) & 1)
+#define BRCC ((op >> 20) & 3)
+#define MOVCC (((op >> 11) & 3) | ((op >> 16) & 4))
+#define OPFCC ((op >> 11) & 7)
+#define TCCCC ((op >> 11) & 3)
+#define ASI ((op >> 5) & 255)
+#define MMASK (op & 15)
+#define CMASK ((op >> 4) & 7)
+
+#define RD ((op >> 25) & 31)
+#define RS1 ((op >> 14) & 31)
+#define RS2 (op & 31)
+
+#define FREG(x) m_fpr[(x)]
+#define FDREG m_fpr[RD]
+#define FSR m_fsr
+
+#define REG(x) *m_regs[(x)]
+#define RDREG *m_regs[RD]
+#define RS1REG *m_regs[RS1]
+#define RS2REG *m_regs[RS2]
+#define SET_RDREG(x) do { if(RD) { RDREG = (x); } } while (0)
+#define ADDRESS (USEIMM ? (RS1REG + SIMM13) : (RS1REG + RS2REG))
+
+#define PC m_pc
+#define nPC m_npc
+
+#define Y m_y
+
+#define ET m_et
+#define EF m_ef
+#define EC m_ec
+#define PIL m_pil
+
+#define MAE m_mae
+#define HOLD_BUS m_hold_bus
+
+#define BIT31(x) ((x) & 0x80000000)
+
+#define UPDATE_PC true
+#define PC_UPDATED false
+
+#define OP_TYPE0 0
+#define OP_CALL 1
+#define OP_ALU 2
+#define OP_LDST 3
+
+#define OP2_UNIMP 0
+#define OP2_BICC 2
+#define OP2_SETHI 4
+#define OP2_FBFCC 6
+#define OP2_CBCCC 7
+
+#define OP3_ADD 0
+#define OP3_AND 1
+#define OP3_OR 2
+#define OP3_XOR 3
+#define OP3_SUB 4
+#define OP3_ANDN 5
+#define OP3_ORN 6
+#define OP3_XNOR 7
+#define OP3_ADDX 8
+#define OP3_UMUL 10
+#define OP3_SMUL 11
+#define OP3_SUBX 12
+#define OP3_UDIV 14
+#define OP3_SDIV 15
+#define OP3_ADDCC 16
+#define OP3_ANDCC 17
+#define OP3_ORCC 18
+#define OP3_XORCC 19
+#define OP3_SUBCC 20
+#define OP3_ANDNCC 21
+#define OP3_ORNCC 22
+#define OP3_XNORCC 23
+#define OP3_ADDXCC 24
+#define OP3_UMULCC 26
+#define OP3_SMULCC 27
+#define OP3_SUBXCC 28
+#define OP3_UDIVCC 30
+#define OP3_SDIVCC 31
+#define OP3_TADDCC 32
+#define OP3_TSUBCC 33
+#define OP3_TADDCCTV 34
+#define OP3_TSUBCCTV 35
+#define OP3_MULSCC 36
+#define OP3_SLL 37
+#define OP3_SRL 38
+#define OP3_SRA 39
+#define OP3_RDASR 40
+#define OP3_RDPSR 41
+#define OP3_RDWIM 42
+#define OP3_RDTBR 43
+#define OP3_WRASR 48
+#define OP3_WRPSR 49
+#define OP3_WRWIM 50
+#define OP3_WRTBR 51
+#define OP3_FPOP1 52
+#define OP3_FPOP2 53
+#define OP3_JMPL 56
+#define OP3_RETT 57
+#define OP3_TICC 58
+#define OP3_SAVE 60
+#define OP3_RESTORE 61
+
+#define OP3_LD 0
+#define OP3_LDUB 1
+#define OP3_LDUH 2
+#define OP3_LDD 3
+#define OP3_ST 4
+#define OP3_STB 5
+#define OP3_STH 6
+#define OP3_STD 7
+#define OP3_LDSB 9
+#define OP3_LDSH 10
+#define OP3_LDSTUB 13
+#define OP3_SWAP 15
+#define OP3_LDA 16
+#define OP3_LDUBA 17
+#define OP3_LDUHA 18
+#define OP3_LDDA 19
+#define OP3_STA 20
+#define OP3_STBA 21
+#define OP3_STHA 22
+#define OP3_STDA 23
+#define OP3_LDSBA 25
+#define OP3_LDSHA 26
+#define OP3_LDSTUBA 29
+#define OP3_SWAPA 31
+#define OP3_LDFPR 32
+#define OP3_LDFSR 33
+#define OP3_LDDFPR 35
+#define OP3_STFPR 36
+#define OP3_STFSR 37
+#define OP3_STDFQ 38
+#define OP3_STDFPR 39
+#define OP3_LDCPR 40
+#define OP3_LDCSR 41
+#define OP3_LDDCPR 43
+#define OP3_STCPR 44
+#define OP3_STCSR 45
+#define OP3_STDCQ 46
+#define OP3_STDCPR 47
+#define OP3_CPOP1 54
+#define OP3_CPOP2 55
+
+#define COND_BN 0
+#define COND_BE 1
+#define COND_BLE 2
+#define COND_BL 3
+#define COND_BLEU 4
+#define COND_BCS 5
+#define COND_BNEG 6
+#define COND_BVS 7
+#define COND_BA 8
+#define COND_BNE 9
+#define COND_BG 10
+#define COND_BGE 11
+#define COND_BGU 12
+#define COND_BCC 13
+#define COND_BPOS 14
+#define COND_BVC 15
+
+#define LDD (OP3 == OP3_LDD)
+#define LD (OP3 == OP3_LD)
+#define LDSH (OP3 == OP3_LDSH)
+#define LDUH (OP3 == OP3_LDUH)
+#define LDSB (OP3 == OP3_LDSB)
+#define LDUB (OP3 == OP3_LDUB)
+#define LDDF (OP3 == OP3_LDDFPR)
+#define LDF (OP3 == OP3_LDFPR)
+#define LDFSR (OP3 == OP3_LDFSR)
+#define LDDC (OP3 == OP3_LDDCPR)
+#define LDC (OP3 == OP3_LDCPR)
+#define LDCSR (OP3 == OP3_LDCSR)
+#define LDDA (OP3 == OP3_LDDA)
+#define LDA (OP3 == OP3_LDA)
+#define LDSHA (OP3 == OP3_LDSHA)
+#define LDUHA (OP3 == OP3_LDUHA)
+#define LDSBA (OP3 == OP3_LDSBA)
+#define LDUBA (OP3 == OP3_LDUBA)
+
+#define STD (OP3 == OP3_STD)
+#define ST (OP3 == OP3_ST)
+#define STH (OP3 == OP3_STH)
+#define STB (OP3 == OP3_STB)
+#define STDA (OP3 == OP3_STDA)
+#define STA (OP3 == OP3_STA)
+#define STHA (OP3 == OP3_STHA)
+#define STBA (OP3 == OP3_STBA)
+#define STF (OP3 == OP3_STFPR)
+#define STFSR (OP3 == OP3_STFSR)
+#define STDFQ (OP3 == OP3_STDFQ)
+#define STDF (OP3 == OP3_STDFPR)
+#define STC (OP3 == OP3_STCPR)
+#define STCSR (OP3 == OP3_STCSR)
+#define STDCQ (OP3 == OP3_STDCQ)
+#define STDC (OP3 == OP3_STDCPR)
+
+#define JMPL (OP3 == OP3_JMPL)
+#define TICC (OP3 == OP3_TICC)
+#define RETT (OP3 == OP3_RETT)
+
+#define SWAP (OP3 == OP3_SWAP)
+#define SWAPA (OP3 == OP3_SWAPA)
+
+#define FPOP1 (OP3 == OP3_FPOP1)
+#define FPOP2 (OP3 == OP3_FPOP2)
+#define CPOP1 (OP3 == OP3_CPOP1)
+#define CPOP2 (OP3 == OP3_CPOP2)
+
+#define LDSTUB (OP3 == OP3_LDSTUB)
+#define LDSTUBA (OP3 == OP3_LDSTUBA)
+
+#define ADD (OP3 == OP3_ADD)
+#define ADDX (OP3 == OP3_ADDX)
+#define ADDCC (OP3 == OP3_ADDCC)
+#define ADDXCC (OP3 == OP3_ADDXCC)
+
+#define SUB (OP3 == OP3_SUB)
+#define SUBX (OP3 == OP3_SUBX)
+#define SUBCC (OP3 == OP3_SUBCC)
+#define SUBXCC (OP3 == OP3_SUBXCC)
+
+#define TADDCCTV (OP3 == OP3_TADDCCTV)
+#define TSUBCCTV (OP3 == OP3_TSUBCCTV)
+
+#define AND (OP3 == OP3_AND)
+#define OR (OP3 == OP3_OR)
+#define XOR (OP3 == OP3_XOR)
+#define ANDN (OP3 == OP3_ANDN)
+#define ORN (OP3 == OP3_ORN)
+#define XNOR (OP3 == OP3_XNOR)
+#define ANDCC (OP3 == OP3_ANDCC)
+#define ORCC (OP3 == OP3_ORCC)
+#define XORCC (OP3 == OP3_XORCC)
+#define ANDNCC (OP3 == OP3_ANDNCC)
+#define ORNCC (OP3 == OP3_ORNCC)
+#define XNORCC (OP3 == OP3_XNORCC)
+
+#define SLL (OP3 == OP3_SLL)
+#define SRL (OP3 == OP3_SRL)
+#define SRA (OP3 == OP3_SRA)
+
+#define RDASR (OP3 == OP3_RDASR)
+#define RDPSR (OP3 == OP3_RDPSR)
+#define RDWIM (OP3 == OP3_RDWIM)
+#define RDTBR (OP3 == OP3_RDTBR)
+
+#define WRASR (OP3 == OP3_WRASR)
+#define WRPSR (OP3 == OP3_WRPSR)
+#define WRWIM (OP3 == OP3_WRWIM)
+#define WRTBR (OP3 == OP3_WRTBR)
+
+#define SAVE (OP3 == OP3_SAVE)
+#define RESTORE (OP3 == OP3_RESTORE)
+
+#define UMUL (OP3 == OP3_UMUL)
+#define UMULCC (OP3 == OP3_UMULCC)
+#define SMUL (OP3 == OP3_SMUL)
+#define SMULCC (OP3 == OP3_SMULCC)
+
+#define UDIV (OP3 == OP3_UDIV)
+#define UDIVCC (OP3 == OP3_UDIVCC)
+#define SDIV (OP3 == OP3_SDIV)
+#define SDIVCC (OP3 == OP3_SDIVCC)
+
+#endif // __MB86901_DEFS_H__
diff --git a/src/devices/cpu/tms32010/tms32010.h b/src/devices/cpu/tms32010/tms32010.h
index 61e36279e17..d595b073997 100644
--- a/src/devices/cpu/tms32010/tms32010.h
+++ b/src/devices/cpu/tms32010/tms32010.h
@@ -45,7 +45,7 @@ public:
// construction/destruction
tms32010_device(const machine_config &mconfig, const char *tag, device_t *owner, UINT32 clock);
tms32010_device(const machine_config &mconfig, device_type type, const char *name, const char *tag, device_t *owner, UINT32 clock, const char *shortname, const char *source, int addr_mask);
-
+
// static configuration helpers
template<class _Object> static devcb_base & set_bio_in_cb(device_t &device, _Object object) { return downcast<tms32010_device &>(device).m_bio_in.set_callback(object); }
@@ -78,7 +78,7 @@ private:
address_space_config m_program_config;
address_space_config m_data_config;
address_space_config m_io_config;
-
+
devcb_read_line m_bio_in;
typedef void ( tms32010_device::*opcode_func ) ();
diff --git a/src/devices/cpu/tms32025/tms32025.h b/src/devices/cpu/tms32025/tms32025.h
index 0d414c1cb4f..e112dafde51 100644
--- a/src/devices/cpu/tms32025/tms32025.h
+++ b/src/devices/cpu/tms32025/tms32025.h
@@ -31,7 +31,7 @@
#define MCFG_TMS32025_HOLD_ACK_OUT_CB(_devcb) \
devcb = &tms32025_device::set_hold_ack_out_cb(*device, DEVCB_##_devcb); /* HOLD Acknowledge output */
-
+
#define MCFG_TMS32025_XF_OUT_CB(_devcb) \
devcb = &tms32025_device::set_xf_out_cb(*device, DEVCB_##_devcb); /* XF output */
@@ -41,7 +41,7 @@
#define MCFG_TMS32025_DX_OUT_CB(_devcb) \
devcb = &tms32025_device::set_dx_out_cb(*device, DEVCB_##_devcb); /* Serial Data Transmit output */
-
+
/****************************************************************************
* Interrupt constants
*/
@@ -83,7 +83,7 @@ public:
// construction/destruction
tms32025_device(const machine_config &mconfig, const char *tag, device_t *owner, UINT32 clock);
tms32025_device(const machine_config &mconfig, device_type type, const char *name, const char *tag, device_t *owner, UINT32 clock, const char *shortname, const char *source);
-
+
// static configuration helpers
template<class _Object> static devcb_base & set_bio_in_cb(device_t &device, _Object object) { return downcast<tms32025_device &>(device).m_bio_in.set_callback(object); }
template<class _Object> static devcb_base & set_hold_in_cb(device_t &device, _Object object) { return downcast<tms32025_device &>(device).m_hold_in.set_callback(object); }
diff --git a/src/devices/imagedev/cassette.cpp b/src/devices/imagedev/cassette.cpp
index 5826f0abf58..313ef6b42a2 100644
--- a/src/devices/imagedev/cassette.cpp
+++ b/src/devices/imagedev/cassette.cpp
@@ -359,7 +359,7 @@ void cassette_image_device::call_unload()
//-------------------------------------------------
// display a small tape animation, with the
-// current position in the tape image
+// current position in the tape image
//-------------------------------------------------
std::string cassette_image_device::call_display()
@@ -389,10 +389,10 @@ std::string cassette_image_device::call_display()
? u8"\u25BA"
: u8"\u25CF";
- // Since you can have anything in a BDF file, we will use crude ascii characters instead
+ // Since you can have anything in a BDF file, we will use crude ascii characters instead
result = string_format("%s %s %02d:%02d (%04d) [%02d:%02d (%04d)]",
- shapes[n], // animation
- status_icon, // play or record
+ shapes[n], // animation
+ status_icon, // play or record
((int)position / 60),
((int)position % 60),
(int)position,
diff --git a/src/devices/machine/68230pit.cpp b/src/devices/machine/68230pit.cpp
index fe84888ffbf..ed9cfee7327 100644
--- a/src/devices/machine/68230pit.cpp
+++ b/src/devices/machine/68230pit.cpp
@@ -46,7 +46,7 @@ const device_type PIT68230 = &device_creator<pit68230_device>;
//-------------------------------------------------
pit68230_device::pit68230_device(const machine_config &mconfig, device_type type, const char *name, const char *tag, device_t *owner, UINT32 clock, UINT32 variant, const char *shortname, const char *source)
: device_t (mconfig, type, name, tag, owner, clock, shortname, source),
- device_execute_interface (mconfig, *this)
+ device_execute_interface (mconfig, *this)
, m_icount (0)
, m_pa_out_cb(*this)
, m_pa_in_cb(*this)
@@ -70,9 +70,9 @@ pit68230_device::pit68230_device(const machine_config &mconfig, device_type type
, m_psr(0)
, m_tcr(0)
, m_cpr(0)
- // , m_cprh(0)
- // , m_cprm(0)
- // , m_cprl(0)
+ // , m_cprh(0)
+ // , m_cprm(0)
+ // , m_cprl(0)
, m_cntr(0)
{
}
@@ -80,7 +80,7 @@ pit68230_device::pit68230_device(const machine_config &mconfig, device_type type
pit68230_device::pit68230_device(const machine_config &mconfig, const char *tag, device_t *owner, UINT32 clock)
: device_t (mconfig, PIT68230, "PIT68230", tag, owner, clock, "pit68230", __FILE__),
- device_execute_interface (mconfig, *this)
+ device_execute_interface (mconfig, *this)
, m_icount (0)
, m_pa_out_cb (*this)
, m_pa_in_cb(*this)
@@ -104,9 +104,9 @@ pit68230_device::pit68230_device(const machine_config &mconfig, const char *tag,
, m_psr(0)
, m_tcr(0)
, m_cpr(0)
- // , m_cprh(0)
- // , m_cprm(0)
- // , m_cprl(0)
+ // , m_cprh(0)
+ // , m_cprm(0)
+ // , m_cprl(0)
, m_cntr(0)
{
}
@@ -263,70 +263,70 @@ void pit68230_device::wr_pitreg_psr(UINT8 data)
/* The timer control register (TCR) determines all operations of the timer. Bits 7-5 configure the PC3/TOUT
and PC7/TIACKpins for port C, square wave, vectored interrupt, or autovectored interrupt operation bit
-4 specifies whether the counter receives data from the counter preload register or continues counting when
-zero detect is reached ; bit 3 is unused and is read as zero bits 2 and 1 configure the path from the CLK
-and TINpins to the counter controller ; and bit 0 ena-bles the timer. This register is readable and writable
-at all times. All bits are cleared to zero when the RESET pin is asserted.
+4 specifies whether the counter receives data from the counter preload register or continues counting when
+zero detect is reached ; bit 3 is unused and is read as zero bits 2 and 1 configure the path from the CLK
+and TINpins to the counter controller ; and bit 0 ena-bles the timer. This register is readable and writable
+at all times. All bits are cleared to zero when the RESET pin is asserted.
TCR bits
7 6 5 TOUT/TIACK Control
----------------------------
- 0 0 X The dual-function pins PC3/TOUT and PC7/TIACK carry the port C function.
- 0 1 X The dual-function pinPC3/TOUT carries the TOUT function. In the run state it is used as a squarewave
- output and is toggled on zero detect. The TOUT pin is high while in the halt state. The dualfunction
- pin PC7/TIACK carries the PC7 function.
- 1 0 0 The dual-function pin PC3/TOUT carries the TOUT function. In the run or halt state it is used as
- a timer interrupt request output. The timer interrupt is disabled, thus, the pin is always three stated.
- The dual-function pin PC7/TIACK carries the TIACK function ; however, since interrupt request is
- negated, the PI/T produces no response (i.e., no data or DTACK) to an asserted TIACK. Refer to
- 5.1.3. Timer Interrupt Acknowledge Cycles for details.
- 1 0 1 The dual-function pin PC3/TOUT carries the TOUTfunction and is used as a timer interrupt request
- output. The timer interrupt is enabled ; thus, the pin is low when the timer ZDS status bit is one.
- The dual-function pin PC7/TIACK carries the TIACK function and is used as a timer interrupt acknowledge
- input. Refer to the5.1.3. Timer InterruptAcknowledge Cycles fordetails. Thiscombination
- supports vectored timer interrupts.
- 1 1 0 The dual-function pin PC3/TOUT function. In the run or halt state it is used as a timer interrupt
- request output. The timer interrupt is disabled ; thus, the pin is always three-stated. The dual-function
- pin PC7/TIACK carries the PC7 function.
- 1 1 1 The dual-function pin PC3/TOUT carries the TOUTfunction and is used as a timer interrupt request
- output. The timer interrupt is enabled ; thus, the pin is low when the timer ZDS status bit is one.
- The dual-function pin PC7/TIACK carries the PC7 function and autovectored interrupts are supported.
+ 0 0 X The dual-function pins PC3/TOUT and PC7/TIACK carry the port C function.
+ 0 1 X The dual-function pinPC3/TOUT carries the TOUT function. In the run state it is used as a squarewave
+ output and is toggled on zero detect. The TOUT pin is high while in the halt state. The dualfunction
+ pin PC7/TIACK carries the PC7 function.
+ 1 0 0 The dual-function pin PC3/TOUT carries the TOUT function. In the run or halt state it is used as
+ a timer interrupt request output. The timer interrupt is disabled, thus, the pin is always three stated.
+ The dual-function pin PC7/TIACK carries the TIACK function ; however, since interrupt request is
+ negated, the PI/T produces no response (i.e., no data or DTACK) to an asserted TIACK. Refer to
+ 5.1.3. Timer Interrupt Acknowledge Cycles for details.
+ 1 0 1 The dual-function pin PC3/TOUT carries the TOUTfunction and is used as a timer interrupt request
+ output. The timer interrupt is enabled ; thus, the pin is low when the timer ZDS status bit is one.
+ The dual-function pin PC7/TIACK carries the TIACK function and is used as a timer interrupt acknowledge
+ input. Refer to the5.1.3. Timer InterruptAcknowledge Cycles fordetails. Thiscombination
+ supports vectored timer interrupts.
+ 1 1 0 The dual-function pin PC3/TOUT function. In the run or halt state it is used as a timer interrupt
+ request output. The timer interrupt is disabled ; thus, the pin is always three-stated. The dual-function
+ pin PC7/TIACK carries the PC7 function.
+ 1 1 1 The dual-function pin PC3/TOUT carries the TOUTfunction and is used as a timer interrupt request
+ output. The timer interrupt is enabled ; thus, the pin is low when the timer ZDS status bit is one.
+ The dual-function pin PC7/TIACK carries the PC7 function and autovectored interrupts are supported.
TCR bit 4 - Zero Detect Control
- 0 The counter is loaded fromthe counter preload register on the first clock to the 24-bit counter after
- zero detect, then resumes counting.
- 1 The counter rolls over on zero detect, then continues counting.
+ 0 The counter is loaded fromthe counter preload register on the first clock to the 24-bit counter after
+ zero detect, then resumes counting.
+ 1 The counter rolls over on zero detect, then continues counting.
TCR bit 3 - Unused and is always read as zero.
TCR bits
2 1 Clock Control
0 0 The PC2/TIN input pin carries the port C function, and the CLK pin and prescaler are used. The
- prescaler is decremented on the falling transition of the CLKpin ; the 24-bit counter is decremented,
- rolls over, or is loaded from the counter preload registers when the prescaler rolls over from $OO
- to $1F. The timer enable bit determines whether the timer is in the run or halt state.
- 0 1 The PC2/TIN pin serves as a timer input, and the CLK pin and prescaler are used. The prescaler
- is decremented on the falling transition of the CLK pin ; the 24-bit counter is decremented, rolls
- over, or is loaded from the counter preload registers when the prescaler rolls over from $00 to $1F.
- The timer is in the run state when the timer enable bit is one and the TIN pin is high ; otherwise,
- the timer is in the halt state.
- 1 0 The PC2/TIN pin serves as a timer input and the prescaler is used. The prescaler is decremented
- following the rising transition of the TIN pin after being synchronized with the internal clock. The
- 24-bit counter is decremented, rolls over, or is loaded from the counter preload registers when the
- prescaler rolls over from $00 to $1F. The timer enable bit determines whether the timer is in the
- run or halt state.
- 1 1 The PC2/TIN pin serves as a timer input and the prescaler is not used. The 24-bit counter is decremented,
- rolls over, or is loaded from the counter preload registers following the rising edge of
- the TIN pin after being synchronized with the internal clock. The timer enable bit determines whether
- the timer is in the run or halt state.
+ prescaler is decremented on the falling transition of the CLKpin ; the 24-bit counter is decremented,
+ rolls over, or is loaded from the counter preload registers when the prescaler rolls over from $OO
+ to $1F. The timer enable bit determines whether the timer is in the run or halt state.
+ 0 1 The PC2/TIN pin serves as a timer input, and the CLK pin and prescaler are used. The prescaler
+ is decremented on the falling transition of the CLK pin ; the 24-bit counter is decremented, rolls
+ over, or is loaded from the counter preload registers when the prescaler rolls over from $00 to $1F.
+ The timer is in the run state when the timer enable bit is one and the TIN pin is high ; otherwise,
+ the timer is in the halt state.
+ 1 0 The PC2/TIN pin serves as a timer input and the prescaler is used. The prescaler is decremented
+ following the rising transition of the TIN pin after being synchronized with the internal clock. The
+ 24-bit counter is decremented, rolls over, or is loaded from the counter preload registers when the
+ prescaler rolls over from $00 to $1F. The timer enable bit determines whether the timer is in the
+ run or halt state.
+ 1 1 The PC2/TIN pin serves as a timer input and the prescaler is not used. The 24-bit counter is decremented,
+ rolls over, or is loaded from the counter preload registers following the rising edge of
+ the TIN pin after being synchronized with the internal clock. The timer enable bit determines whether
+ the timer is in the run or halt state.
TCR bit 0 - Timer Enable
- 0 Disabled
- 1 Enabled
+ 0 Disabled
+ 1 Enabled
*/
void pit68230_device::wr_pitreg_tcr(UINT8 data)
{
- LOG(("%s(%02x) \"%s\": %s - %02x Timer %s\n",
- FUNCNAME, data, m_owner->tag(), FUNCNAME, data, data & REG_TCR_ENABLE ? "enabled" : "disabled"));
+ LOG(("%s(%02x) \"%s\": %s - %02x Timer %s\n",
+ FUNCNAME, data, m_owner->tag(), FUNCNAME, data, data & REG_TCR_ENABLE ? "enabled" : "disabled"));
m_tcr = data;
}
@@ -335,7 +335,7 @@ void pit68230_device::wr_pitreg_cprh(UINT8 data)
LOG(("%s(%02x) \"%s\": %s - %02x\n", FUNCNAME, data, m_owner->tag(), FUNCNAME, data));
m_cpr &= ~0xff0000;
m_cpr |= ((data << 16) & 0xff0000);
- // m_cprh = data;
+ // m_cprh = data;
}
void pit68230_device::wr_pitreg_cprm(UINT8 data)
@@ -343,7 +343,7 @@ void pit68230_device::wr_pitreg_cprm(UINT8 data)
LOG(("%s(%02x) \"%s\": %s - %02x\n", FUNCNAME, data, m_owner->tag(), FUNCNAME, data));
m_cpr &= ~0x00ff00;
m_cpr |= ((data << 8) & 0x00ff00);
- // m_cprm = data;
+ // m_cprm = data;
}
void pit68230_device::wr_pitreg_cprl(UINT8 data)
@@ -351,28 +351,28 @@ void pit68230_device::wr_pitreg_cprl(UINT8 data)
LOG(("%s(%02x) \"%s\": %s - %02x\n", FUNCNAME, data, m_owner->tag(), FUNCNAME, data));
m_cpr &= ~0x0000ff;
m_cpr |= ((data << 0) & 0x0000ff);
- // m_cprl = data;
+ // m_cprl = data;
}
WRITE8_MEMBER (pit68230_device::write)
{
LOG(("%s %s \n",tag(), FUNCNAME));
switch (offset) {
- case PIT_68230_PGCR: wr_pitreg_pgcr(data); break;
- case PIT_68230_PSRR: wr_pitreg_psrr(data); break;
- case PIT_68230_PADDR: wr_pitreg_paddr(data); break;
- case PIT_68230_PBDDR: wr_pitreg_pbddr(data); break;
- case PIT_68230_PCDDR: wr_pitreg_pcddr(data); break;
- case PIT_68230_PACR: wr_pitreg_pacr(data); break;
- case PIT_68230_PBCR: wr_pitreg_pbcr(data); break;
- case PIT_68230_PADR: wr_pitreg_padr(data); break;
- case PIT_68230_PAAR: break; // RO register so ignored
- case PIT_68230_PBAR: break; // RO register so ignored
- case PIT_68230_PSR: wr_pitreg_psr(data); break;
- case PIT_68230_TCR: wr_pitreg_tcr(data); break;
- case PIT_68230_CPRH: wr_pitreg_cprh(data); break;
- case PIT_68230_CPRM: wr_pitreg_cprm(data); break;
- case PIT_68230_CPRL: wr_pitreg_cprl(data); break;
+ case PIT_68230_PGCR: wr_pitreg_pgcr(data); break;
+ case PIT_68230_PSRR: wr_pitreg_psrr(data); break;
+ case PIT_68230_PADDR: wr_pitreg_paddr(data); break;
+ case PIT_68230_PBDDR: wr_pitreg_pbddr(data); break;
+ case PIT_68230_PCDDR: wr_pitreg_pcddr(data); break;
+ case PIT_68230_PACR: wr_pitreg_pacr(data); break;
+ case PIT_68230_PBCR: wr_pitreg_pbcr(data); break;
+ case PIT_68230_PADR: wr_pitreg_padr(data); break;
+ case PIT_68230_PAAR: break; // RO register so ignored
+ case PIT_68230_PBAR: break; // RO register so ignored
+ case PIT_68230_PSR: wr_pitreg_psr(data); break;
+ case PIT_68230_TCR: wr_pitreg_tcr(data); break;
+ case PIT_68230_CPRH: wr_pitreg_cprh(data); break;
+ case PIT_68230_CPRM: wr_pitreg_cprm(data); break;
+ case PIT_68230_CPRL: wr_pitreg_cprl(data); break;
default:
LOG (("Unhandled Write of %02x to register %02x", data, offset));
}
@@ -458,22 +458,22 @@ UINT8 pit68230_device::rr_pitreg_pbdr()
return m_pbdr;
}
-/* The port A alternate register is an alternate register for reading the port A pins.
+/* The port A alternate register is an alternate register for reading the port A pins.
It is a read-only address and no other PI/T condition is affected. In all modes,
-the instantaneous pin level is read and no input latching is performed except at the
+the instantaneous pin level is read and no input latching is performed except at the
data bus interface. Writes to this address are answered with DTACK, but the data is ignored.*/
UINT8 pit68230_device::rr_pitreg_paar()
{
- // NOTE: no side effect emulated so using ..padr
+ // NOTE: no side effect emulated so using ..padr
UINT8 ret;
ret = m_pa_in_cb();
LOGR(("%s %s <- %02x\n",tag(), FUNCNAME, ret));
return ret;
}
-/* The port B alternate register is an alternate register for reading the port B pins.
+/* The port B alternate register is an alternate register for reading the port B pins.
It is a read-only address and no other PI/T condition is affected. In all modes,
-the instantaneous pin level is read and no input latching is performed except at the
+the instantaneous pin level is read and no input latching is performed except at the
data bus interface.Writes to this address are answered with DTACK, but the data is ignored.*/
UINT8 pit68230_device::rr_pitreg_pbar()
{
@@ -518,21 +518,21 @@ READ8_MEMBER (pit68230_device::read){
UINT8 data;
switch (offset) {
- case PIT_68230_PGCR: data = rr_pitreg_pgcr(); break;
- case PIT_68230_PSRR: data = rr_pitreg_psrr(); break;
- case PIT_68230_PADDR: data = rr_pitreg_paddr(); break;
- case PIT_68230_PBDDR: data = rr_pitreg_pbddr(); break;
- case PIT_68230_PCDDR: data = rr_pitreg_pcddr(); break;
- case PIT_68230_PACR: data = rr_pitreg_pacr(); break;
- case PIT_68230_PBCR: data = rr_pitreg_pbcr(); break;
- case PIT_68230_PADR: data = rr_pitreg_padr(); break;
- case PIT_68230_PBDR: data = rr_pitreg_pbdr(); break;
- case PIT_68230_PAAR: data = rr_pitreg_paar(); break;
- case PIT_68230_PBAR: data = rr_pitreg_pbar(); break;
- case PIT_68230_PSR: data = rr_pitreg_psr(); break;
- case PIT_68230_CNTRH: data = rr_pitreg_cntrh(); break;
- case PIT_68230_CNTRM: data = rr_pitreg_cntrm(); break;
- case PIT_68230_CNTRL: data = rr_pitreg_cntrl(); break;
+ case PIT_68230_PGCR: data = rr_pitreg_pgcr(); break;
+ case PIT_68230_PSRR: data = rr_pitreg_psrr(); break;
+ case PIT_68230_PADDR: data = rr_pitreg_paddr(); break;
+ case PIT_68230_PBDDR: data = rr_pitreg_pbddr(); break;
+ case PIT_68230_PCDDR: data = rr_pitreg_pcddr(); break;
+ case PIT_68230_PACR: data = rr_pitreg_pacr(); break;
+ case PIT_68230_PBCR: data = rr_pitreg_pbcr(); break;
+ case PIT_68230_PADR: data = rr_pitreg_padr(); break;
+ case PIT_68230_PBDR: data = rr_pitreg_pbdr(); break;
+ case PIT_68230_PAAR: data = rr_pitreg_paar(); break;
+ case PIT_68230_PBAR: data = rr_pitreg_pbar(); break;
+ case PIT_68230_PSR: data = rr_pitreg_psr(); break;
+ case PIT_68230_CNTRH: data = rr_pitreg_cntrh(); break;
+ case PIT_68230_CNTRM: data = rr_pitreg_cntrm(); break;
+ case PIT_68230_CNTRL: data = rr_pitreg_cntrl(); break;
default:
LOG (("Unhandled read register %02x\n", offset));
data = 0;
diff --git a/src/devices/machine/68230pit.h b/src/devices/machine/68230pit.h
index 7712419f7fc..736868afa66 100644
--- a/src/devices/machine/68230pit.h
+++ b/src/devices/machine/68230pit.h
@@ -105,7 +105,7 @@
//**************************************************************************
class pit68230_device : public device_t, public device_execute_interface
{
- public:
+ public:
// construction/destruction
pit68230_device(const machine_config &mconfig, device_type type, const char *name, const char *tag, device_t *owner, UINT32 clock, UINT32 variant, const char *shortname, const char *source);
pit68230_device(const machine_config &mconfig, const char *tag, device_t *owner, UINT32 clock);
@@ -161,7 +161,7 @@ class pit68230_device : public device_t, public device_execute_interface
protected:
enum {
- REG_TCR_ENABLE = 0x01
+ REG_TCR_ENABLE = 0x01
};
// device-level overrides
@@ -171,16 +171,16 @@ protected:
virtual void execute_run () override;
int m_icount;
- devcb_write8 m_pa_out_cb;
- devcb_read8 m_pa_in_cb;
- devcb_write8 m_pb_out_cb;
- devcb_read8 m_pb_in_cb;
- devcb_write8 m_pc_out_cb;
- devcb_read8 m_pc_in_cb;
- devcb_write_line m_h1_out_cb;
- devcb_write_line m_h2_out_cb;
- devcb_write_line m_h3_out_cb;
- devcb_write_line m_h4_out_cb;
+ devcb_write8 m_pa_out_cb;
+ devcb_read8 m_pa_in_cb;
+ devcb_write8 m_pb_out_cb;
+ devcb_read8 m_pb_in_cb;
+ devcb_write8 m_pc_out_cb;
+ devcb_read8 m_pc_in_cb;
+ devcb_write_line m_h1_out_cb;
+ devcb_write_line m_h2_out_cb;
+ devcb_write_line m_h3_out_cb;
+ devcb_write_line m_h4_out_cb;
// peripheral ports
UINT8 m_pgcr; // Port General Control register
@@ -193,12 +193,12 @@ protected:
UINT8 m_padr; // Port A Data register
UINT8 m_pbdr; // Port B Data register
UINT8 m_psr; // Port Status Register
- UINT8 m_tcr; // Timer Control Register
- int m_cpr; // Counter Preload Registers (3 x 8 = 24 bits)
- // UINT8 m_cprh; // Counter Preload Register High
- // UINT8 m_cprm; // Counter Preload Register Mid
- // UINT8 m_cprl; // Counter Preload Register Low
- int m_cntr; // - The 24 bit Counter
+ UINT8 m_tcr; // Timer Control Register
+ int m_cpr; // Counter Preload Registers (3 x 8 = 24 bits)
+ // UINT8 m_cprh; // Counter Preload Register High
+ // UINT8 m_cprm; // Counter Preload Register Mid
+ // UINT8 m_cprl; // Counter Preload Register Low
+ int m_cntr; // - The 24 bit Counter
};
// device type definition
diff --git a/src/devices/machine/8530scc.cpp b/src/devices/machine/8530scc.cpp
index be3bbf6ed6d..bf1c5e09203 100644
--- a/src/devices/machine/8530scc.cpp
+++ b/src/devices/machine/8530scc.cpp
@@ -480,8 +480,8 @@ UINT8 scc8530_t::read_reg(int offset)
switch(offset)
{
- case 0: /* Channel B (Printer Port) Control */
- case 1: /* Channel A (Modem Port) Control */
+ case 0: /* Channel B (Printer Port) Control */
+ case 1: /* Channel A (Modem Port) Control */
if (mode == 1)
mode = 0;
@@ -491,7 +491,7 @@ UINT8 scc8530_t::read_reg(int offset)
result = (offset == 0) ? getbreg() : getareg();
break;
- case 2: /* Channel B (Printer Port) Data */
+ case 2: /* Channel B (Printer Port) Data */
case 3:/* Channel A (Modem Port) Data */
result = channel[offset == 2 ? 1 : 0].rxData;
break;
@@ -527,8 +527,8 @@ void scc8530_t::write_reg(int offset, UINT8 data)
//Chan *pChan;
switch(offset)
{
- case 0: /* Channel B (Printer Port) Control */
- case 1: /* Channel A (Modem Port) Control */
+ case 0: /* Channel B (Printer Port) Control */
+ case 1: /* Channel A (Modem Port) Control */
{
int chan = ((offset == 2) ? 1 : 0);
if (mode == 0)
@@ -537,7 +537,7 @@ void scc8530_t::write_reg(int offset, UINT8 data)
{
mode = 1;
reg = data & 0x0f;
-// putbreg(data & 0xf0);
+// putbreg(data & 0xf0);
}
else if (data == 0x10)
{
@@ -555,8 +555,8 @@ void scc8530_t::write_reg(int offset, UINT8 data)
break;
}
- case 2: /* Channel B (Printer Port) Data */
- case 3: /* Channel A (Modem Port) Data */
+ case 2: /* Channel B (Printer Port) Data */
+ case 3: /* Channel A (Modem Port) Data */
{
int chan = ((offset == 2) ? 1 : 0);
if (channel[chan].txEnable)
diff --git a/src/devices/machine/eeprom.h b/src/devices/machine/eeprom.h
index 02dd2eaf6de..7fdcc8cd473 100644
--- a/src/devices/machine/eeprom.h
+++ b/src/devices/machine/eeprom.h
@@ -44,7 +44,7 @@
// ======================> eeprom_base_device
class eeprom_base_device : public device_t,
- public device_nvram_interface
+ public device_nvram_interface
{
protected:
// construction/destruction
diff --git a/src/devices/machine/ldp1000.cpp b/src/devices/machine/ldp1000.cpp
index abfa23913b0..df211f56d5a 100644
--- a/src/devices/machine/ldp1000.cpp
+++ b/src/devices/machine/ldp1000.cpp
@@ -2,12 +2,12 @@
// copyright-holders:Angelo Salese
/***************************************************************************
- Sony LDP-1000 laserdisc emulation.
+ Sony LDP-1000 laserdisc emulation.
- TODO:
- - Dump BIOSes (seven of them according to docs);
- - Serial interface, needs BIOS dump;
- - Hookup with Sony SMC-70 / SMC-777;
+ TODO:
+ - Dump BIOSes (seven of them according to docs);
+ - Serial interface, needs BIOS dump;
+ - Hookup with Sony SMC-70 / SMC-777;
***************************************************************************/
@@ -71,7 +71,7 @@ void sony_ldp1000_device::device_start()
void sony_ldp1000_device::device_reset()
{
laserdisc_device::device_reset();
-
+
for(int i=0;i<0x10;i++)
m_internal_bcd[i] = 0;
@@ -152,12 +152,12 @@ UINT32 sony_ldp1000_device::bcd_to_raw()
void sony_ldp1000_device::exec_enter_cmd()
{
//const UINT32 saved_frame = bcd_to_raw();
-
+
switch(m_player_state)
{
case player_standby:
throw emu_fatalerror("Unimplemented standby state detected");
-
+
case player_search:
// TODO: move to timer
//advance_slider(1);
@@ -187,18 +187,18 @@ WRITE8_MEMBER( sony_ldp1000_device::command_w )
exec_enter_cmd();
m_status = stat_ack;
break;
-
+
case 0x43: // search
set_new_player_state(player_search);
m_status = stat_ack;
break;
-
+
/*
- audio channels absolute enable / disable
- ---- --x- select channel
- ---- ---x enable channel (active low)
+ audio channels absolute enable / disable
+ ---- --x- select channel
+ ---- ---x enable channel (active low)
*/
- case 0x46:
+ case 0x46:
case 0x47:
case 0x48:
case 0x49:
diff --git a/src/devices/machine/ldp1000.h b/src/devices/machine/ldp1000.h
index 142886da936..e759442fa57 100644
--- a/src/devices/machine/ldp1000.h
+++ b/src/devices/machine/ldp1000.h
@@ -2,7 +2,7 @@
// copyright-holders:Angelo Salese
/***************************************************************************
- Sony LDP-1000 laserdisc emulation.
+ Sony LDP-1000 laserdisc emulation.
***************************************************************************/
@@ -46,27 +46,27 @@ protected:
virtual void device_start() override;
virtual void device_reset() override;
virtual const rom_entry *device_rom_region() const override;
-
+
virtual void player_vsync(const vbi_metadata &vbi, int fieldnum, const attotime &curtime) override;
virtual INT32 player_update(const vbi_metadata &vbi, int fieldnum, const attotime &curtime) override;
virtual void player_overlay(bitmap_yuy16 &bitmap) override { }
enum ldp1000_status {
- stat_undef = 0x00,
- stat_completion = 0x01,
- stat_error = 0x02,
- stat_pgm_end = 0x04,
- stat_not_target = 0x05,
- stat_no_frame = 0x06,
- stat_ack = 0x0a,
- stat_nak = 0x0b
+ stat_undef = 0x00,
+ stat_completion = 0x01,
+ stat_error = 0x02,
+ stat_pgm_end = 0x04,
+ stat_not_target = 0x05,
+ stat_no_frame = 0x06,
+ stat_ack = 0x0a,
+ stat_nak = 0x0b
};
enum ldp1000_player_state {
player_standby = 0,
player_search
};
-
+
private:
UINT8 m_command;
ldp1000_status m_status;
@@ -79,7 +79,7 @@ private:
void exec_enter_cmd();
UINT8 m_internal_bcd[0x10];
UINT8 m_index_state;
-
+
};
diff --git a/src/devices/machine/ldv1000.cpp b/src/devices/machine/ldv1000.cpp
index 27c874eadf7..fb4cec974dd 100644
--- a/src/devices/machine/ldv1000.cpp
+++ b/src/devices/machine/ldv1000.cpp
@@ -176,7 +176,7 @@ void pioneer_ldv1000_device::device_start()
// allocate timers
m_multitimer = timer_alloc(TID_MULTIJUMP);
-
+
m_command_strobe_cb.resolve_safe();
}
@@ -653,7 +653,7 @@ WRITE8_MEMBER( pioneer_ldv1000_device::ppi1_portc_w )
// bit 4 sends a command strobe signal to Host CPU
m_command_strobe_cb(bool(data & 0x10));
-
+
// video squelch is controlled by bit 3
set_video_squelch((data & 0x08) == 0);
diff --git a/src/devices/machine/ldv1000.h b/src/devices/machine/ldv1000.h
index c7d798d89df..36f84f096a1 100644
--- a/src/devices/machine/ldv1000.h
+++ b/src/devices/machine/ldv1000.h
@@ -129,7 +129,7 @@ protected:
UINT8 m_vbi[7*3]; /* VBI data */
bool m_vbiready; /* VBI ready flag */
UINT8 m_vbiindex; /* index within the VBI data */
-
+
};
diff --git a/src/devices/machine/pci-ide.cpp b/src/devices/machine/pci-ide.cpp
index e6c18219e0d..0f3f6f8cbb6 100644
--- a/src/devices/machine/pci-ide.cpp
+++ b/src/devices/machine/pci-ide.cpp
@@ -132,7 +132,6 @@ WRITE_LINE_MEMBER(ide_pci_device::ide_interrupt)
// PCI646U2 Offset 0x50 is interrupt status
if (main_id == 0x10950646) {
-
if (state)
m_config_data[0x10 / 4] |= 0x4;
else
diff --git a/src/devices/machine/scnxx562.cpp b/src/devices/machine/scnxx562.cpp
index 099a8c6cdea..e4e388eade4 100644
--- a/src/devices/machine/scnxx562.cpp
+++ b/src/devices/machine/scnxx562.cpp
@@ -4,37 +4,37 @@
DUSCC Dual Serial Communications Controller emulation
The DUSCC was introduced in the mid 80:ies by Signetics, a part of Philips
- Semiconductor that later became NXP, and apparantly trying to dig into
+ Semiconductor that later became NXP, and apparantly trying to dig into
the huge success of the Zilog SCC with a very similar feature set but not
- software compatible at all.
+ software compatible at all.
The variants in the DUSCC family are as follows:
- Bus type
- Intel Motorola
+ Bus type
+ Intel Motorola
----------------------------------
- NMOS 26562 68562
- CMOS 26C562 68C562
+ NMOS 26562 68562
+ CMOS 26C562 68C562
----------------------------------
- For more info see:
+ For more info see:
page 511: http://bitsavers.informatik.uni-stuttgart.de/pdf/signetics/_dataBooks/1986_Signetics_Microprocessor.pdf
page 514: http://bitsavers.informatik.uni-stuttgart.de/pdf/signetics/_dataBooks/1994_Signetics_Data_Communications.pdf
Designs known of including one or more DUSCCs
------------------------------------------------
- Force Computers
+ Force Computers
CPU VME boards: CPU-22, CPU-26, CPU-30, CPU-33, CPU-386, CPU-40, CPU-41
- Graphics VME boards: AGC-1
+ Graphics VME boards: AGC-1
Serial VME boards: ISIO-1, ISIO-2
Digital Equipment
DEC MicroServer DEMSA, DECrouter-150, DECrouter-250
------------------------------------------------
TODO/ "NDUSCC" "CDUSCC"
-DONE (x) (p=partly) NMOS CMOS
+DONE (x) (p=partly) NMOS CMOS
------------------------------------------------
- Channels 2 FD 2 FD
- Synch data rates 4Mbps 10Mbps
+ Channels 2 FD 2 FD
+ Synch data rates 4Mbps 10Mbps
----- asynchrounous features ------------------
p 5-8 bit per char Y Y
y 1,1.5,2 stop bits Y Y in 1/16 bit increments
@@ -42,7 +42,7 @@ DONE (x) (p=partly) NMOS CMOS
x1,x16 Y Y
break det/gen Y Y
parity, framing & Y Y
- overrun error det
+ overrun error det
-- byte oriented synchrounous features --
Int/ext char sync Y Y
1/2 synch chars ? ?
@@ -58,7 +58,7 @@ DONE (x) (p=partly) NMOS CMOS
--
Receiver FIFO 4 16
Transmitter FIFO 4 16
- NRZ, NRZI, FM1 or Y Y
+ NRZ, NRZI, FM1 or Y Y
FM2 enc/dec
Manchester dec Y Y
Baud gen per chan Y Y
@@ -72,7 +72,7 @@ DONE (x) (p=partly) NMOS CMOS
TxFifo Empty status N Y
Interrupt enable bits N Y
X.21 pattern recogn N Y
- Improved BiSync support N Y
+ Improved BiSync support N Y
-------------------------------------------------------------------------
x/p = Features that has been implemented n/a = features that will not
***************************************************************************/
@@ -88,7 +88,7 @@ DONE (x) (p=partly) NMOS CMOS
#define VERBOSE 2
#define LOG(x) do { if (VERBOSE) logerror x; } while (0)
-#define LOGR(x)
+#define LOGR(x)
#if VERBOSE == 0
#define logerror printf
#endif
@@ -108,12 +108,12 @@ DONE (x) (p=partly) NMOS CMOS
// DEVICE DEFINITIONS
//**************************************************************************
// device type definition
-const device_type DUSCC = &device_creator<duscc_device>;
+const device_type DUSCC = &device_creator<duscc_device>;
const device_type DUSCC_CHANNEL = &device_creator<duscc_channel>;
-const device_type DUSCC26562 = &device_creator<duscc26562_device>;
-const device_type DUSCC26C562 = &device_creator<duscc26C562_device>;
-const device_type DUSCC68562 = &device_creator<duscc68562_device>;
-const device_type DUSCC68C562 = &device_creator<duscc68C562_device>;
+const device_type DUSCC26562 = &device_creator<duscc26562_device>;
+const device_type DUSCC26C562 = &device_creator<duscc26C562_device>;
+const device_type DUSCC68562 = &device_creator<duscc68562_device>;
+const device_type DUSCC68C562 = &device_creator<duscc68C562_device>;
//-------------------------------------------------
// device_mconfig_additions -
@@ -137,7 +137,7 @@ machine_config_constructor duscc_device::device_mconfig_additions() const
//-------------------------------------------------
duscc_device::duscc_device(const machine_config &mconfig, device_type type, const char *name, const char *tag, device_t *owner, UINT32 clock, UINT32 variant, const char *shortname, const char *source)
: device_t(mconfig, type, name, tag, owner, clock, shortname, source),
- // device_z80daisy_interface(mconfig, *this),
+ // device_z80daisy_interface(mconfig, *this),
m_chanA(*this, CHANA_TAG),
m_chanB(*this, CHANB_TAG),
#if 0
@@ -233,7 +233,7 @@ void duscc_device::device_reset()
void duscc_device::check_interrupts()
{
LOG(("%s %s - not implemented\n",tag(), FUNCNAME));
- // m_out_int_cb(state);
+ // m_out_int_cb(state);
}
@@ -313,10 +313,10 @@ duscc_channel::duscc_channel(const machine_config &mconfig, const char *tag, dev
LOG(("%s\n",FUNCNAME));
// Reset all registers
- m_cmr1 = m_cmr2 = m_s1r = m_s2r = m_tpr = m_ttr = m_rpr = m_rtr
- = m_ctprh = m_ctprl = m_ctcr = m_omr = m_cth = m_ctl = m_pcr
+ m_cmr1 = m_cmr2 = m_s1r = m_s2r = m_tpr = m_ttr = m_rpr = m_rtr
+ = m_ctprh = m_ctprl = m_ctcr = m_omr = m_cth = m_ctl = m_pcr
= m_ccr = m_rsr = m_trsr = m_ictsr = m_gsr = m_ier /* = m_rea */
- = m_cid = m_ivr = m_icr = /*m_sea =*/ m_ivrm = m_mrr = m_ier1
+ = m_cid = m_ivr = m_icr = /*m_sea =*/ m_ivrm = m_mrr = m_ier1
= m_ier2 = m_ier3 = m_trcr = m_rflr = m_ftlr = m_trmsr = m_telr = 0;
for (int i = 0; i < sizeof(m_rx_data_fifo); i++)
@@ -373,11 +373,11 @@ void duscc_channel::device_start()
save_item(NAME(m_ictsr));
save_item(NAME(m_gsr)); // TODO: Move this to the device instead, it is a global register
save_item(NAME(m_ier));
- // save_item(NAME(m_rea));
+ // save_item(NAME(m_rea));
save_item(NAME(m_cid));
save_item(NAME(m_ivr));
save_item(NAME(m_icr));
- // save_item(NAME(m_sea));
+ // save_item(NAME(m_sea));
save_item(NAME(m_ivrm));
save_item(NAME(m_mrr));
save_item(NAME(m_ier1));
@@ -422,37 +422,37 @@ void duscc_channel::device_reset()
transmit_register_reset();
// Soft/Channel Reset values according to DUSCC users guide
- m_cmr1 =0x00;
- m_cmr2 =0x00;
- m_s1r =0x00;
- m_s2r =0x00;
- m_tpr =0x00;
- m_ttr =0x00;
- m_rpr =0x00;
- m_rtr =0x00;
- m_ctcr =0x00;
- m_omr =0x00;
- m_pcr =0x00;
- m_ccr =0x00;
- m_rsr =0x00;
- m_trsr =0x00;
- m_ictsr =0x00;
- m_gsr =0x00;
- m_ier =0x00;
- // m_rea =0x00;
- m_ivr =0x0f;
- m_icr =0x00;
- // m_sea =0x00;
- m_ivrm =0x00;
- m_mrr =0x00; // TODO: Need a read after reset to enable CMOS features
- m_ier1 =0x00;
- m_ier2 =0x00;
- m_ier3 =0x00;
- m_trcr =0x00;
- m_rflr =0x00;
- m_ftlr =0x33;
- m_trmsr =0x00;
- m_telr =0x10;
+ m_cmr1 =0x00;
+ m_cmr2 =0x00;
+ m_s1r =0x00;
+ m_s2r =0x00;
+ m_tpr =0x00;
+ m_ttr =0x00;
+ m_rpr =0x00;
+ m_rtr =0x00;
+ m_ctcr =0x00;
+ m_omr =0x00;
+ m_pcr =0x00;
+ m_ccr =0x00;
+ m_rsr =0x00;
+ m_trsr =0x00;
+ m_ictsr =0x00;
+ m_gsr =0x00;
+ m_ier =0x00;
+ // m_rea =0x00;
+ m_ivr =0x0f;
+ m_icr =0x00;
+ // m_sea =0x00;
+ m_ivrm =0x00;
+ m_mrr =0x00; // TODO: Need a read after reset to enable CMOS features
+ m_ier1 =0x00;
+ m_ier2 =0x00;
+ m_ier3 =0x00;
+ m_trcr =0x00;
+ m_rflr =0x00;
+ m_ftlr =0x33;
+ m_trmsr =0x00;
+ m_telr =0x10;
// reset external lines TODO: check relation to control bits and reset
set_rts(1);
@@ -502,7 +502,7 @@ void duscc_channel::tra_callback()
//------------------------------------------
// tra_complete -
-// TODO:
+// TODO:
// - Fix mark and space tx support
//------------------------------------------
@@ -513,7 +513,7 @@ void duscc_channel::tra_complete()
if (m_tx_fifo_rp != m_tx_fifo_wp) // there are more characters to send?
{
transmit_register_setup(m_tx_data_fifo[m_tx_fifo_rp]); // Reload the shift register
- m_tx_fifo_rp_step();
+ m_tx_fifo_rp_step();
}
if (m_omr & REG_OMR_TXRDY_ACTIVATED)// Wait until FIFO empty before ready for more data?
{
@@ -598,7 +598,7 @@ void duscc_channel::set_rts(int state)
* or 2 stop bits. It is also dependent on the data bit length
* TODO: Support finer granularity of stop bits in diserial if/when nessesarry
* ---------------------------------------------------------------------------
- * TPR[4:7] TPR[0:1]
+ * TPR[4:7] TPR[0:1]
* 5 bits 6-8 bits
* 00 01,10,11
* ---------------------------
@@ -622,16 +622,16 @@ void duscc_channel::set_rts(int state)
*/
device_serial_interface::stop_bits_t duscc_channel::get_stop_bits()
{
- const stop_bits_t bits5[] =
+ const stop_bits_t bits5[] =
{ STOP_BITS_1, STOP_BITS_1, STOP_BITS_1, STOP_BITS_1, STOP_BITS_1_5, STOP_BITS_1_5, STOP_BITS_1_5, STOP_BITS_1_5,
- STOP_BITS_1_5, STOP_BITS_1_5, STOP_BITS_1_5, STOP_BITS_2, STOP_BITS_2, STOP_BITS_2, STOP_BITS_2, STOP_BITS_2 };
- const stop_bits_t bits6to8[] =
+ STOP_BITS_1_5, STOP_BITS_1_5, STOP_BITS_1_5, STOP_BITS_2, STOP_BITS_2, STOP_BITS_2, STOP_BITS_2, STOP_BITS_2 };
+ const stop_bits_t bits6to8[] =
{ STOP_BITS_1, STOP_BITS_1, STOP_BITS_1, STOP_BITS_1, STOP_BITS_1, STOP_BITS_1, STOP_BITS_1, STOP_BITS_1,
- STOP_BITS_1, STOP_BITS_1_5, STOP_BITS_1_5, STOP_BITS_2, STOP_BITS_2, STOP_BITS_2, STOP_BITS_2, STOP_BITS_2 };
+ STOP_BITS_1, STOP_BITS_1_5, STOP_BITS_1_5, STOP_BITS_2, STOP_BITS_2, STOP_BITS_2, STOP_BITS_2, STOP_BITS_2 };
/* 5 data bits */
if (get_tx_word_length() == 5)
- {
+ {
return bits5[((m_tpr & REG_TPR_STOP_BITS_MASK) >> 4) & 0x0f];
}
else /* 6-8 data bits */
@@ -651,7 +651,7 @@ int duscc_channel::get_rx_word_length()
int bits = 5;
switch (m_rpr & REG_RPR_DATA_BITS_MASK)
- {
+ {
case REG_RPR_DATA_BITS_5BIT: bits = 5; break;
case REG_RPR_DATA_BITS_6BIT: bits = 6; break;
case REG_RPR_DATA_BITS_7BIT: bits = 7; break;
@@ -671,7 +671,7 @@ int duscc_channel::get_tx_word_length()
int bits = 5;
switch (m_tpr & REG_TPR_DATA_BITS_MASK)
- {
+ {
case REG_TPR_DATA_BITS_5BIT: bits = 5; break;
case REG_TPR_DATA_BITS_6BIT: bits = 6; break;
case REG_TPR_DATA_BITS_7BIT: bits = 7; break;
@@ -700,13 +700,13 @@ UINT8 duscc_channel::do_dusccreg_pcr_r(){ logerror("register access method %s is
/* Commands to the DUSCC are entered through the channel command register.A read of this
register returns the last invoked command (with bits 4 and 5 set to 1). */
UINT8 duscc_channel::do_dusccreg_ccr_r()
-{
+{
LOG(("%s\n", FUNCNAME));
- return (UINT8) m_ccr | 1 << 4 | 1 << 5;
+ return (UINT8) m_ccr | 1 << 4 | 1 << 5;
}
UINT8 duscc_channel::do_dusccreg_rxfifo_r()
-{
+{
UINT8 data = 0;
LOG(("%s\n", FUNCNAME));
@@ -725,48 +725,48 @@ UINT8 duscc_channel::do_dusccreg_rxfifo_r()
LOG(("- RX FIFO empty despite RxREADY\n"));
}
- return (UINT8) data;
+ return (UINT8) data;
}
UINT8 duscc_channel::do_dusccreg_rsr_r(){ logerror("register access method %s is not implemented yet\n", FUNCNAME); return (UINT8) 0; }
UINT8 duscc_channel::do_dusccreg_trsr_r(){ logerror("register access method %s is not implemented yet\n", FUNCNAME); return (UINT8) 0; }
UINT8 duscc_channel::do_dusccreg_ictsr_r()
-{
- logerror("register access method %s is not implemented yet\n", FUNCNAME);
- return (UINT8) m_ictsr;
+{
+ logerror("register access method %s is not implemented yet\n", FUNCNAME);
+ return (UINT8) m_ictsr;
}
/* General Status Register (GSR)
This register provides a 'quick look' at the overall status of both channels of the DUSCC. A write to this register with ls at the
corresponding bit pOSitions causes TxRDY (bits 5 and 1) and/or RxRDY (bits 4 and 0) to be reset. The other status bits can be reset
- only by resetting the individual status bits that they point to.
- [7] Channel B External or Counter/timer Status - This bit indicates that one of the following status bits is asserted: ICTSRB[6:4]
- [6] Channel B Receiver or Transmitter Status - This bit indicates that one of the following status bits is asserted: TRSRB[7:1], TRSRB[7:3].
- [5] Channel B Transmitter Ready - The assertion of this bit indicates that one or more characters may be loaded into the Channel B transmitter
- FIFO to be serialized by the transmit shift register. See description of OMR[4j. This bit can be asserted only when the transmitter is enabled.
- Resetting the transmitter negates TxRDY.
- [4] Channel B Receiver Ready - The assertion of this bit indicates that one or more characters are available in the Channel B receiver
+ only by resetting the individual status bits that they point to.
+ [7] Channel B External or Counter/timer Status - This bit indicates that one of the following status bits is asserted: ICTSRB[6:4]
+ [6] Channel B Receiver or Transmitter Status - This bit indicates that one of the following status bits is asserted: TRSRB[7:1], TRSRB[7:3].
+ [5] Channel B Transmitter Ready - The assertion of this bit indicates that one or more characters may be loaded into the Channel B transmitter
+ FIFO to be serialized by the transmit shift register. See description of OMR[4j. This bit can be asserted only when the transmitter is enabled.
+ Resetting the transmitter negates TxRDY.
+ [4] Channel B Receiver Ready - The assertion of this bit indicates that one or more characters are available in the Channel B receiver
FIFO to be read by the CPU. See deSCription of OMR[3]. RxRDY is initially reset (negated) by a chip reset or when a 'reset Channel B
- receiver' command is invoked.
- [3] Channel A External or Countermmer Status - This bit indicates that one of the following status bits is asserted: ICTSRA[6:4].
- [2] Channel A Receiver or Transmitter Status - This bit indicates that one of the following status bits is asserted: TRSRA[7:0], TRSRA[7:3].
- [1] Channel A Transmitter Ready - The assertion of this bit indicates that one or more characters may be loaded into the Channel A
- transmitter FIFO to be serialized by the transmit shift register. See description of OMR[4]. This bit can be asserted only
- when the transmitter is enabled. Resetting the transmitter negates TxRDY.
- [0] Channel A Receiver Ready - The assertion of this bit indicates that one or more characters are available in the Channel A receiver
- FIFO to be read by the CPU. See description of OMR[3]. RxRDY is initially reset (negated) by a chip reset or when a 'reset Channel A
- receiver' command is invoked.
+ receiver' command is invoked.
+ [3] Channel A External or Countermmer Status - This bit indicates that one of the following status bits is asserted: ICTSRA[6:4].
+ [2] Channel A Receiver or Transmitter Status - This bit indicates that one of the following status bits is asserted: TRSRA[7:0], TRSRA[7:3].
+ [1] Channel A Transmitter Ready - The assertion of this bit indicates that one or more characters may be loaded into the Channel A
+ transmitter FIFO to be serialized by the transmit shift register. See description of OMR[4]. This bit can be asserted only
+ when the transmitter is enabled. Resetting the transmitter negates TxRDY.
+ [0] Channel A Receiver Ready - The assertion of this bit indicates that one or more characters are available in the Channel A receiver
+ FIFO to be read by the CPU. See description of OMR[3]. RxRDY is initially reset (negated) by a chip reset or when a 'reset Channel A
+ receiver' command is invoked.
*/
UINT8 duscc_channel::do_dusccreg_gsr_r()
-{
+{
LOGR(("%s <- %02x\n", FUNCNAME, m_gsr));
- return (UINT8) m_gsr;
+ return (UINT8) m_gsr;
}
UINT8 duscc_channel::do_dusccreg_ier_r(){ logerror("register access method %s is not implemented yet\n", FUNCNAME); return (UINT8) 0; }
UINT8 duscc_channel::do_dusccreg_cid_r()
-{
+{
LOG(("%s\n", FUNCNAME));
if ( m_uart->m_variant != SET_CMOS )
{
@@ -797,186 +797,186 @@ UINT8 duscc_channel::do_dusccreg_telr_r(){ logerror("register access method %s i
// write register handlers
/* CMR1 register
- [7:6] Data Encoding - These bits select the data encoding for the received and transmitted data:
- 00 If the DPLL is set to NRZI mode (see DPLL commands), it selects positive logic (1 = high, 0 = low).
+ [7:6] Data Encoding - These bits select the data encoding for the received and transmitted data:
+ 00 If the DPLL is set to NRZI mode (see DPLL commands), it selects positive logic (1 = high, 0 = low).
If the DPLL is set to FM mode (see DPLL commands), Manchester (bi-phase level) encoding is selected.
- 01 NRZI. Non-return-to-zero inverted.
- 10 FMO. Bi-phase space.
- 11 FM 1. Bi-phase mark.
- [5] Extended Control (BOP) -
- 0 No. A one-octet control field follows the address field.
- 1 Yes. A two-octet control field follows the address field.
- [5] Parity (COP/ ASYNC), Code Select (BISYNC)
- 0 Even parity if with parity is selected by [4:3] or a 0 in the parity bit position if force parity is
- selected by [4:3]. In BISYNC protocol mode, internal character comparisons are made using EBCDIC coding.
- 1 Odd parity if with parity is selected by [4:3] or a 1 in the parity bit position if force parity is selected by [4:3].
- In BISYNC protocol mode, internal character comparisons are made using Bbit ASCII coding.
- [4:3] Address Mode (BOP) -
- This field controls whether a single octet or multiple octets follow the opening FLAG(s) for both the receiver and the transmitter.
- This field is activated by selection of BOP secondary mode through the channel protocol mode bits CMR1_[2:0] (see Detailed Operation).
- 00 Single octet address.
- 01 Extended address.
- 10 Dual octet address.
- 11 Dual octet address with group.
- [4:3] Parity Mode (COP/ASYNC) -
- This field selects the parity mode for both the receiver and the transmitter. A parity bit is added to the programmed character length if
- with parity or force parity is selected:
- 00 No parity. Required when BISYNC protocol mode is programmed.
- 01 Reserved.
- 10 With parity. Odd or even parity is selected by [5].
- 11 Force parity. The parity bit is forced to the state selected by [5].
- [2:0] Channel Protocol Mode -
- This field selects the operational protocol and submode for both the receiver and transmitter:
- 000 - BOP Primary. No address comparison is performed. For receive, all characters received after the opening FLAG(s) are transferred to the FIFO.
- 001 - BOP Secondary. This mode activates the address modes selected by [4:3]. Except in the case of extended address ([4:3]=01), an address comparison
- is performed to determine if a frame should be received. Refer to Detailed Operation for details of the various addressing modes. If a valid comparison
- occurs, the receiver is activated and the address octets and all subsequent received characters of the frame are transferred to the receive FIFO.
- 010 - BOP Loop. The DUSCC acts as a secondary station in a loop. The GO-ON-LOOP and GO-OFF-LOOP commands are used to cause the DUSCC to go on and off the
- loop. Normally, the TXD output echoes the RXD input with a three bit time delay. If the transmitter is enabled and the 'go active on poll' command has been
- asserted, the transmitter will begin sending when an EOP sequence consisting of a zero followed by seven ones is detected. The DUSCC changes the last one of
- the EOP to zero, making it another FLAG, and then operates as described in the detailed operation section. The loop sending status bit (TRSR[6]) is asserted
- concurrent with the beginning of transmission. The frame should normally be terminated with an EOM followed by an echo of the marking RXD line so that secondary
- stations further down the loop can append their messages to the messages from up-loop stations by the same process. If the 'go active on poll'command is not
- asserted, the transmitter remains inactive (other than echOing the received data) even when the EOP sequence is received.
- 011 - BOP Loop without address comparison. Same as normal loop mode except that address field comparisons are disabled. All received frames aretransmitted to the CPU.
- 100 - COP Dual SYN. Character sync is achieved upon receipt of a bit sequence matching the contents of the appropriate bits of SIR and S2R (SYNI-SYN2), including
- parity bits if any.
- 101 - COP Dual SYN (BISYNC). Character sync is achieved upon receipt of a bit sequence matching the contents of the appropriate bits of SI Rand S2R
- (SYN1·SYN2). In this mode, special transmitter and receive logic is activated. Transmitter and receiver character length must be programmed to 8 bits and no parity
- 110 - COP Single SYN. Character sync is achieved upon receipt of a bit sequence matching the contents of the appropriate bits of Sl R (SYN1), including parity bit if any.
- This mode is required when the external sync mode is selected.
- 111 Asynchronous. Start/stop format.
+ 01 NRZI. Non-return-to-zero inverted.
+ 10 FMO. Bi-phase space.
+ 11 FM 1. Bi-phase mark.
+ [5] Extended Control (BOP) -
+ 0 No. A one-octet control field follows the address field.
+ 1 Yes. A two-octet control field follows the address field.
+ [5] Parity (COP/ ASYNC), Code Select (BISYNC)
+ 0 Even parity if with parity is selected by [4:3] or a 0 in the parity bit position if force parity is
+ selected by [4:3]. In BISYNC protocol mode, internal character comparisons are made using EBCDIC coding.
+ 1 Odd parity if with parity is selected by [4:3] or a 1 in the parity bit position if force parity is selected by [4:3].
+ In BISYNC protocol mode, internal character comparisons are made using Bbit ASCII coding.
+ [4:3] Address Mode (BOP) -
+ This field controls whether a single octet or multiple octets follow the opening FLAG(s) for both the receiver and the transmitter.
+ This field is activated by selection of BOP secondary mode through the channel protocol mode bits CMR1_[2:0] (see Detailed Operation).
+ 00 Single octet address.
+ 01 Extended address.
+ 10 Dual octet address.
+ 11 Dual octet address with group.
+ [4:3] Parity Mode (COP/ASYNC) -
+ This field selects the parity mode for both the receiver and the transmitter. A parity bit is added to the programmed character length if
+ with parity or force parity is selected:
+ 00 No parity. Required when BISYNC protocol mode is programmed.
+ 01 Reserved.
+ 10 With parity. Odd or even parity is selected by [5].
+ 11 Force parity. The parity bit is forced to the state selected by [5].
+ [2:0] Channel Protocol Mode -
+ This field selects the operational protocol and submode for both the receiver and transmitter:
+ 000 - BOP Primary. No address comparison is performed. For receive, all characters received after the opening FLAG(s) are transferred to the FIFO.
+ 001 - BOP Secondary. This mode activates the address modes selected by [4:3]. Except in the case of extended address ([4:3]=01), an address comparison
+ is performed to determine if a frame should be received. Refer to Detailed Operation for details of the various addressing modes. If a valid comparison
+ occurs, the receiver is activated and the address octets and all subsequent received characters of the frame are transferred to the receive FIFO.
+ 010 - BOP Loop. The DUSCC acts as a secondary station in a loop. The GO-ON-LOOP and GO-OFF-LOOP commands are used to cause the DUSCC to go on and off the
+ loop. Normally, the TXD output echoes the RXD input with a three bit time delay. If the transmitter is enabled and the 'go active on poll' command has been
+ asserted, the transmitter will begin sending when an EOP sequence consisting of a zero followed by seven ones is detected. The DUSCC changes the last one of
+ the EOP to zero, making it another FLAG, and then operates as described in the detailed operation section. The loop sending status bit (TRSR[6]) is asserted
+ concurrent with the beginning of transmission. The frame should normally be terminated with an EOM followed by an echo of the marking RXD line so that secondary
+ stations further down the loop can append their messages to the messages from up-loop stations by the same process. If the 'go active on poll'command is not
+ asserted, the transmitter remains inactive (other than echOing the received data) even when the EOP sequence is received.
+ 011 - BOP Loop without address comparison. Same as normal loop mode except that address field comparisons are disabled. All received frames aretransmitted to the CPU.
+ 100 - COP Dual SYN. Character sync is achieved upon receipt of a bit sequence matching the contents of the appropriate bits of SIR and S2R (SYNI-SYN2), including
+ parity bits if any.
+ 101 - COP Dual SYN (BISYNC). Character sync is achieved upon receipt of a bit sequence matching the contents of the appropriate bits of SI Rand S2R
+ (SYN1?SYN2). In this mode, special transmitter and receive logic is activated. Transmitter and receiver character length must be programmed to 8 bits and no parity
+ 110 - COP Single SYN. Character sync is achieved upon receipt of a bit sequence matching the contents of the appropriate bits of Sl R (SYN1), including parity bit if any.
+ This mode is required when the external sync mode is selected.
+ 111 Asynchronous. Start/stop format.
*/
void duscc_channel::do_dusccreg_cmr1_w(UINT8 data)
-{
+{
LOG(("%s(%02x)\n", FUNCNAME, data));
m_cmr1 = data;
LOG(("- Setting up %s mode\n", (m_cmr1 & REG_CMR1_CPMODE_MASK) == REG_CMR1_CPMODE_ASYNC ? "ASYNC" : "SYNC"));
LOG(("- Parity: %s\n", ((m_cmr1 & REG_CMR1_PMMODE_MASK) == REG_CMR1_PMMODE_PARITY ? (m_cmr1 & REG_CMR1_PARITY ? "odd" : "even") : "none")));
- return;
+ return;
}
/* CMR2 register
- [7:6] Channel Connection - This field selects the mode of operation of the channel. The user must exercise care when switching into and out of the various modes. The
- selected mode will be activated immediately upon mode selection, even if this occurs in the middle of a received or transmitted character.
-
- 00 - Normal mode. The 1ransmitter and receiver operate independently in either half or full-duplex, controlled by the respective enable commands.
-
- 01 - Automatic echo mode. Automatically retransmits the received data with a half-bit time delay (ASYNC, 16X clock mode) or a one-bit time delay (allother modes).
- The following conditions are true while in automatic echo mode:
- 1. Received data is reclocked and retransmitted on the TXD output.
- 2. The receiver clock is used for the transmitter.
- 3. The receiver must be enabled, but the transmitter need not be enabled.
- 4. The TXRDY and underrun status bits are inactive.
- 5. The received parity and/or FCS are checked if required, but are not regenerated for transmission,
- i.e., transmitted parity and/ or FCS are as received.
- 6. In ASYNC mode, character framing is checked, but the stop bits are retransmitted as received.
- A received break is echoed as received.
- 7. CPU to receiver communication continues normally, but the CPU to transmitter link is disabled.
-
- 10 - Local loopback mode. In this mode:
- 1. The transmitter output is internally connected to the receiver input.
- 2. The transmit clock is used for the receiver if NRZI or NRZ encoding is used. For FM or Manchester encoding because the receiver clock is derived from the DPLL,
+ [7:6] Channel Connection - This field selects the mode of operation of the channel. The user must exercise care when switching into and out of the various modes. The
+ selected mode will be activated immediately upon mode selection, even if this occurs in the middle of a received or transmitted character.
+
+ 00 - Normal mode. The 1ransmitter and receiver operate independently in either half or full-duplex, controlled by the respective enable commands.
+
+ 01 - Automatic echo mode. Automatically retransmits the received data with a half-bit time delay (ASYNC, 16X clock mode) or a one-bit time delay (allother modes).
+ The following conditions are true while in automatic echo mode:
+ 1. Received data is reclocked and retransmitted on the TXD output.
+ 2. The receiver clock is used for the transmitter.
+ 3. The receiver must be enabled, but the transmitter need not be enabled.
+ 4. The TXRDY and underrun status bits are inactive.
+ 5. The received parity and/or FCS are checked if required, but are not regenerated for transmission,
+ i.e., transmitted parity and/ or FCS are as received.
+ 6. In ASYNC mode, character framing is checked, but the stop bits are retransmitted as received.
+ A received break is echoed as received.
+ 7. CPU to receiver communication continues normally, but the CPU to transmitter link is disabled.
+
+ 10 - Local loopback mode. In this mode:
+ 1. The transmitter output is internally connected to the receiver input.
+ 2. The transmit clock is used for the receiver if NRZI or NRZ encoding is used. For FM or Manchester encoding because the receiver clock is derived from the DPLL,
the DPLL source clock must be maintained.
- 3. The TXD output is held high.
- 4. The RXD input is ignored.
- 5. The receiver and transmitter must be enabled.
- 6. CPU to transmitter and receiver communications continue normally.
-
- 11 - Reserved.
-
- [5:3] Data Transfer Interface - This field specifies the type of data transfer between the DUSCC's RX and TX FIFOs and the CPU.
- All interrupt and status functions operate normally regardless of the data transfer interface programmed.
- 000 - Half duplex single address DMA.
- 001 - Half duplex dual address DMA.
- 010 - Full duplex single address DMA.
- 011 - Full duplex dual address DMA.
- 100 - Wait on receive only. In this mode a read of a non-empty receive FIFO results in a normal bus cycle. However, if the receive FIFO of the channel
- is empty when a read RX FIFO cycle is initiated, the DTACKN output remains negated until a character is received and loaded into the FIFO.
- DT ACKN is then asserted and the cycle is completed normally.
- 101 - Wait on transmit only. In this mode a write to a non-full transmit FI Fa results in a normal bus cycle. However, if the transmit FIFO of the channel is
- full when a write TX FIFO cycle is initiated, the DTACKN output remains negated until a FI Fa position becomes available for the new character. DT ACKN
- is then asserted and the cycle is completed normally.
- 110 - Wait on transmit and receive. As above for both wait on receive and transmit operations.
- 111 - Polled or interrupt. DMA and wait functions of the channel are not activated. Data transfers to the RX and TX FIFOs are via normal bus read and
- write cycles in response to polling of the status registers and/or interrupts.
-
- [2:0] Frame Check Sequence Select - This field selects the optional frame check sequence (FCS) to be appended at the end of a transmitted frame.
- When CRC is selected in COP, then no parity and 8-bit character length must be used. The selected FCS is transmitted as follows:
- 1. Following the transmission of a FIFO'ed character tagged with the 'send EOM' command.
- 2. If underrun control (TPR[7:6]) is programmed for TEOM, upon occurrence of an underrun.
- 3. If TEOM on zero count or done (TPR[4]) is asserted and the counter/timer is counting transmitted characters, after transmission of the character which
- causes the counter to reach zero count.
- 4. In DMA mode with TEOM on zero count or done (TPR[4]) set, after transmission of a character if DONEN is asserted when that character was loaded into the
- TX FIFO by the DMA controller.
-
- 000 - No frame check sequence.
- 001 - Reserved
- 010 - LRC8: Divisor ~ x8+ 1, dividend preset to zeros. The TX sends the calculated LRC non-inverted. The RX indicates an error if the computed LRC is
- not equal to O. Valid for COP modes only.
- 011 - LRC8: Divisor ~ x8+ 1, dividend preset to ones. The TX sends the calculated LRC non-inverted. The RX indicates
- an error if the computed LRC is not equal to O. Valid for COP modes only.
- 100 - CRCI6: Divisor ~ x16+x15+x2+1, dividend preset to zeros. The TX sends the calculated CRC non-inverted. The RX indicates an error if the
- computed CRC is not equal to O. Not valid for ASYNC mode.
- 101 - CRCI6: Divisor ~ x16+x15+x2+1, dividend preset to ones. The TX sends the calculated CRC non-inverted. The RX indicates an error if the
- computed CRC is not equal to O. Not valid for ASYNC mode.
- 110 - CRC-CCITT: Divisor ~ x16+x12+x5+1, dividend preset to zeros. The TX sends the calculated CRC non-inverted. The RX indicates an error if the
- computed CRC is not equal to O. Not valid for ASYNC mode.
- 111 CRC-CCITT: Divisor ~ x16+x12+x5+1, dividend preset to ones. The TX sends the calculated CRC inverted. The RX indicates an error if the computed
- CRC is not equal to H' FOB8'. Not valid for ASYNC mode.
+ 3. The TXD output is held high.
+ 4. The RXD input is ignored.
+ 5. The receiver and transmitter must be enabled.
+ 6. CPU to transmitter and receiver communications continue normally.
+
+ 11 - Reserved.
+
+ [5:3] Data Transfer Interface - This field specifies the type of data transfer between the DUSCC's RX and TX FIFOs and the CPU.
+ All interrupt and status functions operate normally regardless of the data transfer interface programmed.
+ 000 - Half duplex single address DMA.
+ 001 - Half duplex dual address DMA.
+ 010 - Full duplex single address DMA.
+ 011 - Full duplex dual address DMA.
+ 100 - Wait on receive only. In this mode a read of a non-empty receive FIFO results in a normal bus cycle. However, if the receive FIFO of the channel
+ is empty when a read RX FIFO cycle is initiated, the DTACKN output remains negated until a character is received and loaded into the FIFO.
+ DT ACKN is then asserted and the cycle is completed normally.
+ 101 - Wait on transmit only. In this mode a write to a non-full transmit FI Fa results in a normal bus cycle. However, if the transmit FIFO of the channel is
+ full when a write TX FIFO cycle is initiated, the DTACKN output remains negated until a FI Fa position becomes available for the new character. DT ACKN
+ is then asserted and the cycle is completed normally.
+ 110 - Wait on transmit and receive. As above for both wait on receive and transmit operations.
+ 111 - Polled or interrupt. DMA and wait functions of the channel are not activated. Data transfers to the RX and TX FIFOs are via normal bus read and
+ write cycles in response to polling of the status registers and/or interrupts.
+
+ [2:0] Frame Check Sequence Select - This field selects the optional frame check sequence (FCS) to be appended at the end of a transmitted frame.
+ When CRC is selected in COP, then no parity and 8-bit character length must be used. The selected FCS is transmitted as follows:
+ 1. Following the transmission of a FIFO'ed character tagged with the 'send EOM' command.
+ 2. If underrun control (TPR[7:6]) is programmed for TEOM, upon occurrence of an underrun.
+ 3. If TEOM on zero count or done (TPR[4]) is asserted and the counter/timer is counting transmitted characters, after transmission of the character which
+ causes the counter to reach zero count.
+ 4. In DMA mode with TEOM on zero count or done (TPR[4]) set, after transmission of a character if DONEN is asserted when that character was loaded into the
+ TX FIFO by the DMA controller.
+
+ 000 - No frame check sequence.
+ 001 - Reserved
+ 010 - LRC8: Divisor ~ x8+ 1, dividend preset to zeros. The TX sends the calculated LRC non-inverted. The RX indicates an error if the computed LRC is
+ not equal to O. Valid for COP modes only.
+ 011 - LRC8: Divisor ~ x8+ 1, dividend preset to ones. The TX sends the calculated LRC non-inverted. The RX indicates
+ an error if the computed LRC is not equal to O. Valid for COP modes only.
+ 100 - CRCI6: Divisor ~ x16+x15+x2+1, dividend preset to zeros. The TX sends the calculated CRC non-inverted. The RX indicates an error if the
+ computed CRC is not equal to O. Not valid for ASYNC mode.
+ 101 - CRCI6: Divisor ~ x16+x15+x2+1, dividend preset to ones. The TX sends the calculated CRC non-inverted. The RX indicates an error if the
+ computed CRC is not equal to O. Not valid for ASYNC mode.
+ 110 - CRC-CCITT: Divisor ~ x16+x12+x5+1, dividend preset to zeros. The TX sends the calculated CRC non-inverted. The RX indicates an error if the
+ computed CRC is not equal to O. Not valid for ASYNC mode.
+ 111 CRC-CCITT: Divisor ~ x16+x12+x5+1, dividend preset to ones. The TX sends the calculated CRC inverted. The RX indicates an error if the computed
+ CRC is not equal to H' FOB8'. Not valid for ASYNC mode.
*/
void duscc_channel::do_dusccreg_cmr2_w(UINT8 data)
-{
+{
LOG(("%s(%02x)\n", FUNCNAME, data));
m_cmr2 = data;
LOG(("- Preparing for %s driven transfers\n", (m_cmr2 & REG_CMR2_DTI_MASK) == REG_CMR2_DTI_NODMA ? "polled or interrupt" : "dma"));
- return;
+ return;
}
void duscc_channel::do_dusccreg_s1r_w(UINT8 data){ logerror("register access method %s is not implemented yet\n", FUNCNAME); return; }
void duscc_channel::do_dusccreg_s2r_w(UINT8 data){ logerror("register access method %s is not implemented yet\n", FUNCNAME); return; }
/* Transmitter Parameter Register (TPRA, TPRB)
- SYNC mode
- [7:6] Underrun Control - In BOP and COP modes, this field selects the transmitter response in the event of an underrun (i.e., the TX FIFO is empty).
- 00 - Normal end of message termination. In BOP, the transmitter sends the FCS (if selected by CMR2[2:011 followed by a FLAG and then either MARKs or
- FLAGs, as specified by [5]. In COP, the transmitter sends the FCS (if selected by CMR2[2:0]) and then either MARKs or SYNs, as specified by [5].
- 01 - Reserved.
- l0 - in BOP, the transmitter sends an ABORT (11111111) and then places the TXD output in a marking condition until receipt of further instructions.
- In COP, the transmitter places the TXD output in a marking condition until receipt of further instructions.
- 11 - In BOP, the transmitter sends an ABORT (11111111) and then sends FLAGs until receipt of further instructions. In COP, the transmitter sends
- SYNs until receipt of further instructions.
- [5] Idle - In BOP and COP modes, this bit selects the transmitter output during idle. Idle is defined as the state following a normal end of message until
- receipt of the next transmitter command.
- 0 - Idle in marking condition.
- 1 - Idle sending SYNs (COP) or FLAGs (BOP).
- [4] Transmit EOM on Zero Count or Done - In BOP and COP modes, the assertion of this bit causes the end of message (FCS in COP, FCS-FLAG in BOP) to be transmitted
- upon the following events:
- 1. If the counterltimer is counting transmitted characters, after transmission of the character which causes the counter to reach zero count. (DONEN is also asserted
- as an output if the channel is in a DMA operation.)
- 2. If the channel is operating in DMA mode, after transmission of a character if DONEN was asserted when that character was loaded into the TX FIFO by the DMA controller.
-
- ASYNC mode
- [7:4] Stop Bits per Character - In ASYNC mode, this field programs the length of the stop bit appended to the transmitted character
- Stop bit lengths of 9/16 to 1 and 1-9/16 to 2 bits, in increments of 1/16 bit, can be programmed for character lengths of 6, 7, and 8 bits.
- For a character length of 5 bits, 1-1/16 to 2 stop bits can be programmed in increments of 1/16 bit. The receiver only checks for a 'mark'
- condition at the center of the first stop bit position (one bit time after the last data bit, or after the parity bit if parity is enabled) in all cases.
- If an external 1 X clock is used for the transmitter, [7) = 0 selects one stop bit and [7) = 1 selects two stop bits to be transmitted.
- If Manchester, NRZI, or FM data encoding is selected, only integral stop bit lengths should be used.
- [3] Transmitter Request-to-Send Control - This bit controls the deactivation of the RTS_N output by the transmitter
- 0 - RTS_N is not affected by status of transmitter.
- 1 - RTS_N changes state as a function of transmitter status.
- [2] Clear-ta-Send Enable Transmitter - The state of this bit determines if the CTS N input controls the operation of the channels transmitter
- The duration of CTS level change is described in the discussion of ICTSR[4).
- 0 - CTS_N has no affect on the transmitter.
- 1 - CTS_N affects the state of the transmitter.
- [1:0] Transmitted Bits per Character - This field selects the number of data bits per character to be transmitted. The character length does not
- include the start, parity, and stop bits in ASYNC or the parity bit in COP. In BOP modes the character length for the address and control
- fields is always 8 bits, and the value of this field only applies to the information (I) field, except for the last character of the I field,
- whose length is specified by OMR[7:5).
+ SYNC mode
+ [7:6] Underrun Control - In BOP and COP modes, this field selects the transmitter response in the event of an underrun (i.e., the TX FIFO is empty).
+ 00 - Normal end of message termination. In BOP, the transmitter sends the FCS (if selected by CMR2[2:011 followed by a FLAG and then either MARKs or
+ FLAGs, as specified by [5]. In COP, the transmitter sends the FCS (if selected by CMR2[2:0]) and then either MARKs or SYNs, as specified by [5].
+ 01 - Reserved.
+ l0 - in BOP, the transmitter sends an ABORT (11111111) and then places the TXD output in a marking condition until receipt of further instructions.
+ In COP, the transmitter places the TXD output in a marking condition until receipt of further instructions.
+ 11 - In BOP, the transmitter sends an ABORT (11111111) and then sends FLAGs until receipt of further instructions. In COP, the transmitter sends
+ SYNs until receipt of further instructions.
+ [5] Idle - In BOP and COP modes, this bit selects the transmitter output during idle. Idle is defined as the state following a normal end of message until
+ receipt of the next transmitter command.
+ 0 - Idle in marking condition.
+ 1 - Idle sending SYNs (COP) or FLAGs (BOP).
+ [4] Transmit EOM on Zero Count or Done - In BOP and COP modes, the assertion of this bit causes the end of message (FCS in COP, FCS-FLAG in BOP) to be transmitted
+ upon the following events:
+ 1. If the counterltimer is counting transmitted characters, after transmission of the character which causes the counter to reach zero count. (DONEN is also asserted
+ as an output if the channel is in a DMA operation.)
+ 2. If the channel is operating in DMA mode, after transmission of a character if DONEN was asserted when that character was loaded into the TX FIFO by the DMA controller.
+
+ ASYNC mode
+ [7:4] Stop Bits per Character - In ASYNC mode, this field programs the length of the stop bit appended to the transmitted character
+ Stop bit lengths of 9/16 to 1 and 1-9/16 to 2 bits, in increments of 1/16 bit, can be programmed for character lengths of 6, 7, and 8 bits.
+ For a character length of 5 bits, 1-1/16 to 2 stop bits can be programmed in increments of 1/16 bit. The receiver only checks for a 'mark'
+ condition at the center of the first stop bit position (one bit time after the last data bit, or after the parity bit if parity is enabled) in all cases.
+ If an external 1 X clock is used for the transmitter, [7) = 0 selects one stop bit and [7) = 1 selects two stop bits to be transmitted.
+ If Manchester, NRZI, or FM data encoding is selected, only integral stop bit lengths should be used.
+ [3] Transmitter Request-to-Send Control - This bit controls the deactivation of the RTS_N output by the transmitter
+ 0 - RTS_N is not affected by status of transmitter.
+ 1 - RTS_N changes state as a function of transmitter status.
+ [2] Clear-ta-Send Enable Transmitter - The state of this bit determines if the CTS N input controls the operation of the channels transmitter
+ The duration of CTS level change is described in the discussion of ICTSR[4).
+ 0 - CTS_N has no affect on the transmitter.
+ 1 - CTS_N affects the state of the transmitter.
+ [1:0] Transmitted Bits per Character - This field selects the number of data bits per character to be transmitted. The character length does not
+ include the start, parity, and stop bits in ASYNC or the parity bit in COP. In BOP modes the character length for the address and control
+ fields is always 8 bits, and the value of this field only applies to the information (I) field, except for the last character of the I field,
+ whose length is specified by OMR[7:5).
*/
void duscc_channel::do_dusccreg_tpr_w(UINT8 data)
-{
+{
LOG(("%s(%02x) Setting up Transmit Parameters\n", FUNCNAME, data));
m_tpr = data;
LOG(("- RTS %u\n", (m_tpr & REG_TPR_RTS) ? 1 : 0));
@@ -985,39 +985,39 @@ void duscc_channel::do_dusccreg_tpr_w(UINT8 data)
LOG(("- Data Tx bits %u\n", get_tx_word_length()));
update_serial();
- return;
+ return;
}
/* Transmitter Timing Register (TTRA, TTRB)
- [7] External Source - This bit selects the RTxC pin or the TRxC pin of the channel as the transmitter clock input when [6:4] specifies
- external. When used for input, the selected pin must be programmed as an input in the PCR [4:3] or [2:0].
- 0 External input form RTxC pin.
- 1 External input from TRxC pin.
- [6:4] Transmitter Clock Select - This field selects the clock for the transmitter.
- 000 External clock from TRxC or RTXC at 1 X the shift (baud) rate.
- 001 External clock from TRXC or RTxC at 16X the shift rate.
- 010 Internal clock from the phase-locked loop at IX the bit rate. It should be used only in half-duplex operation since the
- DPLL will periodically resync itself to the received data if in full-duplex operation.
- 0ll Internal clock from the bit rate generator at 32X the shift rate. The clock signal is divided by two before use in the
- transmitter which operates at 16X the baud rate. Rate selected by [3:0].
- 100 Internal clock from counter/timer of other channel. The C/T should be programmed to produce a clock at 2X the shift rate.
- 101 Internal clock from counter/timer of other channel. The C/T should be programmed to produce a clock at 32X the shift rate.
- 110 Internal clock from the counter/timer of own channel. The C/T should be programmed to produce a clock at 2X the shift rate.
- 111 Internal clock from the counter/timer of own channel. The C/T should be programmed to produce a clock at 32X the shift rate.
- [3:0] Bit Rate Select - This field selects an output from the bit rate generator to be used by the transmitter circuits. The actual
- frequency output from the BRG is 32X the bit rate shown in Table 5. With a crystal or external clock of 14.7456MHz the bit rates are as
- given in Table 5 (this input is divided by two before being applied to the oscillator circuit).
-
- Table 5. Receiver/Transmitter Baud Rates
- [3:0] BIT RATE [3:0] BIT RATE
- 0000 50 1000 1050
- 0001 75 1001 1200
- 0010 110 1010 2000
- 0011 134.5 1011 2400
- 0100 150 1100 4800
- 0101 200 1101 9600
- 0110 300 1110 19.2K
- 0111 600 1111 38.4K
+ [7] External Source - This bit selects the RTxC pin or the TRxC pin of the channel as the transmitter clock input when [6:4] specifies
+ external. When used for input, the selected pin must be programmed as an input in the PCR [4:3] or [2:0].
+ 0 External input form RTxC pin.
+ 1 External input from TRxC pin.
+ [6:4] Transmitter Clock Select - This field selects the clock for the transmitter.
+ 000 External clock from TRxC or RTXC at 1 X the shift (baud) rate.
+ 001 External clock from TRXC or RTxC at 16X the shift rate.
+ 010 Internal clock from the phase-locked loop at IX the bit rate. It should be used only in half-duplex operation since the
+ DPLL will periodically resync itself to the received data if in full-duplex operation.
+ 0ll Internal clock from the bit rate generator at 32X the shift rate. The clock signal is divided by two before use in the
+ transmitter which operates at 16X the baud rate. Rate selected by [3:0].
+ 100 Internal clock from counter/timer of other channel. The C/T should be programmed to produce a clock at 2X the shift rate.
+ 101 Internal clock from counter/timer of other channel. The C/T should be programmed to produce a clock at 32X the shift rate.
+ 110 Internal clock from the counter/timer of own channel. The C/T should be programmed to produce a clock at 2X the shift rate.
+ 111 Internal clock from the counter/timer of own channel. The C/T should be programmed to produce a clock at 32X the shift rate.
+ [3:0] Bit Rate Select - This field selects an output from the bit rate generator to be used by the transmitter circuits. The actual
+ frequency output from the BRG is 32X the bit rate shown in Table 5. With a crystal or external clock of 14.7456MHz the bit rates are as
+ given in Table 5 (this input is divided by two before being applied to the oscillator circuit).
+
+ Table 5. Receiver/Transmitter Baud Rates
+ [3:0] BIT RATE [3:0] BIT RATE
+ 0000 50 1000 1050
+ 0001 75 1001 1200
+ 0010 110 1010 2000
+ 0011 134.5 1011 2400
+ 0100 150 1100 4800
+ 0101 200 1101 9600
+ 0110 300 1110 19.2K
+ 0111 600 1111 38.4K
*/
void duscc_channel::do_dusccreg_ttr_w(UINT8 data)
{
@@ -1028,17 +1028,17 @@ void duscc_channel::do_dusccreg_ttr_w(UINT8 data)
#if VERBOSE > 0
switch(m_ttr & REG_TTR_TXCLK_MASK)
{
- case REG_TTR_TXCLK_1XEXT: LOG(("1x External - not implemented\n")); break;
- case REG_TTR_TXCLK_16XEXT: LOG(("16x External - not implemented\n")); break;
- case REG_TTR_TXCLK_DPLL: LOG(("DPLL - not implemented\n")); break;
- case REG_TTR_TXCLK_BRG:
- LOG(("BRG\n"));
+ case REG_TTR_TXCLK_1XEXT: LOG(("1x External - not implemented\n")); break;
+ case REG_TTR_TXCLK_16XEXT: LOG(("16x External - not implemented\n")); break;
+ case REG_TTR_TXCLK_DPLL: LOG(("DPLL - not implemented\n")); break;
+ case REG_TTR_TXCLK_BRG:
+ LOG(("BRG\n"));
m_brg_tx_rate = get_baudrate(m_ttr & REG_TTR_BRG_RATE_MASK);
break;
- case REG_TTR_TXCLK_2X_OTHER: LOG(("2x other channel C/T - not implemented\n")); break;
- case REG_TTR_TXCLK_32X_OTHER: LOG(("32x other channel C/T - not implemented\n")); break;
- case REG_TTR_TXCLK_2X_OWN: LOG(("2x own channel C/T - not implemented\n")); break;
- case REG_TTR_TXCLK_32X_OWN: LOG(("32x own channel C/T - not implemented\n")); break;
+ case REG_TTR_TXCLK_2X_OTHER: LOG(("2x other channel C/T - not implemented\n")); break;
+ case REG_TTR_TXCLK_32X_OTHER: LOG(("32x other channel C/T - not implemented\n")); break;
+ case REG_TTR_TXCLK_2X_OWN: LOG(("2x own channel C/T - not implemented\n")); break;
+ case REG_TTR_TXCLK_32X_OWN: LOG(("32x own channel C/T - not implemented\n")); break;
default: LOG(("Wrong programming\n")); break; // Should never happen
}
#endif
@@ -1046,81 +1046,81 @@ void duscc_channel::do_dusccreg_ttr_w(UINT8 data)
LOG(("- BRG Tx rate %u assuming a 14.7456MHz CLK crystal\n", get_baudrate(m_ttr & REG_TTR_BRG_RATE_MASK)));
update_serial();
- return;
+ return;
}
/* Receiver Parameter Resgister (RPRA, RPRB)
- [7] SYN Stripping - This bit controls the DUSCC processing in COP modes of SYN 'character patterns' that occur after the initial
+ [7] SYN Stripping - This bit controls the DUSCC processing in COP modes of SYN 'character patterns' that occur after the initial
character synchronization. Refer to Detailed Operation of the receiver for details and definition of SYN 'patterns', and their
- accumulation of FCS.
- 0 Strip only leading SYN 'patterns' (i.e. before a message).
- 1 Strip all SYN 'patterns' (including all odd DLE's in BISYNC transparent mode).
-
- [6] Transfer Received FCS to FIFO - In BISYNC and BOP modes, the assertion of this bit causes the received FCS to be loaded into the
- RxFIFO. When this bit is set, BOP mode operates correctly only if a minimum of two extra FLAGs (without shared zeros) are appended
- to the frame. If the FCS is specified to be transferred to the FI FO, the EOM status bit will be tagged onto the last byte of the
- FCS instead of to the last character of the message.
- 0 Do not transfer FCS to RxFIFO.
- 1 Transfer FCS to RxFIFO.
-
- [5] Auto-Hunt and Pad Check (BISYNC) -In BISYNC rnode, the assertion of this bit causes the receiver to go into hunt for character
- sync mode after detecting certain End-Ol-Message (EOM) characters. These are defined in the Detailed Operations section for
- COP receiver operation. After the EOT and NAK sequences, the receiver also does a check for a closing PAD of four 1 s.
- 0 Disable auto-hunt and PAD check.
- 1 Enable auto-hunt and PAD check.
- [5] Overrun Mode (BOP) - The state of this control bit deterrnines the operation of the receiver in the event of a data overrun, i.e.,
- when a character is received while the RxFIFO and the Rx shift register are both full.
- 0 The receiver terrninates receiving the current frame and goes into hunt phase, looking for a FLAG to be received.
- 1 The receiver continues receiving the current frame. The overrunning character is lost. (The five characters already
- assembled in the RxFIFO and Rx shift register are protected).
-
- [4] Receiver Request-to-Send Control (ASYNC)
- 0 Receiver does not control RTSN output.
- 1 Receiver can negate RTSN output.
- [4] External Sync (COP) - In COP single SYN mode, the assertion of this bit enables external character synchronization and
- receipt of SYN patterns is not required. In order to use this feature, the DUSCC must be programmed to COP single SYN mode,
- CMR1[2:0] = 110, which is used to set up the internal data paths. In all other respects, however, the external sync mode operation is
- protocol transparent. A negative signal on the DCDN/SYNIN pin will cause the receiver to establish synchronization on the next rising
- edge of the receiver clock. Character assembly will start at this edge with the RxD input pin considered to have the second bit of
- data. The sync signal can then be negated. Receipt of the Active-High external sync input causes the SYN detect status bit
- (RSR[2]) to be set and the SYNBOUTN pin to be asserted for one bit time. When this mode is enable, the internal SYN (COP mode)
- detection and special character recognition (e.g., IDLE, STX, ETX, etc.) circuits are disabled. Character assembly begins as ~ in the
- I-field with character length as programmed in RPR[I :)]. Incoming COP frames with parity specified optionally can have it stripped by
- programming RPR[3J. The user must wait at least eight bit times after Rx is enabled before applying the SYNIN signal. This time is
- required to flush the internal data paths. The receiver remains in this mode and further external sync pulses are ignored until the
- receiver is disabled and then reenabled to resynchronize or to return to normal mode.
- 0 External sync not enabled.
- 1 External sync enabled.
- Note that EXT SYNC and DCD ENABLE Rx cannot be asserted simultaneously since they use the same pin.
-
- [3] Strip Parity - In COP and ASYNC modes with parity enabled, this bit controls whether the received parity bit is stripped from the
- data placed in the receiver FIFO. It is valid ony for programmed character lengths of 5, 6, and 7 bits. If the bit is stripped, the
- corresponding bit in the received data is set to zero.
- 0 Transfer parity bit as received.
- 1 Stop parity bit from data.
- [3] All Parties Address - In BOP secondary modes, the assertion of this bit causes the receiver to 'wake-up' upon receipt of the
- address H'FF' or H'FF, FF', for single- and dual-octet address modes, respectively, in addition to its normal station address. This
- feature allows all stations to receive a message.
- 0 Don't recognize all parties address.
- 1 Recognize all parties address.
-
- [2] DCD Enable Receiver - If this bit is asserted, the DCDN/SYNIN input must be Low in order for the receiver to operate.
- If the input is negated (goes High) while a character is being received, the receiver terminates receipt of the current message
- (this action in effect disables the receiver). If DCD is subsequently asserted, the receiver will search for the start bit, SYN pattern, or
- FLAG, depending on the channel protocol. (Note that the change of input can be programmed to generate an interrupt; the duration of
- the DCD level change is described in the discussion of the input and counter/timer status register (CTSR[5]).
- 0 DCD not used to enabled receiver.
- 1 DCD used to enabled receiver.
- NOTE that EXT SYNC and DCD ENABLE Rx cannot be asserted simultaneously since they use the same pin.
-
- [1:0] Received Bits per Character - This field selects the number of data bits per character to be assembled by the receiver. The
- character length does not include the start, parity, and stop bits in the ASYNC or the parity bit in COP. In BOP modes, the character
- length for the address and control field is always 8 bits, and the value of this field only applies to the information field. lithe number
- of bits assembled for the last character of the l-field is less than the value programmed in this field, RCL not zero (RSR[O]) is asserted
- and the actual number of bits received is given in TRSR[2:0].
+ accumulation of FCS.
+ 0 Strip only leading SYN 'patterns' (i.e. before a message).
+ 1 Strip all SYN 'patterns' (including all odd DLE's in BISYNC transparent mode).
+
+ [6] Transfer Received FCS to FIFO - In BISYNC and BOP modes, the assertion of this bit causes the received FCS to be loaded into the
+ RxFIFO. When this bit is set, BOP mode operates correctly only if a minimum of two extra FLAGs (without shared zeros) are appended
+ to the frame. If the FCS is specified to be transferred to the FI FO, the EOM status bit will be tagged onto the last byte of the
+ FCS instead of to the last character of the message.
+ 0 Do not transfer FCS to RxFIFO.
+ 1 Transfer FCS to RxFIFO.
+
+ [5] Auto-Hunt and Pad Check (BISYNC) -In BISYNC rnode, the assertion of this bit causes the receiver to go into hunt for character
+ sync mode after detecting certain End-Ol-Message (EOM) characters. These are defined in the Detailed Operations section for
+ COP receiver operation. After the EOT and NAK sequences, the receiver also does a check for a closing PAD of four 1 s.
+ 0 Disable auto-hunt and PAD check.
+ 1 Enable auto-hunt and PAD check.
+ [5] Overrun Mode (BOP) - The state of this control bit deterrnines the operation of the receiver in the event of a data overrun, i.e.,
+ when a character is received while the RxFIFO and the Rx shift register are both full.
+ 0 The receiver terrninates receiving the current frame and goes into hunt phase, looking for a FLAG to be received.
+ 1 The receiver continues receiving the current frame. The overrunning character is lost. (The five characters already
+ assembled in the RxFIFO and Rx shift register are protected).
+
+ [4] Receiver Request-to-Send Control (ASYNC)
+ 0 Receiver does not control RTSN output.
+ 1 Receiver can negate RTSN output.
+ [4] External Sync (COP) - In COP single SYN mode, the assertion of this bit enables external character synchronization and
+ receipt of SYN patterns is not required. In order to use this feature, the DUSCC must be programmed to COP single SYN mode,
+ CMR1[2:0] = 110, which is used to set up the internal data paths. In all other respects, however, the external sync mode operation is
+ protocol transparent. A negative signal on the DCDN/SYNIN pin will cause the receiver to establish synchronization on the next rising
+ edge of the receiver clock. Character assembly will start at this edge with the RxD input pin considered to have the second bit of
+ data. The sync signal can then be negated. Receipt of the Active-High external sync input causes the SYN detect status bit
+ (RSR[2]) to be set and the SYNBOUTN pin to be asserted for one bit time. When this mode is enable, the internal SYN (COP mode)
+ detection and special character recognition (e.g., IDLE, STX, ETX, etc.) circuits are disabled. Character assembly begins as ~ in the
+ I-field with character length as programmed in RPR[I :)]. Incoming COP frames with parity specified optionally can have it stripped by
+ programming RPR[3J. The user must wait at least eight bit times after Rx is enabled before applying the SYNIN signal. This time is
+ required to flush the internal data paths. The receiver remains in this mode and further external sync pulses are ignored until the
+ receiver is disabled and then reenabled to resynchronize or to return to normal mode.
+ 0 External sync not enabled.
+ 1 External sync enabled.
+ Note that EXT SYNC and DCD ENABLE Rx cannot be asserted simultaneously since they use the same pin.
+
+ [3] Strip Parity - In COP and ASYNC modes with parity enabled, this bit controls whether the received parity bit is stripped from the
+ data placed in the receiver FIFO. It is valid ony for programmed character lengths of 5, 6, and 7 bits. If the bit is stripped, the
+ corresponding bit in the received data is set to zero.
+ 0 Transfer parity bit as received.
+ 1 Stop parity bit from data.
+ [3] All Parties Address - In BOP secondary modes, the assertion of this bit causes the receiver to 'wake-up' upon receipt of the
+ address H'FF' or H'FF, FF', for single- and dual-octet address modes, respectively, in addition to its normal station address. This
+ feature allows all stations to receive a message.
+ 0 Don't recognize all parties address.
+ 1 Recognize all parties address.
+
+ [2] DCD Enable Receiver - If this bit is asserted, the DCDN/SYNIN input must be Low in order for the receiver to operate.
+ If the input is negated (goes High) while a character is being received, the receiver terminates receipt of the current message
+ (this action in effect disables the receiver). If DCD is subsequently asserted, the receiver will search for the start bit, SYN pattern, or
+ FLAG, depending on the channel protocol. (Note that the change of input can be programmed to generate an interrupt; the duration of
+ the DCD level change is described in the discussion of the input and counter/timer status register (CTSR[5]).
+ 0 DCD not used to enabled receiver.
+ 1 DCD used to enabled receiver.
+ NOTE that EXT SYNC and DCD ENABLE Rx cannot be asserted simultaneously since they use the same pin.
+
+ [1:0] Received Bits per Character - This field selects the number of data bits per character to be assembled by the receiver. The
+ character length does not include the start, parity, and stop bits in the ASYNC or the parity bit in COP. In BOP modes, the character
+ length for the address and control field is always 8 bits, and the value of this field only applies to the information field. lithe number
+ of bits assembled for the last character of the l-field is less than the value programmed in this field, RCL not zero (RSR[O]) is asserted
+ and the actual number of bits received is given in TRSR[2:0].
*/
void duscc_channel::do_dusccreg_rpr_w(UINT8 data)
-{
+{
LOG(("%s(%02x) Setting up Receiver Parameters\n", FUNCNAME, data));
m_rpr = data;
LOG(("- RTS output %u\n", (m_rpr & REG_RPR_RTS) ? 1 : 0));
@@ -1129,35 +1129,35 @@ void duscc_channel::do_dusccreg_rpr_w(UINT8 data)
LOG(("- Data Rx bits %u\n", get_rx_word_length()));
update_serial();
- return;
+ return;
}
/* Receiver Timing Register (RTRA, RTRB)
- [7] External Source - This M selects the RTxC pin or the TRxC pin of the channel as the receiver or DPLL clock input, when [6:4J
- specifies external. When used for input, the selected pin must be programmed as an input in the PCR [4:3] or [2:0].
- 0 External input form RTxC pin.
- 1 External input form TRxC pin.
- [6:4] Receiver Clock Select- This field selects the clock for the receiver.
- 000 External clock from TRxC or RTxC at 1 X the shift (baud) rate.
- 001 External clock fromTRxC or RTxC at 16X the shift rate. Used for ASYNC mode only.
- 010 Internal clock from the bit rate generator at 32X the shift rate. Clock is divided by two before used by the receiver
- logic, which operates at 16X the baud rate. Rate selected
- by [3:0J. Used for ASYNC mode only.
- 011 Internal clock from counter/timer of own channel. The CIT should be programmed to produce a clock at 32X the shift
- rate. Clock is divided by two before use in the receiver logic. Used for ASYNC mode only.
- 100 Internal clock from the digital phase- locked loop. The clock for the DPLL is a 64X clock from the crystal oscillator or
- system clock input. (The input to the oscillator is divided by two).
- 101 Internal clock from the digital phase- locked loop. The clock for the DPLL is an external 32X clock from the RTxC or
- TRxC pin, as selected by [7J.
- 110 Internal clock from the digital phase- locked loop. The clock for the DPLL is a 32X clock from the BRG. The frequency
- is programmed by [3:0].
- 111 Internal clock from the digital phase- locked loop. The clock for the DPLL is a 32X clock from the counter/timer of the
- channel.
- [3:0] Bit Rate Select- This field selects an output from the bit rate generator to be used by the receiver circuits. The actual frequency
- output from the BRG is 32X the bit rate shown in Table 5.*/
+ [7] External Source - This M selects the RTxC pin or the TRxC pin of the channel as the receiver or DPLL clock input, when [6:4J
+ specifies external. When used for input, the selected pin must be programmed as an input in the PCR [4:3] or [2:0].
+ 0 External input form RTxC pin.
+ 1 External input form TRxC pin.
+ [6:4] Receiver Clock Select- This field selects the clock for the receiver.
+ 000 External clock from TRxC or RTxC at 1 X the shift (baud) rate.
+ 001 External clock fromTRxC or RTxC at 16X the shift rate. Used for ASYNC mode only.
+ 010 Internal clock from the bit rate generator at 32X the shift rate. Clock is divided by two before used by the receiver
+ logic, which operates at 16X the baud rate. Rate selected
+ by [3:0J. Used for ASYNC mode only.
+ 011 Internal clock from counter/timer of own channel. The CIT should be programmed to produce a clock at 32X the shift
+ rate. Clock is divided by two before use in the receiver logic. Used for ASYNC mode only.
+ 100 Internal clock from the digital phase- locked loop. The clock for the DPLL is a 64X clock from the crystal oscillator or
+ system clock input. (The input to the oscillator is divided by two).
+ 101 Internal clock from the digital phase- locked loop. The clock for the DPLL is an external 32X clock from the RTxC or
+ TRxC pin, as selected by [7J.
+ 110 Internal clock from the digital phase- locked loop. The clock for the DPLL is a 32X clock from the BRG. The frequency
+ is programmed by [3:0].
+ 111 Internal clock from the digital phase- locked loop. The clock for the DPLL is a 32X clock from the counter/timer of the
+ channel.
+ [3:0] Bit Rate Select- This field selects an output from the bit rate generator to be used by the receiver circuits. The actual frequency
+ output from the BRG is 32X the bit rate shown in Table 5.*/
void duscc_channel::do_dusccreg_rtr_w(UINT8 data)
-{
+{
LOG(("%s(%02x) Setting up Receiver Timing\n", FUNCNAME, data));
m_rtr = data;
LOG(("- External source: %s\n", (m_rtr & REG_RTR_EXT) ? "TRxC" : "RTxC"));
@@ -1166,17 +1166,17 @@ void duscc_channel::do_dusccreg_rtr_w(UINT8 data)
#if VERBOSE > 0
switch(m_rtr & REG_RTR_RXCLK_MASK)
{
- case REG_RTR_RXCLK_1XEXT: LOG(("1x External - not implemented\n")); break;
- case REG_RTR_RXCLK_16XEXT: LOG(("16x External - not implemented\n")); break;
+ case REG_RTR_RXCLK_1XEXT: LOG(("1x External - not implemented\n")); break;
+ case REG_RTR_RXCLK_16XEXT: LOG(("16x External - not implemented\n")); break;
case REG_RTR_RXCLK_BRG:
- LOG(("BRG\n"));
+ LOG(("BRG\n"));
m_brg_rx_rate = get_baudrate(m_rtr & REG_RTR_BRG_RATE_MASK);
break;
- case REG_RTR_RXCLK_CT: LOG(("C/T of channel - not implemented\n")); break;
- case REG_RTR_RXCLK_DPLL_64X_X1: LOG(("DPLL, source = 64X X1/CLK - not implemented\n")); break;
+ case REG_RTR_RXCLK_CT: LOG(("C/T of channel - not implemented\n")); break;
+ case REG_RTR_RXCLK_DPLL_64X_X1: LOG(("DPLL, source = 64X X1/CLK - not implemented\n")); break;
case REG_RTR_RXCLK_DPLL_32X_EXT:LOG(("DPLL, source = 32X External - not implemented\n")); break;
case REG_RTR_RXCLK_DPLL_32X_BRG:LOG(("DPLL, source = 32X BRG - not implemented\n")); break;
- case REG_RTR_RXCLK_DPLL_32X_CT: LOG(("DPLL, source = 32X C/T - not implemented\n")); break;
+ case REG_RTR_RXCLK_DPLL_32X_CT: LOG(("DPLL, source = 32X C/T - not implemented\n")); break;
default: LOG(("Wrong programming\n")); break; // Should never happen
}
#endif
@@ -1184,7 +1184,7 @@ void duscc_channel::do_dusccreg_rtr_w(UINT8 data)
LOG(("- BRG Rx rate %u assuming a 14.7456MHz CLK crystal\n", get_baudrate(m_rtr & REG_RTR_BRG_RATE_MASK)));
update_serial();
- return;
+ return;
}
void duscc_channel::do_dusccreg_ctprh_w(UINT8 data){ logerror("register access method %s is not implemented yet\n", FUNCNAME); return; }
@@ -1192,44 +1192,44 @@ void duscc_channel::do_dusccreg_ctprl_w(UINT8 data){ logerror("register access m
void duscc_channel::do_dusccreg_ctcr_w(UINT8 data){ logerror("register access method %s is not implemented yet\n", FUNCNAME); return; }
/* Output and Miscellaneous Register (OMRA, OMRB)
- [7:5] Transmitted Residual Character Length - In BOP modes, this field determines the number of bits transmitted for the last
- character in the information field. This length applies to:
- - The character in the transmit FIFO accompanied by the FIFOed TEOM command.
- - The character loaded into the FIFO by the DMA controller if DONEN is simultaneously asserted and TPR(4) is asserted.
- - The character loaded into the FIFO which causes the counter to reach zero count when TPR[4J is asserted.
- The length of all other characters in the frame's information field is selected by TPR[I :OJ. If this field is 111,
- the number of bits in the last character is the same as programmed in TPR[1:0].
- [4] TxRDY Activate Mode -
- 0 FIFO not full. The channel's TxRDY status bit is asserted each time a character is transferred from the transmit FIFO
- to the transmit shift register. If not reset by the CPU, TxRDY remains asserted until the FIFO is full, at which time
- it is automatically negated.
- 1 FIFO empty. The channel's TxRDY status bit is asserted when a character transfer from the transmit FIFO to the
- transmit shift register causes the FI FO to become empty. If not reset by the CPU, TxRDY remains asserted until the
- FIFO is full, at which time it is negated.
- If the TxRDY status bit is reset by the CPU, it will remain negated regardless of the current state of the transmit
- FIFO, until it is asserted again due to the occurrence of one of the above conditions.
- [3] RxRDY Activate Mode -
- 0 FIFO not empty. The channel's RxRDY status bit is asserted each time a character is transferred from the
- receive shift register to the receive FIFO. If not reset by the CPU, RxRDY remains asserted until the receive FIFO is
- empty, at which time it is automatically negated.
- 1 FIFO full. The channel's RxRDY status bit is asserted when a character transfer from the receive shift register to the
- receive FIFO causes the FIFO to become full. If not reset by the CPU, RxRDY reamins asserted until the FIFO is empty,
- at which time it is negated.
- The RxRDY status bit will also be asserted, regardless of the receiver FIFO full condition, when an end-of-message
- character is loaded in the RxFIFO (BOP/BISYNC), when a BREAK condition (ASYNC mode) is detected in RSR[2), or
- when the counterltimer is programmed to count received characters and the character which causes it to reach zero
- is loaded in the FIFO (all modes). If reset by the CPU, the RxRDY status bit will remain negated, regardless of the
- current state of the receiver FIFO, until it is asserted again due to one of the above conditions.
- [2] General Purpose Output 2 -
- This general purpose bit is used to control the TxDRQN/GP02lRTSN pin, when it is used as an output. The output is
- High when the bit is a 0 and is Low when the bit is a 1.
- [1] General Purpose Output 1 - This bit is used to control the RTxDRQN/GPOl N output, which is a general purpose output
- when the channel is not in DMA mode. The output is High when the bit is a 0 and is Low when the bit is a 1.
- [0] Request-to-Send Output - This bit controls the TxDRQN/GP02N/RTSN and SYNOUTN/RTSN pin, when either is
- used as a RTS output. The output is High when the bit is a 0 and is Low when the bit is a 1.
+ [7:5] Transmitted Residual Character Length - In BOP modes, this field determines the number of bits transmitted for the last
+ character in the information field. This length applies to:
+ - The character in the transmit FIFO accompanied by the FIFOed TEOM command.
+ - The character loaded into the FIFO by the DMA controller if DONEN is simultaneously asserted and TPR(4) is asserted.
+ - The character loaded into the FIFO which causes the counter to reach zero count when TPR[4J is asserted.
+ The length of all other characters in the frame's information field is selected by TPR[I :OJ. If this field is 111,
+ the number of bits in the last character is the same as programmed in TPR[1:0].
+ [4] TxRDY Activate Mode -
+ 0 FIFO not full. The channel's TxRDY status bit is asserted each time a character is transferred from the transmit FIFO
+ to the transmit shift register. If not reset by the CPU, TxRDY remains asserted until the FIFO is full, at which time
+ it is automatically negated.
+ 1 FIFO empty. The channel's TxRDY status bit is asserted when a character transfer from the transmit FIFO to the
+ transmit shift register causes the FI FO to become empty. If not reset by the CPU, TxRDY remains asserted until the
+ FIFO is full, at which time it is negated.
+ If the TxRDY status bit is reset by the CPU, it will remain negated regardless of the current state of the transmit
+ FIFO, until it is asserted again due to the occurrence of one of the above conditions.
+ [3] RxRDY Activate Mode -
+ 0 FIFO not empty. The channel's RxRDY status bit is asserted each time a character is transferred from the
+ receive shift register to the receive FIFO. If not reset by the CPU, RxRDY remains asserted until the receive FIFO is
+ empty, at which time it is automatically negated.
+ 1 FIFO full. The channel's RxRDY status bit is asserted when a character transfer from the receive shift register to the
+ receive FIFO causes the FIFO to become full. If not reset by the CPU, RxRDY reamins asserted until the FIFO is empty,
+ at which time it is negated.
+ The RxRDY status bit will also be asserted, regardless of the receiver FIFO full condition, when an end-of-message
+ character is loaded in the RxFIFO (BOP/BISYNC), when a BREAK condition (ASYNC mode) is detected in RSR[2), or
+ when the counterltimer is programmed to count received characters and the character which causes it to reach zero
+ is loaded in the FIFO (all modes). If reset by the CPU, the RxRDY status bit will remain negated, regardless of the
+ current state of the receiver FIFO, until it is asserted again due to one of the above conditions.
+ [2] General Purpose Output 2 -
+ This general purpose bit is used to control the TxDRQN/GP02lRTSN pin, when it is used as an output. The output is
+ High when the bit is a 0 and is Low when the bit is a 1.
+ [1] General Purpose Output 1 - This bit is used to control the RTxDRQN/GPOl N output, which is a general purpose output
+ when the channel is not in DMA mode. The output is High when the bit is a 0 and is Low when the bit is a 1.
+ [0] Request-to-Send Output - This bit controls the TxDRQN/GP02N/RTSN and SYNOUTN/RTSN pin, when either is
+ used as a RTS output. The output is High when the bit is a 0 and is Low when the bit is a 1.
*/
void duscc_channel::do_dusccreg_omr_w(UINT8 data)
-{
+{
LOG(("%s(%02x) Output and Miscellaneous Register\n", FUNCNAME, data));
m_omr = data;
LOG(("- Tx Residual Character Length is "));
@@ -1242,42 +1242,42 @@ void duscc_channel::do_dusccreg_omr_w(UINT8 data)
LOG(("- GP02, if configured as output, is: %u\n", m_omr & REG_OMR_GP02 ? 0 : 1));
LOG(("- GP01, if configured as output, is: %u\n", m_omr & REG_OMR_GP01 ? 0 : 1));
LOG(("- RTS, either pin if configured as output, is: %u\n", m_omr & REG_OMR_RTS ? 0 : 1));
- return;
+ return;
}
/* Pin Configuration Register (PCRA, PCRB)
- This register selects the functions for multipurpose 1/0 pins.
- [7] X2IIDC - This bit is defined only for PCRA. It is not used in PCRB.
- 0 The X2/IDCN pin is used as a crystal connection.
- 1 The X2/IDCN pin is the interrupt daisy chain output.
- [6] GP02/RTS - The function of this pin is programmable only when not operating in full-duplex DMA mode.
- 0 The TxDRQN/GP02N/RTSN pin is a general purpose output. It is Low when OMR[2] is a 1 and High when OMR[2] is a O.
- 1 The pin is a request-to-send output The logical stale of the pin is controlled by OMR[O]. When OMR[O] is set, the output is Low.
- [5] SYNOUT/RTS -
- 0 The SYNOUTN/RTSN pin is an active-Low output which is asserted one bit time after a SYN pattern (COP modes) in HSRH/HSRL or FLAG
- (BOP modes) is detected in CCSR.The output remains asserted for one receiver clock period.
- 1 The pin is a request-to-send output The,logical state of the pin Is controlled by OMR[O] when OMR[O] is set, the output is Low.
- [4:3] RTxC-
- 00 The pin is an input. It must be programmed for input when used as the input for the receiver or transmitter clock, the DPLL, or the CIT.
- 01 The pin is an output for the counterltimer.
- 10 The pin is an output for the transmitter shift register clock.
- 11 The pin is an output for the receiver shift register clock.
- [2:0]TRxC-
- 000 The pin is an input. It must be programmed for input when used as the input for the receiver or transmitter clock, the DPLL, or the CIT.
- 001 The pin is an output from the crystal oscillator divided by two.
- 010 The pin is an outputfor the DPLL output clock.
- 011 The pin is an output for the counterltimer. Refer to CTCRAIB description.
- 100 The pin is an output for the transmitter BRG at 16X the rate selected by TTR [3:0].
- 101 The pin is an output for the receiver BRG at 16X the rate selected by RTR [3:0].
- 110 The pin is an output for the transmitter shift register clock.
- 111 The pin is an output for the receiver shift register clock.
+ This register selects the functions for multipurpose 1/0 pins.
+ [7] X2IIDC - This bit is defined only for PCRA. It is not used in PCRB.
+ 0 The X2/IDCN pin is used as a crystal connection.
+ 1 The X2/IDCN pin is the interrupt daisy chain output.
+ [6] GP02/RTS - The function of this pin is programmable only when not operating in full-duplex DMA mode.
+ 0 The TxDRQN/GP02N/RTSN pin is a general purpose output. It is Low when OMR[2] is a 1 and High when OMR[2] is a O.
+ 1 The pin is a request-to-send output The logical stale of the pin is controlled by OMR[O]. When OMR[O] is set, the output is Low.
+ [5] SYNOUT/RTS -
+ 0 The SYNOUTN/RTSN pin is an active-Low output which is asserted one bit time after a SYN pattern (COP modes) in HSRH/HSRL or FLAG
+ (BOP modes) is detected in CCSR.The output remains asserted for one receiver clock period.
+ 1 The pin is a request-to-send output The,logical state of the pin Is controlled by OMR[O] when OMR[O] is set, the output is Low.
+ [4:3] RTxC-
+ 00 The pin is an input. It must be programmed for input when used as the input for the receiver or transmitter clock, the DPLL, or the CIT.
+ 01 The pin is an output for the counterltimer.
+ 10 The pin is an output for the transmitter shift register clock.
+ 11 The pin is an output for the receiver shift register clock.
+ [2:0]TRxC-
+ 000 The pin is an input. It must be programmed for input when used as the input for the receiver or transmitter clock, the DPLL, or the CIT.
+ 001 The pin is an output from the crystal oscillator divided by two.
+ 010 The pin is an outputfor the DPLL output clock.
+ 011 The pin is an output for the counterltimer. Refer to CTCRAIB description.
+ 100 The pin is an output for the transmitter BRG at 16X the rate selected by TTR [3:0].
+ 101 The pin is an output for the receiver BRG at 16X the rate selected by RTR [3:0].
+ 110 The pin is an output for the transmitter shift register clock.
+ 111 The pin is an output for the receiver shift register clock.
*/
void duscc_channel::do_dusccreg_pcr_w(UINT8 data)
-{
+{
LOG(("%s(%02x) Pin Configuration Register\n", FUNCNAME, data));
m_pcr = data;
- LOG(("- The X2/IDCN pin is %s\n", m_index == duscc_device::CHANNEL_B ? "ignored for channel B" :
- ((m_pcr & REG_PCR_X2_IDC) ? "crystal input" : "daisy chain interrupt output")));
+ LOG(("- The X2/IDCN pin is %s\n", m_index == duscc_device::CHANNEL_B ? "ignored for channel B" :
+ ((m_pcr & REG_PCR_X2_IDC) ? "crystal input" : "daisy chain interrupt output")));
LOG(("- The GP02/RTS pin is %s\n", m_pcr & REG_PCR_GP02_RTS ? "RTS" : "GP02"));
LOG(("- The SYNOUT/RTS pin is %s\n", m_pcr & REG_PCR_SYNOUT_RTS ? "RTS" : "SYNOUT"));
@@ -1285,8 +1285,8 @@ void duscc_channel::do_dusccreg_pcr_w(UINT8 data)
LOG(("- The RTxC pin is "));
switch ( m_pcr & REG_PCR_RTXC_MASK )
{
- case REG_PCR_RTXC_INPUT: LOG(("- an input\n")); break;
- case REG_PCR_RTXC_CNTR_OUT: LOG(("- a counter/timer output\n")); break;
+ case REG_PCR_RTXC_INPUT: LOG(("- an input\n")); break;
+ case REG_PCR_RTXC_CNTR_OUT: LOG(("- a counter/timer output\n")); break;
case REG_PCR_RTXC_TXCLK_OUT:LOG(("- a Tx clock output\n")); break;
case REG_PCR_RTXC_RXCLK_OUT:LOG(("- a Rx clock output\n")); break;
default: LOG(("Wrong programming\n")); break; // Should never happen
@@ -1294,10 +1294,10 @@ void duscc_channel::do_dusccreg_pcr_w(UINT8 data)
LOG(("- The TRxC pin is "));
switch( m_pcr & REG_PCR_TRXC_MASK )
{
- case REG_PCR_TRXC_INPUT: LOG(("- an input\n")); break;
+ case REG_PCR_TRXC_INPUT: LOG(("- an input\n")); break;
case REG_PCR_TRXC_CRYST_OUT:LOG(("- a crystal/2 output\n")); break;
- case REG_PCR_TRXC_DPLL_OUT: LOG(("- a DPLL output\n")); break;
- case REG_PCR_TRXC_CNTR_OUT: LOG(("- a counter/timer output\n")); break;
+ case REG_PCR_TRXC_DPLL_OUT: LOG(("- a DPLL output\n")); break;
+ case REG_PCR_TRXC_CNTR_OUT: LOG(("- a counter/timer output\n")); break;
case REG_PCR_TRXC_TXBRG_OUT:LOG(("- a Tx BRG output\n")); break;
case REG_PCR_TRXC_RXBRG_OUT:LOG(("- a Rx BRG output\n")); break;
case REG_PCR_TRXC_TXCLK_OUT:LOG(("- a Tx CLK output\n")); break;
@@ -1307,14 +1307,14 @@ void duscc_channel::do_dusccreg_pcr_w(UINT8 data)
#endif
- return;
+ return;
}
/*
* Commands to the DUSCC are entered through the CCR channel command register.
*
* TODO:
- * - support enable/disable of Tx/Rx using m_tra/m_rcv respectivelly
+ * - support enable/disable of Tx/Rx using m_tra/m_rcv respectivelly
*/
void duscc_channel::do_dusccreg_ccr_w(UINT8 data)
{
@@ -1322,48 +1322,47 @@ void duscc_channel::do_dusccreg_ccr_w(UINT8 data)
LOG(("%s\n", FUNCNAME));
switch(m_ccr)
{
-
// TRANSMITTER COMMANDS
- /* Reset transmitter. Causes the transmitter to cease operation immediately.
- The transmit FIFO is cleared and the TxD output goes into the marking state.
+ /* Reset transmitter. Causes the transmitter to cease operation immediately.
+ The transmit FIFO is cleared and the TxD output goes into the marking state.
Also clears the transmitter status bits (TRSR[7:4]) and resets the TxRDY
- status bit (GSR[I] or GSR[5] for Channels A and B, respectively).
+ status bit (GSR[I] or GSR[5] for Channels A and B, respectively).
The counter/timer and other registers are not affected*/
- case REG_CCR_RESET_TX: LOG(("- Reset Tx\n"));
+ case REG_CCR_RESET_TX: LOG(("- Reset Tx\n"));
set_tra_rate(0);
m_tx_fifo_wp = m_tx_fifo_rp = 0;
m_trsr &= 0x0f;
m_gsr &= ~(m_index == duscc_device::CHANNEL_A ? REG_GSR_CHAN_A_TXREADY : REG_GSR_CHAN_B_TXREADY);
break;
- /* Enable transmitter. Enables transmitter operation, conditioned by the state of
- the CTS ENABLE Tx bit, TPR[2]. Has no effect if invoked when the transmitter has
+ /* Enable transmitter. Enables transmitter operation, conditioned by the state of
+ the CTS ENABLE Tx bit, TPR[2]. Has no effect if invoked when the transmitter has
previously been enabled.*/
- case REG_CCR_ENABLE_TX: LOG(("- Enable Tx\n"));
+ case REG_CCR_ENABLE_TX: LOG(("- Enable Tx\n"));
m_gsr |= (m_index == duscc_device::CHANNEL_A ? REG_GSR_CHAN_A_TXREADY : REG_GSR_CHAN_B_TXREADY);
m_tra = 1;
set_tra_rate(m_brg_tx_rate);
break;
- /* Disable transmitter. Terminates transmitter operation and places the TXD output in the
- marking state at the next occurrence of a transmit FIFO empty condition. All characters
+ /* Disable transmitter. Terminates transmitter operation and places the TXD output in the
+ marking state at the next occurrence of a transmit FIFO empty condition. All characters
currently in the FIFO, or any loaded subsequently prior to attaining an empty condition,
- will be transmitted.
+ will be transmitted.
TODO: let all the chararcters be transmitted before shutting down shifter */
- case REG_CCR_DISABLE_TX: LOG(("- Disable Tx\n"));
+ case REG_CCR_DISABLE_TX: LOG(("- Disable Tx\n"));
set_tra_rate(0);
m_tra = 0;
m_gsr &= ~(m_index == duscc_device::CHANNEL_A ? REG_GSR_CHAN_A_TXREADY : REG_GSR_CHAN_B_TXREADY);
break;
// RECEIVER COMMANDS
-
- /* Reset Receiver. Causes the receiver to cease operation, clears the receiver FIFO,
+
+ /* Reset Receiver. Causes the receiver to cease operation, clears the receiver FIFO,
clears the data path, and clears the receiver status (RSR[7:0], TRSR[3:0], and either
- GSR[O] or GSR[4] for Channels A and B, respectively). The counter/timer and other
+ GSR[O] or GSR[4] for Channels A and B, respectively). The counter/timer and other
registers are not affected.*/
- case REG_CCR_RESET_RX: LOG(("- Reset Rx\n"));
+ case REG_CCR_RESET_RX: LOG(("- Reset Rx\n"));
set_rcv_rate(0);
m_rx_fifo_wp = m_rx_fifo_rp = 0;
m_trsr &= 0xf0;
@@ -1371,33 +1370,33 @@ void duscc_channel::do_dusccreg_ccr_w(UINT8 data)
m_gsr &= ~(m_index == duscc_device::CHANNEL_A ? REG_GSR_CHAN_A_RXREADY : REG_GSR_CHAN_B_RXREADY);
break;
- /* Enable receiver. Causes receiver operation to begin, conditioned by the state of the DCD
- ENABLED Rx bit, RPR[2]. Receiver goes into START, SYN, or FLAG search mode depending on
+ /* Enable receiver. Causes receiver operation to begin, conditioned by the state of the DCD
+ ENABLED Rx bit, RPR[2]. Receiver goes into START, SYN, or FLAG search mode depending on
channel protocol mode. Has no effect if invoked when the receiver has previously been enabled.*/
- case REG_CCR_ENABLE_RX: LOG(("- Enable Rx\n"));
+ case REG_CCR_ENABLE_RX: LOG(("- Enable Rx\n"));
m_rcv = 1;
set_rcv_rate(m_brg_rx_rate);
//m_gsr |= (m_index == duscc_device::CHANNEL_A ? REG_GSR_CHAN_A_RXREADY : REG_GSR_CHAN_B_RXREADY);
break;
- /* Disable receiver. Terminates operation of the receiver. Any character currently being assembled
+ /* Disable receiver. Terminates operation of the receiver. Any character currently being assembled
will be lost. Does not affect FIFO or any status.*/
- case REG_CCR_DISABLE_RX: LOG(("- Disable Rx\n"));
+ case REG_CCR_DISABLE_RX: LOG(("- Disable Rx\n"));
m_rcv = 0;
m_gsr &= ~(m_index == duscc_device::CHANNEL_A ? REG_GSR_CHAN_A_RXREADY : REG_GSR_CHAN_B_RXREADY);
break;
default: LOG((" - command %02x not implemented yet\n", data));
}
- return;
+ return;
}
void duscc_channel::do_dusccreg_txfifo_w(UINT8 data)
-{
+{
LOG(("%s(%02x)'%c'\n", FUNCNAME,data, isalnum(data) ? data : ' '));
LOG((" - TX wp:%d rp:%d sz:%d\n", m_tx_fifo_wp, m_tx_fifo_rp, m_tx_fifo_sz));
/* Tx FIFO is full or...? */
- if (m_tx_fifo_wp + 1 == m_tx_fifo_rp || ( (m_tx_fifo_wp + 1 == m_tx_fifo_sz) && (m_tx_fifo_rp == 0) ))
+ if (m_tx_fifo_wp + 1 == m_tx_fifo_rp || ( (m_tx_fifo_wp + 1 == m_tx_fifo_sz) && (m_tx_fifo_rp == 0) ))
{
logerror("- TX FIFO is full, discarding data\n");
LOG(("- TX FIFO is full, discarding data\n"));
@@ -1423,8 +1422,8 @@ void duscc_channel::do_dusccreg_txfifo_w(UINT8 data)
m_tx_fifo_rp_step();
}
}
- // check if Tx FIFO is FULL and set TxREADY accordingly
- if (m_tx_fifo_wp + 1 == m_tx_fifo_rp || ( (m_tx_fifo_wp + 1 == m_tx_fifo_sz) && (m_tx_fifo_rp == 0) ))
+ // check if Tx FIFO is FULL and set TxREADY accordingly
+ if (m_tx_fifo_wp + 1 == m_tx_fifo_rp || ( (m_tx_fifo_wp + 1 == m_tx_fifo_sz) && (m_tx_fifo_rp == 0) ))
{
m_gsr &= ~(m_index == duscc_device::CHANNEL_A ? REG_GSR_CHAN_A_TXREADY : REG_GSR_CHAN_B_TXREADY);
}
@@ -1433,7 +1432,7 @@ void duscc_channel::do_dusccreg_txfifo_w(UINT8 data)
m_gsr |= (m_index == duscc_device::CHANNEL_A ? REG_GSR_CHAN_A_TXREADY : REG_GSR_CHAN_B_TXREADY);
}
- return;
+ return;
}
void duscc_channel::do_dusccreg_rsr_w(UINT8 data){ logerror("register access method %s is not implemented yet\n", FUNCNAME); return; }
@@ -1466,13 +1465,13 @@ UINT8 duscc_channel::read(offs_t &offset)
switch (reg)
{
- case REG_CID: data = do_dusccreg_cid_r(); break;
- case REG_CCR: data = do_dusccreg_ccr_r(); break;
- case REG_RXFIFO_0: data = do_dusccreg_rxfifo_r(); break;
- case REG_RXFIFO_1: data = do_dusccreg_rxfifo_r(); break;
- case REG_RXFIFO_2: data = do_dusccreg_rxfifo_r(); break;
- case REG_RXFIFO_3: data = do_dusccreg_rxfifo_r(); break;
- case REG_GSR: data = do_dusccreg_gsr_r(); break;
+ case REG_CID: data = do_dusccreg_cid_r(); break;
+ case REG_CCR: data = do_dusccreg_ccr_r(); break;
+ case REG_RXFIFO_0: data = do_dusccreg_rxfifo_r(); break;
+ case REG_RXFIFO_1: data = do_dusccreg_rxfifo_r(); break;
+ case REG_RXFIFO_2: data = do_dusccreg_rxfifo_r(); break;
+ case REG_RXFIFO_3: data = do_dusccreg_rxfifo_r(); break;
+ case REG_GSR: data = do_dusccreg_gsr_r(); break;
default:
logerror(" \"%s\" %s: %c : Unsupported RRx register:%02x\n", m_owner->tag(), FUNCNAME, 'A' + m_index, reg);
}
@@ -1500,47 +1499,47 @@ void duscc_channel::write(UINT8 data, offs_t &offset)
m_a7 = 0;
}
else
- m_a7 = (m_index == duscc_device::CHANNEL_A ? 0x40 : 0);
+ m_a7 = (m_index == duscc_device::CHANNEL_A ? 0x40 : 0);
break;
- case REG_CMR1: do_dusccreg_cmr1_w(data); break;
- case REG_CMR2: do_dusccreg_cmr2_w(data); break;
- case REG_S1R: LOG(("REG_S1R \n")); break;
- case REG_S2R: LOG(("REG_S2R \n")); break;
- case REG_TPR: do_dusccreg_tpr_w(data); break;
- case REG_TTR: do_dusccreg_ttr_w(data); break;
- case REG_RPR: do_dusccreg_rpr_w(data); break;
- case REG_RTR: do_dusccreg_rtr_w(data); break;
- case REG_CTPRH: LOG(("REG_CTPRH\n")); break;
- case REG_CTPRL: LOG(("REG_CTPRL\n")); break;
- case REG_CTCR: LOG(("REG_CTCR\n")); break;
- case REG_OMR: do_dusccreg_omr_w(data); break;
- case REG_CTH: LOG(("REG_CTH \n")); break;
- case REG_CTL: LOG(("REG_CTL \n")); break;
- case REG_PCR: do_dusccreg_pcr_w(data); break;
- case REG_CCR: do_dusccreg_ccr_w(data); break;
- case REG_TXFIFO_0: do_dusccreg_txfifo_w(data); break;
- case REG_TXFIFO_1: do_dusccreg_txfifo_w(data); break;
- case REG_TXFIFO_2: do_dusccreg_txfifo_w(data); break;
- case REG_TXFIFO_3: do_dusccreg_txfifo_w(data); break;
- case REG_RSR: LOG(("REG_RSR \n")); break;
- case REG_TRSR: LOG(("REG_TRSR\n")); break;
- case REG_ICTSR: LOG(("REG_ICTSR\n")); break;
- case REG_GSR: LOG(("REG_GSR \n")); break;
- case REG_IER: LOG(("REG_IER \n")); break;
-// case REG_CID: LOG(("REG_CID \n")); break;
- case REG_IVR: LOG(("REG_IVR \n")); break;
- case REG_ICR: LOG(("REG_ICR \n")); break;
-// case REG_SEA: LOG(("REG_SEA \n")); break;
-// case REG_IVRM: LOG(("REG_IVRM\n")); break;
-// case REG_MRR: LOG(("REG_MRR \n")); break;
- case REG_IER1: LOG(("REG_IER1\n")); break;
- case REG_IER2: LOG(("REG_IER2\n")); break;
- case REG_IER3: LOG(("REG_IER3\n")); break;
- case REG_TRCR: LOG(("REG_TRCR\n")); break;
- case REG_RFLR: LOG(("REG_RFLR\n")); break;
- case REG_FTLR: LOG(("REG_FTLR\n")); break;
- case REG_TRMSR: LOG(("REG_TRMSR\n")); break;
- case REG_TELR: LOG(("REG_TELR\n")); break;
+ case REG_CMR1: do_dusccreg_cmr1_w(data); break;
+ case REG_CMR2: do_dusccreg_cmr2_w(data); break;
+ case REG_S1R: LOG(("REG_S1R \n")); break;
+ case REG_S2R: LOG(("REG_S2R \n")); break;
+ case REG_TPR: do_dusccreg_tpr_w(data); break;
+ case REG_TTR: do_dusccreg_ttr_w(data); break;
+ case REG_RPR: do_dusccreg_rpr_w(data); break;
+ case REG_RTR: do_dusccreg_rtr_w(data); break;
+ case REG_CTPRH: LOG(("REG_CTPRH\n")); break;
+ case REG_CTPRL: LOG(("REG_CTPRL\n")); break;
+ case REG_CTCR: LOG(("REG_CTCR\n")); break;
+ case REG_OMR: do_dusccreg_omr_w(data); break;
+ case REG_CTH: LOG(("REG_CTH \n")); break;
+ case REG_CTL: LOG(("REG_CTL \n")); break;
+ case REG_PCR: do_dusccreg_pcr_w(data); break;
+ case REG_CCR: do_dusccreg_ccr_w(data); break;
+ case REG_TXFIFO_0: do_dusccreg_txfifo_w(data); break;
+ case REG_TXFIFO_1: do_dusccreg_txfifo_w(data); break;
+ case REG_TXFIFO_2: do_dusccreg_txfifo_w(data); break;
+ case REG_TXFIFO_3: do_dusccreg_txfifo_w(data); break;
+ case REG_RSR: LOG(("REG_RSR \n")); break;
+ case REG_TRSR: LOG(("REG_TRSR\n")); break;
+ case REG_ICTSR: LOG(("REG_ICTSR\n")); break;
+ case REG_GSR: LOG(("REG_GSR \n")); break;
+ case REG_IER: LOG(("REG_IER \n")); break;
+// case REG_CID: LOG(("REG_CID \n")); break;
+ case REG_IVR: LOG(("REG_IVR \n")); break;
+ case REG_ICR: LOG(("REG_ICR \n")); break;
+// case REG_SEA: LOG(("REG_SEA \n")); break;
+// case REG_IVRM: LOG(("REG_IVRM\n")); break;
+// case REG_MRR: LOG(("REG_MRR \n")); break;
+ case REG_IER1: LOG(("REG_IER1\n")); break;
+ case REG_IER2: LOG(("REG_IER2\n")); break;
+ case REG_IER3: LOG(("REG_IER3\n")); break;
+ case REG_TRCR: LOG(("REG_TRCR\n")); break;
+ case REG_RFLR: LOG(("REG_RFLR\n")); break;
+ case REG_FTLR: LOG(("REG_FTLR\n")); break;
+ case REG_TRMSR: LOG(("REG_TRMSR\n")); break;
+ case REG_TELR: LOG(("REG_TELR\n")); break;
default:
logerror(" \"%s\" %s: %c : Unsupported WRx register:%02x(%02x)\n", m_owner->tag(), FUNCNAME, 'A' + m_index, reg, data);
@@ -1572,7 +1571,7 @@ void duscc_channel::m_rx_fifo_rp_step()
if (m_rx_fifo_rp == m_rx_fifo_wp)
{
// no more characters available in the FIFO
- // m_rr0 &= ~ RR0_RX_CHAR_AVAILABLE;
+ // m_rr0 &= ~ RR0_RX_CHAR_AVAILABLE;
m_gsr &= ~(m_index == duscc_device::CHANNEL_A ? REG_GSR_CHAN_A_RXREADY : REG_GSR_CHAN_B_RXREADY);
}
}
@@ -1595,7 +1594,7 @@ void duscc_channel::receive_data(UINT8 data)
{
LOG(("\"%s\": %c : Receive Data Byte '%02x'\n", m_owner->tag(), 'A' + m_index, data));
#
- if (m_rx_fifo_wp + 1 == m_rx_fifo_rp || ( (m_rx_fifo_wp + 1 == m_rx_fifo_sz) && (m_rx_fifo_rp == 0) ))
+ if (m_rx_fifo_wp + 1 == m_rx_fifo_rp || ( (m_rx_fifo_wp + 1 == m_rx_fifo_sz) && (m_rx_fifo_rp == 0) ))
{
// receive overrun error detected
m_rsr |= REG_RSR_OVERRUN_ERROR;
@@ -1678,7 +1677,7 @@ WRITE_LINE_MEMBER( duscc_channel::dcd_w )
WRITE_LINE_MEMBER( duscc_channel::ri_w )
{
LOG(("\"%s\" %s: %c : RI %u - not implemented\n", m_owner->tag(), FUNCNAME, 'A' + m_index, state));
-#if 0
+#if 0
if (m_ri != state)
{
// set ring indicator state
@@ -1731,7 +1730,7 @@ void duscc_channel::update_serial()
parity = PARITY_NONE;
LOG((LLFORMAT " %s() \"%s \"Channel %c setting data frame %d+%d%c%d\n", machine().firstcpu->total_cycles(), FUNCNAME, m_owner->tag(), 'A' + m_index, 1,
- data_bit_count, parity == PARITY_NONE ? 'N' : parity == PARITY_EVEN ? 'E' : 'O', (stop_bits + 1) / 2));
+ data_bit_count, parity == PARITY_NONE ? 'N' : parity == PARITY_EVEN ? 'E' : 'O', (stop_bits + 1) / 2));
set_data_frame(1, data_bit_count, parity, stop_bits);
diff --git a/src/devices/machine/scnxx562.h b/src/devices/machine/scnxx562.h
index 917f816228a..cec9d6a8fb3 100644
--- a/src/devices/machine/scnxx562.h
+++ b/src/devices/machine/scnxx562.h
@@ -186,10 +186,10 @@ public:
void do_dusccreg_ictsr_w(UINT8 data);
void do_dusccreg_gsr_w(UINT8 data);
void do_dusccreg_ier_w(UINT8 data);
- // void do_dusccreg_rea_w(UINT8 data); // Short cutted non complex feature
+ // void do_dusccreg_rea_w(UINT8 data); // Short cutted non complex feature
void do_dusccreg_ivr_w(UINT8 data);
void do_dusccreg_icr_w(UINT8 data);
- // void do_dusccreg_sea_w(UINT8 data); // Short cutted non complex feature
+ // void do_dusccreg_sea_w(UINT8 data); // Short cutted non complex feature
void do_dusccreg_mrr_w(UINT8 data);
void do_dusccreg_ier1_w(UINT8 data);
void do_dusccreg_ier2_w(UINT8 data);
@@ -201,8 +201,8 @@ public:
UINT8 read(offs_t &offset);
void write(UINT8 data, offs_t &offset);
- // UINT8 data_read();
- // void data_write(UINT8 data);
+ // UINT8 data_read();
+ // void data_write(UINT8 data);
void receive_data(UINT8 data);
void m_tx_fifo_rp_step();
@@ -246,11 +246,11 @@ public:
UINT8 m_ictsr;
UINT8 m_gsr;
UINT8 m_ier;
- // UINT8 m_rea;
+ // UINT8 m_rea;
UINT8 m_cid;
UINT8 m_ivr;
UINT8 m_icr;
- // UINT8 m_sea;
+ // UINT8 m_sea;
UINT8 m_ivrm;
UINT8 m_mrr;
UINT8 m_ier1;
@@ -261,7 +261,7 @@ public:
UINT8 m_ftlr;
UINT8 m_trmsr;
UINT8 m_telr;
-
+
protected:
enum
{
@@ -273,24 +273,24 @@ protected:
enum
{
- REG_CCR_RESET_TX = 0x00,
- REG_CCR_ENABLE_TX = 0x02,
- REG_CCR_DISABLE_TX = 0x03,
- REG_CCR_RESET_RX = 0x40,
- REG_CCR_ENABLE_RX = 0x42,
- REG_CCR_DISABLE_RX = 0x43
+ REG_CCR_RESET_TX = 0x00,
+ REG_CCR_ENABLE_TX = 0x02,
+ REG_CCR_DISABLE_TX = 0x03,
+ REG_CCR_RESET_RX = 0x40,
+ REG_CCR_ENABLE_RX = 0x42,
+ REG_CCR_DISABLE_RX = 0x43
};
enum
{
- REG_CMR1_PARITY = 0x20,
- REG_CMR1_PMMODE_MASK = 0x18,
- REG_CMR1_PMMODE_NONE = 0x00,
- REG_CMR1_PMMODE_RES = 0x01,
- REG_CMR1_PMMODE_PARITY = 0x10,
- REG_CMR1_PMMODE_FORCED = 0x11,
- REG_CMR1_CPMODE_MASK = 0x07,
- REG_CMR1_CPMODE_ASYNC = 0x07
+ REG_CMR1_PARITY = 0x20,
+ REG_CMR1_PMMODE_MASK = 0x18,
+ REG_CMR1_PMMODE_NONE = 0x00,
+ REG_CMR1_PMMODE_RES = 0x01,
+ REG_CMR1_PMMODE_PARITY = 0x10,
+ REG_CMR1_PMMODE_FORCED = 0x11,
+ REG_CMR1_CPMODE_MASK = 0x07,
+ REG_CMR1_CPMODE_ASYNC = 0x07
};
enum
@@ -301,129 +301,129 @@ protected:
enum
{
- REG_RPR_DATA_BITS_MASK = 0x03,
- REG_RPR_DATA_BITS_5BIT = 0x00,
- REG_RPR_DATA_BITS_6BIT = 0x01,
- REG_RPR_DATA_BITS_7BIT = 0x02,
- REG_RPR_DATA_BITS_8BIT = 0x03,
- REG_RPR_DCD = 0x04,
- REG_RPR_STRIP_PARITY = 0x08,
- REG_RPR_RTS = 0x10
+ REG_RPR_DATA_BITS_MASK = 0x03,
+ REG_RPR_DATA_BITS_5BIT = 0x00,
+ REG_RPR_DATA_BITS_6BIT = 0x01,
+ REG_RPR_DATA_BITS_7BIT = 0x02,
+ REG_RPR_DATA_BITS_8BIT = 0x03,
+ REG_RPR_DCD = 0x04,
+ REG_RPR_STRIP_PARITY = 0x08,
+ REG_RPR_RTS = 0x10
};
enum
{
- REG_TPR_DATA_BITS_MASK = 0x03,
- REG_TPR_DATA_BITS_5BIT = 0x00,
- REG_TPR_DATA_BITS_6BIT = 0x01,
- REG_TPR_DATA_BITS_7BIT = 0x02,
- REG_TPR_DATA_BITS_8BIT = 0x03,
- REG_TPR_CTS = 0x04,
- REG_TPR_RTS = 0x08,
- REG_TPR_STOP_BITS_MASK = 0xf0
+ REG_TPR_DATA_BITS_MASK = 0x03,
+ REG_TPR_DATA_BITS_5BIT = 0x00,
+ REG_TPR_DATA_BITS_6BIT = 0x01,
+ REG_TPR_DATA_BITS_7BIT = 0x02,
+ REG_TPR_DATA_BITS_8BIT = 0x03,
+ REG_TPR_CTS = 0x04,
+ REG_TPR_RTS = 0x08,
+ REG_TPR_STOP_BITS_MASK = 0xf0
};
enum
{
- REG_TTR_EXT = 0x80,
- REG_TTR_TXCLK_MASK = 0x70,
- REG_TTR_TXCLK_1XEXT = 0x00,
- REG_TTR_TXCLK_16XEXT = 0x10,
- REG_TTR_TXCLK_DPLL = 0x20,
- REG_TTR_TXCLK_BRG = 0x30,
- REG_TTR_TXCLK_2X_OTHER = 0x40,
- REG_TTR_TXCLK_32X_OTHER = 0x50,
- REG_TTR_TXCLK_2X_OWN = 0x60,
- REG_TTR_TXCLK_32X_OWN = 0x70,
- REG_TTR_BRG_RATE_MASK = 0x0f,
+ REG_TTR_EXT = 0x80,
+ REG_TTR_TXCLK_MASK = 0x70,
+ REG_TTR_TXCLK_1XEXT = 0x00,
+ REG_TTR_TXCLK_16XEXT = 0x10,
+ REG_TTR_TXCLK_DPLL = 0x20,
+ REG_TTR_TXCLK_BRG = 0x30,
+ REG_TTR_TXCLK_2X_OTHER = 0x40,
+ REG_TTR_TXCLK_32X_OTHER = 0x50,
+ REG_TTR_TXCLK_2X_OWN = 0x60,
+ REG_TTR_TXCLK_32X_OWN = 0x70,
+ REG_TTR_BRG_RATE_MASK = 0x0f,
};
enum
{
- REG_RTR_EXT = 0x80,
- REG_RTR_RXCLK_MASK = 0x70,
- REG_RTR_RXCLK_1XEXT = 0x00,
- REG_RTR_RXCLK_16XEXT = 0x10,
- REG_RTR_RXCLK_BRG = 0x20,
- REG_RTR_RXCLK_CT = 0x30,
- REG_RTR_RXCLK_DPLL_64X_X1 = 0x40,
- REG_RTR_RXCLK_DPLL_32X_EXT = 0x50,
- REG_RTR_RXCLK_DPLL_32X_BRG = 0x60,
- REG_RTR_RXCLK_DPLL_32X_CT = 0x70,
- REG_RTR_BRG_RATE_MASK = 0x0f,
+ REG_RTR_EXT = 0x80,
+ REG_RTR_RXCLK_MASK = 0x70,
+ REG_RTR_RXCLK_1XEXT = 0x00,
+ REG_RTR_RXCLK_16XEXT = 0x10,
+ REG_RTR_RXCLK_BRG = 0x20,
+ REG_RTR_RXCLK_CT = 0x30,
+ REG_RTR_RXCLK_DPLL_64X_X1 = 0x40,
+ REG_RTR_RXCLK_DPLL_32X_EXT = 0x50,
+ REG_RTR_RXCLK_DPLL_32X_BRG = 0x60,
+ REG_RTR_RXCLK_DPLL_32X_CT = 0x70,
+ REG_RTR_BRG_RATE_MASK = 0x0f,
};
enum
{
- REG_PCR_X2_IDC = 0x80,
- REG_PCR_GP02_RTS = 0x40,
- REG_PCR_SYNOUT_RTS = 0x20,
- REG_PCR_RTXC_MASK = 0x18,
- REG_PCR_RTXC_INPUT = 0x00,
- REG_PCR_RTXC_CNTR_OUT = 0x08,
- REG_PCR_RTXC_TXCLK_OUT = 0x10,
- REG_PCR_RTXC_RXCLK_OUT = 0x18,
- REG_PCR_TRXC_MASK = 0x07,
- REG_PCR_TRXC_INPUT = 0x00,
- REG_PCR_TRXC_CRYST_OUT = 0x01,
- REG_PCR_TRXC_DPLL_OUT = 0x02,
- REG_PCR_TRXC_CNTR_OUT = 0x03,
- REG_PCR_TRXC_TXBRG_OUT = 0x04,
- REG_PCR_TRXC_RXBRG_OUT = 0x05,
- REG_PCR_TRXC_TXCLK_OUT = 0x06,
- REG_PCR_TRXC_RXCLK_OUT = 0x07,
+ REG_PCR_X2_IDC = 0x80,
+ REG_PCR_GP02_RTS = 0x40,
+ REG_PCR_SYNOUT_RTS = 0x20,
+ REG_PCR_RTXC_MASK = 0x18,
+ REG_PCR_RTXC_INPUT = 0x00,
+ REG_PCR_RTXC_CNTR_OUT = 0x08,
+ REG_PCR_RTXC_TXCLK_OUT = 0x10,
+ REG_PCR_RTXC_RXCLK_OUT = 0x18,
+ REG_PCR_TRXC_MASK = 0x07,
+ REG_PCR_TRXC_INPUT = 0x00,
+ REG_PCR_TRXC_CRYST_OUT = 0x01,
+ REG_PCR_TRXC_DPLL_OUT = 0x02,
+ REG_PCR_TRXC_CNTR_OUT = 0x03,
+ REG_PCR_TRXC_TXBRG_OUT = 0x04,
+ REG_PCR_TRXC_RXBRG_OUT = 0x05,
+ REG_PCR_TRXC_TXCLK_OUT = 0x06,
+ REG_PCR_TRXC_RXCLK_OUT = 0x07,
};
enum
{
- REG_OMR_TXRCL_MASK = 0xe0,
- REG_OMR_TXRCL_8BIT = 0xe0,
- REG_OMR_TXRDY_ACTIVATED = 0x10,
- REG_OMR_RXRDY_ACTIVATED = 0x08,
- REG_OMR_GP02 = 0x04,
- REG_OMR_GP01 = 0x02,
- REG_OMR_RTS = 0x01,
+ REG_OMR_TXRCL_MASK = 0xe0,
+ REG_OMR_TXRCL_8BIT = 0xe0,
+ REG_OMR_TXRDY_ACTIVATED = 0x10,
+ REG_OMR_RXRDY_ACTIVATED = 0x08,
+ REG_OMR_GP02 = 0x04,
+ REG_OMR_GP01 = 0x02,
+ REG_OMR_RTS = 0x01,
};
enum
{
- REG_RSR_OVERRUN_ERROR = 0x20,
+ REG_RSR_OVERRUN_ERROR = 0x20,
};
enum
{
- REG_ICTSR_DELTA_CTS = 0x10,
- REG_ICTSR_DCD = 0x08,
- REG_ICTSR_CTS = 0x04,
+ REG_ICTSR_DELTA_CTS = 0x10,
+ REG_ICTSR_DCD = 0x08,
+ REG_ICTSR_CTS = 0x04,
};
enum
{
- REG_GSR_CHAN_A_RXREADY = 0x01,
- REG_GSR_CHAN_B_RXREADY = 0x10,
- REG_GSR_CHAN_A_TXREADY = 0x02,
- REG_GSR_CHAN_B_TXREADY = 0x20,
+ REG_GSR_CHAN_A_RXREADY = 0x01,
+ REG_GSR_CHAN_B_RXREADY = 0x10,
+ REG_GSR_CHAN_A_TXREADY = 0x02,
+ REG_GSR_CHAN_B_TXREADY = 0x20,
};
// Register offsets, stripped from channel bit 0x20 but including A7 bit
enum
{
- REG_CMR1 = 0x00,
- REG_CMR2 = 0x01,
- REG_S1R = 0x02,
- REG_S2R = 0x03,
- REG_TPR = 0x04,
- REG_TTR = 0x05,
- REG_RPR = 0x06,
- REG_RTR = 0x07,
- REG_CTPRH = 0x08,
- REG_CTPRL = 0x09,
- REG_CTCR = 0x0a,
- REG_OMR = 0x0b,
- REG_CTH = 0x0c,
- REG_CTL = 0x0d,
- REG_PCR = 0x0e,
- REG_CCR = 0x0f,
+ REG_CMR1 = 0x00,
+ REG_CMR2 = 0x01,
+ REG_S1R = 0x02,
+ REG_S2R = 0x03,
+ REG_TPR = 0x04,
+ REG_TTR = 0x05,
+ REG_RPR = 0x06,
+ REG_RTR = 0x07,
+ REG_CTPRH = 0x08,
+ REG_CTPRL = 0x09,
+ REG_CTCR = 0x0a,
+ REG_OMR = 0x0b,
+ REG_CTH = 0x0c,
+ REG_CTL = 0x0d,
+ REG_PCR = 0x0e,
+ REG_CCR = 0x0f,
REG_TXFIFO_0= 0x10,
REG_TXFIFO_1= 0x11,
REG_TXFIFO_2= 0x12,
@@ -432,26 +432,26 @@ protected:
REG_RXFIFO_1= 0x15,
REG_RXFIFO_2= 0x16,
REG_RXFIFO_3= 0x17,
- REG_RSR = 0x18,
- REG_TRSR = 0x19,
- REG_ICTSR = 0x1a,
- REG_GSR = 0x1b,
- REG_IER = 0x1c,
- REG_REA = 0x1d,
- REG_CID = 0x1d,
- REG_IVR = 0x1e,
- REG_ICR = 0x1f,
- REG_SEA = 0x1d,
- REG_IVRM = 0x1e,
- REG_MRR = 0x1f,
- REG_IER1 = 0x42,
- REG_IER2 = 0x43,
- REG_IER3 = 0x45,
- REG_TRCR = 0x47,
- REG_RFLR = 0x4e,
- REG_FTLR = 0x5c,
- REG_TRMSR = 0x5e,
- REG_TELR = 0x5f,
+ REG_RSR = 0x18,
+ REG_TRSR = 0x19,
+ REG_ICTSR = 0x1a,
+ REG_GSR = 0x1b,
+ REG_IER = 0x1c,
+ REG_REA = 0x1d,
+ REG_CID = 0x1d,
+ REG_IVR = 0x1e,
+ REG_ICR = 0x1f,
+ REG_SEA = 0x1d,
+ REG_IVRM = 0x1e,
+ REG_MRR = 0x1f,
+ REG_IER1 = 0x42,
+ REG_IER2 = 0x43,
+ REG_IER3 = 0x45,
+ REG_TRCR = 0x47,
+ REG_RFLR = 0x4e,
+ REG_FTLR = 0x5c,
+ REG_TRMSR = 0x5e,
+ REG_TELR = 0x5f,
};
enum
@@ -471,22 +471,22 @@ protected:
{
switch (br)
{
- case 0x00: return 50; break;
- case 0x01: return 75; break;
- case 0x02: return 110; break;
- case 0x03: return 134; break;
- case 0x04: return 150; break;
- case 0x05: return 200; break;
- case 0x06: return 300; break;
- case 0x07: return 600; break;
- case 0x08: return 1050; break;
- case 0x09: return 1200; break;
- case 0x0a: return 2000; break;
- case 0x0b: return 2400; break;
- case 0x0c: return 4800; break;
- case 0x0d: return 9600; break;
- case 0x0e: return 19200; break;
- case 0x0f: return 38400; break;
+ case 0x00: return 50; break;
+ case 0x01: return 75; break;
+ case 0x02: return 110; break;
+ case 0x03: return 134; break;
+ case 0x04: return 150; break;
+ case 0x05: return 200; break;
+ case 0x06: return 300; break;
+ case 0x07: return 600; break;
+ case 0x08: return 1050; break;
+ case 0x09: return 1200; break;
+ case 0x0a: return 2000; break;
+ case 0x0b: return 2400; break;
+ case 0x0c: return 4800; break;
+ case 0x0d: return 9600; break;
+ case 0x0e: return 19200; break;
+ case 0x0f: return 38400; break;
};
return 0;
}
@@ -503,47 +503,47 @@ protected:
/* FIFOs and rx/tx status */
/* Receiver */
- UINT8 m_rx_data_fifo[16]; // data FIFO
- UINT8 m_rx_error_fifo[16]; // error FIFO
- int m_rx_fifo_rp; // FIFO read pointer
- int m_rx_fifo_wp; // FIFO write pointer
- int m_rx_fifo_sz; // FIFO size
- UINT8 m_rx_error; // current error
-
- /* Transmitter */
- UINT8 m_tx_data_fifo[16]; // data FIFO
- UINT8 m_tx_error_fifo[16]; // error FIFO
- int m_tx_fifo_rp; // FIFO read pointer
- int m_tx_fifo_wp; // FIFO write pointer
- int m_tx_fifo_sz; // FIFO size
- UINT8 m_tx_error; // current error
-
- int m_rx_clock; // receive clock pulse count
- int m_rx_first; // first character received
- int m_rx_break; // receive break condition
- // UINT8 m_rx_rr0_latch; // read register 0 latched
+ UINT8 m_rx_data_fifo[16]; // data FIFO
+ UINT8 m_rx_error_fifo[16]; // error FIFO
+ int m_rx_fifo_rp; // FIFO read pointer
+ int m_rx_fifo_wp; // FIFO write pointer
+ int m_rx_fifo_sz; // FIFO size
+ UINT8 m_rx_error; // current error
+
+ /* Transmitter */
+ UINT8 m_tx_data_fifo[16]; // data FIFO
+ UINT8 m_tx_error_fifo[16]; // error FIFO
+ int m_tx_fifo_rp; // FIFO read pointer
+ int m_tx_fifo_wp; // FIFO write pointer
+ int m_tx_fifo_sz; // FIFO size
+ UINT8 m_tx_error; // current error
+
+ int m_rx_clock; // receive clock pulse count
+ int m_rx_first; // first character received
+ int m_rx_break; // receive break condition
+ // UINT8 m_rx_rr0_latch; // read register 0 latched
int m_rxd;
- int m_ri; // ring indicator latch
- int m_cts; // clear to send latch
- int m_dcd; // data carrier detect latch
+ int m_ri; // ring indicator latch
+ int m_cts; // clear to send latch
+ int m_dcd; // data carrier detect latch
// transmitter state
- UINT8 m_tx_data; // transmit data register
- int m_tx_clock; // transmit clock pulse count
+ UINT8 m_tx_data; // transmit data register
+ int m_tx_clock; // transmit clock pulse count
- int m_dtr; // data terminal ready
- int m_rts; // request to send
+ int m_dtr; // data terminal ready
+ int m_rts; // request to send
// synchronous state
- UINT16 m_sync; // sync character
+ UINT16 m_sync; // sync character
int m_rcv_mode;
int m_index;
duscc_device *m_uart;
// CDUSCC specifics
- int m_a7; // Access additional registers
+ int m_a7; // Access additional registers
};
@@ -551,7 +551,7 @@ protected:
class duscc_device : public device_t
-// ,public device_z80daisy_interface
+// ,public device_z80daisy_interface
{
friend class duscc_channel;
@@ -585,7 +585,7 @@ public:
DECLARE_WRITE8_MEMBER( write );
// interrupt acknowledge
- // int m1_r();
+ // int m1_r();
DECLARE_WRITE_LINE_MEMBER( rxa_w ) { m_chanA->write_rx(state); }
DECLARE_WRITE_LINE_MEMBER( rxb_w ) { m_chanB->write_rx(state); }
@@ -596,7 +596,7 @@ public:
DECLARE_WRITE_LINE_MEMBER( ria_w ) { m_chanA->ri_w(state); }
DECLARE_WRITE_LINE_MEMBER( rib_w ) { m_chanB->ri_w(state); }
#if 0
- DECLARE_WRITE_LINE_MEMBER( rxca_w ) { m_chanA->rxc_w(state); }
+ DECLARE_WRITE_LINE_MEMBER( rxca_w ) { m_chanA->rxc_w(state); }
DECLARE_WRITE_LINE_MEMBER( rxcb_w ) { m_chanB->rxc_w(state); }
DECLARE_WRITE_LINE_MEMBER( txca_w ) { m_chanA->txc_w(state); }
DECLARE_WRITE_LINE_MEMBER( txcb_w ) { m_chanB->txc_w(state); }
diff --git a/src/devices/machine/z80scc.h b/src/devices/machine/z80scc.h
index c050b75b75f..d1abae4f574 100644
--- a/src/devices/machine/z80scc.h
+++ b/src/devices/machine/z80scc.h
@@ -536,18 +536,18 @@ protected:
int get_tx_word_length();
// receiver state
- UINT8 m_rx_data_fifo[8]; // receive data FIFO
- UINT8 m_rx_error_fifo[8]; // receive error FIFO
- UINT8 m_rx_error; // current receive error
- //int m_rx_fifo // receive FIFO pointer
- int m_rx_fifo_rp; // receive FIFO read pointer
- int m_rx_fifo_wp; // receive FIFO write pointer
- int m_rx_fifo_sz; // receive FIFO size
-
- int m_rx_clock; // receive clock pulse count
- int m_rx_first; // first character received
- int m_rx_break; // receive break condition
- UINT8 m_rx_rr0_latch; // read register 0 latched
+ UINT8 m_rx_data_fifo[8]; // receive data FIFO
+ UINT8 m_rx_error_fifo[8]; // receive error FIFO
+ UINT8 m_rx_error; // current receive error
+ //int m_rx_fifo // receive FIFO pointer
+ int m_rx_fifo_rp; // receive FIFO read pointer
+ int m_rx_fifo_wp; // receive FIFO write pointer
+ int m_rx_fifo_sz; // receive FIFO size
+
+ int m_rx_clock; // receive clock pulse count
+ int m_rx_first; // first character received
+ int m_rx_break; // receive break condition
+ UINT8 m_rx_rr0_latch; // read register 0 latched
int m_rxd;
int m_ri; // ring indicator latch
diff --git a/src/devices/video/zeus2.cpp b/src/devices/video/zeus2.cpp
index 4887b70c688..f41253ffb6f 100644
--- a/src/devices/video/zeus2.cpp
+++ b/src/devices/video/zeus2.cpp
@@ -38,7 +38,7 @@ TIMER_CALLBACK_MEMBER(zeus2_device::display_irq_off)
///* if zero, adjust to next frame, otherwise we may get stuck in an infinite loop */
//if (vblank_period == attotime::zero)
- // vblank_period = m_screen->frame_period();
+ // vblank_period = m_screen->frame_period();
//vblank_timer->adjust(vblank_period);
vblank_timer->adjust(m_screen->time_until_vblank_start());
//machine().scheduler().timer_set(attotime::from_hz(30000000), timer_expired_delegate(FUNC(zeus2_device::display_irq), this));
@@ -66,7 +66,6 @@ TIMER_CALLBACK_MEMBER(zeus2_device::int_timer_callback)
void zeus2_device::device_start()
{
-
/* allocate memory for "wave" RAM */
waveram[0] = auto_alloc_array(machine(), UINT32, WAVERAM0_WIDTH * WAVERAM0_HEIGHT * 8/4);
//waveram[1] = auto_alloc_array(machine(), UINT32, WAVERAM1_WIDTH * WAVERAM1_HEIGHT * 12/4);
@@ -257,7 +256,7 @@ if (machine().input().code_pressed(KEYCODE_DOWN)) { zbase -= 1.0f; popmessage("Z
READ32_MEMBER( zeus2_device::zeus2_r )
{
- int logit = (offset != 0x00 && offset != 0x01 &&
+ int logit = (offset != 0x00 && offset != 0x01 &&
offset != 0x48 && offset != 0x49 &&
offset != 0x54 && offset != 0x58 && offset != 0x59 && offset != 0x5a);
logit &= LOG_REGS;
@@ -457,7 +456,7 @@ void zeus2_device::zeus2_register_update(offs_t offset, UINT32 oldval, int logit
m_zeusbase[0x41] += (m_zeusbase[0x41] & 0x400) << 6;
m_zeusbase[0x41] &= ~0xfc00;
}
- }
+ }
break;
case 0x41:
/* this is the address, except in read mode, where it latches values */
@@ -541,7 +540,7 @@ void zeus2_device::zeus2_register_update(offs_t offset, UINT32 oldval, int logit
//printf("Clearing buffer: numPixels: %08X addr: %08X reg50: %08X\n", numBytes/4, addr, m_zeusbase[0x50]);
memset(&m_frameColor[addr], m_fill_color, numBytes);
memset(&m_frameDepth[addr], m_fill_depth, numBytes/2);
- }
+ }
else if ((m_zeusbase[0x5e] >> 16) != 0xf208 && !(m_zeusbase[0x5e] & 0xffff)) {
/* If 0x5e==0xf20a0000 (atlantis) or 0xf20d0000 (the grid) then process the read/write now */
/*
@@ -585,16 +584,16 @@ void zeus2_device::zeus2_register_update(offs_t offset, UINT32 oldval, int logit
/* thegrid uses this to write either left or right halves of pixels */
//if (m_zeusbase[0x50] == 0x00e90000)
//{
- // UINT32 addr = frame_addr_from_reg51();
- // if (m_zeusbase[0x57] & 1)
- // m_frameColor[addr] = m_zeusbase[0x58];
- // if (m_zeusbase[0x57] & 4)
- // m_frameColor[addr+1] = m_zeusbase[0x59];
+ // UINT32 addr = frame_addr_from_reg51();
+ // if (m_zeusbase[0x57] & 1)
+ // m_frameColor[addr] = m_zeusbase[0x58];
+ // if (m_zeusbase[0x57] & 4)
+ // m_frameColor[addr+1] = m_zeusbase[0x59];
//}
///* make sure we log anything else */
//else if (logit)
- // logerror("\t[50]=%08X [5E]=%08X\n", m_zeusbase[0x50], m_zeusbase[0x5e]);
+ // logerror("\t[50]=%08X [5E]=%08X\n", m_zeusbase[0x50], m_zeusbase[0x5e]);
break;
case 0x58:
@@ -1246,39 +1245,39 @@ void zeus2_renderer::zeus2_draw_quad(const UINT32 *databuffer, UINT32 texdata, i
//case 0x95d: /* crusnexo */
//case 0xc1d: /* crusnexo */
//case 0xc5d: /* crusnexo */
- // extra.texwidth = 256;
- // break;
+ // extra.texwidth = 256;
+ // break;
//case 0x18a: // atlantis
//case 0x059: /* crusnexo */
//case 0x0d9: /* crusnexo */
//case 0x119: /* crusnexo: license plates */
//case 0x159: /* crusnexo */
- // extra.texwidth = 128;
- // break;
+ // extra.texwidth = 128;
+ // break;
//case 0x055: /* crusnexo */
//case 0x145: // atlantis
//case 0x155: /* crusnexo */
- // extra.texwidth = 64;
- // break;
+ // extra.texwidth = 64;
+ // break;
//case 0x000: // thegrid guess
//case 0x120: // thegrid guess
//case 0x140: // atlantis
//case 0x141: // atlantis
- // extra.texwidth = 32;
- // break;
+ // extra.texwidth = 32;
+ // break;
//default:
//{
- // static UINT8 hits[0x10000];
- // if (!hits[(texdata & 0xffff)])
- // {
- // hits[(texdata & 0xffff)] = 1;
- // printf("texMode = %04X\n", (texdata & 0xffff));
- // }
- // break;
+ // static UINT8 hits[0x10000];
+ // if (!hits[(texdata & 0xffff)])
+ // {
+ // hits[(texdata & 0xffff)] = 1;
+ // printf("texMode = %04X\n", (texdata & 0xffff));
+ // }
+ // break;
//}
//}
diff --git a/src/emu/debug/debugcmd.cpp b/src/emu/debug/debugcmd.cpp
index 72865e06680..361f8f14fdf 100644
--- a/src/emu/debug/debugcmd.cpp
+++ b/src/emu/debug/debugcmd.cpp
@@ -94,8 +94,8 @@ UINT64 debugger_commands::cheat_read_extended(const cheat_system *cheatsys, addr
debugger_commands::debugger_commands(running_machine& machine, debugger_cpu& cpu, debugger_console& console)
: m_machine(machine)
- , m_cpu(cpu)
- , m_console(console)
+ , m_cpu(cpu)
+ , m_console(console)
{
m_global_array = auto_alloc_array_clear(m_machine, global_entry, MAX_GLOBALS);
@@ -271,7 +271,7 @@ debugger_commands::debugger_commands(running_machine& machine, debugger_cpu& cpu
/* set up the initial debugscript if specified */
const char* name = m_machine.options().debug_script();
if (name[0] != 0)
- m_cpu.source_script(name);
+ m_cpu.source_script(name);
m_cheat.cpu[0] = m_cheat.cpu[1] = 0;
}
@@ -683,7 +683,7 @@ void debugger_commands::execute_tracelog(int ref, int params, const char *param[
/* then do a printf */
char buffer[1024];
if (mini_printf(buffer, param[0], params - 1, &values[1]))
- m_cpu.get_visible_cpu()->debug()->trace_printf("%s", buffer);
+ m_cpu.get_visible_cpu()->debug()->trace_printf("%s", buffer);
}
@@ -720,7 +720,7 @@ void debugger_commands::execute_step(int ref, int params, const char *param[])
if (!validate_number_parameter(param[0], &steps))
return;
- m_cpu.get_visible_cpu()->debug()->single_step(steps);
+ m_cpu.get_visible_cpu()->debug()->single_step(steps);
}
@@ -735,7 +735,7 @@ void debugger_commands::execute_over(int ref, int params, const char *param[])
if (!validate_number_parameter(param[0], &steps))
return;
- m_cpu.get_visible_cpu()->debug()->single_step_over(steps);
+ m_cpu.get_visible_cpu()->debug()->single_step_over(steps);
}
@@ -745,7 +745,7 @@ void debugger_commands::execute_over(int ref, int params, const char *param[])
void debugger_commands::execute_out(int ref, int params, const char *param[])
{
- m_cpu.get_visible_cpu()->debug()->single_step_out();
+ m_cpu.get_visible_cpu()->debug()->single_step_out();
}
@@ -761,7 +761,7 @@ void debugger_commands::execute_go(int ref, int params, const char *param[])
if (!validate_number_parameter(param[0], &addr))
return;
- m_cpu.get_visible_cpu()->debug()->go(addr);
+ m_cpu.get_visible_cpu()->debug()->go(addr);
}
@@ -772,7 +772,7 @@ void debugger_commands::execute_go(int ref, int params, const char *param[])
void debugger_commands::execute_go_vblank(int ref, int params, const char *param[])
{
- m_cpu.get_visible_cpu()->debug()->go_vblank();
+ m_cpu.get_visible_cpu()->debug()->go_vblank();
}
@@ -788,7 +788,7 @@ void debugger_commands::execute_go_interrupt(int ref, int params, const char *pa
if (!validate_number_parameter(param[0], &irqline))
return;
- m_cpu.get_visible_cpu()->debug()->go_interrupt(irqline);
+ m_cpu.get_visible_cpu()->debug()->go_interrupt(irqline);
}
@@ -804,7 +804,7 @@ void debugger_commands::execute_go_time(int ref, int params, const char *param[]
if (!validate_number_parameter(param[0], &milliseconds))
return;
- m_cpu.get_visible_cpu()->debug()->go_milliseconds(milliseconds);
+ m_cpu.get_visible_cpu()->debug()->go_milliseconds(milliseconds);
}
@@ -814,7 +814,7 @@ void debugger_commands::execute_go_time(int ref, int params, const char *param[]
void debugger_commands::execute_next(int ref, int params, const char *param[])
{
- m_cpu.get_visible_cpu()->debug()->go_next_device();
+ m_cpu.get_visible_cpu()->debug()->go_next_device();
}
@@ -1008,8 +1008,8 @@ void debugger_commands::execute_comment_del(int ref, int params, const char *par
/**
* @fn void execute_comment_list(running_machine &machine, int ref, int params, const char *param[])
* @brief Print current list of comments in debugger
- *
- *
+ *
+ *
*/
void debugger_commands::execute_comment_list(int ref, int params, const char *param[])
@@ -1029,7 +1029,7 @@ void debugger_commands::execute_comment_commit(int ref, int params, const char *
execute_comment_add(ref, params, param);
execute_comment_save(ref, params, param);
}
-
+
/*-------------------------------------------------
execute_comment - add a comment to a line
-------------------------------------------------*/
@@ -1053,7 +1053,7 @@ void debugger_commands::execute_comment_save(int ref, int params, const char *pa
* @todo add shorthand for color modify and save
*
*/
-
+
/*-------------------------------------------------
@@ -1651,7 +1651,7 @@ void debugger_commands::execute_load(int ref, int params, const char *param[])
/* check if end of file has been reached and stop loading if it has */
if (feof(f))
break;
- m_cpu.write_byte(*space, i, byte, true);
+ m_cpu.write_byte(*space, i, byte, true);
}
/* close the file */
fclose(f);
@@ -2513,7 +2513,7 @@ void debugger_commands::execute_traceover(int ref, int params, const char *param
void debugger_commands::execute_traceflush(int ref, int params, const char *param[])
{
- m_cpu.flush_traces();
+ m_cpu.flush_traces();
}
@@ -2733,7 +2733,7 @@ void debugger_commands::execute_snap(int ref, int params, const char *param[])
void debugger_commands::execute_source(int ref, int params, const char *param[])
{
- m_cpu.source_script(param[0]);
+ m_cpu.source_script(param[0]);
}
diff --git a/src/emu/debug/debugcmd.h b/src/emu/debug/debugcmd.h
index b771aa84174..7ecfc87958b 100644
--- a/src/emu/debug/debugcmd.h
+++ b/src/emu/debug/debugcmd.h
@@ -157,9 +157,9 @@ private:
void execute_input(int ref, int params, const char **param);
void execute_dumpkbd(int ref, int params, const char **param);
- running_machine& m_machine;
- debugger_cpu& m_cpu;
- debugger_console& m_console;
+ running_machine& m_machine;
+ debugger_cpu& m_cpu;
+ debugger_console& m_console;
global_entry *m_global_array;
cheat_system m_cheat;
diff --git a/src/emu/debug/debugcon.h b/src/emu/debug/debugcon.h
index 5e04d349454..e6e5145119a 100644
--- a/src/emu/debug/debugcon.h
+++ b/src/emu/debug/debugcon.h
@@ -124,12 +124,12 @@ private:
int maxparams;
};
- running_machine &m_machine;
+ running_machine &m_machine;
- text_buffer *m_console_textbuf;
- text_buffer *m_errorlog_textbuf;
+ text_buffer *m_console_textbuf;
+ text_buffer *m_errorlog_textbuf;
- debug_command *m_commandlist;
+ debug_command *m_commandlist;
};
#endif
diff --git a/src/emu/debug/debugcpu.cpp b/src/emu/debug/debugcpu.cpp
index 021d745d0ec..1bc78847b6b 100644
--- a/src/emu/debug/debugcpu.cpp
+++ b/src/emu/debug/debugcpu.cpp
@@ -36,19 +36,19 @@ const size_t debugger_cpu::NUM_TEMP_VARIABLES = 10;
debugger_cpu::debugger_cpu(running_machine &machine)
: m_machine(machine)
- , m_livecpu(nullptr)
- , m_visiblecpu(nullptr)
- , m_breakcpu(nullptr)
- , m_source_file(nullptr)
- , m_symtable(nullptr)
- , m_execution_state(EXECUTION_STATE_STOPPED)
- , m_bpindex(1)
- , m_wpindex(1)
- , m_rpindex(1)
- , m_wpdata(0)
- , m_wpaddr(0)
+ , m_livecpu(nullptr)
+ , m_visiblecpu(nullptr)
+ , m_breakcpu(nullptr)
+ , m_source_file(nullptr)
+ , m_symtable(nullptr)
+ , m_execution_state(EXECUTION_STATE_STOPPED)
+ , m_bpindex(1)
+ , m_wpindex(1)
+ , m_rpindex(1)
+ , m_wpdata(0)
+ , m_wpaddr(0)
, m_last_periodic_update_time(0)
- , m_comments_loaded(false)
+ , m_comments_loaded(false)
{
screen_device *first_screen = m_machine.first_screen();
@@ -327,7 +327,7 @@ bool debugger_cpu::comment_load(bool is_inline)
{
if(is_inline == false)
m_machine.debugger().console().printf("@%s\n", cputag_name);
-
+
if (!device->debug()->comment_import(*cpunode,is_inline))
throw emu_exception();
}
@@ -392,11 +392,11 @@ UINT8 debugger_cpu::read_byte(address_space &space, offs_t address, int apply_tr
result = 0xff;
}
else if (space.device().memory().read(space.spacenum(), address, 1, custom))
- { /* if there is a custom read handler, and it returns true, use that value */
+ { /* if there is a custom read handler, and it returns true, use that value */
result = custom;
}
else
- { /* otherwise, call the byte reading function for the translated address */
+ { /* otherwise, call the byte reading function for the translated address */
result = space.read_byte(address);
}
@@ -419,7 +419,7 @@ UINT16 debugger_cpu::read_word(address_space &space, offs_t address, int apply_t
UINT16 result;
if (!WORD_ALIGNED(address))
- { /* if this is misaligned read, or if there are no word readers, just read two bytes */
+ { /* if this is misaligned read, or if there are no word readers, just read two bytes */
UINT8 byte0 = read_byte(space, address + 0, apply_translation);
UINT8 byte1 = read_byte(space, address + 1, apply_translation);
@@ -430,7 +430,7 @@ UINT16 debugger_cpu::read_word(address_space &space, offs_t address, int apply_t
result = byte1 | (byte0 << 8);
}
else
- { /* otherwise, this proceeds like the byte case */
+ { /* otherwise, this proceeds like the byte case */
/* all accesses from this point on are for the debugger */
m_debugger_access = true;
@@ -443,11 +443,11 @@ UINT16 debugger_cpu::read_word(address_space &space, offs_t address, int apply_t
result = 0xffff;
}
else if (space.device().memory().read(space.spacenum(), address, 2, custom))
- { /* if there is a custom read handler, and it returns true, use that value */
+ { /* if there is a custom read handler, and it returns true, use that value */
result = custom;
}
else
- { /* otherwise, call the byte reading function for the translated address */
+ { /* otherwise, call the byte reading function for the translated address */
result = space.read_word(address);
}
@@ -472,7 +472,7 @@ UINT32 debugger_cpu::read_dword(address_space &space, offs_t address, int apply_
UINT32 result;
if (!DWORD_ALIGNED(address))
- { /* if this is a misaligned read, or if there are no dword readers, just read two words */
+ { /* if this is a misaligned read, or if there are no dword readers, just read two words */
UINT16 word0 = read_word(space, address + 0, apply_translation);
UINT16 word1 = read_word(space, address + 2, apply_translation);
@@ -483,7 +483,7 @@ UINT32 debugger_cpu::read_dword(address_space &space, offs_t address, int apply_
result = word1 | (word0 << 16);
}
else
- { /* otherwise, this proceeds like the byte case */
+ { /* otherwise, this proceeds like the byte case */
/* all accesses from this point on are for the debugger */
m_debugger_access = true;
@@ -491,15 +491,15 @@ UINT32 debugger_cpu::read_dword(address_space &space, offs_t address, int apply_
UINT64 custom;
if (apply_translation && !translate(space, TRANSLATE_READ_DEBUG, &address))
- { /* translate if necessary; if not mapped, return 0xffffffff */
+ { /* translate if necessary; if not mapped, return 0xffffffff */
result = 0xffffffff;
}
else if (space.device().memory().read(space.spacenum(), address, 4, custom))
- { /* if there is a custom read handler, and it returns true, use that value */
+ { /* if there is a custom read handler, and it returns true, use that value */
result = custom;
}
else
- { /* otherwise, call the byte reading function for the translated address */
+ { /* otherwise, call the byte reading function for the translated address */
result = space.read_dword(address);
}
@@ -524,7 +524,7 @@ UINT64 debugger_cpu::read_qword(address_space &space, offs_t address, int apply_
UINT64 result;
if (!QWORD_ALIGNED(address))
- { /* if this is a misaligned read, or if there are no qword readers, just read two dwords */
+ { /* if this is a misaligned read, or if there are no qword readers, just read two dwords */
UINT32 dword0 = read_dword(space, address + 0, apply_translation);
UINT32 dword1 = read_dword(space, address + 4, apply_translation);
@@ -535,7 +535,7 @@ UINT64 debugger_cpu::read_qword(address_space &space, offs_t address, int apply_
result = dword1 | ((UINT64)dword0 << 32);
}
else
- { /* otherwise, this proceeds like the byte case */
+ { /* otherwise, this proceeds like the byte case */
/* all accesses from this point on are for the debugger */
m_debugger_access = true;
@@ -548,11 +548,11 @@ UINT64 debugger_cpu::read_qword(address_space &space, offs_t address, int apply_
result = ~(UINT64)0;
}
else if (space.device().memory().read(space.spacenum(), address, 8, custom))
- { /* if there is a custom read handler, and it returns true, use that value */
+ { /* if there is a custom read handler, and it returns true, use that value */
result = custom;
}
else
- { /* otherwise, call the byte reading function for the translated address */
+ { /* otherwise, call the byte reading function for the translated address */
result = space.read_qword(address);
}
@@ -1528,13 +1528,13 @@ void debugger_cpu::start_hook(device_t *device, bool stop_on_vblank)
if (m_execution_state != EXECUTION_STATE_STOPPED)
{
if (device == m_visiblecpu && osd_ticks() > m_last_periodic_update_time + osd_ticks_per_second() / 4)
- { // check for periodic updates
+ { // check for periodic updates
m_machine.debug_view().update_all();
m_machine.debug_view().flush_osd_updates();
m_last_periodic_update_time = osd_ticks();
}
else if (device == m_breakcpu)
- { // check for pending breaks
+ { // check for pending breaks
m_execution_state = EXECUTION_STATE_STOPPED;
m_breakcpu = nullptr;
}
@@ -2613,7 +2613,7 @@ bool device_debug::comment_export(xml_data_node &curnode)
//-------------------------------------------------
bool device_debug::comment_import(xml_data_node &cpunode,bool is_inline)
-{
+{
// iterate through nodes
for (xml_data_node *datanode = xml_get_sibling(cpunode.child, "comment"); datanode; datanode = xml_get_sibling(datanode->next, "comment"))
{
diff --git a/src/emu/debug/debugcpu.h b/src/emu/debug/debugcpu.h
index 757fc57649a..7dfebf0cb76 100644
--- a/src/emu/debug/debugcpu.h
+++ b/src/emu/debug/debugcpu.h
@@ -603,36 +603,35 @@ private:
/* internal helpers */
void on_vblank(screen_device &device, bool vblank_state);
- running_machine& m_machine;
+ running_machine& m_machine;
- device_t * m_livecpu;
- device_t * m_visiblecpu;
- device_t * m_breakcpu;
+ device_t * m_livecpu;
+ device_t * m_visiblecpu;
+ device_t * m_breakcpu;
- FILE * m_source_file; // script source file
+ FILE * m_source_file; // script source file
- std::unique_ptr<symbol_table> m_symtable; // global symbol table
+ std::unique_ptr<symbol_table> m_symtable; // global symbol table
- bool m_within_instruction_hook;
- bool m_vblank_occurred;
- bool m_memory_modified;
- bool m_debugger_access;
+ bool m_within_instruction_hook;
+ bool m_vblank_occurred;
+ bool m_memory_modified;
+ bool m_debugger_access;
- int m_execution_state;
- device_t * m_stop_when_not_device; // stop execution when the device ceases to be this
+ int m_execution_state;
+ device_t * m_stop_when_not_device; // stop execution when the device ceases to be this
- UINT32 m_bpindex;
- UINT32 m_wpindex;
- UINT32 m_rpindex;
+ UINT32 m_bpindex;
+ UINT32 m_wpindex;
+ UINT32 m_rpindex;
- UINT64 m_wpdata;
- UINT64 m_wpaddr;
+ UINT64 m_wpdata;
+ UINT64 m_wpaddr;
std::unique_ptr<UINT64[]> m_tempvar;
- osd_ticks_t m_last_periodic_update_time;
+ osd_ticks_t m_last_periodic_update_time;
- bool m_comments_loaded;
+ bool m_comments_loaded;
};
#endif
-
diff --git a/src/emu/debug/debughlp.cpp b/src/emu/debug/debughlp.cpp
index d397c726f15..8d66f59d85a 100644
--- a/src/emu/debug/debughlp.cpp
+++ b/src/emu/debug/debughlp.cpp
@@ -1258,7 +1258,7 @@ static const help_item static_help_list[] =
"\n"
" commit[/*] <address>,<comment>\n"
"\n"
- "Adds a string <comment> to the disassembled code at <address> then saves to file. Basically same as comadd + comsave via a single line.\n"
+ "Adds a string <comment> to the disassembled code at <address> then saves to file. Basically same as comadd + comsave via a single line.\n"
"The shortcut for this command is simply '/*'\n"
"\n"
"Examples:\n"
diff --git a/src/emu/debugger.cpp b/src/emu/debugger.cpp
index 52031ff7753..b2e5bfd3fd6 100644
--- a/src/emu/debugger.cpp
+++ b/src/emu/debugger.cpp
@@ -125,7 +125,7 @@ debugger_manager::debugger_manager(running_machine &machine)
/* initialize the submodules */
m_cpu = std::make_unique<debugger_cpu>(machine);
m_console = std::make_unique<debugger_console>(machine);
- m_commands = std::make_unique<debugger_commands>(machine, cpu(), console());
+ m_commands = std::make_unique<debugger_commands>(machine, cpu(), console());
g_machine = &machine;
diff --git a/src/emu/device.cpp b/src/emu/device.cpp
index b2a2e3e325d..2ca2db31e36 100644
--- a/src/emu/device.cpp
+++ b/src/emu/device.cpp
@@ -77,13 +77,13 @@ memory_region *device_t::memregion(const char *_tag) const
if (_tag)
{
auto search = machine().memory().regions().find(subtag(_tag).c_str());
- if (search != machine().memory().regions().end())
- return search->second.get();
- else
+ if (search != machine().memory().regions().end())
+ return search->second.get();
+ else
return nullptr;
- }
+ }
else
- return nullptr;
+ return nullptr;
}
@@ -104,7 +104,7 @@ memory_share *device_t::memshare(const char *_tag) const
return nullptr;
}
else
- return nullptr;
+ return nullptr;
}
diff --git a/src/emu/emumem.cpp b/src/emu/emumem.cpp
index 0b4e66a12ec..243adbc3aea 100644
--- a/src/emu/emumem.cpp
+++ b/src/emu/emumem.cpp
@@ -1766,14 +1766,14 @@ void address_space::allocate(std::vector<std::unique_ptr<address_space>> &space_
case 8:
if (config.endianness() == ENDIANNESS_LITTLE)
{
- if (large)
+ if (large)
space_list.push_back(std::make_unique<address_space_8le_large>(manager, memory, spacenum));
else
space_list.push_back(std::make_unique<address_space_8le_small>(manager, memory, spacenum));
}
else
{
- if (large)
+ if (large)
space_list.push_back(std::make_unique<address_space_8be_large>(manager, memory, spacenum));
else
space_list.push_back(std::make_unique<address_space_8be_small>(manager, memory, spacenum));
@@ -1783,7 +1783,7 @@ void address_space::allocate(std::vector<std::unique_ptr<address_space>> &space_
case 16:
if (config.endianness() == ENDIANNESS_LITTLE)
{
- if (large)
+ if (large)
space_list.push_back(std::make_unique<address_space_16le_large>(manager, memory, spacenum));
else
space_list.push_back(std::make_unique<address_space_16le_small>(manager, memory, spacenum));
@@ -1832,7 +1832,7 @@ void address_space::allocate(std::vector<std::unique_ptr<address_space>> &space_
break;
default:
throw emu_fatalerror("Invalid width %d specified for address_space::allocate", config.data_width());
- }
+ }
}
@@ -2208,7 +2208,7 @@ void address_space::allocate_memory()
// loop over all blocks just allocated and assign pointers from them
address_map_entry *unassigned = nullptr;
-
+
for (auto memblock = blocklist.begin() + tail; memblock != blocklist.end(); ++memblock)
unassigned = block_assign_intersecting(memblock->get()->bytestart(), memblock->get()->byteend(), memblock->get()->data());
@@ -2252,7 +2252,7 @@ void address_space::allocate_memory()
offs_t curbytestart = curblockstart * MEMORY_BLOCK_CHUNK;
offs_t curbyteend = curblockend * MEMORY_BLOCK_CHUNK + (MEMORY_BLOCK_CHUNK - 1);
auto block = std::make_unique<memory_block>(*this, curbytestart, curbyteend);
-
+
// assign memory that intersected the new block
unassigned = block_assign_intersecting(curbytestart, curbyteend, block.get()->data());
blocklist.push_back(std::move(block));
@@ -2577,7 +2577,7 @@ void address_space::install_ram_generic(offs_t addrstart, offs_t addrend, offs_t
{
if (machine().phase() >= MACHINE_PHASE_RESET)
fatalerror("Attempted to call install_ram_generic() after initialization time without a baseptr!\n");
- auto block = std::make_unique<memory_block>(*this, address_to_byte(addrstart), address_to_byte_end(addrend));
+ auto block = std::make_unique<memory_block>(*this, address_to_byte(addrstart), address_to_byte_end(addrend));
bank.set_base(block.get()->data());
manager().m_blocklist.push_back(std::move(block));
}
@@ -4262,7 +4262,7 @@ void memory_bank::configure_entries(int startentry, int numentries, void *base,
//-------------------------------------------------
memory_region::memory_region(running_machine &machine, const char *name, UINT32 length, UINT8 width, endianness_t endian)
- : m_machine(machine),
+ : m_machine(machine),
m_name(name),
m_buffer(length),
m_endianness(endian),
@@ -4474,7 +4474,7 @@ void handler_entry::description(char *buffer) const
m_subunit_infos[i].m_shift,
m_subunit_infos[i].m_offset,
m_subunit_infos[i].m_multiplier,
- m_subunit_infos[i].m_bytemask,
+ m_subunit_infos[i].m_bytemask,
subunit_name(i));
}
}
diff --git a/src/emu/emumem.h b/src/emu/emumem.h
index cf517d84236..f44e34f8060 100644
--- a/src/emu/emumem.h
+++ b/src/emu/emumem.h
@@ -148,9 +148,9 @@ public:
public:
// construction
direct_range(): m_bytestart(0),m_byteend(~0) { }
-
+
inline bool operator==(direct_range val) noexcept
- { // return true if _Left and _Right identify the same thread
+ { // return true if _Left and _Right identify the same thread
return (m_bytestart == val.m_bytestart) && (m_byteend == val.m_byteend);
}
@@ -521,7 +521,7 @@ class memory_bank
// construction/destruction
bank_reference(address_space &space, read_or_write readorwrite)
: m_space(space),
- m_readorwrite(readorwrite) { }
+ m_readorwrite(readorwrite) { }
// getters
address_space &space() const { return m_space; }
diff --git a/src/emu/emuopts.h b/src/emu/emuopts.h
index e3ae4bda6d8..1e7829690c0 100644
--- a/src/emu/emuopts.h
+++ b/src/emu/emuopts.h
@@ -198,7 +198,7 @@ public:
UI_CABINET,
UI_SIMPLE
};
-
+
// construction/destruction
emu_options();
diff --git a/src/emu/hashfile.cpp b/src/emu/hashfile.cpp
index 1d3a2b63171..95341347b97 100644
--- a/src/emu/hashfile.cpp
+++ b/src/emu/hashfile.cpp
@@ -32,7 +32,7 @@ bool read_hash_config(device_image_interface &image, const char *sysname, std::s
pugi::xml_document doc;
pugi::xml_parse_result res = doc.load_file(file.fullpath());
- if (res)
+ if (res)
{
// Do search by CRC32 and SHA1
std::string query = "/hashfile/hash[";
@@ -46,7 +46,7 @@ bool read_hash_config(device_image_interface &image, const char *sysname, std::s
return true;
}
- // Try search by CRC32 only
+ // Try search by CRC32 only
query = "/hashfile/hash[";
query += "@crc32='" + crc + "']/extrainfo";
tools = doc.select_nodes(query.c_str());
diff --git a/src/emu/romload.cpp b/src/emu/romload.cpp
index e158f7ea304..5d832fd2022 100644
--- a/src/emu/romload.cpp
+++ b/src/emu/romload.cpp
@@ -811,7 +811,7 @@ void rom_load_manager::fill_rom_data(const rom_entry *romp)
/* make sure the length was valid */
if (numbytes == 0)
fatalerror("Error in RomModule definition: FILL has an invalid length\n");
-
+
/* fill the data (filling value is stored in place of the hashdata) */
if(skip != 0)
{
diff --git a/src/emu/screen.h b/src/emu/screen.h
index 8a969c5e9b8..4c0d9081a48 100644
--- a/src/emu/screen.h
+++ b/src/emu/screen.h
@@ -54,21 +54,21 @@ const UINT32 UPDATE_HAS_NOT_CHANGED = 0x0001; // the video has not changed
@def VIDEO_UPDATE_BEFORE_VBLANK
update_video called at the start of the VBLANK period
@todo hack, remove me
-
+
@def VIDEO_UPDATE_AFTER_VBLANK
update_video called at the end of the VBLANK period
@todo hack, remove me
@def VIDEO_SELF_RENDER
indicates VIDEO_UPDATE will add container bits itself
-
+
@def VIDEO_ALWAYS_UPDATE
force VIDEO_UPDATE to be called even for skipped frames.
@todo in case you need this one for model updating, then you're doing it wrong (read: hack)
-
+
@def VIDEO_UPDATE_SCANLINE
calls VIDEO_UPDATE for every visible scanline, even for skipped frames
-
+
@}
*/
@@ -377,82 +377,82 @@ typedef device_type_iterator<&device_creator<screen_device>, screen_device> scre
@{
@def MCFG_SCREEN_ADD
Add a new legacy screen color device
-
+
@def MCFG_SCREEN_ADD_MONOCHROME
Add a new legacy monochrome screen device
-
+
@def MCFG_SCREEN_MODIFY
Modify a legacy screen device
-
+
@def MCFG_SCREEN_TYPE
Modify the screen device type
@see screen_type_enum
-
+
@def MCFG_SCREEN_RAW_PARAMS
- Configures screen parameters for the given screen.
+ Configures screen parameters for the given screen.
@remark It's better than using @see MCFG_SCREEN_REFRESH_RATE and @see MCFG_SCREEN_VBLANK_TIME but still not enough.
-
- @param _pixclock
+
+ @param _pixclock
Pixel Clock frequency value
-
- @param _htotal
+
+ @param _htotal
Total number of horizontal pixels, including hblank period.
-
- @param _hbend
+
+ @param _hbend
Horizontal pixel position for HBlank end event, also first pixel where screen rectangle is visible.
-
- @param _hbstart
+
+ @param _hbstart
Horizontal pixel position for HBlank start event, also last pixel where screen rectangle is visible.
-
- @param _vtotal
+
+ @param _vtotal
Total number of vertical pixels, including vblank period.
-
- @param _vbend
+
+ @param _vbend
Vertical pixel position for VBlank end event, also first pixel where screen rectangle is visible.
-
- @param _vbstart
+
+ @param _vbstart
Vertical pixel position for VBlank start event, also last pixel where screen rectangle is visible.
-
+
@def MCFG_SCREEN_REFRESH_RATE
Sets the number of Frames Per Second for this screen
@remarks Please use @see MCFG_SCREEN_RAW_PARAMS instead. Gives imprecise timings.
- @param _rate
+ @param _rate
FPS number
@def MCFG_SCREEN_VBLANK_TIME
Sets the vblank time of the given screen
@remarks Please use @see MCFG_SCREEN_RAW_PARAMS instead. Gives imprecise timings.
-
- @param _time
+
+ @param _time
Time parameter, in attotime value
@def MCFG_SCREEN_SIZE
Sets total screen size, including H/V-Blanks
@remarks Please use @see MCFG_SCREEN_RAW_PARAMS instead. Gives imprecise timings.
-
- @param _width
+
+ @param _width
Screen horizontal size
@param _height
Screen vertical size
-
+
@def MCFG_SCREEN_VISIBLE_AREA
Sets screen visible area
@remarks Please use MCFG_SCREEN_RAW_PARAMS instead. Gives imprecise timings.
- @param _minx
+ @param _minx
Screen left border
-
- @param _maxx
+
+ @param _maxx
Screen right border, must be in N-1 format
-
- @param _miny
+
+ @param _miny
Screen top border
-
- @param _maxx
+
+ @param _maxx
Screen bottom border, must be in N-1 format
-
+
@}
*/
diff --git a/src/frontend/mame/cheat.cpp b/src/frontend/mame/cheat.cpp
index 3f23904c2da..71569aff8b4 100644
--- a/src/frontend/mame/cheat.cpp
+++ b/src/frontend/mame/cheat.cpp
@@ -401,7 +401,7 @@ void cheat_script::save(emu_file &cheatfile) const
cheat_script::script_entry::script_entry(cheat_manager &manager, symbol_table &symbols, const char *filename, xml_data_node &entrynode, bool isaction)
: m_condition(&symbols),
- m_expression(&symbols)
+ m_expression(&symbols)
{
const char *expression = nullptr;
try
@@ -444,7 +444,7 @@ cheat_script::script_entry::script_entry(cheat_manager &manager, symbol_table &s
int totalargs = 0;
for (xml_data_node *argnode = xml_get_sibling(entrynode.child, "argument"); argnode != nullptr; argnode = xml_get_sibling(argnode->next, "argument"))
{
- auto curarg = std::make_unique<output_argument>(manager, symbols, filename, *argnode);
+ auto curarg = std::make_unique<output_argument>(manager, symbols, filename, *argnode);
// verify we didn't overrun the argument count
totalargs += curarg->count();
@@ -610,7 +610,7 @@ void cheat_script::script_entry::validate_format(const char *filename, int line)
cheat_script::script_entry::output_argument::output_argument(cheat_manager &manager, symbol_table &symbols, const char *filename, xml_data_node &argnode)
: m_expression(&symbols),
- m_count(0)
+ m_count(0)
{
// first extract attributes
m_count = xml_get_attribute_int(&argnode, "count", 1);
diff --git a/src/frontend/mame/cheat.h b/src/frontend/mame/cheat.h
index f69e3dfd94c..af68af56ef0 100644
--- a/src/frontend/mame/cheat.h
+++ b/src/frontend/mame/cheat.h
@@ -100,7 +100,7 @@ private:
// construction/destruction
item(const char *text, UINT64 value, int valformat)
: m_text(text),
- m_value(value, valformat) { }
+ m_value(value, valformat) { }
// getters
const number_and_format &value() const { return m_value; }
@@ -175,12 +175,12 @@ private:
void validate_format(const char *filename, int line);
// internal state
- parsed_expression m_condition; // condition under which this is executed
- parsed_expression m_expression; // expression to execute
- std::string m_format; // string format to print
- std::vector<std::unique_ptr<output_argument>> m_arglist; // list of arguments
- INT8 m_line; // which line to print on
- ui::text_layout::text_justify m_justify; // justification when printing
+ parsed_expression m_condition; // condition under which this is executed
+ parsed_expression m_expression; // expression to execute
+ std::string m_format; // string format to print
+ std::vector<std::unique_ptr<output_argument>> m_arglist; // list of arguments
+ INT8 m_line; // which line to print on
+ ui::text_layout::text_justify m_justify; // justification when printing
// constants
static const int MAX_ARGUMENTS = 32;
@@ -306,12 +306,12 @@ private:
std::vector<std::unique_ptr<cheat_entry>> m_cheatlist; // cheat list
UINT64 m_framecount; // frame count
std::vector<std::string> m_output; // array of output strings
- std::vector<ui::text_layout::text_justify> m_justify; // justification for each string
+ std::vector<ui::text_layout::text_justify> m_justify; // justification for each string
UINT8 m_numlines; // number of lines available for output
INT8 m_lastline; // last line used for output
bool m_disabled; // true if the cheat engine is disabled
symbol_table m_symtable; // global symbol table
- std::unique_ptr<debugger_cpu> m_cpu; // debugger interface for cpus/memory
+ std::unique_ptr<debugger_cpu> m_cpu; // debugger interface for cpus/memory
// constants
static constexpr int CHEAT_VERSION = 1;
diff --git a/src/frontend/mame/ui/auditmenu.cpp b/src/frontend/mame/ui/auditmenu.cpp
index 5da65f597c9..84af69df8cc 100644
--- a/src/frontend/mame/ui/auditmenu.cpp
+++ b/src/frontend/mame/ui/auditmenu.cpp
@@ -18,7 +18,6 @@
extern const char UI_VERSION_TAG[];
namespace ui {
-
//-------------------------------------------------
// sort
//-------------------------------------------------
diff --git a/src/frontend/mame/ui/auditmenu.h b/src/frontend/mame/ui/auditmenu.h
index 957fc79ae00..a7427c2861e 100644
--- a/src/frontend/mame/ui/auditmenu.h
+++ b/src/frontend/mame/ui/auditmenu.h
@@ -16,7 +16,6 @@
#include "ui/menu.h"
namespace ui {
-
//-------------------------------------------------
// class audit menu
//-------------------------------------------------
diff --git a/src/frontend/mame/ui/barcode.cpp b/src/frontend/mame/ui/barcode.cpp
index 76bef2757ee..bde8324cb1c 100644
--- a/src/frontend/mame/ui/barcode.cpp
+++ b/src/frontend/mame/ui/barcode.cpp
@@ -14,7 +14,6 @@
#include "ui/ui.h"
namespace ui {
-
// itemrefs for key menu items
#define ITEMREF_NEW_BARCODE ((void *) 0x0001)
#define ITEMREF_ENTER_BARCODE ((void *) 0x0002)
@@ -157,4 +156,4 @@ void menu_barcode_reader::handle()
}
}
-} // namespace ui \ No newline at end of file
+} // namespace ui
diff --git a/src/frontend/mame/ui/barcode.h b/src/frontend/mame/ui/barcode.h
index 5e42e64ce65..114e797a5f8 100644
--- a/src/frontend/mame/ui/barcode.h
+++ b/src/frontend/mame/ui/barcode.h
@@ -17,7 +17,6 @@
#include "ui/devctrl.h"
namespace ui {
-
class menu_barcode_reader : public menu_device_control<barcode_reader_device> {
public:
menu_barcode_reader(mame_ui_manager &mui, render_container *container, barcode_reader_device *device);
diff --git a/src/frontend/mame/ui/cheatopt.cpp b/src/frontend/mame/ui/cheatopt.cpp
index f72eed5d20f..b54e5e7ee3a 100644
--- a/src/frontend/mame/ui/cheatopt.cpp
+++ b/src/frontend/mame/ui/cheatopt.cpp
@@ -18,7 +18,6 @@
namespace ui {
-
// itemrefs for key menu items
#define ITEMREF_CHEATS_RESET_ALL ((void *) 0x0001)
#define ITEMREF_CHEATS_RELOAD_ALL ((void *) 0x0002)
diff --git a/src/frontend/mame/ui/cheatopt.h b/src/frontend/mame/ui/cheatopt.h
index 1bad6fbab9c..349ed4bf29c 100644
--- a/src/frontend/mame/ui/cheatopt.h
+++ b/src/frontend/mame/ui/cheatopt.h
@@ -16,7 +16,6 @@
#include "ui/menu.h"
namespace ui {
-
class menu_cheat : public menu
{
public:
diff --git a/src/frontend/mame/ui/custmenu.cpp b/src/frontend/mame/ui/custmenu.cpp
index 67c056be682..d293bd1c495 100644
--- a/src/frontend/mame/ui/custmenu.cpp
+++ b/src/frontend/mame/ui/custmenu.cpp
@@ -18,7 +18,6 @@
namespace ui {
-
/**************************************************
MENU CUSTOM FILTER
**************************************************/
diff --git a/src/frontend/mame/ui/custmenu.h b/src/frontend/mame/ui/custmenu.h
index 6394e7d245e..9bd4ba9b4ef 100644
--- a/src/frontend/mame/ui/custmenu.h
+++ b/src/frontend/mame/ui/custmenu.h
@@ -18,7 +18,6 @@
#include "ui/utils.h"
namespace ui {
-
// Software region
struct c_sw_region
{
diff --git a/src/frontend/mame/ui/custui.cpp b/src/frontend/mame/ui/custui.cpp
index 4cb4450b9ce..6e9a8a0ca6f 100644
--- a/src/frontend/mame/ui/custui.cpp
+++ b/src/frontend/mame/ui/custui.cpp
@@ -20,7 +20,6 @@
#include "osdepend.h"
namespace ui {
-
const char *const menu_custom_ui::hide_status[] = {
__("Show All"),
__("Hide Filters"),
diff --git a/src/frontend/mame/ui/custui.h b/src/frontend/mame/ui/custui.h
index 7cf10d44a45..4e861bf9618 100644
--- a/src/frontend/mame/ui/custui.h
+++ b/src/frontend/mame/ui/custui.h
@@ -16,7 +16,6 @@
#include "ui/menu.h"
namespace ui {
-
//-------------------------------------------------
// Custom UI menu
//-------------------------------------------------
diff --git a/src/frontend/mame/ui/datfile.cpp b/src/frontend/mame/ui/datfile.cpp
index ea391a9eadf..ee196d11668 100644
--- a/src/frontend/mame/ui/datfile.cpp
+++ b/src/frontend/mame/ui/datfile.cpp
@@ -60,7 +60,7 @@ bool datfile_manager::first_run = true;
//-------------------------------------------------
// ctor
//-------------------------------------------------
-datfile_manager::datfile_manager(running_machine &machine, ui_options &moptions)
+datfile_manager::datfile_manager(running_machine &machine, ui_options &moptions)
: m_machine(machine)
, m_options(moptions)
{
diff --git a/src/frontend/mame/ui/datmenu.cpp b/src/frontend/mame/ui/datmenu.cpp
index 5aa43f74a39..7396541962c 100644
--- a/src/frontend/mame/ui/datmenu.cpp
+++ b/src/frontend/mame/ui/datmenu.cpp
@@ -20,7 +20,6 @@
#include "softlist.h"
namespace ui {
-
//-------------------------------------------------
// ctor / dtor
//-------------------------------------------------
diff --git a/src/frontend/mame/ui/datmenu.h b/src/frontend/mame/ui/datmenu.h
index 44797dd243c..fb896781ef9 100644
--- a/src/frontend/mame/ui/datmenu.h
+++ b/src/frontend/mame/ui/datmenu.h
@@ -23,7 +23,6 @@
struct ui_software_info;
namespace ui {
-
//-------------------------------------------------
// class dats menu
//-------------------------------------------------
diff --git a/src/frontend/mame/ui/devctrl.h b/src/frontend/mame/ui/devctrl.h
index 23c8243ffce..21505e0a0e7 100644
--- a/src/frontend/mame/ui/devctrl.h
+++ b/src/frontend/mame/ui/devctrl.h
@@ -26,7 +26,6 @@
#include "ui/menu.h"
namespace ui {
-
template<class DeviceType>
class menu_device_control : public menu
{
diff --git a/src/frontend/mame/ui/devopt.cpp b/src/frontend/mame/ui/devopt.cpp
index 52e0264b43f..5b3b97a8907 100644
--- a/src/frontend/mame/ui/devopt.cpp
+++ b/src/frontend/mame/ui/devopt.cpp
@@ -14,7 +14,6 @@
namespace ui {
-
/*-------------------------------------------------
device_config - handle the game information
menu
diff --git a/src/frontend/mame/ui/devopt.h b/src/frontend/mame/ui/devopt.h
index 7cc3f26516d..0079291323a 100644
--- a/src/frontend/mame/ui/devopt.h
+++ b/src/frontend/mame/ui/devopt.h
@@ -16,7 +16,6 @@
#include "ui/menu.h"
namespace ui {
-
class menu_device_config : public menu
{
public:
diff --git a/src/frontend/mame/ui/dirmenu.cpp b/src/frontend/mame/ui/dirmenu.cpp
index 1a500e14482..1d63fb1cdde 100644
--- a/src/frontend/mame/ui/dirmenu.cpp
+++ b/src/frontend/mame/ui/dirmenu.cpp
@@ -21,7 +21,6 @@
namespace ui {
-
static int ADDING = 1;
static int CHANGE = 2;
diff --git a/src/frontend/mame/ui/dirmenu.h b/src/frontend/mame/ui/dirmenu.h
index 17cf28726aa..b9f07a33b3e 100644
--- a/src/frontend/mame/ui/dirmenu.h
+++ b/src/frontend/mame/ui/dirmenu.h
@@ -19,7 +19,6 @@
#include <vector>
namespace ui {
-
//-------------------------------------------------
// class directory menu
//-------------------------------------------------
diff --git a/src/frontend/mame/ui/filemngr.cpp b/src/frontend/mame/ui/filemngr.cpp
index ee24c78aa33..403f7373e2c 100644
--- a/src/frontend/mame/ui/filemngr.cpp
+++ b/src/frontend/mame/ui/filemngr.cpp
@@ -23,7 +23,6 @@
namespace ui {
-
/***************************************************************************
FILE MANAGER
***************************************************************************/
@@ -215,4 +214,4 @@ void menu_file_manager::force_file_manager(mame_ui_manager &mui, render_containe
mui.machine().pause();
}
-} // namespace ui \ No newline at end of file
+} // namespace ui
diff --git a/src/frontend/mame/ui/filemngr.h b/src/frontend/mame/ui/filemngr.h
index 4fa88531290..25f364ea487 100644
--- a/src/frontend/mame/ui/filemngr.h
+++ b/src/frontend/mame/ui/filemngr.h
@@ -14,7 +14,6 @@
#define MAME_FRONTEND_UI_FILEMNGR_H
namespace ui {
-
class menu_file_manager : public menu
{
public:
diff --git a/src/frontend/mame/ui/filesel.cpp b/src/frontend/mame/ui/filesel.cpp
index 1fe8c8e0bf4..2dd8efa34ec 100644
--- a/src/frontend/mame/ui/filesel.cpp
+++ b/src/frontend/mame/ui/filesel.cpp
@@ -25,7 +25,6 @@
namespace ui {
-
/***************************************************************************
CONSTANTS
***************************************************************************/
diff --git a/src/frontend/mame/ui/filesel.h b/src/frontend/mame/ui/filesel.h
index 571c11e4413..a487db4e7b7 100644
--- a/src/frontend/mame/ui/filesel.h
+++ b/src/frontend/mame/ui/filesel.h
@@ -18,7 +18,6 @@
class floppy_image_format_t;
namespace ui {
-
// ======================> menu_confirm_save_as
class menu_confirm_save_as : public menu
@@ -101,7 +100,7 @@ private:
bool m_has_create;
int * m_result;
file_selector_entry * m_entrylist;
- std::string m_hover_directory;
+ std::string m_hover_directory;
char m_filename_buffer[1024];
// methods
diff --git a/src/frontend/mame/ui/floppycntrl.cpp b/src/frontend/mame/ui/floppycntrl.cpp
index e80f51babcb..55a496c13ff 100644
--- a/src/frontend/mame/ui/floppycntrl.cpp
+++ b/src/frontend/mame/ui/floppycntrl.cpp
@@ -15,7 +15,6 @@
namespace ui {
-
/***************************************************************************
IMPLEMENTATION
***************************************************************************/
diff --git a/src/frontend/mame/ui/floppycntrl.h b/src/frontend/mame/ui/floppycntrl.h
index 2c9cc310c0d..2902b8bf13c 100644
--- a/src/frontend/mame/ui/floppycntrl.h
+++ b/src/frontend/mame/ui/floppycntrl.h
@@ -17,7 +17,6 @@
#include "formats/flopimg.h"
namespace ui {
-
class menu_control_floppy_image : public menu_control_device_image
{
public:
diff --git a/src/frontend/mame/ui/imgcntrl.cpp b/src/frontend/mame/ui/imgcntrl.cpp
index 3468fa04b2d..06ad1e157b2 100644
--- a/src/frontend/mame/ui/imgcntrl.cpp
+++ b/src/frontend/mame/ui/imgcntrl.cpp
@@ -24,7 +24,6 @@
namespace ui {
-
/***************************************************************************
IMPLEMENTATION
***************************************************************************/
diff --git a/src/frontend/mame/ui/imgcntrl.h b/src/frontend/mame/ui/imgcntrl.h
index aac63a65702..d32acf836b0 100644
--- a/src/frontend/mame/ui/imgcntrl.h
+++ b/src/frontend/mame/ui/imgcntrl.h
@@ -16,7 +16,6 @@
#include "ui/menu.h"
namespace ui {
-
// ======================> menu_control_device_image
class menu_control_device_image : public menu
diff --git a/src/frontend/mame/ui/info.cpp b/src/frontend/mame/ui/info.cpp
index f76d14b89ce..575acc2eca8 100644
--- a/src/frontend/mame/ui/info.cpp
+++ b/src/frontend/mame/ui/info.cpp
@@ -16,7 +16,6 @@
#include "softlist.h"
namespace ui {
-
/*-------------------------------------------------
menu_game_info - handle the game information
menu
diff --git a/src/frontend/mame/ui/info.h b/src/frontend/mame/ui/info.h
index 5e9e6719b2b..e76c33cd669 100644
--- a/src/frontend/mame/ui/info.h
+++ b/src/frontend/mame/ui/info.h
@@ -16,7 +16,6 @@
#include "ui/menu.h"
namespace ui {
-
class menu_game_info : public menu
{
public:
diff --git a/src/frontend/mame/ui/info_pty.cpp b/src/frontend/mame/ui/info_pty.cpp
index 30567a03453..8a8d22e41ce 100644
--- a/src/frontend/mame/ui/info_pty.cpp
+++ b/src/frontend/mame/ui/info_pty.cpp
@@ -14,7 +14,6 @@
namespace ui {
-
menu_pty_info::menu_pty_info(mame_ui_manager &mui, render_container *container) :
menu(mui, container)
{
diff --git a/src/frontend/mame/ui/info_pty.h b/src/frontend/mame/ui/info_pty.h
index acad9005906..46829bd3f0c 100644
--- a/src/frontend/mame/ui/info_pty.h
+++ b/src/frontend/mame/ui/info_pty.h
@@ -16,7 +16,6 @@
#include "ui/menu.h"
namespace ui {
-
class menu_pty_info : public menu
{
public:
diff --git a/src/frontend/mame/ui/inputmap.cpp b/src/frontend/mame/ui/inputmap.cpp
index 0762db03a9e..976dfc590ea 100644
--- a/src/frontend/mame/ui/inputmap.cpp
+++ b/src/frontend/mame/ui/inputmap.cpp
@@ -17,7 +17,6 @@
namespace ui {
-
/***************************************************************************
CONSTANTS
***************************************************************************/
diff --git a/src/frontend/mame/ui/inputmap.h b/src/frontend/mame/ui/inputmap.h
index ef14ef9b064..290125c734f 100644
--- a/src/frontend/mame/ui/inputmap.h
+++ b/src/frontend/mame/ui/inputmap.h
@@ -17,7 +17,6 @@
namespace ui {
-
class menu_input_groups : public menu
{
public:
diff --git a/src/frontend/mame/ui/mainmenu.cpp b/src/frontend/mame/ui/mainmenu.cpp
index 70e766cd38b..827e98b90b6 100644
--- a/src/frontend/mame/ui/mainmenu.cpp
+++ b/src/frontend/mame/ui/mainmenu.cpp
@@ -36,7 +36,6 @@
namespace ui {
-
/***************************************************************************
MENU HANDLERS
***************************************************************************/
diff --git a/src/frontend/mame/ui/mainmenu.h b/src/frontend/mame/ui/mainmenu.h
index 40063bab0d3..0a60d594f92 100644
--- a/src/frontend/mame/ui/mainmenu.h
+++ b/src/frontend/mame/ui/mainmenu.h
@@ -14,7 +14,6 @@
#define MAME_FRONTEND_UI_MAINMENU_H
namespace ui {
-
class menu_main : public menu
{
public:
diff --git a/src/frontend/mame/ui/menu.cpp b/src/frontend/mame/ui/menu.cpp
index 817eb64097c..a3b9b13a255 100644
--- a/src/frontend/mame/ui/menu.cpp
+++ b/src/frontend/mame/ui/menu.cpp
@@ -29,7 +29,6 @@
namespace ui {
-
/***************************************************************************
CONSTANTS
***************************************************************************/
@@ -2446,7 +2445,7 @@ void menu::draw_common_arrow(float origx1, float origy1, float origx2, float ori
float menu::draw_icon(int linenum, void *selectedref, float x0, float y0)
{
- if (!ui_globals::has_icons || (item[0].flags & FLAG_UI_SWLIST))
+ if (!ui_globals::has_icons || (item[0].flags & FLAG_UI_SWLIST))
return 0.0f;
float ud_arrow_width = ui().get_line_height() * container->manager().ui_aspect(container);
@@ -2948,7 +2947,7 @@ void menu::extra_text_draw_box(float origx1, float origx2, float origy, float ys
//-------------------------------------------------
// extra_text_position - given extra text that has
-// been put into a layout, position it
+// been put into a layout, position it
//-------------------------------------------------
void menu::extra_text_position(float origx1, float origx2, float origy, float yspan, text_layout &layout,
diff --git a/src/frontend/mame/ui/menu.h b/src/frontend/mame/ui/menu.h
index d1e3b500898..3d7a60219aa 100644
--- a/src/frontend/mame/ui/menu.h
+++ b/src/frontend/mame/ui/menu.h
@@ -23,7 +23,6 @@
namespace ui {
-
/***************************************************************************
TYPE DEFINITIONS
***************************************************************************/
diff --git a/src/frontend/mame/ui/menuitem.h b/src/frontend/mame/ui/menuitem.h
index 58a8b50d07b..1cfd8f1c1cf 100644
--- a/src/frontend/mame/ui/menuitem.h
+++ b/src/frontend/mame/ui/menuitem.h
@@ -17,7 +17,6 @@
#include "emu.h"
namespace ui {
-
// special menu item for separators
#define MENU_SEPARATOR_ITEM "---"
diff --git a/src/frontend/mame/ui/miscmenu.cpp b/src/frontend/mame/ui/miscmenu.cpp
index f48110dc6da..76b834cefa4 100644
--- a/src/frontend/mame/ui/miscmenu.cpp
+++ b/src/frontend/mame/ui/miscmenu.cpp
@@ -24,7 +24,6 @@
#include "ui/submenu.h"
namespace ui {
-
/***************************************************************************
MENU HANDLERS
***************************************************************************/
diff --git a/src/frontend/mame/ui/miscmenu.h b/src/frontend/mame/ui/miscmenu.h
index 01348d4be41..86d7477c1db 100644
--- a/src/frontend/mame/ui/miscmenu.h
+++ b/src/frontend/mame/ui/miscmenu.h
@@ -21,7 +21,6 @@
namespace ui {
-
class menu_keyboard_mode : public menu
{
public:
diff --git a/src/frontend/mame/ui/optsmenu.cpp b/src/frontend/mame/ui/optsmenu.cpp
index 6872c3498da..32200489888 100644
--- a/src/frontend/mame/ui/optsmenu.cpp
+++ b/src/frontend/mame/ui/optsmenu.cpp
@@ -27,7 +27,6 @@
#include "rendfont.h"
namespace ui {
-
//-------------------------------------------------
// ctor
//-------------------------------------------------
diff --git a/src/frontend/mame/ui/optsmenu.h b/src/frontend/mame/ui/optsmenu.h
index b8ee8ebc628..6c388163d51 100644
--- a/src/frontend/mame/ui/optsmenu.h
+++ b/src/frontend/mame/ui/optsmenu.h
@@ -16,7 +16,6 @@
#include "ui/menu.h"
namespace ui {
-
class menu_game_options : public menu
{
public:
diff --git a/src/frontend/mame/ui/pluginopt.cpp b/src/frontend/mame/ui/pluginopt.cpp
index 71a0a0aceee..b9c0c238033 100644
--- a/src/frontend/mame/ui/pluginopt.cpp
+++ b/src/frontend/mame/ui/pluginopt.cpp
@@ -17,7 +17,6 @@
namespace ui {
-
void menu_plugin::handle()
{
const event *menu_event = process(0);
diff --git a/src/frontend/mame/ui/pluginopt.h b/src/frontend/mame/ui/pluginopt.h
index 9a4470d11f7..83f40b44fd8 100644
--- a/src/frontend/mame/ui/pluginopt.h
+++ b/src/frontend/mame/ui/pluginopt.h
@@ -21,7 +21,6 @@
namespace ui {
-
class menu_plugin : public menu
{
public:
diff --git a/src/frontend/mame/ui/selector.cpp b/src/frontend/mame/ui/selector.cpp
index e1f05e6e47d..ceeec87e199 100644
--- a/src/frontend/mame/ui/selector.cpp
+++ b/src/frontend/mame/ui/selector.cpp
@@ -17,7 +17,6 @@
#include "mame.h"
namespace ui {
-
//-------------------------------------------------
// ctor / dtor
//-------------------------------------------------
diff --git a/src/frontend/mame/ui/selector.h b/src/frontend/mame/ui/selector.h
index 9c13b15c3b3..2b6747e2c80 100644
--- a/src/frontend/mame/ui/selector.h
+++ b/src/frontend/mame/ui/selector.h
@@ -16,7 +16,6 @@
#include "ui/menu.h"
namespace ui {
-
//-------------------------------------------------
// class selector menu
//-------------------------------------------------
diff --git a/src/frontend/mame/ui/selgame.cpp b/src/frontend/mame/ui/selgame.cpp
index 87a8ebaec79..6300bec7d32 100644
--- a/src/frontend/mame/ui/selgame.cpp
+++ b/src/frontend/mame/ui/selgame.cpp
@@ -37,7 +37,6 @@
extern const char UI_VERSION_TAG[];
namespace ui {
-
static bool first_start = true;
static const char *dats_info[] = {
__("General Info"),
@@ -1100,11 +1099,11 @@ void menu_select_game::inkey_select_favorite(const event *menu_event)
// special case for configure machine
else if ((FPTR)ui_swinfo == CONF_MACHINE)
{
- if (m_prev_selected != nullptr)
- {
- ui_software_info *swinfo = (ui_software_info *)m_prev_selected;
+ if (m_prev_selected != nullptr)
+ {
+ ui_software_info *swinfo = (ui_software_info *)m_prev_selected;
menu::stack_push<menu_machine_configure>(ui(), container, (const game_driver *)swinfo->driver);
- }
+ }
return;
}
// special case for configure plugins
diff --git a/src/frontend/mame/ui/selgame.h b/src/frontend/mame/ui/selgame.h
index 074db944b4c..b826dfaf5fc 100644
--- a/src/frontend/mame/ui/selgame.h
+++ b/src/frontend/mame/ui/selgame.h
@@ -17,7 +17,6 @@
namespace ui {
-
class menu_select_game : public menu
{
public:
diff --git a/src/frontend/mame/ui/selsoft.cpp b/src/frontend/mame/ui/selsoft.cpp
index 81c0bc97afe..d88d7bfc904 100644
--- a/src/frontend/mame/ui/selsoft.cpp
+++ b/src/frontend/mame/ui/selsoft.cpp
@@ -29,7 +29,6 @@
namespace ui {
-
std::string reselect_last::driver;
std::string reselect_last::software;
std::string reselect_last::swlist;
diff --git a/src/frontend/mame/ui/selsoft.h b/src/frontend/mame/ui/selsoft.h
index 478f7add19d..faf178565f2 100644
--- a/src/frontend/mame/ui/selsoft.h
+++ b/src/frontend/mame/ui/selsoft.h
@@ -15,7 +15,6 @@
#include "ui/custmenu.h"
namespace ui {
-
using s_bios = std::vector<std::pair<std::string, int>>;
using s_parts = std::unordered_map<std::string, std::string>;
diff --git a/src/frontend/mame/ui/simpleselgame.cpp b/src/frontend/mame/ui/simpleselgame.cpp
index c947279a001..a061eae97f8 100644
--- a/src/frontend/mame/ui/simpleselgame.cpp
+++ b/src/frontend/mame/ui/simpleselgame.cpp
@@ -26,7 +26,6 @@
namespace ui {
-
//-------------------------------------------------
// ctor
//-------------------------------------------------
diff --git a/src/frontend/mame/ui/simpleselgame.h b/src/frontend/mame/ui/simpleselgame.h
index ee185d5b4a6..8df2a047f9a 100644
--- a/src/frontend/mame/ui/simpleselgame.h
+++ b/src/frontend/mame/ui/simpleselgame.h
@@ -18,7 +18,6 @@
class driver_enumerator;
namespace ui {
-
class simple_menu_select_game : public menu {
public:
simple_menu_select_game(mame_ui_manager &mui, render_container *container, const char *gamename);
diff --git a/src/frontend/mame/ui/slider.h b/src/frontend/mame/ui/slider.h
index 7cd4b580831..431fa8fcb94 100644
--- a/src/frontend/mame/ui/slider.h
+++ b/src/frontend/mame/ui/slider.h
@@ -26,7 +26,7 @@ typedef std::function<INT32(running_machine&, void*, int, std::string*, INT32)>
struct slider_state
{
slider_state * next; /* pointer to next slider */
- slider_update update; /* callback */
+ slider_update update; /* callback */
void * arg; /* argument */
INT32 minval; /* minimum value */
INT32 defval; /* default value */
diff --git a/src/frontend/mame/ui/sliders.cpp b/src/frontend/mame/ui/sliders.cpp
index 31904c73a02..f8854b0aaca 100644
--- a/src/frontend/mame/ui/sliders.cpp
+++ b/src/frontend/mame/ui/sliders.cpp
@@ -17,7 +17,6 @@
#include "ui/slider.h"
namespace ui {
-
menu_sliders::menu_sliders(mame_ui_manager &mui, render_container *container, bool menuless_mode) : menu(mui, container)
{
m_menuless_mode = m_hidden = menuless_mode;
@@ -28,7 +27,7 @@ menu_sliders::~menu_sliders()
}
//-------------------------------------------------
-// menu_sliders - handle the sliders menu
+// menu_sliders - handle the sliders menu
//-------------------------------------------------
void menu_sliders::handle()
@@ -132,8 +131,8 @@ void menu_sliders::handle()
//-------------------------------------------------
-// menu_sliders_populate - populate the sliders
-// menu
+// menu_sliders_populate - populate the sliders
+// menu
//-------------------------------------------------
void menu_sliders::populate()
@@ -188,8 +187,8 @@ void menu_sliders::populate()
}
//-------------------------------------------------
-// menu_sliders_custom_render - perform our special
-// rendering
+// menu_sliders_custom_render - perform our special
+// rendering
//-------------------------------------------------
void menu_sliders::custom_render(void *selectedref, float top, float bottom, float x1, float y1, float x2, float y2)
@@ -259,9 +258,9 @@ void menu_sliders::custom_render(void *selectedref, float top, float bottom, flo
//-------------------------------------------------
-// slider_ui_handler - pushes the slider
-// menu on the stack and hands off to the
-// standard menu handler
+// slider_ui_handler - pushes the slider
+// menu on the stack and hands off to the
+// standard menu handler
//-------------------------------------------------
UINT32 menu_sliders::ui_handler(render_container *container, mame_ui_manager &mui)
diff --git a/src/frontend/mame/ui/sliders.h b/src/frontend/mame/ui/sliders.h
index bfb5bc26f4e..147674b7375 100644
--- a/src/frontend/mame/ui/sliders.h
+++ b/src/frontend/mame/ui/sliders.h
@@ -16,7 +16,6 @@
#include "ui/menu.h"
namespace ui {
-
class menu_sliders : public menu
{
public:
diff --git a/src/frontend/mame/ui/slotopt.cpp b/src/frontend/mame/ui/slotopt.cpp
index 5c97dc594a0..a5249739236 100644
--- a/src/frontend/mame/ui/slotopt.cpp
+++ b/src/frontend/mame/ui/slotopt.cpp
@@ -19,7 +19,6 @@
namespace ui {
-
/*-------------------------------------------------
slot_get_current_option - returns
-------------------------------------------------*/
diff --git a/src/frontend/mame/ui/slotopt.h b/src/frontend/mame/ui/slotopt.h
index 923c6131d5e..e1883fe33d7 100644
--- a/src/frontend/mame/ui/slotopt.h
+++ b/src/frontend/mame/ui/slotopt.h
@@ -17,7 +17,6 @@
namespace ui {
-
class menu_slot_devices : public menu
{
public:
diff --git a/src/frontend/mame/ui/sndmenu.cpp b/src/frontend/mame/ui/sndmenu.cpp
index 72c5068c3ac..a4f32222aa6 100644
--- a/src/frontend/mame/ui/sndmenu.cpp
+++ b/src/frontend/mame/ui/sndmenu.cpp
@@ -15,7 +15,6 @@
#include "../osd/modules/lib/osdobj_common.h" // TODO: remove
namespace ui {
-
const int menu_sound_options::m_sound_rate[] = { 11025, 22050, 44100, 48000 };
//-------------------------------------------------
diff --git a/src/frontend/mame/ui/sndmenu.h b/src/frontend/mame/ui/sndmenu.h
index bc7fbeb21b8..171e4016759 100644
--- a/src/frontend/mame/ui/sndmenu.h
+++ b/src/frontend/mame/ui/sndmenu.h
@@ -16,7 +16,6 @@
#include "ui/menu.h"
namespace ui {
-
//-------------------------------------------------
// class sound options menu
//-------------------------------------------------
diff --git a/src/frontend/mame/ui/submenu.cpp b/src/frontend/mame/ui/submenu.cpp
index 6cabf4e784a..4721ed87b1c 100644
--- a/src/frontend/mame/ui/submenu.cpp
+++ b/src/frontend/mame/ui/submenu.cpp
@@ -17,7 +17,6 @@
#include <limits>
namespace ui {
-
std::vector<submenu::option> submenu::misc_options = {
{ submenu::option_type::HEAD, __("Miscellaneous Options") },
{ submenu::option_type::UI, __("Re-select last machine played"), OPTION_REMEMBER_LAST },
diff --git a/src/frontend/mame/ui/submenu.h b/src/frontend/mame/ui/submenu.h
index ccee31ab11e..8631b4b001f 100644
--- a/src/frontend/mame/ui/submenu.h
+++ b/src/frontend/mame/ui/submenu.h
@@ -26,7 +26,6 @@
namespace ui {
-
//-------------------------------------------------
// class ui menu
//-------------------------------------------------
diff --git a/src/frontend/mame/ui/swlist.cpp b/src/frontend/mame/ui/swlist.cpp
index 02def0f940b..05b95153a4a 100644
--- a/src/frontend/mame/ui/swlist.cpp
+++ b/src/frontend/mame/ui/swlist.cpp
@@ -17,7 +17,6 @@
namespace ui {
-
/***************************************************************************
CONSTANTS
***************************************************************************/
diff --git a/src/frontend/mame/ui/swlist.h b/src/frontend/mame/ui/swlist.h
index 7ffccc50ec1..eef8e454139 100644
--- a/src/frontend/mame/ui/swlist.h
+++ b/src/frontend/mame/ui/swlist.h
@@ -15,7 +15,6 @@
namespace ui {
-
// ======================> menu_software_parts
class menu_software_parts : public menu
diff --git a/src/frontend/mame/ui/tapectrl.cpp b/src/frontend/mame/ui/tapectrl.cpp
index 6628af89b03..973de43c1a9 100644
--- a/src/frontend/mame/ui/tapectrl.cpp
+++ b/src/frontend/mame/ui/tapectrl.cpp
@@ -13,7 +13,6 @@
#include "ui/tapectrl.h"
namespace ui {
-
/***************************************************************************
CONSTANTS
***************************************************************************/
diff --git a/src/frontend/mame/ui/tapectrl.h b/src/frontend/mame/ui/tapectrl.h
index 566aed7288a..09f50d844b0 100644
--- a/src/frontend/mame/ui/tapectrl.h
+++ b/src/frontend/mame/ui/tapectrl.h
@@ -17,7 +17,6 @@
#include "ui/devctrl.h"
namespace ui {
-
class menu_tape_control : public menu_device_control<cassette_image_device>
{
public:
diff --git a/src/frontend/mame/ui/text.cpp b/src/frontend/mame/ui/text.cpp
index fbd9e8de5d2..02cc3c59030 100644
--- a/src/frontend/mame/ui/text.cpp
+++ b/src/frontend/mame/ui/text.cpp
@@ -2,9 +2,9 @@
// copyright-holders:Nicola Salmoria, Aaron Giles, Nathan Woods
/*********************************************************************
- text.cpp
+ text.cpp
- Text functionality for MAME's crude user interface
+ Text functionality for MAME's crude user interface
*********************************************************************/
@@ -13,7 +13,6 @@
#include "render.h"
namespace ui {
-
/***************************************************************************
INLINE FUNCTIONS
***************************************************************************/
@@ -91,7 +90,7 @@ text_layout::text_layout(render_font &font, float xscale, float yscale, float wi
text_layout::text_layout(text_layout &&that)
: m_font(that.m_font), m_xscale(that.m_xscale), m_yscale(that.m_yscale), m_width(that.m_width), m_calculated_actual_width(that.m_calculated_actual_width), m_justify(that.m_justify), m_wrap(that.m_wrap), m_lines(std::move(that.m_lines)),
- m_current_line(that.m_current_line), m_last_break(that.m_last_break), m_text_position(that.m_text_position), m_truncating(false)
+ m_current_line(that.m_current_line), m_last_break(that.m_last_break), m_text_position(that.m_text_position), m_truncating(false)
{
that.invalidate_calculated_actual_width();
}
@@ -475,7 +474,7 @@ void text_layout::emit(render_container *container, float x, float y)
for (auto i = 0; i < line->character_count(); i++)
{
auto &ch = line->character(i);
-
+
// position this specific character correctly (TODO - this doesn't
// handle differently sized text (yet)
float char_x = x + line_xoffset + ch.xoffset;
diff --git a/src/frontend/mame/ui/text.h b/src/frontend/mame/ui/text.h
index edcaf35b3c7..5db5aef7216 100644
--- a/src/frontend/mame/ui/text.h
+++ b/src/frontend/mame/ui/text.h
@@ -2,9 +2,9 @@
// copyright-holders:Nicola Salmoria, Aaron Giles, Nathan Woods
/***************************************************************************
- text.h
+ text.h
- Text functionality for MAME's crude user interface
+ Text functionality for MAME's crude user interface
***************************************************************************/
@@ -20,7 +20,6 @@ class render_font;
class render_container;
namespace ui {
-
/***************************************************************************
TYPE DEFINITIONS
***************************************************************************/
diff --git a/src/frontend/mame/ui/ui.h b/src/frontend/mame/ui/ui.h
index d02e9dd2037..77c33c4119b 100644
--- a/src/frontend/mame/ui/ui.h
+++ b/src/frontend/mame/ui/ui.h
@@ -24,7 +24,6 @@
#include "ui/text.h"
namespace ui {
-
class menu_item;
} // namespace ui
@@ -70,57 +69,57 @@ class menu_item;
/* cancel return value for a UI handler */
#define UI_HANDLER_CANCEL ((UINT32)~0)
-#define SLIDER_DEVICE_SPACING 0x0ff
-#define SLIDER_SCREEN_SPACING 0x0f
-#define SLIDER_INPUT_SPACING 0x0f
+#define SLIDER_DEVICE_SPACING 0x0ff
+#define SLIDER_SCREEN_SPACING 0x0f
+#define SLIDER_INPUT_SPACING 0x0f
enum
{
- SLIDER_ID_VOLUME = 0,
+ SLIDER_ID_VOLUME = 0,
SLIDER_ID_MIXERVOL,
- SLIDER_ID_MIXERVOL_LAST = SLIDER_ID_MIXERVOL + SLIDER_DEVICE_SPACING,
+ SLIDER_ID_MIXERVOL_LAST = SLIDER_ID_MIXERVOL + SLIDER_DEVICE_SPACING,
SLIDER_ID_ADJUSTER,
- SLIDER_ID_ADJUSTER_LAST = SLIDER_ID_ADJUSTER + SLIDER_DEVICE_SPACING,
+ SLIDER_ID_ADJUSTER_LAST = SLIDER_ID_ADJUSTER + SLIDER_DEVICE_SPACING,
SLIDER_ID_OVERCLOCK,
- SLIDER_ID_OVERCLOCK_LAST = SLIDER_ID_OVERCLOCK + SLIDER_DEVICE_SPACING,
+ SLIDER_ID_OVERCLOCK_LAST = SLIDER_ID_OVERCLOCK + SLIDER_DEVICE_SPACING,
SLIDER_ID_REFRESH,
- SLIDER_ID_REFRESH_LAST = SLIDER_ID_REFRESH + SLIDER_SCREEN_SPACING,
+ SLIDER_ID_REFRESH_LAST = SLIDER_ID_REFRESH + SLIDER_SCREEN_SPACING,
SLIDER_ID_BRIGHTNESS,
- SLIDER_ID_BRIGHTNESS_LAST = SLIDER_ID_BRIGHTNESS + SLIDER_SCREEN_SPACING,
+ SLIDER_ID_BRIGHTNESS_LAST = SLIDER_ID_BRIGHTNESS + SLIDER_SCREEN_SPACING,
SLIDER_ID_CONTRAST,
- SLIDER_ID_CONTRAST_LAST = SLIDER_ID_CONTRAST + SLIDER_SCREEN_SPACING,
+ SLIDER_ID_CONTRAST_LAST = SLIDER_ID_CONTRAST + SLIDER_SCREEN_SPACING,
SLIDER_ID_GAMMA,
- SLIDER_ID_GAMMA_LAST = SLIDER_ID_GAMMA + SLIDER_SCREEN_SPACING,
+ SLIDER_ID_GAMMA_LAST = SLIDER_ID_GAMMA + SLIDER_SCREEN_SPACING,
SLIDER_ID_XSCALE,
- SLIDER_ID_XSCALE_LAST = SLIDER_ID_XSCALE + SLIDER_SCREEN_SPACING,
+ SLIDER_ID_XSCALE_LAST = SLIDER_ID_XSCALE + SLIDER_SCREEN_SPACING,
SLIDER_ID_YSCALE,
- SLIDER_ID_YSCALE_LAST = SLIDER_ID_YSCALE + SLIDER_SCREEN_SPACING,
+ SLIDER_ID_YSCALE_LAST = SLIDER_ID_YSCALE + SLIDER_SCREEN_SPACING,
SLIDER_ID_XOFFSET,
- SLIDER_ID_XOFFSET_LAST = SLIDER_ID_XOFFSET + SLIDER_SCREEN_SPACING,
+ SLIDER_ID_XOFFSET_LAST = SLIDER_ID_XOFFSET + SLIDER_SCREEN_SPACING,
SLIDER_ID_YOFFSET,
- SLIDER_ID_YOFFSET_LAST = SLIDER_ID_YOFFSET + SLIDER_SCREEN_SPACING,
+ SLIDER_ID_YOFFSET_LAST = SLIDER_ID_YOFFSET + SLIDER_SCREEN_SPACING,
SLIDER_ID_OVERLAY_XSCALE,
- SLIDER_ID_OVERLAY_XSCALE_LAST = SLIDER_ID_OVERLAY_XSCALE + SLIDER_SCREEN_SPACING,
+ SLIDER_ID_OVERLAY_XSCALE_LAST = SLIDER_ID_OVERLAY_XSCALE + SLIDER_SCREEN_SPACING,
SLIDER_ID_OVERLAY_YSCALE,
- SLIDER_ID_OVERLAY_YSCALE_LAST = SLIDER_ID_OVERLAY_YSCALE + SLIDER_SCREEN_SPACING,
+ SLIDER_ID_OVERLAY_YSCALE_LAST = SLIDER_ID_OVERLAY_YSCALE + SLIDER_SCREEN_SPACING,
SLIDER_ID_OVERLAY_XOFFSET,
- SLIDER_ID_OVERLAY_XOFFSET_LAST = SLIDER_ID_OVERLAY_XOFFSET + SLIDER_SCREEN_SPACING,
+ SLIDER_ID_OVERLAY_XOFFSET_LAST = SLIDER_ID_OVERLAY_XOFFSET + SLIDER_SCREEN_SPACING,
SLIDER_ID_OVERLAY_YOFFSET,
- SLIDER_ID_OVERLAY_YOFFSET_LAST = SLIDER_ID_OVERLAY_YOFFSET + SLIDER_SCREEN_SPACING,
+ SLIDER_ID_OVERLAY_YOFFSET_LAST = SLIDER_ID_OVERLAY_YOFFSET + SLIDER_SCREEN_SPACING,
SLIDER_ID_FLICKER,
- SLIDER_ID_FLICKER_LAST = SLIDER_ID_FLICKER + SLIDER_SCREEN_SPACING,
+ SLIDER_ID_FLICKER_LAST = SLIDER_ID_FLICKER + SLIDER_SCREEN_SPACING,
SLIDER_ID_BEAM_WIDTH_MIN,
- SLIDER_ID_BEAM_WIDTH_MIN_LAST = SLIDER_ID_BEAM_WIDTH_MIN + SLIDER_SCREEN_SPACING,
+ SLIDER_ID_BEAM_WIDTH_MIN_LAST = SLIDER_ID_BEAM_WIDTH_MIN + SLIDER_SCREEN_SPACING,
SLIDER_ID_BEAM_WIDTH_MAX,
- SLIDER_ID_BEAM_WIDTH_MAX_LAST = SLIDER_ID_BEAM_WIDTH_MAX + SLIDER_SCREEN_SPACING,
+ SLIDER_ID_BEAM_WIDTH_MAX_LAST = SLIDER_ID_BEAM_WIDTH_MAX + SLIDER_SCREEN_SPACING,
SLIDER_ID_BEAM_INTENSITY,
- SLIDER_ID_BEAM_INTENSITY_LAST = SLIDER_ID_BEAM_INTENSITY + SLIDER_SCREEN_SPACING,
+ SLIDER_ID_BEAM_INTENSITY_LAST = SLIDER_ID_BEAM_INTENSITY + SLIDER_SCREEN_SPACING,
SLIDER_ID_CROSSHAIR_SCALE,
- SLIDER_ID_CROSSHAIR_SCALE_LAST = SLIDER_ID_CROSSHAIR_SCALE + SLIDER_INPUT_SPACING,
+ SLIDER_ID_CROSSHAIR_SCALE_LAST = SLIDER_ID_CROSSHAIR_SCALE + SLIDER_INPUT_SPACING,
SLIDER_ID_CROSSHAIR_OFFSET,
- SLIDER_ID_CROSSHAIR_OFFSET_LAST = SLIDER_ID_CROSSHAIR_OFFSET + SLIDER_INPUT_SPACING,
+ SLIDER_ID_CROSSHAIR_OFFSET_LAST = SLIDER_ID_CROSSHAIR_OFFSET + SLIDER_INPUT_SPACING,
- SLIDER_ID_CORE_LAST = SLIDER_ID_CROSSHAIR_OFFSET,
+ SLIDER_ID_CORE_LAST = SLIDER_ID_CROSSHAIR_OFFSET,
SLIDER_ID_CORE_COUNT
};
@@ -262,7 +261,7 @@ private:
// instance variables
render_font * m_font;
std::function<UINT32 (render_container *)> m_handler_callback;
- ui_callback_type m_handler_callback_type;
+ ui_callback_type m_handler_callback_type;
UINT32 m_handler_param;
bool m_single_step;
bool m_showfps;
diff --git a/src/frontend/mame/ui/utils.cpp b/src/frontend/mame/ui/utils.cpp
index 5ad21c6839c..b706e14682a 100644
--- a/src/frontend/mame/ui/utils.cpp
+++ b/src/frontend/mame/ui/utils.cpp
@@ -98,7 +98,7 @@ std::vector<std::string> tokenize(const std::string &text, char sep)
std::vector<std::string> tokens;
tokens.reserve(64);
std::size_t start = 0, end = 0;
- while ((end = text.find(sep, start)) != std::string::npos)
+ while ((end = text.find(sep, start)) != std::string::npos)
{
std::string temp = text.substr(start, end - start);
if (!temp.empty()) tokens.push_back(temp);
diff --git a/src/frontend/mame/ui/videoopt.cpp b/src/frontend/mame/ui/videoopt.cpp
index f6debc1c0b0..45c1c52e7fa 100644
--- a/src/frontend/mame/ui/videoopt.cpp
+++ b/src/frontend/mame/ui/videoopt.cpp
@@ -15,7 +15,6 @@
#include "rendutil.h"
namespace ui {
-
/*-------------------------------------------------
menu_video_targets - handle the video targets
menu
diff --git a/src/frontend/mame/ui/videoopt.h b/src/frontend/mame/ui/videoopt.h
index 1f772009144..37148054c8d 100644
--- a/src/frontend/mame/ui/videoopt.h
+++ b/src/frontend/mame/ui/videoopt.h
@@ -16,7 +16,6 @@
#include "ui/menu.h"
namespace ui {
-
class menu_video_targets : public menu
{
public:
diff --git a/src/frontend/mame/ui/viewgfx.cpp b/src/frontend/mame/ui/viewgfx.cpp
index 8e55b8ac86f..3d251becbe1 100644
--- a/src/frontend/mame/ui/viewgfx.cpp
+++ b/src/frontend/mame/ui/viewgfx.cpp
@@ -1104,7 +1104,7 @@ static void tilemap_handle_keys(running_machine &machine, ui_gfx_state &state, i
state.tilemap.yoffs = 0;
state.bitmap_dirty = true;
}
-
+
// handle navigation (up,down,left,right)
step = 8;
if (machine.input().code_pressed(KEYCODE_LSHIFT)) step = 1;
diff --git a/src/lib/netlist/plib/pchrono.h b/src/lib/netlist/plib/pchrono.h
index c715ff1c868..efb8cc061b5 100644
--- a/src/lib/netlist/plib/pchrono.h
+++ b/src/lib/netlist/plib/pchrono.h
@@ -82,7 +82,7 @@ namespace chrono {
#endif
- /* Based on "How to Benchmark Code Execution Times on Intel® IA-32 and IA-64
+ /* Based on "How to Benchmark Code Execution Times on Intel?? IA-32 and IA-64
* Instruction Set Architectures", Intel, 2010
*
*/
diff --git a/src/lib/netlist/solver/nld_ms_sm.h b/src/lib/netlist/solver/nld_ms_sm.h
index 9fa71810be7..8fae5243b42 100644
--- a/src/lib/netlist/solver/nld_ms_sm.h
+++ b/src/lib/netlist/solver/nld_ms_sm.h
@@ -13,9 +13,9 @@
* In this specific implementation, u is a unit vector specifying the row which
* changed. Thus v contains the changed column.
*
- * Than z = Aâ»Â¹ u , w = transpose(Aâ»Â¹) v , lambda = v z
+ * Than z = A^-1 u , w = transpose(A^-1) v , lambda = v z
*
- * Aâ»Â¹ <- 1.0 / (1.0 + lambda) * (z x w)
+ * A^-1 <- 1.0 / (1.0 + lambda) * (z x w)
*
* The approach is iterative and applied for each row changed.
*
diff --git a/src/lib/netlist/solver/nld_ms_w.h b/src/lib/netlist/solver/nld_ms_w.h
index f59086c0c83..986eabc16c5 100644
--- a/src/lib/netlist/solver/nld_ms_w.h
+++ b/src/lib/netlist/solver/nld_ms_w.h
@@ -15,7 +15,7 @@
* Whilst the book proposes to invert the matrix R=(I+transpose(V)*Z) we define
*
* w = transpose(V)*y
- * a = Râ»Â¹ * w
+ * a = R^-1 * w
*
* and consequently
*
diff --git a/src/lib/util/timeconv.cpp b/src/lib/util/timeconv.cpp
index 4511aa20d41..e0d41fbde75 100644
--- a/src/lib/util/timeconv.cpp
+++ b/src/lib/util/timeconv.cpp
@@ -2,9 +2,9 @@
// copyright-holders:Vas Crabb, Nathan Woods
/*********************************************************************
- timeconv.cpp
+ timeconv.cpp
- Time conversion utility code
+ Time conversion utility code
***************************************************************************/
@@ -16,21 +16,21 @@
namespace util {
namespace {
/***************************************************************************
- PROTOTYPES
+ PROTOTYPES
***************************************************************************/
util::ntfs_duration calculate_ntfs_offset();
/***************************************************************************
- GLOBAL VARIABLES
+ GLOBAL VARIABLES
***************************************************************************/
util::ntfs_duration f_ntfs_offset(calculate_ntfs_offset());
/***************************************************************************
- IMPLEMENTATION
+ IMPLEMENTATION
***************************************************************************/
util::ntfs_duration calculate_ntfs_offset()
diff --git a/src/lib/util/timeconv.h b/src/lib/util/timeconv.h
index 5d3d4d4905c..ab8fd50fdcd 100644
--- a/src/lib/util/timeconv.h
+++ b/src/lib/util/timeconv.h
@@ -2,9 +2,9 @@
// copyright-holders:Vas Crabb, Nathan Woods
/***************************************************************************
- timeconv.h
+ timeconv.h
- Time conversion utility code
+ Time conversion utility code
***************************************************************************/
@@ -19,16 +19,15 @@
namespace util {
-
/***************************************************************************
- TYPE DEFINITIONS
+ TYPE DEFINITIONS
***************************************************************************/
typedef std::chrono::duration<std::uint64_t, std::ratio<1, 10000000> > ntfs_duration;
/***************************************************************************
- INLINE FUNCTIONS
+ INLINE FUNCTIONS
***************************************************************************/
// -------------------------------------------------
@@ -42,7 +41,7 @@ inline constexpr ntfs_duration ntfs_duration_from_filetime(std::uint32_t high, s
/***************************************************************************
- FUNCTION PROTOTYPES
+ FUNCTION PROTOTYPES
***************************************************************************/
std::chrono::system_clock::time_point system_clock_time_point_from_ntfs_duration(ntfs_duration d);
diff --git a/src/mame/audio/mario.cpp b/src/mame/audio/mario.cpp
index d30fada6968..6e4d5722ec9 100644
--- a/src/mame/audio/mario.cpp
+++ b/src/mame/audio/mario.cpp
@@ -883,7 +883,7 @@ MACHINE_CONFIG_FRAGMENT( mario_audio )
MCFG_CPU_IO_MAP(mario_sound_io_map)
MCFG_SPEAKER_STANDARD_MONO("mono")
-
+
MCFG_GENERIC_LATCH_8_ADD("soundlatch")
MCFG_GENERIC_LATCH_8_ADD("soundlatch2")
MCFG_GENERIC_LATCH_8_ADD("soundlatch3")
diff --git a/src/mame/drivers/8080bw.cpp b/src/mame/drivers/8080bw.cpp
index 1894ebbac57..641f278df1a 100644
--- a/src/mame/drivers/8080bw.cpp
+++ b/src/mame/drivers/8080bw.cpp
@@ -3552,14 +3552,14 @@ ROM_END
ROM_START( sicv1 ) // Original Taito board AA017742B - data match for sicv, just smaller program roms (2708s vs. 2716s)
ROM_REGION( 0x10000, "maincpu", 0 )
- ROM_LOAD( "cv11.s1", 0x0000, 0x0400, CRC(309d4582) SHA1(e60a1a696111502c115ee00d84cd418c85aba9af) )
- ROM_LOAD( "cv12.r1", 0x0400, 0x0400, CRC(70153e09) SHA1(b75068b7738aa232f75272c539fca04b3d0c2c4a) )
- ROM_LOAD( "cv13.np1", 0x0800, 0x0400, CRC(2ca24fee) SHA1(4b516ebd5a777b001443159233d89fc0a331f756) )
- ROM_FILL( 0x0c00, 0x0400, 0xff ) /* rom socket at M1 is unpopulated */
+ ROM_LOAD( "cv11.s1", 0x0000, 0x0400, CRC(309d4582) SHA1(e60a1a696111502c115ee00d84cd418c85aba9af) )
+ ROM_LOAD( "cv12.r1", 0x0400, 0x0400, CRC(70153e09) SHA1(b75068b7738aa232f75272c539fca04b3d0c2c4a) )
+ ROM_LOAD( "cv13.np1", 0x0800, 0x0400, CRC(2ca24fee) SHA1(4b516ebd5a777b001443159233d89fc0a331f756) )
+ ROM_FILL( 0x0c00, 0x0400, 0xff ) /* rom socket at M1 is unpopulated */
ROM_FILL( 0x1000, 0x0400, 0xff ) /* rom socket at L1 is unpopulated */
- ROM_LOAD( "cv14.jk1", 0x1400, 0x0400, CRC(556d9a97) SHA1(fb792e981658d79d1c801b01f06345c237e9e803) )
- ROM_LOAD( "cv15.i1", 0x1800, 0x0400, CRC(ac520cf5) SHA1(47281256083d64a2754b2045c252e74fe5b71153) )
- ROM_LOAD( "cv16.g1", 0x1c00, 0x0400, CRC(285cfb59) SHA1(53eab8ed07dc9ca107e2e91b4556b9424a073530) )
+ ROM_LOAD( "cv14.jk1", 0x1400, 0x0400, CRC(556d9a97) SHA1(fb792e981658d79d1c801b01f06345c237e9e803) )
+ ROM_LOAD( "cv15.i1", 0x1800, 0x0400, CRC(ac520cf5) SHA1(47281256083d64a2754b2045c252e74fe5b71153) )
+ ROM_LOAD( "cv16.g1", 0x1c00, 0x0400, CRC(285cfb59) SHA1(53eab8ed07dc9ca107e2e91b4556b9424a073530) )
ROM_REGION( 0x0800, "proms", 0 ) /* color maps player 1/player 2 */
ROM_LOAD( "cv01.1", 0x0000, 0x0400, CRC(037e16ac) SHA1(d585030aaff428330c91ae94d7cd5c96ebdd67dd) )
@@ -4590,7 +4590,7 @@ ROM_END
/*
------------------------------
-Ozma Wars by SHIN NIHON KIKAKU
+Ozma Wars by SHIN NIHON KIKAKU
------------------------------
Location Type File ID Checksum
diff --git a/src/mame/drivers/abc80x.cpp b/src/mame/drivers/abc80x.cpp
index e02e5fdf0ec..17b09bd9441 100644
--- a/src/mame/drivers/abc80x.cpp
+++ b/src/mame/drivers/abc80x.cpp
@@ -1523,26 +1523,26 @@ ROM_START( abc806 )
ROM_REGION( 0x104, "abc_p3", 0 )
/*
- 1 12MHz
- 2 DOT
- 3 RTF
- 4 GTF
- 5 BTF
- 6 RTB
- 7 GTB
- 8 BTB
- 9 SFG
- 10 GND
- 11 GND
- 12 RFG
- 13 GFG
- 14 >YL
- 15 >BL
- 16 >GL
- 17 >RL
- 18 BFG
- 19 >FGE
- 20 Vcc
+ 1 12MHz
+ 2 DOT
+ 3 RTF
+ 4 GTF
+ 5 BTF
+ 6 RTB
+ 7 GTB
+ 8 BTB
+ 9 SFG
+ 10 GND
+ 11 GND
+ 12 RFG
+ 13 GFG
+ 14 >YL
+ 15 >BL
+ 16 >GL
+ 17 >RL
+ 18 BFG
+ 19 >FGE
+ 20 Vcc
*/
ROM_LOAD( "60 90239-01.1b", 0x000, 0x104, CRC(f3d0ba00) SHA1(bcc0ee26ecac0028aef6bf5cb308133b509bb360) ) // "ABC P3-11" PAL16R4, color encoder
diff --git a/src/mame/drivers/aerofgt.cpp b/src/mame/drivers/aerofgt.cpp
index 6794f8bf8e0..cbd5f8465d0 100644
--- a/src/mame/drivers/aerofgt.cpp
+++ b/src/mame/drivers/aerofgt.cpp
@@ -244,8 +244,8 @@ static ADDRESS_MAP_START( spinlbrk_map, AS_PROGRAM, 16, aerofgt_state )
AM_RANGE(0xfff002, 0xfff003) AM_READ_PORT("IN1") AM_WRITE(aerofgt_bg2scrollx_w)
AM_RANGE(0xfff004, 0xfff005) AM_READ_PORT("DSW")
AM_RANGE(0xfff006, 0xfff007) AM_WRITE(sound_command_w)
-// AM_RANGE(0xfff008, 0xfff009) - read when analog inputs are enabled
-// AM_RANGE(0xfff00a, 0xfff00b) /
+// AM_RANGE(0xfff008, 0xfff009) - read when analog inputs are enabled
+// AM_RANGE(0xfff00a, 0xfff00b) /
ADDRESS_MAP_END
static ADDRESS_MAP_START( turbofrc_map, AS_PROGRAM, 16, aerofgt_state )
@@ -1575,15 +1575,15 @@ static MACHINE_CONFIG_START( karatblzbl, aerofgt_state )
MCFG_VSYSTEM_SPR2_GFXDECODE("gfxdecode")
MCFG_VIDEO_START_OVERRIDE(aerofgt_state,karatblz)
-
+
MCFG_GENERIC_LATCH_8_ADD("soundlatch")
MCFG_GENERIC_LATCH_8_ADD("soundlatch2")
/* sound hardware */
-
+
MCFG_SPEAKER_STANDARD_MONO("mono")
- MCFG_SOUND_ADD("ymsnd", YM3812, XTAL_8MHz/2)
+ MCFG_SOUND_ADD("ymsnd", YM3812, XTAL_8MHz/2)
MCFG_YM3812_IRQ_HANDLER(INPUTLINE("audiocpu", 0))
MCFG_SOUND_ROUTE(ALL_OUTPUTS, "mono", 1.0)
diff --git a/src/mame/drivers/alesis_qs.cpp b/src/mame/drivers/alesis_qs.cpp
index e50e7aa3667..61215c782ad 100644
--- a/src/mame/drivers/alesis_qs.cpp
+++ b/src/mame/drivers/alesis_qs.cpp
@@ -51,41 +51,41 @@ static MACHINE_CONFIG_START( qs7, qs_state )
MCFG_CPU_ADD("maincpu", H83048, XTAL_10MHz) /* FIX-ME! Actual CPU is H8/510 and XTAL value is a guess */
MCFG_CPU_PROGRAM_MAP(qs7_prog_map)
- //MCFG_ALESIS_KEYSCAN_ASIC_ADD("keyscan")
+ //MCFG_ALESIS_KEYSCAN_ASIC_ADD("keyscan")
- /* Alesis Sound Generator ASIC */
- //MCFG_ALESIS_SG_ASIC_ADD("sndgen")
+ /* Alesis Sound Generator ASIC */
+ //MCFG_ALESIS_SG_ASIC_ADD("sndgen")
- /* Alesis Sound Effects Processor ASIC */
- //MCFG_ALESIS_FX_ASIC_ADD("sfx")
+ /* Alesis Sound Effects Processor ASIC */
+ //MCFG_ALESIS_FX_ASIC_ADD("sfx")
/* video hardware */
- //TODO: add LCD display controller here
+ //TODO: add LCD display controller here
/* sound hardware */
//MCFG_SPEAKER_STANDARD_STEREO("stereo")
//MCFG_ALESIS_QS_SERIES_ADD("sound", SND_CLOCK)
//MCFG_SOUND_ROUTE(ALL_OUTPUTS, "stereo", 1.0)
- /* Interfaces */
- //MCFG_PCMCIA_ADD("pcmcia")
- //MIDI
- //RS232
+ /* Interfaces */
+ //MCFG_PCMCIA_ADD("pcmcia")
+ //MIDI
+ //RS232
MACHINE_CONFIG_END
ROM_START( alesqs7 )
ROM_REGION( 0x80000, "maincpu", 0 )
ROM_LOAD( "2-31-0069_q7_v1.02_alesis_sp_09_12_96_cs_dbcc.u18", 0x00000, 0x80000, CRC(6e5404cb) SHA1(f00598b66ab7a83b16105cbb73e09c66ce3493a7) )
-// ROM_REGION( 0x200000, "sound", 0 ) /* Samples ROMs (2Mbyte each) */
-// ROM_LOAD( "?.u?", 0x00000, 0x200000, NO_DUMP )
-// ROM_LOAD( "?.u?", 0x00000, 0x200000, NO_DUMP )
-// ROM_LOAD( "?.u?", 0x00000, 0x200000, NO_DUMP )
-// ROM_LOAD( "?.u?", 0x00000, 0x200000, NO_DUMP )
-// ROM_LOAD( "?.u?", 0x00000, 0x200000, NO_DUMP )
-// ROM_LOAD( "?.u?", 0x00000, 0x200000, NO_DUMP )
-// ROM_LOAD( "?.u?", 0x00000, 0x200000, NO_DUMP )
-// ROM_LOAD( "?.u?", 0x00000, 0x200000, NO_DUMP )
+// ROM_REGION( 0x200000, "sound", 0 ) /* Samples ROMs (2Mbyte each) */
+// ROM_LOAD( "?.u?", 0x00000, 0x200000, NO_DUMP )
+// ROM_LOAD( "?.u?", 0x00000, 0x200000, NO_DUMP )
+// ROM_LOAD( "?.u?", 0x00000, 0x200000, NO_DUMP )
+// ROM_LOAD( "?.u?", 0x00000, 0x200000, NO_DUMP )
+// ROM_LOAD( "?.u?", 0x00000, 0x200000, NO_DUMP )
+// ROM_LOAD( "?.u?", 0x00000, 0x200000, NO_DUMP )
+// ROM_LOAD( "?.u?", 0x00000, 0x200000, NO_DUMP )
+// ROM_LOAD( "?.u?", 0x00000, 0x200000, NO_DUMP )
ROM_END
/* YEAR NAME PARENT COMPAT MACHINE INPUT INIT COMPANY FULLNAME FLAGS */
diff --git a/src/mame/drivers/altair.cpp b/src/mame/drivers/altair.cpp
index b9099974f73..60dc683c006 100644
--- a/src/mame/drivers/altair.cpp
+++ b/src/mame/drivers/altair.cpp
@@ -5,7 +5,7 @@
MITS Altair 8800b Turnkey
04/12/2009 Initial driver by Miodrag Milanovic
-
+
Supposedly introduced October 1977.
Commands:
@@ -17,7 +17,7 @@
D - Memory Dump
J - Jump to address
M - Modify memory
-
+
Reference:
http://www.computercloset.org/MITSAltair8800bt.htm
diff --git a/src/mame/drivers/aristmk5.cpp b/src/mame/drivers/aristmk5.cpp
index afcf9106e49..58d7288de1b 100644
--- a/src/mame/drivers/aristmk5.cpp
+++ b/src/mame/drivers/aristmk5.cpp
@@ -2122,7 +2122,7 @@ ROM_END
ROM_START( topbana )
ARISTOCRAT_MK5_BIOS
ROM_REGION( 0x400000, "game_prg", ROMREGION_ERASEFF )
- ROM_LOAD32_WORD("0100550v.u11", 0x0000002, 0x007fffa, BAD_DUMP CRC(140a73bc) SHA1(3fd88797b6310f5849e901d032fbeb8a2d8604fb) ) // This is a bad .u8 from Indian Dream, not proper Top Banana .u11!!
+ ROM_LOAD32_WORD("0100550v.u11", 0x0000002, 0x007fffa, BAD_DUMP CRC(140a73bc) SHA1(3fd88797b6310f5849e901d032fbeb8a2d8604fb) ) // This is a bad .u8 from Indian Dream, not proper Top Banana .u11!!
ROM_LOAD32_WORD("0100550v.u7", 0x0000000, 0x0080000, CRC(1f60241c) SHA1(3a6207d9c919319fc10b6de63bc030f8d335588e) )
ROM_REGION( 0x800000, "maincpu", ROMREGION_ERASE00 ) /* ARM Code */
@@ -2422,4 +2422,3 @@ GAME( 1996, wcougar, aristmk5, aristmk5_usa, aristmk5, aristmk5_state, aristmk
GAME( 1997, wcougaru, wcougar, aristmk5_usa, aristmk5, aristmk5_state, aristmk5, ROT0, "Aristocrat", "Wild Cougar (NHG0296-04, US)", MACHINE_FLAGS ) // 569/8, D - 19/05/97
GAME( 1999, wthing, aristmk5, aristmk5_usa, aristmk5, aristmk5_state, aristmk5, ROT0, "Aristocrat", "Wild Thing (0101158V, NSW/ACT)", MACHINE_NOT_WORKING | MACHINE_NO_SOUND ) // 608/4, B - 14/12/99
GAME( 1999, wtiger, 0, aristmk5, aristmk5, aristmk5_state, aristmk5, ROT0, "Aristocrat", "White Tiger Classic (0200954V, NSW/ACT)", MACHINE_FLAGS ) // 638/1, B - 08/07/99
-
diff --git a/src/mame/drivers/aristmk6.cpp b/src/mame/drivers/aristmk6.cpp
index 5a192fa1d87..d8094f26c6a 100644
--- a/src/mame/drivers/aristmk6.cpp
+++ b/src/mame/drivers/aristmk6.cpp
@@ -305,7 +305,7 @@ MACHINE_CONFIG_END
ROM_LOAD32_WORD_BIOS( 16,"02061013 System 02 Left", 0x0000002, 0x0100000, CRC(e70a7007) SHA1(0935f924866162d9c0fbdbb99391cbf730a04b76) ) \
ROM_LOAD32_WORD_BIOS( 16,"02061013 System 02 Right", 0x0000000, 0x0100000, CRC(7a8619a5) SHA1(bd03ddb68817c1660b009e102ccf69e5b603b875) ) \
ROM_SYSTEM_BIOS( 17, "bios17", "Aristocrat MK6 Base (03030708)" ) \
- ROM_LOAD32_WORD_BIOS( 17,"03030708 System 03 SA LEFT", 0x0000002, 0x0100000, CRC(4e5ad823) SHA1(77ab1c29c6172cfdcef776222a72b2b44114d4da) ) /* From Scatter Magic II */ \
+ ROM_LOAD32_WORD_BIOS( 17,"03030708 System 03 SA LEFT", 0x0000002, 0x0100000, CRC(4e5ad823) SHA1(77ab1c29c6172cfdcef776222a72b2b44114d4da) ) /* From Scatter Magic II */ \
ROM_LOAD32_WORD_BIOS( 17,"03030708 System 03 SA RIGHT", 0x0000000, 0x0100000, CRC(b4b3c6a5) SHA1(5747f98a6eaa5c24a23d1d76a28b33a3bfbbfd1f) ) \
ROM_SYSTEM_BIOS( 18, "bios18", "Aristocrat MK6 Base (09011001)" ) \
ROM_LOAD32_WORD_BIOS( 18,"09011001_SYSTEM_09_EPROM_NSW_LEFT", 0x0000002, 0x0200000, CRC(229c2e63) SHA1(91fd2b1acb69efe073647e93db9f11042add2feb) ) \
@@ -341,7 +341,7 @@ ROM labels all look basically the same (as with aristmk5.cpp boards)
20151911 NSW
INDIAN DREAMING-LL
742 4MB 6 eproms
- Aristocrat � 2005 P U72
+ Aristocrat 2005 P U72
"ID string" + "Region" + "Game Name" + "Combination No." + "ROM size"
+ "ROM numbers" + "Copyright" + "Location"
@@ -378,12 +378,12 @@ ROM_END
ROM_START( 5dragce )
ARISTMK6_BIOS
ROM_REGION( 0x2000000, "game_rom", ROMREGION_ERASEFF)
- ROM_LOAD32_WORD("0152309.u71", 0x1000002, 0x0400000, CRC(a0f5999e) SHA1(0be0d58588adbdbc7b728f164538d03509f13fe5) ) /* m27v322 */
- ROM_LOAD32_WORD("0152309.u72", 0x0800002, 0x0400000, CRC(e399df66) SHA1(d85a8011ab62b899b18873e4296c12da4291870a) ) /* m27v322 */
- ROM_LOAD32_WORD("0152309.u73", 0x0000002, 0x0400000, CRC(7298e59b) SHA1(b104aec9be996bacad74120f461ad8cd7ef96e09) ) /* m27v322 */
- ROM_LOAD32_WORD("0152309.u84", 0x1000000, 0x0400000, CRC(f37a1ce5) SHA1(8684d64b20e1fe853e3b0f1a31796cddeb8b0dee) ) /* m27v322 */
- ROM_LOAD32_WORD("0152309.u85", 0x0800000, 0x0400000, CRC(4af3cae0) SHA1(79eb28b403aacf3ec7f52a5b3ff9e59ea35933c6) ) /* m27v322 */
- ROM_LOAD32_WORD("0152309.u86", 0x0000000, 0x0400000, CRC(1c3fd707) SHA1(3a9fc3e865c43ae0afa31954b2372487eb729d8a) ) /* m27v322 */
+ ROM_LOAD32_WORD("0152309.u71", 0x1000002, 0x0400000, CRC(a0f5999e) SHA1(0be0d58588adbdbc7b728f164538d03509f13fe5) ) /* m27v322 */
+ ROM_LOAD32_WORD("0152309.u72", 0x0800002, 0x0400000, CRC(e399df66) SHA1(d85a8011ab62b899b18873e4296c12da4291870a) ) /* m27v322 */
+ ROM_LOAD32_WORD("0152309.u73", 0x0000002, 0x0400000, CRC(7298e59b) SHA1(b104aec9be996bacad74120f461ad8cd7ef96e09) ) /* m27v322 */
+ ROM_LOAD32_WORD("0152309.u84", 0x1000000, 0x0400000, CRC(f37a1ce5) SHA1(8684d64b20e1fe853e3b0f1a31796cddeb8b0dee) ) /* m27v322 */
+ ROM_LOAD32_WORD("0152309.u85", 0x0800000, 0x0400000, CRC(4af3cae0) SHA1(79eb28b403aacf3ec7f52a5b3ff9e59ea35933c6) ) /* m27v322 */
+ ROM_LOAD32_WORD("0152309.u86", 0x0000000, 0x0400000, CRC(1c3fd707) SHA1(3a9fc3e865c43ae0afa31954b2372487eb729d8a) ) /* m27v322 */
ROM_END
@@ -561,10 +561,10 @@ ROM_END
ROM_START( arwincm )
ARISTMK6_BIOS
ROM_REGION( 0x2000000, "game_rom", ROMREGION_ERASEFF)
- ROM_LOAD32_WORD("0151065.u72", 0x0800002, 0x0400000, CRC(3a133d96) SHA1(4c7dc422c3e0a81da1f81267d525e3a90a7d79d7) ) /* m27v322 */
- ROM_LOAD32_WORD("0151065.u73", 0x0000002, 0x0400000, CRC(0c3e441c) SHA1(763879bae2b256c2c4edddc99507b3c54cbab976) ) /* m27v322 */
- ROM_LOAD32_WORD("0151065.u85", 0x0800000, 0x0400000, CRC(498b2ab7) SHA1(7f1da5ff34572c1f27f9a0735b8a9571b34ac17e) ) /* m27v322 */
- ROM_LOAD32_WORD("0151065.u86", 0x0000000, 0x0400000, CRC(961cca3d) SHA1(f5bd3fdb8863688a1bf96dcd74a261860a008952) ) /* m27v322 */
+ ROM_LOAD32_WORD("0151065.u72", 0x0800002, 0x0400000, CRC(3a133d96) SHA1(4c7dc422c3e0a81da1f81267d525e3a90a7d79d7) ) /* m27v322 */
+ ROM_LOAD32_WORD("0151065.u73", 0x0000002, 0x0400000, CRC(0c3e441c) SHA1(763879bae2b256c2c4edddc99507b3c54cbab976) ) /* m27v322 */
+ ROM_LOAD32_WORD("0151065.u85", 0x0800000, 0x0400000, CRC(498b2ab7) SHA1(7f1da5ff34572c1f27f9a0735b8a9571b34ac17e) ) /* m27v322 */
+ ROM_LOAD32_WORD("0151065.u86", 0x0000000, 0x0400000, CRC(961cca3d) SHA1(f5bd3fdb8863688a1bf96dcd74a261860a008952) ) /* m27v322 */
ROM_END
@@ -667,14 +667,14 @@ ROM_END
ROM_START( bobdolly )
ARISTMK6_BIOS
ROM_REGION( 0x2000000, "game_rom", ROMREGION_ERASEFF)
- ROM_LOAD32_WORD("0352298.u21", 0x0000000, 0x0400000, CRC(8e32da10) SHA1(28a49ecc3bab512e5828c96392d6fa4ff9394a0f) ) /* 27v322 */
- ROM_LOAD32_WORD("0352298.u11", 0x0000002, 0x0400000, CRC(d3657369) SHA1(621fb20238f10e06c486dfbd6460f94047898a42) ) /* 27v322 */
- ROM_LOAD32_WORD("0352298.u22", 0x0800000, 0x0400000, CRC(4302ae5e) SHA1(fe1d122093ad9234a7a5337b3a4c2de7fe046822) ) /* 27v322 */
- ROM_LOAD32_WORD("0352298.u12", 0x0800002, 0x0400000, CRC(47429081) SHA1(23d996aa522c2f9beadf1fdb7c0584ca939917da) ) /* 27v322 */
- ROM_LOAD32_WORD("0352298.u23", 0x1000000, 0x0400000, CRC(a9726ec5) SHA1(cdf78adc3ebcd50e503b2587564493a91b73f578) ) /* 27v322 */
- ROM_LOAD32_WORD("0352298.u13", 0x1000002, 0x0400000, CRC(e73883db) SHA1(6382386ac6f576c739c959cbf6b6df2605496845) ) /* 27v322 */
- ROM_LOAD32_WORD("0352298.u24", 0x1800000, 0x0400000, CRC(3646c16d) SHA1(c52fab2e11f39c126bcbbb348750bbf30ff96090) ) /* 27v322 */
- ROM_LOAD32_WORD("0352298.u14", 0x1800002, 0x0400000, CRC(0f1a6b7c) SHA1(17686829a1a64f6d8982e015067f2d08bcb00402) ) /* 27v322 */
+ ROM_LOAD32_WORD("0352298.u21", 0x0000000, 0x0400000, CRC(8e32da10) SHA1(28a49ecc3bab512e5828c96392d6fa4ff9394a0f) ) /* 27v322 */
+ ROM_LOAD32_WORD("0352298.u11", 0x0000002, 0x0400000, CRC(d3657369) SHA1(621fb20238f10e06c486dfbd6460f94047898a42) ) /* 27v322 */
+ ROM_LOAD32_WORD("0352298.u22", 0x0800000, 0x0400000, CRC(4302ae5e) SHA1(fe1d122093ad9234a7a5337b3a4c2de7fe046822) ) /* 27v322 */
+ ROM_LOAD32_WORD("0352298.u12", 0x0800002, 0x0400000, CRC(47429081) SHA1(23d996aa522c2f9beadf1fdb7c0584ca939917da) ) /* 27v322 */
+ ROM_LOAD32_WORD("0352298.u23", 0x1000000, 0x0400000, CRC(a9726ec5) SHA1(cdf78adc3ebcd50e503b2587564493a91b73f578) ) /* 27v322 */
+ ROM_LOAD32_WORD("0352298.u13", 0x1000002, 0x0400000, CRC(e73883db) SHA1(6382386ac6f576c739c959cbf6b6df2605496845) ) /* 27v322 */
+ ROM_LOAD32_WORD("0352298.u24", 0x1800000, 0x0400000, CRC(3646c16d) SHA1(c52fab2e11f39c126bcbbb348750bbf30ff96090) ) /* 27v322 */
+ ROM_LOAD32_WORD("0352298.u14", 0x1800002, 0x0400000, CRC(0f1a6b7c) SHA1(17686829a1a64f6d8982e015067f2d08bcb00402) ) /* 27v322 */
ROM_END
@@ -727,7 +727,7 @@ ROM_END
ROM_START( bmbugs )
ARISTMK6_BIOS
ROM_REGION( 0x2000000, "game_rom", ROMREGION_ERASEFF)
- ROM_LOAD32_WORD("0351180.u73", 0x0000002, 0x0400000, CRC(79dd907f) SHA1(06352c55ff36a82f4d0550b1723667f3287c4923) ) /* 27v322 */
+ ROM_LOAD32_WORD("0351180.u73", 0x0000002, 0x0400000, CRC(79dd907f) SHA1(06352c55ff36a82f4d0550b1723667f3287c4923) ) /* 27v322 */
ROM_LOAD32_WORD("0351180.u86", 0x0000000, 0x0400000, CRC(f5c204f9) SHA1(592fac02d26ec5edffce862fcce67869430028dd) )
ROM_END
@@ -959,12 +959,12 @@ ROM_END
ROM_START( dimeyece )
ARISTMK6_BIOS
ROM_REGION( 0x2000000, "game_rom", ROMREGION_ERASEFF)
- ROM_LOAD32_WORD("0152039.u71", 0x1000002, 0x0400000, CRC(5706aa40) SHA1(d847bd0a4e210e3f065aa59129ee4654e3087909) ) /* m27v322 */
- ROM_LOAD32_WORD("0152039.u72", 0x0800002, 0x0400000, CRC(9f6b5923) SHA1(739d3848998ddbfaf577982c12d8edd19c348548) ) /* m27v322 */
- ROM_LOAD32_WORD("0152039.u73", 0x0000002, 0x0400000, CRC(235ba6ca) SHA1(3534b4f74531a42543383b55a2c57853b1d3f4f1) ) /* m27v322 */
- ROM_LOAD32_WORD("0152039.u84", 0x1000000, 0x0400000, CRC(6d0dea65) SHA1(ee23c0fe2ecb5adb5e383757ade9be17880e6b45) ) /* m27v322 */
- ROM_LOAD32_WORD("0152039.u85", 0x0800000, 0x0400000, CRC(f6ef5d9c) SHA1(94505a470ad65e75c6c984ec163ce92c558f491a) ) /* m27v322 */
- ROM_LOAD32_WORD("0152039.u86", 0x0000000, 0x0400000, CRC(926ce073) SHA1(12f0aa1e387f0f87be92afb9a917a30d51a63277) ) /* m27v322 */
+ ROM_LOAD32_WORD("0152039.u71", 0x1000002, 0x0400000, CRC(5706aa40) SHA1(d847bd0a4e210e3f065aa59129ee4654e3087909) ) /* m27v322 */
+ ROM_LOAD32_WORD("0152039.u72", 0x0800002, 0x0400000, CRC(9f6b5923) SHA1(739d3848998ddbfaf577982c12d8edd19c348548) ) /* m27v322 */
+ ROM_LOAD32_WORD("0152039.u73", 0x0000002, 0x0400000, CRC(235ba6ca) SHA1(3534b4f74531a42543383b55a2c57853b1d3f4f1) ) /* m27v322 */
+ ROM_LOAD32_WORD("0152039.u84", 0x1000000, 0x0400000, CRC(6d0dea65) SHA1(ee23c0fe2ecb5adb5e383757ade9be17880e6b45) ) /* m27v322 */
+ ROM_LOAD32_WORD("0152039.u85", 0x0800000, 0x0400000, CRC(f6ef5d9c) SHA1(94505a470ad65e75c6c984ec163ce92c558f491a) ) /* m27v322 */
+ ROM_LOAD32_WORD("0152039.u86", 0x0000000, 0x0400000, CRC(926ce073) SHA1(12f0aa1e387f0f87be92afb9a917a30d51a63277) ) /* m27v322 */
ROM_END
@@ -1145,10 +1145,10 @@ ROM_END
ROM_START( flamoljc )
ARISTMK6_BIOS
ROM_REGION( 0x2000000, "game_rom", ROMREGION_ERASEFF)
- ROM_LOAD32_WORD("0251048.u72", 0x0800002, 0x0400000, CRC(330c1988) SHA1(0d7dae49495c5b164121cd756d6e22af17a9b41b) ) /* m27v322 */
- ROM_LOAD32_WORD("0251048.u73", 0x0000002, 0x0400000, CRC(c8337682) SHA1(e87c5be62528e2e73659ce73a17d1ea21ed3ccf0) ) /* m27v322 */
- ROM_LOAD32_WORD("0251048.u85", 0x0800000, 0x0400000, CRC(2661893a) SHA1(4a79f0b638f5d4fdfa7dcc7661afe3ae1823e6ce) ) /* m27v322 */
- ROM_LOAD32_WORD("0251048.u86", 0x0000000, 0x0400000, CRC(2ea7c6d9) SHA1(cd887f0689737fd447786b966297ea3994fb8cb7) ) /* m27v322 */
+ ROM_LOAD32_WORD("0251048.u72", 0x0800002, 0x0400000, CRC(330c1988) SHA1(0d7dae49495c5b164121cd756d6e22af17a9b41b) ) /* m27v322 */
+ ROM_LOAD32_WORD("0251048.u73", 0x0000002, 0x0400000, CRC(c8337682) SHA1(e87c5be62528e2e73659ce73a17d1ea21ed3ccf0) ) /* m27v322 */
+ ROM_LOAD32_WORD("0251048.u85", 0x0800000, 0x0400000, CRC(2661893a) SHA1(4a79f0b638f5d4fdfa7dcc7661afe3ae1823e6ce) ) /* m27v322 */
+ ROM_LOAD32_WORD("0251048.u86", 0x0000000, 0x0400000, CRC(2ea7c6d9) SHA1(cd887f0689737fd447786b966297ea3994fb8cb7) ) /* m27v322 */
ROM_END
@@ -1183,10 +1183,10 @@ ROM_END
ROM_START( frogwld )
ARISTMK6_BIOS
ROM_REGION( 0x2000000, "game_rom", ROMREGION_ERASEFF)
- ROM_LOAD32_WORD("0251114.u72", 0x0800002, 0x0400000, CRC(36f8066f) SHA1(c8a3dc25488d7d578e05bf247b2d3e0959f5c511) ) /* m27v322 */
- ROM_LOAD32_WORD("0251114.u73", 0x0000002, 0x0400000, CRC(f058f8f3) SHA1(02efb3de7765e917fb6c29cbfdd90845fb3f0a7b) ) /* m27v322 */
- ROM_LOAD32_WORD("0251114.u85", 0x0800000, 0x0400000, CRC(b4165c0f) SHA1(823179a70841f49c8100d8d77620548ceea01550) ) /* m27v322 */
- ROM_LOAD32_WORD("0251114.u86", 0x0000000, 0x0400000, CRC(feb93395) SHA1(56c0f9b0e3616bc57a564220303c13f60fc72df8) ) /* m27v322 */
+ ROM_LOAD32_WORD("0251114.u72", 0x0800002, 0x0400000, CRC(36f8066f) SHA1(c8a3dc25488d7d578e05bf247b2d3e0959f5c511) ) /* m27v322 */
+ ROM_LOAD32_WORD("0251114.u73", 0x0000002, 0x0400000, CRC(f058f8f3) SHA1(02efb3de7765e917fb6c29cbfdd90845fb3f0a7b) ) /* m27v322 */
+ ROM_LOAD32_WORD("0251114.u85", 0x0800000, 0x0400000, CRC(b4165c0f) SHA1(823179a70841f49c8100d8d77620548ceea01550) ) /* m27v322 */
+ ROM_LOAD32_WORD("0251114.u86", 0x0000000, 0x0400000, CRC(feb93395) SHA1(56c0f9b0e3616bc57a564220303c13f60fc72df8) ) /* m27v322 */
ROM_END
@@ -1482,10 +1482,10 @@ ROM_END
ROM_START( jefffox )
ARISTMK6_BIOS
ROM_REGION( 0x2000000, "game_rom", ROMREGION_ERASEFF)
- ROM_LOAD32_WORD("0351068.u72", 0x0800002, 0x0400000, CRC(ff2ff01d) SHA1(c0d17b3d9907d3876c7a1dbc19b023afcffb2bb1) ) /* m27v322 */
- ROM_LOAD32_WORD("0351068.u73", 0x0000002, 0x0400000, CRC(4b778a84) SHA1(d11b2aefcaa2ac22fea80faab524f82511b6344a) ) /* m27v322 */
- ROM_LOAD32_WORD("0351068.u85", 0x0800000, 0x0400000, CRC(52d5395e) SHA1(57b854e516881bc208b48ed82fdef25059e2efab) ) /* m27v322 */
- ROM_LOAD32_WORD("0351068.u86", 0x0000000, 0x0400000, CRC(6b0a7eb3) SHA1(cd99fed52643afa596bfbf4a18deca42043520ef) ) /* m27v322 */
+ ROM_LOAD32_WORD("0351068.u72", 0x0800002, 0x0400000, CRC(ff2ff01d) SHA1(c0d17b3d9907d3876c7a1dbc19b023afcffb2bb1) ) /* m27v322 */
+ ROM_LOAD32_WORD("0351068.u73", 0x0000002, 0x0400000, CRC(4b778a84) SHA1(d11b2aefcaa2ac22fea80faab524f82511b6344a) ) /* m27v322 */
+ ROM_LOAD32_WORD("0351068.u85", 0x0800000, 0x0400000, CRC(52d5395e) SHA1(57b854e516881bc208b48ed82fdef25059e2efab) ) /* m27v322 */
+ ROM_LOAD32_WORD("0351068.u86", 0x0000000, 0x0400000, CRC(6b0a7eb3) SHA1(cd99fed52643afa596bfbf4a18deca42043520ef) ) /* m27v322 */
ROM_END
@@ -1614,8 +1614,8 @@ ROM_END
ROM_START( lovestrk )
ARISTMK6_BIOS
ROM_REGION( 0x2000000, "game_rom", ROMREGION_ERASEFF)
- ROM_LOAD32_WORD("0152583.u73", 0x0000002, 0x0400000, BAD_DUMP CRC(421f717d) SHA1(29eaecef6dd389329a8cfdcfa4bf3f90252eb096) ) /* 27v322 */
- ROM_LOAD32_WORD("0152583.u86", 0x0000000, 0x0400000, CRC(c374ee56) SHA1(18b084c32a4dad6dacd3eeaf6ba430053405dbe8) ) /* 27v322 */
+ ROM_LOAD32_WORD("0152583.u73", 0x0000002, 0x0400000, BAD_DUMP CRC(421f717d) SHA1(29eaecef6dd389329a8cfdcfa4bf3f90252eb096) ) /* 27v322 */
+ ROM_LOAD32_WORD("0152583.u86", 0x0000000, 0x0400000, CRC(c374ee56) SHA1(18b084c32a4dad6dacd3eeaf6ba430053405dbe8) ) /* 27v322 */
ROM_END
@@ -1742,10 +1742,10 @@ ROM_END
ROM_START( mystarr )
ARISTMK6_BIOS
ROM_REGION( 0x2000000, "game_rom", ROMREGION_ERASEFF)
- ROM_LOAD32_WORD("0151009.u72", 0x0800002, 0x0400000, CRC(4aa6e68b) SHA1(5f015885c15fd206053d23983a38dd1dbb8f89ce) ) /* m27v322 */
- ROM_LOAD32_WORD("0151009.u73", 0x0000002, 0x0400000, CRC(7b8ed0d9) SHA1(6ea4bddedef955513e841ee14ec5e6ded23c1ea7) ) /* m27v322 */
- ROM_LOAD32_WORD("0151009.u85", 0x0800000, 0x0400000, CRC(ea82c5db) SHA1(01db2730b1eec5c9f5c011525459ec72903761cc) ) /* m27v322 */
- ROM_LOAD32_WORD("0151009.u86", 0x0000000, 0x0400000, CRC(8a1475ac) SHA1(c948f0ca991b64d9a07e42fdb346e6df450718f2) ) /* m27v322 */
+ ROM_LOAD32_WORD("0151009.u72", 0x0800002, 0x0400000, CRC(4aa6e68b) SHA1(5f015885c15fd206053d23983a38dd1dbb8f89ce) ) /* m27v322 */
+ ROM_LOAD32_WORD("0151009.u73", 0x0000002, 0x0400000, CRC(7b8ed0d9) SHA1(6ea4bddedef955513e841ee14ec5e6ded23c1ea7) ) /* m27v322 */
+ ROM_LOAD32_WORD("0151009.u85", 0x0800000, 0x0400000, CRC(ea82c5db) SHA1(01db2730b1eec5c9f5c011525459ec72903761cc) ) /* m27v322 */
+ ROM_LOAD32_WORD("0151009.u86", 0x0000000, 0x0400000, CRC(8a1475ac) SHA1(c948f0ca991b64d9a07e42fdb346e6df450718f2) ) /* m27v322 */
ROM_END
@@ -1762,10 +1762,10 @@ ROM_END
ROM_START( mysteycmu )
ARISTMK6_BIOS
ROM_REGION( 0x2000000, "game_rom", ROMREGION_ERASEFF)
- ROM_LOAD32_WORD("0251024.u72", 0x0800002, 0x0400000, CRC(380a868e) SHA1(a1ac6ec1a760f8bbf68b3b86cf5dd4623dc130c7) ) /* m27v322 */
- ROM_LOAD32_WORD("0251024.u73", 0x0000002, 0x0400000, CRC(85ad1a00) SHA1(d4f1d86647eb7724c94c3cfa89d5545a20323e62) ) /* m27v322 */
- ROM_LOAD32_WORD("0251024.u85", 0x0800000, 0x0400000, CRC(ee781c0f) SHA1(7729a55e1d5ff7b8a373dda8a0798374ff60a89b) ) /* m27v322 */
- ROM_LOAD32_WORD("0251024.u86", 0x0000000, 0x0400000, CRC(a7bdbd03) SHA1(0e763933c082163de85c408be91d216d6545e9d7) ) /* m27v322 */
+ ROM_LOAD32_WORD("0251024.u72", 0x0800002, 0x0400000, CRC(380a868e) SHA1(a1ac6ec1a760f8bbf68b3b86cf5dd4623dc130c7) ) /* m27v322 */
+ ROM_LOAD32_WORD("0251024.u73", 0x0000002, 0x0400000, CRC(85ad1a00) SHA1(d4f1d86647eb7724c94c3cfa89d5545a20323e62) ) /* m27v322 */
+ ROM_LOAD32_WORD("0251024.u85", 0x0800000, 0x0400000, CRC(ee781c0f) SHA1(7729a55e1d5ff7b8a373dda8a0798374ff60a89b) ) /* m27v322 */
+ ROM_LOAD32_WORD("0251024.u86", 0x0000000, 0x0400000, CRC(a7bdbd03) SHA1(0e763933c082163de85c408be91d216d6545e9d7) ) /* m27v322 */
ROM_END
@@ -1852,10 +1852,10 @@ ROM_END
ROM_START( parislgtu )
ARISTMK6_BIOS
ROM_REGION( 0x2000000, "game_rom", ROMREGION_ERASEFF)
- ROM_LOAD32_WORD("0251031.u72", 0x0800002, 0x0400000, CRC(8dc6a0ec) SHA1(855e8f5c6752bfc4ba25116a20ed82dfb4912c07) ) /* m27v322 */
- ROM_LOAD32_WORD("0251031.u73", 0x0000002, 0x0400000, CRC(d0587548) SHA1(30d0021a78ee79c6f66fb27c8c484427a5a2db1b) ) /* m27v322 */
- ROM_LOAD32_WORD("0251031.u85", 0x0800000, 0x0400000, CRC(e7ed0bf4) SHA1(39cb9744462f10fc791d6c604631c1182da9466b) ) /* m27v322 */
- ROM_LOAD32_WORD("0251031.u86", 0x0000000, 0x0400000, CRC(5224e683) SHA1(8b0dbb2fcea4d1a522160d8a6634687c5bad8acd) ) /* m27v322 */
+ ROM_LOAD32_WORD("0251031.u72", 0x0800002, 0x0400000, CRC(8dc6a0ec) SHA1(855e8f5c6752bfc4ba25116a20ed82dfb4912c07) ) /* m27v322 */
+ ROM_LOAD32_WORD("0251031.u73", 0x0000002, 0x0400000, CRC(d0587548) SHA1(30d0021a78ee79c6f66fb27c8c484427a5a2db1b) ) /* m27v322 */
+ ROM_LOAD32_WORD("0251031.u85", 0x0800000, 0x0400000, CRC(e7ed0bf4) SHA1(39cb9744462f10fc791d6c604631c1182da9466b) ) /* m27v322 */
+ ROM_LOAD32_WORD("0251031.u86", 0x0000000, 0x0400000, CRC(5224e683) SHA1(8b0dbb2fcea4d1a522160d8a6634687c5bad8acd) ) /* m27v322 */
ROM_END
@@ -2006,16 +2006,16 @@ ROM_END
ROM_START( pwsuper )
ARISTMK6_BIOS
ROM_REGION( 0x3000000, "game_rom", ROMREGION_ERASEFF)
- ROM_LOAD32_WORD("0154019.u21", 0x0000000, 0x0400000, CRC(678b0be2) SHA1(16f5460d67a1e897390e0c03b847511f5c14156a) ) /* m27v322 */
- ROM_LOAD32_WORD("0154019.u11", 0x0000002, 0x0400000, CRC(48f60a2c) SHA1(0d27d544991b3403672250ff79c5bbbf35cdf175) ) /* m27v322 */
- ROM_LOAD32_WORD("0154019.u22", 0x0800000, 0x0400000, CRC(9dbdefb7) SHA1(445a24233b435e3812747d8376addf969fea5cd2) ) /* m27v322 */
- ROM_LOAD32_WORD("0154019.u12", 0x0800002, 0x0400000, CRC(5354cff5) SHA1(bf818e53a432aa8e7a2578dbb367be2c5f51bb16) ) /* m27v322 */
- ROM_LOAD32_WORD("0154019.u23", 0x1000000, 0x0400000, CRC(ae04211a) SHA1(8db4fc936fa6d0e0a372b81f2e9590047522b843) ) /* m27v322 */
- ROM_LOAD32_WORD("0154019.u13", 0x1000002, 0x0400000, CRC(43b44f26) SHA1(5410eea0a4911a274a794d6b27e369fb98c6edf7) ) /* m27v322 */
- ROM_LOAD32_WORD("0154019.u24", 0x1800000, 0x0400000, CRC(dbb073f1) SHA1(e3a7f14cabab613453baffde3b592889d11578e7) ) /* m27v322 */
- ROM_LOAD32_WORD("0154019.u14", 0x1800002, 0x0400000, CRC(a850af7f) SHA1(8d029de0083aad57ddd8b36153214b40cd388d56) ) /* m27v322 */
- ROM_LOAD32_WORD("0154019.u25", 0x2000000, 0x0400000, CRC(5f9b8ef7) SHA1(f0c954d1f448f2061dbe284c78eddcfcb5afdc7c) ) /* m27v322 */
- ROM_LOAD32_WORD("0154019.u15", 0x2000002, 0x0400000, CRC(2c7fe966) SHA1(42fc364dded0ce079ce4970b1f951c6a0ebf6c51) ) /* m27v322 */
+ ROM_LOAD32_WORD("0154019.u21", 0x0000000, 0x0400000, CRC(678b0be2) SHA1(16f5460d67a1e897390e0c03b847511f5c14156a) ) /* m27v322 */
+ ROM_LOAD32_WORD("0154019.u11", 0x0000002, 0x0400000, CRC(48f60a2c) SHA1(0d27d544991b3403672250ff79c5bbbf35cdf175) ) /* m27v322 */
+ ROM_LOAD32_WORD("0154019.u22", 0x0800000, 0x0400000, CRC(9dbdefb7) SHA1(445a24233b435e3812747d8376addf969fea5cd2) ) /* m27v322 */
+ ROM_LOAD32_WORD("0154019.u12", 0x0800002, 0x0400000, CRC(5354cff5) SHA1(bf818e53a432aa8e7a2578dbb367be2c5f51bb16) ) /* m27v322 */
+ ROM_LOAD32_WORD("0154019.u23", 0x1000000, 0x0400000, CRC(ae04211a) SHA1(8db4fc936fa6d0e0a372b81f2e9590047522b843) ) /* m27v322 */
+ ROM_LOAD32_WORD("0154019.u13", 0x1000002, 0x0400000, CRC(43b44f26) SHA1(5410eea0a4911a274a794d6b27e369fb98c6edf7) ) /* m27v322 */
+ ROM_LOAD32_WORD("0154019.u24", 0x1800000, 0x0400000, CRC(dbb073f1) SHA1(e3a7f14cabab613453baffde3b592889d11578e7) ) /* m27v322 */
+ ROM_LOAD32_WORD("0154019.u14", 0x1800002, 0x0400000, CRC(a850af7f) SHA1(8d029de0083aad57ddd8b36153214b40cd388d56) ) /* m27v322 */
+ ROM_LOAD32_WORD("0154019.u25", 0x2000000, 0x0400000, CRC(5f9b8ef7) SHA1(f0c954d1f448f2061dbe284c78eddcfcb5afdc7c) ) /* m27v322 */
+ ROM_LOAD32_WORD("0154019.u15", 0x2000002, 0x0400000, CRC(2c7fe966) SHA1(42fc364dded0ce079ce4970b1f951c6a0ebf6c51) ) /* m27v322 */
ROM_END
@@ -2196,10 +2196,10 @@ ROM_END
ROM_START( sealdeal )
ARISTMK6_BIOS
ROM_REGION( 0x2000000, "game_rom", ROMREGION_ERASEFF)
- ROM_LOAD32_WORD("0251029.u72", 0x0800002, 0x0400000, CRC(43ef1218) SHA1(e1d03cd9845ac81a71b5a0471d146addc2f56e0e) ) /* m27v322 */
- ROM_LOAD32_WORD("0251029.u73", 0x0000002, 0x0400000, CRC(383d55a9) SHA1(81bef0ed325ef7208403afa6d7af458c755a4de3) ) /* m27v322 */
- ROM_LOAD32_WORD("0251029.u85", 0x0800000, 0x0400000, CRC(a6327726) SHA1(2c0f02a8d361bcbfc007b9d75a4b7b685aa2b1ac) ) /* m27v322 */
- ROM_LOAD32_WORD("0251029.u86", 0x0000000, 0x0400000, CRC(ea6b666b) SHA1(ad80042770f8e66e7455010b46d81873689f63db) ) /* m27v322 */
+ ROM_LOAD32_WORD("0251029.u72", 0x0800002, 0x0400000, CRC(43ef1218) SHA1(e1d03cd9845ac81a71b5a0471d146addc2f56e0e) ) /* m27v322 */
+ ROM_LOAD32_WORD("0251029.u73", 0x0000002, 0x0400000, CRC(383d55a9) SHA1(81bef0ed325ef7208403afa6d7af458c755a4de3) ) /* m27v322 */
+ ROM_LOAD32_WORD("0251029.u85", 0x0800000, 0x0400000, CRC(a6327726) SHA1(2c0f02a8d361bcbfc007b9d75a4b7b685aa2b1ac) ) /* m27v322 */
+ ROM_LOAD32_WORD("0251029.u86", 0x0000000, 0x0400000, CRC(ea6b666b) SHA1(ad80042770f8e66e7455010b46d81873689f63db) ) /* m27v322 */
ROM_END
@@ -2292,10 +2292,10 @@ ROM_END
ROM_START( stardrftu )
ARISTMK6_BIOS
ROM_REGION( 0x2000000, "game_rom", ROMREGION_ERASEFF)
- ROM_LOAD32_WORD("0451341.u72", 0x0800002, 0x0400000, CRC(dc7a30c1) SHA1(8f24c18efd6171cda7ca841d3b275937e35e2be8) ) /* m27v322 */
- ROM_LOAD32_WORD("0451341.u73", 0x0000002, 0x0400000, CRC(3e59b84f) SHA1(3148d48df74c35681759a234d7aa746cbb0afb0e) ) /* m27v322 */
- ROM_LOAD32_WORD("0451341.u85", 0x0800000, 0x0400000, CRC(689ded33) SHA1(5d5b744321313c4618ecf319827c778be646245f) ) /* m27v322 */
- ROM_LOAD32_WORD("0451341.u86", 0x0000000, 0x0400000, CRC(73023e64) SHA1(4d2d586a1e91ac5bac379994973dffcf9f3a3293) ) /* m27v322 */
+ ROM_LOAD32_WORD("0451341.u72", 0x0800002, 0x0400000, CRC(dc7a30c1) SHA1(8f24c18efd6171cda7ca841d3b275937e35e2be8) ) /* m27v322 */
+ ROM_LOAD32_WORD("0451341.u73", 0x0000002, 0x0400000, CRC(3e59b84f) SHA1(3148d48df74c35681759a234d7aa746cbb0afb0e) ) /* m27v322 */
+ ROM_LOAD32_WORD("0451341.u85", 0x0800000, 0x0400000, CRC(689ded33) SHA1(5d5b744321313c4618ecf319827c778be646245f) ) /* m27v322 */
+ ROM_LOAD32_WORD("0451341.u86", 0x0000000, 0x0400000, CRC(73023e64) SHA1(4d2d586a1e91ac5bac379994973dffcf9f3a3293) ) /* m27v322 */
ROM_END
@@ -2784,13 +2784,13 @@ ROM_END
GAME( 2000, aristmk6, 0, aristmk6, aristmk6, driver_device, 0, ROT0, "Aristocrat", "Aristocrat MK6 System Software", MACHINE_NOT_WORKING | MACHINE_NO_SOUND | MACHINE_IS_BIOS_ROOT)
// Dates listed below are for the combination (reel layout), not release dates
-GAME( 2004, 5drag, aristmk6, aristmk6, aristmk6, driver_device, 0, ROT0, "Aristocrat", "5 Dragons (20161011, NSW/ACT)", MACHINE_NOT_WORKING | MACHINE_NO_SOUND ) // 744, C - 14/01/04
-GAME( 2004, 5dragsp, 5drag, aristmk6, aristmk6, driver_device, 0, ROT0, "Aristocrat", "5 Dragons (20161011, NSW/ACT, Show Program)", MACHINE_NOT_WORKING | MACHINE_NO_SOUND ) // 744, C - 14/01/04
-GAME( 2007, 5dragce, aristmk6, aristmk6, aristmk6, driver_device, 0, ROT0, "Aristocrat", "5 Dragons - Cash Express (0152309, US)", MACHINE_NOT_WORKING | MACHINE_NO_SOUND ) // US211, A - 01/09/07
-GAME( 2007, 5koipp, aristmk6, aristmk6, aristmk6, driver_device, 0, ROT0, "Aristocrat", "5 Koi - Power Pay (10250711, NSW/ACT)", MACHINE_NOT_WORKING | MACHINE_NO_SOUND ) // 744/2, C - 25/10/07
+GAME( 2004, 5drag, aristmk6, aristmk6, aristmk6, driver_device, 0, ROT0, "Aristocrat", "5 Dragons (20161011, NSW/ACT)", MACHINE_NOT_WORKING | MACHINE_NO_SOUND ) // 744, C - 14/01/04
+GAME( 2004, 5dragsp, 5drag, aristmk6, aristmk6, driver_device, 0, ROT0, "Aristocrat", "5 Dragons (20161011, NSW/ACT, Show Program)", MACHINE_NOT_WORKING | MACHINE_NO_SOUND ) // 744, C - 14/01/04
+GAME( 2007, 5dragce, aristmk6, aristmk6, aristmk6, driver_device, 0, ROT0, "Aristocrat", "5 Dragons - Cash Express (0152309, US)", MACHINE_NOT_WORKING | MACHINE_NO_SOUND ) // US211, A - 01/09/07
+GAME( 2007, 5koipp, aristmk6, aristmk6, aristmk6, driver_device, 0, ROT0, "Aristocrat", "5 Koi - Power Pay (10250711, NSW/ACT)", MACHINE_NOT_WORKING | MACHINE_NO_SOUND ) // 744/2, C - 25/10/07
GAME( 2002, 50lions, aristmk6, aristmk6, aristmk6, driver_device, 0, ROT0, "Aristocrat", "50 Lions (10120511, NSW/ACT)", MACHINE_NOT_WORKING | MACHINE_NO_SOUND ) // 717, A - 11/10/02
GAME( 2003, 50lionsm, 50lions, aristmk6, aristmk6, driver_device, 0, ROT0, "Aristocrat", "50 Lions (10156111, Malaysia)", MACHINE_NOT_WORKING | MACHINE_NO_SOUND ) // 717, D - 20/10/03
-GAME( 2012, 50lionrr, aristmk6, aristmk6, aristmk6, driver_device, 0, ROT0, "Aristocrat", "50 Lions - Roaring Riches (20301311, NSW/ACT)", MACHINE_NOT_WORKING | MACHINE_NO_SOUND ) // 1049, B - 20/08/12
+GAME( 2012, 50lionrr, aristmk6, aristmk6, aristmk6, driver_device, 0, ROT0, "Aristocrat", "50 Lions - Roaring Riches (20301311, NSW/ACT)", MACHINE_NOT_WORKING | MACHINE_NO_SOUND ) // 1049, B - 20/08/12
GAME( 2006, 100lions, aristmk6, aristmk6, aristmk6, driver_device, 0, ROT0, "Aristocrat", "100 Lions (10219211, NSW/ACT)", MACHINE_NOT_WORKING | MACHINE_NO_SOUND ) // 717/4, B - 13/06/06
GAME( 2005, adonisa6, aristmk6, aristmk6, aristmk6, driver_device, 0, ROT0, "Aristocrat", "Adonis (0151178, US)", MACHINE_NOT_WORKING | MACHINE_NO_SOUND ) // US168, A - 05/26/05
GAME( 2001, adustcm, aristmk6, aristmk6, aristmk6, driver_device, 0, ROT0, "Aristocrat", "African Dusk - Mr. Cashman (20006711, NSW/ACT)", MACHINE_NOT_WORKING | MACHINE_NO_SOUND ) // 665/1, B- 13/07/01
@@ -2820,7 +2820,7 @@ GAME( 2005, brazil, aristmk6, aristmk6, aristmk6, driver_device, 0, RO
GAME( 2004, bucaneer, aristmk6, aristmk6, aristmk6, driver_device, 0, ROT0, "Aristocrat", "Buccaneer (10173011, NSW/ACT)", MACHINE_NOT_WORKING | MACHINE_NO_SOUND ) // 765, A - 05/04/04
GAME( 2010, buckstop, aristmk6, aristmk6, aristmk6, driver_device, 0, ROT0, "Aristocrat", "The Buck Stops Here (10294311, NSW/ACT)", MACHINE_NOT_WORKING | MACHINE_NO_SOUND ) // 897/1, A - 22/07/10
GAME( 2006, buffalo, aristmk6, aristmk6, aristmk6, driver_device, 0, ROT0, "Aristocrat", "Buffalo (10217811, NSW/ACT)", MACHINE_NOT_WORKING | MACHINE_NO_SOUND ) // 806, E - 06/10/06
-GAME( 200?, buffalou, buffalo, aristmk6, aristmk6, driver_device, 0, ROT0, "Aristocrat", "Buffalo (0252636, US)", MACHINE_NOT_WORKING | MACHINE_NO_SOUND ) // MV4328, (no data)
+GAME( 200?, buffalou, buffalo, aristmk6, aristmk6, driver_device, 0, ROT0, "Aristocrat", "Buffalo (0252636, US)", MACHINE_NOT_WORKING | MACHINE_NO_SOUND ) // MV4328, (no data)
GAME( 2005, bmbugs, aristmk6, aristmk6, aristmk6, driver_device, 0, ROT0, "Aristocrat", "Bumble Bugs (0351180, US)", MACHINE_NOT_WORKING | MACHINE_NO_SOUND ) // US166, A - 05/13/05
GAME( 2001, bushrngr, aristmk6, aristmk6, aristmk6, driver_device, 0, ROT0, "Aristocrat", "Bushranger (10006111, NSW/ACT)", MACHINE_NOT_WORKING | MACHINE_NO_SOUND ) // 673, A - 18/04/01
GAME( 2007, cactusco, aristmk6, aristmk6, aristmk6, driver_device, 0, ROT0, "Aristocrat", "Cactus Corral (10237711, NSW/ACT)", MACHINE_NOT_WORKING | MACHINE_NO_SOUND ) // 818, D - 24/07/07
diff --git a/src/mame/drivers/atarigx2.cpp b/src/mame/drivers/atarigx2.cpp
index 29ec3b5e588..e35dc22e5cb 100644
--- a/src/mame/drivers/atarigx2.cpp
+++ b/src/mame/drivers/atarigx2.cpp
@@ -5,7 +5,7 @@
Atari GX2 hardware
driver by Aaron Giles
-
+
Moto Frenzy protection reverse engineered by:
Morten Shearman Kirkegaard, Samuel Neves, Peter Wilhelmsen
@@ -1181,7 +1181,7 @@ READ32_MEMBER(atarigx2_state::atarigx2_protection_r)
READ32_MEMBER( atarigx2_state::rrreveng_prot_r )
{
- return 0;
+ return 0;
}
@@ -1468,7 +1468,7 @@ static MACHINE_CONFIG_START( atarigx2, atarigx2_state )
MCFG_MACHINE_RESET_OVERRIDE(atarigx2_state,atarigx2)
- MCFG_DEVICE_ADD("xga", ATARI_XGA, 0);
+ MCFG_DEVICE_ADD("xga", ATARI_XGA, 0);
MCFG_ATARI_EEPROM_2816_ADD("eeprom")
@@ -2220,7 +2220,7 @@ ROM_END
DRIVER_INIT_MEMBER(atarigx2_state,spclords)
{
m_playfield_base = 0x000;
- m_maincpu->space(AS_PROGRAM).install_readwrite_handler(0xca0000, 0xca0fff, read32_delegate(FUNC(atarigx2_state::atarigx2_protection_r),this), write32_delegate(FUNC(atarigx2_state::atarigx2_protection_w),this));
+ m_maincpu->space(AS_PROGRAM).install_readwrite_handler(0xca0000, 0xca0fff, read32_delegate(FUNC(atarigx2_state::atarigx2_protection_r),this), write32_delegate(FUNC(atarigx2_state::atarigx2_protection_w),this));
}
@@ -2249,14 +2249,14 @@ XMEM=68.A23*E.A22*!E.A21*68.A20 = 1101 xxxx = d0
+68.A23*E.A22*!E.A21*!68.A20*68.A19 = 1100 1xxx = c80000-cfffff
+!68.A23*!E.A22*!E.A21 = 000x xxxx = 000000-1fffff
*/
- m_maincpu->space(AS_PROGRAM).install_readwrite_handler(0xca0000, 0xca0fff, read32_delegate(FUNC(atari_xga_device::read),&(*m_xga)), write32_delegate(FUNC(atari_xga_device::write),&(*m_xga)));
+ m_maincpu->space(AS_PROGRAM).install_readwrite_handler(0xca0000, 0xca0fff, read32_delegate(FUNC(atari_xga_device::read),&(*m_xga)), write32_delegate(FUNC(atari_xga_device::write),&(*m_xga)));
}
DRIVER_INIT_MEMBER(atarigx2_state,rrreveng)
{
m_playfield_base = 0x000;
- m_maincpu->space(AS_PROGRAM).install_readwrite_handler(0xca0000, 0xca0fff, read32_delegate(FUNC(atarigx2_state::atarigx2_protection_r),this), write32_delegate(FUNC(atarigx2_state::atarigx2_protection_w),this));
+ m_maincpu->space(AS_PROGRAM).install_readwrite_handler(0xca0000, 0xca0fff, read32_delegate(FUNC(atarigx2_state::atarigx2_protection_r),this), write32_delegate(FUNC(atarigx2_state::atarigx2_protection_w),this));
m_maincpu->space(AS_PROGRAM).install_read_handler(0xca0fc0, 0xca0fc3, read32_delegate(FUNC(atarigx2_state::rrreveng_prot_r),this));
}
diff --git a/src/mame/drivers/atlantis.cpp b/src/mame/drivers/atlantis.cpp
index e18abf06d1e..60173f3ce22 100644
--- a/src/mame/drivers/atlantis.cpp
+++ b/src/mame/drivers/atlantis.cpp
@@ -76,7 +76,7 @@
#define LOG_RTC (0)
#define LOG_RED (0)
#define LOG_PORT (0)
-#define LOG_IRQ (0)
+#define LOG_IRQ (0)
class atlantis_state : public driver_device
{
@@ -810,7 +810,7 @@ static MACHINE_CONFIG_START( mwskins, atlantis_state )
MCFG_PCI9050_SET_MAP(3, map3)
MCFG_PCI9050_USER_OUTPUT_CALLBACK(DEVWRITE32(":", atlantis_state, user_io_output))
MCFG_PCI9050_USER_INPUT_CALLBACK(DEVREAD32(":", atlantis_state, user_io_input))
-
+
MCFG_NVRAM_ADD_0FILL("rtc")
MCFG_IDE_PCI_ADD(PCI_ID_IDE, 0x10950646, 0x03, 0x0)
diff --git a/src/mame/drivers/bfcobra.cpp b/src/mame/drivers/bfcobra.cpp
index ae57eaed23e..3523fa6e492 100644
--- a/src/mame/drivers/bfcobra.cpp
+++ b/src/mame/drivers/bfcobra.cpp
@@ -1273,7 +1273,7 @@ ADDRESS_MAP_GLOBAL_MASK(0xff)
AM_RANGE(0x53, 0x53) AM_DEVWRITE("ramdac", ramdac_device, index_r_w)
ADDRESS_MAP_END
-
+
static ADDRESS_MAP_START( ramdac_map, AS_0, 8, bfcobra_state )
AM_RANGE(0x000, 0x3ff) AM_DEVREADWRITE("ramdac", ramdac_device, ramdac_pal_r, ramdac_rgb666_w)
ADDRESS_MAP_END
diff --git a/src/mame/drivers/bloodbro.cpp b/src/mame/drivers/bloodbro.cpp
index 90c1650d460..354d9068285 100644
--- a/src/mame/drivers/bloodbro.cpp
+++ b/src/mame/drivers/bloodbro.cpp
@@ -520,7 +520,7 @@ static MACHINE_CONFIG_DERIVED( weststry, bloodbro )
MCFG_PALETTE_ENTRIES(1024)
MCFG_PALETTE_FORMAT(xxxxBBBBGGGGRRRR)
- // Bootleg video hardware is non-Seibu
+ // Bootleg video hardware is non-Seibu
MCFG_SCREEN_MODIFY("screen")
MCFG_SCREEN_UPDATE_DRIVER(bloodbro_state, screen_update_weststry)
MCFG_DEVICE_REMOVE("crtc")
diff --git a/src/mame/drivers/cclimber.cpp b/src/mame/drivers/cclimber.cpp
index 9c7e887820c..0bad5858b9d 100644
--- a/src/mame/drivers/cclimber.cpp
+++ b/src/mame/drivers/cclimber.cpp
@@ -1937,23 +1937,23 @@ ROM_END
*/
ROM_START( rpatrol )
- ROM_REGION( 0x6000, "maincpu", 0 ) // encrypted
- ROM_LOAD( "1.1h", 0x000000, 0x001000, CRC(065197f0) SHA1(6e482967949bdb126b7ac484abb84c24f4687a3a) )
- ROM_LOAD( "2.1f", 0x001000, 0x001000, CRC(3614b820) SHA1(01966e6ae2ead93797d402bc8d789458b0bdcd75) )
- ROM_LOAD( "3.1d", 0x002000, 0x001000, CRC(ba428bbf) SHA1(ac4cd6ac0adab79bc2cfec3ec2683291c5f0f376) )
- ROM_LOAD( "4.1c", 0x003000, 0x001000, CRC(41497a94) SHA1(7550e74f93c1fd1d5e7fc70c4a2cd2d1b4c22ce5) )
- ROM_LOAD( "5.1a", 0x004000, 0x001000, CRC(e20ee7e7) SHA1(53f7ec5c6805043d3e8f014ade2480cd6dbd94db) )
-
+ ROM_REGION( 0x6000, "maincpu", 0 ) // encrypted
+ ROM_LOAD( "1.1h", 0x000000, 0x001000, CRC(065197f0) SHA1(6e482967949bdb126b7ac484abb84c24f4687a3a) )
+ ROM_LOAD( "2.1f", 0x001000, 0x001000, CRC(3614b820) SHA1(01966e6ae2ead93797d402bc8d789458b0bdcd75) )
+ ROM_LOAD( "3.1d", 0x002000, 0x001000, CRC(ba428bbf) SHA1(ac4cd6ac0adab79bc2cfec3ec2683291c5f0f376) )
+ ROM_LOAD( "4.1c", 0x003000, 0x001000, CRC(41497a94) SHA1(7550e74f93c1fd1d5e7fc70c4a2cd2d1b4c22ce5) )
+ ROM_LOAD( "5.1a", 0x004000, 0x001000, CRC(e20ee7e7) SHA1(53f7ec5c6805043d3e8f014ade2480cd6dbd94db) )
+
ROM_REGION( 0x4000, "gfx1", 0 )
- ROM_LOAD( "6.6l.2732", 0x000000, 0x000800, CRC(b38d8aca) SHA1(b93aa0010b0c0ab23284188a881d4a9bb0fd4582) )
- ROM_CONTINUE( 0x001000, 0x000800 )
- ROM_LOAD( "7.6p.2732", 0x002000, 0x000800, CRC(bc2bddf9) SHA1(4057fc535b1a2db943f893290afe9bfd865ac84b) )
- ROM_CONTINUE( 0x003000, 0x000800 )
+ ROM_LOAD( "6.6l.2732", 0x000000, 0x000800, CRC(b38d8aca) SHA1(b93aa0010b0c0ab23284188a881d4a9bb0fd4582) )
+ ROM_CONTINUE( 0x001000, 0x000800 )
+ ROM_LOAD( "7.6p.2732", 0x002000, 0x000800, CRC(bc2bddf9) SHA1(4057fc535b1a2db943f893290afe9bfd865ac84b) )
+ ROM_CONTINUE( 0x003000, 0x000800 )
ROM_REGION( 0x1000, "gfx2", 0 )
- ROM_LOAD( "9.2t", 0x000000, 0x000800, CRC(d373fc48) SHA1(f06017190955d7458ac652b37c47cee033bc5498) )
- ROM_LOAD( "8.2s", 0x000800, 0x000800, CRC(59747c31) SHA1(92acf07489f3e17f0c1769a0df15b6ddb117830f) )
-
+ ROM_LOAD( "9.2t", 0x000000, 0x000800, CRC(d373fc48) SHA1(f06017190955d7458ac652b37c47cee033bc5498) )
+ ROM_LOAD( "8.2s", 0x000800, 0x000800, CRC(59747c31) SHA1(92acf07489f3e17f0c1769a0df15b6ddb117830f) )
+
ROM_REGION( 0x0060, "proms", 0 )
// probably matches with existing sets
ROM_LOAD( "bprom1.9n", 0x0000, 0x0020, BAD_DUMP CRC(f9a2383b) SHA1(4d88c177740efdb27708474c9ee0fcdca5a78c36) )
diff --git a/src/mame/drivers/chihiro.cpp b/src/mame/drivers/chihiro.cpp
index 0c108510c56..e57641c9630 100644
--- a/src/mame/drivers/chihiro.cpp
+++ b/src/mame/drivers/chihiro.cpp
@@ -646,7 +646,7 @@ static const struct {
} hacks[3] = { { "chihiro", { { 0x6a79f/*3f79f*/, 0x01 }, { 0x6a7a0/*3f7a0*/, 0x00 }, { 0x6b575/*40575*/, 0x00 }, { 0x6b576/*40576*/, 0x00 }, { 0x6b5af/*405af*/, 0x75 }, { 0x6b78a/*4078a*/, 0x75 }, { 0x6b7ca/*407ca*/, 0x00 }, { 0x6b7b8/*407b8*/, 0x00 }, { 0x8f5b2, 0x75 }, { 0x79a9e/*2ea9e*/, 0x74 }, { 0x79b80/*2eb80*/, 0xeb }, { 0x79b97/*2eb97*/, 0x74 }, { 0, 0 } } },
{ "outr2", { { 0x12e4cf, 0x01 }, { 0x12e4d0, 0x00 }, { 0x4793e, 0x01 }, { 0x4793f, 0x00 }, { 0x47aa3, 0x01 }, { 0x47aa4, 0x00 }, { 0x14f2b6, 0x84 }, { 0x14f2d1, 0x75 }, { 0x8732f, 0x7d }, { 0x87384, 0x7d }, { 0x87388, 0xeb }, { 0, 0 } } },
{ "crtaxihr", { { 0x121dce/*f6dce*/, 0xeb }, { 0x121deb/*f6deb*/, 0xeb }, { 0x121fa0/*f6fa0*/, 0xeb }, { 0x14ada5/*11fda5*/, 0x90 }, { 0x14ada6/*11fda6*/, 0x90 }, /*{ 0x8d0bc 620bc , 0xeb },*/ { 0, 0 } } }
- };
+ };
void chihiro_state::hack_usb()
{
diff --git a/src/mame/drivers/deco_ld.cpp b/src/mame/drivers/deco_ld.cpp
index 7101b91cb3b..4ae33ed2bda 100644
--- a/src/mame/drivers/deco_ld.cpp
+++ b/src/mame/drivers/deco_ld.cpp
@@ -468,7 +468,7 @@ static MACHINE_CONFIG_START( rblaster, deco_ld_state )
// MCFG_QUANTUM_TIME(attotime::from_hz(6000))
- MCFG_LASERDISC_LDP1000_ADD("laserdisc")
+ MCFG_LASERDISC_LDP1000_ADD("laserdisc")
MCFG_LASERDISC_OVERLAY_DRIVER(256, 256, deco_ld_state, screen_update_rblaster)
//MCFG_LASERDISC_OVERLAY_CLIP(0, 256-1, 8, 240-1)
MCFG_LASERDISC_OVERLAY_PALETTE("palette")
@@ -482,7 +482,7 @@ static MACHINE_CONFIG_START( rblaster, deco_ld_state )
//MCFG_DEVICE_ADD("acia", ACIA6850, 0)
//MCFG_ACIA6850_TXD_HANDLER(DEVWRITELINE("laserdisc", sony_ldp1000_device, write))
//MCFG_ACIA6850_RXD_HANDLER(DEVREADLINE("laserdisc", sony_ldp1000_device, read))
-
+
/* sound hardware */
/* TODO: mixing */
MCFG_SPEAKER_STANDARD_STEREO("lspeaker", "rspeaker")
diff --git a/src/mame/drivers/divebomb.cpp b/src/mame/drivers/divebomb.cpp
index 65249b6e6ba..e87e3c6d08d 100755
--- a/src/mame/drivers/divebomb.cpp
+++ b/src/mame/drivers/divebomb.cpp
@@ -3,14 +3,14 @@
/***************************************************************************
Kyuukoukabakugekitai - Dive Bomber Squad
-
+
(C) Konami 1989
****************************************************************************
-
+
PCB Layout
----------
-
+
GX840 PWB35165
|--------------------------------------------------------------------------|
| |
@@ -40,22 +40,22 @@
| U22 SN76489 VR |
| |
|--------------------------------------------------------------------------|
-
+
Notes:
There are numerous wire modificationss connecting pins of U15-U18 to
various other components on the PCB
-
+
MB81C86 - 64kx4 SRAM
HM6116AP - 2kx8 SRAM
8464A - 8kx8 SRAM
MN53060KGB - Panasonic CMOS gate array (6016 gates)
051316 - Konami PSAC
CN1/CN2 - ROM board connectors
-
-
+
+
ROM Board
---------
-
+
GX840 PWB451716
|--------------------------|
| |
@@ -68,15 +68,15 @@
| U41 U5 U9 |
| |
|--------------------------|
-
+
Notes:
All ROMs are 27512 EPROMs
-
+
To do:
* Verify layer alignment
* Deduce unknown DIP switch settings
-
+
To verify against original HW:
* Game has no sprites when you reach level 4 and becomes unplayable
* Game often hangs (sprites no longer animate, screen scrolls/rotates endlessly) due to a communication breakdown
@@ -132,44 +132,44 @@ ADDRESS_MAP_END
READ8_MEMBER(divebomb_state::fgcpu_spr_comm_r)
{
- has_fromsprite = false;
- update_irqs();
- return from_sprite;
+ has_fromsprite = false;
+ update_irqs();
+ return from_sprite;
}
WRITE8_MEMBER(divebomb_state::fgcpu_spr_comm_w)
{
- m_spritecpu->set_input_line(INPUT_LINE_IRQ0, ASSERT_LINE);
- to_spritecpu = data;
+ m_spritecpu->set_input_line(INPUT_LINE_IRQ0, ASSERT_LINE);
+ to_spritecpu = data;
}
READ8_MEMBER(divebomb_state::fgcpu_roz_comm_r)
{
- has_fromroz = false;
- update_irqs();
- return from_roz;
+ has_fromroz = false;
+ update_irqs();
+ return from_roz;
}
WRITE8_MEMBER(divebomb_state::fgcpu_roz_comm_w)
{
- m_rozcpucpu->set_input_line(INPUT_LINE_IRQ0, ASSERT_LINE);
- to_rozcpu = data;
+ m_rozcpucpu->set_input_line(INPUT_LINE_IRQ0, ASSERT_LINE);
+ to_rozcpu = data;
}
READ8_MEMBER(divebomb_state::fgcpu_comm_flags_r)
{
- UINT8 result = 0;
-
- if (has_fromroz)
- result |= 1;
- if (has_fromsprite)
- result |= 2;
-
- return result;
+ UINT8 result = 0;
+
+ if (has_fromroz)
+ result |= 1;
+ if (has_fromsprite)
+ result |= 2;
+
+ return result;
}
@@ -183,7 +183,7 @@ READ8_MEMBER(divebomb_state::fgcpu_comm_flags_r)
static ADDRESS_MAP_START( divebomb_spritecpu_map, AS_PROGRAM, 8, divebomb_state )
AM_RANGE(0x0000, 0x7fff) AM_ROM
AM_RANGE(0xc000, 0xc7ff) AM_RAM AM_SHARE("spriteram")
- AM_RANGE(0xc800, 0xdfff) AM_WRITENOP
+ AM_RANGE(0xc800, 0xdfff) AM_WRITENOP
AM_RANGE(0xe000, 0xffff) AM_RAM
ADDRESS_MAP_END
@@ -197,23 +197,23 @@ ADDRESS_MAP_END
READ8_MEMBER(divebomb_state::spritecpu_comm_r)
{
- m_spritecpu->set_input_line(INPUT_LINE_IRQ0, CLEAR_LINE);
- return to_spritecpu;
+ m_spritecpu->set_input_line(INPUT_LINE_IRQ0, CLEAR_LINE);
+ return to_spritecpu;
}
WRITE8_MEMBER(divebomb_state::spritecpu_comm_w)
{
- from_sprite = data;
- has_fromsprite = true;
- update_irqs();
+ from_sprite = data;
+ has_fromsprite = true;
+ update_irqs();
}
WRITE8_MEMBER(divebomb_state::spritecpu_port00_w)
{
- // Written with 0x00 on reset
- // Written with 0x34 7 times in succession on occasion (see PC:0x00E3)
+ // Written with 0x00 on reset
+ // Written with 0x34 7 times in succession on occasion (see PC:0x00E3)
}
@@ -226,7 +226,7 @@ WRITE8_MEMBER(divebomb_state::spritecpu_port00_w)
static ADDRESS_MAP_START( divebomb_rozcpu_map, AS_PROGRAM, 8, divebomb_state )
AM_RANGE(0x0000, 0x7fff) AM_ROM
- AM_RANGE(0x8000, 0xbfff) AM_ROMBANK("bank1")
+ AM_RANGE(0x8000, 0xbfff) AM_ROMBANK("bank1")
AM_RANGE(0xc000, 0xc7ff) AM_RAM AM_DEVREADWRITE("k051316_1", k051316_device, read, write)
AM_RANGE(0xd000, 0xd7ff) AM_RAM AM_DEVREADWRITE("k051316_2", k051316_device, read, write)
AM_RANGE(0xe000, 0xffff) AM_RAM
@@ -249,26 +249,26 @@ ADDRESS_MAP_END
WRITE8_MEMBER(divebomb_state::rozcpu_bank_w)
{
- UINT32 bank = BITSWAP8(data, 4, 5, 6, 7, 3, 2, 1, 0) >> 4;
- m_bank1->set_entry(bank);
+ UINT32 bank = BITSWAP8(data, 4, 5, 6, 7, 3, 2, 1, 0) >> 4;
+ m_bank1->set_entry(bank);
- if (data & 0x0f)
- logerror("rozcpu_bank_w %02x\n", data);
+ if (data & 0x0f)
+ logerror("rozcpu_bank_w %02x\n", data);
}
READ8_MEMBER(divebomb_state::rozcpu_comm_r)
{
- m_rozcpucpu->set_input_line(INPUT_LINE_IRQ0, CLEAR_LINE);
- return to_rozcpu;
+ m_rozcpucpu->set_input_line(INPUT_LINE_IRQ0, CLEAR_LINE);
+ return to_rozcpu;
}
WRITE8_MEMBER(divebomb_state::rozcpu_comm_w)
{
- from_roz = data;
- has_fromroz = true;
- update_irqs();
+ from_roz = data;
+ has_fromroz = true;
+ update_irqs();
}
@@ -281,10 +281,10 @@ WRITE8_MEMBER(divebomb_state::rozcpu_comm_w)
void divebomb_state::update_irqs()
{
- if (has_fromsprite || has_fromroz)
- m_fgcpu->set_input_line(INPUT_LINE_IRQ0, ASSERT_LINE);
- else
- m_fgcpu->set_input_line(INPUT_LINE_IRQ0, CLEAR_LINE);
+ if (has_fromsprite || has_fromroz)
+ m_fgcpu->set_input_line(INPUT_LINE_IRQ0, ASSERT_LINE);
+ else
+ m_fgcpu->set_input_line(INPUT_LINE_IRQ0, CLEAR_LINE);
}
@@ -328,9 +328,9 @@ static INPUT_PORTS_START( divebomb )
PORT_DIPSETTING( 0x02, "5" )
PORT_DIPSETTING( 0x01, "7" )
PORT_DIPSETTING( 0x00, "9" )
- PORT_DIPNAME( 0x04, 0x00, DEF_STR( Cabinet ) ) PORT_DIPLOCATION("SW2:3")
- PORT_DIPSETTING( 0x00, DEF_STR( Upright ) )
- PORT_DIPSETTING( 0x04, DEF_STR( Cocktail ) )
+ PORT_DIPNAME( 0x04, 0x00, DEF_STR( Cabinet ) ) PORT_DIPLOCATION("SW2:3")
+ PORT_DIPSETTING( 0x00, DEF_STR( Upright ) )
+ PORT_DIPSETTING( 0x04, DEF_STR( Cocktail ) )
PORT_DIPNAME( 0x08, 0x00, DEF_STR( Unknown ) ) PORT_DIPLOCATION("SW2:4")
PORT_DIPSETTING( 0x08, DEF_STR( Off ) )
PORT_DIPSETTING( 0x00, DEF_STR( On ) )
@@ -348,24 +348,24 @@ static INPUT_PORTS_START( divebomb )
PORT_DIPSETTING( 0x00, DEF_STR( On ) )
PORT_START("DSW3")
- PORT_DIPUNUSED_DIPLOC( 0x01, 0x01, "SW3:1" )
- PORT_DIPUNUSED_DIPLOC( 0x02, 0x02, "SW3:2" )
- PORT_DIPUNUSED_DIPLOC( 0x04, 0x04, "SW3:3" )
- PORT_DIPUNUSED_DIPLOC( 0x08, 0x08, "SW3:4" )
- PORT_DIPUNUSED_DIPLOC( 0x10, 0x10, "SW3:5" )
- PORT_DIPUNUSED_DIPLOC( 0x20, 0x20, "SW3:6" )
- PORT_DIPUNUSED_DIPLOC( 0x40, 0x40, "SW3:7" )
- PORT_DIPUNUSED_DIPLOC( 0x80, 0x80, "SW3:8" )
-
- PORT_START("DSW4")
- PORT_DIPUNUSED_DIPLOC( 0x01, 0x01, "SW4:1" )
- PORT_DIPUNUSED_DIPLOC( 0x02, 0x02, "SW4:2" )
- PORT_DIPUNUSED_DIPLOC( 0x04, 0x04, "SW4:3" )
- PORT_DIPUNUSED_DIPLOC( 0x08, 0x08, "SW4:4" )
- PORT_DIPUNUSED_DIPLOC( 0x10, 0x10, "SW4:5" )
- PORT_DIPUNUSED_DIPLOC( 0x20, 0x20, "SW4:6" )
- PORT_DIPUNUSED_DIPLOC( 0x40, 0x40, "SW4:7" )
- PORT_DIPUNUSED_DIPLOC( 0x80, 0x80, "SW4:8" )
+ PORT_DIPUNUSED_DIPLOC( 0x01, 0x01, "SW3:1" )
+ PORT_DIPUNUSED_DIPLOC( 0x02, 0x02, "SW3:2" )
+ PORT_DIPUNUSED_DIPLOC( 0x04, 0x04, "SW3:3" )
+ PORT_DIPUNUSED_DIPLOC( 0x08, 0x08, "SW3:4" )
+ PORT_DIPUNUSED_DIPLOC( 0x10, 0x10, "SW3:5" )
+ PORT_DIPUNUSED_DIPLOC( 0x20, 0x20, "SW3:6" )
+ PORT_DIPUNUSED_DIPLOC( 0x40, 0x40, "SW3:7" )
+ PORT_DIPUNUSED_DIPLOC( 0x80, 0x80, "SW3:8" )
+
+ PORT_START("DSW4")
+ PORT_DIPUNUSED_DIPLOC( 0x01, 0x01, "SW4:1" )
+ PORT_DIPUNUSED_DIPLOC( 0x02, 0x02, "SW4:2" )
+ PORT_DIPUNUSED_DIPLOC( 0x04, 0x04, "SW4:3" )
+ PORT_DIPUNUSED_DIPLOC( 0x08, 0x08, "SW4:4" )
+ PORT_DIPUNUSED_DIPLOC( 0x10, 0x10, "SW4:5" )
+ PORT_DIPUNUSED_DIPLOC( 0x20, 0x20, "SW4:6" )
+ PORT_DIPUNUSED_DIPLOC( 0x40, 0x40, "SW4:7" )
+ PORT_DIPUNUSED_DIPLOC( 0x80, 0x80, "SW4:8" )
PORT_START("IN0")
PORT_BIT( 0x01, IP_ACTIVE_LOW, IPT_JOYSTICK_UP ) PORT_8WAY
@@ -388,14 +388,14 @@ static INPUT_PORTS_START( divebomb )
PORT_BIT( 0x80, IP_ACTIVE_LOW, IPT_BUTTON3 ) PORT_PLAYER(2)
PORT_START("SYSTEM")
- PORT_BIT( 0x01, IP_ACTIVE_LOW, IPT_UNKNOWN )
- PORT_BIT( 0x02, IP_ACTIVE_LOW, IPT_UNKNOWN )
- PORT_BIT( 0x04, IP_ACTIVE_LOW, IPT_UNKNOWN )
+ PORT_BIT( 0x01, IP_ACTIVE_LOW, IPT_UNKNOWN )
+ PORT_BIT( 0x02, IP_ACTIVE_LOW, IPT_UNKNOWN )
+ PORT_BIT( 0x04, IP_ACTIVE_LOW, IPT_UNKNOWN )
PORT_BIT( 0x08, IP_ACTIVE_LOW, IPT_COIN1 )
- PORT_BIT( 0x10, IP_ACTIVE_LOW, IPT_UNKNOWN )
- PORT_BIT( 0x20, IP_ACTIVE_LOW, IPT_UNKNOWN )
- PORT_BIT( 0x40, IP_ACTIVE_LOW, IPT_UNKNOWN )
- PORT_BIT( 0x80, IP_ACTIVE_LOW, IPT_UNKNOWN )
+ PORT_BIT( 0x10, IP_ACTIVE_LOW, IPT_UNKNOWN )
+ PORT_BIT( 0x20, IP_ACTIVE_LOW, IPT_UNKNOWN )
+ PORT_BIT( 0x40, IP_ACTIVE_LOW, IPT_UNKNOWN )
+ PORT_BIT( 0x80, IP_ACTIVE_LOW, IPT_UNKNOWN )
INPUT_PORTS_END
@@ -476,10 +476,10 @@ static MACHINE_CONFIG_START( divebomb, divebomb_state )
MCFG_K051316_OFFSETS(-88, -16)
MCFG_K051316_CB(divebomb_state, zoom_callback_2)
- MCFG_MACHINE_START_OVERRIDE(divebomb_state, divebomb)
- MCFG_MACHINE_RESET_OVERRIDE(divebomb_state, divebomb)
+ MCFG_MACHINE_START_OVERRIDE(divebomb_state, divebomb)
+ MCFG_MACHINE_RESET_OVERRIDE(divebomb_state, divebomb)
- MCFG_VIDEO_START_OVERRIDE(divebomb_state, divebomb)
+ MCFG_VIDEO_START_OVERRIDE(divebomb_state, divebomb)
/* video hardware */
MCFG_SCREEN_ADD("screen", RASTER)
@@ -498,7 +498,7 @@ static MACHINE_CONFIG_START( divebomb, divebomb_state )
/* sound hardware */
MCFG_SPEAKER_STANDARD_MONO("mono")
- // All frequencies unverified
+ // All frequencies unverified
MCFG_SOUND_ADD("sn0", SN76489, XTAL1/8)
MCFG_SOUND_ROUTE(ALL_OUTPUTS, "mono", 0.15)
MCFG_SOUND_ADD("sn1", SN76489, XTAL1/8)
@@ -524,7 +524,7 @@ MACHINE_CONFIG_END
ROM_START( divebomb )
ROM_REGION( 0x08000, "fgcpu", 0 )
ROM_LOAD( "U20.27256", 0x00000, 0x08000, CRC(89a30c82) SHA1(ecb3dcc00192b9646dab55ec6c102ab1d2e403e8) )
-
+
ROM_REGION( 0x08000, "spritecpu", 0 )
ROM_LOAD( "U21.27256", 0x00000, 0x08000, CRC(3896d3f6) SHA1(86d10c907bf00977656d8fa426b2f1ac211acdb3) )
@@ -565,17 +565,17 @@ ROM_START( divebomb )
ROM_LOAD( "u36.MB7122.bin", 0x400, 0x400, CRC(0c1ecdb5) SHA1(4ba9e283c747d6a760fe2e0a8b2bfdfcc55a3969) )
ROM_LOAD( "u37.MB7122.bin", 0x000, 0x400, CRC(55c17465) SHA1(153e99a09604467ddd8c641d60c5f1b8d9a205b4) )
- ROM_REGION( 0xc00, "k051316_1_pr", 0 ) // front roz ( k051316_1 )
- // looks like banks 0,1,2 are valid
- ROM_LOAD( "u29.MB7122.bin", 0x000, 0x400, CRC(8b3d60d2) SHA1(a9ac4d3dd5e72522717dd18c32d3f88b75bb077c) ) // the last 0x100 block is invalid (copy of data in u33)
- ROM_LOAD( "u30.MB7122.bin", 0x400, 0x400, CRC(0aeb1a88) SHA1(7b00e85ced210a5f7dfc100c15baa9e1735c7c80) ) // the last 0x100 block is empty
- ROM_LOAD( "u31.MB7122.bin", 0x800, 0x400, CRC(75cf5f3d) SHA1(ec02b99ab65e561596b773918569b28313f21835) ) // the last 0x100 block is invalid (copy of data in u33)
+ ROM_REGION( 0xc00, "k051316_1_pr", 0 ) // front roz ( k051316_1 )
+ // looks like banks 0,1,2 are valid
+ ROM_LOAD( "u29.MB7122.bin", 0x000, 0x400, CRC(8b3d60d2) SHA1(a9ac4d3dd5e72522717dd18c32d3f88b75bb077c) ) // the last 0x100 block is invalid (copy of data in u33)
+ ROM_LOAD( "u30.MB7122.bin", 0x400, 0x400, CRC(0aeb1a88) SHA1(7b00e85ced210a5f7dfc100c15baa9e1735c7c80) ) // the last 0x100 block is empty
+ ROM_LOAD( "u31.MB7122.bin", 0x800, 0x400, CRC(75cf5f3d) SHA1(ec02b99ab65e561596b773918569b28313f21835) ) // the last 0x100 block is invalid (copy of data in u33)
ROM_REGION( 0xc00, "k051316_2_pr", 0 ) // back roz ( k051316_2 )
// 4 valid palettes but our code is only using 1
- ROM_LOAD( "u34.MB7122.bin", 0x000, 0x400, CRC(e0e2d93b) SHA1(9043929520abde15727e9333c153cf97104c9003) )
- ROM_LOAD( "u33.MB7122.bin", 0x400, 0x400, CRC(4df75f4f) SHA1(0157d6e268cdd797622c712648eb2e88214b12d9) )
- ROM_LOAD( "u32.MB7122.bin", 0x800, 0x400, CRC(e2e4b443) SHA1(e97a4e2988e29f992c5dec6f817a783b14535742) )
+ ROM_LOAD( "u34.MB7122.bin", 0x000, 0x400, CRC(e0e2d93b) SHA1(9043929520abde15727e9333c153cf97104c9003) )
+ ROM_LOAD( "u33.MB7122.bin", 0x400, 0x400, CRC(4df75f4f) SHA1(0157d6e268cdd797622c712648eb2e88214b12d9) )
+ ROM_LOAD( "u32.MB7122.bin", 0x800, 0x400, CRC(e2e4b443) SHA1(e97a4e2988e29f992c5dec6f817a783b14535742) )
ROM_REGION( 0x300, "spr_proms", 0 ) // sprite layer palette
ROM_LOAD( "u83.MB7114.bin", 0x000, 0x100, CRC(d216110d) SHA1(3de935dbf876f82864b8b69049c8681101619411) )
@@ -593,30 +593,30 @@ ROM_END
MACHINE_START_MEMBER(divebomb_state, divebomb)
{
- m_bank1->configure_entries(0, 16, memregion("rozcpudata")->base(), 0x4000);
-
- save_item(NAME(roz1_enable));
- save_item(NAME(roz2_enable));
- save_item(NAME(roz1_wrap));
- save_item(NAME(roz2_wrap));
- save_item(NAME(to_spritecpu));
- save_item(NAME(to_rozcpu));
- save_item(NAME(has_fromsprite));
- save_item(NAME(has_fromroz));
- save_item(NAME(from_sprite));
- save_item(NAME(from_roz));
- save_item(NAME(roz_pal));
+ m_bank1->configure_entries(0, 16, memregion("rozcpudata")->base(), 0x4000);
+
+ save_item(NAME(roz1_enable));
+ save_item(NAME(roz2_enable));
+ save_item(NAME(roz1_wrap));
+ save_item(NAME(roz2_wrap));
+ save_item(NAME(to_spritecpu));
+ save_item(NAME(to_rozcpu));
+ save_item(NAME(has_fromsprite));
+ save_item(NAME(has_fromroz));
+ save_item(NAME(from_sprite));
+ save_item(NAME(from_roz));
+ save_item(NAME(roz_pal));
}
MACHINE_RESET_MEMBER(divebomb_state, divebomb)
{
- roz1_enable = false;
- roz2_enable = false;
- roz1_wrap = false;
- roz2_wrap = false;
- has_fromsprite = false;
- has_fromroz = false;
+ roz1_enable = false;
+ roz2_enable = false;
+ roz1_wrap = false;
+ roz2_wrap = false;
+ has_fromsprite = false;
+ has_fromroz = false;
}
diff --git a/src/mame/drivers/dlair.cpp b/src/mame/drivers/dlair.cpp
index c9932c76271..7b6328cc855 100644
--- a/src/mame/drivers/dlair.cpp
+++ b/src/mame/drivers/dlair.cpp
@@ -473,7 +473,7 @@ Address in ROM:
*
*************************************/
- // TODO: DIPs still needs work
+ // TODO: DIPs still needs work
static INPUT_PORTS_START( dlair )
PORT_START("DSW1")
PORT_DIPNAME( 0x01, 0x00, DEF_STR( Coinage ) ) PORT_DIPLOCATION("A:1")
@@ -500,7 +500,7 @@ static INPUT_PORTS_START( dlair )
PORT_START("DSW2")
PORT_DIPNAME( 0x01, 0x01, "Sound every 8 attracts" ) PORT_DIPLOCATION("B:1")
PORT_DIPSETTING( 0x00, DEF_STR( Off ) )
- PORT_DIPSETTING( 0x01, DEF_STR( On ) )
+ PORT_DIPSETTING( 0x01, DEF_STR( On ) )
PORT_DIPNAME( 0x02, 0x00, DEF_STR( Demo_Sounds ) ) PORT_DIPLOCATION("B:2")
PORT_DIPSETTING( 0x02, DEF_STR( Off ) )
PORT_DIPSETTING( 0x00, DEF_STR( On ) )
@@ -652,7 +652,7 @@ static INPUT_PORTS_START( spaceace )
PORT_DIPSETTING( 0x20, "1 out of eight times" )
PORT_DIPUNUSED_DIPLOC( 0x40, IP_ACTIVE_HIGH, "A:7")
PORT_DIPUNUSED_DIPLOC( 0x80, IP_ACTIVE_HIGH, "A:8")
-
+
PORT_MODIFY("DSW2")
PORT_DIPNAME( 0x01, 0x01, "LD Player" ) PORT_DIPLOCATION("B:1")
PORT_DIPSETTING( 0x00, "LD-PR7820" )
@@ -663,7 +663,7 @@ static INPUT_PORTS_START( spaceace )
PORT_DIPNAME( 0x10, 0x00, DEF_STR( Free_Play ) ) PORT_DIPLOCATION("B:5")
PORT_DIPSETTING( 0x00, DEF_STR( No ) )
PORT_DIPSETTING( 0x10, DEF_STR( Yes ) )
- PORT_DIPNAME( 0x20, 0x00, "Unlimited Lives" ) PORT_DIPLOCATION("B:6")
+ PORT_DIPNAME( 0x20, 0x00, "Unlimited Lives" ) PORT_DIPLOCATION("B:6")
PORT_DIPSETTING( 0x00, DEF_STR( No ) )
PORT_DIPSETTING( 0x20, DEF_STR( Yes ) )
PORT_DIPNAME( 0x40, 0x00, "Enable Frame Display" ) PORT_DIPLOCATION("B:7") // ?
diff --git a/src/mame/drivers/esh.cpp b/src/mame/drivers/esh.cpp
index 65940aae7fa..f31fda60211 100644
--- a/src/mame/drivers/esh.cpp
+++ b/src/mame/drivers/esh.cpp
@@ -15,9 +15,9 @@ Notes:
Todo:
- LD TROUBLE appears at POST. Sync/timing issue?
- - Performance spike after some time of gameplay, CPU comms gets corrupt?
- - How to init NVRAM? Current defaults definitely aren't.
- - Wrong overlay colors;
+ - Performance spike after some time of gameplay, CPU comms gets corrupt?
+ - How to init NVRAM? Current defaults definitely aren't.
+ - Wrong overlay colors;
- Convert to tilemaps (see next ToDo for feasibility).
- Rumor has it there's an analog beep hanging off 0xf5? Implement it and finish off 0xf5 bits.
- NVRAM range 0xe000-0xe800 might be too large. It doesn't seem to write past 0xe600...
@@ -85,7 +85,7 @@ UINT32 esh_state::screen_update_esh(screen_device &screen, bitmap_rgb32 &bitmap,
/* clear */
bitmap.fill(0, cliprect);
-
+
/* Draw tiles */
for (charx = 0; charx < 32; charx++)
{
@@ -98,26 +98,26 @@ UINT32 esh_state::screen_update_esh(screen_device &screen, bitmap_rgb32 &bitmap,
bool blinkLine = bool((m_tile_control_ram[current_screen_character] & 0x40) >> 6);
bool blinkChar = bool((m_tile_control_ram[current_screen_character] & 0x80) >> 7);
-
+
// TODO: blink timing
if(blinkChar == true && m_screen->frame_number() & 8)
{
if(trans_mask == 0)
continue;
-
+
for(int yi=0;yi<8;yi++)
for(int xi=0;xi<8;xi++)
bitmap.pix32(yi+chary*8, xi+charx*8) = m_palette->pen(palIndex * 8 + pal_bank * 0x100);
continue;
}
-
+
if(blinkLine == true && m_screen->frame_number() & 8)
gfx = m_gfxdecode->gfx(1);
else
gfx = m_gfxdecode->gfx(0);
-
-
+
+
gfx->transpen(bitmap,cliprect,
m_tile_ram[current_screen_character] + (0x100 * tileOffs),
palIndex + pal_bank,
@@ -193,9 +193,9 @@ WRITE8_MEMBER(esh_state::nmi_line_w)
// 0 -> 1 transition enables this, else disabled?
m_nmi_enable = (data & 1) == 1;
//if (data == 0x00)
- // m_maincpu->set_input_line(INPUT_LINE_NMI, ASSERT_LINE);
+ // m_maincpu->set_input_line(INPUT_LINE_NMI, ASSERT_LINE);
//if (data == 0x01)
- // m_maincpu->set_input_line(INPUT_LINE_NMI, CLEAR_LINE);
+ // m_maincpu->set_input_line(INPUT_LINE_NMI, CLEAR_LINE);
if (data & 0xfe)
logerror("NMI line unknown bit set %02x\n",data);
@@ -305,7 +305,7 @@ PALETTE_INIT_MEMBER(esh_state, esh)
bit2 = (color_prom[i+0x100] >> 6) & 0x01;
b = 0x21 * bit0 + 0x47 * bit1 + 0x97 * bit2;
}
-
+
palette.set_pen_color(i,rgb_t(r,g,b));
}
@@ -333,7 +333,7 @@ INTERRUPT_GEN_MEMBER(esh_state::vblank_callback_esh)
device.execute().set_input_line(0, HOLD_LINE);
}
-// TODO: 0xfe NMI enabled after writing to LD command port, NMI reads LD port.
+// TODO: 0xfe NMI enabled after writing to LD command port, NMI reads LD port.
WRITE_LINE_MEMBER(esh_state::ld_command_strobe_cb)
{
if(m_nmi_enable)
@@ -352,7 +352,7 @@ static MACHINE_CONFIG_START( esh, esh_state )
MCFG_CPU_PROGRAM_MAP(z80_0_mem)
MCFG_CPU_IO_MAP(z80_0_io)
MCFG_CPU_VBLANK_INT_DRIVER("screen", esh_state, vblank_callback_esh)
-
+
MCFG_NVRAM_ADD_0FILL("nvram")
MCFG_LASERDISC_LDV1000_ADD("laserdisc")
@@ -380,8 +380,7 @@ MACHINE_CONFIG_END
#define ROM_INTERLACED_GFX \
ROM_REGION( 0x3000, "gfx2", 0 ) \
ROM_COPY( "gfx1", 0, 0, 0x3000 ) \
- ROMX_FILL( 0, 0x3000, 0x00, ROM_SKIP(1) ) \
-
+ ROMX_FILL( 0, 0x3000, 0x00, ROM_SKIP(1) )
ROM_START( esh )
/* Main program CPU */
ROM_REGION( 0x4000, "maincpu", 0 )
diff --git a/src/mame/drivers/fccpu30.cpp b/src/mame/drivers/fccpu30.cpp
index 2be0284abe7..d20e24390b8 100644
--- a/src/mame/drivers/fccpu30.cpp
+++ b/src/mame/drivers/fccpu30.cpp
@@ -7,10 +7,10 @@
* 21/05/2016
*
* Thanks to Al Kossow his site http://www.bitsavers.org/ I got the information
- * required to start the work with this driver.
+ * required to start the work with this driver.
*
- * The driver is currently starting up and the Boot ROM asks for input do start FGA-002
- * diagnostics and do SRAM setup, which it does. After that it jumps to zeroed memory
+ * The driver is currently starting up and the Boot ROM asks for input do start FGA-002
+ * diagnostics and do SRAM setup, which it does. After that it jumps to zeroed memory
* and crashes so needs some more work to be useful
*
*
@@ -102,7 +102,7 @@
* Range Decscription
* --------------------------------------------------------------------------
* 00000000-0xxFFFFF Shared DRAM D8-D32 xx=0x1F-0x03 for 32Mb-4Mb
- * 0yy00000-FAFFFFFF VME A32 D8-D32 yy=xx+1
+ * 0yy00000-FAFFFFFF VME A32 D8-D32 yy=xx+1
* FB000000-FBFEFFFF VME A24 D8-D32
* FBFF0000-FBFFFFFF VME A16 D8-D32
* FC000000-FCFEFFFF VME A24 D8-D16
@@ -219,11 +219,11 @@ private:
required_device<pit68230_device> m_pit2;
// Pointer to System ROMs needed by bootvect_r and masking RAM buffer for post reset accesses
- UINT32 *m_sysrom;
- UINT32 m_sysram[2];
+ UINT32 *m_sysrom;
+ UINT32 m_sysram[2];
- // FGA-002
- UINT8 m_fga002[0x500];
+ // FGA-002
+ UINT8 m_fga002[0x500];
};
static ADDRESS_MAP_START (fccpu30_mem, AS_PROGRAM, 32, fccpu30_state)
@@ -239,8 +239,8 @@ static ADDRESS_MAP_START (fccpu30_mem, AS_PROGRAM, 32, fccpu30_state)
AM_RANGE (0xffd00000, 0xffd004ff) AM_READWRITE8(fga8_r, fga8_w, 0xffffffff) /* FGA-002 Force Gate Array */
AM_RANGE (0xffe00000, 0xffefffff) AM_ROM AM_REGION("maincpu", 0xffe00000)
- //AM_RANGE(0x100000, 0xfeffff) AM_READWRITE(vme_a24_r, vme_a24_w) /* VMEbus Rev B addresses (24 bits) - not verified */
- //AM_RANGE(0xff0000, 0xffffff) AM_READWRITE(vme_a16_r, vme_a16_w) /* VMEbus Rev B addresses (16 bits) - not verified */
+ //AM_RANGE(0x100000, 0xfeffff) AM_READWRITE(vme_a24_r, vme_a24_w) /* VMEbus Rev B addresses (24 bits) - not verified */
+ //AM_RANGE(0xff0000, 0xffffff) AM_READWRITE(vme_a16_r, vme_a16_w) /* VMEbus Rev B addresses (16 bits) - not verified */
ADDRESS_MAP_END
/* Input ports */
@@ -362,23 +362,23 @@ void fccpu30_state::machine_reset ()
if (m_sysrom == &m_sysram[0]) /* Condition needed because memory map is not setup first time */
m_sysrom = (UINT32*)(memregion ("maincpu")->base () + 0xffe00000);
- /* Reset values for the FGA-002 */
+ /* Reset values for the FGA-002 */
memset(&m_fga002[0], 0, sizeof(m_fga002));
- m_fga002[FGA_RSVMECALL] = 0x80;
- m_fga002[FGA_RSKEYRES] = 0x80;
- m_fga002[FGA_RSCPUCALL] = 0x80;
- m_fga002[FGA_RSLOCSW] = 0x80;
- m_fga002[FGA_ISTIM0] = 0x80;
- m_fga002[FGA_ISDMANORM] = 0x80;
- m_fga002[FGA_ISDMAERR] = 0x80;
- m_fga002[FGA_ISFMB0REF] = 0x80;
- m_fga002[FGA_ISFMB1REF] = 0x80;
- m_fga002[FGA_ISPARITY] = 0x80;
- m_fga002[FGA_ISABORT] = 0x80;
- m_fga002[FGA_ISACFAIL] = 0x80;
- m_fga002[FGA_ISSYSFAIL] = 0x80;
- m_fga002[FGA_ISFMB0MES] = 0x80;
- m_fga002[FGA_ISFMB1MES] = 0x80;
+ m_fga002[FGA_RSVMECALL] = 0x80;
+ m_fga002[FGA_RSKEYRES] = 0x80;
+ m_fga002[FGA_RSCPUCALL] = 0x80;
+ m_fga002[FGA_RSLOCSW] = 0x80;
+ m_fga002[FGA_ISTIM0] = 0x80;
+ m_fga002[FGA_ISDMANORM] = 0x80;
+ m_fga002[FGA_ISDMAERR] = 0x80;
+ m_fga002[FGA_ISFMB0REF] = 0x80;
+ m_fga002[FGA_ISFMB1REF] = 0x80;
+ m_fga002[FGA_ISPARITY] = 0x80;
+ m_fga002[FGA_ISABORT] = 0x80;
+ m_fga002[FGA_ISACFAIL] = 0x80;
+ m_fga002[FGA_ISSYSFAIL] = 0x80;
+ m_fga002[FGA_ISFMB0MES] = 0x80;
+ m_fga002[FGA_ISFMB1MES] = 0x80;
}
/* Boot vector handler, the PCB hardwires the first 8 bytes from 0xff800000 to 0x0 at reset*/
@@ -395,12 +395,12 @@ WRITE32_MEMBER (fccpu30_state::bootvect_w){
/*
* FGA-002 driver, might deserve its own driver but will rest here until another board wants it
*
-The FGA-002 gate array is a high speed CMOS device manufactured in 1.2 micron technology and
-containing 24,000 gates in a 281 pin PGA package. It provides interfaces to the 68020/30 microprocessor
+The FGA-002 gate array is a high speed CMOS device manufactured in 1.2 micron technology and
+containing 24,000 gates in a 281 pin PGA package. It provides interfaces to the 68020/30 microprocessor
as well as a VMEbus compatible interface. The auxilary interface of the gate array is a high speed data
-channel used by the internal 32 bit DMA controller. The interface allows data transfer rates of up to
-6 MByte/second. The timing of the local I/O interface is programmable and provides easy interfacing of
-local I/O devices. All control, address and data lines of the CPU and the VMEbus are either directly
+channel used by the internal 32 bit DMA controller. The interface allows data transfer rates of up to
+6 MByte/second. The timing of the local I/O interface is programmable and provides easy interfacing of
+local I/O devices. All control, address and data lines of the CPU and the VMEbus are either directly
connected or connected via buffers to the gate array allowing easy implementation and usage.
The gate array registers are programmed by the local CPU.
@@ -413,210 +413,209 @@ FEATURES:
- 8 bit TIMER with 16 selectable internal source clocks
*/
WRITE8_MEMBER (fccpu30_state::fga8_w){
- LOG(("%s[%04x] <- %02x - ", FUNCNAME, offset, data));
+ LOG(("%s[%04x] <- %02x - ", FUNCNAME, offset, data));
switch(offset)
{
- case FGA_SPECIALENA : LOG(("FGA_SPECIALENA - not implemented\n")); m_fga002[FGA_SPECIALENA] = data; break;
- case FGA_RSVMECALL : LOG(("FGA_RSVMECALL - not implemented\n")); m_fga002[FGA_RSVMECALL] = data; break;
- case FGA_RSKEYRES : LOG(("FGA_RSKEYRES - not implemented\n")); m_fga002[FGA_RSKEYRES] = data; break;
- case FGA_RSCPUCALL : LOG(("FGA_RSCPUCALL - not implemented\n")); m_fga002[FGA_RSCPUCALL] = data; break;
- case FGA_RSLOCSW : LOG(("FGA_RSLOCSW - not implemented\n")); m_fga002[FGA_RSLOCSW] = data; break;
- case FGA_ICRMBOX0 : LOG(("FGA_ICRMBOX0 - not implemented\n")); m_fga002[FGA_ICRMBOX0] = data; break;
- case FGA_ICRMBOX1 : LOG(("FGA_ICRMBOX1 - not implemented\n")); m_fga002[FGA_ICRMBOX1] = data; break;
- case FGA_ICRMBOX2 : LOG(("FGA_ICRMBOX2 - not implemented\n")); m_fga002[FGA_ICRMBOX2] = data; break;
- case FGA_ICRMBOX3 : LOG(("FGA_ICRMBOX3 - not implemented\n")); m_fga002[FGA_ICRMBOX3] = data; break;
- case FGA_ICRMBOX4 : LOG(("FGA_ICRMBOX4 - not implemented\n")); m_fga002[FGA_ICRMBOX4] = data; break;
- case FGA_ICRMBOX5 : LOG(("FGA_ICRMBOX5 - not implemented\n")); m_fga002[FGA_ICRMBOX5] = data; break;
- case FGA_ICRMBOX6 : LOG(("FGA_ICRMBOX6 - not implemented\n")); m_fga002[FGA_ICRMBOX6] = data; break;
- case FGA_ICRMBOX7 : LOG(("FGA_ICRMBOX7 - not implemented\n")); m_fga002[FGA_ICRMBOX7] = data; break;
- case FGA_VMEPAGE : LOG(("FGA_VMEPAGE - not implemented\n")); m_fga002[FGA_VMEPAGE ] = data; break;
- case FGA_ICRVME1 : LOG(("FGA_ICRVME1 - not implemented\n")); m_fga002[FGA_ICRVME1] = data; break;
- case FGA_ICRVME2 : LOG(("FGA_ICRVME2 - not implemented\n")); m_fga002[FGA_ICRVME2] = data; break;
- case FGA_ICRVME3 : LOG(("FGA_ICRVME3 - not implemented\n")); m_fga002[FGA_ICRVME3] = data; break;
- case FGA_ICRVME4 : LOG(("FGA_ICRVME4 - not implemented\n")); m_fga002[FGA_ICRVME4] = data; break;
- case FGA_ICRVME5 : LOG(("FGA_ICRVME5 - not implemented\n")); m_fga002[FGA_ICRVME5] = data; break;
- case FGA_ICRVME6 : LOG(("FGA_ICRVME6 - not implemented\n")); m_fga002[FGA_ICRVME6] = data; break;
- case FGA_ICRVME7 : LOG(("FGA_ICRVME7 - not implemented\n")); m_fga002[FGA_ICRVME7] = data; break;
- case FGA_ICRTIM0 : LOG(("FGA_ICRTIM0 - not implemented\n")); m_fga002[FGA_ICRTIM0] = data; break;
- case FGA_ICRDMANORM : LOG(("FGA_ICRDMANORM - not implemented\n")); m_fga002[FGA_ICRDMANORM] = data; break;
- case FGA_ICRDMAERR : LOG(("FGA_ICRDMAERR - not implemented\n")); m_fga002[FGA_ICRDMAERR] = data; break;
- case FGA_CTL1 : LOG(("FGA_CTL1 - not implemented\n")); m_fga002[FGA_CTL1] = data; break;
- case FGA_CTL2 : LOG(("FGA_CTL2 - not implemented\n")); m_fga002[FGA_CTL2] = data; break;
- case FGA_ICRFMB0REF : LOG(("FGA_ICRFMB0REF - not implemented\n")); m_fga002[FGA_ICRFMB0REF] = data; break;
- case FGA_ICRFMB1REF : LOG(("FGA_ICRFMB1REF - not implemented\n")); m_fga002[FGA_ICRFMB1REF] = data; break;
- case FGA_ICRFMB0MES : LOG(("FGA_ICRFMB0MES - not implemented\n")); m_fga002[FGA_ICRFMB0MES] = data; break;
- case FGA_ICRFMB1MES : LOG(("FGA_ICRFMB1MES - not implemented\n")); m_fga002[FGA_ICRFMB1MES] = data; break;
- case FGA_CTL3 : LOG(("FGA_CTL3 - not implemented\n")); m_fga002[FGA_CTL3] = data; break;
- case FGA_CTL4 : LOG(("FGA_CTL4 - not implemented\n")); m_fga002[FGA_CTL4] = data; break;
- case FGA_ICRPARITY : LOG(("FGA_ICRPARITY - not implemented\n")); m_fga002[FGA_ICRPARITY] = data; break;
- case FGA_AUXPINCTL : LOG(("FGA_AUXPINCTL - not implemented\n")); m_fga002[FGA_AUXPINCTL] = data; break;
- case FGA_CTL5 : LOG(("FGA_CTL5 - not implemented\n")); m_fga002[FGA_CTL5] = data; break;
- case FGA_AUXFIFWEX : LOG(("FGA_AUXFIFWEX - not implemented\n")); m_fga002[FGA_AUXFIFWEX] = data; break;
- case FGA_AUXFIFREX : LOG(("FGA_AUXFIFREX - not implemented\n")); m_fga002[FGA_AUXFIFREX] = data; break;
- case FGA_CTL6 : LOG(("FGA_CTL6 - not implemented\n")); m_fga002[FGA_CTL6] = data; break;
- case FGA_CTL7 : LOG(("FGA_CTL7 - not implemented\n")); m_fga002[FGA_CTL7] = data; break;
- case FGA_CTL8 : LOG(("FGA_CTL8 - not implemented\n")); m_fga002[FGA_CTL8] = data; break;
- case FGA_CTL9 : LOG(("FGA_CTL9 - not implemented\n")); m_fga002[FGA_CTL9] = data; break;
- case FGA_ICRABORT : LOG(("FGA_ICRABORT - not implemented\n")); m_fga002[FGA_ICRABORT] = data; break;
- case FGA_ICRACFAIL : LOG(("FGA_ICRACFAIL - not implemented\n")); m_fga002[FGA_ICRACFAIL] = data; break;
- case FGA_ICRSYSFAIL : LOG(("FGA_ICRSYSFAIL - not implemented\n")); m_fga002[FGA_ICRSYSFAIL] = data; break;
- case FGA_ICRLOCAL0 : LOG(("FGA_ICRLOCAL0 - not implemented\n")); m_fga002[FGA_ICRLOCAL0] = data; break;
- case FGA_ICRLOCAL1 : LOG(("FGA_ICRLOCAL1 - not implemented\n")); m_fga002[FGA_ICRLOCAL1] = data; break;
- case FGA_ICRLOCAL2 : LOG(("FGA_ICRLOCAL2 - not implemented\n")); m_fga002[FGA_ICRLOCAL2] = data; break;
- case FGA_ICRLOCAL3 : LOG(("FGA_ICRLOCAL3 - not implemented\n")); m_fga002[FGA_ICRLOCAL3] = data; break;
- case FGA_ICRLOCAL4 : LOG(("FGA_ICRLOCAL4 - not implemented\n")); m_fga002[FGA_ICRLOCAL4] = data; break;
- case FGA_ICRLOCAL5 : LOG(("FGA_ICRLOCAL5 - not implemented\n")); m_fga002[FGA_ICRLOCAL5] = data; break;
- case FGA_ICRLOCAL6 : LOG(("FGA_ICRLOCAL6 - not implemented\n")); m_fga002[FGA_ICRLOCAL6] = data; break;
- case FGA_ICRLOCAL7 : LOG(("FGA_ICRLOCAL7 - not implemented\n")); m_fga002[FGA_ICRLOCAL7] = data; break;
- case FGA_ENAMCODE : LOG(("FGA_ENAMCODE - not implemented\n")); m_fga002[FGA_ENAMCODE] = data; break;
- case FGA_CTL10 : LOG(("FGA_CTL10 - not implemented\n")); m_fga002[FGA_CTL10] = data; break;
- case FGA_CTL11 : LOG(("FGA_CTL11 - not implemented\n")); m_fga002[FGA_CTL11] = data; break;
- case FGA_MAINUM : LOG(("FGA_MAINUM - not implemented\n")); m_fga002[FGA_MAINUM] = data; break;
- case FGA_MAINUU : LOG(("FGA_MAINUU - not implemented\n")); m_fga002[FGA_MAINUU] = data; break;
- case FGA_BOTTOMPAGEU : LOG(("FGA_BOTTOMPAGEU - not implemented\n")); m_fga002[FGA_BOTTOMPAGEU] = data; break;
- case FGA_BOTTOMPAGEL : LOG(("FGA_BOTTOMPAGEL - not implemented\n")); m_fga002[FGA_BOTTOMPAGEL] = data; break;
- case FGA_TOPPAGEU : LOG(("FGA_TOPPAGEU - not implemented\n")); m_fga002[FGA_TOPPAGEU] = data; break;
- case FGA_TOPPAGEL : LOG(("FGA_TOPPAGEL - not implemented\n")); m_fga002[FGA_TOPPAGEL] = data; break;
- case FGA_MYVMEPAGE : LOG(("FGA_MYVMEPAGE - not implemented\n")); m_fga002[FGA_MYVMEPAGE] = data; break;
- case FGA_TIM0PRELOAD : LOG(("FGA_TIM0PRELOAD - not implemented\n")); m_fga002[FGA_TIM0PRELOAD] = data; break;
- case FGA_TIM0CTL : LOG(("FGA_TIM0CTL - not implemented\n")); m_fga002[FGA_TIM0CTL] = data; break;
- case FGA_DMASRCATT : LOG(("FGA_DMASRCATT - not implemented\n")); m_fga002[FGA_DMASRCATT] = data; break;
- case FGA_DMADSTATT : LOG(("FGA_DMADSTATT - not implemented\n")); m_fga002[FGA_DMADSTATT] = data; break;
- case FGA_DMA_GENERAL : LOG(("FGA_DMA_GENERAL - not implemented\n")); m_fga002[FGA_DMA_GENERAL] = data; break;
- case FGA_CTL12 : LOG(("FGA_CTL12 - not implemented\n")); m_fga002[FGA_CTL12] = data; break;
- case FGA_LIOTIMING : LOG(("FGA_LIOTIMING - not implemented\n")); m_fga002[FGA_LIOTIMING] = data; break;
- case FGA_LOCALIACK : LOG(("FGA_LOCALIACK - not implemented\n")); m_fga002[FGA_LOCALIACK] = data; break;
- case FGA_FMBCTL : LOG(("FGA_FMBCTL - not implemented\n")); m_fga002[FGA_FMBCTL] = data; break;
- case FGA_FMBAREA : LOG(("FGA_FMBAREA - not implemented\n")); m_fga002[FGA_FMBAREA] = data; break;
- case FGA_AUXSRCSTART : LOG(("FGA_AUXSRCSTART - not implemented\n")); m_fga002[FGA_AUXSRCSTART] = data; break;
- case FGA_AUXDSTSTART : LOG(("FGA_AUXDSTSTART - not implemented\n")); m_fga002[FGA_AUXDSTSTART] = data; break;
- case FGA_AUXSRCTERM : LOG(("FGA_AUXSRCTERM - not implemented\n")); m_fga002[FGA_AUXSRCTERM] = data; break;
- case FGA_AUXDSTTERM : LOG(("FGA_AUXDSTTERM - not implemented\n")); m_fga002[FGA_AUXDSTTERM] = data; break;
- case FGA_CTL13 : LOG(("FGA_CTL13 - not implemented\n")); m_fga002[FGA_CTL13] = data; break;
- case FGA_CTL14 : LOG(("FGA_CTL14 - not implemented\n")); m_fga002[FGA_CTL14] = data; break;
- case FGA_CTL15 : LOG(("FGA_CTL15 - not implemented\n")); m_fga002[FGA_CTL15] = data; break;
- case FGA_CTL16 : LOG(("FGA_CTL16 - not implemented\n")); m_fga002[FGA_CTL16] = data; break;
- case FGA_ISTIM0 : LOG(("FGA_ISTIM0 - not implemented\n")); m_fga002[FGA_ISTIM0] = data; break;
- case FGA_ISDMANORM : LOG(("FGA_ISDMANORM - not implemented\n")); m_fga002[FGA_ISDMANORM] = data; break;
- case FGA_ISDMAERR : LOG(("FGA_ISDMAERR - not implemented\n")); m_fga002[FGA_ISDMAERR] = data; break;
- case FGA_ISFMB0REF : LOG(("FGA_ISFMB0REF - not implemented\n")); m_fga002[FGA_ISFMB0REF] = data; break;
- case FGA_ISFMB1REF : LOG(("FGA_ISFMB1REF - not implemented\n")); m_fga002[FGA_ISFMB1REF] = data; break;
- case FGA_ISPARITY : LOG(("FGA_ISPARITY - not implemented\n")); m_fga002[FGA_ISPARITY] = data; break;
- case FGA_DMARUNCTL : LOG(("FGA_DMARUNCTL - not implemented\n")); m_fga002[FGA_DMARUNCTL] = data; break;
- case FGA_ISABORT : LOG(("FGA_ISABORT - not implemented\n")); m_fga002[FGA_ISABORT] = data; break;
- case FGA_ISFMB0MES : LOG(("FGA_ISFMB0MES - not implemented\n")); m_fga002[FGA_ISFMB0MES] = data; break;
- case FGA_ISFMB1MES : LOG(("FGA_ISFMB1MES - not implemented\n")); m_fga002[FGA_ISFMB1MES] = data; break;
- case FGA_ABORTPIN : LOG(("FGA_ABORTPIN - not implemented\n")); m_fga002[FGA_ABORTPIN] = data; break;
+ case FGA_SPECIALENA : LOG(("FGA_SPECIALENA - not implemented\n")); m_fga002[FGA_SPECIALENA] = data; break;
+ case FGA_RSVMECALL : LOG(("FGA_RSVMECALL - not implemented\n")); m_fga002[FGA_RSVMECALL] = data; break;
+ case FGA_RSKEYRES : LOG(("FGA_RSKEYRES - not implemented\n")); m_fga002[FGA_RSKEYRES] = data; break;
+ case FGA_RSCPUCALL : LOG(("FGA_RSCPUCALL - not implemented\n")); m_fga002[FGA_RSCPUCALL] = data; break;
+ case FGA_RSLOCSW : LOG(("FGA_RSLOCSW - not implemented\n")); m_fga002[FGA_RSLOCSW] = data; break;
+ case FGA_ICRMBOX0 : LOG(("FGA_ICRMBOX0 - not implemented\n")); m_fga002[FGA_ICRMBOX0] = data; break;
+ case FGA_ICRMBOX1 : LOG(("FGA_ICRMBOX1 - not implemented\n")); m_fga002[FGA_ICRMBOX1] = data; break;
+ case FGA_ICRMBOX2 : LOG(("FGA_ICRMBOX2 - not implemented\n")); m_fga002[FGA_ICRMBOX2] = data; break;
+ case FGA_ICRMBOX3 : LOG(("FGA_ICRMBOX3 - not implemented\n")); m_fga002[FGA_ICRMBOX3] = data; break;
+ case FGA_ICRMBOX4 : LOG(("FGA_ICRMBOX4 - not implemented\n")); m_fga002[FGA_ICRMBOX4] = data; break;
+ case FGA_ICRMBOX5 : LOG(("FGA_ICRMBOX5 - not implemented\n")); m_fga002[FGA_ICRMBOX5] = data; break;
+ case FGA_ICRMBOX6 : LOG(("FGA_ICRMBOX6 - not implemented\n")); m_fga002[FGA_ICRMBOX6] = data; break;
+ case FGA_ICRMBOX7 : LOG(("FGA_ICRMBOX7 - not implemented\n")); m_fga002[FGA_ICRMBOX7] = data; break;
+ case FGA_VMEPAGE : LOG(("FGA_VMEPAGE - not implemented\n")); m_fga002[FGA_VMEPAGE ] = data; break;
+ case FGA_ICRVME1 : LOG(("FGA_ICRVME1 - not implemented\n")); m_fga002[FGA_ICRVME1] = data; break;
+ case FGA_ICRVME2 : LOG(("FGA_ICRVME2 - not implemented\n")); m_fga002[FGA_ICRVME2] = data; break;
+ case FGA_ICRVME3 : LOG(("FGA_ICRVME3 - not implemented\n")); m_fga002[FGA_ICRVME3] = data; break;
+ case FGA_ICRVME4 : LOG(("FGA_ICRVME4 - not implemented\n")); m_fga002[FGA_ICRVME4] = data; break;
+ case FGA_ICRVME5 : LOG(("FGA_ICRVME5 - not implemented\n")); m_fga002[FGA_ICRVME5] = data; break;
+ case FGA_ICRVME6 : LOG(("FGA_ICRVME6 - not implemented\n")); m_fga002[FGA_ICRVME6] = data; break;
+ case FGA_ICRVME7 : LOG(("FGA_ICRVME7 - not implemented\n")); m_fga002[FGA_ICRVME7] = data; break;
+ case FGA_ICRTIM0 : LOG(("FGA_ICRTIM0 - not implemented\n")); m_fga002[FGA_ICRTIM0] = data; break;
+ case FGA_ICRDMANORM : LOG(("FGA_ICRDMANORM - not implemented\n")); m_fga002[FGA_ICRDMANORM] = data; break;
+ case FGA_ICRDMAERR : LOG(("FGA_ICRDMAERR - not implemented\n")); m_fga002[FGA_ICRDMAERR] = data; break;
+ case FGA_CTL1 : LOG(("FGA_CTL1 - not implemented\n")); m_fga002[FGA_CTL1] = data; break;
+ case FGA_CTL2 : LOG(("FGA_CTL2 - not implemented\n")); m_fga002[FGA_CTL2] = data; break;
+ case FGA_ICRFMB0REF : LOG(("FGA_ICRFMB0REF - not implemented\n")); m_fga002[FGA_ICRFMB0REF] = data; break;
+ case FGA_ICRFMB1REF : LOG(("FGA_ICRFMB1REF - not implemented\n")); m_fga002[FGA_ICRFMB1REF] = data; break;
+ case FGA_ICRFMB0MES : LOG(("FGA_ICRFMB0MES - not implemented\n")); m_fga002[FGA_ICRFMB0MES] = data; break;
+ case FGA_ICRFMB1MES : LOG(("FGA_ICRFMB1MES - not implemented\n")); m_fga002[FGA_ICRFMB1MES] = data; break;
+ case FGA_CTL3 : LOG(("FGA_CTL3 - not implemented\n")); m_fga002[FGA_CTL3] = data; break;
+ case FGA_CTL4 : LOG(("FGA_CTL4 - not implemented\n")); m_fga002[FGA_CTL4] = data; break;
+ case FGA_ICRPARITY : LOG(("FGA_ICRPARITY - not implemented\n")); m_fga002[FGA_ICRPARITY] = data; break;
+ case FGA_AUXPINCTL : LOG(("FGA_AUXPINCTL - not implemented\n")); m_fga002[FGA_AUXPINCTL] = data; break;
+ case FGA_CTL5 : LOG(("FGA_CTL5 - not implemented\n")); m_fga002[FGA_CTL5] = data; break;
+ case FGA_AUXFIFWEX : LOG(("FGA_AUXFIFWEX - not implemented\n")); m_fga002[FGA_AUXFIFWEX] = data; break;
+ case FGA_AUXFIFREX : LOG(("FGA_AUXFIFREX - not implemented\n")); m_fga002[FGA_AUXFIFREX] = data; break;
+ case FGA_CTL6 : LOG(("FGA_CTL6 - not implemented\n")); m_fga002[FGA_CTL6] = data; break;
+ case FGA_CTL7 : LOG(("FGA_CTL7 - not implemented\n")); m_fga002[FGA_CTL7] = data; break;
+ case FGA_CTL8 : LOG(("FGA_CTL8 - not implemented\n")); m_fga002[FGA_CTL8] = data; break;
+ case FGA_CTL9 : LOG(("FGA_CTL9 - not implemented\n")); m_fga002[FGA_CTL9] = data; break;
+ case FGA_ICRABORT : LOG(("FGA_ICRABORT - not implemented\n")); m_fga002[FGA_ICRABORT] = data; break;
+ case FGA_ICRACFAIL : LOG(("FGA_ICRACFAIL - not implemented\n")); m_fga002[FGA_ICRACFAIL] = data; break;
+ case FGA_ICRSYSFAIL : LOG(("FGA_ICRSYSFAIL - not implemented\n")); m_fga002[FGA_ICRSYSFAIL] = data; break;
+ case FGA_ICRLOCAL0 : LOG(("FGA_ICRLOCAL0 - not implemented\n")); m_fga002[FGA_ICRLOCAL0] = data; break;
+ case FGA_ICRLOCAL1 : LOG(("FGA_ICRLOCAL1 - not implemented\n")); m_fga002[FGA_ICRLOCAL1] = data; break;
+ case FGA_ICRLOCAL2 : LOG(("FGA_ICRLOCAL2 - not implemented\n")); m_fga002[FGA_ICRLOCAL2] = data; break;
+ case FGA_ICRLOCAL3 : LOG(("FGA_ICRLOCAL3 - not implemented\n")); m_fga002[FGA_ICRLOCAL3] = data; break;
+ case FGA_ICRLOCAL4 : LOG(("FGA_ICRLOCAL4 - not implemented\n")); m_fga002[FGA_ICRLOCAL4] = data; break;
+ case FGA_ICRLOCAL5 : LOG(("FGA_ICRLOCAL5 - not implemented\n")); m_fga002[FGA_ICRLOCAL5] = data; break;
+ case FGA_ICRLOCAL6 : LOG(("FGA_ICRLOCAL6 - not implemented\n")); m_fga002[FGA_ICRLOCAL6] = data; break;
+ case FGA_ICRLOCAL7 : LOG(("FGA_ICRLOCAL7 - not implemented\n")); m_fga002[FGA_ICRLOCAL7] = data; break;
+ case FGA_ENAMCODE : LOG(("FGA_ENAMCODE - not implemented\n")); m_fga002[FGA_ENAMCODE] = data; break;
+ case FGA_CTL10 : LOG(("FGA_CTL10 - not implemented\n")); m_fga002[FGA_CTL10] = data; break;
+ case FGA_CTL11 : LOG(("FGA_CTL11 - not implemented\n")); m_fga002[FGA_CTL11] = data; break;
+ case FGA_MAINUM : LOG(("FGA_MAINUM - not implemented\n")); m_fga002[FGA_MAINUM] = data; break;
+ case FGA_MAINUU : LOG(("FGA_MAINUU - not implemented\n")); m_fga002[FGA_MAINUU] = data; break;
+ case FGA_BOTTOMPAGEU : LOG(("FGA_BOTTOMPAGEU - not implemented\n")); m_fga002[FGA_BOTTOMPAGEU] = data; break;
+ case FGA_BOTTOMPAGEL : LOG(("FGA_BOTTOMPAGEL - not implemented\n")); m_fga002[FGA_BOTTOMPAGEL] = data; break;
+ case FGA_TOPPAGEU : LOG(("FGA_TOPPAGEU - not implemented\n")); m_fga002[FGA_TOPPAGEU] = data; break;
+ case FGA_TOPPAGEL : LOG(("FGA_TOPPAGEL - not implemented\n")); m_fga002[FGA_TOPPAGEL] = data; break;
+ case FGA_MYVMEPAGE : LOG(("FGA_MYVMEPAGE - not implemented\n")); m_fga002[FGA_MYVMEPAGE] = data; break;
+ case FGA_TIM0PRELOAD : LOG(("FGA_TIM0PRELOAD - not implemented\n")); m_fga002[FGA_TIM0PRELOAD] = data; break;
+ case FGA_TIM0CTL : LOG(("FGA_TIM0CTL - not implemented\n")); m_fga002[FGA_TIM0CTL] = data; break;
+ case FGA_DMASRCATT : LOG(("FGA_DMASRCATT - not implemented\n")); m_fga002[FGA_DMASRCATT] = data; break;
+ case FGA_DMADSTATT : LOG(("FGA_DMADSTATT - not implemented\n")); m_fga002[FGA_DMADSTATT] = data; break;
+ case FGA_DMA_GENERAL : LOG(("FGA_DMA_GENERAL - not implemented\n")); m_fga002[FGA_DMA_GENERAL] = data; break;
+ case FGA_CTL12 : LOG(("FGA_CTL12 - not implemented\n")); m_fga002[FGA_CTL12] = data; break;
+ case FGA_LIOTIMING : LOG(("FGA_LIOTIMING - not implemented\n")); m_fga002[FGA_LIOTIMING] = data; break;
+ case FGA_LOCALIACK : LOG(("FGA_LOCALIACK - not implemented\n")); m_fga002[FGA_LOCALIACK] = data; break;
+ case FGA_FMBCTL : LOG(("FGA_FMBCTL - not implemented\n")); m_fga002[FGA_FMBCTL] = data; break;
+ case FGA_FMBAREA : LOG(("FGA_FMBAREA - not implemented\n")); m_fga002[FGA_FMBAREA] = data; break;
+ case FGA_AUXSRCSTART : LOG(("FGA_AUXSRCSTART - not implemented\n")); m_fga002[FGA_AUXSRCSTART] = data; break;
+ case FGA_AUXDSTSTART : LOG(("FGA_AUXDSTSTART - not implemented\n")); m_fga002[FGA_AUXDSTSTART] = data; break;
+ case FGA_AUXSRCTERM : LOG(("FGA_AUXSRCTERM - not implemented\n")); m_fga002[FGA_AUXSRCTERM] = data; break;
+ case FGA_AUXDSTTERM : LOG(("FGA_AUXDSTTERM - not implemented\n")); m_fga002[FGA_AUXDSTTERM] = data; break;
+ case FGA_CTL13 : LOG(("FGA_CTL13 - not implemented\n")); m_fga002[FGA_CTL13] = data; break;
+ case FGA_CTL14 : LOG(("FGA_CTL14 - not implemented\n")); m_fga002[FGA_CTL14] = data; break;
+ case FGA_CTL15 : LOG(("FGA_CTL15 - not implemented\n")); m_fga002[FGA_CTL15] = data; break;
+ case FGA_CTL16 : LOG(("FGA_CTL16 - not implemented\n")); m_fga002[FGA_CTL16] = data; break;
+ case FGA_ISTIM0 : LOG(("FGA_ISTIM0 - not implemented\n")); m_fga002[FGA_ISTIM0] = data; break;
+ case FGA_ISDMANORM : LOG(("FGA_ISDMANORM - not implemented\n")); m_fga002[FGA_ISDMANORM] = data; break;
+ case FGA_ISDMAERR : LOG(("FGA_ISDMAERR - not implemented\n")); m_fga002[FGA_ISDMAERR] = data; break;
+ case FGA_ISFMB0REF : LOG(("FGA_ISFMB0REF - not implemented\n")); m_fga002[FGA_ISFMB0REF] = data; break;
+ case FGA_ISFMB1REF : LOG(("FGA_ISFMB1REF - not implemented\n")); m_fga002[FGA_ISFMB1REF] = data; break;
+ case FGA_ISPARITY : LOG(("FGA_ISPARITY - not implemented\n")); m_fga002[FGA_ISPARITY] = data; break;
+ case FGA_DMARUNCTL : LOG(("FGA_DMARUNCTL - not implemented\n")); m_fga002[FGA_DMARUNCTL] = data; break;
+ case FGA_ISABORT : LOG(("FGA_ISABORT - not implemented\n")); m_fga002[FGA_ISABORT] = data; break;
+ case FGA_ISFMB0MES : LOG(("FGA_ISFMB0MES - not implemented\n")); m_fga002[FGA_ISFMB0MES] = data; break;
+ case FGA_ISFMB1MES : LOG(("FGA_ISFMB1MES - not implemented\n")); m_fga002[FGA_ISFMB1MES] = data; break;
+ case FGA_ABORTPIN : LOG(("FGA_ABORTPIN - not implemented\n")); m_fga002[FGA_ABORTPIN] = data; break;
default:
LOG(("Unsupported register %04x\n", offset));
}
}
READ8_MEMBER (fccpu30_state::fga8_r){
-
UINT8 ret = 0;
- LOG(("%s[%04x] ", FUNCNAME, offset));
+ LOG(("%s[%04x] ", FUNCNAME, offset));
switch(offset)
{
- case FGA_SPECIALENA : ret = m_fga002[FGA_SPECIALENA]; LOG(("FGA_SPECIALENA returns %02x - not implemented\n", ret)); break;
- case FGA_RSVMECALL : ret = m_fga002[FGA_RSVMECALL]; LOG(("FGA_RSVMECALL returns %02x - not implemented\n", ret)); break;
- case FGA_RSKEYRES : ret = m_fga002[FGA_RSKEYRES]; LOG(("FGA_RSKEYRES returns %02x - not implemented\n", ret)); break;
- case FGA_RSCPUCALL : ret = m_fga002[FGA_RSCPUCALL]; LOG(("FGA_RSCPUCALL returns %02x - not implemented\n", ret)); break;
- case FGA_RSLOCSW : ret = m_fga002[FGA_RSLOCSW]; LOG(("FGA_RSLOCSW returns %02x - not implemented\n", ret)); break;
- case FGA_ICRMBOX0 : ret = m_fga002[FGA_ICRMBOX0]; LOG(("FGA_ICRMBOX0 returns %02x - not implemented\n", ret)); break;
- case FGA_ICRMBOX1 : ret = m_fga002[FGA_ICRMBOX1]; LOG(("FGA_ICRMBOX1 returns %02x - not implemented\n", ret)); break;
- case FGA_ICRMBOX2 : ret = m_fga002[FGA_ICRMBOX2]; LOG(("FGA_ICRMBOX2 returns %02x - not implemented\n", ret)); break;
- case FGA_ICRMBOX3 : ret = m_fga002[FGA_ICRMBOX3]; LOG(("FGA_ICRMBOX3 returns %02x - not implemented\n", ret)); break;
- case FGA_ICRMBOX4 : ret = m_fga002[FGA_ICRMBOX4]; LOG(("FGA_ICRMBOX4 returns %02x - not implemented\n", ret)); break;
- case FGA_ICRMBOX5 : ret = m_fga002[FGA_ICRMBOX5]; LOG(("FGA_ICRMBOX5 returns %02x - not implemented\n", ret)); break;
- case FGA_ICRMBOX6 : ret = m_fga002[FGA_ICRMBOX6]; LOG(("FGA_ICRMBOX6 returns %02x - not implemented\n", ret)); break;
- case FGA_ICRMBOX7 : ret = m_fga002[FGA_ICRMBOX7]; LOG(("FGA_ICRMBOX7 returns %02x - not implemented\n", ret)); break;
- case FGA_VMEPAGE : ret = m_fga002[FGA_VMEPAGE]; LOG(("FGA_VMEPAGE returns %02x - not implemented\n", ret)); break;
- case FGA_ICRVME1 : ret = m_fga002[FGA_ICRVME1]; LOG(("FGA_ICRVME1 returns %02x - not implemented\n", ret)); break;
- case FGA_ICRVME2 : ret = m_fga002[FGA_ICRVME2]; LOG(("FGA_ICRVME2 returns %02x - not implemented\n", ret)); break;
- case FGA_ICRVME3 : ret = m_fga002[FGA_ICRVME3]; LOG(("FGA_ICRVME3 returns %02x - not implemented\n", ret)); break;
- case FGA_ICRVME4 : ret = m_fga002[FGA_ICRVME4]; LOG(("FGA_ICRVME4 returns %02x - not implemented\n", ret)); break;
- case FGA_ICRVME5 : ret = m_fga002[FGA_ICRVME5]; LOG(("FGA_ICRVME5 returns %02x - not implemented\n", ret)); break;
- case FGA_ICRVME6 : ret = m_fga002[FGA_ICRVME6]; LOG(("FGA_ICRVME6 returns %02x - not implemented\n", ret)); break;
- case FGA_ICRVME7 : ret = m_fga002[FGA_ICRVME7]; LOG(("FGA_ICRVME7 returns %02x - not implemented\n", ret)); break;
- case FGA_ICRTIM0 : ret = m_fga002[FGA_ICRTIM0]; LOG(("FGA_ICRTIM0 returns %02x - not implemented\n", ret)); break;
- case FGA_ICRDMANORM : ret = m_fga002[FGA_ICRDMANORM]; LOG(("FGA_ICRDMANORM returns %02x - not implemented\n", ret)); break;
- case FGA_ICRDMAERR : ret = m_fga002[FGA_ICRDMAERR]; LOG(("FGA_ICRDMAERR returns %02x - not implemented\n", ret)); break;
- case FGA_CTL1 : ret = m_fga002[FGA_CTL1]; LOG(("FGA_CTL1 returns %02x - not implemented\n", ret)); break;
- case FGA_CTL2 : ret = m_fga002[FGA_CTL2]; LOG(("FGA_CTL2 returns %02x - not implemented\n", ret)); break;
- case FGA_ICRFMB0REF : ret = m_fga002[FGA_ICRFMB0REF]; LOG(("FGA_ICRFMB0REF returns %02x - not implemented\n", ret)); break;
- case FGA_ICRFMB1REF : ret = m_fga002[FGA_ICRFMB1REF]; LOG(("FGA_ICRFMB1REF returns %02x - not implemented\n", ret)); break;
- case FGA_ICRFMB0MES : ret = m_fga002[FGA_ICRFMB0MES]; LOG(("FGA_ICRFMB0MES returns %02x - not implemented\n", ret)); break;
- case FGA_ICRFMB1MES : ret = m_fga002[FGA_ICRFMB1MES]; LOG(("FGA_ICRFMB1MES returns %02x - not implemented\n", ret)); break;
- case FGA_CTL3 : ret = m_fga002[FGA_CTL3]; LOG(("FGA_CTL3 returns %02x - not implemented\n", ret)); break;
- case FGA_CTL4 : ret = m_fga002[FGA_CTL4]; LOG(("FGA_CTL4 returns %02x - not implemented\n", ret)); break;
- case FGA_ICRPARITY : ret = m_fga002[FGA_ICRPARITY]; LOG(("FGA_ICRPARITY returns %02x - not implemented\n", ret)); break;
- case FGA_AUXPINCTL : ret = m_fga002[FGA_AUXPINCTL]; LOG(("FGA_AUXPINCTL returns %02x - not implemented\n", ret)); break;
- case FGA_CTL5 : ret = m_fga002[FGA_CTL5]; LOG(("FGA_CTL5 returns %02x - not implemented\n", ret)); break;
- case FGA_AUXFIFWEX : ret = m_fga002[FGA_AUXFIFWEX]; LOG(("FGA_AUXFIFWEX returns %02x - not implemented\n", ret)); break;
- case FGA_AUXFIFREX : ret = m_fga002[FGA_AUXFIFREX]; LOG(("FGA_AUXFIFREX returns %02x - not implemented\n", ret)); break;
- case FGA_CTL6 : ret = m_fga002[FGA_CTL6]; LOG(("FGA_CTL6 returns %02x - not implemented\n", ret)); break;
- case FGA_CTL7 : ret = m_fga002[FGA_CTL7]; LOG(("FGA_CTL7 returns %02x - not implemented\n", ret)); break;
- case FGA_CTL8 : ret = m_fga002[FGA_CTL8]; LOG(("FGA_CTL8 returns %02x - not implemented\n", ret)); break;
- case FGA_CTL9 : ret = m_fga002[FGA_CTL9]; LOG(("FGA_CTL9 returns %02x - not implemented\n", ret)); break;
- case FGA_ICRABORT : ret = m_fga002[FGA_ICRABORT]; LOG(("FGA_ICRABORT returns %02x - not implemented\n", ret)); break;
- case FGA_ICRACFAIL : ret = m_fga002[FGA_ICRACFAIL]; LOG(("FGA_ICRACFAIL returns %02x - not implemented\n", ret)); break;
- case FGA_ICRSYSFAIL : ret = m_fga002[FGA_ICRSYSFAIL]; LOG(("FGA_ICRSYSFAIL returns %02x - not implemented\n", ret)); break;
- case FGA_ICRLOCAL0 : ret = m_fga002[FGA_ICRLOCAL0]; LOG(("FGA_ICRLOCAL0 returns %02x - not implemented\n", ret)); break;
- case FGA_ICRLOCAL1 : ret = m_fga002[FGA_ICRLOCAL1]; LOG(("FGA_ICRLOCAL1 returns %02x - not implemented\n", ret)); break;
- case FGA_ICRLOCAL2 : ret = m_fga002[FGA_ICRLOCAL2]; LOG(("FGA_ICRLOCAL2 returns %02x - not implemented\n", ret)); break;
- case FGA_ICRLOCAL3 : ret = m_fga002[FGA_ICRLOCAL3]; LOG(("FGA_ICRLOCAL3 returns %02x - not implemented\n", ret)); break;
- case FGA_ICRLOCAL4 : ret = m_fga002[FGA_ICRLOCAL4]; LOG(("FGA_ICRLOCAL4 returns %02x - not implemented\n", ret)); break;
- case FGA_ICRLOCAL5 : ret = m_fga002[FGA_ICRLOCAL5]; LOG(("FGA_ICRLOCAL5 returns %02x - not implemented\n", ret)); break;
- case FGA_ICRLOCAL6 : ret = m_fga002[FGA_ICRLOCAL6]; LOG(("FGA_ICRLOCAL6 returns %02x - not implemented\n", ret)); break;
- case FGA_ICRLOCAL7 : ret = m_fga002[FGA_ICRLOCAL7]; LOG(("FGA_ICRLOCAL7 returns %02x - not implemented\n", ret)); break;
- case FGA_ENAMCODE : ret = m_fga002[FGA_ENAMCODE]; LOG(("FGA_ENAMCODE returns %02x - not implemented\n", ret)); break;
- case FGA_CTL10 : ret = m_fga002[FGA_CTL10]; LOG(("FGA_CTL10 returns %02x - not implemented\n", ret)); break;
- case FGA_CTL11 : ret = m_fga002[FGA_CTL11]; LOG(("FGA_CTL11 returns %02x - not implemented\n", ret)); break;
- case FGA_MAINUM : ret = m_fga002[FGA_MAINUM]; LOG(("FGA_MAINUM returns %02x - not implemented\n", ret)); break;
- case FGA_MAINUU : ret = m_fga002[FGA_MAINUU]; LOG(("FGA_MAINUU returns %02x - not implemented\n", ret)); break;
- case FGA_BOTTOMPAGEU : ret = m_fga002[FGA_BOTTOMPAGEU]; LOG(("FGA_BOTTOMPAGEU returns %02x - not implemented\n", ret)); break;
- case FGA_BOTTOMPAGEL : ret = m_fga002[FGA_BOTTOMPAGEL]; LOG(("FGA_BOTTOMPAGEL returns %02x - not implemented\n", ret)); break;
- case FGA_TOPPAGEU : ret = m_fga002[FGA_TOPPAGEU]; LOG(("FGA_TOPPAGEU returns %02x - not implemented\n", ret)); break;
- case FGA_TOPPAGEL : ret = m_fga002[FGA_TOPPAGEL]; LOG(("FGA_TOPPAGEL returns %02x - not implemented\n", ret)); break;
- case FGA_MYVMEPAGE : ret = m_fga002[FGA_MYVMEPAGE]; LOG(("FGA_MYVMEPAGE returns %02x - not implemented\n", ret)); break;
- case FGA_TIM0PRELOAD : ret = m_fga002[FGA_TIM0PRELOAD]; LOG(("FGA_TIM0PRELOAD returns %02x - not implemented\n", ret)); break;
- case FGA_TIM0CTL : ret = m_fga002[FGA_TIM0CTL]; LOG(("FGA_TIM0CTL returns %02x - not implemented\n", ret)); break;
- case FGA_DMASRCATT : ret = m_fga002[FGA_DMASRCATT]; LOG(("FGA_DMASRCATT returns %02x - not implemented\n", ret)); break;
- case FGA_DMADSTATT : ret = m_fga002[FGA_DMADSTATT]; LOG(("FGA_DMADSTATT returns %02x - not implemented\n", ret)); break;
- case FGA_DMA_GENERAL : ret = m_fga002[FGA_DMA_GENERAL]; LOG(("FGA_DMA_GENERAL returns %02x - not implemented\n", ret)); break;
- case FGA_CTL12 : ret = m_fga002[FGA_CTL12]; LOG(("FGA_CTL12 returns %02x - not implemented\n", ret)); break;
- case FGA_LIOTIMING : ret = m_fga002[FGA_LIOTIMING]; LOG(("FGA_LIOTIMING returns %02x - not implemented\n", ret)); break;
- case FGA_LOCALIACK : ret = m_fga002[FGA_LOCALIACK]; LOG(("FGA_LOCALIACK returns %02x - not implemented\n", ret)); break;
- case FGA_FMBCTL : ret = m_fga002[FGA_FMBCTL]; LOG(("FGA_FMBCTL returns %02x - not implemented\n", ret)); break;
- case FGA_FMBAREA : ret = m_fga002[FGA_FMBAREA]; LOG(("FGA_FMBAREA returns %02x - not implemented\n", ret)); break;
- case FGA_AUXSRCSTART : ret = m_fga002[FGA_AUXSRCSTART]; LOG(("FGA_AUXSRCSTART returns %02x - not implemented\n", ret)); break;
- case FGA_AUXDSTSTART : ret = m_fga002[FGA_AUXDSTSTART]; LOG(("FGA_AUXDSTSTART returns %02x - not implemented\n", ret)); break;
- case FGA_AUXSRCTERM : ret = m_fga002[FGA_AUXSRCTERM]; LOG(("FGA_AUXSRCTERM returns %02x - not implemented\n", ret)); break;
- case FGA_AUXDSTTERM : ret = m_fga002[FGA_AUXDSTTERM]; LOG(("FGA_AUXDSTTERM returns %02x - not implemented\n", ret)); break;
- case FGA_CTL13 : ret = m_fga002[FGA_CTL13]; LOG(("FGA_CTL13 returns %02x - not implemented\n", ret)); break;
- case FGA_CTL14 : ret = m_fga002[FGA_CTL14]; LOG(("FGA_CTL14 returns %02x - not implemented\n", ret)); break;
- case FGA_CTL15 : ret = m_fga002[FGA_CTL15]; LOG(("FGA_CTL15 returns %02x - not implemented\n", ret)); break;
- case FGA_CTL16 : ret = m_fga002[FGA_CTL16]; LOG(("FGA_CTL16 returns %02x - not implemented\n", ret)); break;
- case FGA_ISTIM0 : ret = m_fga002[FGA_ISTIM0]; LOG(("FGA_ISTIM0 returns %02x - not implemented\n", ret)); break;
- case FGA_ISDMANORM : ret = m_fga002[FGA_ISDMANORM]; LOG(("FGA_ISDMANORM returns %02x - not implemented\n", ret)); break;
- case FGA_ISDMAERR : ret = m_fga002[FGA_ISDMAERR]; LOG(("FGA_ISDMAERR returns %02x - not implemented\n", ret)); break;
- case FGA_ISFMB0REF : ret = m_fga002[FGA_ISFMB0REF]; LOG(("FGA_ISFMB0REF returns %02x - not implemented\n", ret)); break;
- case FGA_ISFMB1REF : ret = m_fga002[FGA_ISFMB1REF]; LOG(("FGA_ISFMB1REF returns %02x - not implemented\n", ret)); break;
- case FGA_ISPARITY : ret = m_fga002[FGA_ISPARITY]; LOG(("FGA_ISPARITY returns %02x - not implemented\n", ret)); break;
- case FGA_DMARUNCTL : ret = m_fga002[FGA_DMARUNCTL]; LOG(("FGA_DMARUNCTL returns %02x - not implemented\n", ret)); break;
- case FGA_ISABORT : ret = m_fga002[FGA_ISABORT]; LOG(("FGA_ISABORT returns %02x - not implemented\n", ret)); break;
- case FGA_ISFMB0MES : ret = m_fga002[FGA_ISFMB0MES]; LOG(("FGA_ISFMB0MES returns %02x - not implemented\n", ret)); break;
- case FGA_ISFMB1MES : ret = m_fga002[FGA_ISFMB1MES]; LOG(("FGA_ISFMB1MES returns %02x - not implemented\n", ret)); break;
- case FGA_ABORTPIN : ret = m_fga002[FGA_ABORTPIN]; LOG(("FGA_ABORTPIN returns %02x - not implemented\n", ret)); break;
+ case FGA_SPECIALENA : ret = m_fga002[FGA_SPECIALENA]; LOG(("FGA_SPECIALENA returns %02x - not implemented\n", ret)); break;
+ case FGA_RSVMECALL : ret = m_fga002[FGA_RSVMECALL]; LOG(("FGA_RSVMECALL returns %02x - not implemented\n", ret)); break;
+ case FGA_RSKEYRES : ret = m_fga002[FGA_RSKEYRES]; LOG(("FGA_RSKEYRES returns %02x - not implemented\n", ret)); break;
+ case FGA_RSCPUCALL : ret = m_fga002[FGA_RSCPUCALL]; LOG(("FGA_RSCPUCALL returns %02x - not implemented\n", ret)); break;
+ case FGA_RSLOCSW : ret = m_fga002[FGA_RSLOCSW]; LOG(("FGA_RSLOCSW returns %02x - not implemented\n", ret)); break;
+ case FGA_ICRMBOX0 : ret = m_fga002[FGA_ICRMBOX0]; LOG(("FGA_ICRMBOX0 returns %02x - not implemented\n", ret)); break;
+ case FGA_ICRMBOX1 : ret = m_fga002[FGA_ICRMBOX1]; LOG(("FGA_ICRMBOX1 returns %02x - not implemented\n", ret)); break;
+ case FGA_ICRMBOX2 : ret = m_fga002[FGA_ICRMBOX2]; LOG(("FGA_ICRMBOX2 returns %02x - not implemented\n", ret)); break;
+ case FGA_ICRMBOX3 : ret = m_fga002[FGA_ICRMBOX3]; LOG(("FGA_ICRMBOX3 returns %02x - not implemented\n", ret)); break;
+ case FGA_ICRMBOX4 : ret = m_fga002[FGA_ICRMBOX4]; LOG(("FGA_ICRMBOX4 returns %02x - not implemented\n", ret)); break;
+ case FGA_ICRMBOX5 : ret = m_fga002[FGA_ICRMBOX5]; LOG(("FGA_ICRMBOX5 returns %02x - not implemented\n", ret)); break;
+ case FGA_ICRMBOX6 : ret = m_fga002[FGA_ICRMBOX6]; LOG(("FGA_ICRMBOX6 returns %02x - not implemented\n", ret)); break;
+ case FGA_ICRMBOX7 : ret = m_fga002[FGA_ICRMBOX7]; LOG(("FGA_ICRMBOX7 returns %02x - not implemented\n", ret)); break;
+ case FGA_VMEPAGE : ret = m_fga002[FGA_VMEPAGE]; LOG(("FGA_VMEPAGE returns %02x - not implemented\n", ret)); break;
+ case FGA_ICRVME1 : ret = m_fga002[FGA_ICRVME1]; LOG(("FGA_ICRVME1 returns %02x - not implemented\n", ret)); break;
+ case FGA_ICRVME2 : ret = m_fga002[FGA_ICRVME2]; LOG(("FGA_ICRVME2 returns %02x - not implemented\n", ret)); break;
+ case FGA_ICRVME3 : ret = m_fga002[FGA_ICRVME3]; LOG(("FGA_ICRVME3 returns %02x - not implemented\n", ret)); break;
+ case FGA_ICRVME4 : ret = m_fga002[FGA_ICRVME4]; LOG(("FGA_ICRVME4 returns %02x - not implemented\n", ret)); break;
+ case FGA_ICRVME5 : ret = m_fga002[FGA_ICRVME5]; LOG(("FGA_ICRVME5 returns %02x - not implemented\n", ret)); break;
+ case FGA_ICRVME6 : ret = m_fga002[FGA_ICRVME6]; LOG(("FGA_ICRVME6 returns %02x - not implemented\n", ret)); break;
+ case FGA_ICRVME7 : ret = m_fga002[FGA_ICRVME7]; LOG(("FGA_ICRVME7 returns %02x - not implemented\n", ret)); break;
+ case FGA_ICRTIM0 : ret = m_fga002[FGA_ICRTIM0]; LOG(("FGA_ICRTIM0 returns %02x - not implemented\n", ret)); break;
+ case FGA_ICRDMANORM : ret = m_fga002[FGA_ICRDMANORM]; LOG(("FGA_ICRDMANORM returns %02x - not implemented\n", ret)); break;
+ case FGA_ICRDMAERR : ret = m_fga002[FGA_ICRDMAERR]; LOG(("FGA_ICRDMAERR returns %02x - not implemented\n", ret)); break;
+ case FGA_CTL1 : ret = m_fga002[FGA_CTL1]; LOG(("FGA_CTL1 returns %02x - not implemented\n", ret)); break;
+ case FGA_CTL2 : ret = m_fga002[FGA_CTL2]; LOG(("FGA_CTL2 returns %02x - not implemented\n", ret)); break;
+ case FGA_ICRFMB0REF : ret = m_fga002[FGA_ICRFMB0REF]; LOG(("FGA_ICRFMB0REF returns %02x - not implemented\n", ret)); break;
+ case FGA_ICRFMB1REF : ret = m_fga002[FGA_ICRFMB1REF]; LOG(("FGA_ICRFMB1REF returns %02x - not implemented\n", ret)); break;
+ case FGA_ICRFMB0MES : ret = m_fga002[FGA_ICRFMB0MES]; LOG(("FGA_ICRFMB0MES returns %02x - not implemented\n", ret)); break;
+ case FGA_ICRFMB1MES : ret = m_fga002[FGA_ICRFMB1MES]; LOG(("FGA_ICRFMB1MES returns %02x - not implemented\n", ret)); break;
+ case FGA_CTL3 : ret = m_fga002[FGA_CTL3]; LOG(("FGA_CTL3 returns %02x - not implemented\n", ret)); break;
+ case FGA_CTL4 : ret = m_fga002[FGA_CTL4]; LOG(("FGA_CTL4 returns %02x - not implemented\n", ret)); break;
+ case FGA_ICRPARITY : ret = m_fga002[FGA_ICRPARITY]; LOG(("FGA_ICRPARITY returns %02x - not implemented\n", ret)); break;
+ case FGA_AUXPINCTL : ret = m_fga002[FGA_AUXPINCTL]; LOG(("FGA_AUXPINCTL returns %02x - not implemented\n", ret)); break;
+ case FGA_CTL5 : ret = m_fga002[FGA_CTL5]; LOG(("FGA_CTL5 returns %02x - not implemented\n", ret)); break;
+ case FGA_AUXFIFWEX : ret = m_fga002[FGA_AUXFIFWEX]; LOG(("FGA_AUXFIFWEX returns %02x - not implemented\n", ret)); break;
+ case FGA_AUXFIFREX : ret = m_fga002[FGA_AUXFIFREX]; LOG(("FGA_AUXFIFREX returns %02x - not implemented\n", ret)); break;
+ case FGA_CTL6 : ret = m_fga002[FGA_CTL6]; LOG(("FGA_CTL6 returns %02x - not implemented\n", ret)); break;
+ case FGA_CTL7 : ret = m_fga002[FGA_CTL7]; LOG(("FGA_CTL7 returns %02x - not implemented\n", ret)); break;
+ case FGA_CTL8 : ret = m_fga002[FGA_CTL8]; LOG(("FGA_CTL8 returns %02x - not implemented\n", ret)); break;
+ case FGA_CTL9 : ret = m_fga002[FGA_CTL9]; LOG(("FGA_CTL9 returns %02x - not implemented\n", ret)); break;
+ case FGA_ICRABORT : ret = m_fga002[FGA_ICRABORT]; LOG(("FGA_ICRABORT returns %02x - not implemented\n", ret)); break;
+ case FGA_ICRACFAIL : ret = m_fga002[FGA_ICRACFAIL]; LOG(("FGA_ICRACFAIL returns %02x - not implemented\n", ret)); break;
+ case FGA_ICRSYSFAIL : ret = m_fga002[FGA_ICRSYSFAIL]; LOG(("FGA_ICRSYSFAIL returns %02x - not implemented\n", ret)); break;
+ case FGA_ICRLOCAL0 : ret = m_fga002[FGA_ICRLOCAL0]; LOG(("FGA_ICRLOCAL0 returns %02x - not implemented\n", ret)); break;
+ case FGA_ICRLOCAL1 : ret = m_fga002[FGA_ICRLOCAL1]; LOG(("FGA_ICRLOCAL1 returns %02x - not implemented\n", ret)); break;
+ case FGA_ICRLOCAL2 : ret = m_fga002[FGA_ICRLOCAL2]; LOG(("FGA_ICRLOCAL2 returns %02x - not implemented\n", ret)); break;
+ case FGA_ICRLOCAL3 : ret = m_fga002[FGA_ICRLOCAL3]; LOG(("FGA_ICRLOCAL3 returns %02x - not implemented\n", ret)); break;
+ case FGA_ICRLOCAL4 : ret = m_fga002[FGA_ICRLOCAL4]; LOG(("FGA_ICRLOCAL4 returns %02x - not implemented\n", ret)); break;
+ case FGA_ICRLOCAL5 : ret = m_fga002[FGA_ICRLOCAL5]; LOG(("FGA_ICRLOCAL5 returns %02x - not implemented\n", ret)); break;
+ case FGA_ICRLOCAL6 : ret = m_fga002[FGA_ICRLOCAL6]; LOG(("FGA_ICRLOCAL6 returns %02x - not implemented\n", ret)); break;
+ case FGA_ICRLOCAL7 : ret = m_fga002[FGA_ICRLOCAL7]; LOG(("FGA_ICRLOCAL7 returns %02x - not implemented\n", ret)); break;
+ case FGA_ENAMCODE : ret = m_fga002[FGA_ENAMCODE]; LOG(("FGA_ENAMCODE returns %02x - not implemented\n", ret)); break;
+ case FGA_CTL10 : ret = m_fga002[FGA_CTL10]; LOG(("FGA_CTL10 returns %02x - not implemented\n", ret)); break;
+ case FGA_CTL11 : ret = m_fga002[FGA_CTL11]; LOG(("FGA_CTL11 returns %02x - not implemented\n", ret)); break;
+ case FGA_MAINUM : ret = m_fga002[FGA_MAINUM]; LOG(("FGA_MAINUM returns %02x - not implemented\n", ret)); break;
+ case FGA_MAINUU : ret = m_fga002[FGA_MAINUU]; LOG(("FGA_MAINUU returns %02x - not implemented\n", ret)); break;
+ case FGA_BOTTOMPAGEU : ret = m_fga002[FGA_BOTTOMPAGEU]; LOG(("FGA_BOTTOMPAGEU returns %02x - not implemented\n", ret)); break;
+ case FGA_BOTTOMPAGEL : ret = m_fga002[FGA_BOTTOMPAGEL]; LOG(("FGA_BOTTOMPAGEL returns %02x - not implemented\n", ret)); break;
+ case FGA_TOPPAGEU : ret = m_fga002[FGA_TOPPAGEU]; LOG(("FGA_TOPPAGEU returns %02x - not implemented\n", ret)); break;
+ case FGA_TOPPAGEL : ret = m_fga002[FGA_TOPPAGEL]; LOG(("FGA_TOPPAGEL returns %02x - not implemented\n", ret)); break;
+ case FGA_MYVMEPAGE : ret = m_fga002[FGA_MYVMEPAGE]; LOG(("FGA_MYVMEPAGE returns %02x - not implemented\n", ret)); break;
+ case FGA_TIM0PRELOAD : ret = m_fga002[FGA_TIM0PRELOAD]; LOG(("FGA_TIM0PRELOAD returns %02x - not implemented\n", ret)); break;
+ case FGA_TIM0CTL : ret = m_fga002[FGA_TIM0CTL]; LOG(("FGA_TIM0CTL returns %02x - not implemented\n", ret)); break;
+ case FGA_DMASRCATT : ret = m_fga002[FGA_DMASRCATT]; LOG(("FGA_DMASRCATT returns %02x - not implemented\n", ret)); break;
+ case FGA_DMADSTATT : ret = m_fga002[FGA_DMADSTATT]; LOG(("FGA_DMADSTATT returns %02x - not implemented\n", ret)); break;
+ case FGA_DMA_GENERAL : ret = m_fga002[FGA_DMA_GENERAL]; LOG(("FGA_DMA_GENERAL returns %02x - not implemented\n", ret)); break;
+ case FGA_CTL12 : ret = m_fga002[FGA_CTL12]; LOG(("FGA_CTL12 returns %02x - not implemented\n", ret)); break;
+ case FGA_LIOTIMING : ret = m_fga002[FGA_LIOTIMING]; LOG(("FGA_LIOTIMING returns %02x - not implemented\n", ret)); break;
+ case FGA_LOCALIACK : ret = m_fga002[FGA_LOCALIACK]; LOG(("FGA_LOCALIACK returns %02x - not implemented\n", ret)); break;
+ case FGA_FMBCTL : ret = m_fga002[FGA_FMBCTL]; LOG(("FGA_FMBCTL returns %02x - not implemented\n", ret)); break;
+ case FGA_FMBAREA : ret = m_fga002[FGA_FMBAREA]; LOG(("FGA_FMBAREA returns %02x - not implemented\n", ret)); break;
+ case FGA_AUXSRCSTART : ret = m_fga002[FGA_AUXSRCSTART]; LOG(("FGA_AUXSRCSTART returns %02x - not implemented\n", ret)); break;
+ case FGA_AUXDSTSTART : ret = m_fga002[FGA_AUXDSTSTART]; LOG(("FGA_AUXDSTSTART returns %02x - not implemented\n", ret)); break;
+ case FGA_AUXSRCTERM : ret = m_fga002[FGA_AUXSRCTERM]; LOG(("FGA_AUXSRCTERM returns %02x - not implemented\n", ret)); break;
+ case FGA_AUXDSTTERM : ret = m_fga002[FGA_AUXDSTTERM]; LOG(("FGA_AUXDSTTERM returns %02x - not implemented\n", ret)); break;
+ case FGA_CTL13 : ret = m_fga002[FGA_CTL13]; LOG(("FGA_CTL13 returns %02x - not implemented\n", ret)); break;
+ case FGA_CTL14 : ret = m_fga002[FGA_CTL14]; LOG(("FGA_CTL14 returns %02x - not implemented\n", ret)); break;
+ case FGA_CTL15 : ret = m_fga002[FGA_CTL15]; LOG(("FGA_CTL15 returns %02x - not implemented\n", ret)); break;
+ case FGA_CTL16 : ret = m_fga002[FGA_CTL16]; LOG(("FGA_CTL16 returns %02x - not implemented\n", ret)); break;
+ case FGA_ISTIM0 : ret = m_fga002[FGA_ISTIM0]; LOG(("FGA_ISTIM0 returns %02x - not implemented\n", ret)); break;
+ case FGA_ISDMANORM : ret = m_fga002[FGA_ISDMANORM]; LOG(("FGA_ISDMANORM returns %02x - not implemented\n", ret)); break;
+ case FGA_ISDMAERR : ret = m_fga002[FGA_ISDMAERR]; LOG(("FGA_ISDMAERR returns %02x - not implemented\n", ret)); break;
+ case FGA_ISFMB0REF : ret = m_fga002[FGA_ISFMB0REF]; LOG(("FGA_ISFMB0REF returns %02x - not implemented\n", ret)); break;
+ case FGA_ISFMB1REF : ret = m_fga002[FGA_ISFMB1REF]; LOG(("FGA_ISFMB1REF returns %02x - not implemented\n", ret)); break;
+ case FGA_ISPARITY : ret = m_fga002[FGA_ISPARITY]; LOG(("FGA_ISPARITY returns %02x - not implemented\n", ret)); break;
+ case FGA_DMARUNCTL : ret = m_fga002[FGA_DMARUNCTL]; LOG(("FGA_DMARUNCTL returns %02x - not implemented\n", ret)); break;
+ case FGA_ISABORT : ret = m_fga002[FGA_ISABORT]; LOG(("FGA_ISABORT returns %02x - not implemented\n", ret)); break;
+ case FGA_ISFMB0MES : ret = m_fga002[FGA_ISFMB0MES]; LOG(("FGA_ISFMB0MES returns %02x - not implemented\n", ret)); break;
+ case FGA_ISFMB1MES : ret = m_fga002[FGA_ISFMB1MES]; LOG(("FGA_ISFMB1MES returns %02x - not implemented\n", ret)); break;
+ case FGA_ABORTPIN : ret = m_fga002[FGA_ABORTPIN]; LOG(("FGA_ABORTPIN returns %02x - not implemented\n", ret)); break;
default:
LOG(("Unsupported register %04x\n", offset));
}
return ret;
}
-/*
+/*
* Rotary Switches - to configure the board
*
* Table 25: PI/T #1 Interface Signals
@@ -625,20 +624,20 @@ READ8_MEMBER (fccpu30_state::fga8_r){
* PA4 PA7 SW2 In
*
* Table 38: Upper Rotary Switch (SW2)
- * Bit 3: This bit indicates whether the RAM disk should be initialized after reset. If this bit is set to "0" (settings 0-7),
- * the RAM disk is initialized as defined by bit 0 and 1. When the disk is initialized, all data on the disk is lost.
- * Bit 2: This bit defines the default data size on the VMEbus. If the bit is set to "0", 16 bits are selected, if it is set
+ * Bit 3: This bit indicates whether the RAM disk should be initialized after reset. If this bit is set to "0" (settings 0-7),
+ * the RAM disk is initialized as defined by bit 0 and 1. When the disk is initialized, all data on the disk is lost.
+ * Bit 2: This bit defines the default data size on the VMEbus. If the bit is set to "0", 16 bits are selected, if it is set
* to "1", 32 bits are selected.
* Bit 1 and Bit 0: These two bits define the default RAM disk. See Table 40, "RAM Disk Usage," a detailed description.
- * If AUTOBOOT is set by bit 2 and 3 of SW1, bit 1 and 0 of SW2 define which operating system will be booted. See Table 42,
+ * If AUTOBOOT is set by bit 2 and 3 of SW1, bit 1 and 0 of SW2 define which operating system will be booted. See Table 42,
* "Boot an Operating System (if AUTOBOOT is selected)," on page 129 for detailed description.
*
* Table 39: Lower Rotary Switch (SW1)
* Bit 3 and Bit 2: These two bits define which program is to be invoked after reset. Please refer
* to Table 41, "Program After Reset," on page 129 for a detailed description.
- * Bit 1: If this switch is "0" (settings 0,1,4,5,8,9,C,D), VMEPROM tries to execute a start-up file after reset. The default
+ * Bit 1: If this switch is "0" (settings 0,1,4,5,8,9,C,D), VMEPROM tries to execute a start-up file after reset. The default
* filename is SY$STRT. If the bit is "1", VMEPROM comes up with the default banner.
- * Bit 0: If this switch is set to "0" (settings 0,2,4,6,8,A,C,E), VMEPROM checks the VMEbus for available hardware after reset.
+ * Bit 0: If this switch is set to "0" (settings 0,2,4,6,8,A,C,E), VMEPROM checks the VMEbus for available hardware after reset.
* In addition VMEPROM waits for SYSFAIL to disappear from the VMEbus. The following hardware can be detected:
* - Contiguous memory
* - ASCU-1/2
@@ -655,20 +654,20 @@ READ8_MEMBER (fccpu30_state::fga8_r){
* 0 0 RAM DISK AT 0x4080 0000 (512 Kbytes) 0,4,8,C
*
* Table 41: Program After Reset
- * Bit 3 Bit 2 Lower Switch (SW 1) selected on
- * 1 1 VMEPROM C,D,E,F
- * 1 0 USER PROGRAM AT 0x4070 0000 8,9,A,B
- * 0 1 AUTOBOOT SYSTEM 4,5,6,7
- * 0 0 USER PROGRAM AT 4080.000016 0,1,2,3
+ * Bit 3 Bit 2 Lower Switch (SW 1) selected on
+ * 1 1 VMEPROM C,D,E,F
+ * 1 0 USER PROGRAM AT 0x4070 0000 8,9,A,B
+ * 0 1 AUTOBOOT SYSTEM 4,5,6,7
+ * 0 0 USER PROGRAM AT 4080.000016 0,1,2,3
*
* Table 42: Boot an Operating System (if AUTOBOOT is selected)
- * Bit 1 Bit 0 Upper Switch (SW 2) selected on
- * 1 1 reserved 3,7,B,F
- * 1 0 Boot UNIX/PDOS 4.x 2,6,A,E
- * 0 1 Boot another operating system 1,5,9,D
- * 0 0 Setup for UNIX mailbox driver 0,4,8,C
+ * Bit 1 Bit 0 Upper Switch (SW 2) selected on
+ * 1 1 reserved 3,7,B,F
+ * 1 0 Boot UNIX/PDOS 4.x 2,6,A,E
+ * 0 1 Boot another operating system 1,5,9,D
+ * 0 0 Setup for UNIX mailbox driver 0,4,8,C
*
- * "To start VMEPROM, the rotary switches must both be set to 'F':" Hmm...
+ * "To start VMEPROM, the rotary switches must both be set to 'F':" Hmm...
*/
READ8_MEMBER (fccpu30_state::rotary_rd){
LOG(("%s\n", FUNCNAME));
@@ -676,18 +675,18 @@ READ8_MEMBER (fccpu30_state::rotary_rd){
}
/*
- * PI/T #2 Factory settings
+ * PI/T #2 Factory settings
* B0-B2 Shared Memory Size - From these lines, the on-board Shared RAM capacity can be read in by software.
* 0 0 0 32 Mb
* 0 0 1 16 Mb
* 0 1 0 8 Mb
* 0 1 1 4 Mb
* 1 x x Reserved
- * B3-B7 Board ID(s) - From these lines, the CPU board identification number can be read in by
- * 0 1 0 1 0 CPU-30 R4 software. Every CPU board has a unique number. Different versions of
- * (fill in more) one CPU board (i.e. different speeds, capacity of memory, or modules)
- * contain the same identification number. In the case of the CPU-30 R4, the
- * number is ten ("10" decimal or 0A16 hexadecimal "01010" binary).
+ * B3-B7 Board ID(s) - From these lines, the CPU board identification number can be read in by
+ * 0 1 0 1 0 CPU-30 R4 software. Every CPU board has a unique number. Different versions of
+ * (fill in more) one CPU board (i.e. different speeds, capacity of memory, or modules)
+ * contain the same identification number. In the case of the CPU-30 R4, the
+ * number is ten ("10" decimal or 0A16 hexadecimal "01010" binary).
*/
READ8_MEMBER (fccpu30_state::board_mem_id_rd){
LOG(("%s\n", FUNCNAME));
@@ -734,7 +733,7 @@ static MACHINE_CONFIG_START (fccpu30, fccpu30_state)
MCFG_RS232_RXD_HANDLER (DEVWRITELINE ("duscc", duscc68562_device, rxa_w))
MCFG_RS232_CTS_HANDLER (DEVWRITELINE ("duscc", duscc68562_device, ctsa_w))
-// MCFG_DUSCC68562_ADD("duscc2", DUSCC_CLOCK, 0, 0, 0, 0 )
+// MCFG_DUSCC68562_ADD("duscc2", DUSCC_CLOCK, 0, 0, 0, 0 )
/* PIT Parallel Interface and Timer device, assuming strapped for on board clock */
MCFG_DEVICE_ADD ("pit1", PIT68230, XTAL_16MHz / 2)
@@ -747,9 +746,9 @@ MACHINE_CONFIG_END
ROM_START (fccpu30)
ROM_REGION32_BE(0xfff00000, "maincpu", 0)
-ROM_LOAD16_BYTE("CPU30LO.BIN", 0xff000000, 0x20000, CRC (fefa88ed) SHA1 (71a9ad807c0c2da5c6f6a6dc68c73ad8b52f3ea9))
-ROM_LOAD16_BYTE("CPU30UP.BIN", 0xff000001, 0x20000, CRC (dfed1f68) SHA1 (71478a77d5ab5da0fabcd78e69537919b560e3b8))
-ROM_LOAD("PGA-002.BIN", 0xffe00000, 0x10000, CRC (faa38972) SHA1 (651dfc2f9a865fc6adf49dad90f9e705f2889919))
+ROM_LOAD16_BYTE("CPU30LO.BIN", 0xff000000, 0x20000, CRC (fefa88ed) SHA1 (71a9ad807c0c2da5c6f6a6dc68c73ad8b52f3ea9))
+ROM_LOAD16_BYTE("CPU30UP.BIN", 0xff000001, 0x20000, CRC (dfed1f68) SHA1 (71478a77d5ab5da0fabcd78e69537919b560e3b8))
+ROM_LOAD("PGA-002.BIN", 0xffe00000, 0x10000, CRC (faa38972) SHA1 (651dfc2f9a865fc6adf49dad90f9e705f2889919))
/*
* System ROM information
@@ -784,8 +783,8 @@ ROM_LOAD("PGA-002.BIN", 0xffe00000, 0x10000, CRC (faa38972) SHA1 (651dfc2f9a86
* 05 3d -> REG_TTR - Tx BRG 9600 (assuming a 14.7456 crystal)
* 07 2d -> REG_RTR - Rx BRG 9600 (assuming a 14.7456 crystal)
* 0e 27 -> REG_PCR - TRxC = RxCLK 1x, RTxC is input, RTS, GPO2, crystal oscillator connected to X2
- * 0b f1 -> REG_OMR - RTS low, OUT1 = OUT2 = high, RxRdy asserted for each character,
- * TxRdy asserted on threshold, Same Tx Residual Character Length as for REG_TPR
+ * 0b f1 -> REG_OMR - RTS low, OUT1 = OUT2 = high, RxRdy asserted for each character,
+ * TxRdy asserted on threshold, Same Tx Residual Character Length as for REG_TPR
* 0f 00 -> REG_CCR - reset Tx Command
* 0f 40 -> REG_CCR - reset Rx Command
* 0f 02 -> REG_CCR - enable Tx Command
diff --git a/src/mame/drivers/fidel6502.cpp b/src/mame/drivers/fidel6502.cpp
index 0cec6776c1b..fc5ff5bc010 100644
--- a/src/mame/drivers/fidel6502.cpp
+++ b/src/mame/drivers/fidel6502.cpp
@@ -4,7 +4,7 @@
/******************************************************************************
Fidelity Electronics 6502 based board driver
-
+
TODO:
- EAS doesn't work, there's some activity if you boot/reset with 1-key held down
@@ -578,7 +578,7 @@ WRITE8_MEMBER(fidel6502_state::eas_ppi_portc_w)
// d0-d3: input/led mux
m_led_select = data & 0xf;
csc_prepare_display();
-
+
// other: ?
}
@@ -1322,7 +1322,7 @@ static MACHINE_CONFIG_START( eas, fidel6502_state )
MACHINE_CONFIG_END
static MACHINE_CONFIG_DERIVED( su9, csc )
-
+
/* basic machine hardware */
MCFG_CPU_REPLACE("maincpu", M6502, 2000000) // same as csc?
MCFG_CPU_PROGRAM_MAP(su9_map)
diff --git a/src/mame/drivers/funkball.cpp b/src/mame/drivers/funkball.cpp
index 44eb87d26ec..601b7e14a5c 100644
--- a/src/mame/drivers/funkball.cpp
+++ b/src/mame/drivers/funkball.cpp
@@ -228,7 +228,7 @@ WRITE8_MEMBER( funkball_state::serial_w )
{
if(offset == 0)
{
- // TODO: hack, main CPU sends a CR only here, actually expecting Windows-style newline.
+ // TODO: hack, main CPU sends a CR only here, actually expecting Windows-style newline.
if(data == 0x0d)
m_terminal->write(space,0,0x0a);
else
@@ -839,7 +839,7 @@ static MACHINE_CONFIG_START( funkball, funkball_state )
MCFG_SCREEN_VISIBLE_AREA(0, 511, 16, 447)
MCFG_DEVICE_ADD("terminal", GENERIC_TERMINAL, 0)
-
+
MCFG_INTEL_28F320J5_ADD("u29")
MCFG_INTEL_28F320J5_ADD("u30")
MCFG_INTEL_28F320J5_ADD("u3")
diff --git a/src/mame/drivers/galaxian.cpp b/src/mame/drivers/galaxian.cpp
index 1d6390e9169..81b4bad535e 100644
--- a/src/mame/drivers/galaxian.cpp
+++ b/src/mame/drivers/galaxian.cpp
@@ -2112,7 +2112,7 @@ static ADDRESS_MAP_START( takeoff_sound_portmap, AS_IO, 8, galaxian_state )
AM_RANGE(0x40, 0x40) AM_DEVWRITE("8912", ay8912_device, address_w)
AM_RANGE(0x80, 0x80) AM_DEVREADWRITE("8912", ay8912_device, data_r, data_w)
ADDRESS_MAP_END
-
+
/* King and Balloon with DAC */
static ADDRESS_MAP_START( kingball_sound_map, AS_PROGRAM, 8, galaxian_state )
ADDRESS_MAP_UNMAP_HIGH
diff --git a/src/mame/drivers/galivan.cpp b/src/mame/drivers/galivan.cpp
index 32edd23bf72..4b5e8b109b3 100644
--- a/src/mame/drivers/galivan.cpp
+++ b/src/mame/drivers/galivan.cpp
@@ -23,14 +23,14 @@ TODO
- bit 3 of ninjemak_gfxbank_w, there currently is a kludge to clear text RAM
but it should really copy stuff from the extra ROM.
- Ninja Emaki has minor protection issues, see NB1414M4 simulation for more info.
-- dangarj has unemulated protection at I/Os 0x80-1 for missing sprites.
+- dangarj has unemulated protection at I/Os 0x80-1 for missing sprites.
[0x80] W is data
[0x81] W --11 xxxx address
[0x80] R result
The protection is used for a code snippet at 0xf9c0, that of course is the
- sprite handling. The code snippet is sum8 with 0x27 at 0x9d74 so no, the
+ sprite handling. The code snippet is sum8 with 0x27 at 0x9d74 so no, the
later dangar US version snippet doesn't work ...
-
+
***************************************************************************/
#include "emu.h"
@@ -721,7 +721,7 @@ ROM_START( dangarb ) /* all rom labels are simply numbers, with the owl logo and
ROM_REGION( 0x10000, "audiocpu", 0 ) /* sound cpu code */
ROM_LOAD( "13.14b", 0x0000, 0x4000, CRC(3e041873) SHA1(8f9e1ec64509c8a7e9e45add9efc95f98f35fcfc) )
ROM_LOAD( "14.15b", 0x4000, 0x8000, CRC(488e3463) SHA1(73ff7ab061be54162f3a548f6bd9ef55b9dec5d9) )
-
+
ROM_REGION( 0x04000, "gfx1", 0 )
ROM_LOAD( "11.13d", 0x00000, 0x4000, CRC(e804ffe1) SHA1(22f16c23b9a82f104dda24bc8fccc08f3f69cf97) ) /* chars */
@@ -758,7 +758,7 @@ ROM_START( dangarj ) /* all rom labels are simply numbers, with the owl logo and
ROM_REGION( 0x10000, "audiocpu", 0 ) /* sound cpu code */
ROM_LOAD( "21.14b", 0x0000, 0x4000, CRC(3e041873) SHA1(8f9e1ec64509c8a7e9e45add9efc95f98f35fcfc) )
ROM_LOAD( "22.15b", 0x4000, 0x4000, CRC(1d484f68) SHA1(7de13d6c6850280fed011c1d1b211cdc5ea9f935) )
-
+
ROM_REGION( 0x04000, "gfx1", 0 )
ROM_LOAD( "11.13d", 0x00000, 0x4000, CRC(e804ffe1) SHA1(22f16c23b9a82f104dda24bc8fccc08f3f69cf97) ) /* chars */
diff --git a/src/mame/drivers/gba.cpp b/src/mame/drivers/gba.cpp
index 54a2ca5527f..b58253c03b2 100644
--- a/src/mame/drivers/gba.cpp
+++ b/src/mame/drivers/gba.cpp
@@ -2258,8 +2258,8 @@ void gba_state::machine_start()
static SLOT_INTERFACE_START(gba_cart)
SLOT_INTERFACE_INTERNAL("gba_rom", GBA_ROM_STD)
SLOT_INTERFACE_INTERNAL("gba_sram", GBA_ROM_SRAM)
- SLOT_INTERFACE_INTERNAL("gba_drilldoz", GBA_ROM_DRILLDOZ) // Rumble output unemulated
- SLOT_INTERFACE_INTERNAL("gba_wariotws", GBA_ROM_WARIOTWS) // Rumble output unemulated
+ SLOT_INTERFACE_INTERNAL("gba_drilldoz", GBA_ROM_DRILLDOZ) // Rumble output unemulated
+ SLOT_INTERFACE_INTERNAL("gba_wariotws", GBA_ROM_WARIOTWS) // Rumble output unemulated
SLOT_INTERFACE_INTERNAL("gba_eeprom", GBA_ROM_EEPROM)
SLOT_INTERFACE_INTERNAL("gba_eeprom_4k", GBA_ROM_EEPROM)
SLOT_INTERFACE_INTERNAL("gba_yoshiug", GBA_ROM_YOSHIUG)
diff --git a/src/mame/drivers/go2000.cpp b/src/mame/drivers/go2000.cpp
index 90391a01e20..a9d5e47d241 100644
--- a/src/mame/drivers/go2000.cpp
+++ b/src/mame/drivers/go2000.cpp
@@ -62,7 +62,7 @@ public:
required_device<screen_device> m_screen;
required_device<palette_device> m_palette;
required_device<generic_latch_8_device> m_soundlatch;
-
+
DECLARE_WRITE16_MEMBER(sound_cmd_w);
DECLARE_WRITE8_MEMBER(go2000_pcm_1_bankswitch_w);
virtual void machine_start() override;
diff --git a/src/mame/drivers/goldnpkr.cpp b/src/mame/drivers/goldnpkr.cpp
index 860b7dd0a55..51391adfe19 100644
--- a/src/mame/drivers/goldnpkr.cpp
+++ b/src/mame/drivers/goldnpkr.cpp
@@ -4969,7 +4969,7 @@ ROM_END
Golden Poker derivative, with blue killer circuitry.
Suitable for "Good Luck" and "Buena Suerte" games.
Addressing, ROM banks, and edge connector close to Magic Fly.
-
+
Discrete sound need to be traced...
30x2-pins Edge connector + 10-pin connector.
@@ -4983,7 +4983,7 @@ ROM_END
+5V. | 01 | +5V.
(GND) Speaker- | 02 | Speaker- (GND)
| 03 | Speaker+
- | 04 |
+ | 04 |
| |
Sync | 05 | Red
Green | 06 | Blue
@@ -5007,8 +5007,8 @@ ROM_END
Common D (4) | 21 | Common B (2)
| |
| 22 | n/c (5)
- | 23 |
- | 24 |
+ | 23 |
+ | 24 |
| |
GND | 25 | GND
+12VAC. | 26 | +12VAC.
@@ -5020,10 +5020,10 @@ ROM_END
(0) 12V. AV *IN*: for lamps, audio, and mech counters.
- (1) =
- (2) =
- (3) =
- (4) =
+ (1) =
+ (2) =
+ (3) =
+ (4) =
Note: Each Common GND (A-B-C-D) are for their respective
Multiplexed groups of inputs, since there are 4 groups
@@ -5038,10 +5038,10 @@ ROM_END
** 10-pin connector **
Only the last 4 have a male connector. The rest are just marked on the PCB.
-
+
0000000000
++++
- ||||
+ ||||
|||'-- Out Mech Counter.
||'--- Out Mech Counter.
|'---- n/c (is routed to a place where another transistor could be mounted).
diff --git a/src/mame/drivers/goldstar.cpp b/src/mame/drivers/goldstar.cpp
index 724d243e33f..50c05729146 100644
--- a/src/mame/drivers/goldstar.cpp
+++ b/src/mame/drivers/goldstar.cpp
@@ -7455,8 +7455,8 @@ static const gfx_layout cb3c_tiles8x32_layout =
{ 0, 1, 2, 3 },
{ 4, 0, 12, 8, 20, 16, 28, 24 },
{ 0*32, 1*32, 2*32, 3*32, 4*32, 5*32, 6*32, 7*32, 8*32, 9*32, 10*32, 11*32, 12*32,
- 13*32, 14*32, 15*32, 16*32, 17*32, 18*32, 19*32, 20*32, 21*32, 22*32, 23*32,
- 24*32, 25*32, 26*32, 27*32, 28*32, 29*32, 30*32, 31*32 },
+ 13*32, 14*32, 15*32, 16*32, 17*32, 18*32, 19*32, 20*32, 21*32, 22*32, 23*32,
+ 24*32, 25*32, 26*32, 27*32, 28*32, 29*32, 30*32, 31*32 },
32*32
};
@@ -7541,9 +7541,9 @@ static const gfx_layout flaming7_tilelayout =
{ 0, 2, 4, 6 },
{ 2*8+0, 2*8+1, 3*8+0, 3*8+1, 0, 1, 1*8+0, 1*8+1 },
{ 0*8, 4*8, 8*8, 12*8, 16*8, 20*8, 24*8, 28*8,
- 32*8, 36*8, 40*8, 44*8, 48*8, 52*8, 56*8, 60*8,
- 64*8, 68*8, 72*8, 76*8, 80*8, 84*8, 88*8, 92*8,
- 96*8, 100*8, 104*8, 108*8, 112*8, 116*8, 120*8, 124*8 },
+ 32*8, 36*8, 40*8, 44*8, 48*8, 52*8, 56*8, 60*8,
+ 64*8, 68*8, 72*8, 76*8, 80*8, 84*8, 88*8, 92*8,
+ 96*8, 100*8, 104*8, 108*8, 112*8, 116*8, 120*8, 124*8 },
128*8 /* every char takes 128 consecutive bytes */
};
@@ -7566,9 +7566,9 @@ static const gfx_layout flam7_tw_tilelayout = // FIXME
{ 0, 2, 4, 6 },
{ 3*8+0, 3*8+1, 2*8+0, 1*8+0, 1*8+1, 2*8+1, 0, 1 },
{ 0*8, 4*8, 8*8, 12*8, 16*8, 20*8, 24*8, 28*8,
- 32*8, 36*8, 40*8, 44*8, 48*8, 52*8, 56*8, 60*8,
- 64*8, 68*8, 72*8, 76*8, 80*8, 84*8, 88*8, 92*8,
- 96*8, 100*8, 104*8, 108*8, 112*8, 116*8, 120*8, 124*8 },
+ 32*8, 36*8, 40*8, 44*8, 48*8, 52*8, 56*8, 60*8,
+ 64*8, 68*8, 72*8, 76*8, 80*8, 84*8, 88*8, 92*8,
+ 96*8, 100*8, 104*8, 108*8, 112*8, 116*8, 120*8, 124*8 },
128*8 /* every char takes 128 consecutive bytes */
};
@@ -7695,8 +7695,8 @@ static const gfx_layout tiles8x32_4bpp_layout =
{ RGN_FRAC(0,4), RGN_FRAC(1,4), RGN_FRAC(2,4), RGN_FRAC(3,4) },
{ 0, 1, 2, 3, 4, 5, 6, 7},
{ 0*8, 1*8, 2*8, 3*8, 4*8, 5*8, 6*8, 7*8, 8*8, 9*8, 10*8, 11*8, 12*8,
- 13*8, 14*8, 15*8, 16*8, 17*8, 18*8, 19*8, 20*8, 21*8, 22*8, 23*8,
- 24*8, 25*8, 26*8, 27*8, 28*8, 29*8, 30*8, 31*8 },
+ 13*8, 14*8, 15*8, 16*8, 17*8, 18*8, 19*8, 20*8, 21*8, 22*8, 23*8,
+ 24*8, 25*8, 26*8, 27*8, 28*8, 29*8, 30*8, 31*8 },
32*8
};
@@ -7812,8 +7812,8 @@ static const gfx_layout cm97_layout32 =
{ 0,1,2,3 },
{ 8,12,0,4,24,28, 16,20 },
{ 0*32, 1*32, 2*32, 3*32, 4*32, 5*32, 6*32, 7*32, 8*32, 9*32, 10*32, 11*32,
- 12*32, 13*32, 14*32, 15*32, 16*32, 17*32, 18*32, 19*32, 20*32, 21*32,
- 22*32, 23*32, 24*32, 25*32, 26*32, 27*32, 28*32, 29*32, 30*32, 31*32 },
+ 12*32, 13*32, 14*32, 15*32, 16*32, 17*32, 18*32, 19*32, 20*32, 21*32,
+ 22*32, 23*32, 24*32, 25*32, 26*32, 27*32, 28*32, 29*32, 30*32, 31*32 },
32*32
};
@@ -8419,7 +8419,7 @@ static MACHINE_CONFIG_DERIVED( flaming7, lucky8 )
MCFG_GFXDECODE_MODIFY("gfxdecode", flaming7)
- // to do serial protection.
+ // to do serial protection.
MCFG_DEVICE_MODIFY("ppi8255_0")
MCFG_I8255_OUT_PORTC_CB(WRITE8(wingco_state, fl7w4_outc802_w))
@@ -8433,7 +8433,7 @@ static MACHINE_CONFIG_DERIVED( flam7_tw, lucky8 )
MCFG_GFXDECODE_MODIFY("gfxdecode", flam7_tw)
- // to do serial protection.
+ // to do serial protection.
MCFG_DEVICE_MODIFY("ppi8255_0")
MCFG_I8255_OUT_PORTC_CB(WRITE8(wingco_state, fl7w4_outc802_w))
@@ -14308,7 +14308,7 @@ ROM_END
Graphics: 4 different types, selectable through DIP switches.
1) Regular Fruits.
- 2) Numbers. (Custom Option 1 in W-4 HW)
+ 2) Numbers. (Custom Option 1 in W-4 HW)
3) Custom Set 1 (Custom Option 2 in W-4 HW)
4) Custom Set 2 (Custom Option 3 in W-4 HW)
@@ -14455,7 +14455,7 @@ ROM_END
| PAPER LOW SENSOR | OFF | | | | | OFF | OFF | OFF | OFF |
| | ON | | | | | ON | OFF | OFF | OFF |
+------------------+----------------+-----+-----+-----+-----+-----+-----+-----+-----+
-
+
NOTE: Set bill validator DIP switches for 1 pulse per dollar. When you choose the
demonation with the DIP switch on the board, the software will know how many
@@ -14567,15 +14567,15 @@ ROM_END
Button Lock |15|51|
|16|52|
|17|53|
- (DBA) Inuput0 |18|54| Coin Switch “Aâ€
- Coin Switch “B†|19|55|
+ (DBA) Inuput0 |18|54| Coin Switch "A"
+ Coin Switch "B" |19|55|
Book Keeping Switch |20|56| Stats / Setup SW
Collect SW |21|57|
Hopper Full Switch |22|58|
- Counter Out “A†|23|59|
+ Counter Out "A" |23|59|
Bell |24|60| Lockout mars (DBA)
Tower Lamp |25|61|
- Counter Out “D†|26|62|
+ Counter Out "D" |26|62|
Played Meter |27|63| Lack of Hopper Counter
Count down Meter Out |28|64|
Start Lamp |29|65|
@@ -14641,10 +14641,10 @@ ROM_END
2) Pin 39 from solder side (speaker GND) and pin 04 from components side (PPI 8255 pin 11, PC6)
are wired with a DS2401 (sillicon serial number) device, to pins 1 & 2 (GND & DATA).
-
- DS2401 has 64bits of internal data: 8 bits for family type + 48 bits for serial + 8 bits for CRC.
- Maxim/Dallas 1-Wire devices use what is called Dow CRC to check that the data bytes were received correctly.
+ DS2401 has 64bits of internal data: 8 bits for family type + 48 bits for serial + 8 bits for CRC.
+
+ Maxim/Dallas 1-Wire devices use what is called Dow CRC to check that the data bytes were received correctly.
This returns an 8-bit CRC value as the last byte and uses a polynomial of X^8 + X^5 + X^4 + X^0.
3) Z80 /INT line (pin 16) is out of socket and wired to a 74161.
@@ -14658,9 +14658,9 @@ ROM_END
Seems that there is an extra layer for the bonus graphics.
This graphic is taken from Bank 2, and is the "representative"
for the chosen gfx set.
-
+
Code writes the bonus graphics at 9A80-9A89, and the "reel scroll"
- at B0C0-B0FF...
+ at B0C0-B0FF...
Tileset:
Reels GFX 1: 00-00-01-02-03-04-05-06-07-00
@@ -14730,7 +14730,7 @@ ROM_END
Main - 50.
Custom Hardware.
-*/
+*/
ROM_START( fl7_50 ) // Serial 00000069A1C9.
ROM_REGION( 0x8000, "maincpu", 0 )
ROM_LOAD( "50-main.u22", 0x0000, 0x8000, CRC(e097e317) SHA1(a903144cc2290b7e22045490784b592adbf9ba97) )
@@ -14762,7 +14762,7 @@ ROM_END
Main - 500.
Custom Hardware.
-*/
+*/
ROM_START( fl7_500 ) // Serial 000000125873.
ROM_REGION( 0x8000, "maincpu", 0 )
ROM_LOAD( "500-main.u22", 0x0000, 0x8000, CRC(e2c82c67) SHA1(951b0044de9b6104f51aa5a3176d0ea475415f7c) )
@@ -14794,7 +14794,7 @@ ROM_END
Main - 2000.
Custom Hardware.
-*/
+*/
ROM_START( fl7_2000 ) // Serial 00000063A47F.
ROM_REGION( 0x8000, "maincpu", 0 )
ROM_LOAD( "2000_main_27c256.u22", 0x0000, 0x8000, CRC(9659b045) SHA1(801b6733b70b35de65cd8faba6814fa013c05ad0) )
@@ -14826,7 +14826,7 @@ ROM_END
2000 Bonus. Egyptian Gold.
Custom Hardware.
-*/
+*/
ROM_START( fl7_2k16 ) // Serial 000000743111.
ROM_REGION( 0x8000, "maincpu", 0 )
ROM_LOAD( "2000_bonus_27c256.u22", 0x0000, 0x8000, CRC(290c37b0) SHA1(a90093d2139fd5ca261870298c2d84648f14e6bc) )
@@ -14857,7 +14857,7 @@ ROM_END
Needs proper graphics ROM decryption and gfxdecode...
-*/
+*/
ROM_START( fl7_tw ) // Serial 00000050E9B7.
ROM_REGION( 0x10000, "maincpu", 0 )
ROM_LOAD( "27c512_tw.u20", 0x0000, 0x10000, CRC(50927a1b) SHA1(2557069f497b23f13978294f3ac108229d9db544) ) // identical halves.
@@ -15532,7 +15532,7 @@ DRIVER_INIT_MEMBER(goldstar_state, wcherry)
/*
Flaming 7's
Cyberdyne Systems.
-
+
Original custom hardware graphics decryption.
*/
@@ -15557,7 +15557,7 @@ DRIVER_INIT_MEMBER(wingco_state, flaming7)
/*
Flaming 7's
Cyberdyne Systems.
-
+
Taiwanese custom hardware.
*/
diff --git a/src/mame/drivers/halleys.cpp b/src/mame/drivers/halleys.cpp
index b3e99df85f6..77ed4220bc6 100644
--- a/src/mame/drivers/halleys.cpp
+++ b/src/mame/drivers/halleys.cpp
@@ -515,7 +515,7 @@ if (0) {
{
if (!(flags & IGNORE_0)) BLOCK_WIPE_COMMON
- dst_ptr += wclip;
+ dst_ptr += wclip;
ecx = wclip = -wclip;
edx = src_dx;
@@ -539,7 +539,7 @@ if (0) {
while (--hclip);
}
else
- {
+ {
do {
do {
al |= *src1_ptr;
@@ -605,7 +605,7 @@ if (0) {
if ((flags & (RGB_MASK | COLOR_ON)) == RGB_MASK + COLOR_ON)
{
if (!(flags & IGNORE_0)) BLOCK_WIPE_COMMON
- dst_ptr += wclip;
+ dst_ptr += wclip;
ecx = wclip = -wclip;
al = ah = (UINT8)pen0;
ebx = rgbmask[color & PENCOLOR] | 0xffffff00;
@@ -708,7 +708,7 @@ if (0) {
//--------------------------------------------------------------------------
- // End of Standard Mode
+ // End of Standard Mode
return;
//--------------------------------------------------------------------------
diff --git a/src/mame/drivers/hh_cop400.cpp b/src/mame/drivers/hh_cop400.cpp
index 2cfa00446c6..6de25264e24 100644
--- a/src/mame/drivers/hh_cop400.cpp
+++ b/src/mame/drivers/hh_cop400.cpp
@@ -999,7 +999,7 @@ MACHINE_CONFIG_END
Milton Bradley Electronic Battleship (1982 version)
* COP420 MCU label COP420-JWE/N
-
+
see hh_tms1k.cpp bship driver for more information
***************************************************************************/
diff --git a/src/mame/drivers/hh_tms1k.cpp b/src/mame/drivers/hh_tms1k.cpp
index cc0b1d20468..e938077bd29 100644
--- a/src/mame/drivers/hh_tms1k.cpp
+++ b/src/mame/drivers/hh_tms1k.cpp
@@ -3722,7 +3722,7 @@ MACHINE_CONFIG_END
This is a 2-player electronic board game. It still needs game pieces like the
original Battleship board game.
-
+
It went through 3 hardware revisions:
1977: model 4750A or B, see notes above
1979: model 4750C: cost-reduced single chip design, lesser quality game board.
@@ -5759,10 +5759,10 @@ MACHINE_CONFIG_END
U.S. Games Super Sports-4
* TMS1100 MP1219 (no decap)
* 4 7seg LEDs, 49 other LEDs, 1-bit sound
-
+
This handheld includes 4 games: Basketball, Football, Soccer, Hockey.
MAME external artwork is needed for the switchable overlays.
-
+
The later Coleco Total Control 4 is clearly based on this.
***************************************************************************/
@@ -5786,7 +5786,7 @@ void ssports4_state::prepare_display()
{
// R0,R1 and R8,R9 are 7segs
set_display_segmask(0x303, 0x7f);
-
+
// note: R2 is an extra column
display_matrix(9, 10, m_o | (m_r << 6 & 0x100), m_r);
}
@@ -5795,7 +5795,7 @@ WRITE16_MEMBER(ssports4_state::write_r)
{
// R10: speaker out
m_speaker->level_w(data >> 10 & 1);
-
+
// R0-R9: led select/data
m_r = data;
prepare_display();
diff --git a/src/mame/drivers/holeland.cpp b/src/mame/drivers/holeland.cpp
index d6f173e6948..54f19c3f6ed 100644
--- a/src/mame/drivers/holeland.cpp
+++ b/src/mame/drivers/holeland.cpp
@@ -124,12 +124,12 @@ static INPUT_PORTS_START( holeland )
INPUT_PORTS_END
static INPUT_PORTS_START( holeland2 )
- PORT_INCLUDE( holeland )
+ PORT_INCLUDE( holeland )
- PORT_MODIFY("DSW1")
- PORT_DIPNAME( 0x04, 0x04, DEF_STR( Language ) )
+ PORT_MODIFY("DSW1")
+ PORT_DIPNAME( 0x04, 0x04, DEF_STR( Language ) )
PORT_DIPSETTING( 0x00, DEF_STR( English ) )
- PORT_DIPSETTING( 0x04, DEF_STR( Spanish ) )
+ PORT_DIPSETTING( 0x04, DEF_STR( Spanish ) )
INPUT_PORTS_END
static INPUT_PORTS_START( crzrally )
diff --git a/src/mame/drivers/homedata.cpp b/src/mame/drivers/homedata.cpp
index e5153d72ca9..716a5b0f0aa 100644
--- a/src/mame/drivers/homedata.cpp
+++ b/src/mame/drivers/homedata.cpp
@@ -156,7 +156,7 @@ Board: X73-PWB-A(C)
CPU: 6809 uPC324C
Sound: SN76489
OSC: 16.000MHz 9.000MHz
-ROM: 28 pin mask rom devices are 1mbit, 32 pin are 2mbit.
+ROM: 28 pin mask rom devices are 1mbit, 32 pin are 2mbit.
----------------------------------------------------------------------------
Mahjong Vitamin C
@@ -971,33 +971,33 @@ INPUT_PORTS_END
static INPUT_PORTS_START( mjjoship )
PORT_INCLUDE( pteacher )
-
+
PORT_MODIFY("DSW")
// SW1
- PORT_DIPNAME( 0x0001, 0x0000, "Attract Sound" ) PORT_DIPLOCATION("SW1:1")
- PORT_DIPSETTING( 0x0001, DEF_STR( Off ) )
- PORT_DIPSETTING( 0x0000, DEF_STR( On ) )
+ PORT_DIPNAME( 0x0001, 0x0000, "Attract Sound" ) PORT_DIPLOCATION("SW1:1")
+ PORT_DIPSETTING( 0x0001, DEF_STR( Off ) )
+ PORT_DIPSETTING( 0x0000, DEF_STR( On ) )
PORT_DIPUNKNOWN_DIPLOC( 0x0002, 0x0002, "SW1:2" )
PORT_DIPUNKNOWN_DIPLOC( 0x0004, 0x0004, "SW1:3" )
PORT_DIPUNKNOWN_DIPLOC( 0x0008, 0x0008, "SW1:4" )
- PORT_DIPNAME( 0x0010, 0x0010, "Player Start Score" ) PORT_DIPLOCATION("SW1:5")
- PORT_DIPSETTING( 0x0010, "1000" )
- PORT_DIPSETTING( 0x0000, "2000" )
+ PORT_DIPNAME( 0x0010, 0x0010, "Player Start Score" ) PORT_DIPLOCATION("SW1:5")
+ PORT_DIPSETTING( 0x0010, "1000" )
+ PORT_DIPSETTING( 0x0000, "2000" )
PORT_DIPUNKNOWN_DIPLOC( 0x0020, 0x0020, "SW1:6" )
PORT_DIPUNKNOWN_DIPLOC( 0x0040, 0x0040, "SW1:7" )
- PORT_DIPNAME( 0x0080, 0x0080, DEF_STR( Flip_Screen ) ) PORT_DIPLOCATION("SW1:8")
- PORT_DIPSETTING( 0x0080, DEF_STR( Off ) )
- PORT_DIPSETTING( 0x0000, DEF_STR( On ) )
-
+ PORT_DIPNAME( 0x0080, 0x0080, DEF_STR( Flip_Screen ) ) PORT_DIPLOCATION("SW1:8")
+ PORT_DIPSETTING( 0x0080, DEF_STR( Off ) )
+ PORT_DIPSETTING( 0x0000, DEF_STR( On ) )
+
// SW2
- PORT_DIPUNKNOWN_DIPLOC( 0x0100, 0x0100, "SW2:1" )
- PORT_DIPUNKNOWN_DIPLOC( 0x0200, 0x0200, "SW2:2" )
+ PORT_DIPUNKNOWN_DIPLOC( 0x0100, 0x0100, "SW2:1" )
+ PORT_DIPUNKNOWN_DIPLOC( 0x0200, 0x0200, "SW2:2" )
PORT_DIPUNKNOWN_DIPLOC( 0x0400, 0x0400, "SW2:3" )
- PORT_DIPUNKNOWN_DIPLOC( 0x0800, 0x0800, "SW2:4" )
+ PORT_DIPUNKNOWN_DIPLOC( 0x0800, 0x0800, "SW2:4" )
PORT_DIPUNKNOWN_DIPLOC( 0x1000, 0x1000, "SW2:5" )
- PORT_DIPUNKNOWN_DIPLOC( 0x2000, 0x2000, "SW2:6" )
+ PORT_DIPUNKNOWN_DIPLOC( 0x2000, 0x2000, "SW2:6" )
PORT_DIPUNKNOWN_DIPLOC( 0x4000, 0x4000, "SW2:7" )
- PORT_DIPUNKNOWN_DIPLOC( 0x8000, 0x8000, "SW2:8" )
+ PORT_DIPUNKNOWN_DIPLOC( 0x8000, 0x8000, "SW2:8" )
INPUT_PORTS_END
@@ -1824,35 +1824,35 @@ ROM_START( mjkojink )
ROM_END
ROM_START( mjjoship )
- ROM_REGION( 0x01c000, "maincpu", 0 ) /* 6809 Code */
- ROM_LOAD( "X73_L01.16E", 0x010000, 0xc000, CRC(df950025) SHA1(3dc22c0a8cf03cff7310fbff36f83804019a5337) )
- ROM_CONTINUE( 0x00c000, 0x4000 )
+ ROM_REGION( 0x01c000, "maincpu", 0 ) /* 6809 Code */
+ ROM_LOAD( "X73_L01.16E", 0x010000, 0xc000, CRC(df950025) SHA1(3dc22c0a8cf03cff7310fbff36f83804019a5337) )
+ ROM_CONTINUE( 0x00c000, 0x4000 )
- ROM_REGION( 0x40000, "audiocpu", 0) /* uPD7807 code */
- ROM_LOAD( "X73_B02.9G", 0x00000, 0x20000, CRC(6b01503b) SHA1(2e1575dac0b9b7c7233a3b8262a99a10e24ec813) )
+ ROM_REGION( 0x40000, "audiocpu", 0) /* uPD7807 code */
+ ROM_LOAD( "X73_B02.9G", 0x00000, 0x20000, CRC(6b01503b) SHA1(2e1575dac0b9b7c7233a3b8262a99a10e24ec813) )
ROM_RELOAD( 0x20000, 0x20000 )
- ROM_REGION( 0x80000, "gfx1", 0 )
- ROM_LOAD32_BYTE( "X73A14.1F", 0, 0x20000, CRC(42f429a5) SHA1(41f64258a65b56f818f8a6ecddab606d0bdc11ab) )
- ROM_LOAD32_BYTE( "X73A15.3F", 1, 0x20000, CRC(2d827236) SHA1(d392dc64f136fd2ef19a2874758ad7804741882a) )
+ ROM_REGION( 0x80000, "gfx1", 0 )
+ ROM_LOAD32_BYTE( "X73A14.1F", 0, 0x20000, CRC(42f429a5) SHA1(41f64258a65b56f818f8a6ecddab606d0bdc11ab) )
+ ROM_LOAD32_BYTE( "X73A15.3F", 1, 0x20000, CRC(2d827236) SHA1(d392dc64f136fd2ef19a2874758ad7804741882a) )
ROM_IGNORE( 0x20000 )
- ROM_LOAD32_BYTE( "X73A16.4F", 2, 0x20000, CRC(c606cd02) SHA1(d316f11ad56359c8ae74858a84b373dd06934888) )
+ ROM_LOAD32_BYTE( "X73A16.4F", 2, 0x20000, CRC(c606cd02) SHA1(d316f11ad56359c8ae74858a84b373dd06934888) )
ROM_IGNORE( 0x20000 )
- ROM_LOAD32_BYTE( "X73A17.6F", 3, 0x20000, CRC(2c0fdbc9) SHA1(3ae5b590db4705deeaeff93680a10ca980e6264f) )
+ ROM_LOAD32_BYTE( "X73A17.6F", 3, 0x20000, CRC(2c0fdbc9) SHA1(3ae5b590db4705deeaeff93680a10ca980e6264f) )
ROM_IGNORE( 0x20000 )
- ROM_REGION( 0x100000, "gfx2", 0 )
- ROM_LOAD32_BYTE( "X73A10.1C", 0, 0x40000, CRC(e6663a99) SHA1(361503c16e32977c8f6b9c5ff981002ac0f97426) )
- ROM_LOAD32_BYTE( "X73A11.3C", 1, 0x40000, CRC(d8a35ebe) SHA1(b6e12db38ddd6dcefa8335b92c0a6e269a6a1e9a) )
- ROM_LOAD32_BYTE( "X73A12.4C", 2, 0x40000, CRC(f3b6ad98) SHA1(d91eeffd18684300809c99fa93d4ac0188530ff7) )
- ROM_LOAD32_BYTE( "X73A13.6C", 3, 0x40000, CRC(30ff8c5f) SHA1(e51d89f6b5db0d8e2c22a046337993f962f6ba8c) )
+ ROM_REGION( 0x100000, "gfx2", 0 )
+ ROM_LOAD32_BYTE( "X73A10.1C", 0, 0x40000, CRC(e6663a99) SHA1(361503c16e32977c8f6b9c5ff981002ac0f97426) )
+ ROM_LOAD32_BYTE( "X73A11.3C", 1, 0x40000, CRC(d8a35ebe) SHA1(b6e12db38ddd6dcefa8335b92c0a6e269a6a1e9a) )
+ ROM_LOAD32_BYTE( "X73A12.4C", 2, 0x40000, CRC(f3b6ad98) SHA1(d91eeffd18684300809c99fa93d4ac0188530ff7) )
+ ROM_LOAD32_BYTE( "X73A13.6C", 3, 0x40000, CRC(30ff8c5f) SHA1(e51d89f6b5db0d8e2c22a046337993f962f6ba8c) )
- ROM_REGION( 0x010000, "proms", 0 ) /* static palette */
- ROM_LOAD16_BYTE( "X73_C19.4K", 0x00000, 0x8000, CRC(f4bdce8a) SHA1(e3168d6aa6f8cd24b497706a117c77353d1c6ef3) )
- ROM_LOAD16_BYTE( "X73_C18.3K", 0x00001, 0x8000, CRC(1ab265cc) SHA1(24dced438a28ea9eb2f06c8859c5c07f4d975bfd) )
+ ROM_REGION( 0x010000, "proms", 0 ) /* static palette */
+ ROM_LOAD16_BYTE( "X73_C19.4K", 0x00000, 0x8000, CRC(f4bdce8a) SHA1(e3168d6aa6f8cd24b497706a117c77353d1c6ef3) )
+ ROM_LOAD16_BYTE( "X73_C18.3K", 0x00001, 0x8000, CRC(1ab265cc) SHA1(24dced438a28ea9eb2f06c8859c5c07f4d975bfd) )
- ROM_REGION( 0x20000, "user1", 0 ) /* blitter data */
- ROM_LOAD( "X73A03.12E", 0x0000, 0x20000, CRC(fd32eb8c) SHA1(584afb1ed2da776a4ff9c0b9eb2906c914b28928) )
+ ROM_REGION( 0x20000, "user1", 0 ) /* blitter data */
+ ROM_LOAD( "X73A03.12E", 0x0000, 0x20000, CRC(fd32eb8c) SHA1(584afb1ed2da776a4ff9c0b9eb2906c914b28928) )
ROM_END
diff --git a/src/mame/drivers/kickgoal.cpp b/src/mame/drivers/kickgoal.cpp
index f1f84912c10..587c2786b73 100644
--- a/src/mame/drivers/kickgoal.cpp
+++ b/src/mame/drivers/kickgoal.cpp
@@ -480,7 +480,7 @@ static ADDRESS_MAP_START( kickgoal_program_map, AS_PROGRAM, 16, kickgoal_state )
/// AM_RANGE(0x30001e, 0x30001f) AM_WRITE(kickgoal_snd_w)
AM_RANGE(0x800000, 0x800001) AM_READ_PORT("P1_P2")
AM_RANGE(0x800002, 0x800003) AM_READ_PORT("SYSTEM")
-/// AM_RANGE(0x800004, 0x800005) AM_DEVWRITE("soundlatch", generic_latch_16_device, write)
+/// AM_RANGE(0x800004, 0x800005) AM_DEVWRITE("soundlatch", generic_latch_16_device, write)
AM_RANGE(0x800004, 0x800005) AM_WRITE(actionhw_snd_w)
AM_RANGE(0x900000, 0x900005) AM_WRITE(kickgoal_eeprom_w)
AM_RANGE(0x900006, 0x900007) AM_READ(kickgoal_eeprom_r)
diff --git a/src/mame/drivers/leland.cpp b/src/mame/drivers/leland.cpp
index a7f2bd3316a..aa59e32d783 100644
--- a/src/mame/drivers/leland.cpp
+++ b/src/mame/drivers/leland.cpp
@@ -3027,4 +3027,3 @@ GAME( 1990, wsf, 0, wsf, wsf, leland_state, wsf, ROT0,
GAME( 1991, indyheat, 0, wsf, indyheat, leland_state, indyheat, ROT0, "Leland Corp.", "Danny Sullivan's Indy Heat", 0 )
GAME( 1991, brutforc, 0, wsf, brutforc, leland_state, brutforc, ROT0, "Leland Corp.", "Brute Force", 0 )
GAME( 1991, asylum, 0, wsf, brutforc, leland_state, asylum, ROT270, "Leland Corp.", "Asylum (prototype)", 0 )
-
diff --git a/src/mame/drivers/lgp.cpp b/src/mame/drivers/lgp.cpp
index 82fa4de476c..85edb077992 100644
--- a/src/mame/drivers/lgp.cpp
+++ b/src/mame/drivers/lgp.cpp
@@ -365,7 +365,7 @@ PALETTE_INIT_MEMBER(lgp_state, lgp)
const UINT8 *color_prom = memregion("proms")->base();
int i;
-// for (i = 0; i < palette.entries(); i++)
+// for (i = 0; i < palette.entries(); i++)
for (i = 0; i < 0x20; i++)
{
int r,g,b;
@@ -388,8 +388,8 @@ PALETTE_INIT_MEMBER(lgp_state, lgp)
bit1 = (color_prom[i] >> 4) & 0x01;
bit2 = (color_prom[i] >> 5) & 0x01;
b = 0x21 * bit0 + 0x47 * bit1 + 0x97 * bit2;
-
-
+
+
palette.set_pen_color(i,rgb_t(r,g,b));
}
@@ -513,7 +513,7 @@ ROM_START( lgp )
ROM_LOAD( "a02_39.109", 0x00300, 0x100, CRC(88363809) SHA1(b22a7bd8ce6b28bf7cfa64c3a08e4cf7f9b4cd20) )
ROM_LOAD( "a02_40.110", 0x00400, 0x100, CRC(fdfc7aac) SHA1(2413f7f9ad11c91d2adc0aab37bf70ff5c68ab6f) )
-
+
DISK_REGION( "laserdisc" )
DISK_IMAGE_READONLY( "lgp", 0, NO_DUMP )
ROM_END
diff --git a/src/mame/drivers/m63.cpp b/src/mame/drivers/m63.cpp
index 2e70f38c2a7..e91548c117e 100644
--- a/src/mame/drivers/m63.cpp
+++ b/src/mame/drivers/m63.cpp
@@ -176,7 +176,7 @@ public:
required_device<cpu_device> m_soundcpu;
optional_device<samples_device> m_samples;
required_device<generic_latch_8_device> m_soundlatch;
-
+
DECLARE_WRITE8_MEMBER(m63_videoram_w);
DECLARE_WRITE8_MEMBER(m63_colorram_w);
DECLARE_WRITE8_MEMBER(m63_videoram2_w);
diff --git a/src/mame/drivers/magicfly.cpp b/src/mame/drivers/magicfly.cpp
index 4dec074f4ed..1e4cc8dfbc7 100644
--- a/src/mame/drivers/magicfly.cpp
+++ b/src/mame/drivers/magicfly.cpp
@@ -163,8 +163,8 @@
(4) = Coin 1, Coin 2, Coupon.
Note: Each Common GND (A-B-C-D) are for their respective
- multiplexed groups of inputs, since there are 4 groups
- with 5 valid inputs each one.
+ multiplexed groups of inputs, since there are 4 groups
+ with 5 valid inputs each one.
**** 10-Pins connector ****
diff --git a/src/mame/drivers/megasys1.cpp b/src/mame/drivers/megasys1.cpp
index b30064e9ca2..9cd36745da0 100644
--- a/src/mame/drivers/megasys1.cpp
+++ b/src/mame/drivers/megasys1.cpp
@@ -925,53 +925,53 @@ INPUT_PORTS_END
static INPUT_PORTS_START( edfp )
PORT_INCLUDE( megasys1_generic )
- PORT_START("DSW")
- PORT_DIPNAME( 0x0007, 0x0007, "DSW bits 2-0" )
- PORT_DIPSETTING( 0x0000, "0" )
- PORT_DIPSETTING( 0x0001, "1" )
- PORT_DIPSETTING( 0x0002, "2" )
- PORT_DIPSETTING( 0x0003, "3" )
- PORT_DIPSETTING( 0x0004, "4" )
- PORT_DIPSETTING( 0x0005, "5" )
- PORT_DIPSETTING( 0x0006, "6" )
- PORT_DIPSETTING( 0x0007, "7" )
- PORT_DIPNAME( 0x0008, 0x0008, DEF_STR( Lives ) )
- PORT_DIPSETTING( 0x0008, "3" )
- PORT_DIPSETTING( 0x0000, "4" )
- PORT_DIPNAME( 0x0030, 0x0030, DEF_STR( Difficulty ) )
- PORT_DIPSETTING( 0x0000, DEF_STR( Easy ) )
- PORT_DIPSETTING( 0x0030, DEF_STR( Normal ) )
- PORT_DIPSETTING( 0x0010, DEF_STR( Hard ) )
- PORT_DIPSETTING( 0x0020, DEF_STR( Very_Hard ) )
- PORT_DIPNAME( 0x0040, 0x0040, DEF_STR( Unknown ) )
- PORT_DIPSETTING( 0x0040, DEF_STR( Off ) )
- PORT_DIPSETTING( 0x0000, DEF_STR( On ) )
- PORT_DIPNAME( 0x0080, 0x0080, DEF_STR( Flip_Screen ) )
- PORT_DIPSETTING( 0x0080, DEF_STR( Off ) )
- PORT_DIPSETTING( 0x0000, DEF_STR( On ) )
-
- PORT_DIPNAME( 0x0700, 0x0700, DEF_STR( Coin_A ) )
- PORT_DIPSETTING( 0x0400, DEF_STR( 3C_1C ) )
- PORT_DIPSETTING( 0x0200, DEF_STR( 2C_1C ) )
- PORT_DIPSETTING( 0x0700, DEF_STR( 1C_1C ) )
- PORT_DIPSETTING( 0x0300, DEF_STR( 1C_2C ) )
- PORT_DIPSETTING( 0x0500, DEF_STR( 1C_3C ) )
- PORT_DIPSETTING( 0x0100, DEF_STR( 1C_4C ) )
- PORT_DIPSETTING( 0x0600, DEF_STR( 1C_5C ) )
- PORT_DIPSETTING( 0x0000, DEF_STR( Free_Play ) )
- PORT_DIPNAME( 0x3800, 0x3800, DEF_STR( Coin_B ) )
- PORT_DIPSETTING( 0x0000, DEF_STR( 4C_1C ) )
- PORT_DIPSETTING( 0x2000, DEF_STR( 3C_1C ) )
- PORT_DIPSETTING( 0x1000, DEF_STR( 2C_1C ) )
- PORT_DIPSETTING( 0x3800, DEF_STR( 1C_1C ) )
- PORT_DIPSETTING( 0x1800, DEF_STR( 1C_2C ) )
- PORT_DIPSETTING( 0x2800, DEF_STR( 1C_3C ) )
- PORT_DIPSETTING( 0x0800, DEF_STR( 1C_4C ) )
- PORT_DIPSETTING( 0x3000, DEF_STR( 1C_5C ) )
- PORT_DIPNAME( 0x4000, 0x4000, DEF_STR( Demo_Sounds ) )
- PORT_DIPSETTING( 0x0000, DEF_STR( Off ) )
- PORT_DIPSETTING( 0x4000, DEF_STR( On ) )
- PORT_SERVICE( 0x8000, IP_ACTIVE_LOW )
+ PORT_START("DSW")
+ PORT_DIPNAME( 0x0007, 0x0007, "DSW bits 2-0" )
+ PORT_DIPSETTING( 0x0000, "0" )
+ PORT_DIPSETTING( 0x0001, "1" )
+ PORT_DIPSETTING( 0x0002, "2" )
+ PORT_DIPSETTING( 0x0003, "3" )
+ PORT_DIPSETTING( 0x0004, "4" )
+ PORT_DIPSETTING( 0x0005, "5" )
+ PORT_DIPSETTING( 0x0006, "6" )
+ PORT_DIPSETTING( 0x0007, "7" )
+ PORT_DIPNAME( 0x0008, 0x0008, DEF_STR( Lives ) )
+ PORT_DIPSETTING( 0x0008, "3" )
+ PORT_DIPSETTING( 0x0000, "4" )
+ PORT_DIPNAME( 0x0030, 0x0030, DEF_STR( Difficulty ) )
+ PORT_DIPSETTING( 0x0000, DEF_STR( Easy ) )
+ PORT_DIPSETTING( 0x0030, DEF_STR( Normal ) )
+ PORT_DIPSETTING( 0x0010, DEF_STR( Hard ) )
+ PORT_DIPSETTING( 0x0020, DEF_STR( Very_Hard ) )
+ PORT_DIPNAME( 0x0040, 0x0040, DEF_STR( Unknown ) )
+ PORT_DIPSETTING( 0x0040, DEF_STR( Off ) )
+ PORT_DIPSETTING( 0x0000, DEF_STR( On ) )
+ PORT_DIPNAME( 0x0080, 0x0080, DEF_STR( Flip_Screen ) )
+ PORT_DIPSETTING( 0x0080, DEF_STR( Off ) )
+ PORT_DIPSETTING( 0x0000, DEF_STR( On ) )
+
+ PORT_DIPNAME( 0x0700, 0x0700, DEF_STR( Coin_A ) )
+ PORT_DIPSETTING( 0x0400, DEF_STR( 3C_1C ) )
+ PORT_DIPSETTING( 0x0200, DEF_STR( 2C_1C ) )
+ PORT_DIPSETTING( 0x0700, DEF_STR( 1C_1C ) )
+ PORT_DIPSETTING( 0x0300, DEF_STR( 1C_2C ) )
+ PORT_DIPSETTING( 0x0500, DEF_STR( 1C_3C ) )
+ PORT_DIPSETTING( 0x0100, DEF_STR( 1C_4C ) )
+ PORT_DIPSETTING( 0x0600, DEF_STR( 1C_5C ) )
+ PORT_DIPSETTING( 0x0000, DEF_STR( Free_Play ) )
+ PORT_DIPNAME( 0x3800, 0x3800, DEF_STR( Coin_B ) )
+ PORT_DIPSETTING( 0x0000, DEF_STR( 4C_1C ) )
+ PORT_DIPSETTING( 0x2000, DEF_STR( 3C_1C ) )
+ PORT_DIPSETTING( 0x1000, DEF_STR( 2C_1C ) )
+ PORT_DIPSETTING( 0x3800, DEF_STR( 1C_1C ) )
+ PORT_DIPSETTING( 0x1800, DEF_STR( 1C_2C ) )
+ PORT_DIPSETTING( 0x2800, DEF_STR( 1C_3C ) )
+ PORT_DIPSETTING( 0x0800, DEF_STR( 1C_4C ) )
+ PORT_DIPSETTING( 0x3000, DEF_STR( 1C_5C ) )
+ PORT_DIPNAME( 0x4000, 0x4000, DEF_STR( Demo_Sounds ) )
+ PORT_DIPSETTING( 0x0000, DEF_STR( Off ) )
+ PORT_DIPSETTING( 0x4000, DEF_STR( On ) )
+ PORT_SERVICE( 0x8000, IP_ACTIVE_LOW )
INPUT_PORTS_END
@@ -2570,7 +2570,7 @@ ROM_END
/*
EDF (Prototype)
-
+
Main Board: MB-8842 (System-A)
ROM Board: MB8845 (with D6500SCW-362 custom)
*/
@@ -2578,43 +2578,43 @@ ROM_START( edfp )
ROM_REGION( 0xc0000, "maincpu", 0 ) /* Main CPU Code */
ROM_LOAD16_BYTE( "2.ROM2.27C010", 0x000000, 0x020000, CRC(358a6ac3) SHA1(b7beaadd2e934071e6bc9cafdaa9cc5a1241488a) )
ROM_LOAD16_BYTE( "1.ROM1.27C010", 0x000001, 0x020000, CRC(f30cfb25) SHA1(38020aa62e61f15dbd4267293bd4b8df356ed16e) )
- ROM_LOAD16_BYTE( "4.ROM4.27512", 0x040001, 0x010000, CRC(41e1a014) SHA1(8d40353228114c762fe58c525162f35aa71ef21b) )
- ROM_LOAD16_BYTE( "3.ROM3.27512", 0x040000, 0x010000, CRC(f0357ba2) SHA1(e4ff21d5149ae7d0b259238c18edb193eb94be5e) )
+ ROM_LOAD16_BYTE( "4.ROM4.27512", 0x040001, 0x010000, CRC(41e1a014) SHA1(8d40353228114c762fe58c525162f35aa71ef21b) )
+ ROM_LOAD16_BYTE( "3.ROM3.27512", 0x040000, 0x010000, CRC(f0357ba2) SHA1(e4ff21d5149ae7d0b259238c18edb193eb94be5e) )
ROM_REGION( 0x40000, "audiocpu", 0 ) /* Sound CPU Code */
- ROM_LOAD16_BYTE( "5.ROM5.27512", 0x000000, 0x010000, CRC(505d09ff) SHA1(681579123257548f71ebb9d591c4db81fc52ff85) )
- ROM_LOAD16_BYTE( "6.ROM6.27512", 0x000001, 0x010000, CRC(13c14471) SHA1(9661ff7ca829260d1b247dee8fc5eb22d92cb1fa) )
+ ROM_LOAD16_BYTE( "5.ROM5.27512", 0x000000, 0x010000, CRC(505d09ff) SHA1(681579123257548f71ebb9d591c4db81fc52ff85) )
+ ROM_LOAD16_BYTE( "6.ROM6.27512", 0x000001, 0x010000, CRC(13c14471) SHA1(9661ff7ca829260d1b247dee8fc5eb22d92cb1fa) )
- /* No MCU */
+ /* No MCU */
ROM_REGION( 0x080000, "gfx1", 0 ) /* Scroll 0 */
ROM_LOAD( "11.ROM11.27C010", 0x000000, 0x020000, CRC(cfba8249) SHA1(f5ca1114296c2e268b44923b363add25b60f9e98) )
- ROM_LOAD( "12.ROM12.27C010", 0x020000, 0x020000, CRC(c2027f34) SHA1(c685666ae368259b27f62563131ffa4c5db2f985) )
- ROM_LOAD( "13.ROM13.27C010", 0x040000, 0x020000, CRC(d4b87d60) SHA1(94e85c9392150d3395e400defb96f7cb3fbc639b) )
- ROM_LOAD( "14.ROM14.27C010", 0x060000, 0x020000, CRC(9814fe96) SHA1(c1c53534bc2b0d97dda9f1caa0e4917d497c08ae) )
+ ROM_LOAD( "12.ROM12.27C010", 0x020000, 0x020000, CRC(c2027f34) SHA1(c685666ae368259b27f62563131ffa4c5db2f985) )
+ ROM_LOAD( "13.ROM13.27C010", 0x040000, 0x020000, CRC(d4b87d60) SHA1(94e85c9392150d3395e400defb96f7cb3fbc639b) )
+ ROM_LOAD( "14.ROM14.27C010", 0x060000, 0x020000, CRC(9814fe96) SHA1(c1c53534bc2b0d97dda9f1caa0e4917d497c08ae) )
ROM_REGION( 0x080000, "gfx2", 0 ) /* Scroll 1 */
- ROM_LOAD( "15.ROM15.27C010", 0x000000, 0x020000, CRC(a91c027d) SHA1(39b68e81e07c81ce9961e5d14e9c123c72b31051) )
- ROM_LOAD( "16.ROM16.27C010", 0x020000, 0x020000, CRC(2caecbc7) SHA1(82c2afcc3763d79ebf281fcf93b429ddbc6c44ae) )
- ROM_LOAD( "17.ROM17.27C010", 0x040000, 0x020000, CRC(3947efe8) SHA1(925dce253bf81c7d454872a707593b5085a0f3d0) )
- ROM_LOAD( "18.ROM18.27C010", 0x060000, 0x020000, CRC(2de832cb) SHA1(2b0266223561e649c535041ab8c543e3c64885ad) )
+ ROM_LOAD( "15.ROM15.27C010", 0x000000, 0x020000, CRC(a91c027d) SHA1(39b68e81e07c81ce9961e5d14e9c123c72b31051) )
+ ROM_LOAD( "16.ROM16.27C010", 0x020000, 0x020000, CRC(2caecbc7) SHA1(82c2afcc3763d79ebf281fcf93b429ddbc6c44ae) )
+ ROM_LOAD( "17.ROM17.27C010", 0x040000, 0x020000, CRC(3947efe8) SHA1(925dce253bf81c7d454872a707593b5085a0f3d0) )
+ ROM_LOAD( "18.ROM18.27C010", 0x060000, 0x020000, CRC(2de832cb) SHA1(2b0266223561e649c535041ab8c543e3c64885ad) )
ROM_REGION( 0x020000, "gfx3", 0 ) /* Scroll 2 */
ROM_LOAD( "19.ROM19.27C010", 0x000000, 0x020000, CRC(96e38983) SHA1(a4fb94f15d9a9f7df1645be66fe3e179d0ebf765) )
ROM_REGION( 0x080000, "gfx4", 0 ) /* Sprites */
ROM_LOAD( "20.ROM20.27C010", 0x000000, 0x020000, CRC(e6956a01) SHA1(3ded46d0372b0633383f2a5d7b0f53687091b220) )
- ROM_LOAD( "21.ROM21.27C010", 0x020000, 0x020000, CRC(8e19ae9a) SHA1(b12cdce9d6dae96a1c9d134828cc1cd7f85f3dab) )
- ROM_LOAD( "22.ROM22.27C010", 0x040000, 0x020000, CRC(b5be39f3) SHA1(a330f26d7355ebb4ba5c81189564c39c896e7544) )
- ROM_LOAD( "23.ROM23.27C010", 0x060000, 0x020000, CRC(01304689) SHA1(ef1836cce5b6a55633965b3c94293c6b99c59eb5) )
+ ROM_LOAD( "21.ROM21.27C010", 0x020000, 0x020000, CRC(8e19ae9a) SHA1(b12cdce9d6dae96a1c9d134828cc1cd7f85f3dab) )
+ ROM_LOAD( "22.ROM22.27C010", 0x040000, 0x020000, CRC(b5be39f3) SHA1(a330f26d7355ebb4ba5c81189564c39c896e7544) )
+ ROM_LOAD( "23.ROM23.27C010", 0x060000, 0x020000, CRC(01304689) SHA1(ef1836cce5b6a55633965b3c94293c6b99c59eb5) )
ROM_REGION( 0x040000, "oki1", 0 ) /* Samples */
- ROM_LOAD( "9.ROM9.27C010", 0x000000, 0x020000, CRC(7182f27c) SHA1(dc83f3552f6d01365f9f3af89ba97a9936f7899c) )
- ROM_LOAD( "10.ROM10.27C010", 0x020000, 0x020000, CRC(f780d92f) SHA1(8bee845a0aaa0b5ca5532ea4962adeb40699e3be) )
+ ROM_LOAD( "9.ROM9.27C010", 0x000000, 0x020000, CRC(7182f27c) SHA1(dc83f3552f6d01365f9f3af89ba97a9936f7899c) )
+ ROM_LOAD( "10.ROM10.27C010", 0x020000, 0x020000, CRC(f780d92f) SHA1(8bee845a0aaa0b5ca5532ea4962adeb40699e3be) )
ROM_REGION( 0x040000, "oki2", 0 ) /* Samples */
- ROM_LOAD( "7.ROM7.27C010", 0x000000, 0x020000, CRC(b9d79c1e) SHA1(315dbed9b7cc289b383c95e6c94267682324154c) )
- ROM_LOAD( "8.ROM8.27C010", 0x020000, 0x020000, CRC(fa0d1887) SHA1(d24c17806669f5b12527b36bc9c10fd16222e23c) )
+ ROM_LOAD( "7.ROM7.27C010", 0x000000, 0x020000, CRC(b9d79c1e) SHA1(315dbed9b7cc289b383c95e6c94267682324154c) )
+ ROM_LOAD( "8.ROM8.27C010", 0x020000, 0x020000, CRC(fa0d1887) SHA1(d24c17806669f5b12527b36bc9c10fd16222e23c) )
ROM_REGION( 0x0200, "proms", 0 ) /* Priority PROM (N82S131N compatible type PROM) */
ROM_LOAD( "rd.20n", 0x0000, 0x0200, CRC(1d877538) SHA1(a5be0dc65dcfc36fbba10d1fddbe155e24b6122f) )
@@ -4247,7 +4247,7 @@ DRIVER_INIT_MEMBER(megasys1_state,edf)
DRIVER_INIT_MEMBER(megasys1_state,edfp)
{
- phantasm_rom_decode(machine(), "maincpu");
+ phantasm_rom_decode(machine(), "maincpu");
}
READ16_MEMBER(megasys1_state::edfbl_input_r)
diff --git a/src/mame/drivers/metlfrzr.cpp b/src/mame/drivers/metlfrzr.cpp
index 83c4b40d579..6f91fdc8525 100644
--- a/src/mame/drivers/metlfrzr.cpp
+++ b/src/mame/drivers/metlfrzr.cpp
@@ -6,8 +6,8 @@
Metal Freezer (c) 1989 Seibu
driver by Angelo Salese, based off initial work by David Haywood
- thanks to Peter Wilhelmsen for the decryption
-
+ thanks to Peter Wilhelmsen for the decryption
+
HW seems the natural evolution of Dark Mist type.
TODO:
@@ -131,7 +131,6 @@ void metlfrzr_state::legacy_obj_draw(bitmap_ind16 &bitmap,const rectangle &clipr
for(count=0x200-4;count>-1;count-=4)
{
-
gfx_element *cur_gfx = base_spriteram[count+1] & 0x40 ? gfx_3 : gfx_2;
UINT8 tile_bank = (base_spriteram[count+1] & 0x30) >> 4;
UINT16 tile = base_spriteram[count] | (tile_bank << 8);
@@ -140,7 +139,7 @@ void metlfrzr_state::legacy_obj_draw(bitmap_ind16 &bitmap,const rectangle &clipr
int x = base_spriteram[count+3];
if(base_spriteram[count+1] & 0x80)
x-=256;
-
+
cur_gfx->transpen(bitmap,cliprect,tile,color,0,0,x,y,0xf);
}
}
@@ -148,7 +147,7 @@ void metlfrzr_state::legacy_obj_draw(bitmap_ind16 &bitmap,const rectangle &clipr
UINT32 metlfrzr_state::screen_update_metlfrzr(screen_device &screen, bitmap_ind16 &bitmap, const rectangle &cliprect)
{
bitmap.fill(m_palette->black_pen(), cliprect);
-
+
legacy_bg_draw(bitmap,cliprect);
legacy_obj_draw(bitmap,cliprect);
return 0;
@@ -168,7 +167,7 @@ WRITE8_MEMBER(metlfrzr_state::output_w)
m_fg_tilebank = (data & 0x10) >> 4;
membank("bank1")->set_entry((data & 0xc) >> 2);
m_rowscroll_enable = bool(BIT(data,1));
-
+
// popmessage("%02x %02x",m_fg_tilebank,data & 3);
}
@@ -249,14 +248,14 @@ static INPUT_PORTS_START( metlfrzr )
PORT_DIPSETTING( 0x00, DEF_STR( Yes ) )
PORT_START("DSW1")
- PORT_DIPNAME( 0x01, 0x00, DEF_STR( Cabinet ) ) PORT_DIPLOCATION("SW1:1")
+ PORT_DIPNAME( 0x01, 0x00, DEF_STR( Cabinet ) ) PORT_DIPLOCATION("SW1:1")
PORT_DIPSETTING( 0x00, DEF_STR( Upright ) )
PORT_DIPSETTING( 0x01, DEF_STR( Cocktail ) )
PORT_SERVICE_DIPLOC( 0x02, IP_ACTIVE_LOW, "SW1:2" )
PORT_DIPNAME( 0x04, 0x04, DEF_STR( Flip_Screen ) ) PORT_DIPLOCATION("SW1:3")
PORT_DIPSETTING( 0x04, DEF_STR( Off ) )
PORT_DIPSETTING( 0x00, DEF_STR( On ) )
- PORT_DIPNAME( 0x38, 0x38, DEF_STR( Coin_A ) ) PORT_DIPLOCATION("SW1:4,5,6")
+ PORT_DIPNAME( 0x38, 0x38, DEF_STR( Coin_A ) ) PORT_DIPLOCATION("SW1:4,5,6")
PORT_DIPSETTING( 0x00, DEF_STR( 5C_1C ) )
PORT_DIPSETTING( 0x20, DEF_STR( 4C_1C ) )
PORT_DIPSETTING( 0x10, DEF_STR( 3C_1C ) )
@@ -265,35 +264,35 @@ static INPUT_PORTS_START( metlfrzr )
PORT_DIPSETTING( 0x18, DEF_STR( 1C_2C ) )
PORT_DIPSETTING( 0x28, DEF_STR( 1C_3C ) )
PORT_DIPSETTING( 0x08, DEF_STR( 1C_5C ) )
- PORT_DIPNAME( 0xc0, 0xc0, DEF_STR( Coin_B ) ) PORT_DIPLOCATION("SW1:7,8")
+ PORT_DIPNAME( 0xc0, 0xc0, DEF_STR( Coin_B ) ) PORT_DIPLOCATION("SW1:7,8")
PORT_DIPSETTING( 0x80, DEF_STR( 2C_1C ) )
PORT_DIPSETTING( 0x00, DEF_STR( 2C_3C ) )
PORT_DIPSETTING( 0xc0, DEF_STR( 1C_1C ) )
PORT_DIPSETTING( 0x40, DEF_STR( 1C_2C ) )
PORT_START("DSW2")
- PORT_DIPNAME( 0x03, 0x03, DEF_STR( Difficulty ) ) PORT_DIPLOCATION("SW2:1,2")
+ PORT_DIPNAME( 0x03, 0x03, DEF_STR( Difficulty ) ) PORT_DIPLOCATION("SW2:1,2")
PORT_DIPSETTING( 0x02, "A" )
PORT_DIPSETTING( 0x03, "B" )
PORT_DIPSETTING( 0x01, "C" )
PORT_DIPSETTING( 0x00, "D" )
// service mode returns these values divided by 10 (so 02/05/10 effectively means 20k, 50k, 100k)
// TODO: check if it extends
- PORT_DIPNAME( 0x0c, 0x0c, DEF_STR( Bonus_Life ) ) PORT_DIPLOCATION("SW2:3,4")
+ PORT_DIPNAME( 0x0c, 0x0c, DEF_STR( Bonus_Life ) ) PORT_DIPLOCATION("SW2:3,4")
PORT_DIPSETTING( 0x08, "20k, 50k, 100k" )
PORT_DIPSETTING( 0x0c, "30k, 80k, 150k" )
PORT_DIPSETTING( 0x04, "50k, 100k, 200k" )
PORT_DIPSETTING( 0x00, "100k, 200k, 400k" )
- PORT_DIPNAME( 0x30, 0x30, DEF_STR( Lives ) ) PORT_DIPLOCATION("SW2:5,6")
+ PORT_DIPNAME( 0x30, 0x30, DEF_STR( Lives ) ) PORT_DIPLOCATION("SW2:5,6")
PORT_DIPSETTING( 0x20, "1" )
PORT_DIPSETTING( 0x10, "2" )
PORT_DIPSETTING( 0x30, "3" )
PORT_DIPSETTING( 0x00, "4" )
// disabling following enables intro / how to play screens
- PORT_DIPNAME( 0x40, 0x40, DEF_STR( Level_Select ) ) PORT_DIPLOCATION("SW2:7")
+ PORT_DIPNAME( 0x40, 0x40, DEF_STR( Level_Select ) ) PORT_DIPLOCATION("SW2:7")
PORT_DIPSETTING( 0x40, DEF_STR( Off ) )
PORT_DIPSETTING( 0x00, DEF_STR( On ) )
- PORT_DIPNAME( 0x80, 0x00, DEF_STR( Demo_Sounds ) ) PORT_DIPLOCATION("SW2:8")
+ PORT_DIPNAME( 0x80, 0x00, DEF_STR( Demo_Sounds ) ) PORT_DIPLOCATION("SW2:8")
PORT_DIPSETTING( 0x80, DEF_STR( Off ) )
PORT_DIPSETTING( 0x00, DEF_STR( On ) )
INPUT_PORTS_END
diff --git a/src/mame/drivers/mgames.cpp b/src/mame/drivers/mgames.cpp
index 1dd83a56ff6..7cb3ec90378 100644
--- a/src/mame/drivers/mgames.cpp
+++ b/src/mame/drivers/mgames.cpp
@@ -652,7 +652,7 @@ static MACHINE_CONFIG_START( mgames, mgames_state )
MCFG_PALETTE_INIT_OWNER(mgames_state, mgames)
/* sound hardware */
- // to do...
+ // to do...
MACHINE_CONFIG_END
diff --git a/src/mame/drivers/naomi.cpp b/src/mame/drivers/naomi.cpp
index f145354c4b3..882e905d2ca 100644
--- a/src/mame/drivers/naomi.cpp
+++ b/src/mame/drivers/naomi.cpp
@@ -5331,7 +5331,7 @@ ROM_START( samba )
NAOMI_DEFAULT_EEPROM
ROM_REGION( 0x8800000, "rom_board", ROMREGION_ERASEFF)
- ROM_LOAD("epr-22966b.ic22",0x0000000, 0x0400000, CRC(893116b8) SHA1(35cb4f40690ff21af5ab7cc5adbc53228d6fb0b3) ) // was also found in cartridge with Rev.A case label
+ ROM_LOAD("epr-22966b.ic22",0x0000000, 0x0400000, CRC(893116b8) SHA1(35cb4f40690ff21af5ab7cc5adbc53228d6fb0b3) ) // was also found in cartridge with Rev.A case label
ROM_LOAD("mpr-22950.ic1", 0x0800000, 0x0800000, CRC(16dee15c) SHA1(b46849e492756ff406bf8956303472255fcf55a5) )
ROM_LOAD("mpr-22951.ic2", 0x1000000, 0x0800000, CRC(f509496f) SHA1(41281576f7d58c8ede9c0a89bfd46a98d5b97033) )
ROM_LOAD("mpr-22952.ic3", 0x1800000, 0x0800000, CRC(fb9b3ef0) SHA1(e9d44b673c273e97445a12186496a0594e291542) )
@@ -9838,7 +9838,7 @@ GAME( 2003, puyofevp, naomi, naomim1, naomi, naomi_state, naomi, ROT0, "Sega", "
/* CDP-10001C*/ GAME( 2003, wccf116, naomigd, naomigd, naomi, naomi_state, naomigd, ROT0, "Hitmaker / Sega", "World Club Champion Football Serie A 2001-2002 Ver. 2 (CDP-10001C)", GAME_FLAGS )
/* CDP-10003 */ GAME( 2002, wccf1dup, naomigd, naomigd, naomi, naomi_state, naomigd, ROT0, "Hitmaker / Sega", "World Club Champion Football Serie A 2001-2002 DIMM FIRM Ver.3.03 (CDP-10003)", GAME_FLAGS )
/* CDV-10002 */ GAME( 2004, wccf212e, naomigd, naomigd, naomi, naomi_state, naomigd, ROT0, "Hitmaker / Sega", "World Club Champion Football Serie A 2002-2003 Ver.2.12 (CDV-10002)", GAME_FLAGS )
-/* CDV-10007 */ GAME( 2004, wccf2chk, naomigd, naomigd, naomi, naomi_state, naomigd, ROT0, "Hitmaker / Sega", "World Club Champion Football Serie A 2002-2003 Drive Checker (CDV-10007)", GAME_FLAGS ) // actually just disc ejector
+/* CDV-10007 */ GAME( 2004, wccf2chk, naomigd, naomigd, naomi, naomi_state, naomigd, ROT0, "Hitmaker / Sega", "World Club Champion Football Serie A 2002-2003 Drive Checker (CDV-10007)", GAME_FLAGS ) // actually just disc ejector
/* CDV-10008 */ GAME( 2004, wccf234j, naomigd, naomigd, naomi, naomi_state, naomigd, ROT0, "Hitmaker / Sega", "World Club Champion Football Serie A 2002-2003 Ver.2.34 (CDV-10008)", GAME_FLAGS )
/* CDV-10013 */ GAME( 2005, wccf310j, naomigd, naomigd, naomi, naomi_state, naomigd, ROT0, "Sega", "World Club Champion Football European Clubs 2004-2005 (CDV-10013)", GAME_FLAGS )
/* CDV-10015 */ GAME( 2005, wccf331e, wccf322e,naomigd, naomi, naomi_state, naomigd, ROT0, "Sega", "World Club Champion Football European Clubs 2004-2005 Ver.1.1 (CDV-10015)", GAME_FLAGS )
diff --git a/src/mame/drivers/neogeo.cpp b/src/mame/drivers/neogeo.cpp
index 8bb9b8069d2..b990065dafb 100644
--- a/src/mame/drivers/neogeo.cpp
+++ b/src/mame/drivers/neogeo.cpp
@@ -1054,12 +1054,12 @@ void neogeo_state::init_cpu()
{
UINT8 *ROM = (!m_slots[m_curr_slot] || m_slots[m_curr_slot]->get_rom_size() == 0) ? m_region_maincpu->base() : (UINT8 *)m_slots[m_curr_slot]->get_rom_base();
UINT32 len = (!m_slots[m_curr_slot] || m_slots[m_curr_slot]->get_rom_size() == 0) ? m_region_maincpu->bytes() : m_slots[m_curr_slot]->get_rom_size();
-
+
if (len > 0x100000)
m_bank_base = 0x100000;
else
m_bank_base = 0;
-
+
m_bank_cartridge->set_base(ROM + m_bank_base);
}
diff --git a/src/mame/drivers/pasopia7.cpp b/src/mame/drivers/pasopia7.cpp
index 88f5a79b3df..eaf0bce140e 100644
--- a/src/mame/drivers/pasopia7.cpp
+++ b/src/mame/drivers/pasopia7.cpp
@@ -817,8 +817,8 @@ WRITE8_MEMBER( pasopia7_state::video_misc_w )
*/
//if(data & 2)
//{
- // printf("VIDEO MISC %02x\n",data);
- // machine().debug_break();
+ // printf("VIDEO MISC %02x\n",data);
+ // machine().debug_break();
//}
m_cursor_blink = data & 0x20;
m_attr_wrap = data & 0x10;
diff --git a/src/mame/drivers/patinho_feio.cpp b/src/mame/drivers/patinho_feio.cpp
index 65a1e5309ec..ae5218ded57 100644
--- a/src/mame/drivers/patinho_feio.cpp
+++ b/src/mame/drivers/patinho_feio.cpp
@@ -232,22 +232,22 @@ static INPUT_PORTS_START( patinho_feio )
PORT_BIT(0x800, IP_ACTIVE_HIGH, IPT_KEYBOARD) PORT_NAME("RC bit 11") PORT_CODE(KEYCODE_1) PORT_TOGGLE
PORT_START("BUTTONS")
- /* Modo de Operação: EXECUÇÃO */
+ /* Modo de Operacao: EXECUCAO */
PORT_BIT(0x001, IP_ACTIVE_HIGH, IPT_KEYBOARD) PORT_NAME("NORMAL") PORT_CODE(KEYCODE_A)
- PORT_BIT(0x002, IP_ACTIVE_HIGH, IPT_KEYBOARD) PORT_NAME("CICLO ÚNICO") PORT_CODE(KEYCODE_S)
- PORT_BIT(0x004, IP_ACTIVE_HIGH, IPT_KEYBOARD) PORT_NAME("INSTRUÇÃO ÚNICA") PORT_CODE(KEYCODE_D)
- /* Modo de Operação: MEMÓRIA */
- PORT_BIT(0x008, IP_ACTIVE_HIGH, IPT_KEYBOARD) PORT_NAME("ENDEREÇAMENTO") PORT_CODE(KEYCODE_Z)
+ PORT_BIT(0x002, IP_ACTIVE_HIGH, IPT_KEYBOARD) PORT_NAME("CICLO UNICO") PORT_CODE(KEYCODE_S)
+ PORT_BIT(0x004, IP_ACTIVE_HIGH, IPT_KEYBOARD) PORT_NAME("INSTRUCAO UNICA") PORT_CODE(KEYCODE_D)
+ /* Modo de Operacao: MEMORIA */
+ PORT_BIT(0x008, IP_ACTIVE_HIGH, IPT_KEYBOARD) PORT_NAME("ENDERECAMENTO") PORT_CODE(KEYCODE_Z)
PORT_BIT(0x010, IP_ACTIVE_HIGH, IPT_KEYBOARD) PORT_NAME("ARMAZENAMENTO") PORT_CODE(KEYCODE_X)
- PORT_BIT(0x020, IP_ACTIVE_HIGH, IPT_KEYBOARD) PORT_NAME("EXPOSIÇÃO") PORT_CODE(KEYCODE_C)
+ PORT_BIT(0x020, IP_ACTIVE_HIGH, IPT_KEYBOARD) PORT_NAME("EXPOSICAO") PORT_CODE(KEYCODE_C)
/* Comando: */
PORT_BIT(0x040, IP_ACTIVE_HIGH, IPT_KEYBOARD) PORT_NAME("ESPERA") PORT_CODE(KEYCODE_Q)
- PORT_BIT(0x080, IP_ACTIVE_HIGH, IPT_KEYBOARD) PORT_NAME("INTERRUPÇÃO") PORT_CODE(KEYCODE_W)
+ PORT_BIT(0x080, IP_ACTIVE_HIGH, IPT_KEYBOARD) PORT_NAME("INTERRUPCAO") PORT_CODE(KEYCODE_W)
PORT_BIT(0x100, IP_ACTIVE_HIGH, IPT_KEYBOARD) PORT_NAME("PARTIDA") PORT_CODE(KEYCODE_E)
- PORT_BIT(0x200, IP_ACTIVE_HIGH, IPT_KEYBOARD) PORT_NAME("PREPARAÇÃO") PORT_CODE(KEYCODE_R)
+ PORT_BIT(0x200, IP_ACTIVE_HIGH, IPT_KEYBOARD) PORT_NAME("PREPARACAO") PORT_CODE(KEYCODE_R)
/* Switches */
- PORT_BIT(0x400, IP_ACTIVE_HIGH, IPT_KEYBOARD) PORT_NAME("ENDEREÇAMENTO (Fixo/Sequencial)") PORT_CODE(KEYCODE_N) PORT_TOGGLE
- PORT_BIT(0x800, IP_ACTIVE_HIGH, IPT_KEYBOARD) PORT_NAME("MEMÓRIA (Liberada/Protegida)") PORT_CODE(KEYCODE_M) PORT_TOGGLE
+ PORT_BIT(0x400, IP_ACTIVE_HIGH, IPT_KEYBOARD) PORT_NAME("ENDERECAMENTO (Fixo/Sequencial)") PORT_CODE(KEYCODE_N) PORT_TOGGLE
+ PORT_BIT(0x800, IP_ACTIVE_HIGH, IPT_KEYBOARD) PORT_NAME("MEMORIA (Liberada/Protegida)") PORT_CODE(KEYCODE_M) PORT_TOGGLE
INPUT_PORTS_END
static MACHINE_CONFIG_START( patinho_feio, patinho_feio_state )
@@ -258,13 +258,13 @@ static MACHINE_CONFIG_START( patinho_feio, patinho_feio_state )
MCFG_PATINHO_BUTTONS_READ_CB(READ16(patinho_feio_state, buttons_r))
/* Printer */
-// MCFG_PATINHO_IODEV_WRITE_CB(0x5, WRITE8(patinho_feio_state, printer_data_w))
+// MCFG_PATINHO_IODEV_WRITE_CB(0x5, WRITE8(patinho_feio_state, printer_data_w))
/* Papertape Puncher */
-// MCFG_PATINHO_IODEV_WRITE_CB(0x8, WRITE8(patinho_feio_state, papertape_punch_data_w))
+// MCFG_PATINHO_IODEV_WRITE_CB(0x8, WRITE8(patinho_feio_state, papertape_punch_data_w))
/* Card Reader */
-// MCFG_PATINHO_IODEV_READ_CB(0x9, READ8(patinho_feio_state, cardreader_data_r))
+// MCFG_PATINHO_IODEV_READ_CB(0x9, READ8(patinho_feio_state, cardreader_data_r))
/* DECWRITER
(max. speed: ?) */
@@ -279,7 +279,7 @@ static MACHINE_CONFIG_START( patinho_feio, patinho_feio_state )
/* Papertape Reader
Hewlett-Packard HP-2737-A
Optical Papertape Reader (max. speed: 300 characteres per second) */
-// MCFG_PATINHO_IODEV_READ_CB(0xE, READ8(patinho_feio_state, papertapereader_data_r))
+// MCFG_PATINHO_IODEV_READ_CB(0xE, READ8(patinho_feio_state, papertapereader_data_r))
/* DECWRITER */
MCFG_DEVICE_ADD("decwriter", TELEPRINTER, 0)
@@ -297,7 +297,7 @@ static MACHINE_CONFIG_START( patinho_feio, patinho_feio_state )
MCFG_DEFAULT_LAYOUT(layout_patinho)
// software lists
-// MCFG_SOFTWARE_LIST_ADD("tape_list", "patinho")
+// MCFG_SOFTWARE_LIST_ADD("tape_list", "patinho")
MACHINE_CONFIG_END
ROM_START( patinho )
@@ -313,7 +313,7 @@ ROM_START( patinho )
/* Micro pre-loader:
This was re-created by professor Joao Jose Neto based on his vague
recollection of sequences of opcode values from almost 40 years ago :-) */
- ROM_REGION( 0x02a, "micro_pre_loader", 0 )
+ ROM_REGION( 0x02a, "micro_pre_loader", 0 )
ROM_LOAD( "micro-pre-loader.bin", 0x000, 0x02a, CRC(1921feab) SHA1(bb063102e44e9ab963f95b45710141dc2c5046b0) )
ROM_END
diff --git a/src/mame/drivers/pc9801.cpp b/src/mame/drivers/pc9801.cpp
index 846f87cb95e..1030b13298b 100644
--- a/src/mame/drivers/pc9801.cpp
+++ b/src/mame/drivers/pc9801.cpp
@@ -3185,7 +3185,7 @@ static MACHINE_CONFIG_FRAGMENT( pc9801_ide )
MCFG_ATA_INTERFACE_IRQ_HANDLER(WRITELINE(pc9801_state, ide1_irq_w))
MCFG_ATA_INTERFACE_ADD("ide2", pc9801_atapi_devices, "pc9801_cd", nullptr, false)
MCFG_ATA_INTERFACE_IRQ_HANDLER(WRITELINE(pc9801_state, ide2_irq_w))
-
+
MCFG_SOFTWARE_LIST_ADD("cd_list","pc98_cd")
MACHINE_CONFIG_END
diff --git a/src/mame/drivers/rainbow.cpp b/src/mame/drivers/rainbow.cpp
index 31fa8996eee..1b88f4e9b83 100644
--- a/src/mame/drivers/rainbow.cpp
+++ b/src/mame/drivers/rainbow.cpp
@@ -24,7 +24,7 @@ BUGS / ISSUES
The former is used in startup tests, the latter seems less relevant (must use menu self test "S").
(2) serial ports do not work, so serial communication failure (ERROR 60) and ERROR 40 (serial
-printer interface) result.
+printer interface) result.
(3) while DOS 3 and UCSD systems (fort_sys, pas_sys) + diag disks boot, CPM 2.x and DOS 2.x die
in secondary boot loader with a RESTORE (seek track 0) when track 2 sector 1 should be loaded.
diff --git a/src/mame/drivers/sg1000.cpp b/src/mame/drivers/sg1000.cpp
index d83b0756b5e..881fb162b80 100644
--- a/src/mame/drivers/sg1000.cpp
+++ b/src/mame/drivers/sg1000.cpp
@@ -93,7 +93,7 @@ WRITE8_MEMBER( sg1000_state::omv_w )
READ8_MEMBER( sg1000_state::peripheral_r )
{
bool joy_ports_disabled = m_sgexpslot->is_readable(offset);
-
+
if (joy_ports_disabled)
{
return m_sgexpslot->read(space, offset);
@@ -110,7 +110,7 @@ READ8_MEMBER( sg1000_state::peripheral_r )
WRITE8_MEMBER( sg1000_state::peripheral_w )
{
bool joy_ports_disabled = m_sgexpslot->is_writeable(offset);
-
+
if (joy_ports_disabled)
{
m_sgexpslot->write(space, offset, data);
diff --git a/src/mame/drivers/sun2.cpp b/src/mame/drivers/sun2.cpp
index ec1611e494a..1fbc83e99e8 100644
--- a/src/mame/drivers/sun2.cpp
+++ b/src/mame/drivers/sun2.cpp
@@ -69,50 +69,50 @@
25/08/2009 Skeleton driver.
31/05/2016 Main screen turn on.
-
+
How the architecture works:
- - There are 3 address sub-spaces: CPU layer, MMU layer, and device layer
- - CPU layer uses MOVS instructions to output FC 3.
- - CPU layer: the low-order address bits A4-A1 specify the device
- 0100x = ID Prom
- 0101x = Diagnostic register (8 bits, 8 LEDs, bit = 0 for ON, 1 for OFF)
- 0110x = Bus error register
- 0111x = System enable register
-
- Bits A5+ address the actual individual parts of these things. ID Prom bytes
- are at 0x0008, 0x0808, 0x1008, 0x1808, 0x2008, 0x2808, 0x3008, etc.
-
- System enable bits:
- b0 = enable parity generation
- b1 = cause level 1 IRQ
- b2 = cause level 2 IRQ
- b3 = cause level 3 IRQ
- b4 = enable parity error checking
- b5 = enable DVMA
- b6 = enable all interrupts
- b7 = boot state (0 = boot, 1 = normal)
- In boot state, all supervisor program reads go to the EPROM.
-
- - MMU layer: also accessed via FC 3
- PAGE MAP at 0 + V
- SEGMENT MAP at 4 + V
- CONTEXT REG at 6 + V
-
- There are 8 hardware contexts. Supervisor and User FCs can have different contexts.
-
- Segment map is 4096 entries, from bits 23-15 of the virtual address + 3 context bits.
- Entries are 8 bits, which point to a page map entry group (PMEG), which is 16 consecutive
- page table entries (32 KB of space).
-
- Page map is 4096 entries each mapping a 2K page. There are 256 groups of 16 entries;
- the PMEG points to these 256 groups. The page map contains a 20-bit page number,
- which combines with the 11 low bits of the original address to get a 31-bit physical address.
- The entry from 0-15 is picked with bits 15-11 of the original address.
-
- Page map entries are written to the PMEG determined by their segment map entry; you must
- set the segment map validly in order to write to the page map. This is how they get away
- with having 16 MB of segment entries and only 8 MB of PMEGs.
-
+ - There are 3 address sub-spaces: CPU layer, MMU layer, and device layer
+ - CPU layer uses MOVS instructions to output FC 3.
+ - CPU layer: the low-order address bits A4-A1 specify the device
+ 0100x = ID Prom
+ 0101x = Diagnostic register (8 bits, 8 LEDs, bit = 0 for ON, 1 for OFF)
+ 0110x = Bus error register
+ 0111x = System enable register
+
+ Bits A5+ address the actual individual parts of these things. ID Prom bytes
+ are at 0x0008, 0x0808, 0x1008, 0x1808, 0x2008, 0x2808, 0x3008, etc.
+
+ System enable bits:
+ b0 = enable parity generation
+ b1 = cause level 1 IRQ
+ b2 = cause level 2 IRQ
+ b3 = cause level 3 IRQ
+ b4 = enable parity error checking
+ b5 = enable DVMA
+ b6 = enable all interrupts
+ b7 = boot state (0 = boot, 1 = normal)
+ In boot state, all supervisor program reads go to the EPROM.
+
+ - MMU layer: also accessed via FC 3
+ PAGE MAP at 0 + V
+ SEGMENT MAP at 4 + V
+ CONTEXT REG at 6 + V
+
+ There are 8 hardware contexts. Supervisor and User FCs can have different contexts.
+
+ Segment map is 4096 entries, from bits 23-15 of the virtual address + 3 context bits.
+ Entries are 8 bits, which point to a page map entry group (PMEG), which is 16 consecutive
+ page table entries (32 KB of space).
+
+ Page map is 4096 entries each mapping a 2K page. There are 256 groups of 16 entries;
+ the PMEG points to these 256 groups. The page map contains a 20-bit page number,
+ which combines with the 11 low bits of the original address to get a 31-bit physical address.
+ The entry from 0-15 is picked with bits 15-11 of the original address.
+
+ Page map entries are written to the PMEG determined by their segment map entry; you must
+ set the segment map validly in order to write to the page map. This is how they get away
+ with having 16 MB of segment entries and only 8 MB of PMEGs.
+
****************************************************************************/
#include "emu.h"
@@ -128,11 +128,11 @@ How the architecture works:
#define RS232B_TAG "rs232b"
// page table entry constants
-#define PM_VALID (0x80000000) // page is valid
-#define PM_PROTMASK (0x7e000000) // protection mask
-#define PM_TYPEMASK (0x01c00000) // type mask
-#define PM_ACCESSED (0x00200000) // accessed flag
-#define PM_MODIFIED (0x00100000) // modified flag
+#define PM_VALID (0x80000000) // page is valid
+#define PM_PROTMASK (0x7e000000) // protection mask
+#define PM_TYPEMASK (0x01c00000) // type mask
+#define PM_ACCESSED (0x00200000) // accessed flag
+#define PM_MODIFIED (0x00100000) // modified flag
class sun2_state : public driver_device
{
@@ -155,20 +155,20 @@ public:
required_device<ram_device> m_ram;
required_device<address_map_bank_device> m_type0space, m_type1space, m_type2space, m_type3space;
required_shared_ptr<UINT16> m_bw2_vram;
-
+
virtual void machine_start() override;
virtual void machine_reset() override;
-
+
DECLARE_READ16_MEMBER( tl_mmu_r );
DECLARE_WRITE16_MEMBER( tl_mmu_w );
DECLARE_READ16_MEMBER( video_ctrl_r );
DECLARE_WRITE16_MEMBER( video_ctrl_w );
DECLARE_READ16_MEMBER( ram_r );
DECLARE_WRITE16_MEMBER( ram_w );
-
+
UINT32 bw2_update(screen_device &screen, bitmap_rgb32 &bitmap, const rectangle &cliprect);
-private:
+private:
UINT16 *m_rom_ptr, *m_ram_ptr;
UINT8 *m_idprom_ptr;
UINT16 m_diagreg, m_sysenable, m_buserror;
@@ -196,49 +196,49 @@ READ16_MEMBER( sun2_state::tl_mmu_r )
if ((fc == 3) && !space.debugger_access())
{
- if (offset & 0x4) // set for CPU space
+ if (offset & 0x4) // set for CPU space
{
switch (offset & 7)
{
case 4:
//printf("sun2: Read IDPROM @ %x (PC=%x)\n", offset<<1, m_maincpu->pc);
return m_idprom_ptr[(offset>>10) & 0x1f]<<8;
-
+
case 5:
//printf("sun2: Read diag reg\n");
return m_diagreg;
-
+
case 6:
//printf("sun2: Read bus error @ PC %x\n", m_maincpu->pc);
return m_buserror;
-
+
case 7:
//printf("sun2: Read sysenable\n");
return m_sysenable;
}
}
- else // clear for MMU space
+ else // clear for MMU space
{
int page;
-
+
switch (offset & 3)
{
- case 0: // page map
+ case 0: // page map
case 1:
page = m_segmap[m_context & 7][offset >> 14] << 4;
page += ((offset >> 10) & 0xf);
-
+
//printf("sun2: Read page map at %x (entry %d)\n", offset<<1, page);
- if (offset & 1) // low-order 16 bits
+ if (offset & 1) // low-order 16 bits
{
return m_pagemap[page] & 0xffff;
}
return m_pagemap[page] >> 16;
-
+
case 2: // segment map
//printf("sun2: Read segment map at %x (entry %d, user ctx %d)\n", offset<<1, offset>>14, m_context & 7);
return m_segmap[m_context & 7][offset >> 14];
-
+
case 3: // context reg
//printf("sun2: Read context reg\n");
return m_context;
@@ -251,66 +251,66 @@ READ16_MEMBER( sun2_state::tl_mmu_r )
{
return m_rom_ptr[offset & 0x3fff];
}
-
+
// debugger hack
if ((space.debugger_access()) && (offset >= (0xef0000>>1)) && (offset <= (0xef8000>>1)))
{
return m_rom_ptr[offset & 0x3fff];
}
-
+
// it's translation time
UINT8 context = (fc & 4) ? ((m_context >> 8) & 7) : (m_context & 7);
UINT8 pmeg = m_segmap[context][offset >> 14];
UINT32 entry = (pmeg << 4) + ((offset >> 10) & 0xf);
- // printf("sun2: Context = %d, pmeg = %d, offset >> 14 = %x, entry = %d, page = %d\n", context, pmeg, offset >> 14, entry, (offset >> 10) & 0xf);
+ // printf("sun2: Context = %d, pmeg = %d, offset >> 14 = %x, entry = %d, page = %d\n", context, pmeg, offset >> 14, entry, (offset >> 10) & 0xf);
if (m_pagemap[entry] & PM_VALID)
{
m_pagemap[entry] |= PM_ACCESSED;
-
+
// Sun2 implementations only use 12 bits from the page entry
UINT32 tmp = (m_pagemap[entry] & 0xfff) << 10;
tmp |= (offset & 0x3ff);
-
- // if (!space.debugger_access())
- // printf("sun2: Translated addr: %08x, type %d (page %d page entry %08x, orig virt %08x, FC %d)\n", tmp << 1, (m_pagemap[entry] >> 22) & 7, entry, m_pagemap[entry], offset<<1, fc);
+
+ // if (!space.debugger_access())
+ // printf("sun2: Translated addr: %08x, type %d (page %d page entry %08x, orig virt %08x, FC %d)\n", tmp << 1, (m_pagemap[entry] >> 22) & 7, entry, m_pagemap[entry], offset<<1, fc);
switch ((m_pagemap[entry] >> 22) & 7)
{
- case 0: // type 0 space
+ case 0: // type 0 space
return m_type0space->read16(space, tmp, mem_mask);
-
+
case 1: // type 1 space
// EPROM space is special: the MMU has a trap door
// where the original bits of the virtual address are
- // restored so that the entire 32K EPROM can be
+ // restored so that the entire 32K EPROM can be
// accessed via a 2K single page view. This isn't
- // obvious in the sun2 manual, but the sun3 manual
+ // obvious in the sun2 manual, but the sun3 manual
// (sun3 has the same mechanism) explains it well.
// the 2/50 ROM tests this specifically at $EF0DF0.
- if (m_idprom_ptr[1] == 0x02) // 2/50 VMEbus has EPROM at 0x7F0000
+ if (m_idprom_ptr[1] == 0x02) // 2/50 VMEbus has EPROM at 0x7F0000
{
if ((tmp >= (0x7f0000>>1)) && (tmp <= (0x7f07ff>>1)))
{
- return m_rom_ptr[offset & 0x3fff];
+ return m_rom_ptr[offset & 0x3fff];
}
}
- else // Multibus has EPROM at 0x000000
+ else // Multibus has EPROM at 0x000000
{
if (tmp <= (0x7ff>>1))
{
- return m_rom_ptr[offset & 0x3fff];
+ return m_rom_ptr[offset & 0x3fff];
}
}
-
+
//printf("read device space @ %x\n", tmp<<1);
return m_type1space->read16(space, tmp, mem_mask);
-
- case 2: // type 2 space
+
+ case 2: // type 2 space
return m_type2space->read16(space, tmp, mem_mask);
-
- case 3: // type 3 space
+
+ case 3: // type 3 space
return m_type3space->read16(space, tmp, mem_mask);
}
}
@@ -318,28 +318,28 @@ READ16_MEMBER( sun2_state::tl_mmu_r )
{
if (!space.debugger_access()) printf("sun2: pagemap entry not valid!\n");
}
-
+
if (!space.debugger_access()) printf("sun2: Unmapped read @ %08x (FC %d, mask %04x, PC=%x, seg %x)\n", offset<<1, fc, mem_mask, m_maincpu->pc, offset>>15);
-
+
return 0xffff;
}
WRITE16_MEMBER( sun2_state::tl_mmu_w )
{
UINT8 fc = m_maincpu->get_fc();
-
+
//printf("sun2: Write %04x (FC %d, mask %04x, PC=%x) to %08x\n", data, fc, mem_mask, m_maincpu->pc, offset<<1);
-
+
if (fc == 3)
{
- if (offset & 0x4) // set for CPU space
+ if (offset & 0x4) // set for CPU space
{
switch (offset & 7)
{
case 4:
//printf("sun2: Write? IDPROM @ %x\n", offset<<1);
return;
-
+
case 5:
// XOR to match Table 2-1 in the 2/50 Field Service Manual
printf("sun2: CPU LEDs to %02x (PC=%x) => ", (data & 0xff) ^ 0xff, m_maincpu->pc);
@@ -357,30 +357,30 @@ WRITE16_MEMBER( sun2_state::tl_mmu_w )
}
printf("\n");
return;
-
+
case 6:
//printf("sun2: Write %04x to bus error not allowed\n", data);
return;
-
+
case 7:
//printf("sun2: Write %04x to system enable\n", data);
COMBINE_DATA(&m_sysenable);
return;
}
}
- else // clear for MMU space
+ else // clear for MMU space
{
int page;
-
+
switch (offset & 3)
{
- case 0: // page map
+ case 0: // page map
case 1:
page = m_segmap[m_context & 7][offset >> 14] << 4;
page += ((offset >> 10) & 0xf);
-
+
//printf("sun2: Write %04x to page map at %x (entry %d), ", data, offset<<1, page);
- if (offset & 1) // low-order 16 bits
+ if (offset & 1) // low-order 16 bits
{
m_pagemap[page] &= 0xffff0000;
m_pagemap[page] |= data;
@@ -392,12 +392,12 @@ WRITE16_MEMBER( sun2_state::tl_mmu_w )
}
//printf("entry now %08x (adr %08x PC=%x)\n", m_pagemap[page], (m_pagemap[page] & 0xfffff) << 11, m_maincpu->pc);
return;
-
+
case 2: // segment map
//printf("sun2: Write %02x to segment map at %x (entry %d, user ctx %d PC=%x)\n", data & 0xff, offset<<1, offset>>14, m_context & 7, m_maincpu->pc);
m_segmap[m_context & 7][offset >> 14] = data & 0xff;
return;
-
+
case 3: // context reg
//printf("sun2: Write %04x to context\n", data);
COMBINE_DATA(&m_context);
@@ -405,16 +405,16 @@ WRITE16_MEMBER( sun2_state::tl_mmu_w )
}
}
}
-
+
// it's translation time
UINT8 context = (fc & 4) ? ((m_context >> 8) & 7) : (m_context & 7);
UINT8 pmeg = m_segmap[context][offset >> 14];
UINT32 entry = (pmeg << 4) + ((offset >> 10) & 0xf);
-
+
if (m_pagemap[entry] & PM_VALID)
{
m_pagemap[entry] |= (PM_ACCESSED | PM_MODIFIED);
-
+
// only 12 of the 20 bits in the page table entry are used on either Sun2 implementation
UINT32 tmp = (m_pagemap[entry] & 0xfff) << 10;
tmp |= (offset & 0x3ff);
@@ -423,20 +423,20 @@ WRITE16_MEMBER( sun2_state::tl_mmu_w )
switch ((m_pagemap[entry] >> 22) & 7)
{
- case 0: // type 0
+ case 0: // type 0
m_type0space->write16(space, tmp, data, mem_mask);
return;
-
+
case 1: // type 1
- //printf("write device space @ %x\n", tmp<<1);
+ //printf("write device space @ %x\n", tmp<<1);
m_type1space->write16(space, tmp, data, mem_mask);
return;
-
- case 2: // type 2
+
+ case 2: // type 2
m_type2space->write16(space, tmp, data, mem_mask);
return;
-
- case 3: // type 3
+
+ case 3: // type 3
m_type3space->write16(space, tmp, data, mem_mask);
return;
}
@@ -445,7 +445,7 @@ WRITE16_MEMBER( sun2_state::tl_mmu_w )
{
if (!space.debugger_access()) printf("sun2: pagemap entry not valid!\n");
}
-
+
printf("sun2: Unmapped write %04x (FC %d, mask %04x, PC=%x) to %08x\n", data, fc, mem_mask, m_maincpu->pc, offset<<1);
}
@@ -475,7 +475,7 @@ ADDRESS_MAP_END
static ADDRESS_MAP_START(vmetype1space_map, AS_PROGRAM, 16, sun2_state)
AM_RANGE(0x000000, 0x01ffff) AM_RAM AM_SHARE("bw2_vram")
AM_RANGE(0x020000, 0x020001) AM_READWRITE( video_ctrl_r, video_ctrl_w )
- AM_RANGE(0x7f0000, 0x7f07ff) AM_ROM AM_REGION("bootprom", 0) // uses MMU loophole to read 32k from a 2k window
+ AM_RANGE(0x7f0000, 0x7f07ff) AM_ROM AM_REGION("bootprom", 0) // uses MMU loophole to read 32k from a 2k window
// 7f0800-7f0fff: Ethernet interface
// 7f1000-7f17ff: AM9518 encryption processor
//AM_RANGE(0x7f1800, 0x7f1801) AM_DEVREADWRITE8(SCC1_TAG, z80scc_device, cb_r, cb_w, 0xff00)
@@ -509,7 +509,7 @@ ADDRESS_MAP_END
// type 1 device space
static ADDRESS_MAP_START(mbustype1space_map, AS_PROGRAM, 16, sun2_state)
- AM_RANGE(0x000000, 0x0007ff) AM_ROM AM_REGION("bootprom", 0) // uses MMU loophole to read 32k from a 2k window
+ AM_RANGE(0x000000, 0x0007ff) AM_ROM AM_REGION("bootprom", 0) // uses MMU loophole to read 32k from a 2k window
// 001000-0017ff: AM9518 encryption processor
// 001800-001fff: Parallel port
AM_RANGE(0x002000, 0x0027ff) AM_DEVREADWRITE8(SCC2_TAG, z80scc_device, ba_cd_inv_r, ba_cd_inv_w, 0xff00)
@@ -577,7 +577,7 @@ void sun2_state::machine_reset()
m_buserror = 0;
memset(m_segmap, 0, sizeof(m_segmap));
memset(m_pagemap, 0, sizeof(m_pagemap));
-
+
m_maincpu->reset();
}
@@ -585,46 +585,46 @@ static MACHINE_CONFIG_START( sun2vme, sun2_state )
/* basic machine hardware */
MCFG_CPU_ADD("maincpu", M68010, 16670000)
MCFG_CPU_PROGRAM_MAP(sun2_mem)
-
+
MCFG_RAM_ADD(RAM_TAG)
MCFG_RAM_DEFAULT_SIZE("2M")
MCFG_RAM_EXTRA_OPTIONS("4M,6M,8M")
MCFG_RAM_DEFAULT_VALUE(0x00)
-
+
// MMU Type 0 device space
MCFG_DEVICE_ADD("type0", ADDRESS_MAP_BANK, 0)
MCFG_DEVICE_PROGRAM_MAP(vmetype0space_map)
MCFG_ADDRESS_MAP_BANK_ENDIANNESS(ENDIANNESS_BIG)
MCFG_ADDRESS_MAP_BANK_DATABUS_WIDTH(16)
MCFG_ADDRESS_MAP_BANK_STRIDE(0x1000000)
-
+
// MMU Type 1 device space
MCFG_DEVICE_ADD("type1", ADDRESS_MAP_BANK, 0)
MCFG_DEVICE_PROGRAM_MAP(vmetype1space_map)
MCFG_ADDRESS_MAP_BANK_ENDIANNESS(ENDIANNESS_BIG)
MCFG_ADDRESS_MAP_BANK_DATABUS_WIDTH(16)
MCFG_ADDRESS_MAP_BANK_STRIDE(0x1000000)
-
+
// MMU Type 2 device space
MCFG_DEVICE_ADD("type2", ADDRESS_MAP_BANK, 0)
MCFG_DEVICE_PROGRAM_MAP(vmetype2space_map)
MCFG_ADDRESS_MAP_BANK_ENDIANNESS(ENDIANNESS_BIG)
MCFG_ADDRESS_MAP_BANK_DATABUS_WIDTH(16)
MCFG_ADDRESS_MAP_BANK_STRIDE(0x1000000)
-
+
// MMU Type 3 device space
MCFG_DEVICE_ADD("type3", ADDRESS_MAP_BANK, 0)
MCFG_DEVICE_PROGRAM_MAP(vmetype3space_map)
MCFG_ADDRESS_MAP_BANK_ENDIANNESS(ENDIANNESS_BIG)
MCFG_ADDRESS_MAP_BANK_DATABUS_WIDTH(16)
MCFG_ADDRESS_MAP_BANK_STRIDE(0x1000000)
-
+
MCFG_SCREEN_ADD("bwtwo", RASTER)
MCFG_SCREEN_UPDATE_DRIVER(sun2_state, bw2_update)
MCFG_SCREEN_SIZE(1152,900)
MCFG_SCREEN_VISIBLE_AREA(0, 1152-1, 0, 900-1)
MCFG_SCREEN_REFRESH_RATE(72)
-
+
MCFG_SCC8530_ADD(SCC1_TAG, XTAL_4_9152MHz, 0, 0, 0, 0)
MCFG_SCC8530_ADD(SCC2_TAG, XTAL_4_9152MHz, 0, 0, 0, 0)
MCFG_Z80SCC_OUT_TXDA_CB(DEVWRITELINE(RS232A_TAG, rs232_port_device, write_txd))
@@ -645,46 +645,46 @@ static MACHINE_CONFIG_START( sun2mbus, sun2_state )
/* basic machine hardware */
MCFG_CPU_ADD("maincpu", M68010, 16670000)
MCFG_CPU_PROGRAM_MAP(sun2_mem)
-
+
MCFG_RAM_ADD(RAM_TAG)
MCFG_RAM_DEFAULT_SIZE("2M")
MCFG_RAM_EXTRA_OPTIONS("4M")
MCFG_RAM_DEFAULT_VALUE(0x00)
-
+
// MMU Type 0 device space
MCFG_DEVICE_ADD("type0", ADDRESS_MAP_BANK, 0)
MCFG_DEVICE_PROGRAM_MAP(mbustype0space_map)
MCFG_ADDRESS_MAP_BANK_ENDIANNESS(ENDIANNESS_BIG)
MCFG_ADDRESS_MAP_BANK_DATABUS_WIDTH(16)
MCFG_ADDRESS_MAP_BANK_STRIDE(0x1000000)
-
+
// MMU Type 1 device space
MCFG_DEVICE_ADD("type1", ADDRESS_MAP_BANK, 0)
MCFG_DEVICE_PROGRAM_MAP(mbustype1space_map)
MCFG_ADDRESS_MAP_BANK_ENDIANNESS(ENDIANNESS_BIG)
MCFG_ADDRESS_MAP_BANK_DATABUS_WIDTH(16)
MCFG_ADDRESS_MAP_BANK_STRIDE(0x1000000)
-
+
// MMU Type 2 device space
MCFG_DEVICE_ADD("type2", ADDRESS_MAP_BANK, 0)
MCFG_DEVICE_PROGRAM_MAP(mbustype2space_map)
MCFG_ADDRESS_MAP_BANK_ENDIANNESS(ENDIANNESS_BIG)
MCFG_ADDRESS_MAP_BANK_DATABUS_WIDTH(16)
MCFG_ADDRESS_MAP_BANK_STRIDE(0x1000000)
-
+
// MMU Type 3 device space
MCFG_DEVICE_ADD("type3", ADDRESS_MAP_BANK, 0)
MCFG_DEVICE_PROGRAM_MAP(mbustype3space_map)
MCFG_ADDRESS_MAP_BANK_ENDIANNESS(ENDIANNESS_BIG)
MCFG_ADDRESS_MAP_BANK_DATABUS_WIDTH(16)
MCFG_ADDRESS_MAP_BANK_STRIDE(0x1000000)
-
+
MCFG_SCREEN_ADD("bwtwo", RASTER)
MCFG_SCREEN_UPDATE_DRIVER(sun2_state, bw2_update)
MCFG_SCREEN_SIZE(1152,900)
MCFG_SCREEN_VISIBLE_AREA(0, 1152-1, 0, 900-1)
MCFG_SCREEN_REFRESH_RATE(72)
-
+
MCFG_SCC8530_ADD(SCC1_TAG, XTAL_4_9152MHz, 0, 0, 0, 0)
MCFG_SCC8530_ADD(SCC2_TAG, XTAL_4_9152MHz, 0, 0, 0, 0)
MCFG_Z80SCC_OUT_TXDA_CB(DEVWRITELINE(RS232A_TAG, rs232_port_device, write_txd))
@@ -707,7 +707,7 @@ ROM_START( sun2_120 )
ROM_LOAD16_WORD_SWAP( "sun2-multi-rev-r.bin", 0x0000, 0x8000, CRC(4df0df77) SHA1(4d6bcf09ddc9cc8f5823847b8ea88f98fe4a642e))
ROM_REGION( 0x20, "idprom", ROMREGION_ERASEFF)
- ROM_LOAD( "sun2120-idprom.bin", 0x000000, 0x000020, CRC(eec8cd1d) SHA1(6a78dc0ea6f9cc7687cffea754d65864fb751ebf) )
+ ROM_LOAD( "sun2120-idprom.bin", 0x000000, 0x000020, CRC(eec8cd1d) SHA1(6a78dc0ea6f9cc7687cffea754d65864fb751ebf) )
ROM_END
ROM_START( sun2_50 )
@@ -716,7 +716,7 @@ ROM_START( sun2_50 )
ROM_LOAD16_BYTE( "250_q_0.rom", 0x0000, 0x4000, CRC(2ee29abe) SHA1(82f52b9f25e92387329581f7c8ba50a171784968))
ROM_REGION( 0x20, "idprom", ROMREGION_ERASEFF)
- ROM_LOAD( "sun250-idprom.bin", 0x000000, 0x000020, CRC(927744ab) SHA1(d29302b69128165e69dd3a79b8c8d45f2163b88a) )
+ ROM_LOAD( "sun250-idprom.bin", 0x000000, 0x000020, CRC(927744ab) SHA1(d29302b69128165e69dd3a79b8c8d45f2163b88a) )
ROM_END
/* Driver */
diff --git a/src/mame/drivers/sun3.cpp b/src/mame/drivers/sun3.cpp
index 4d198c29399..eb76ef1adbb 100644
--- a/src/mame/drivers/sun3.cpp
+++ b/src/mame/drivers/sun3.cpp
@@ -158,7 +158,7 @@
factor. Serial and keyboard ports. External RAM,
framebuffer, and SCSI/ethernet boards
available.
-
+
3/60 ROM breakpoints of interest
fefb104 - bus error test
fefb18e - interrupt test
@@ -194,20 +194,20 @@ fefc34a - start of mem_size, which queries ECC registers for each memory board
#define RS232B_TAG "rs232b"
// page table entry constants
-#define PM_VALID (0x80000000) // page is valid
-#define PM_WRITEMASK (0x40000000) // writable?
-#define PM_SYSMASK (0x20000000) // system use only?
-#define PM_CACHE (0x10000000) // cachable?
-#define PM_TYPEMASK (0x0c000000) // type mask
-#define PM_ACCESSED (0x02000000) // accessed flag
-#define PM_MODIFIED (0x01000000) // modified flag
-
-#define BE_FPENABLE (0x04) // FPU not enabled
-#define BE_FPBERR (0x08) // FPU encountered a bus error
-#define BE_VMEBERR (0x10) // VME encountered a bus error
-#define BE_TIMEOUT (0x20) // timeout - memory doesn't exist
-#define BE_PROTERR (0x40) // protection failed on MMU page lookup
-#define BE_INVALID (0x80) // invalid entry on MMU page lookup
+#define PM_VALID (0x80000000) // page is valid
+#define PM_WRITEMASK (0x40000000) // writable?
+#define PM_SYSMASK (0x20000000) // system use only?
+#define PM_CACHE (0x10000000) // cachable?
+#define PM_TYPEMASK (0x0c000000) // type mask
+#define PM_ACCESSED (0x02000000) // accessed flag
+#define PM_MODIFIED (0x01000000) // modified flag
+
+#define BE_FPENABLE (0x04) // FPU not enabled
+#define BE_FPBERR (0x08) // FPU encountered a bus error
+#define BE_VMEBERR (0x10) // VME encountered a bus error
+#define BE_TIMEOUT (0x20) // timeout - memory doesn't exist
+#define BE_PROTERR (0x40) // protection failed on MMU page lookup
+#define BE_INVALID (0x80) // invalid entry on MMU page lookup
class sun3_state : public driver_device
{
@@ -270,7 +270,7 @@ private:
UINT32 m_pagemap[4096];
UINT32 m_ram_size, m_ram_size_words;
bool m_bInBusErr;
-
+
UINT32 m_cache_tags[0x4000], m_cache_data[0x4000];
};
@@ -280,17 +280,17 @@ READ32_MEMBER( sun3_state::ram_r )
{
//printf("ECC testing, RAM read ofs %x\n", offset);
m_ecc[1] &= 0x00ffffff;
-
- if (m_ecc[2] == 0x01000000) // single-bit error test
+
+ if (m_ecc[2] == 0x01000000) // single-bit error test
{
- m_ecc[1] |= 0x8f000000; // put in the syndrome code the first ECC test wants
-
+ m_ecc[1] |= 0x8f000000; // put in the syndrome code the first ECC test wants
+
if (offset == 0)
{
return 0x80000000;
}
}
- else if (m_ecc[2] == 0x01000200) // double-bit error test
+ else if (m_ecc[2] == 0x01000200) // double-bit error test
{
m_ecc[1] |= 0xfc000000;
}
@@ -305,7 +305,7 @@ READ32_MEMBER( sun3_state::ram_r )
m_buserr = BE_TIMEOUT;
m_maincpu->set_input_line(M68K_LINE_BUSERROR, ASSERT_LINE);
m_maincpu->set_input_line(M68K_LINE_BUSERROR, CLEAR_LINE);
- }
+ }
return 0xffffffff;
}
@@ -353,10 +353,10 @@ WRITE32_MEMBER( sun3_state::ram_w )
m_parregs[0] |= 0x0f<<24;
break;
}
-
+
// indicate parity interrupt
m_parregs[0] |= 0x80000000;
-
+
// and can we take that now?
if (m_parregs[0] & 0x40000000)
{
@@ -365,7 +365,7 @@ WRITE32_MEMBER( sun3_state::ram_w )
}
}
- if (offset < m_ram_size_words)
+ if (offset < m_ram_size_words)
{
COMBINE_DATA(&m_ram_ptr[offset]);
return;
@@ -384,60 +384,60 @@ WRITE32_MEMBER( sun3_state::ram_w )
READ32_MEMBER( sun3_state::tl_mmu_r )
{
UINT8 fc = m_maincpu->get_fc();
-
+
if ((fc == 3) && !space.debugger_access())
- {
+ {
int page;
-
+
switch (offset >> 26)
{
case 0: // IDPROM
//printf("sun3: Read IDPROM at %x (mask %08x)\n", offset, mem_mask);
return m_idprom_ptr[(offset*4)] << 24 | m_idprom_ptr[(offset*4)+1]<<16 | m_idprom_ptr[(offset*4)+2]<<8 | m_idprom_ptr[(offset*4)+3];
-
- case 1: // page map
+
+ case 1: // page map
page = m_segmap[m_context & 7][(offset >> 15) & 0x7ff] << 4;
- page += (offset >> 11) & 0xf;
- //printf("sun3: Read page map at %x (entry %d)\n", offset<<1, page);
+ page += (offset >> 11) & 0xf;
+ //printf("sun3: Read page map at %x (entry %d)\n", offset<<1, page);
return m_pagemap[page];
-
+
case 2: // segment map
//printf("sun3: Read segment map at %x (entry %d, user ctx %d mask %x)\n", offset<<2, (offset & ~0x3c000000) >> 15, m_context & 7, mem_mask);
return m_segmap[m_context & 7][(offset >> 15) & 0x7ff]<<24;
-
+
case 3: // context reg
//printf("sun3: Read context reg\n");
return m_context<<24;
-
+
case 4: // enable reg
return m_enable;
-
+
case 5: // DVMA enable
return m_dvma_enable<<24;
-
+
case 6: // bus error
m_bInBusErr = false;
//printf("Reading bus error: %02x\n", m_buserr);
return m_buserr<<24;
-
+
case 7: // diagnostic reg
return 0;
-
+
case 8: // cache tags
//printf("sun3: read cache tags @ %x, PC = %x\n", offset, m_maincpu->pc);
return m_cache_tags[(offset & 0x3fff) >> 2];
-
+
case 9: // cache data
//printf("sun3: read cache data @ %x, PC = %x\n", offset, m_maincpu->pc);
return m_cache_data[(offset & 0x3fff)];
-
+
case 10: // flush cache
return 0xffffffff;
-
+
case 11: // block copy
printf("sun3: read block copy @ %x, PC = %x\n", offset, m_maincpu->pc);
return 0xffffffff;
-
+
case 15: // UART bypass
//printf("sun3: read UART bypass @ %x, PC = %x, mask = %08x\n", offset, m_maincpu->pc, mem_mask);
return 0xffffffff;
@@ -449,13 +449,13 @@ READ32_MEMBER( sun3_state::tl_mmu_r )
{
return m_rom_ptr[offset & 0x3fff];
}
-
+
// debugger hack
if ((space.debugger_access()) && (offset >= (0xfef0000>>2)) && (offset <= (0xfefffff>>2)))
{
return m_rom_ptr[offset & 0x3fff];
}
-
+
// it's translation time
UINT8 pmeg = m_segmap[m_context & 7][(offset >> 15) & 0x7ff];
UINT32 entry = (pmeg << 4) + ((offset >> 11) & 0xf);
@@ -472,40 +472,40 @@ READ32_MEMBER( sun3_state::tl_mmu_r )
m_bInBusErr = true;
return 0xffffffff;
}
-
+
m_pagemap[entry] |= PM_ACCESSED;
-
+
UINT32 tmp = (m_pagemap[entry] & 0x7ffff) << 11;
tmp |= (offset & 0x7ff);
-
+
//printf("pmeg %d, entry %d = %08x, virt %08x => tmp %08x\n", pmeg, entry, m_pagemap[entry], offset << 2, tmp);
-
- // if (!space.debugger_access())
+
+ // if (!space.debugger_access())
//printf("sun3: Translated addr: %08x, type %d (page %d page entry %08x, orig virt %08x, FC %d)\n", tmp << 2, (m_pagemap[entry] >> 26) & 3, entry, m_pagemap[entry], offset<<2, fc);
switch ((m_pagemap[entry] >> 26) & 3)
{
- case 0: // type 0 space
+ case 0: // type 0 space
return m_type0space->read32(space, tmp, mem_mask);
-
+
case 1: // type 1 space
// magic ROM bypass
if ((tmp >= (0x100000>>2)) && (tmp <= (0x10ffff>>2)))
{
- return m_rom_ptr[offset & 0x3fff];
+ return m_rom_ptr[offset & 0x3fff];
}
return m_type1space->read32(space, tmp, mem_mask);
-
- case 2: // type 2 space
+
+ case 2: // type 2 space
return m_type2space->read32(space, tmp, mem_mask);
-
- case 3: // type 3 space
+
+ case 3: // type 3 space
return m_type3space->read32(space, tmp, mem_mask);
}
}
else
{
-// if (!space.debugger_access()) printf("sun3: pagemap entry not valid! (PC=%x)\n", m_maincpu->pc);
+// if (!space.debugger_access()) printf("sun3: pagemap entry not valid! (PC=%x)\n", m_maincpu->pc);
m_maincpu->set_input_line(M68K_LINE_BUSERROR, ASSERT_LINE);
m_maincpu->set_input_line(M68K_LINE_BUSERROR, CLEAR_LINE);
m_buserr = BE_INVALID;
@@ -514,59 +514,59 @@ READ32_MEMBER( sun3_state::tl_mmu_r )
}
if (!space.debugger_access()) logerror("sun3: Unmapped read @ %08x (FC %d, mask %08x, PC=%x, seg %x)\n", offset<<2, fc, mem_mask, m_maincpu->pc, offset>>15);
-
+
return 0xffffffff;
}
WRITE32_MEMBER( sun3_state::tl_mmu_w )
{
UINT8 fc = m_maincpu->get_fc();
-
+
//printf("sun3: Write %08x (FC %d, mask %08x, PC=%x) to %08x\n", data, fc, mem_mask, m_maincpu->pc, offset<<1);
-
- if (fc == 3) // control space
+
+ if (fc == 3) // control space
{
int page;
-
+
switch (offset >> 26)
{
- case 0: // IDPROM
+ case 0: // IDPROM
return;
-
- case 1: // page map fefaf32
+
+ case 1: // page map fefaf32
page = m_segmap[m_context & 7][(offset >> 15) & 0x7ff] << 4;
//printf("context = %d, segment = %d, PMEG = %d, add = %d\n", m_context & 7, (offset >> 15) & 0x7ff, page, (offset >> 11) & 0xf);
page += (offset >> 11) & 0xf;
-
+
//printf("sun3: Write %04x to page map at %x (entry %d), ", data, offset<<2, page);
COMBINE_DATA(&m_pagemap[page]);
-
+
//printf("entry now %08x (adr %08x PC=%x mask %x)\n", m_pagemap[page], (m_pagemap[page] & 0xfffff) << 13, m_maincpu->pc, mem_mask);
return;
-
+
case 2: // segment map
//printf("sun3: Write %02x to segment map at %x (entry %d, user ctx %d PC=%x mask %x)\n", (data>>24) & 0xff, offset<<2, (offset & ~0x3c000000)>>15, m_context & 7, m_maincpu->pc, mem_mask);
m_segmap[m_context & 7][(offset >> 15) & 0x7ff] = (data>>24) & 0xff;
//printf("segment map[%d][%d] now %x\n", m_context & 7, (offset & ~0x3c000000) >> 15, m_segmap[m_context & 7][(offset & ~0x3c000000) >> 15] = (data>>24) & 0xff);
return;
-
+
case 3: // context reg
//printf("sun3: Write (%x) %x to context\n", data, data>>24);
m_context = data >> 24;
return;
-
+
case 4: // enable reg
//printf("sun3: Write %x to enable, PC=%x\n", data, m_maincpu->pc);
COMBINE_DATA(&m_enable);
return;
-
+
case 5: // DVMA enable
m_dvma_enable = data>>24;
return;
-
+
case 6: // bus error (read-only)
return;
-
+
case 7: // diagnostic reg
m_diag = data >> 24;
#if 0
@@ -574,9 +574,9 @@ WRITE32_MEMBER( sun3_state::tl_mmu_w )
for (int i = 0; i < 8; i++)
{
if (m_diag & (1<<i))
- {
- printf(".");
- }
+ {
+ printf(".");
+ }
else
{
printf("*");
@@ -585,34 +585,34 @@ WRITE32_MEMBER( sun3_state::tl_mmu_w )
printf("\n");
#endif
return;
-
+
case 8: // cache tags
//printf("sun3: %08x to cache tags @ %x, PC = %x, mask = %08x\n", data, offset, m_maincpu->pc, mem_mask);
m_cache_tags[(offset & 0x3fff) >> 2] = data;
return;
-
+
case 9: // cache data
//printf("sun3: %08x to cache data @ %x, PC = %x, mask = %08x\n", data, offset, m_maincpu->pc, mem_mask);
m_cache_data[(offset & 0x3fff)] = data;
return;
-
+
case 10: // flush cache
return;
-
+
case 11: // block copy
printf("sun3: %08x to block copy @ %x, PC = %x\n", data, offset, m_maincpu->pc);
return;
-
+
case 15: // UART bypass
//printf("sun3: %08x to UART bypass @ %x, PC = %x\n", data, offset, m_maincpu->pc);
return;
}
}
-
+
// it's translation time
UINT8 pmeg = m_segmap[m_context & 7][(offset >> 15) & 0x7ff];
UINT32 entry = (pmeg << 4) + ((offset >> 11) & 0xf);
-
+
if (m_pagemap[entry] & PM_VALID)
{
if ((!(m_pagemap[entry] & PM_WRITEMASK)) ||
@@ -625,9 +625,9 @@ WRITE32_MEMBER( sun3_state::tl_mmu_w )
m_bInBusErr = true;
return;
}
-
+
m_pagemap[entry] |= (PM_ACCESSED | PM_MODIFIED);
-
+
UINT32 tmp = (m_pagemap[entry] & 0x7ffff) << 11;
tmp |= (offset & 0x7ff);
@@ -635,20 +635,20 @@ WRITE32_MEMBER( sun3_state::tl_mmu_w )
switch ((m_pagemap[entry] >> 26) & 3)
{
- case 0: // type 0
+ case 0: // type 0
m_type0space->write32(space, tmp, data, mem_mask);
return;
-
+
case 1: // type 1
- //printf("write device space @ %x\n", tmp<<1);
+ //printf("write device space @ %x\n", tmp<<1);
m_type1space->write32(space, tmp, data, mem_mask);
return;
-
- case 2: // type 2
+
+ case 2: // type 2
m_type2space->write32(space, tmp, data, mem_mask);
return;
-
- case 3: // type 3
+
+ case 3: // type 3
m_type3space->write32(space, tmp, data, mem_mask);
return;
}
@@ -662,15 +662,15 @@ WRITE32_MEMBER( sun3_state::tl_mmu_w )
m_bInBusErr = true;
return;
}
-
+
logerror("sun3: Unmapped write %04x (FC %d, mask %04x, PC=%x) to %08x\n", data, fc, mem_mask, m_maincpu->pc, offset<<2);
}
READ32_MEMBER(sun3_state::parity_r)
{
UINT32 rv = m_parregs[offset];
-
- if (offset == 0) // clear interrupt if any
+
+ if (offset == 0) // clear interrupt if any
{
m_maincpu->set_input_line(M68K_IRQ_7, CLEAR_LINE);
m_parregs[offset] &= ~0x8f000000;
@@ -682,16 +682,16 @@ READ32_MEMBER(sun3_state::parity_r)
WRITE32_MEMBER(sun3_state::parity_w)
{
//printf("sun3: %08x to parity registers @ %x (mask %08x)\n", data, offset, mem_mask);
-
+
if (offset == 0)
{
m_parregs[0] &= 0x8f000000;
-
+
if ((m_parregs[0] & 0x80000000) && (data & 0x40000000))
{
m_maincpu->set_input_line(M68K_IRQ_7, ASSERT_LINE);
}
-
+
m_parregs[0] |= (data & 0x70000000);
}
else
@@ -707,7 +707,7 @@ ADDRESS_MAP_END
// type 0 device space
static ADDRESS_MAP_START(vmetype0space_map, AS_PROGRAM, 32, sun3_state)
AM_RANGE(0x00000000, 0x08ffffff) AM_READWRITE(ram_r, ram_w)
- AM_RANGE(0xfe400000, 0xfe41ffff) AM_RAM // not sure what's going on here (3/110)
+ AM_RANGE(0xfe400000, 0xfe41ffff) AM_RAM // not sure what's going on here (3/110)
AM_RANGE(0xff000000, 0xff03ffff) AM_RAM AM_SHARE("bw2_vram")
ADDRESS_MAP_END
@@ -720,7 +720,7 @@ ADDRESS_MAP_END
static ADDRESS_MAP_START(vmetype1space_map, AS_PROGRAM, 32, sun3_state)
AM_RANGE(0x00000000, 0x0000000f) AM_DEVREADWRITE8(SCC1_TAG, z80scc_device, ba_cd_inv_r, ba_cd_inv_w, 0xff00ff00)
AM_RANGE(0x00020000, 0x0002000f) AM_DEVREADWRITE8(SCC2_TAG, z80scc_device, ba_cd_inv_r, ba_cd_inv_w, 0xff00ff00)
- AM_RANGE(0x00040000, 0x000407ff) AM_RAM AM_SHARE("nvram") // type 2816 parallel EEPROM
+ AM_RANGE(0x00040000, 0x000407ff) AM_RAM AM_SHARE("nvram") // type 2816 parallel EEPROM
AM_RANGE(0x00060000, 0x0006ffff) AM_READWRITE8(rtc7170_r, rtc7170_w, 0xffffffff)
AM_RANGE(0x00080000, 0x0008000f) AM_READWRITE(parity_r, parity_w)
AM_RANGE(0x000a0000, 0x000a0003) AM_READWRITE(irqctrl_r, irqctrl_w)
@@ -776,19 +776,19 @@ WRITE32_MEMBER(sun3_state::irqctrl_w)
READ8_MEMBER(sun3_state::rtc7170_r)
{
//printf("read 7170 @ %x, PC=%x\n", offset, m_maincpu->pc);
-
+
return 0xff;
}
WRITE8_MEMBER(sun3_state::rtc7170_w)
{
//printf("%02x to 7170 @ %x\n", data, offset);
-
+
if ((offset == 0x11) && (data == 0x1c))
{
if ((m_irqctrl & 0x21000000) == 0x21000000)
{
- m_maincpu->set_input_line(M68K_IRQ_5, ASSERT_LINE);
+ m_maincpu->set_input_line(M68K_IRQ_5, ASSERT_LINE);
}
}
}
@@ -799,27 +799,27 @@ READ32_MEMBER(sun3_state::ecc_r)
// fefc34a
int mbram = (m_ram_size / (1024*1024));
int beoff = (mbram / 32) * 0x10;
-
+
//printf("offset %x MB %d beoff %x\n", offset, mbram, beoff);
-
+
if (offset >= beoff)
{
m_buserr = BE_TIMEOUT;
m_maincpu->set_input_line(M68K_LINE_BUSERROR, ASSERT_LINE);
m_maincpu->set_input_line(M68K_LINE_BUSERROR, CLEAR_LINE);
}
-
+
UINT32 rv = m_ecc[offset & 0xf];
-
- if ((offset & 0xf) == 0) rv |= 0x06000000; // indicate each ECC board is 32MB, for 128MB total
-
+
+ if ((offset & 0xf) == 0) rv |= 0x06000000; // indicate each ECC board is 32MB, for 128MB total
+
return rv;
}
WRITE32_MEMBER(sun3_state::ecc_w)
{
//printf("%08x to ecc @ %x, mask %08x\n", data, offset, mem_mask);
-
+
offset &= 0xf;
m_ecc[offset] = data;
}
@@ -928,11 +928,11 @@ void sun3_state::machine_start()
m_ram_ptr = (UINT32 *)m_ram->pointer();
m_idprom_ptr = (UINT8 *)m_idprom->base();
m_ram_size = m_ram->size();
- m_ram_size_words = m_ram_size >> 2;
+ m_ram_size_words = m_ram_size >> 2;
}
void sun3_state::machine_reset()
-{
+{
m_maincpu->reset();
m_enable = 0;
m_buserr = 0;
@@ -953,7 +953,7 @@ static MACHINE_CONFIG_START( sun3, sun3_state )
MCFG_SCREEN_SIZE(1600,1100)
MCFG_SCREEN_VISIBLE_AREA(0, 1152-1, 0, 900-1)
MCFG_SCREEN_REFRESH_RATE(72)
-
+
MCFG_RAM_ADD(RAM_TAG)
MCFG_RAM_DEFAULT_SIZE("4M")
MCFG_RAM_EXTRA_OPTIONS("6M,8M,12M,16M,20M,24M,28M,32M")
@@ -967,30 +967,30 @@ static MACHINE_CONFIG_START( sun3, sun3_state )
MCFG_ADDRESS_MAP_BANK_ENDIANNESS(ENDIANNESS_BIG)
MCFG_ADDRESS_MAP_BANK_DATABUS_WIDTH(32)
MCFG_ADDRESS_MAP_BANK_STRIDE(0x80000000)
-
+
// MMU Type 1 device space
MCFG_DEVICE_ADD("type1", ADDRESS_MAP_BANK, 0)
MCFG_DEVICE_PROGRAM_MAP(vmetype1space_map)
MCFG_ADDRESS_MAP_BANK_ENDIANNESS(ENDIANNESS_BIG)
MCFG_ADDRESS_MAP_BANK_DATABUS_WIDTH(32)
MCFG_ADDRESS_MAP_BANK_STRIDE(0x80000000)
-
+
// MMU Type 2 device space
MCFG_DEVICE_ADD("type2", ADDRESS_MAP_BANK, 0)
MCFG_DEVICE_PROGRAM_MAP(vmetype2space_map)
MCFG_ADDRESS_MAP_BANK_ENDIANNESS(ENDIANNESS_BIG)
MCFG_ADDRESS_MAP_BANK_DATABUS_WIDTH(32)
MCFG_ADDRESS_MAP_BANK_STRIDE(0x80000000)
-
+
// MMU Type 3 device space
MCFG_DEVICE_ADD("type3", ADDRESS_MAP_BANK, 0)
MCFG_DEVICE_PROGRAM_MAP(vmetype3space_map)
MCFG_ADDRESS_MAP_BANK_ENDIANNESS(ENDIANNESS_BIG)
MCFG_ADDRESS_MAP_BANK_DATABUS_WIDTH(32)
MCFG_ADDRESS_MAP_BANK_STRIDE(0x80000000)
-
+
MCFG_TIMER_DRIVER_ADD_PERIODIC("timer", sun3_state, sun3_timer, attotime::from_hz(100))
-
+
MCFG_SCC8530_ADD(SCC1_TAG, XTAL_4_9152MHz, 0, 0, 0, 0)
MCFG_SCC8530_ADD(SCC2_TAG, XTAL_4_9152MHz, 0, 0, 0, 0)
MCFG_Z80SCC_OUT_TXDA_CB(DEVWRITELINE(RS232A_TAG, rs232_port_device, write_txd))
@@ -1011,7 +1011,7 @@ MACHINE_CONFIG_END
static MACHINE_CONFIG_DERIVED( sun3_60, sun3 )
MCFG_CPU_REPLACE("maincpu", M68020, 20000000)
MCFG_CPU_PROGRAM_MAP(sun3_mem)
-
+
MCFG_SCREEN_MODIFY("bwtwo")
MCFG_SCREEN_UPDATE_DRIVER(sun3_state, bw2_16x11_update)
MCFG_SCREEN_SIZE(1600,1100)
@@ -1029,13 +1029,13 @@ MACHINE_CONFIG_END
static MACHINE_CONFIG_DERIVED( sun3200, sun3 )
MCFG_CPU_REPLACE("maincpu", M68020, 25000000)
MCFG_CPU_PROGRAM_MAP(sun3_mem)
-
+
MCFG_SCREEN_MODIFY("bwtwo")
MCFG_SCREEN_UPDATE_DRIVER(sun3_state, bw2_16x11_update)
MCFG_SCREEN_SIZE(1600,1100)
MCFG_SCREEN_VISIBLE_AREA(0, 1600-1, 0, 1100-1)
MCFG_SCREEN_REFRESH_RATE(72)
-
+
MCFG_RAM_MODIFY(RAM_TAG)
MCFG_RAM_DEFAULT_SIZE("32M")
MCFG_RAM_EXTRA_OPTIONS("64M,96M,128M")
@@ -1051,11 +1051,11 @@ static MACHINE_CONFIG_START( sun3_50, sun3_state )
MCFG_SCREEN_SIZE(1600,1100)
MCFG_SCREEN_VISIBLE_AREA(0, 1152-1, 0, 900-1)
MCFG_SCREEN_REFRESH_RATE(72)
-
+
MCFG_NVRAM_ADD_0FILL("nvram")
-
+
MCFG_TIMER_DRIVER_ADD_PERIODIC("timer", sun3_state, sun3_timer, attotime::from_hz(100))
-
+
MCFG_RAM_ADD(RAM_TAG)
MCFG_RAM_DEFAULT_SIZE("4M")
MCFG_RAM_DEFAULT_VALUE(0x00)
@@ -1066,28 +1066,28 @@ static MACHINE_CONFIG_START( sun3_50, sun3_state )
MCFG_ADDRESS_MAP_BANK_ENDIANNESS(ENDIANNESS_BIG)
MCFG_ADDRESS_MAP_BANK_DATABUS_WIDTH(32)
MCFG_ADDRESS_MAP_BANK_STRIDE(0x80000000)
-
+
// MMU Type 1 device space
MCFG_DEVICE_ADD("type1", ADDRESS_MAP_BANK, 0)
MCFG_DEVICE_PROGRAM_MAP(vmetype1space_map)
MCFG_ADDRESS_MAP_BANK_ENDIANNESS(ENDIANNESS_BIG)
MCFG_ADDRESS_MAP_BANK_DATABUS_WIDTH(32)
MCFG_ADDRESS_MAP_BANK_STRIDE(0x80000000)
-
+
// MMU Type 2 device space
MCFG_DEVICE_ADD("type2", ADDRESS_MAP_BANK, 0)
MCFG_DEVICE_PROGRAM_MAP(vmetype2space_map)
MCFG_ADDRESS_MAP_BANK_ENDIANNESS(ENDIANNESS_BIG)
MCFG_ADDRESS_MAP_BANK_DATABUS_WIDTH(32)
MCFG_ADDRESS_MAP_BANK_STRIDE(0x80000000)
-
+
// MMU Type 3 device space
MCFG_DEVICE_ADD("type3", ADDRESS_MAP_BANK, 0)
MCFG_DEVICE_PROGRAM_MAP(vmetype3space_map)
MCFG_ADDRESS_MAP_BANK_ENDIANNESS(ENDIANNESS_BIG)
MCFG_ADDRESS_MAP_BANK_DATABUS_WIDTH(32)
MCFG_ADDRESS_MAP_BANK_STRIDE(0x80000000)
-
+
MCFG_SCC8530_ADD(SCC1_TAG, XTAL_4_9152MHz, 0, 0, 0, 0)
MCFG_SCC8530_ADD(SCC2_TAG, XTAL_4_9152MHz, 0, 0, 0, 0)
MCFG_Z80SCC_OUT_TXDA_CB(DEVWRITELINE(RS232A_TAG, rs232_port_device, write_txd))
@@ -1133,7 +1133,7 @@ Sun 3/50 V2.8 Bootprom
ROMX_LOAD( "sun3_50_v1.6", 0x0000, 0x10000, CRC(8be20826) SHA1(2a4d73fcb7fe0f0c83eb0f4c91d957b7bf88b7ed), ROM_BIOS(5))
ROM_REGION( 0x20, "idprom", ROMREGION_ERASEFF)
- ROM_LOAD( "sun3-50-idprom.bin", 0x000000, 0x000020, CRC(80610dbe) SHA1(0f37e31ed209b8905c5dc7c2663fa01a9b9baaba) )
+ ROM_LOAD( "sun3-50-idprom.bin", 0x000000, 0x000020, CRC(80610dbe) SHA1(0f37e31ed209b8905c5dc7c2663fa01a9b9baaba) )
ROM_END
ROM_START( sun3_60 )
@@ -1155,7 +1155,7 @@ Sun 3/60 V3.0.1 Bootprom
ROMX_LOAD( "sun_3.60v1.9", 0x0000, 0x10000, CRC(32b6d3a9) SHA1(307756ba5698611d51059881057f8086956ce895), ROM_BIOS(3))
ROM_REGION( 0x20, "idprom", ROMREGION_ERASEFF)
- ROM_LOAD( "sun3-60-idprom.bin", 0x000000, 0x000020, CRC(117e766a) SHA1(f01547be0156bd4e06bbdee4c342d1b38c7646ae) )
+ ROM_LOAD( "sun3-60-idprom.bin", 0x000000, 0x000020, CRC(117e766a) SHA1(f01547be0156bd4e06bbdee4c342d1b38c7646ae) )
ROM_END
ROM_START( sun3_110 )
@@ -1228,7 +1228,7 @@ Sun 3/260/280 V3.0 Bootprom
ROMX_LOAD( "sun3_260_v2.6", 0x0000, 0x10000, CRC(e8b17951) SHA1(e1fdef42670a349d99b0eca9c50c8566b8bb7c56), ROM_BIOS(3))
ROM_REGION( 0x20, "idprom", ROMREGION_ERASEFF)
- ROM_LOAD( "sun3-260-idprom.bin", 0x000000, 0x000020, CRC(d51794f3) SHA1(17930c773b6fe9a32819094ffaf69e5453d1ea4d) )
+ ROM_LOAD( "sun3-260-idprom.bin", 0x000000, 0x000020, CRC(d51794f3) SHA1(17930c773b6fe9a32819094ffaf69e5453d1ea4d) )
ROM_END
ROM_START( sun3_e )
@@ -1237,7 +1237,7 @@ ROM_START( sun3_e )
ROMX_LOAD( "sun3_e.32", 0x0000, 0x10000, CRC(acedde7e) SHA1(1ab6ec28f4365a613a5e326c34cb37585c3f0ecc), ROM_BIOS(1))
ROM_REGION( 0x20, "idprom", ROMREGION_ERASEFF)
- ROM_LOAD( "sun3-e-idprom.bin", 0x000000, 0x000020, CRC(d1a92116) SHA1(4836f3188f2c3dd5ba49ab66e0b55caa6b1b1791) )
+ ROM_LOAD( "sun3-e-idprom.bin", 0x000000, 0x000020, CRC(d1a92116) SHA1(4836f3188f2c3dd5ba49ab66e0b55caa6b1b1791) )
ROM_END
/* YEAR NAME PARENT COMPAT MACHINE INPUT INIT COMPANY FULLNAME FLAGS */
diff --git a/src/mame/drivers/sun4.cpp b/src/mame/drivers/sun4.cpp
index 7b3d00a240b..95551566d5e 100644
--- a/src/mame/drivers/sun4.cpp
+++ b/src/mame/drivers/sun4.cpp
@@ -381,15 +381,15 @@
21/11/2011 Skeleton driver.
20/06/2016 Much less skeletony.
-
+
4/60 ROM notes:
-
+
ffe809fc: call to print "Sizing Memory" to the UART
- ffe80a70: call to "Setting up RAM for monitor" that goes wrong
- ffe80210: testing memory
- ffe80274: loop that goes wobbly and fails
- ffe80dc4: switch off boot mode, MMU maps ROM to copy in RAM from here on
- ffe82000: start of FORTH (?) interpreter once decompressed
+ ffe80a70: call to "Setting up RAM for monitor" that goes wrong
+ ffe80210: testing memory
+ ffe80274: loop that goes wobbly and fails
+ ffe80dc4: switch off boot mode, MMU maps ROM to copy in RAM from here on
+ ffe82000: start of FORTH (?) interpreter once decompressed
text in decmopressed area claims to be FORTH-83 FCode, but the opcodes
do not match the documented OpenFirmware FCode ones at all.
@@ -415,26 +415,26 @@
#define RS232A_TAG "rs232a"
#define RS232B_TAG "rs232b"
-#define ENA_NOTBOOT (0x80)
-#define ENA_SDVMA (0x20)
-#define ENA_CACHE (0x10)
-#define ENA_RESET (0x04)
-#define ENA_DIAG (0x01)
+#define ENA_NOTBOOT (0x80)
+#define ENA_SDVMA (0x20)
+#define ENA_CACHE (0x10)
+#define ENA_RESET (0x04)
+#define ENA_DIAG (0x01)
// page table entry constants
-#define PM_VALID (0x80000000) // page is valid
-#define PM_WRITEMASK (0x40000000) // writable?
-#define PM_SYSMASK (0x20000000) // system use only?
-#define PM_CACHE (0x10000000) // cachable?
-#define PM_TYPEMASK (0x0c000000) // type mask
-#define PM_ACCESSED (0x02000000) // accessed flag
-#define PM_MODIFIED (0x01000000) // modified flag
+#define PM_VALID (0x80000000) // page is valid
+#define PM_WRITEMASK (0x40000000) // writable?
+#define PM_SYSMASK (0x20000000) // system use only?
+#define PM_CACHE (0x10000000) // cachable?
+#define PM_TYPEMASK (0x0c000000) // type mask
+#define PM_ACCESSED (0x02000000) // accessed flag
+#define PM_MODIFIED (0x01000000) // modified flag
namespace
{
const sparc_disassembler::asi_desc_map::value_type sun4_asi_desc[] = {
- { 0x10, { nullptr, "Flush I-Cache (Segment)" } },
- { 0x11, { nullptr, "Flush I-Cache (Page)" } },
+ { 0x10, { nullptr, "Flush I-Cache (Segment)" } },
+ { 0x11, { nullptr, "Flush I-Cache (Page)" } },
{ 0x02, { nullptr, "System Space" } }, { 0x12, { nullptr, "Flush I-Cache (Context)" } },
{ 0x03, { nullptr, "Segment Map" } }, { 0x13, { nullptr, "Flush I-Cache (User)" } },
{ 0x04, { nullptr, "Page Map" } }, { 0x14, { nullptr, "Flush D-Cache (Segment)" } },
@@ -452,16 +452,16 @@ const sparc_disassembler::asi_desc_map::value_type sun4_asi_desc[] = {
};
/* TODO: make SPARCstation-1 a different machine type so it can load its own ASI descriptions - it's a subset of Sun4
const sparc_disassembler::asi_desc_map::value_type sun4c_asi_desc[] = {
- { 0x02, { nullptr, "System Space" } },
- { 0x03, { nullptr, "Segment Map" } },
- { 0x04, { nullptr, "Page Map" } },
- { 0x08, { nullptr, "User Instruction" } },
- { 0x09, { nullptr, "Supervisor Instruction" } },
- { 0x0a, { nullptr, "User Data" } },
- { 0x0b, { nullptr, "Supervisor Data" } },
- { 0x0c, { nullptr, "Flush Cache (Segment)" } },
- { 0x0d, { nullptr, "Flush Cache (Page)" } },
- { 0x0e, { nullptr, "Flush Cache (Context)" } }
+ { 0x02, { nullptr, "System Space" } },
+ { 0x03, { nullptr, "Segment Map" } },
+ { 0x04, { nullptr, "Page Map" } },
+ { 0x08, { nullptr, "User Instruction" } },
+ { 0x09, { nullptr, "Supervisor Instruction" } },
+ { 0x0a, { nullptr, "User Data" } },
+ { 0x0b, { nullptr, "Supervisor Data" } },
+ { 0x0c, { nullptr, "Flush Cache (Segment)" } },
+ { 0x0d, { nullptr, "Flush Cache (Page)" } },
+ { 0x0e, { nullptr, "Flush Cache (Context)" } }
};
*/
}
@@ -492,7 +492,7 @@ public:
DECLARE_WRITE32_MEMBER( ram_w );
DECLARE_READ32_MEMBER( ss1_sl0_id );
DECLARE_READ32_MEMBER( ss1_sl3_id );
-
+
protected:
required_device<mb86901_device> m_maincpu;
required_device<z80scc_device> m_scc1;
@@ -510,7 +510,7 @@ private:
UINT8 m_segmap[8][4096];
UINT32 m_pagemap[8192];
UINT32 m_ram_size, m_ram_size_words;
-
+
void l2p_command(int ref, int params, const char **param);
};
@@ -521,18 +521,18 @@ READ32_MEMBER( sun4_state::sun4_mmu_r )
// make debugger fetches emulate supervisor program for best compatibility with boot PROM execution
if (space.debugger_access()) asi = 9;
-
+
// supervisor program fetches in boot state are special
if ((!(m_system_enable & ENA_NOTBOOT)) && (asi == 9))
{
return m_rom_ptr[offset & 0x1ffff];
}
-
+
switch (asi)
{
- case 2: // system space
+ case 2: // system space
switch (offset >> 26)
- {
+ {
case 3: // context reg
return m_context<<24;
@@ -550,8 +550,8 @@ READ32_MEMBER( sun4_state::sun4_mmu_r )
case 9: // (d-)cache data
logerror("sun4: read dcache data @ %x, PC = %x\n", offset, m_maincpu->pc());
return 0xffffffff;
-
- case 0xf: // UART bypass
+
+ case 0xf: // UART bypass
//printf("read UART bypass @ %x mask %08x\n", offset<<2, mem_mask);
switch (offset & 3)
{
@@ -566,7 +566,7 @@ READ32_MEMBER( sun4_state::sun4_mmu_r )
return 0;
}
break;
- case 3: // segment map
+ case 3: // segment map
//printf("sun4: read segment map @ %x (entry %d, mem_mask %08x, PC=%x)\n", offset << 2, (offset>>16) & 0xfff, mem_mask, m_maincpu->pc());
if (mem_mask == 0xffff0000)
{
@@ -576,9 +576,9 @@ READ32_MEMBER( sun4_state::sun4_mmu_r )
{
return m_segmap[m_context][(offset>>16) & 0xfff]<<24;
}
- else
+ else
{
- // printf("sun4: read segment map w/unk mask %08x\n", mem_mask);
+ // printf("sun4: read segment map w/unk mask %08x\n", mem_mask);
}
return 0x0;
@@ -588,7 +588,7 @@ READ32_MEMBER( sun4_state::sun4_mmu_r )
//printf("sun4: read page map @ %x (entry %d, mem_mask %08x, PC=%x)\n", offset << 2, page, mem_mask, m_maincpu->pc());
return m_pagemap[page];
break;
-
+
case 8:
case 9:
case 10:
@@ -601,26 +601,26 @@ READ32_MEMBER( sun4_state::sun4_mmu_r )
if (m_pagemap[entry] & PM_VALID)
{
m_pagemap[entry] |= PM_ACCESSED;
-
+
UINT32 tmp = (m_pagemap[entry] & 0xffff) << 10;
tmp |= (offset & 0x3ff);
-
+
//printf("sun4: read translated vaddr %08x to phys %08x type %d, PTE %08x, PC=%x\n", offset<<2, tmp<<2, (m_pagemap[entry]>>26) & 3, m_pagemap[entry], m_maincpu->pc());
-
+
switch ((m_pagemap[entry] >> 26) & 3)
{
- case 0: // type 0 space
+ case 0: // type 0 space
return m_type0space->read32(space, tmp, mem_mask);
-
+
case 1: // type 1 space
// magic EPROM bypass
if ((tmp >= (0x6000000>>2)) && (tmp <= (0x6ffffff>>2)))
{
- return m_rom_ptr[offset & 0x1ffff];
+ return m_rom_ptr[offset & 0x1ffff];
}
//printf("Read type 1 @ VA %08x, phys %08x\n", offset<<2, tmp<<2);
return m_type1space->read32(space, tmp, mem_mask);
-
+
default:
printf("sun4: access to memory type not defined in sun4c\n");
return 0;
@@ -632,19 +632,19 @@ READ32_MEMBER( sun4_state::sun4_mmu_r )
{
printf("sun4: INVALID PTE entry %d %08x accessed! vaddr=%x PC=%x\n", entry, m_pagemap[entry], offset <<2, m_maincpu->pc());
//m_maincpu->trap(SPARC_DATA_ACCESS_EXCEPTION);
- //m_buserror[0] = 0x88; // read, invalid PTE
+ //m_buserror[0] = 0x88; // read, invalid PTE
//m_buserror[1] = offset<<2;
}
return 0;
- }
+ }
}
break;
-
+
default:
if (!space.debugger_access()) printf("sun4: ASI %d unhandled read @ %x (PC=%x)\n", asi, offset<<2, m_maincpu->pc());
return 0;
}
-
+
printf("sun4: read asi %d byte offset %x, PC = %x\n", asi, offset << 2, m_maincpu->pc());
return 0;
@@ -678,8 +678,8 @@ WRITE32_MEMBER( sun4_state::sun4_mmu_w )
case 9: // cache data
logerror("sun4: %08x to cache data @ %x, PC = %x\n", data, offset, m_maincpu->pc());
return;
-
- case 0xf: // UART bypass
+
+ case 0xf: // UART bypass
//printf("%08x to UART @ %d, mask %08x\n", data, offset & 3, mem_mask);
switch (offset & 3)
{
@@ -701,18 +701,18 @@ WRITE32_MEMBER( sun4_state::sun4_mmu_w )
if (mem_mask == 0xffff0000) segdata = (data >> 16) & 0x7f;
else if (mem_mask == 0xff000000) segdata = (data >> 24) & 0x7f;
else logerror("sun4: writing segment map with unknown mask %08x, PC=%x\n", mem_mask, m_maincpu->pc());
-
+
//printf("sun4: %08x to segment map @ %x (entry %d, mem_mask %08x, PC=%x)\n", segdata, offset << 2, (offset>>16) & 0xfff, mem_mask, m_maincpu->pc());
- m_segmap[m_context & 7][(offset>>16) & 0xfff] = segdata; // only 7 bits of the segment are necessary
+ m_segmap[m_context & 7][(offset>>16) & 0xfff] = segdata; // only 7 bits of the segment are necessary
}
return;
-
+
case 4: // page map
- page = m_segmap[m_context & 7][(offset >> 16) & 0xfff] << 6; // get the PMEG
- page += (offset >> 10) & 0x3f; // add the offset
+ page = m_segmap[m_context & 7][(offset >> 16) & 0xfff] << 6; // get the PMEG
+ page += (offset >> 10) & 0x3f; // add the offset
//printf("sun4: %08x to page map @ %x (entry %d, mem_mask %08x, PC=%x)\n", data, offset << 2, page, mem_mask, m_maincpu->pc());
COMBINE_DATA(&m_pagemap[page]);
- m_pagemap[page] &= 0xff00ffff; // these 8 bits are cleared when written and tested as such
+ m_pagemap[page] &= 0xff00ffff; // these 8 bits are cleared when written and tested as such
return;
case 8:
case 9:
@@ -725,20 +725,20 @@ WRITE32_MEMBER( sun4_state::sun4_mmu_w )
if (m_pagemap[entry] & PM_VALID)
{
m_pagemap[entry] |= PM_ACCESSED;
-
+
UINT32 tmp = (m_pagemap[entry] & 0xffff) << 10;
tmp |= (offset & 0x3ff);
-
+
//printf("sun4: write translated vaddr %08x to phys %08x type %d, PTE %08x, PC=%x\n", offset<<2, tmp<<2, (m_pagemap[entry]>>26) & 3, m_pagemap[entry], m_maincpu->pc());
switch ((m_pagemap[entry] >> 26) & 3)
{
- case 0: // type 0
+ case 0: // type 0
m_type0space->write32(space, tmp, data, mem_mask);
return;
-
+
case 1: // type 1
- //printf("write device space @ %x\n", tmp<<1);
+ //printf("write device space @ %x\n", tmp<<1);
m_type1space->write32(space, tmp, data, mem_mask);
return;
default:
@@ -750,26 +750,26 @@ WRITE32_MEMBER( sun4_state::sun4_mmu_w )
{
printf("sun4: INVALID PTE entry %d %08x accessed! vaddr=%x PC=%x\n", entry, m_pagemap[entry], offset <<2, m_maincpu->pc());
//m_maincpu->trap(SPARC_DATA_ACCESS_EXCEPTION);
- //m_buserror[0] = 0x8; // invalid PTE
+ //m_buserror[0] = 0x8; // invalid PTE
//m_buserror[1] = offset<<2;
return;
}
break;
-
+
}
printf("sun4: %08x to asi %d byte offset %x, PC = %x, mask = %08x\n", data, asi, offset << 2, m_maincpu->pc(), mem_mask);
}
void sun4_state::l2p_command(int ref, int params, const char **param)
-{
+{
UINT64 addr, offset;
-
+
if (!machine().debugger().commands().validate_number_parameter(param[0], &addr)) return;
-
+
addr &= 0xffffffff;
offset = addr >> 2;
-
+
UINT8 pmeg = m_segmap[m_context & 7][(offset >> 16) & 0xfff];
UINT32 entry = (pmeg << 6) + ((offset >> 10) & 0x3f);
UINT32 tmp = (m_pagemap[entry] & 0xffff) << 10;
@@ -805,8 +805,8 @@ void sun4_state::machine_start()
m_rom_ptr = (UINT32 *)m_rom->base();
m_ram_ptr = (UINT32 *)m_ram->pointer();
m_ram_size = m_ram->size();
- m_ram_size_words = m_ram_size >> 2;
-
+ m_ram_size_words = m_ram_size >> 2;
+
if (machine().debug_flags & DEBUG_FLAG_ENABLED)
{
using namespace std::placeholders;
@@ -867,10 +867,10 @@ WRITE32_MEMBER( sun4_state::ram_w )
m_parregs[0] |= 0x0f<<24;
break;
}
-
+
// indicate parity interrupt
m_parregs[0] |= 0x80000000;
-
+
// and can we take that now?
if (m_parregs[0] & 0x40000000)
{
@@ -882,7 +882,7 @@ WRITE32_MEMBER( sun4_state::ram_w )
//if ((offset<<2) == 0xfb2000) printf("write %08x to %08x, mask %08x, PC=%x\n", data, offset<<2, mem_mask, m_maincpu->pc());
- if (offset < m_ram_size_words)
+ if (offset < m_ram_size_words)
{
COMBINE_DATA(&m_ram_ptr[offset]);
return;
@@ -897,9 +897,9 @@ static ADDRESS_MAP_START(type1space_map, AS_PROGRAM, 32, sun4_state)
AM_RANGE(0x00000000, 0x0000000f) AM_DEVREADWRITE8(SCC1_TAG, z80scc_device, ba_cd_inv_r, ba_cd_inv_w, 0xff00ff00)
AM_RANGE(0x01000000, 0x0100000f) AM_DEVREADWRITE8(SCC2_TAG, z80scc_device, ba_cd_inv_r, ba_cd_inv_w, 0xff00ff00)
AM_RANGE(0x02000000, 0x020007ff) AM_DEVREADWRITE8(TIMEKEEPER_TAG, timekeeper_device, read, write, 0xffffffff)
- AM_RANGE(0x06000000, 0x0607ffff) AM_ROM AM_REGION("user1", 0)
- AM_RANGE(0x08000000, 0x08000003) AM_READ(ss1_sl0_id) // slot 0 contains SCSI/DMA/Ethernet
- AM_RANGE(0x0e000000, 0x0e000003) AM_READ(ss1_sl3_id) // slot 3 contains video board
+ AM_RANGE(0x06000000, 0x0607ffff) AM_ROM AM_REGION("user1", 0)
+ AM_RANGE(0x08000000, 0x08000003) AM_READ(ss1_sl0_id) // slot 0 contains SCSI/DMA/Ethernet
+ AM_RANGE(0x0e000000, 0x0e000003) AM_READ(ss1_sl3_id) // slot 3 contains video board
ADDRESS_MAP_END
// indicate 4/60 SCSI/DMA/Ethernet card exists
@@ -932,7 +932,7 @@ static MACHINE_CONFIG_START( sun4, sun4_state )
MCFG_ADDRESS_MAP_BANK_ENDIANNESS(ENDIANNESS_BIG)
MCFG_ADDRESS_MAP_BANK_DATABUS_WIDTH(32)
MCFG_ADDRESS_MAP_BANK_STRIDE(0x80000000)
-
+
// MMU Type 1 device space
MCFG_DEVICE_ADD("type1", ADDRESS_MAP_BANK, 0)
MCFG_DEVICE_PROGRAM_MAP(type1space_map)
diff --git a/src/mame/drivers/system16.cpp b/src/mame/drivers/system16.cpp
index 3291f592b37..2316b5b72f4 100644
--- a/src/mame/drivers/system16.cpp
+++ b/src/mame/drivers/system16.cpp
@@ -2090,7 +2090,7 @@ static MACHINE_CONFIG_DERIVED( shinobi_datsu, system16_base )
MCFG_VIDEO_START_OVERRIDE(segas1x_bootleg_state, s16a_bootleg_shinobi )
MCFG_SCREEN_MODIFY("screen")
MCFG_SCREEN_UPDATE_DRIVER(segas1x_bootleg_state, screen_update_s16a_bootleg)
-
+
MCFG_FRAGMENT_ADD(datsu_2x_ym2203)
MACHINE_CONFIG_END
@@ -2127,7 +2127,7 @@ static MACHINE_CONFIG_DERIVED( passsht4b, system16_base )
MCFG_VIDEO_START_OVERRIDE(segas1x_bootleg_state, s16a_bootleg_passsht )
MCFG_SCREEN_MODIFY("screen")
MCFG_SCREEN_UPDATE_DRIVER(segas1x_bootleg_state, screen_update_s16a_bootleg_passht4b)
-
+
MCFG_FRAGMENT_ADD(datsu_2x_ym2203)
MACHINE_CONFIG_END
@@ -2145,7 +2145,7 @@ static MACHINE_CONFIG_DERIVED( wb3bb, system16_base )
MCFG_VIDEO_START_OVERRIDE(segas1x_bootleg_state, s16a_bootleg_wb3bl )
MCFG_SCREEN_MODIFY("screen")
MCFG_SCREEN_UPDATE_DRIVER(segas1x_bootleg_state, screen_update_s16a_bootleg)
-
+
MCFG_FRAGMENT_ADD(z80_ym2151)
MACHINE_CONFIG_END
@@ -2231,7 +2231,7 @@ static MACHINE_CONFIG_DERIVED( dduxbl, system16_base )
MCFG_BOOTLEG_SYS16B_SPRITES_ADD("sprites")
MCFG_BOOTLEG_SYS16B_SPRITES_XORIGIN(189-112)
-
+
MCFG_FRAGMENT_ADD(z80_ym2151)
MACHINE_CONFIG_END
@@ -2243,7 +2243,7 @@ static MACHINE_CONFIG_DERIVED( eswatbl, system16_base )
MCFG_BOOTLEG_SYS16B_SPRITES_ADD("sprites")
MCFG_BOOTLEG_SYS16B_SPRITES_XORIGIN(189-124)
-
+
MCFG_FRAGMENT_ADD(z80_ym2151_upd7759)
MACHINE_CONFIG_END
@@ -2257,7 +2257,7 @@ static MACHINE_CONFIG_DERIVED( tetrisbl, system16_base )
MCFG_BOOTLEG_SYS16B_SPRITES_ADD("sprites")
MCFG_BOOTLEG_SYS16B_SPRITES_XORIGIN(189-112)
-
+
MCFG_FRAGMENT_ADD(z80_ym2151)
MACHINE_CONFIG_END
@@ -2268,7 +2268,7 @@ static MACHINE_CONFIG_DERIVED( altbeastbl, system16_base )
MCFG_BOOTLEG_SYS16B_SPRITES_ADD("sprites")
MCFG_BOOTLEG_SYS16B_SPRITES_XORIGIN(189-112)
-
+
MCFG_FRAGMENT_ADD(datsu_2x_ym2203)
MACHINE_CONFIG_END
@@ -2280,7 +2280,7 @@ static MACHINE_CONFIG_DERIVED( beautyb, system16_base )
MCFG_BOOTLEG_SYS16B_SPRITES_ADD("sprites")
MCFG_BOOTLEG_SYS16B_SPRITES_XORIGIN(189-112)
-
+
MCFG_FRAGMENT_ADD(z80_ym2151)
MACHINE_CONFIG_END
@@ -3009,7 +3009,7 @@ ROM_START( mutantwarr )
ROM_REGION( 0x60000, "gfx1", ROMREGION_INVERT ) // tiles
ROM_LOAD( "16.bin", 0x00000, 0x10000, CRC(a4967d10) SHA1(537b9ea604a38a919c111ece5dd3e55a5070d346) ) // plane 1
- ROM_LOAD( "15.bin", 0x10000, 0x10000, CRC(e091ae2c) SHA1(5a129f2445d13c321cb3ad0eff7ab8ea3f6ddf43) )
+ ROM_LOAD( "15.bin", 0x10000, 0x10000, CRC(e091ae2c) SHA1(5a129f2445d13c321cb3ad0eff7ab8ea3f6ddf43) )
ROM_LOAD( "14.bin", 0x20000, 0x10000, CRC(1a26cf3f) SHA1(3a488ee485db7b3f27d5ed6c6e7d263d4840bd6a) ) // plane 2
ROM_LOAD( "13.bin", 0x30000, 0x10000, CRC(277ef086) SHA1(d7a5e944f5287aa15d14ff940d1aca8d1e649d26) )
ROM_LOAD( "12.bin", 0x40000, 0x10000, CRC(661225af) SHA1(115303efeb5676ab059600a48edf36b8a56f6c15) ) // plane 3
diff --git a/src/mame/drivers/tek440x.cpp b/src/mame/drivers/tek440x.cpp
index f56f9dbd306..8072e4f2cf9 100755
--- a/src/mame/drivers/tek440x.cpp
+++ b/src/mame/drivers/tek440x.cpp
@@ -3,48 +3,48 @@
/***************************************************************************
Tektronix 440x "AI Workstations"
-
+
skeleton by R. Belmont
Hardware overview:
* 68010 (4404) or 68020 (4405) with custom MMU
- * Intelligent floppy subsystem with 6502 driving a uPD765 controller
- * NS32081 FPU
- * 6551 debug console AICA
- * SN76496 PSG for sound
- * MC146818 RTC
- * MC68681 DUART / timer (3.6864 MHz clock) (serial channel A = keyboard, channel B = RS-232 port)
- * AM9513 timer (source of timer IRQ)
- * NCR5385 SCSI controller
-
- Video is a 640x480 1bpp window on a 1024x1024 VRAM area; smooth panning around that area
- is possible as is flat-out changing the scanout address.
-
- IRQ levels:
- 7 = Debug (NMI)
- 6 = VBL
- 5 = UART
- 4 = Spare (exp slots)
- 3 = SCSI
- 2 = DMA
- 1 = Timer
- 0 = Unused
-
- MMU info:
- Map control register (location unk): bit 15 = VM enable, bits 10-8 = process ID
-
- Map entries:
- bit 15 = dirty
- bit 14 = write enable
- bit 13-11 = process ID
- bits 10-0 = address bits 22-12 in the final address
+ * Intelligent floppy subsystem with 6502 driving a uPD765 controller
+ * NS32081 FPU
+ * 6551 debug console AICA
+ * SN76496 PSG for sound
+ * MC146818 RTC
+ * MC68681 DUART / timer (3.6864 MHz clock) (serial channel A = keyboard, channel B = RS-232 port)
+ * AM9513 timer (source of timer IRQ)
+ * NCR5385 SCSI controller
+
+ Video is a 640x480 1bpp window on a 1024x1024 VRAM area; smooth panning around that area
+ is possible as is flat-out changing the scanout address.
+
+ IRQ levels:
+ 7 = Debug (NMI)
+ 6 = VBL
+ 5 = UART
+ 4 = Spare (exp slots)
+ 3 = SCSI
+ 2 = DMA
+ 1 = Timer
+ 0 = Unused
+
+ MMU info:
+ Map control register (location unk): bit 15 = VM enable, bits 10-8 = process ID
+
+ Map entries:
+ bit 15 = dirty
+ bit 14 = write enable
+ bit 13-11 = process ID
+ bits 10-0 = address bits 22-12 in the final address
***************************************************************************/
#include "emu.h"
#include "cpu/m68000/m68000.h"
#include "cpu/m6502/m6502.h"
-#include "machine/mos6551.h" // debug tty
+#include "machine/mos6551.h" // debug tty
#include "machine/mc146818.h"
#include "bus/rs232/rs232.h"
@@ -58,7 +58,7 @@ public:
m_mainram(*this, "mainram"),
m_vram(*this, "vram")
{}
-
+
virtual void machine_start() override;
virtual void machine_reset() override;
UINT32 screen_update(screen_device &screen, bitmap_ind16 &bitmap, const rectangle &cliprect);
@@ -92,8 +92,8 @@ void tek440x_state::machine_reset()
UINT8 *RAM = (UINT8 *)m_mainram.target();
memcpy(RAM, ROM, 256);
-
- m_maincpu->reset();
+
+ m_maincpu->reset();
}
@@ -183,7 +183,7 @@ static MACHINE_CONFIG_START( tek4404, tek440x_state )
/* basic machine hardware */
MCFG_CPU_ADD("maincpu", M68010, 166666666)
MCFG_CPU_PROGRAM_MAP(maincpu_map)
-
+
MCFG_CPU_ADD("fdccpu", M6502, 1000000)
MCFG_CPU_PROGRAM_MAP(fdccpu_map)
@@ -197,7 +197,7 @@ static MACHINE_CONFIG_START( tek4404, tek440x_state )
MCFG_SCREEN_UPDATE_DRIVER(tek440x_state, screen_update)
MCFG_SCREEN_PALETTE("palette")
MCFG_PALETTE_ADD_MONOCHROME("palette")
-
+
MCFG_DEVICE_ADD("aica", MOS6551, 0)
MCFG_MOS6551_XTAL(XTAL_1_8432MHz)
MCFG_MOS6551_TXD_HANDLER(DEVWRITELINE("rs232", rs232_port_device, write_txd))
@@ -219,14 +219,14 @@ MACHINE_CONFIG_END
ROM_START( tek4404 )
ROM_REGION( 0x8000, "maincpu", 0 )
- ROM_LOAD16_BYTE( "tek_u158.bin", 0x000000, 0x004000, CRC(9939e660) SHA1(66b4309e93e4ff20c1295dc2ec2a8d6389b2578c) )
- ROM_LOAD16_BYTE( "tek_u163.bin", 0x000001, 0x004000, CRC(a82dcbb1) SHA1(a7e4545e9ea57619faacc1556fa346b18f870084) )
-
+ ROM_LOAD16_BYTE( "tek_u158.bin", 0x000000, 0x004000, CRC(9939e660) SHA1(66b4309e93e4ff20c1295dc2ec2a8d6389b2578c) )
+ ROM_LOAD16_BYTE( "tek_u163.bin", 0x000001, 0x004000, CRC(a82dcbb1) SHA1(a7e4545e9ea57619faacc1556fa346b18f870084) )
+
ROM_REGION( 0x1000, "fdccpu", 0 )
- ROM_LOAD( "tek_u130.bin", 0x000000, 0x001000, CRC(2c11a3f1) SHA1(b29b3705692d50f15f7e8bbba12a24c69817d52e) )
-
+ ROM_LOAD( "tek_u130.bin", 0x000000, 0x001000, CRC(2c11a3f1) SHA1(b29b3705692d50f15f7e8bbba12a24c69817d52e) )
+
ROM_REGION( 0x2000, "scsimfm", 0 )
- ROM_LOAD( "scsi_mfm.bin", 0x000000, 0x002000, CRC(b4293435) SHA1(5e2b96c19c4f5c63a5afa2de504d29fe64a4c908) )
+ ROM_LOAD( "scsi_mfm.bin", 0x000000, 0x002000, CRC(b4293435) SHA1(5e2b96c19c4f5c63a5afa2de504d29fe64a4c908) )
ROM_END
/*************************************
diff --git a/src/mame/drivers/toaplan1.cpp b/src/mame/drivers/toaplan1.cpp
index 2bae7de4e7c..36ea7c5ec07 100644
--- a/src/mame/drivers/toaplan1.cpp
+++ b/src/mame/drivers/toaplan1.cpp
@@ -792,7 +792,7 @@ ADDRESS_MAP_END
static ADDRESS_MAP_START( outzonecv_main_map, AS_PROGRAM, 16, toaplan1_state )
AM_RANGE(0x000000, 0x03ffff) AM_ROM
-// AM_RANGE(0x040000, 0x07ffff) AM_ROM
+// AM_RANGE(0x040000, 0x07ffff) AM_ROM
AM_RANGE(0x080000, 0x087fff) AM_RAM
AM_RANGE(0x0c0000, 0x0c0003) AM_WRITE(toaplan1_tile_offsets_w)
AM_RANGE(0x0c0006, 0x0c0007) AM_WRITE(toaplan1_fcu_flipscreen_w)
diff --git a/src/mame/drivers/toaplan2.cpp b/src/mame/drivers/toaplan2.cpp
index d546fbe5786..afaf0db60da 100644
--- a/src/mame/drivers/toaplan2.cpp
+++ b/src/mame/drivers/toaplan2.cpp
@@ -3180,9 +3180,9 @@ static MACHINE_CONFIG_START( dogyuun, toaplan2_state )
MCFG_CPU_ADD("audiocpu", V25, XTAL_25MHz/2) /* NEC V25 type Toaplan marked CPU ??? */
MCFG_CPU_PROGRAM_MAP(v25_mem)
MCFG_V25_CONFIG(nitro_decryption_table)
- MCFG_V25_PORT_PT_READ_CB(IOPORT("DSWB")) MCFG_DEVCB_XOR(0xff)
- MCFG_V25_PORT_P0_READ_CB(IOPORT("DSWA")) MCFG_DEVCB_XOR(0xff)
- MCFG_V25_PORT_P1_READ_CB(IOPORT("JMPR")) MCFG_DEVCB_XOR(0xff)
+ MCFG_V25_PORT_PT_READ_CB(IOPORT("DSWB")) MCFG_DEVCB_XOR(0xff)
+ MCFG_V25_PORT_P0_READ_CB(IOPORT("DSWA")) MCFG_DEVCB_XOR(0xff)
+ MCFG_V25_PORT_P1_READ_CB(IOPORT("JMPR")) MCFG_DEVCB_XOR(0xff)
MCFG_V25_PORT_P2_WRITE_CB(NOOP) // bit 0 is FAULT according to kbash schematic
MCFG_MACHINE_START_OVERRIDE(toaplan2_state,toaplan2)
@@ -3228,9 +3228,9 @@ static MACHINE_CONFIG_START( kbash, toaplan2_state )
MCFG_CPU_ADD("audiocpu", V25, XTAL_16MHz) /* NEC V25 type Toaplan marked CPU ??? */
MCFG_CPU_PROGRAM_MAP(kbash_v25_mem)
MCFG_V25_CONFIG(nitro_decryption_table)
- MCFG_V25_PORT_PT_READ_CB(IOPORT("DSWA")) MCFG_DEVCB_XOR(0xff)
- MCFG_V25_PORT_P0_READ_CB(IOPORT("DSWB")) MCFG_DEVCB_XOR(0xff)
- MCFG_V25_PORT_P1_READ_CB(IOPORT("JMPR")) MCFG_DEVCB_XOR(0xff)
+ MCFG_V25_PORT_PT_READ_CB(IOPORT("DSWA")) MCFG_DEVCB_XOR(0xff)
+ MCFG_V25_PORT_P0_READ_CB(IOPORT("DSWB")) MCFG_DEVCB_XOR(0xff)
+ MCFG_V25_PORT_P1_READ_CB(IOPORT("JMPR")) MCFG_DEVCB_XOR(0xff)
MCFG_V25_PORT_P2_WRITE_CB(NOOP) // bit 0 is FAULT according to kbash schematic
MCFG_MACHINE_START_OVERRIDE(toaplan2_state,toaplan2)
@@ -3569,9 +3569,9 @@ static MACHINE_CONFIG_START( vfive, toaplan2_state )
MCFG_CPU_ADD("audiocpu", V25, XTAL_20MHz/2) /* Verified on pcb, NEC V25 type Toaplan mark scratched out */
MCFG_CPU_PROGRAM_MAP(vfive_v25_mem)
MCFG_V25_CONFIG(nitro_decryption_table)
- MCFG_V25_PORT_PT_READ_CB(IOPORT("DSWA")) MCFG_DEVCB_XOR(0xff)
- MCFG_V25_PORT_P0_READ_CB(IOPORT("DSWB")) MCFG_DEVCB_XOR(0xff)
- MCFG_V25_PORT_P1_READ_CB(IOPORT("JMPR")) MCFG_DEVCB_XOR(0xff)
+ MCFG_V25_PORT_PT_READ_CB(IOPORT("DSWA")) MCFG_DEVCB_XOR(0xff)
+ MCFG_V25_PORT_P0_READ_CB(IOPORT("DSWB")) MCFG_DEVCB_XOR(0xff)
+ MCFG_V25_PORT_P1_READ_CB(IOPORT("JMPR")) MCFG_DEVCB_XOR(0xff)
MCFG_V25_PORT_P2_WRITE_CB(NOOP) // bit 0 is FAULT according to kbash schematic
MCFG_MACHINE_START_OVERRIDE(toaplan2_state,toaplan2)
@@ -3609,9 +3609,9 @@ static MACHINE_CONFIG_START( batsugun, toaplan2_state )
MCFG_CPU_ADD("audiocpu", V25, XTAL_32MHz/2) /* NEC V25 type Toaplan marked CPU ??? */
MCFG_CPU_PROGRAM_MAP(v25_mem)
- MCFG_V25_PORT_PT_READ_CB(IOPORT("DSWA")) MCFG_DEVCB_XOR(0xff)
- MCFG_V25_PORT_P0_READ_CB(IOPORT("DSWB")) MCFG_DEVCB_XOR(0xff)
- MCFG_V25_PORT_P1_READ_CB(IOPORT("JMPR")) MCFG_DEVCB_XOR(0xff)
+ MCFG_V25_PORT_PT_READ_CB(IOPORT("DSWA")) MCFG_DEVCB_XOR(0xff)
+ MCFG_V25_PORT_P0_READ_CB(IOPORT("DSWB")) MCFG_DEVCB_XOR(0xff)
+ MCFG_V25_PORT_P1_READ_CB(IOPORT("JMPR")) MCFG_DEVCB_XOR(0xff)
MCFG_V25_PORT_P2_WRITE_CB(NOOP) // bit 0 is FAULT according to kbash schematic
MCFG_MACHINE_START_OVERRIDE(toaplan2_state,toaplan2)
diff --git a/src/mame/drivers/toratora.cpp b/src/mame/drivers/toratora.cpp
index a3b1b92cedc..8bdea76b5ca 100644
--- a/src/mame/drivers/toratora.cpp
+++ b/src/mame/drivers/toratora.cpp
@@ -9,23 +9,23 @@ driver by Nicola Salmoria, qwijibo
deviations from schematics verified on set 2 pcb:
main pcb:
- - U33.3 connected to /IRQ line via inverter U67.9,
- providing timer IRQ for input polling.
+ - U33.3 connected to /IRQ line via inverter U67.9,
+ providing timer IRQ for input polling.
- - U43 removed from timer circuit, U52.9 wired directly to
- U32.5, increasing timer frequency to 250 Hz.
+ - U43 removed from timer circuit, U52.9 wired directly to
+ U32.5, increasing timer frequency to 250 Hz.
audio pcb:
- - U6.10 wired to U14.21, cut from R14/16
- - R16 wired to R1 in series, R1 cut from GND
- - R14 wired to GND instead of U6.10
+ - U6.10 wired to U14.21, cut from R14/16
+ - R16 wired to R1 in series, R1 cut from GND
+ - R14 wired to GND instead of U6.10
- - U5.10 wired to U15.21, cut from R13/15
- - R15 wired to R2 in series, R2 cut from GND
- - R13 wired to GND instead of U5.10
+ - U5.10 wired to U15.21, cut from R13/15
+ - R15 wired to R2 in series, R2 cut from GND
+ - R13 wired to GND instead of U5.10
- - EXT VCO DACs (U11, U12) and surrounding logic not placed
- - Numerous changes to SN74677 timing component R & C values
+ - EXT VCO DACs (U11, U12) and surrounding logic not placed
+ - Numerous changes to SN74677 timing component R & C values
TODO:
- The game reads some unmapped memory addresses, missing ROMs? There's an empty
diff --git a/src/mame/drivers/vegas.cpp b/src/mame/drivers/vegas.cpp
index aa3b43d4d25..71bfa6e06de 100644
--- a/src/mame/drivers/vegas.cpp
+++ b/src/mame/drivers/vegas.cpp
@@ -1057,7 +1057,7 @@ READ32_MEMBER( vegas_state::nile_r )
if (m_nile_regs[offset - 1] & 1)
{
//if (m_nile_regs[offset - 1] & 2)
- // logerror("Unexpected value: timer %d is prescaled\n", which);
+ // logerror("Unexpected value: timer %d is prescaled\n", which);
UINT32 scale = 1;
if (m_nile_regs[offset - 1] & 2) {
UINT32 scaleSrc = (m_nile_regs[offset - 1] >> 2) & 0x3;
@@ -1192,7 +1192,7 @@ WRITE32_MEMBER( vegas_state::nile_w )
{
UINT32 scale = m_nile_regs[offset - 1];
//if (m_nile_regs[offset] & 2)
- // logerror("Unexpected value: timer %d is prescaled\n", which);
+ // logerror("Unexpected value: timer %d is prescaled\n", which);
if (m_nile_regs[offset] & 2) {
UINT32 scaleSrc = (m_nile_regs[offset] >> 2) & 0x3;
scale *= m_nile_regs[NREG_T0CTRL + scaleSrc * 4];
@@ -1207,7 +1207,7 @@ WRITE32_MEMBER( vegas_state::nile_w )
else if ((olddata & 1) && !(m_nile_regs[offset] & 1))
{
//if (m_nile_regs[offset] & 2)
- // logerror("Unexpected value: timer %d is prescaled\n", which);
+ // logerror("Unexpected value: timer %d is prescaled\n", which);
UINT32 scale = 1;
if (m_nile_regs[offset] & 2) {
UINT32 scaleSrc = (m_nile_regs[offset] >> 2) & 0x3;
@@ -1230,7 +1230,7 @@ WRITE32_MEMBER( vegas_state::nile_w )
if (m_nile_regs[offset - 1] & 1)
{
//if (m_nile_regs[offset - 1] & 2)
- // logerror("Unexpected value: timer %d is prescaled\n", which);
+ // logerror("Unexpected value: timer %d is prescaled\n", which);
UINT32 scale = 1;
if (m_nile_regs[offset - 1] & 2) {
UINT32 scaleSrc = (m_nile_regs[offset - 1] >> 2) & 0x3;
diff --git a/src/mame/drivers/vsmilepro.cpp b/src/mame/drivers/vsmilepro.cpp
index a591f729882..a5110e4891f 100644
--- a/src/mame/drivers/vsmilepro.cpp
+++ b/src/mame/drivers/vsmilepro.cpp
@@ -6,13 +6,13 @@
30/05/2016
- Some information about the hardware can be found at
-
- http://www.x86-secret.com/dossier-64-VTech_V_Smile_Pro.html
+ Some information about the hardware can be found at
+ http://www.x86-secret.com/dossier-64-VTech_V_Smile_Pro.html
- In particular
- - It uses a LSI Zevio 1020 CPU + peripherals which comprises ARM926EJ-S CPU,
+
+ In particular
+ - It uses a LSI Zevio 1020 CPU + peripherals which comprises ARM926EJ-S CPU,
ZSP400 DPS, 3D graphics processor & 2D graphics processor
- The CD controller is a Sony CXD3059AR
diff --git a/src/mame/drivers/x1.cpp b/src/mame/drivers/x1.cpp
index cee20b3fbea..741f93a5c02 100644
--- a/src/mame/drivers/x1.cpp
+++ b/src/mame/drivers/x1.cpp
@@ -62,7 +62,7 @@
[0x01 to 0x0d] ROM header, i.e. title for the loader
[0x12 - 0x13] initial copy size
[0x14 - 0x15] destination address start address
- [0x16 to 0x17] start boot jump vector
+ [0x16 to 0x17] start boot jump vector
[0x1d to 0x1f] start boot data vector
- Gruppe: shows a random bitmap graphic then returns "program load error" ... it wants that the floppy has write protection enabled (!) (btanb)
- Maidum: you need to load BOTH disk with write protection disabled, otherwise it refuses to run. (btanb)
diff --git a/src/mame/includes/aerofgt.h b/src/mame/includes/aerofgt.h
index 75e9d14053e..85661959bdf 100644
--- a/src/mame/includes/aerofgt.h
+++ b/src/mame/includes/aerofgt.h
@@ -52,7 +52,7 @@ public:
optional_device<vsystem_spr2_device> m_spr_old; // every other (non-bootleg) uses this
optional_device<vsystem_spr2_device> m_spr_old2; // or a pair of them..
optional_device<generic_latch_8_device> m_soundlatch;
-
+
/* video-related */
diff --git a/src/mame/includes/atarigx2.h b/src/mame/includes/atarigx2.h
index 1cf61d8ecac..678b9c19b22 100644
--- a/src/mame/includes/atarigx2.h
+++ b/src/mame/includes/atarigx2.h
@@ -17,7 +17,7 @@ public:
atarigx2_state(const machine_config &mconfig, device_type type, const char *tag)
: atarigen_state(mconfig, type, tag),
m_jsa(*this, "jsa"),
- m_xga(*this, "xga"),
+ m_xga(*this, "xga"),
m_mo_command(*this, "mo_command"),
m_playfield_tilemap(*this, "playfield"),
m_alpha_tilemap(*this, "alpha"),
@@ -27,7 +27,7 @@ public:
UINT16 m_playfield_base;
required_device<atari_jsa_iiis_device> m_jsa;
- required_device<atari_xga_device> m_xga;
+ required_device<atari_xga_device> m_xga;
required_shared_ptr<UINT32> m_mo_command;
@@ -41,10 +41,10 @@ public:
UINT16 m_playfield_xscroll;
UINT16 m_playfield_yscroll;
- // LEGACY PROTECTION
+ // LEGACY PROTECTION
UINT16 m_last_write;
UINT16 m_last_write_offset;
- UINT32 m_protection_ram[0x1000];
+ UINT32 m_protection_ram[0x1000];
virtual void update_interrupts() override;
virtual void scanline_update(screen_device &screen, int scanline) override;
diff --git a/src/mame/includes/divebomb.h b/src/mame/includes/divebomb.h
index b254be2b5d0..c79a3774093 100644
--- a/src/mame/includes/divebomb.h
+++ b/src/mame/includes/divebomb.h
@@ -15,77 +15,77 @@
class divebomb_state : public driver_device
{
public:
- divebomb_state(const machine_config &mconfig, device_type type, const char *tag)
- : driver_device(mconfig, type, tag),
- m_spritecpu(*this, "spritecpu"),
- m_fgcpu(*this, "fgcpu"),
- m_rozcpucpu(*this, "rozcpu"),
- m_bank1(*this, "bank1"),
- m_fgram(*this, "fgram"),
- m_spriteram(*this, "spriteram"),
- m_gfxdecode(*this, "gfxdecode"),
- m_palette(*this, "palette"),
- m_k051316_1(*this, "k051316_1"),
- m_k051316_2(*this, "k051316_2")
- { }
-
- required_device<cpu_device> m_spritecpu;
- required_device<cpu_device> m_fgcpu;
- required_device<cpu_device> m_rozcpucpu;
- required_memory_bank m_bank1;
- required_shared_ptr<UINT8> m_fgram;
- required_shared_ptr<UINT8> m_spriteram;
- required_device<gfxdecode_device> m_gfxdecode;
- required_device<palette_device> m_palette;
- required_device<k051316_device> m_k051316_1;
- required_device<k051316_device> m_k051316_2;
-
- tilemap_t *m_fg_tilemap;
- UINT8 to_spritecpu;
- UINT8 to_rozcpu;
- UINT8 from_sprite;
- UINT8 from_roz;
- bool has_fromsprite;
- bool has_fromroz;
+ divebomb_state(const machine_config &mconfig, device_type type, const char *tag)
+ : driver_device(mconfig, type, tag),
+ m_spritecpu(*this, "spritecpu"),
+ m_fgcpu(*this, "fgcpu"),
+ m_rozcpucpu(*this, "rozcpu"),
+ m_bank1(*this, "bank1"),
+ m_fgram(*this, "fgram"),
+ m_spriteram(*this, "spriteram"),
+ m_gfxdecode(*this, "gfxdecode"),
+ m_palette(*this, "palette"),
+ m_k051316_1(*this, "k051316_1"),
+ m_k051316_2(*this, "k051316_2")
+ { }
- UINT8 roz_pal;
- bool roz1_enable;
- bool roz2_enable;
- bool roz1_wrap;
- bool roz2_wrap;
-
- DECLARE_MACHINE_RESET(divebomb);
- DECLARE_MACHINE_START(divebomb);
- DECLARE_VIDEO_START(divebomb);
- DECLARE_PALETTE_INIT(divebomb);
+ required_device<cpu_device> m_spritecpu;
+ required_device<cpu_device> m_fgcpu;
+ required_device<cpu_device> m_rozcpucpu;
+ required_memory_bank m_bank1;
+ required_shared_ptr<UINT8> m_fgram;
+ required_shared_ptr<UINT8> m_spriteram;
+ required_device<gfxdecode_device> m_gfxdecode;
+ required_device<palette_device> m_palette;
+ required_device<k051316_device> m_k051316_1;
+ required_device<k051316_device> m_k051316_2;
- void update_irqs();
- void draw_sprites(bitmap_ind16 &bitmap, const rectangle &cliprect);
- void decode_proms(const UINT8* rgn, int size, int index, bool inv);
- UINT32 screen_update_divebomb(screen_device &screen, bitmap_ind16 &bitmap, const rectangle &cliprect);
-
- K051316_CB_MEMBER(zoom_callback_1);
- K051316_CB_MEMBER(zoom_callback_2);
-
- TILE_GET_INFO_MEMBER(get_fg_tile_info);
+ tilemap_t *m_fg_tilemap;
+ UINT8 to_spritecpu;
+ UINT8 to_rozcpu;
+ UINT8 from_sprite;
+ UINT8 from_roz;
+ bool has_fromsprite;
+ bool has_fromroz;
- DECLARE_READ8_MEMBER(fgcpu_roz_comm_r);
- DECLARE_WRITE8_MEMBER(fgcpu_roz_comm_w);
- DECLARE_READ8_MEMBER(fgcpu_spr_comm_r);
- DECLARE_WRITE8_MEMBER(fgcpu_spr_comm_w);
- DECLARE_READ8_MEMBER(fgcpu_comm_flags_r);
- DECLARE_WRITE8_MEMBER(fgram_w);
-
- DECLARE_WRITE8_MEMBER(spritecpu_port00_w);
- DECLARE_READ8_MEMBER(spritecpu_comm_r);
- DECLARE_WRITE8_MEMBER(spritecpu_comm_w);
-
- DECLARE_WRITE8_MEMBER(rozcpu_bank_w);
- DECLARE_WRITE8_MEMBER(rozcpu_wrap1_enable_w);
- DECLARE_WRITE8_MEMBER(rozcpu_enable1_w);
- DECLARE_WRITE8_MEMBER(rozcpu_enable2_w);
- DECLARE_WRITE8_MEMBER(rozcpu_wrap2_enable_w);
- DECLARE_READ8_MEMBER(rozcpu_comm_r);
- DECLARE_WRITE8_MEMBER(rozcpu_comm_w);
- DECLARE_WRITE8_MEMBER(rozcpu_pal_w);
+ UINT8 roz_pal;
+ bool roz1_enable;
+ bool roz2_enable;
+ bool roz1_wrap;
+ bool roz2_wrap;
+
+ DECLARE_MACHINE_RESET(divebomb);
+ DECLARE_MACHINE_START(divebomb);
+ DECLARE_VIDEO_START(divebomb);
+ DECLARE_PALETTE_INIT(divebomb);
+
+ void update_irqs();
+ void draw_sprites(bitmap_ind16 &bitmap, const rectangle &cliprect);
+ void decode_proms(const UINT8* rgn, int size, int index, bool inv);
+ UINT32 screen_update_divebomb(screen_device &screen, bitmap_ind16 &bitmap, const rectangle &cliprect);
+
+ K051316_CB_MEMBER(zoom_callback_1);
+ K051316_CB_MEMBER(zoom_callback_2);
+
+ TILE_GET_INFO_MEMBER(get_fg_tile_info);
+
+ DECLARE_READ8_MEMBER(fgcpu_roz_comm_r);
+ DECLARE_WRITE8_MEMBER(fgcpu_roz_comm_w);
+ DECLARE_READ8_MEMBER(fgcpu_spr_comm_r);
+ DECLARE_WRITE8_MEMBER(fgcpu_spr_comm_w);
+ DECLARE_READ8_MEMBER(fgcpu_comm_flags_r);
+ DECLARE_WRITE8_MEMBER(fgram_w);
+
+ DECLARE_WRITE8_MEMBER(spritecpu_port00_w);
+ DECLARE_READ8_MEMBER(spritecpu_comm_r);
+ DECLARE_WRITE8_MEMBER(spritecpu_comm_w);
+
+ DECLARE_WRITE8_MEMBER(rozcpu_bank_w);
+ DECLARE_WRITE8_MEMBER(rozcpu_wrap1_enable_w);
+ DECLARE_WRITE8_MEMBER(rozcpu_enable1_w);
+ DECLARE_WRITE8_MEMBER(rozcpu_enable2_w);
+ DECLARE_WRITE8_MEMBER(rozcpu_wrap2_enable_w);
+ DECLARE_READ8_MEMBER(rozcpu_comm_r);
+ DECLARE_WRITE8_MEMBER(rozcpu_comm_w);
+ DECLARE_WRITE8_MEMBER(rozcpu_pal_w);
};
diff --git a/src/mame/includes/gameplan.h b/src/mame/includes/gameplan.h
index f668b23d338..b3968301d1e 100644
--- a/src/mame/includes/gameplan.h
+++ b/src/mame/includes/gameplan.h
@@ -70,7 +70,7 @@ public:
required_device<screen_device> m_screen;
optional_device<generic_latch_8_device> m_soundlatch;
-
+
DECLARE_WRITE8_MEMBER(io_select_w);
DECLARE_READ8_MEMBER(io_port_r);
DECLARE_WRITE_LINE_MEMBER(coin_w);
diff --git a/src/mame/includes/megasys1.h b/src/mame/includes/megasys1.h
index dcd8a6f5269..1e52cfc056c 100644
--- a/src/mame/includes/megasys1.h
+++ b/src/mame/includes/megasys1.h
@@ -143,7 +143,7 @@ public:
DECLARE_DRIVER_INIT(avspirit);
DECLARE_DRIVER_INIT(monkelf);
DECLARE_DRIVER_INIT(edf);
- DECLARE_DRIVER_INIT(edfp);
+ DECLARE_DRIVER_INIT(edfp);
DECLARE_DRIVER_INIT(bigstrik);
DECLARE_DRIVER_INIT(rodland);
DECLARE_DRIVER_INIT(edfbl);
diff --git a/src/mame/includes/namconb1.h b/src/mame/includes/namconb1.h
index e3f065361dc..9aeb6ddc251 100644
--- a/src/mame/includes/namconb1.h
+++ b/src/mame/includes/namconb1.h
@@ -95,7 +95,7 @@ public:
UINT32 screen_update_namconb2(screen_device &screen, bitmap_ind16 &bitmap, const rectangle &cliprect);
TIMER_DEVICE_CALLBACK_MEMBER(scantimer);
-
+
int NB1objcode2tile(int code);
int NB2objcode2tile(int code);
};
diff --git a/src/mame/includes/nmk16.h b/src/mame/includes/nmk16.h
index 5ec3b51de31..91fd9563305 100644
--- a/src/mame/includes/nmk16.h
+++ b/src/mame/includes/nmk16.h
@@ -56,7 +56,7 @@ public:
optional_shared_ptr<UINT16> m_nmk_bgvideoram3;
optional_shared_ptr<UINT16> m_afega_scroll_0;
optional_shared_ptr<UINT16> m_afega_scroll_1;
-
+
int m_sprdma_base;
int mask[4*2];
diff --git a/src/mame/includes/plygonet.h b/src/mame/includes/plygonet.h
index 5b71fa27476..020cbe7621b 100644
--- a/src/mame/includes/plygonet.h
+++ b/src/mame/includes/plygonet.h
@@ -43,7 +43,7 @@ public:
required_device<generic_latch_8_device> m_soundlatch;
required_device<generic_latch_8_device> m_soundlatch2;
required_device<generic_latch_8_device> m_soundlatch3;
-
+
/* 68k-side shared ram */
required_shared_ptr<UINT32> m_shared_ram;
diff --git a/src/mame/includes/sg1000.h b/src/mame/includes/sg1000.h
index 6e496fed31b..efa24e6c683 100644
--- a/src/mame/includes/sg1000.h
+++ b/src/mame/includes/sg1000.h
@@ -77,7 +77,7 @@ public:
: sg1000_state(mconfig, type, tag)
{ }
- virtual void machine_start() override;
+ virtual void machine_start() override;
};
class sf7000_state : public sc3000_state
diff --git a/src/mame/includes/tsamurai.h b/src/mame/includes/tsamurai.h
index cd371126147..5d29d9e4d27 100644
--- a/src/mame/includes/tsamurai.h
+++ b/src/mame/includes/tsamurai.h
@@ -26,7 +26,7 @@ public:
optional_device<cpu_device> m_audio3;
required_device<gfxdecode_device> m_gfxdecode;
required_device<palette_device> m_palette;
- optional_device<generic_latch_8_device> m_soundlatch; // vsgongf only
+ optional_device<generic_latch_8_device> m_soundlatch; // vsgongf only
required_shared_ptr<UINT8> m_videoram;
optional_shared_ptr<UINT8> m_colorram;
diff --git a/src/mame/layout/patinho.lay b/src/mame/layout/patinho.lay
index 7c6296034bf..768b8283ac3 100644
--- a/src/mame/layout/patinho.lay
+++ b/src/mame/layout/patinho.lay
@@ -26,117 +26,117 @@
</disk>
</element>
- <element name="rectangle">
- <rect>
- <color red="0.3" green="0.9" blue="0.6" />
- </rect>
- </element>
-
- <element name="str_flags_t">
- <text string="TRANSBORDO">
- <color red="0" green="0" blue="0" /></text>
- </element>
-
- <element name="str_flags_v">
- <text string="VAI - UM">
- <color red="0" green="0" blue="0" /></text>
- </element>
-
- <element name="str_ula">
- <text string="UNIDADE ARITMETICA E LÓGICA" >
- <color red="0" green="0" blue="0" /></text>
- </element>
-
- <element name="str_rc">
- <text string="DADOS DO PAINEL">
- <color red="0" green="0" blue="0" /></text>
- </element>
-
- <element name="str_pc">
- <text string="ENDEREÇO DE INSTRUÇÃO">
- <color red="0" green="0" blue="0" /></text>
- </element>
-
- <element name="str_mem_addr">
- <text string="ENDEREÇO DA MEMÓRIA">
- <color red="0" green="0" blue="0" /></text>
- </element>
-
- <element name="str_acc">
- <text string="ACUMULADOR">
- <color red="0" green="0" blue="0" /></text>
- </element>
-
- <element name="str_opcode">
- <text string="CÓDIGO DE INSTRUÇÃO">
- <color red="0" green="0" blue="0" /></text>
- </element>
-
- <element name="str_mem_data">
- <text string="DADOS DA MEMÓRIA">
- <color red="0" green="0" blue="0" /></text>
- </element>
-
- <element name="str_mem">
- <text string="MEMÓRIA">
- <color red="0" green="0" blue="0" /></text>
- </element>
-
-
- <element name="str_NORMAL">
- <text string="NORMAL">
- <color red="0" green="0" blue="0" /></text>
- </element>
-
-
- <element name="str_CICLOUNICO">
- <text string="CICLO
-ÚNICO">
- <color red="0" green="0" blue="0" /></text>
- </element>
-
- <element name="str_INSTRUCAOUNICA">
- <text string="INSTRUÇÃO
-ÚNICA">
- <color red="0" green="0" blue="0" /></text>
- </element>
-
- <element name="str_ENDERECAMENTO">
- <text string="ENDEREÇAMENTO">
- <color red="0" green="0" blue="0" /></text>
- </element>
-
- <element name="str_ARMAZENAMENTO">
- <text string="ARMAZENAMENTO">
- <color red="0" green="0" blue="0" /></text>
- </element>
-
- <element name="str_EXPOSICAO">
- <text string="EXPOSIÇÃO">
- <color red="0" green="0" blue="0" /></text>
- </element>
-
-
-
- <element name="str_ESPERA">
- <text string="ESPERA">
- <color red="0" green="0" blue="0" /></text>
- </element>
-
- <element name="str_INTERRUPCAO">
- <text string="INTERRUPÇÃO">
- <color red="0" green="0" blue="0" /></text>
- </element>
-
- <element name="str_PARTIDA">
- <text string="PARTIDA">
- <color red="0" green="0" blue="0" /></text>
- </element>
-
- <element name="str_PREPARACAO">
- <text string="PREPARAÇÃO">
- <color red="0" green="0" blue="0" /></text>
- </element>
+ <element name="rectangle">
+ <rect>
+ <color red="0.3" green="0.9" blue="0.6" />
+ </rect>
+ </element>
+
+ <element name="str_flags_t">
+ <text string="TRANSBORDO">
+ <color red="0" green="0" blue="0" /></text>
+ </element>
+
+ <element name="str_flags_v">
+ <text string="VAI - UM">
+ <color red="0" green="0" blue="0" /></text>
+ </element>
+
+ <element name="str_ula">
+ <text string="UNIDADE ARITMETICA E LOGICA" >
+ <color red="0" green="0" blue="0" /></text>
+ </element>
+
+ <element name="str_rc">
+ <text string="DADOS DO PAINEL">
+ <color red="0" green="0" blue="0" /></text>
+ </element>
+
+ <element name="str_pc">
+ <text string="ENDERECO DE INSTRUCAO">
+ <color red="0" green="0" blue="0" /></text>
+ </element>
+
+ <element name="str_mem_addr">
+ <text string="ENDERECO DA MEMORIA">
+ <color red="0" green="0" blue="0" /></text>
+ </element>
+
+ <element name="str_acc">
+ <text string="ACUMULADOR">
+ <color red="0" green="0" blue="0" /></text>
+ </element>
+
+ <element name="str_opcode">
+ <text string="CODIGO DE INSTRUCAO">
+ <color red="0" green="0" blue="0" /></text>
+ </element>
+
+ <element name="str_mem_data">
+ <text string="DADOS DA MEMORIA">
+ <color red="0" green="0" blue="0" /></text>
+ </element>
+
+ <element name="str_mem">
+ <text string="MEMORIA">
+ <color red="0" green="0" blue="0" /></text>
+ </element>
+
+
+ <element name="str_NORMAL">
+ <text string="NORMAL">
+ <color red="0" green="0" blue="0" /></text>
+ </element>
+
+
+ <element name="str_CICLOUNICO">
+ <text string="CICLO
+UNICO">
+ <color red="0" green="0" blue="0" /></text>
+ </element>
+
+ <element name="str_INSTRUCAOUNICA">
+ <text string="INSTRUCAO
+UNICA">
+ <color red="0" green="0" blue="0" /></text>
+ </element>
+
+ <element name="str_ENDERECAMENTO">
+ <text string="ENDERECAMENTO">
+ <color red="0" green="0" blue="0" /></text>
+ </element>
+
+ <element name="str_ARMAZENAMENTO">
+ <text string="ARMAZENAMENTO">
+ <color red="0" green="0" blue="0" /></text>
+ </element>
+
+ <element name="str_EXPOSICAO">
+ <text string="EXPOSICAO">
+ <color red="0" green="0" blue="0" /></text>
+ </element>
+
+
+
+ <element name="str_ESPERA">
+ <text string="ESPERA">
+ <color red="0" green="0" blue="0" /></text>
+ </element>
+
+ <element name="str_INTERRUPCAO">
+ <text string="INTERRUP????O">
+ <color red="0" green="0" blue="0" /></text>
+ </element>
+
+ <element name="str_PARTIDA">
+ <text string="PARTIDA">
+ <color red="0" green="0" blue="0" /></text>
+ </element>
+
+ <element name="str_PREPARACAO">
+ <text string="PREPARACAO">
+ <color red="0" green="0" blue="0" /></text>
+ </element>
<!-- define background -->
@@ -148,7 +148,7 @@
<!-- define lamps -->
<bezel element="rectangle">
- <bounds x="150" y="100" width="625" height="450" />
+ <bounds x="150" y="100" width="625" height="450" />
</bezel>
<bezel name="mem_data7" element="bit_lamp" inputtag="mem_data" inputmask="0x080">
@@ -184,7 +184,7 @@
</bezel>
<bezel element="str_mem_data">
- <bounds x="200" y="470" width="200" height="20" />
+ <bounds x="200" y="470" width="200" height="20" />
</bezel>
<bezel name="opcode7" element="bit_lamp" inputtag="opcode" inputmask="0x080">
@@ -220,7 +220,7 @@
</bezel>
<bezel element="str_opcode">
- <bounds x="200" y="370" width="200" height="20" />
+ <bounds x="200" y="370" width="200" height="20" />
</bezel>
<bezel name="acc7" element="bit_lamp" inputtag="ACC" inputmask="0x080">
@@ -256,7 +256,7 @@
</bezel>
<bezel element="str_acc">
- <bounds x="200" y="270" width="200" height="20" />
+ <bounds x="200" y="270" width="200" height="20" />
</bezel>
<bezel name="rc11" element="bit_lamp" inputtag="RC" inputmask="0x800">
@@ -308,7 +308,7 @@
</bezel>
<bezel element="str_rc">
- <bounds x="450" y="520" width="299" height="20" />
+ <bounds x="450" y="520" width="299" height="20" />
</bezel>
<bezel name="flags1" element="bit_lamp" inputtag="FLAGS" inputmask="0x002">
@@ -320,11 +320,11 @@
</bezel>
<bezel element="str_flags_t">
- <bounds x="400" y="350" width="199" height="20" />
+ <bounds x="400" y="350" width="199" height="20" />
</bezel>
<bezel element="str_flags_v">
- <bounds x="650" y="350" width="99" height="20" />
+ <bounds x="650" y="350" width="99" height="20" />
</bezel>
<bezel name="pc11" element="bit_lamp" inputtag="PC" inputmask="0x800">
@@ -376,7 +376,7 @@
</bezel>
<bezel element="str_pc">
- <bounds x="450" y="270" width="299" height="20" />
+ <bounds x="450" y="270" width="299" height="20" />
</bezel>
<bezel name="mem_addr11" element="bit_lamp" inputtag="mem_addr" inputmask="0x800">
@@ -428,7 +428,7 @@
</bezel>
<bezel element="str_mem_addr">
- <bounds x="450" y="170" width="299" height="20" />
+ <bounds x="450" y="170" width="299" height="20" />
</bezel>
<bezel name="NORMAL" element="button" inputtag="BUTTONS" inputmask="0x001">
@@ -436,7 +436,7 @@
</bezel>
<bezel element="str_NORMAL">
- <bounds x="12" y="610" width="150" height="20" />
+ <bounds x="12" y="610" width="150" height="20" />
</bezel>
<bezel name="CICLOUNICO" element="button" inputtag="BUTTONS" inputmask="0x002">
@@ -444,7 +444,7 @@
</bezel>
<bezel element="str_CICLOUNICO">
- <bounds x="162" y="610" width="150" height="20" />
+ <bounds x="162" y="610" width="150" height="20" />
</bezel>
<bezel name="INSTRUCAOUNICA" element="button" inputtag="BUTTONS" inputmask="0x004">
@@ -452,7 +452,7 @@
</bezel>
<bezel element="str_INSTRUCAOUNICA">
- <bounds x="312" y="610" width="150" height="20" />
+ <bounds x="312" y="610" width="150" height="20" />
</bezel>
<bezel name="ENDERECAMENTO" element="button" inputtag="BUTTONS" inputmask="0x008">
@@ -460,7 +460,7 @@
</bezel>
<bezel element="str_ENDERECAMENTO">
- <bounds x="462" y="610" width="150" height="20" />
+ <bounds x="462" y="610" width="150" height="20" />
</bezel>
<bezel name="ARMAZENAMENTO" element="button" inputtag="BUTTONS" inputmask="0x010">
@@ -468,7 +468,7 @@
</bezel>
<bezel element="str_ARMAZENAMENTO">
- <bounds x="612" y="610" width="150" height="20" />
+ <bounds x="612" y="610" width="150" height="20" />
</bezel>
<bezel name="EXPOSICAO" element="button" inputtag="BUTTONS" inputmask="0x020">
@@ -476,7 +476,7 @@
</bezel>
<bezel element="str_EXPOSICAO">
- <bounds x="762" y="610" width="150" height="20" />
+ <bounds x="762" y="610" width="150" height="20" />
</bezel>
<bezel name="ESPERA" element="button" inputtag="BUTTONS" inputmask="0x040">
@@ -484,7 +484,7 @@
</bezel>
<bezel element="str_ESPERA">
- <bounds x="308" y="710" width="166" height="20" />
+ <bounds x="308" y="710" width="166" height="20" />
</bezel>
<bezel name="INTERRUPCAO" element="button" inputtag="BUTTONS" inputmask="0x080">
@@ -492,7 +492,7 @@
</bezel>
<bezel element="str_INTERRUPCAO">
- <bounds x="474" y="710" width="166" height="20" />
+ <bounds x="474" y="710" width="166" height="20" />
</bezel>
<bezel name="PARTIDA" element="button" inputtag="BUTTONS" inputmask="0x100">
@@ -500,7 +500,7 @@
</bezel>
<bezel element="str_PARTIDA">
- <bounds x="641" y="710" width="166" height="20" />
+ <bounds x="641" y="710" width="166" height="20" />
</bezel>
<bezel name="PREPARACAO" element="button" inputtag="BUTTONS" inputmask="0x200">
@@ -508,7 +508,7 @@
</bezel>
<bezel element="str_PREPARACAO">
- <bounds x="808" y="710" width="166" height="20" />
+ <bounds x="808" y="710" width="166" height="20" />
</bezel>
</view>
diff --git a/src/mame/machine/atarixga.h b/src/mame/machine/atarixga.h
index 710aedb22c2..8d6980a3ac3 100644
--- a/src/mame/machine/atarixga.h
+++ b/src/mame/machine/atarixga.h
@@ -3,7 +3,7 @@
/*************************************************************************
atarixga.h
-
+
Atari XGA encryption FPGA
*************************************************************************/
@@ -16,38 +16,38 @@ extern const device_type ATARI_XGA;
class atari_xga_device : public device_t
{
public:
- // construction/destruction
- atari_xga_device(const machine_config &mconfig, const char *tag, device_t *owner, UINT32 clock);
-
- DECLARE_WRITE32_MEMBER(write);
- DECLARE_READ32_MEMBER(read);
-
+ // construction/destruction
+ atari_xga_device(const machine_config &mconfig, const char *tag, device_t *owner, UINT32 clock);
+
+ DECLARE_WRITE32_MEMBER(write);
+ DECLARE_READ32_MEMBER(read);
+
protected:
- virtual void device_start() override;
- virtual void device_reset() override;
-
+ virtual void device_start() override;
+ virtual void device_reset() override;
+
private:
- static const size_t RAM_WORDS = 2048;
-
- enum fpga_mode
- {
- FPGA_RESET,
- FPGA_SETKEY,
- FPGA_DECIPHER
- };
-
- UINT16 powers2(UINT8 k, UINT16 x);
- UINT16 lfsr2(UINT16 x);
- UINT16 lfsr1(UINT16 x);
- UINT16 parity(UINT16 x);
- size_t popcount(UINT16 x);
- UINT16 ctz(UINT16 x);
- UINT16 decipher(UINT8 k, UINT16 c);
-
- fpga_mode m_mode;
- UINT16 m_address; // last written address
- UINT16 m_ciphertext; // last written ciphertext
- std::unique_ptr<UINT16[]> m_ram; // CY7C185-45PC, only 16-Kbit used
+ static const size_t RAM_WORDS = 2048;
+
+ enum fpga_mode
+ {
+ FPGA_RESET,
+ FPGA_SETKEY,
+ FPGA_DECIPHER
+ };
+
+ UINT16 powers2(UINT8 k, UINT16 x);
+ UINT16 lfsr2(UINT16 x);
+ UINT16 lfsr1(UINT16 x);
+ UINT16 parity(UINT16 x);
+ size_t popcount(UINT16 x);
+ UINT16 ctz(UINT16 x);
+ UINT16 decipher(UINT8 k, UINT16 c);
+
+ fpga_mode m_mode;
+ UINT16 m_address; // last written address
+ UINT16 m_ciphertext; // last written ciphertext
+ std::unique_ptr<UINT16[]> m_ram; // CY7C185-45PC, only 16-Kbit used
};
diff --git a/src/mame/machine/dccons.cpp b/src/mame/machine/dccons.cpp
index 776e6d8ead2..0a0792c14d6 100644
--- a/src/mame/machine/dccons.cpp
+++ b/src/mame/machine/dccons.cpp
@@ -126,12 +126,12 @@ READ32_MEMBER(dc_cons_state::dc_mess_g1_ctrl_r )
case SB_GDLEND:
//machine().debug_break();
return atapi_xferlen; // TODO: check me
- case SB_SECUR_EADR: // always read 0xFF on hardware
+ case SB_SECUR_EADR: // always read 0xFF on hardware
return 0x000000ff;
- case SB_SECUR_STATE: // state of BIOS checksum security system (R/O):
+ case SB_SECUR_STATE: // state of BIOS checksum security system (R/O):
// 3 - check passed OK, G1 ATA (5F70xx) registers area accessible
- // 2 - check failed, G1 ATA area blocked (read FFFFFFFFh)
- // 0 - check in progress, BIOS data summed, G1 ATA area blocked (read FFFFFFFFh)
+ // 2 - check failed, G1 ATA area blocked (read FFFFFFFFh)
+ // 0 - check in progress, BIOS data summed, G1 ATA area blocked (read FFFFFFFFh)
return 3;
default:
printf("G1CTRL: Unmapped read %08x\n", 0x5f7400+offset*4);
@@ -185,10 +185,10 @@ WRITE32_MEMBER(dc_cons_state::dc_mess_g1_ctrl_w )
if values doesn't match - security system switch to state 2 (check fail):
- G1 ATA locked
- - can be switched to state 0 by write to SB_SECUR_EADR register, however passing valid data block through security system set it back to state 2
+ - can be switched to state 0 by write to SB_SECUR_EADR register, however passing valid data block through security system set it back to state 2
- the only exit from this state - power off/on or reset;
- current state can be read from SB_SECUR_STATE register
+ current state can be read from SB_SECUR_STATE register
actual checksum algorithm is unknown, but its supposed to be simple and weak,
known few modded BIOSes which succesfully passes this CRC check, because of good luck
diff --git a/src/mame/machine/dec_lk201.cpp b/src/mame/machine/dec_lk201.cpp
index 353856f928c..0ba3d6a0fdc 100644
--- a/src/mame/machine/dec_lk201.cpp
+++ b/src/mame/machine/dec_lk201.cpp
@@ -3,7 +3,7 @@
/*
DEC LK-201 keyboard
Emulation by R. Belmont & M. Burke
-with contributions by Cracyc and Karl-Ludwig Deisenhofer (2016)
+with contributions by Cracyc and Karl-Ludwig Deisenhofer (2016)
This is the later "cost-reduced" 6805 version with green LEDs; there's also an 8048 version.
The LK-201 mechanical elements are described in US Patent 4,467,150
@@ -181,10 +181,10 @@ const device_type LK201 = &device_creator<lk201_device>;
ROM_START( lk201 )
ROM_REGION(0x2000, LK201_CPU_TAG, 0)
-// 23-001s9-00.bin is for the newer LK201 version (green LEDs, Motorola 6805)
+// 23-001s9-00.bin is for the newer LK201 version (green LEDs, Motorola 6805)
ROM_LOAD( "23-001s9-00.bin", 0x0000, 0x2000, CRC(be293c51) SHA1(a11ae004d2d6055d7279da3560c3e56610a19fdb) )
-// 23-004M1 or 23-004M2 are in the older LK201 keyboard with red LEDs (8051)
+// 23-004M1 or 23-004M2 are in the older LK201 keyboard with red LEDs (8051)
ROM_END
@@ -541,10 +541,10 @@ void lk201_device::device_timer(emu_timer &timer, device_timer_id id, int param,
{
switch (id)
{
- case 1:
- m_timer.tsr |= TSR_OCFL;
+ case 1:
+ m_timer.tsr |= TSR_OCFL;
- if ((m_timer.tcr & TCR_OCIE) && (m_timer.tsr & TSR_OCFL))
+ if ((m_timer.tcr & TCR_OCIE) && (m_timer.tsr & TSR_OCFL))
m_maincpu->set_input_line(M68HC05EG_INT_TIMER, ASSERT_LINE);
break;
@@ -567,7 +567,7 @@ void lk201_device::rcv_complete()
int data = get_received_char();
m_kbd_state = data;
-// printf("\nlk201 got %02x\n", m_kbd_state);
+// printf("\nlk201 got %02x\n", m_kbd_state);
}
void lk201_device::tra_complete()
@@ -602,7 +602,7 @@ READ8_MEMBER( lk201_device::timer_r )
switch (offset)
{
case 8: // ACRH (high value is stored and reused when reading low)
- count = (m_maincpu->total_cycles() / 4) & 0x0000ffff;
+ count = (m_maincpu->total_cycles() / 4) & 0x0000ffff;
ret = count >> 8;
break;
case 9: // ACRL
@@ -637,7 +637,7 @@ WRITE8_MEMBER( lk201_device::timer_w )
count |= m_timer.ocrl;
m_timer.ocrh = count >> 8;
- m_timer.tsr = save_tsr; // restore flags
+ m_timer.tsr = save_tsr; // restore flags
break;
}
}
@@ -675,7 +675,7 @@ WRITE8_MEMBER( lk201_device::ports_w )
UINT8 olddata = ports[offset];
ports[offset] = data; // "port writes are independent of DDRC"
send_port(space, offset, olddata & ddrs[offset]);
-// printf("\nPORT %c write %02x (OLD = %02x) (DDR = %02x) (PC=%x)\n", 'A' + offset, data, olddata, ddrs[offset], m_maincpu->pc());
+// printf("\nPORT %c write %02x (OLD = %02x) (DDR = %02x) (PC=%x)\n", 'A' + offset, data, olddata, ddrs[offset], m_maincpu->pc());
}
void lk201_device::send_port(address_space &space, UINT8 offset, UINT8 olddata)
@@ -719,8 +719,8 @@ void lk201_device::send_port(address_space &space, UINT8 offset, UINT8 olddata)
// Check for LED update strobe
if (((portc & 0x80) == 0) && (olddata & 0x80))
{
- if(ddrs[2] != 0x00)
- { // Lower nibble contains the LED values (1 = on, 0 = off)
+ if(ddrs[2] != 0x00)
+ { // Lower nibble contains the LED values (1 = on, 0 = off)
machine().output().set_value("led_wait" , (led_data & 0x1) == 1);
machine().output().set_value("led_compose", (led_data & 0x2) == 2);
machine().output().set_value("led_lock" , (led_data & 0x4) == 4);
@@ -731,11 +731,11 @@ void lk201_device::send_port(address_space &space, UINT8 offset, UINT8 olddata)
m_speaker->set_state(1);
// Beeps < 20 ms are clipped. A key click on a LK201 lasts 2 ms...
if(m_kbd_state == LK_CMD_BELL)
- m_beeper->adjust(attotime::from_msec(125));
- else
+ m_beeper->adjust(attotime::from_msec(125));
+ else
m_beeper->adjust(attotime::from_msec(25)); // see note
}
- // Upper 4 bits of LED_DATA contain encoded volume info
+ // Upper 4 bits of LED_DATA contain encoded volume info
switch (led_data & 0xf0)
{
case 0xf0: // 8 - (see TABLE 4 in 68HC05xx ROM)
@@ -765,10 +765,10 @@ void lk201_device::send_port(address_space &space, UINT8 offset, UINT8 olddata)
default:
;
} // switch (volume)
-
+
} // if (update_strobe)
-
- } // outer switch
+
+ } // outer switch
}
READ8_MEMBER( lk201_device::sci_r )
diff --git a/src/mame/machine/dec_lk201.h b/src/mame/machine/dec_lk201.h
index 1df36577b7b..3185a0a139f 100644
--- a/src/mame/machine/dec_lk201.h
+++ b/src/mame/machine/dec_lk201.h
@@ -24,12 +24,12 @@
#define LK_CMD_ENB_BELL 0x23 /* enable the bell - 1st param: volume */
#define LK_CMD_BELL 0xa7 /* emit a bell - 1st param: volume */
-// TCR - Timer Compare Register
+// TCR - Timer Compare Register
#define TCR_OCIE 0x40 // Bit 6 (output compare IRQ enable)
-#define TCR_OLVL 0x01 // Bit 1 (output level)
+#define TCR_OLVL 0x01 // Bit 1 (output level)
-// TSR - Timer Status Register
-#define TSR_OCFL 0x40 // TSR (68HC05 output compare flag)
+// TSR - Timer Status Register
+#define TSR_OCFL 0x40 // TSR (68HC05 output compare flag)
//**************************************************************************
// INTERFACE CONFIGURATION MACROS
diff --git a/src/mame/machine/fd1094.cpp b/src/mame/machine/fd1094.cpp
index ed358b97cc2..4a37174d306 100644
--- a/src/mame/machine/fd1094.cpp
+++ b/src/mame/machine/fd1094.cpp
@@ -816,7 +816,7 @@ UINT16 fd1094_device::decrypt_one(offs_t address, UINT16 val, const UINT8 *main_
val = BITSWAP16(val, 15, 9,10,13, 3,12, 0,14, 6, 5, 2,11, 8, 1, 4, 7);
if (!global_xor1) if (~val & 0x0800) val ^= 0x3002; // 1,12,13
- if (true) if (~val & 0x0020) val ^= 0x0044; // 2,6
+ if (true) if (~val & 0x0020) val ^= 0x0044; // 2,6
if (!key_1b) if (~val & 0x0400) val ^= 0x0890; // 4,7,11
if (!global_swap2) if (!key_0c) val ^= 0x0308; // 3,8,9
val ^= 0x6561;
diff --git a/src/mame/machine/kaneko_toybox.cpp b/src/mame/machine/kaneko_toybox.cpp
index ee863a303d7..0815db16863 100644
--- a/src/mame/machine/kaneko_toybox.cpp
+++ b/src/mame/machine/kaneko_toybox.cpp
@@ -192,7 +192,7 @@ void kaneko_toybox_device::mcu_run()
case 0x42: // Write to NVRAM
{
- eeprom_serial_93cxx_device *eeprom = machine().device<eeprom_serial_93cxx_device>(":eeprom");
+ eeprom_serial_93cxx_device *eeprom = machine().device<eeprom_serial_93cxx_device>(":eeprom");
UINT8* nvdat = (UINT8*)&m_mcuram[mcu_offset];
for (int i=0;i<0x80;i++)
{
diff --git a/src/mame/machine/m2comm.cpp b/src/mame/machine/m2comm.cpp
index 4b3f4dbe3c3..92756c75806 100644
--- a/src/mame/machine/m2comm.cpp
+++ b/src/mame/machine/m2comm.cpp
@@ -328,7 +328,7 @@ void m2comm_device::comm_init()
{
// TODO - check EPR-16726 on Daytona USA and Sega Rally Championship
// EPR-18643(A) - these are accessed by VirtuaON and Sega Touring Car Championship
-
+
// frameSize - 0xe00
m_shared[0x12] = 0x00;
m_shared[0x13] = 0x0e;
@@ -343,10 +343,10 @@ void m2comm_device::comm_tick()
if (m_linkenable == 0x01)
{
m_zfg ^= 1;
-
+
int frameSize = m_shared[0x13] << 8 | m_shared[0x12];
int frameOffset = m_shared[0x15] << 8 | m_shared[0x14];
-
+
int dataSize = frameSize + 1;
int togo = 0;
int recv = 0;
diff --git a/src/mame/machine/namcoic.cpp b/src/mame/machine/namcoic.cpp
index dc8c34c8645..4e49a755686 100644
--- a/src/mame/machine/namcoic.cpp
+++ b/src/mame/machine/namcoic.cpp
@@ -79,7 +79,7 @@ void namcos2_shared_state::namco_tilemap_init( int gfxbank, void *maskBaseAddr,
mTilemapInfo.tmap[i]->set_scrolldx( -dx, 288+dx );
mTilemapInfo.tmap[i]->set_scrolldy( -24, 224+24 );
}
-
+
save_item(NAME(mTilemapInfo.control));
save_pointer(NAME(mTilemapInfo.videoram.get()), 0x10000);
} /* namco_tilemap_init */
@@ -822,7 +822,7 @@ void namcos2_shared_state::c355_obj_init(int gfxbank, int pal_xor, c355_obj_code
memset(m_c355_obj_ram, 0, sizeof(m_c355_obj_ram)); // needed for Nebulas Ray
memset(m_c355_obj_position, 0, sizeof(m_c355_obj_position));
-
+
save_item(NAME(m_c355_obj_position));
save_item(NAME(m_c355_obj_ram));
save_item(NAME(m_player_mux));
diff --git a/src/mame/machine/pcecommn.h b/src/mame/machine/pcecommn.h
index 732b044768f..c4318f80230 100644
--- a/src/mame/machine/pcecommn.h
+++ b/src/mame/machine/pcecommn.h
@@ -33,7 +33,7 @@ public:
virtual UINT8 joy_read();
UINT32 screen_update(screen_device &screen, bitmap_ind16 &bitmap, const rectangle &cliprect);
required_device<huc6260_device> m_huc6260;
-
+
private:
UINT8 m_io_port_options; /*driver-specific options for the PCE*/
int m_joystick_port_select; /* internal index of joystick ports */
diff --git a/src/mame/machine/seibucop/seibucop.cpp b/src/mame/machine/seibucop/seibucop.cpp
index 1490ef5cd81..06f093a0d0d 100644
--- a/src/mame/machine/seibucop/seibucop.cpp
+++ b/src/mame/machine/seibucop/seibucop.cpp
@@ -2,63 +2,63 @@
// copyright-holders:Olivier Galibert, Angelo Salese, David Haywood, Tomasz Slanina
/***************************************************************************
- Seibu Cop (Co-Processor) device emulation
- a.k.a. known as Toshiba gate array TC25SC rebadged as:
- SEI300 - Legionnaire PCB
- [...]
- There's also a ROM labeled COP-Dx, which is probably used for some in-game maths:
- COP-D1 - Seibu Cup Soccer PCBs
- COP-D2 - legionna.cpp and raiden2.cpp, latter might use another component too
- COP-D3 - New Zero Team / Raiden 2 V33 HWs
- Raiden 2 first boss arms is known to behave strangely without this ROM on a real PCB
-
- TODO:
- - improve documentation, ffs!
- - split into files, still needed:
- - BCD;
- - collision detection;
- - command parser -> to cmd file;
- - sd gundam sprite dma -> to dma file;
- - convert to internal memory map, remove trampolines along the way.
- - DMA mode needs to be cleaned up;
- - improve class OO public/protected/private;
- - nuke legacy command implementations;
- - assert for something that needs actual playtesting is bad.
- - add better debug facilities in a new sub-class, including but not limited to:
- - disable collision detection;
- - printing facilities;
- - debugger break on pre-setted commands;
- - ...
-
- per-game TODO:
- Legionnaire
- - (fixed) player walks on spot on stage clear;
- - several if not all enemies definitely wants some sort of "axis aligned bounding box" in order to stop from going out of range
- (when i.e. first boss goes to bottom of the screen and become unreachable)
- - (btanb) Throw is made by quickly double jumping (!)
- Heated Barrel
- - gives random value to hi-score if you continue (only the first time, not a bug?);
- - (fixed?) throws random address exceptions at level 3 and above, a RAM address arrives corrupt in the snippet at 0x136a;
- - (fixed?) some corrupt sprites, probably a non-fatal version of the one above;
- - stage 2 boss attacks only in vertical (regressed with the 130e / 3b30 / 42c2 command merge);
- - (fixed) level 3+ boss movements looks wrong;
- - stage 3 "homing" missiles doesn't seem to like our 6200 hookup here, except it's NOT 6200!?
- - barrels seen in later levels seems to fail an axis aligned bounding box, not unlike Legionnaire.
- SD Gundam
- - stage 3 mid-boss still has the sprite garbage bug;
- - stage 4: has sprite stuck on bottom-left of screen;
- - palette dims too much on attract / continue screen.
+ Seibu Cop (Co-Processor) device emulation
+ a.k.a. known as Toshiba gate array TC25SC rebadged as:
+ SEI300 - Legionnaire PCB
+ [...]
+ There's also a ROM labeled COP-Dx, which is probably used for some in-game maths:
+ COP-D1 - Seibu Cup Soccer PCBs
+ COP-D2 - legionna.cpp and raiden2.cpp, latter might use another component too
+ COP-D3 - New Zero Team / Raiden 2 V33 HWs
+ Raiden 2 first boss arms is known to behave strangely without this ROM on a real PCB
+
+ TODO:
+ - improve documentation, ffs!
+ - split into files, still needed:
+ - BCD;
+ - collision detection;
+ - command parser -> to cmd file;
+ - sd gundam sprite dma -> to dma file;
+ - convert to internal memory map, remove trampolines along the way.
+ - DMA mode needs to be cleaned up;
+ - improve class OO public/protected/private;
+ - nuke legacy command implementations;
+ - assert for something that needs actual playtesting is bad.
+ - add better debug facilities in a new sub-class, including but not limited to:
+ - disable collision detection;
+ - printing facilities;
+ - debugger break on pre-setted commands;
+ - ...
+
+ per-game TODO:
+ Legionnaire
+ - (fixed) player walks on spot on stage clear;
+ - several if not all enemies definitely wants some sort of "axis aligned bounding box" in order to stop from going out of range
+ (when i.e. first boss goes to bottom of the screen and become unreachable)
+ - (btanb) Throw is made by quickly double jumping (!)
+ Heated Barrel
+ - gives random value to hi-score if you continue (only the first time, not a bug?);
+ - (fixed?) throws random address exceptions at level 3 and above, a RAM address arrives corrupt in the snippet at 0x136a;
+ - (fixed?) some corrupt sprites, probably a non-fatal version of the one above;
+ - stage 2 boss attacks only in vertical (regressed with the 130e / 3b30 / 42c2 command merge);
+ - (fixed) level 3+ boss movements looks wrong;
+ - stage 3 "homing" missiles doesn't seem to like our 6200 hookup here, except it's NOT 6200!?
+ - barrels seen in later levels seems to fail an axis aligned bounding box, not unlike Legionnaire.
+ SD Gundam
+ - stage 3 mid-boss still has the sprite garbage bug;
+ - stage 4: has sprite stuck on bottom-left of screen;
+ - palette dims too much on attract / continue screen.
It's known that the DMA data arrangement gives same results on a real Legionnaire board, so shrug?
-
- Tech notes (to move into mainpage):
- -----------
- [0x6fc] DMA mode bit scheme:
- ---1 ---1 ---- ---- fill op if true, else transfer
- ---- ---- x--- ---- palette brightness
- ---- ---- ---x ---- internal buffer selector
- ---- ---- ---- x--- size modifier? Bus transfer size actually?
- ---- ---- ---- -xxx select channel
-
+
+ Tech notes (to move into mainpage):
+ -----------
+ [0x6fc] DMA mode bit scheme:
+ ---1 ---1 ---- ---- fill op if true, else transfer
+ ---- ---- x--- ---- palette brightness
+ ---- ---- ---x ---- internal buffer selector
+ ---- ---- ---- x--- size modifier? Bus transfer size actually?
+ ---- ---- ---- -xxx select channel
+
***************************************************************************/
#include "emu.h"
@@ -242,7 +242,7 @@ void raiden2cop_device::device_start()
m_host_cpu = machine().device<cpu_device>("maincpu");
m_host_space = &m_host_cpu->space(AS_PROGRAM);
m_host_endian = m_host_space->endianness() == ENDIANNESS_BIG; // m_cpu_is_68k
-
+
m_byte_endian_val = m_host_endian ? 3 : 0;
m_word_endian_val = m_host_endian ? 2 : 0;
}
@@ -708,11 +708,11 @@ WRITE16_MEMBER(raiden2cop_device::cop_dma_trigger_w)
switch (cop_dma_mode)
{
case 0x14:
- {
+ {
dma_tilemap_buffer();
break;
}
-
+
case 0x15:
{
dma_palette_buffer();
@@ -727,10 +727,10 @@ WRITE16_MEMBER(raiden2cop_device::cop_dma_trigger_w)
case 0x85:
case 0x86:
case 0x87:
- { dma_palette_brightness();
+ { dma_palette_brightness();
break;
}
-
+
/********************************************************************************************************************/
case 0x09: {
UINT32 src, dst, size;
@@ -795,7 +795,7 @@ WRITE16_MEMBER(raiden2cop_device::cop_dma_trigger_w)
case 0x11c:
case 0x11d:
case 0x11e:
- case 0x11f:
+ case 0x11f:
{
dma_fill();
break;
@@ -843,7 +843,7 @@ WRITE16_MEMBER(raiden2cop_device::cop_itoa_low_w)
WRITE16_MEMBER(raiden2cop_device::cop_itoa_high_w)
{
cop_itoa = (cop_itoa & ~(mem_mask << 16)) | ((data & mem_mask) << 16);
-
+
// Godzilla cares, otherwise you get 2p score overflow in 1p vs 2p, TODO: might actually be HW endianness dependant?
bcd_update();
}
@@ -1553,7 +1553,7 @@ WRITE16_MEMBER(raiden2cop_device::LEGACY_cop_cmd_w)
{
if(data == 0xf105) // cupsoc transition from presentation to kick off
return;
-
+
printf("did not execute %04x\n", data); // cup soccer triggers this a lot (and others)
}
}
diff --git a/src/mame/machine/seibucop/seibucop.h b/src/mame/machine/seibucop/seibucop.h
index 1e6e2c4c9fa..fbf8ecced76 100644
--- a/src/mame/machine/seibucop/seibucop.h
+++ b/src/mame/machine/seibucop/seibucop.h
@@ -10,9 +10,9 @@
#ifndef RAIDEN2COP_H
#define RAIDEN2COP_H
-#define LOG_Commands 0
-#define LOG_Phytagoras 0
-#define LOG_Division 0
+#define LOG_Commands 0
+#define LOG_Phytagoras 0
+#define LOG_Division 0
#define LOG_Move0205 0
#define LOG_Move0905 0
@@ -211,14 +211,14 @@ private:
// internal state
devcb_write16 m_videoramout_cb;
required_device<palette_device> m_palette;
-
- cpu_device *m_host_cpu; /**< reference to the host cpu */
+
+ cpu_device *m_host_cpu; /**< reference to the host cpu */
address_space *m_host_space; /**< reference to the host cpu space */
- bool m_host_endian; /**< reference to the host cpu endianness, some commands cares! */
- UINT8 m_byte_endian_val; /**< 2 if m_host_endian is big (68k) else 0 */
- UINT8 m_word_endian_val; /**< 3 if m_host_endian is big (68k) else 0 */
+ bool m_host_endian; /**< reference to the host cpu endianness, some commands cares! */
+ UINT8 m_byte_endian_val; /**< 2 if m_host_endian is big (68k) else 0 */
+ UINT8 m_word_endian_val; /**< 3 if m_host_endian is big (68k) else 0 */
+
-
void cop_collision_read_pos(int slot, UINT32 spradr, bool allow_swap);
// commands, TODO: needs commenting!
@@ -257,15 +257,15 @@ private:
void LEGACY_execute_d104(int offset, UINT16 data);
void LEGACY_execute_6980(int offset, UINT16 data);
void LEGACY_execute_c480(int offset, UINT16 data);
-
+
void cop_collision_update_hitbox(UINT16 data, int slot, UINT32 hitadr);
void bcd_update();
-
+
UINT16 cop_read_word(int address);
UINT8 cop_read_byte(int address);
void cop_write_word(int address, UINT16 data);
void cop_write_byte(int address, UINT8 data);
-
+
void dma_tilemap_buffer();
void dma_palette_buffer();
void dma_fill();
diff --git a/src/mame/machine/sms.cpp b/src/mame/machine/sms.cpp
index 8941b2513f2..2a1f57da928 100644
--- a/src/mame/machine/sms.cpp
+++ b/src/mame/machine/sms.cpp
@@ -800,7 +800,7 @@ WRITE8_MEMBER(sms_state::sms_mem_control_w)
READ8_MEMBER(sms_state::sg1000m3_peripheral_r)
{
bool joy_ports_disabled = m_sgexpslot->is_readable(offset);
-
+
if (joy_ports_disabled)
{
return m_sgexpslot->read(space, offset);
@@ -818,7 +818,7 @@ READ8_MEMBER(sms_state::sg1000m3_peripheral_r)
WRITE8_MEMBER(sms_state::sg1000m3_peripheral_w)
{
bool joy_ports_disabled = m_sgexpslot->is_writeable(offset);
-
+
if (joy_ports_disabled)
{
m_sgexpslot->write(space, offset, data);
diff --git a/src/mame/machine/xbox.cpp b/src/mame/machine/xbox.cpp
index e4cdcee007b..35654e90b42 100644
--- a/src/mame/machine/xbox.cpp
+++ b/src/mame/machine/xbox.cpp
@@ -2362,17 +2362,17 @@ int xbox_base_state::smbus_cx25871(int command, int rw, int data)
// let's try to fake the missing eeprom, make sure its ntsc
static int dummyeeprom[256] = {
- 0x39, 0xe3, 0xcc, 0x81, 0xb0, 0xa9, 0x97, 0x09, 0x57, 0xac, 0x57, 0x12, 0xf7, 0xc2, 0xc0, 0x21, 0xce, 0x0d, 0x0a, 0xdb, 0x20, 0x7a, 0xf3, 0xff,
- 0xdf, 0x67, 0xed, 0xf4, 0xf8, 0x95, 0x5c, 0xd0, 0x9b, 0xef, 0x7b, 0x81, 0xda, 0xd5, 0x98, 0xc1, 0xb1, 0xb3, 0x74, 0x18, 0x86, 0x05, 0xe2, 0x7c,
- 0xd1, 0xad, 0xc9, 0x90, 0x30, 0x31, 0x32, 0x33, 0x34, 0x35, 0x36, 0x37, 0x38, 0x39, 0x41, 0x42, 0x11, 0x22, 0x33, 0x44, 0x55, 0x66, 0x00, 0x00,
- 0xaa, 0xbb, 0xcc, 0xdd, 0xee, 0xff, 0xab, 0xcd, 0xef, 0xba, 0xdc, 0xfe, 0xa1, 0xb2, 0xc3, 0xd3, 0x00, 0x01, 0x40, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0xff, 0xff, 0xff, 0xff, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 };
+ 0x39, 0xe3, 0xcc, 0x81, 0xb0, 0xa9, 0x97, 0x09, 0x57, 0xac, 0x57, 0x12, 0xf7, 0xc2, 0xc0, 0x21, 0xce, 0x0d, 0x0a, 0xdb, 0x20, 0x7a, 0xf3, 0xff,
+ 0xdf, 0x67, 0xed, 0xf4, 0xf8, 0x95, 0x5c, 0xd0, 0x9b, 0xef, 0x7b, 0x81, 0xda, 0xd5, 0x98, 0xc1, 0xb1, 0xb3, 0x74, 0x18, 0x86, 0x05, 0xe2, 0x7c,
+ 0xd1, 0xad, 0xc9, 0x90, 0x30, 0x31, 0x32, 0x33, 0x34, 0x35, 0x36, 0x37, 0x38, 0x39, 0x41, 0x42, 0x11, 0x22, 0x33, 0x44, 0x55, 0x66, 0x00, 0x00,
+ 0xaa, 0xbb, 0xcc, 0xdd, 0xee, 0xff, 0xab, 0xcd, 0xef, 0xba, 0xdc, 0xfe, 0xa1, 0xb2, 0xc3, 0xd3, 0x00, 0x01, 0x40, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0xff, 0xff, 0xff, 0xff, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 };
int smbus_callback_eeprom(xbox_base_state &chs, int command, int rw, int data)
{
diff --git a/src/mame/mame.lst b/src/mame/mame.lst
index 559fd730b5e..4a723c60b12 100644
--- a/src/mame/mame.lst
+++ b/src/mame/mame.lst
@@ -9204,8 +9204,8 @@ dking // Crazy Kong Bootleg
guzzler // (c) 1983 Tehkan
guzzlers // (c) 1983 Tehkan (Swimmer Conversion)
monkeyd // bootleg
-rpatrol // (c) 1981.01 Orca
-rpatrola // bootleg
+rpatrol // (c) 1981.01 Orca
+rpatrola // bootleg
rpatrolb // bootleg
silvland // Falcon
swimmer // (c) 1982 Tehkan
@@ -14198,7 +14198,7 @@ mjkinjas // (c) 1991 Home Data
mjkojink // (c) 1989 Home Data
mjprivat // (c) 1991 Matoba
mjyougo // (c) 1989 Home Data
-mjjoship // (c) 1988 Home Data
+mjjoship // (c) 1988 Home Data
mrokumei // (c) 1988 Home Data
reikaids // (c) 1988 Home Data
vitaminc // (c) 1989 Home Data
diff --git a/src/mame/video/chihiro.cpp b/src/mame/video/chihiro.cpp
index 7ce95c67ff9..48cca5d119c 100644
--- a/src/mame/video/chihiro.cpp
+++ b/src/mame/video/chihiro.cpp
@@ -4617,7 +4617,7 @@ WRITE32_MEMBER(nv2a_renderer::geforce_w)
//printf("dmaget %08X dmaput %08X\n\r",*dmaget,*dmaput);
if (((*dmaput == 0x048cf000) && (*dmaget == 0x07f4d000)) || // only for outr2
((*dmaput == 0x07dca000) && (*dmaget == 0x07f4d000))) // only for crtaxihr
- {
+ {
*dmaget = *dmaput;
puller_waiting = 0;
puller_timer->enable(false);
diff --git a/src/mame/video/divebomb.cpp b/src/mame/video/divebomb.cpp
index 275ef64e173..1da5769aa31 100644
--- a/src/mame/video/divebomb.cpp
+++ b/src/mame/video/divebomb.cpp
@@ -20,13 +20,13 @@
TILE_GET_INFO_MEMBER(divebomb_state::get_fg_tile_info)
{
- UINT32 code = m_fgram[tile_index + 0x000];
- UINT32 attr = m_fgram[tile_index + 0x400];
- UINT32 colour = attr >> 4;
+ UINT32 code = m_fgram[tile_index + 0x000];
+ UINT32 attr = m_fgram[tile_index + 0x400];
+ UINT32 colour = attr >> 4;
- code |= (attr & 0x3) << 8;
+ code |= (attr & 0x3) << 8;
- SET_TILE_INFO_MEMBER(0, code, colour, 0);
+ SET_TILE_INFO_MEMBER(0, code, colour, 0);
}
@@ -39,15 +39,15 @@ TILE_GET_INFO_MEMBER(divebomb_state::get_fg_tile_info)
K051316_CB_MEMBER(divebomb_state::zoom_callback_1)
{
- *code |= (*color & 0x03) << 8;
- *color = 0 + ((roz_pal >> 4) & 3);
+ *code |= (*color & 0x03) << 8;
+ *color = 0 + ((roz_pal >> 4) & 3);
}
K051316_CB_MEMBER(divebomb_state::zoom_callback_2)
{
- *code |= (*color & 0x03) << 8;
- *color = 4 + (roz_pal & 3);
+ *code |= (*color & 0x03) << 8;
+ *color = 4 + (roz_pal & 3);
}
@@ -60,47 +60,47 @@ K051316_CB_MEMBER(divebomb_state::zoom_callback_2)
WRITE8_MEMBER(divebomb_state::fgram_w)
{
- m_fgram[offset] = data;
- m_fg_tilemap->mark_tile_dirty(offset & 0x3ff);
+ m_fgram[offset] = data;
+ m_fg_tilemap->mark_tile_dirty(offset & 0x3ff);
}
WRITE8_MEMBER(divebomb_state::rozcpu_wrap1_enable_w)
{
- roz1_wrap = !(data & 1);
+ roz1_wrap = !(data & 1);
}
WRITE8_MEMBER(divebomb_state::rozcpu_enable1_w)
{
- roz1_enable = !(data & 1);
+ roz1_enable = !(data & 1);
}
WRITE8_MEMBER(divebomb_state::rozcpu_enable2_w)
{
- roz2_enable = !(data & 1);
+ roz2_enable = !(data & 1);
}
WRITE8_MEMBER(divebomb_state::rozcpu_wrap2_enable_w)
{
- roz2_wrap = !(data & 1);
+ roz2_wrap = !(data & 1);
}
WRITE8_MEMBER(divebomb_state::rozcpu_pal_w)
{
- //.... ..xx K051316 1 palette select
- //..xx .... K051316 2 palette select
-
- roz_pal = data;
-
- m_k051316_2->mark_tmap_dirty();
- m_k051316_1->mark_tmap_dirty();
-
- if (data & 0xcc)
- logerror("rozcpu_port50_w %02x\n", data);
+ //.... ..xx K051316 1 palette select
+ //..xx .... K051316 2 palette select
+
+ roz_pal = data;
+
+ m_k051316_2->mark_tmap_dirty();
+ m_k051316_1->mark_tmap_dirty();
+
+ if (data & 0xcc)
+ logerror("rozcpu_port50_w %02x\n", data);
}
@@ -113,50 +113,50 @@ WRITE8_MEMBER(divebomb_state::rozcpu_pal_w)
void divebomb_state::decode_proms(const UINT8 * rgn, int size, int index, bool inv)
{
- static const int resistances[4] = { 2000, 1000, 470, 220 };
-
- double rweights[4], gweights[4], bweights[4];
-
- /* compute the color output resistor weights */
- compute_resistor_weights(0, 255, -1.0,
- 4, resistances, rweights, 0, 0,
- 4, resistances, gweights, 0, 0,
- 4, resistances, bweights, 0, 0);
-
- /* create a lookup table for the palette */
- for (UINT32 i = 0; i < size; ++i)
- {
- UINT32 rdata = rgn[i + size*2] & 0x0f;
- UINT32 r = combine_4_weights(rweights, BIT(rdata, 0), BIT(rdata, 1), BIT(rdata, 2), BIT(rdata, 3));
-
- UINT32 gdata = rgn[i + size] & 0x0f;
- UINT32 g = combine_4_weights(gweights, BIT(gdata, 0), BIT(gdata, 1), BIT(gdata, 2), BIT(gdata, 3));
-
- UINT32 bdata = rgn[i] & 0x0f;
- UINT32 b = combine_4_weights(bweights, BIT(bdata, 0), BIT(bdata, 1), BIT(bdata, 2), BIT(bdata, 3));
-
- if (!inv)
- m_palette->set_pen_color(index + i, rgb_t(r, g, b));
- else
- m_palette->set_pen_color(index + (i ^ 0xff), rgb_t(r, g, b));
- }
+ static const int resistances[4] = { 2000, 1000, 470, 220 };
+
+ double rweights[4], gweights[4], bweights[4];
+
+ /* compute the color output resistor weights */
+ compute_resistor_weights(0, 255, -1.0,
+ 4, resistances, rweights, 0, 0,
+ 4, resistances, gweights, 0, 0,
+ 4, resistances, bweights, 0, 0);
+
+ /* create a lookup table for the palette */
+ for (UINT32 i = 0; i < size; ++i)
+ {
+ UINT32 rdata = rgn[i + size*2] & 0x0f;
+ UINT32 r = combine_4_weights(rweights, BIT(rdata, 0), BIT(rdata, 1), BIT(rdata, 2), BIT(rdata, 3));
+
+ UINT32 gdata = rgn[i + size] & 0x0f;
+ UINT32 g = combine_4_weights(gweights, BIT(gdata, 0), BIT(gdata, 1), BIT(gdata, 2), BIT(gdata, 3));
+
+ UINT32 bdata = rgn[i] & 0x0f;
+ UINT32 b = combine_4_weights(bweights, BIT(bdata, 0), BIT(bdata, 1), BIT(bdata, 2), BIT(bdata, 3));
+
+ if (!inv)
+ m_palette->set_pen_color(index + i, rgb_t(r, g, b));
+ else
+ m_palette->set_pen_color(index + (i ^ 0xff), rgb_t(r, g, b));
+ }
}
PALETTE_INIT_MEMBER(divebomb_state, divebomb)
{
- decode_proms(memregion("spr_proms")->base(), 0x100, 0x400 + 0x400 + 0x400, false);
- decode_proms(memregion("fg_proms")->base(), 0x400, 0x400 + 0x400, false);
- decode_proms(memregion("k051316_1_pr")->base(), 0x400, 0, true);
- decode_proms(memregion("k051316_2_pr")->base(), 0x400, 0x400, true);
+ decode_proms(memregion("spr_proms")->base(), 0x100, 0x400 + 0x400 + 0x400, false);
+ decode_proms(memregion("fg_proms")->base(), 0x400, 0x400 + 0x400, false);
+ decode_proms(memregion("k051316_1_pr")->base(), 0x400, 0, true);
+ decode_proms(memregion("k051316_2_pr")->base(), 0x400, 0x400, true);
}
VIDEO_START_MEMBER(divebomb_state,divebomb)
{
- m_fg_tilemap = &machine().tilemap().create(m_gfxdecode, tilemap_get_info_delegate(FUNC(divebomb_state::get_fg_tile_info),this), TILEMAP_SCAN_ROWS, 8, 8, 32, 32);
- m_fg_tilemap->set_transparent_pen(0);
- m_fg_tilemap->set_scrolly(0, 16);
+ m_fg_tilemap = &machine().tilemap().create(m_gfxdecode, tilemap_get_info_delegate(FUNC(divebomb_state::get_fg_tile_info),this), TILEMAP_SCAN_ROWS, 8, 8, 32, 32);
+ m_fg_tilemap->set_transparent_pen(0);
+ m_fg_tilemap->set_scrolly(0, 16);
}
@@ -169,41 +169,41 @@ VIDEO_START_MEMBER(divebomb_state,divebomb)
void divebomb_state::draw_sprites(bitmap_ind16 &bitmap, const rectangle &cliprect)
{
- const UINT8 *spriteram = m_spriteram;
-
- for (UINT32 i = 0; i < m_spriteram.bytes(); i += 4)
- {
- UINT32 sy = spriteram[i + 3];
- UINT32 sx = spriteram[i + 0];
- UINT32 code = spriteram[i + 2];
- UINT32 attr = spriteram[i + 1];
-
- code += (attr & 0x0f) << 8;
-
- UINT32 colour = attr >> 4;
-
- m_gfxdecode->gfx(1)->transpen(bitmap, cliprect, code, colour, 0, 0, sx, sy, 0);
- m_gfxdecode->gfx(1)->transpen(bitmap, cliprect, code, colour, 0, 0, sx, sy-256, 0);
- }
+ const UINT8 *spriteram = m_spriteram;
+
+ for (UINT32 i = 0; i < m_spriteram.bytes(); i += 4)
+ {
+ UINT32 sy = spriteram[i + 3];
+ UINT32 sx = spriteram[i + 0];
+ UINT32 code = spriteram[i + 2];
+ UINT32 attr = spriteram[i + 1];
+
+ code += (attr & 0x0f) << 8;
+
+ UINT32 colour = attr >> 4;
+
+ m_gfxdecode->gfx(1)->transpen(bitmap, cliprect, code, colour, 0, 0, sx, sy, 0);
+ m_gfxdecode->gfx(1)->transpen(bitmap, cliprect, code, colour, 0, 0, sx, sy-256, 0);
+ }
}
UINT32 divebomb_state::screen_update_divebomb(screen_device &screen, bitmap_ind16 &bitmap, const rectangle &cliprect)
{
- m_k051316_1->wraparound_enable(roz1_wrap);
- m_k051316_2->wraparound_enable(roz2_wrap);
+ m_k051316_1->wraparound_enable(roz1_wrap);
+ m_k051316_2->wraparound_enable(roz2_wrap);
+
+ bitmap.fill(m_palette->black_pen(), cliprect);
- bitmap.fill(m_palette->black_pen(), cliprect);
+ if (roz2_enable)
+ m_k051316_2->zoom_draw(screen, bitmap, cliprect, 0, 0);
- if (roz2_enable)
- m_k051316_2->zoom_draw(screen, bitmap, cliprect, 0, 0);
-
- if (roz1_enable)
- m_k051316_1->zoom_draw(screen, bitmap, cliprect, 0, 0);
+ if (roz1_enable)
+ m_k051316_1->zoom_draw(screen, bitmap, cliprect, 0, 0);
- draw_sprites(bitmap, cliprect);
+ draw_sprites(bitmap, cliprect);
- m_fg_tilemap->draw(screen, bitmap, cliprect, 0, 0);
+ m_fg_tilemap->draw(screen, bitmap, cliprect, 0, 0);
- return 0;
+ return 0;
}
diff --git a/src/mame/video/exerion.cpp b/src/mame/video/exerion.cpp
index c2d30a8daac..df90f829362 100644
--- a/src/mame/video/exerion.cpp
+++ b/src/mame/video/exerion.cpp
@@ -389,11 +389,11 @@ UINT32 exerion_state::screen_update_exerion(screen_device &screen, bitmap_ind16
code &= ~0x10, code2 |= 0x10;
gfx->transmask(bitmap,cliprect, code2, color, xflip, yflip, x, y + gfx->height(),
- m_palette->transpen_mask(*gfx, color, 0x10));
+ m_palette->transpen_mask(*gfx, color, 0x10));
}
gfx->transmask(bitmap,cliprect, code, color, xflip, yflip, x, y,
- m_palette->transpen_mask(*gfx, color, 0x10));
+ m_palette->transpen_mask(*gfx, color, 0x10));
if (doubled) i += 4;
}
diff --git a/src/mame/video/gotya.cpp b/src/mame/video/gotya.cpp
index ca2070a70f1..54f549f8513 100644
--- a/src/mame/video/gotya.cpp
+++ b/src/mame/video/gotya.cpp
@@ -153,9 +153,9 @@ void gotya_state::draw_sprites( bitmap_ind16 &bitmap, const rectangle &cliprect
m_gfxdecode->gfx(1)->transpen(bitmap,cliprect,
- code, color,
- flip_screen_x(), flip_screen_y(),
- sx, sy, 0);
+ code, color,
+ flip_screen_x(), flip_screen_y(),
+ sx, sy, 0);
}
}
diff --git a/src/mame/video/homedata.cpp b/src/mame/video/homedata.cpp
index 355cf3411c7..a77e534e821 100644
--- a/src/mame/video/homedata.cpp
+++ b/src/mame/video/homedata.cpp
@@ -949,7 +949,7 @@ UINT32 homedata_state::screen_update_pteacher(screen_device &screen, bitmap_ind1
246 = 96 17 ef db (mjjoship)
35*8 = bc 0b ef f0
51*8 = a6 07 ef db (mjikaga)
- 414 = b7 10 ef db (mjjoship, db becomes e8 after first loss)
+ 414 = b7 10 ef db (mjjoship, db becomes e8 after first loss)
54*8 = bc 07 ef e8
but in mjkinjas it's
@@ -987,17 +987,17 @@ UINT32 homedata_state::screen_update_pteacher(screen_device &screen, bitmap_ind1
}
else
{
- if (m_vreg[0x3] == 0xa6)
+ if (m_vreg[0x3] == 0xa6)
{
screen.set_visible_area(0*8, 51*8-1, 2*8, 30*8-1);
scroll_low = 7 - (m_vreg[0x4] & 0x0f);
}
- else if (m_vreg[0x3] == 0xb7)
+ else if (m_vreg[0x3] == 0xb7)
{
screen.set_visible_area(0*8, 52*8-3, 2*8, 30*8-1);
- scroll_low = 0;
+ scroll_low = 0;
}
- else
+ else
{
screen.set_visible_area(0*8, 54*8-1, 2*8, 30*8-1);
scroll_low = 7 - (m_vreg[0x4] & 0x0f);
diff --git a/src/mame/video/megasys1.cpp b/src/mame/video/megasys1.cpp
index 35d9f95cc3e..0d422feb0f4 100644
--- a/src/mame/video/megasys1.cpp
+++ b/src/mame/video/megasys1.cpp
@@ -447,7 +447,7 @@ WRITE16_MEMBER(megasys1_state::megasys1_vregs_A_w)
break;
case 0x308/2 : if (!m_hardware_type_z)
- {
+ {
m_soundlatch->write(space,0,new_data,0xffff);
m_audiocpu->set_input_line(4, HOLD_LINE);
}
diff --git a/src/mame/video/model3.cpp b/src/mame/video/model3.cpp
index 28b3a5efe11..0113e5dadcc 100644
--- a/src/mame/video/model3.cpp
+++ b/src/mame/video/model3.cpp
@@ -711,20 +711,20 @@ cached_texture *model3_state::get_texture(int page, int texx, int texy, int texw
- Color table (is this featured in Model 3?)
0x00: xxxxxxxx xxxxxxxx xxxxxx-- -------- Viewport number
- -------- -------- ------xx -------- Viewport select 0-3
- -------- -------- -------- x------- Display select
- -------- -------- -------- -x------ Fix point centroid
- -------- -------- -------- --x----- Viewport off
+ -------- -------- ------xx -------- Viewport select 0-3
+ -------- -------- -------- x------- Display select
+ -------- -------- -------- -x------ Fix point centroid
+ -------- -------- -------- --x----- Viewport off
-------- -------- -------- ---xx--- Viewport priority
- -------- -------- -------- -----x-- "clr_xlator_tbl_sel"
- -------- -------- -------- ------xx Node type
+ -------- -------- -------- -----x-- "clr_xlator_tbl_sel"
+ -------- -------- -------- ------xx Node type
0x01: -------x -------- -------- -------- Sibling null
- -------- xxxxxxxx xxxxxxxx xxxxxxxx Sibling pointer
+ -------- xxxxxxxx xxxxxxxx xxxxxxxx Sibling pointer
0x02: -----x-- -------- -------- -------- Child is sibling table
- -------x -------- -------- -------- Leaf node
- -------- xxxxxxxx xxxxxxxx xxxxxxxx Child pointer
+ -------x -------- -------- -------- Leaf node
+ -------- xxxxxxxx xxxxxxxx xxxxxxxx Child pointer
0x03: "cota" (float) Affected by frustum angles and viewport size
0x04: Sun light vector X-component (float)
@@ -763,7 +763,7 @@ cached_texture *model3_state::get_texture(int page, int texx, int texy, int texw
0x1b: Copy of word 0x00
0x1c: xxxxxxxx xxxxxxxx -------- -------- "lj"
- -------- -------- xxxxxxxx xxxxxxxx "li"
+ -------- -------- xxxxxxxx xxxxxxxx "li"
0x1d: -------- xxxxxxxx -------- -------- Spotlight Y size
-------- -------- xxxxxxxx xxxxxxxx Spotlight Y position (13.3 fixed-point?)
@@ -775,7 +775,7 @@ cached_texture *model3_state::get_texture(int page, int texx, int texy, int texw
0x20: xxxxxxxx -------- -------- -------- ?
-------- xxxxxxxx -------- -------- ?
- -------- -------- -x------ -------- Parallel projection
+ -------- -------- -x------ -------- Parallel projection
-------- -------- --xxx--- -------- Light RGB (RGB111?)
-------- -------- -----xxx -------- Light RGB Fog (RGB111?)
-------- -------- -------- xxxxxxxx Scroll Fog (0.8 fixed-point?) What is this???
@@ -789,15 +789,15 @@ cached_texture *model3_state::get_texture(int page, int texx, int texy, int texw
-------- -------- -------- xxxxxxxx Scroll attenuation (0.8 fixed-point) What is this???
0x25: -------- xxxxxxxx -------- -------- Ambient fog
- -------- -------- xxxxxxxx xxxxxxxx Fog offset
+ -------- -------- xxxxxxxx xxxxxxxx Fog offset
0x26: xxxxxxxx xxxxxxxx xxxxxxxx -------- Spot light
- -------- -------- -------- x------- Clear viewport
- -------- -------- -------- -x------ New sun parameters
+ -------- -------- -------- x------- Clear viewport
+ -------- -------- -------- -x------ New sun parameters
0x27: x------- -------- -------- -------- Valid spot light
- -x------ -------- -------- -------- Pro 1000 dummy
- -------- --xxxxxx xxxxxxxx xxxxxxxx "upgrade_wd_10"
+ -x------ -------- -------- -------- Pro 1000 dummy
+ -------- --xxxxxx xxxxxxxx xxxxxxxx "upgrade_wd_10"
0x28: Fog layer altitude (float)
@@ -806,7 +806,7 @@ cached_texture *model3_state::get_texture(int page, int texx, int texy, int texw
0x2a: Bottom fog density (float)
0x2b: Near clipping plane (float)
-
+
0x2c: Far clipping plane (float)
0x2d: Pfog offset top
@@ -851,22 +851,22 @@ cached_texture *model3_state::get_texture(int page, int texx, int texy, int texw
Instance Node?
0x00: x------- -------- -------- -------- Is UF ref
- -x------ -------- -------- -------- Is 3D model
- --x----- -------- -------- -------- Is point
- ---x---- -------- -------- -------- Is point ref
- ----x--- -------- -------- -------- Is animation
- -----x-- -------- -------- -------- Is billboard
- ------x- -------- -------- -------- Child is billboard
- -------x -------- -------- -------- Extra child pointer needed
- -------- -----xxx xxxxxx-- -------- Node ID
-
- -------- -------- -------- x------- Reset matrix
- -------- -------- -------- -x------ Use child pointer
- -------- -------- -------- --x----- Use sibling pointer
- -------- -------- -------- ---x---- No matrix
- -------- -------- -------- ----x--- Indirect child
- -------- -------- -------- -----x-- Valid color table
- -------- -------- -------- ------xx Node type (0 = viewport, 1 = root node, 2 = culling node)
+ -x------ -------- -------- -------- Is 3D model
+ --x----- -------- -------- -------- Is point
+ ---x---- -------- -------- -------- Is point ref
+ ----x--- -------- -------- -------- Is animation
+ -----x-- -------- -------- -------- Is billboard
+ ------x- -------- -------- -------- Child is billboard
+ -------x -------- -------- -------- Extra child pointer needed
+ -------- -----xxx xxxxxx-- -------- Node ID
+
+ -------- -------- -------- x------- Reset matrix
+ -------- -------- -------- -x------ Use child pointer
+ -------- -------- -------- --x----- Use sibling pointer
+ -------- -------- -------- ---x---- No matrix
+ -------- -------- -------- ----x--- Indirect child
+ -------- -------- -------- -----x-- Valid color table
+ -------- -------- -------- ------xx Node type (0 = viewport, 1 = root node, 2 = culling node)
0x01,0x02 only present on Step 2+
@@ -885,14 +885,14 @@ cached_texture *model3_state::get_texture(int page, int texx, int texy, int texw
0x06: Translation Z coordinate
0x07: xxxx---- -------- -------- -------- Color table address 2
- -----x-- -------- -------- -------- Sibling table
- ------x- -------- -------- -------- Point
- -------x -------- -------- -------- Leaf node
- -------- xxxxxxxx xxxxxxxx xxxxxxxx Child pointer
-
- 0x08: xxxxxxx- -------- -------- -------- Color table address 3
- -------x -------- -------- -------- Null sibling
- -------- xxxxxxxx xxxxxxxx xxxxxxxx Sibling pointer
+ -----x-- -------- -------- -------- Sibling table
+ ------x- -------- -------- -------- Point
+ -------x -------- -------- -------- Leaf node
+ -------- xxxxxxxx xxxxxxxx xxxxxxxx Child pointer
+
+ 0x08: xxxxxxx- -------- -------- -------- Color table address 3
+ -------x -------- -------- -------- Null sibling
+ -------- xxxxxxxx xxxxxxxx xxxxxxxx Sibling pointer
0x09: xxxxxxxx xxxxxxxx -------- -------- Blend radius
-------- -------- xxxxxxxx xxxxxxxx Culling radius
diff --git a/src/mame/video/namconb1.cpp b/src/mame/video/namconb1.cpp
index 20e6a501a08..b18246ec376 100644
--- a/src/mame/video/namconb1.cpp
+++ b/src/mame/video/namconb1.cpp
@@ -130,7 +130,7 @@ VIDEO_START_MEMBER(namconb1_state,namconb1)
{
namco_tilemap_init(NAMCONB1_TILEGFX, memregion(NAMCONB1_TILEMASKREGION)->base(), NB1TilemapCB );
c355_obj_init(NAMCONB1_SPRITEGFX,0x0,namcos2_shared_state::c355_obj_code2tile_delegate(FUNC(namconb1_state::NB1objcode2tile), this));
-
+
save_item(NAME(m_tilemap_tile_bank));
} /* namconb1 */
@@ -189,6 +189,6 @@ VIDEO_START_MEMBER(namconb1_state,namconb2)
namco_tilemap_init(NAMCONB1_TILEGFX, memregion(NAMCONB1_TILEMASKREGION)->base(), NB2TilemapCB );
c355_obj_init(NAMCONB1_SPRITEGFX,0x0,namcos2_shared_state::c355_obj_code2tile_delegate(FUNC(namconb1_state::NB2objcode2tile), this));
c169_roz_init(NAMCONB1_ROTGFX,NAMCONB1_ROTMASKREGION);
-
+
save_item(NAME(m_tilemap_tile_bank));
} /* namconb2_vh_start */
diff --git a/src/mame/video/namcos2.cpp b/src/mame/video/namcos2.cpp
index 21e1979caf0..89986aea6fe 100644
--- a/src/mame/video/namcos2.cpp
+++ b/src/mame/video/namcos2.cpp
@@ -294,7 +294,7 @@ WRITE16_MEMBER( namcos2_state::rozram_word_w )
m_tilemap_roz->mark_tile_dirty(offset);
//if( space.machine().input().code_pressed(KEYCODE_Q) )
//{
- // machine().debug_break();
+ // machine().debug_break();
//}
}
diff --git a/src/mame/video/powervr2.cpp b/src/mame/video/powervr2.cpp
index b2f05d94069..8e512a0f7e1 100644
--- a/src/mame/video/powervr2.cpp
+++ b/src/mame/video/powervr2.cpp
@@ -1024,7 +1024,7 @@ WRITE32_MEMBER( powervr2_device::startrender_w )
}
// printf("ISP START %d %d\n",sanitycount,m_screen->vpos());
/* Fire ISP irq after a set amount of time TODO: timing of this */
- endofrender_timer_isp->adjust(state->m_maincpu->cycles_to_attotime(sanitycount*25 + 500000)); // hacky end of render delay for Capcom games, otherwise they works at ~1/10 speed
+ endofrender_timer_isp->adjust(state->m_maincpu->cycles_to_attotime(sanitycount*25 + 500000)); // hacky end of render delay for Capcom games, otherwise they works at ~1/10 speed
break;
}
}
diff --git a/src/mame/video/seibu_crtc.cpp b/src/mame/video/seibu_crtc.cpp
index 511f3046ebf..99200dae945 100644
--- a/src/mame/video/seibu_crtc.cpp
+++ b/src/mame/video/seibu_crtc.cpp
@@ -21,7 +21,7 @@ Raiden later rev (probably the first game to use it)
TODO:
- Most registers are still a mystery;
-- Get the proper Seibu chip ID number.
+- Get the proper Seibu chip ID number.
Kold found that a Raiden alt set has irq request pin from a chip named SEI0160, which might be our man.
preliminary memory map:
diff --git a/src/mame/video/vtvideo.cpp b/src/mame/video/vtvideo.cpp
index cea29595dc2..1356efc70ca 100644
--- a/src/mame/video/vtvideo.cpp
+++ b/src/mame/video/vtvideo.cpp
@@ -249,15 +249,15 @@ WRITE8_MEMBER(vt100_video_device::dc012_w)
printf("MHFU ___ENABLED___ %05x \n", space.device().safe_pc());
MHFU_FLAG = true;
- MHFU_counter = 0;
+ MHFU_counter = 0;
}
if (!(data & 0x08))
{
if (!(data & 0x04))
{
- m_scroll_latch_valid = false;
- m_scroll_latch = data & 0x03; // LSB is written first.
+ m_scroll_latch_valid = false;
+ m_scroll_latch = data & 0x03; // LSB is written first.
}
else // set MSB of scroll_latch
{
diff --git a/src/osd/modules/debugger/debugimgui.cpp b/src/osd/modules/debugger/debugimgui.cpp
index b4cead4938c..0c4f16919f9 100644
--- a/src/osd/modules/debugger/debugimgui.cpp
+++ b/src/osd/modules/debugger/debugimgui.cpp
@@ -504,7 +504,7 @@ int debug_imgui::history_set(ImGuiTextEditCallbackData* data)
data->CursorPos = data->BufTextLen = (int)snprintf(data->Buf, (size_t)data->BufSize, "%s", "");
else
data->CursorPos = data->BufTextLen = (int)snprintf(data->Buf, (size_t)data->BufSize, "%s", view_main_console->console_history[history_pos].c_str());
-
+
data->BufDirty = true;
return 0;
}
@@ -613,7 +613,7 @@ void debug_imgui::draw_view(debug_area* view_ptr, bool exp_change)
drawlist->AddRect(ImVec2(view_ptr->ofs_x,view_ptr->ofs_y + ImGui::GetScrollY()),
ImVec2(view_ptr->ofs_x + view_ptr->view_width,view_ptr->ofs_y + ImGui::GetScrollY() + view_ptr->view_height),col);
}
-
+
// if the vertical scroll bar is at the end, then force it to the maximum value in case of an update
if(view_ptr->scroll_end)
ImGui::SetScrollY(ImGui::GetScrollMaxY());
@@ -622,7 +622,7 @@ void debug_imgui::draw_view(debug_area* view_ptr, bool exp_change)
if(view_ptr->scroll_follow)
if(ImGui::GetScrollY() == ImGui::GetScrollMaxY() || ImGui::GetScrollMaxY() < 0)
view_ptr->scroll_end = true;
-
+
ImGui::PopStyleVar(2);
}
@@ -882,7 +882,7 @@ void debug_imgui::draw_memory(debug_area* view_ptr, bool* opened)
ImGui::End();
}
else
- view_ptr->is_collapsed = true;
+ view_ptr->is_collapsed = true;
}
void debug_imgui::add_memory(int id)
@@ -1002,7 +1002,7 @@ void debug_imgui::draw_console()
draw_view(view_main_console,false);
ImGui::EndChild();
ImGui::Separator();
-
+
ImGuiInputTextFlags flags = ImGuiInputTextFlags_EnterReturnsTrue | ImGuiInputTextFlags_CallbackHistory;
if(m_running)
flags |= ImGuiInputTextFlags_ReadOnly;
diff --git a/src/osd/modules/diagnostics/diagnostics_win32.cpp b/src/osd/modules/diagnostics/diagnostics_win32.cpp
index 70e290240c2..60707f2baad 100644
--- a/src/osd/modules/diagnostics/diagnostics_win32.cpp
+++ b/src/osd/modules/diagnostics/diagnostics_win32.cpp
@@ -185,7 +185,7 @@ stack_walker::stack_walker()
m_sym_function_table_access_64 = m_dbghelp_dll->bind<SymFunctionTableAccess64_fn>("SymFunctionTableAccess64");
m_sym_get_module_base_64 = m_dbghelp_dll->bind<SymGetModuleBase64_fn>("SymGetModuleBase64");
m_rtl_capture_context = m_kernel32_dll->bind<RtlCaptureContext_fn>("RtlCaptureContext");
-
+
// initialize the symbols
if (!s_initialized && m_sym_initialize && m_stack_walk_64 && m_sym_function_table_access_64 && m_sym_get_module_base_64)
{
diff --git a/src/osd/modules/file/posixdir.cpp b/src/osd/modules/file/posixdir.cpp
index 161ea62c404..ea3218584d7 100644
--- a/src/osd/modules/file/posixdir.cpp
+++ b/src/osd/modules/file/posixdir.cpp
@@ -99,12 +99,12 @@ public:
bool open_impl(std::string const &dirname);
private:
- typedef std::unique_ptr<DIR, int (*)(DIR *)> dir_ptr;
+ typedef std::unique_ptr<DIR, int (*)(DIR *)> dir_ptr;
- entry m_entry;
- sdl_dirent *m_data;
- dir_ptr m_fd;
- std::string m_path;
+ entry m_entry;
+ sdl_dirent *m_data;
+ dir_ptr m_fd;
+ std::string m_path;
};
diff --git a/src/osd/modules/file/windir.cpp b/src/osd/modules/file/windir.cpp
index ad463f2d337..3ecd2412910 100644
--- a/src/osd/modules/file/windir.cpp
+++ b/src/osd/modules/file/windir.cpp
@@ -45,7 +45,7 @@ public:
private:
HANDLE m_find; // handle to the finder
bool m_is_first; // true if this is the first entry
- entry m_entry; // current entry's data
+ entry m_entry; // current entry's data
WIN32_FIND_DATA m_data; // current raw data
};
diff --git a/src/osd/modules/font/font_dwrite.cpp b/src/osd/modules/font/font_dwrite.cpp
index 599a562de2b..725c8b9bc81 100644
--- a/src/osd/modules/font/font_dwrite.cpp
+++ b/src/osd/modules/font/font_dwrite.cpp
@@ -149,7 +149,7 @@ HRESULT SaveBitmap(IWICBitmap* bitmap, GUID pixelFormat, const WCHAR *filename)
HR_RETHR(frameEncode->Commit());
HR_RETHR(encoder->Commit());
-
+
return S_OK;
}
diff --git a/src/osd/modules/input/input_sdl.cpp b/src/osd/modules/input/input_sdl.cpp
index a60746ca3fa..f0bd112116f 100644
--- a/src/osd/modules/input/input_sdl.cpp
+++ b/src/osd/modules/input/input_sdl.cpp
@@ -513,7 +513,7 @@ public:
sdl_input_module::input_init(machine);
static int event_types[] = {
- static_cast<int>(SDL_KEYDOWN),
+ static_cast<int>(SDL_KEYDOWN),
static_cast<int>(SDL_KEYUP),
static_cast<int>(SDL_TEXTINPUT)
};
diff --git a/src/osd/modules/input/input_windows.cpp b/src/osd/modules/input/input_windows.cpp
index 4455a77c991..88a82b8b877 100644
--- a/src/osd/modules/input/input_windows.cpp
+++ b/src/osd/modules/input/input_windows.cpp
@@ -24,10 +24,10 @@ bool windows_osd_interface::should_hide_mouse() const
{
bool hidemouse = false;
wininput_module* mod;
-
+
mod = dynamic_cast<wininput_module*>(m_keyboard_input);
if (mod) hidemouse |= mod->should_hide_mouse();
-
+
mod = dynamic_cast<wininput_module*>(m_mouse_input);
if (mod) hidemouse |= mod->should_hide_mouse();
diff --git a/src/osd/modules/input/input_xinput.cpp b/src/osd/modules/input/input_xinput.cpp
index 2d01b702bd8..d1dcfd8b023 100644
--- a/src/osd/modules/input/input_xinput.cpp
+++ b/src/osd/modules/input/input_xinput.cpp
@@ -44,7 +44,7 @@ int xinput_api_helper::initialize()
XInputGetState = m_xinput_dll->bind<xinput_get_state_fn>("XInputGetState");
XInputGetCapabilities = m_xinput_dll->bind<xinput_get_caps_fn>("XInputGetCapabilities");
-
+
if (!XInputGetState || !XInputGetCapabilities)
{
osd_printf_verbose("Could not find XInput. Please try to reinstall DirectX runtime package.\n");
diff --git a/src/osd/modules/lib/osdlib.h b/src/osd/modules/lib/osdlib.h
index 64bd556cd3c..17f341b8934 100644
--- a/src/osd/modules/lib/osdlib.h
+++ b/src/osd/modules/lib/osdlib.h
@@ -78,7 +78,6 @@ char *osd_get_clipboard_text(void);
-----------------------------------------------------------------------------*/
namespace osd {
-
class dynamic_module
{
public:
diff --git a/src/osd/modules/lib/osdlib_macosx.cpp b/src/osd/modules/lib/osdlib_macosx.cpp
index b3a7ed642e3..770078a254f 100644
--- a/src/osd/modules/lib/osdlib_macosx.cpp
+++ b/src/osd/modules/lib/osdlib_macosx.cpp
@@ -227,7 +227,6 @@ char *osd_get_clipboard_text(void)
//============================================================
namespace osd {
-
class dynamic_module_posix_impl : public dynamic_module
{
public:
@@ -265,7 +264,7 @@ protected:
if (function != nullptr)
{
- m_module = module;
+ m_module = module;
return function;
}
else
@@ -274,7 +273,7 @@ protected:
}
}
}
-
+
return nullptr;
}
diff --git a/src/osd/modules/lib/osdlib_unix.cpp b/src/osd/modules/lib/osdlib_unix.cpp
index 81d9967ff64..3f3bbb00269 100644
--- a/src/osd/modules/lib/osdlib_unix.cpp
+++ b/src/osd/modules/lib/osdlib_unix.cpp
@@ -172,7 +172,6 @@ char *osd_get_clipboard_text(void)
//============================================================
namespace osd {
-
class dynamic_module_posix_impl : public dynamic_module
{
public:
@@ -210,7 +209,7 @@ protected:
if (function != nullptr)
{
- m_module = module;
+ m_module = module;
return function;
}
else
@@ -219,7 +218,7 @@ protected:
}
}
}
-
+
return nullptr;
}
diff --git a/src/osd/modules/lib/osdlib_win32.cpp b/src/osd/modules/lib/osdlib_win32.cpp
index e65509cc436..06a979a7a77 100644
--- a/src/osd/modules/lib/osdlib_win32.cpp
+++ b/src/osd/modules/lib/osdlib_win32.cpp
@@ -330,7 +330,6 @@ char *osd_get_clipboard_text(void)
#endif
namespace osd {
-
class dynamic_module_win32_impl : public dynamic_module
{
public:
@@ -374,7 +373,7 @@ protected:
if (function != nullptr)
{
- m_module = module;
+ m_module = module;
return function;
}
else
@@ -383,7 +382,7 @@ protected:
}
}
}
-
+
return nullptr;
}
diff --git a/src/osd/modules/netdev/pcap.cpp b/src/osd/modules/netdev/pcap.cpp
index 91ff840473b..f5e01d8ea98 100644
--- a/src/osd/modules/netdev/pcap.cpp
+++ b/src/osd/modules/netdev/pcap.cpp
@@ -13,7 +13,7 @@
#define WIN32_LEAN_AND_MEAN
#include <windows.h>
#undef interface
-#define LIB_NAME "wpcap.dll"
+#define LIB_NAME "wpcap.dll"
#elif defined(SDLMAME_MACOSX)
#include <pthread.h>
diff --git a/src/osd/modules/output/output_module.h b/src/osd/modules/output/output_module.h
index f3461d3e1f6..83b9a464f07 100644
--- a/src/osd/modules/output/output_module.h
+++ b/src/osd/modules/output/output_module.h
@@ -25,7 +25,7 @@ public:
virtual ~output_module() { }
virtual void notify(const char *outname, INT32 value) = 0;
-
+
void set_machine(running_machine *machine) { m_machine = machine; };
running_machine &machine() const { return *m_machine; }
private:
diff --git a/src/osd/modules/render/bgfx/chain.cpp b/src/osd/modules/render/bgfx/chain.cpp
index 4ba069d18a4..5806c3ce042 100644
--- a/src/osd/modules/render/bgfx/chain.cpp
+++ b/src/osd/modules/render/bgfx/chain.cpp
@@ -34,11 +34,11 @@ bgfx_chain::bgfx_chain(std::string name, std::string author, bool transform, tar
, m_current_time(0)
, m_screen_index(screen_index)
{
- for (bgfx_target* target : m_target_list)
- {
- m_target_map[target->name()] = target;
- m_target_names.push_back(target->name());
- }
+ for (bgfx_target* target : m_target_list)
+ {
+ m_target_map[target->name()] = target;
+ m_target_names.push_back(target->name());
+ }
}
bgfx_chain::~bgfx_chain()
@@ -63,13 +63,13 @@ bgfx_chain::~bgfx_chain()
void bgfx_chain::repopulate_targets()
{
- for (size_t i = 0; i < m_target_names.size(); i++)
- {
- bgfx_target* target = m_targets.target(m_screen_index, m_target_names[i]);
- if (target != nullptr) {
- m_target_list[i] = target;
- }
- }
+ for (size_t i = 0; i < m_target_names.size(); i++)
+ {
+ bgfx_target* target = m_targets.target(m_screen_index, m_target_names[i]);
+ if (target != nullptr) {
+ m_target_list[i] = target;
+ }
+ }
}
void bgfx_chain::process(render_primitive* prim, int view, int screen, texture_manager& textures, osd_window& window, uint64_t blend)
@@ -87,19 +87,19 @@ void bgfx_chain::process(render_primitive* prim, int view, int screen, texture_m
bool orientation_swap_xy = (window.machine().system().flags & ORIENTATION_SWAP_XY) == ORIENTATION_SWAP_XY;
bool rotation_swap_xy = (window.target()->orientation() & ORIENTATION_SWAP_XY) == ORIENTATION_SWAP_XY;
bool swap_xy = orientation_swap_xy ^ rotation_swap_xy;
-
- float screen_scale_x = 1.0f;
- float screen_scale_y = 1.0f;
- float screen_offset_x = 0.0f;
- float screen_offset_y = 0.0f;
- if (screen_device != nullptr)
- {
- render_container &screen_container = screen_device->container();
- screen_scale_x = 1.0f / screen_container.xscale();
- screen_scale_y = 1.0f / screen_container.yscale();
- screen_offset_x = -screen_container.xoffset();
- screen_offset_y = -screen_container.yoffset();
- }
+
+ float screen_scale_x = 1.0f;
+ float screen_scale_y = 1.0f;
+ float screen_offset_x = 0.0f;
+ float screen_offset_y = 0.0f;
+ if (screen_device != nullptr)
+ {
+ render_container &screen_container = screen_device->container();
+ screen_scale_x = 1.0f / screen_container.xscale();
+ screen_scale_y = 1.0f / screen_container.yscale();
+ screen_offset_x = -screen_container.xoffset();
+ screen_offset_y = -screen_container.yoffset();
+ }
for (bgfx_chain_entry* entry : m_entries)
{
diff --git a/src/osd/modules/render/bgfx/chain.h b/src/osd/modules/render/bgfx/chain.h
index bddec2c9bc3..157f92173cf 100644
--- a/src/osd/modules/render/bgfx/chain.h
+++ b/src/osd/modules/render/bgfx/chain.h
@@ -32,7 +32,7 @@ public:
~bgfx_chain();
void process(render_primitive* prim, int view, int screen, texture_manager& textures, osd_window &window, uint64_t blend = 0L);
- void repopulate_targets();
+ void repopulate_targets();
// Getters
std::vector<bgfx_slider*>& sliders() { return m_sliders; }
@@ -49,8 +49,8 @@ private:
std::vector<bgfx_parameter*> m_params;
std::vector<bgfx_chain_entry*> m_entries;
std::vector<bgfx_target*> m_target_list;
- std::vector<std::string> m_target_names;
- std::map<std::string, bgfx_target*> m_target_map;
+ std::vector<std::string> m_target_names;
+ std::map<std::string, bgfx_target*> m_target_map;
int64_t m_current_time;
uint32_t m_screen_index;
};
diff --git a/src/osd/modules/render/bgfx/chainmanager.cpp b/src/osd/modules/render/bgfx/chainmanager.cpp
index d4c59f9bb6a..2116322f19a 100644
--- a/src/osd/modules/render/bgfx/chainmanager.cpp
+++ b/src/osd/modules/render/bgfx/chainmanager.cpp
@@ -293,17 +293,17 @@ void chain_manager::process_screen_quad(uint32_t view, uint32_t screen, render_p
bgfx_texture *texture = new bgfx_texture(full_name, bgfx::TextureFormat::RGBA8, tex_width, tex_height, mem, BGFX_TEXTURE_U_CLAMP | BGFX_TEXTURE_V_CLAMP | BGFX_TEXTURE_MIN_POINT | BGFX_TEXTURE_MAG_POINT | BGFX_TEXTURE_MIP_POINT);
m_textures.add_provider(full_name, texture);
- const bool any_targets_rebuilt = m_targets.update_target_sizes(screen, tex_width, tex_height, TARGET_STYLE_GUEST);
+ const bool any_targets_rebuilt = m_targets.update_target_sizes(screen, tex_width, tex_height, TARGET_STYLE_GUEST);
if (any_targets_rebuilt)
- {
- for (bgfx_chain* chain : m_screen_chains)
- {
- if (chain != nullptr)
- {
- chain->repopulate_targets();
- }
- }
- }
+ {
+ for (bgfx_chain* chain : m_screen_chains)
+ {
+ if (chain != nullptr)
+ {
+ chain->repopulate_targets();
+ }
+ }
+ }
bgfx_chain* chain = screen_chain(screen);
chain->process(prim, view, screen, m_textures, window, bgfx_util::get_blend_state(PRIMFLAG_GET_BLENDMODE(prim->flags)));
@@ -441,19 +441,19 @@ uint32_t chain_manager::handle_screen_chains(uint32_t view, render_primitive *st
std::swap(screen_width, screen_height);
}
- const bool any_targets_rebuilt = m_targets.update_target_sizes(screen_index, screen_width, screen_height, TARGET_STYLE_NATIVE);
- if (any_targets_rebuilt)
- {
- for (bgfx_chain* chain : m_screen_chains)
- {
- if (chain != nullptr)
- {
- chain->repopulate_targets();
- }
- }
- }
-
- process_screen_quad(view + used_views, screen_index, prim, window);
+ const bool any_targets_rebuilt = m_targets.update_target_sizes(screen_index, screen_width, screen_height, TARGET_STYLE_NATIVE);
+ if (any_targets_rebuilt)
+ {
+ for (bgfx_chain* chain : m_screen_chains)
+ {
+ if (chain != nullptr)
+ {
+ chain->repopulate_targets();
+ }
+ }
+ }
+
+ process_screen_quad(view + used_views, screen_index, prim, window);
used_views += screen_chain(screen_index)->applicable_passes();
screen_index++;
diff --git a/src/osd/modules/render/bgfx/targetmanager.cpp b/src/osd/modules/render/bgfx/targetmanager.cpp
index 7e8577b95b3..dfc1678ee34 100644
--- a/src/osd/modules/render/bgfx/targetmanager.cpp
+++ b/src/osd/modules/render/bgfx/targetmanager.cpp
@@ -102,10 +102,10 @@ bool target_manager::update_target_sizes(uint32_t screen, uint16_t width, uint16
{
sizes[screen] = osd_dim(width, height);
rebuild_targets(screen, style);
- return true;
+ return true;
}
- return false;
+ return false;
}
void target_manager::rebuild_targets(uint32_t screen, uint32_t style)
diff --git a/src/osd/modules/render/d3d/d3dhlsl.cpp b/src/osd/modules/render/d3d/d3dhlsl.cpp
index feb88dc0add..38f23bb2afc 100644
--- a/src/osd/modules/render/d3d/d3dhlsl.cpp
+++ b/src/osd/modules/render/d3d/d3dhlsl.cpp
@@ -47,7 +47,7 @@ shaders::shaders() :
shadow_texture(nullptr), options(nullptr), avi_output_file(nullptr), avi_frame(0), avi_copy_surface(nullptr), avi_copy_texture(nullptr), avi_final_target(nullptr), avi_final_texture(nullptr),
black_surface(nullptr), black_texture(nullptr), render_snap(false), snap_rendered(false), snap_copy_target(nullptr), snap_copy_texture(nullptr), snap_target(nullptr), snap_texture(nullptr),
snap_width(0), snap_height(0), lines_pending(false), initialized(false), backbuffer(nullptr), curr_effect(nullptr), default_effect(nullptr), prescale_effect(nullptr), post_effect(nullptr),
- distortion_effect(nullptr), focus_effect(nullptr), phosphor_effect(nullptr), deconverge_effect(nullptr), color_effect(nullptr), ntsc_effect(nullptr), bloom_effect(nullptr),
+ distortion_effect(nullptr), focus_effect(nullptr), phosphor_effect(nullptr), deconverge_effect(nullptr), color_effect(nullptr), ntsc_effect(nullptr), bloom_effect(nullptr),
downsample_effect(nullptr), vector_effect(nullptr), fsfx_vertices(nullptr), curr_texture(nullptr), curr_render_target(nullptr), curr_poly(nullptr), targethead(nullptr), cachehead(nullptr)
{
}
diff --git a/src/osd/modules/render/drawd3d.cpp b/src/osd/modules/render/drawd3d.cpp
index ce024866319..a29b747bbe1 100644
--- a/src/osd/modules/render/drawd3d.cpp
+++ b/src/osd/modules/render/drawd3d.cpp
@@ -565,7 +565,7 @@ int renderer_d3d9::pre_window_draw_check()
m_shaders->toggle();
m_sliders_dirty = true;
- // re-create resources
+ // re-create resources
if (device_create_resources())
{
osd_printf_verbose("Direct3D: failed to recreate resources for device; failing permanently\n");
@@ -834,8 +834,8 @@ int renderer_d3d9::device_create(HWND device_hwnd)
try_again:
// try for XRGB first
m_screen_format = D3DFMT_X8R8G8B8;
- HRESULT result = d3dintf->d3dobj->CheckDeviceFormat(m_adapter, D3DDEVTYPE_HAL, m_pixformat,
- m_texture_manager->is_dynamic_supported()
+ HRESULT result = d3dintf->d3dobj->CheckDeviceFormat(m_adapter, D3DDEVTYPE_HAL, m_pixformat,
+ m_texture_manager->is_dynamic_supported()
? D3DUSAGE_DYNAMIC
: 0,
D3DRTYPE_TEXTURE, m_screen_format);
@@ -865,7 +865,7 @@ try_again:
// create the D3D device
result = d3dintf->d3dobj->CreateDevice(
- m_adapter, D3DDEVTYPE_HAL, device_hwnd, D3DCREATE_SOFTWARE_VERTEXPROCESSING | D3DCREATE_FPU_PRESERVE, &m_presentation, &m_device);
+ m_adapter, D3DDEVTYPE_HAL, device_hwnd, D3DCREATE_SOFTWARE_VERTEXPROCESSING | D3DCREATE_FPU_PRESERVE, &m_presentation, &m_device);
if (FAILED(result))
{
// if we got a "DEVICELOST" error, it may be transitory; count it and only fail if
@@ -923,7 +923,7 @@ int renderer_d3d9::device_create_resources()
HRESULT result = m_device->CreateVertexBuffer(
sizeof(vertex) * VERTEX_BUFFER_SIZE,
D3DUSAGE_DYNAMIC | D3DUSAGE_SOFTWAREPROCESSING | D3DUSAGE_WRITEONLY,
- VERTEX_BASE_FORMAT | ((m_shaders->enabled() && d3dintf->post_fx_available)
+ VERTEX_BASE_FORMAT | ((m_shaders->enabled() && d3dintf->post_fx_available)
? D3DFVF_XYZW
: D3DFVF_XYZRHW),
D3DPOOL_DEFAULT, &m_vertexbuf, nullptr);
@@ -935,8 +935,8 @@ int renderer_d3d9::device_create_resources()
// set the vertex format
result = m_device->SetFVF(
- (D3DFORMAT)(VERTEX_BASE_FORMAT | ((m_shaders->enabled() && d3dintf->post_fx_available)
- ? D3DFVF_XYZW
+ (D3DFORMAT)(VERTEX_BASE_FORMAT | ((m_shaders->enabled() && d3dintf->post_fx_available)
+ ? D3DFVF_XYZW
: D3DFVF_XYZRHW)));
if (FAILED(result))
{
@@ -993,9 +993,9 @@ renderer_d3d9::~renderer_d3d9()
// todo: throws error when switching from full screen to window mode
//if (m_shaders != nullptr)
//{
- // // delete the HLSL interface
- // global_free(m_shaders);
- // m_shaders = nullptr;
+ // // delete the HLSL interface
+ // global_free(m_shaders);
+ // m_shaders = nullptr;
//}
}
@@ -1686,7 +1686,7 @@ void renderer_d3d9::draw_line(const render_primitive &prim)
}
// now add a polygon entry
- m_poly[m_numpolys].init(D3DPT_TRIANGLESTRIP, 2, 4, prim.flags, nullptr, D3DTOP_MODULATE, 0.0f, 1.0f, 0.0f, 0.0f);
+ m_poly[m_numpolys].init(D3DPT_TRIANGLESTRIP, 2, 4, prim.flags, nullptr, D3DTOP_MODULATE, 0.0f, 1.0f, 0.0f, 0.0f);
m_numpolys++;
}
diff --git a/src/osd/modules/render/winglcontext.h b/src/osd/modules/render/winglcontext.h
index ec63b11ff72..f0cb1b6af77 100644
--- a/src/osd/modules/render/winglcontext.h
+++ b/src/osd/modules/render/winglcontext.h
@@ -156,7 +156,7 @@ private:
{
if (pfn_wglGetExtensionsStringEXT == nullptr)
return false;
-
+
// printf("%s\n", pfn_wglGetExtensionsStringEXT());
if (strstr(pfn_wglGetExtensionsStringEXT(), extension_name) != nullptr)
diff --git a/src/osd/modules/sound/xaudio2_sound.cpp b/src/osd/modules/sound/xaudio2_sound.cpp
index 0f6ec2b5297..bb45626a6c6 100755
--- a/src/osd/modules/sound/xaudio2_sound.cpp
+++ b/src/osd/modules/sound/xaudio2_sound.cpp
@@ -287,7 +287,7 @@ int sound_xaudio2::init(osd_options const &options)
// Make sure our XAudio2Create entrypoint is bound
if (!XAudio2Create)
{
- osd_printf_error("Could not find XAudio2. Please try to reinstall DirectX runtime package.\n");
+ osd_printf_error("Could not find XAudio2. Please try to reinstall DirectX runtime package.\n");
return 1;
}
@@ -342,7 +342,7 @@ void sound_xaudio2::exit()
SetEvent(m_hEventExiting);
m_hEventExiting = nullptr;
}
-
+
if (m_audioThread.joinable())
m_audioThread.join();
diff --git a/src/osd/osdcore.h b/src/osd/osdcore.h
index 141f3db55d9..a224fb7059c 100644
--- a/src/osd/osdcore.h
+++ b/src/osd/osdcore.h
@@ -319,21 +319,21 @@ namespace osd
OTHER
};
- const char * name; // name of the entry
- entry_type type; // type of the entry
- std::uint64_t size; // size of the entry
- std::chrono::system_clock::time_point last_modified; // last modified time
+ const char * name; // name of the entry
+ entry_type type; // type of the entry
+ std::uint64_t size; // size of the entry
+ std::chrono::system_clock::time_point last_modified; // last modified time
};
// -----------------------------------------------------------------------------
// osd::directory::open: open a directory for iteration
- //
+ //
// Parameters:
- //
+ //
// dirname - path to the directory in question
- //
+ //
// Return value:
- //
+ //
// upon success, this function should return an directory pointer
// which contains opaque data necessary to traverse the directory; on
// failure, this function should return nullptr
@@ -347,9 +347,9 @@ namespace osd
// -----------------------------------------------------------------------------
// osd::directory::read: return information about the next entry in the directory
- //
+ //
// Return value:
- //
+ //
// a constant pointer to an entry representing the current item
// in the directory, or nullptr, indicating that no more entries are
// present
diff --git a/src/osd/sdl/window.h b/src/osd/sdl/window.h
index 098c1823b50..9f6b42790b3 100644
--- a/src/osd/sdl/window.h
+++ b/src/osd/sdl/window.h
@@ -111,8 +111,8 @@ private:
// monitor info
osd_monitor_info * m_monitor;
int m_fullscreen;
- bool m_mouse_captured;
- bool m_mouse_hidden;
+ bool m_mouse_captured;
+ bool m_mouse_hidden;
void measure_fps(int update);
diff --git a/src/osd/windows/window.cpp b/src/osd/windows/window.cpp
index 418c6c6c8f8..fce936a2440 100644
--- a/src/osd/windows/window.cpp
+++ b/src/osd/windows/window.cpp
@@ -1096,7 +1096,7 @@ int win_window_info::complete_create()
SetWindowLongPtr(hwnd, GWLP_USERDATA, (LONG_PTR)this);
// skip the positioning stuff for -video none */
- if (video_config.mode == VIDEO_MODE_NONE)
+ if (video_config.mode == VIDEO_MODE_NONE)
{
set_renderer(osd_renderer::make_for_type(video_config.mode, shared_from_this()));
renderer().create();