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authorGravatarGravatar Miodrag Milanovic <mmicko@gmail.com>2016-06-29 08:34:30 +0200
committerGravatarGravatar Miodrag Milanovic <mmicko@gmail.com>2016-06-29 08:34:30 +0200
commit63f9a01f8c5d43b9cfe68c2d401a84647d19c10e (patch)
treea1f1874aa84850bddbebd2b0e0bfc3e1c77ce8c4
parent1f6f1bfd6cfb748d9c5e159d6bd014bab8d30944 (diff)
Cleanup and version bumpmame0175
-rw-r--r--android-project/app/src/main/AndroidManifest.xml4
-rw-r--r--hash/bbca_cass.xml2
-rw-r--r--hash/cdi.xml12
-rw-r--r--hash/fmtowns_cd.xml388
-rw-r--r--hash/gba.xml10
-rw-r--r--hash/intv.xml2
-rw-r--r--hash/leapster.xml12
-rw-r--r--hash/megadriv.xml24
-rw-r--r--hash/n64.xml14
-rw-r--r--hash/pc98.xml6
-rw-r--r--hash/pc98_cd.xml102
-rw-r--r--hash/pce_tourvision.xml2
-rw-r--r--hash/pippin.xml48
-rw-r--r--hash/pofo.xml4
-rw-r--r--hash/snes.xml12
-rw-r--r--hash/vsmile_cart.xml22
-rw-r--r--hash/vsmile_cd.xml22
-rw-r--r--makefile4
-rw-r--r--src/devices/bus/electron/exp.cpp2
-rw-r--r--src/devices/bus/electron/exp.h146
-rw-r--r--src/devices/bus/gameboy/mbc.cpp33
-rw-r--r--src/devices/bus/gameboy/mbc.h2
-rw-r--r--src/devices/bus/gba/gba_slot.h2
-rw-r--r--src/devices/bus/gba/rom.cpp73
-rw-r--r--src/devices/bus/gba/rom.h34
-rw-r--r--src/devices/bus/isa/cga.cpp8
-rw-r--r--src/devices/bus/macpds/macpds.h2
-rw-r--r--src/devices/bus/megadrive/rom.cpp2
-rw-r--r--src/devices/bus/megadrive/rom.h2
-rw-r--r--src/devices/bus/nes/bootleg.cpp27
-rw-r--r--src/devices/bus/nes/bootleg.h4
-rw-r--r--src/devices/bus/nes/kaiser.cpp37
-rw-r--r--src/devices/bus/nes/kaiser.h12
-rw-r--r--src/devices/bus/nubus/nubus_image.h2
-rw-r--r--src/devices/bus/pofo/exp.h76
-rw-r--r--src/devices/bus/pofo/hpc101.h6
-rw-r--r--src/devices/bus/pofo/hpc102.h10
-rw-r--r--src/devices/bus/sg1000_exp/fm_unit.cpp3
-rw-r--r--src/devices/bus/sg1000_exp/sk1100.cpp1
-rw-r--r--src/devices/cpu/asap/asapdasm.cpp2
-rw-r--r--src/devices/cpu/avr8/avr8.cpp2
-rw-r--r--src/devices/cpu/drcbex64.cpp1
-rw-r--r--src/devices/cpu/drcbex64.h1
-rw-r--r--src/devices/cpu/m6502/odeco16.lst2
-rw-r--r--src/devices/cpu/mb86235/mb86235d.cpp58
-rw-r--r--src/devices/cpu/nec/v25.h4
-rw-r--r--src/devices/cpu/patinhofeio/patinho_feio.cpp36
-rw-r--r--src/devices/cpu/patinhofeio/patinhofeio_cpu.h38
-rw-r--r--src/devices/cpu/sharc/sharc.cpp8
-rw-r--r--src/devices/cpu/sharc/sharc.h38
-rw-r--r--src/devices/cpu/sharc/sharcdrc.cpp2098
-rw-r--r--src/devices/cpu/sharc/sharcfe.cpp802
-rw-r--r--src/devices/cpu/sparc/mb86901.cpp1175
-rw-r--r--src/devices/cpu/sparc/sparc.h102
-rw-r--r--src/devices/cpu/sparc/sparcdefs.h738
-rw-r--r--src/devices/cpu/tms32010/tms32010.h4
-rw-r--r--src/devices/cpu/tms32025/tms32025.h6
-rw-r--r--src/devices/imagedev/cassette.cpp8
-rw-r--r--src/devices/machine/68230pit.cpp188
-rw-r--r--src/devices/machine/68230pit.h36
-rw-r--r--src/devices/machine/8530scc.cpp16
-rw-r--r--src/devices/machine/eeprom.h2
-rw-r--r--src/devices/machine/ldp1000.cpp28
-rw-r--r--src/devices/machine/ldp1000.h24
-rw-r--r--src/devices/machine/ldv1000.cpp4
-rw-r--r--src/devices/machine/ldv1000.h2
-rw-r--r--src/devices/machine/pci-ide.cpp1
-rw-r--r--src/devices/machine/scnxx562.cpp1079
-rw-r--r--src/devices/machine/scnxx562.h348
-rw-r--r--src/devices/machine/z80scc.h24
-rw-r--r--src/devices/video/zeus2.cpp51
-rw-r--r--src/emu/debug/debugcmd.cpp38
-rw-r--r--src/emu/debug/debugcmd.h6
-rw-r--r--src/emu/debug/debugcon.h8
-rw-r--r--src/emu/debug/debugcpu.cpp62
-rw-r--r--src/emu/debug/debugcpu.h39
-rw-r--r--src/emu/debug/debughlp.cpp2
-rw-r--r--src/emu/debugger.cpp2
-rw-r--r--src/emu/device.cpp12
-rw-r--r--src/emu/emumem.cpp18
-rw-r--r--src/emu/emumem.h6
-rw-r--r--src/emu/emuopts.h2
-rw-r--r--src/emu/hashfile.cpp4
-rw-r--r--src/emu/romload.cpp2
-rw-r--r--src/emu/screen.h76
-rw-r--r--src/frontend/mame/cheat.cpp6
-rw-r--r--src/frontend/mame/cheat.h18
-rw-r--r--src/frontend/mame/ui/auditmenu.cpp1
-rw-r--r--src/frontend/mame/ui/auditmenu.h1
-rw-r--r--src/frontend/mame/ui/barcode.cpp3
-rw-r--r--src/frontend/mame/ui/barcode.h1
-rw-r--r--src/frontend/mame/ui/cheatopt.cpp1
-rw-r--r--src/frontend/mame/ui/cheatopt.h1
-rw-r--r--src/frontend/mame/ui/custmenu.cpp1
-rw-r--r--src/frontend/mame/ui/custmenu.h1
-rw-r--r--src/frontend/mame/ui/custui.cpp1
-rw-r--r--src/frontend/mame/ui/custui.h1
-rw-r--r--src/frontend/mame/ui/datfile.cpp2
-rw-r--r--src/frontend/mame/ui/datmenu.cpp1
-rw-r--r--src/frontend/mame/ui/datmenu.h1
-rw-r--r--src/frontend/mame/ui/devctrl.h1
-rw-r--r--src/frontend/mame/ui/devopt.cpp1
-rw-r--r--src/frontend/mame/ui/devopt.h1
-rw-r--r--src/frontend/mame/ui/dirmenu.cpp1
-rw-r--r--src/frontend/mame/ui/dirmenu.h1
-rw-r--r--src/frontend/mame/ui/filemngr.cpp3
-rw-r--r--src/frontend/mame/ui/filemngr.h1
-rw-r--r--src/frontend/mame/ui/filesel.cpp1
-rw-r--r--src/frontend/mame/ui/filesel.h3
-rw-r--r--src/frontend/mame/ui/floppycntrl.cpp1
-rw-r--r--src/frontend/mame/ui/floppycntrl.h1
-rw-r--r--src/frontend/mame/ui/imgcntrl.cpp1
-rw-r--r--src/frontend/mame/ui/imgcntrl.h1
-rw-r--r--src/frontend/mame/ui/info.cpp1
-rw-r--r--src/frontend/mame/ui/info.h1
-rw-r--r--src/frontend/mame/ui/info_pty.cpp1
-rw-r--r--src/frontend/mame/ui/info_pty.h1
-rw-r--r--src/frontend/mame/ui/inputmap.cpp1
-rw-r--r--src/frontend/mame/ui/inputmap.h1
-rw-r--r--src/frontend/mame/ui/mainmenu.cpp1
-rw-r--r--src/frontend/mame/ui/mainmenu.h1
-rw-r--r--src/frontend/mame/ui/menu.cpp5
-rw-r--r--src/frontend/mame/ui/menu.h1
-rw-r--r--src/frontend/mame/ui/menuitem.h1
-rw-r--r--src/frontend/mame/ui/miscmenu.cpp1
-rw-r--r--src/frontend/mame/ui/miscmenu.h1
-rw-r--r--src/frontend/mame/ui/optsmenu.cpp1
-rw-r--r--src/frontend/mame/ui/optsmenu.h1
-rw-r--r--src/frontend/mame/ui/pluginopt.cpp1
-rw-r--r--src/frontend/mame/ui/pluginopt.h1
-rw-r--r--src/frontend/mame/ui/selector.cpp1
-rw-r--r--src/frontend/mame/ui/selector.h1
-rw-r--r--src/frontend/mame/ui/selgame.cpp9
-rw-r--r--src/frontend/mame/ui/selgame.h1
-rw-r--r--src/frontend/mame/ui/selsoft.cpp1
-rw-r--r--src/frontend/mame/ui/selsoft.h1
-rw-r--r--src/frontend/mame/ui/simpleselgame.cpp1
-rw-r--r--src/frontend/mame/ui/simpleselgame.h1
-rw-r--r--src/frontend/mame/ui/slider.h2
-rw-r--r--src/frontend/mame/ui/sliders.cpp17
-rw-r--r--src/frontend/mame/ui/sliders.h1
-rw-r--r--src/frontend/mame/ui/slotopt.cpp1
-rw-r--r--src/frontend/mame/ui/slotopt.h1
-rw-r--r--src/frontend/mame/ui/sndmenu.cpp1
-rw-r--r--src/frontend/mame/ui/sndmenu.h1
-rw-r--r--src/frontend/mame/ui/submenu.cpp1
-rw-r--r--src/frontend/mame/ui/submenu.h1
-rw-r--r--src/frontend/mame/ui/swlist.cpp1
-rw-r--r--src/frontend/mame/ui/swlist.h1
-rw-r--r--src/frontend/mame/ui/tapectrl.cpp1
-rw-r--r--src/frontend/mame/ui/tapectrl.h1
-rw-r--r--src/frontend/mame/ui/text.cpp9
-rw-r--r--src/frontend/mame/ui/text.h5
-rw-r--r--src/frontend/mame/ui/ui.h55
-rw-r--r--src/frontend/mame/ui/utils.cpp2
-rw-r--r--src/frontend/mame/ui/videoopt.cpp1
-rw-r--r--src/frontend/mame/ui/videoopt.h1
-rw-r--r--src/frontend/mame/ui/viewgfx.cpp2
-rw-r--r--src/lib/netlist/plib/pchrono.h2
-rw-r--r--src/lib/netlist/solver/nld_ms_sm.h4
-rw-r--r--src/lib/netlist/solver/nld_ms_w.h2
-rw-r--r--src/lib/util/timeconv.cpp10
-rw-r--r--src/lib/util/timeconv.h11
-rw-r--r--src/mame/audio/mario.cpp2
-rw-r--r--src/mame/drivers/8080bw.cpp16
-rw-r--r--src/mame/drivers/abc80x.cpp40
-rw-r--r--src/mame/drivers/aerofgt.cpp10
-rw-r--r--src/mame/drivers/alesis_qs.cpp38
-rw-r--r--src/mame/drivers/altair.cpp4
-rw-r--r--src/mame/drivers/aristmk5.cpp3
-rw-r--r--src/mame/drivers/aristmk6.cpp154
-rw-r--r--src/mame/drivers/atarigx2.cpp12
-rw-r--r--src/mame/drivers/atlantis.cpp4
-rw-r--r--src/mame/drivers/bfcobra.cpp2
-rw-r--r--src/mame/drivers/bloodbro.cpp2
-rw-r--r--src/mame/drivers/cclimber.cpp28
-rw-r--r--src/mame/drivers/chihiro.cpp2
-rw-r--r--src/mame/drivers/deco_ld.cpp4
-rwxr-xr-xsrc/mame/drivers/divebomb.cpp222
-rw-r--r--src/mame/drivers/dlair.cpp8
-rw-r--r--src/mame/drivers/esh.cpp31
-rw-r--r--src/mame/drivers/fccpu30.cpp491
-rw-r--r--src/mame/drivers/fidel6502.cpp6
-rw-r--r--src/mame/drivers/funkball.cpp4
-rw-r--r--src/mame/drivers/galaxian.cpp2
-rw-r--r--src/mame/drivers/galivan.cpp10
-rw-r--r--src/mame/drivers/gba.cpp4
-rw-r--r--src/mame/drivers/go2000.cpp2
-rw-r--r--src/mame/drivers/goldnpkr.cpp20
-rw-r--r--src/mame/drivers/goldstar.cpp64
-rw-r--r--src/mame/drivers/halleys.cpp8
-rw-r--r--src/mame/drivers/hh_cop400.cpp2
-rw-r--r--src/mame/drivers/hh_tms1k.cpp10
-rw-r--r--src/mame/drivers/holeland.cpp8
-rw-r--r--src/mame/drivers/homedata.cpp74
-rw-r--r--src/mame/drivers/kickgoal.cpp2
-rw-r--r--src/mame/drivers/leland.cpp1
-rw-r--r--src/mame/drivers/lgp.cpp8
-rw-r--r--src/mame/drivers/m63.cpp2
-rw-r--r--src/mame/drivers/magicfly.cpp4
-rw-r--r--src/mame/drivers/megasys1.cpp136
-rw-r--r--src/mame/drivers/metlfrzr.cpp27
-rw-r--r--src/mame/drivers/mgames.cpp2
-rw-r--r--src/mame/drivers/naomi.cpp4
-rw-r--r--src/mame/drivers/neogeo.cpp4
-rw-r--r--src/mame/drivers/pasopia7.cpp4
-rw-r--r--src/mame/drivers/patinho_feio.cpp32
-rw-r--r--src/mame/drivers/pc9801.cpp2
-rw-r--r--src/mame/drivers/rainbow.cpp2
-rw-r--r--src/mame/drivers/sg1000.cpp4
-rw-r--r--src/mame/drivers/sun2.cpp256
-rw-r--r--src/mame/drivers/sun3.cpp266
-rw-r--r--src/mame/drivers/sun4.cpp164
-rw-r--r--src/mame/drivers/system16.cpp18
-rwxr-xr-xsrc/mame/drivers/tek440x.cpp86
-rw-r--r--src/mame/drivers/toaplan1.cpp2
-rw-r--r--src/mame/drivers/toaplan2.cpp24
-rw-r--r--src/mame/drivers/toratora.cpp24
-rw-r--r--src/mame/drivers/vegas.cpp8
-rw-r--r--src/mame/drivers/vsmilepro.cpp10
-rw-r--r--src/mame/drivers/x1.cpp2
-rw-r--r--src/mame/includes/aerofgt.h2
-rw-r--r--src/mame/includes/atarigx2.h8
-rw-r--r--src/mame/includes/divebomb.h140
-rw-r--r--src/mame/includes/gameplan.h2
-rw-r--r--src/mame/includes/megasys1.h2
-rw-r--r--src/mame/includes/namconb1.h2
-rw-r--r--src/mame/includes/nmk16.h2
-rw-r--r--src/mame/includes/plygonet.h2
-rw-r--r--src/mame/includes/sg1000.h2
-rw-r--r--src/mame/includes/tsamurai.h2
-rw-r--r--src/mame/layout/patinho.lay260
-rw-r--r--src/mame/machine/atarixga.h62
-rw-r--r--src/mame/machine/dccons.cpp12
-rw-r--r--src/mame/machine/dec_lk201.cpp36
-rw-r--r--src/mame/machine/dec_lk201.h8
-rw-r--r--src/mame/machine/fd1094.cpp2
-rw-r--r--src/mame/machine/kaneko_toybox.cpp2
-rw-r--r--src/mame/machine/m2comm.cpp6
-rw-r--r--src/mame/machine/namcoic.cpp4
-rw-r--r--src/mame/machine/pcecommn.h2
-rw-r--r--src/mame/machine/seibucop/seibucop.cpp128
-rw-r--r--src/mame/machine/seibucop/seibucop.h24
-rw-r--r--src/mame/machine/sms.cpp4
-rw-r--r--src/mame/machine/xbox.cpp22
-rw-r--r--src/mame/mame.lst6
-rw-r--r--src/mame/video/chihiro.cpp2
-rw-r--r--src/mame/video/divebomb.cpp172
-rw-r--r--src/mame/video/exerion.cpp4
-rw-r--r--src/mame/video/gotya.cpp6
-rw-r--r--src/mame/video/homedata.cpp10
-rw-r--r--src/mame/video/megasys1.cpp2
-rw-r--r--src/mame/video/model3.cpp82
-rw-r--r--src/mame/video/namconb1.cpp4
-rw-r--r--src/mame/video/namcos2.cpp2
-rw-r--r--src/mame/video/powervr2.cpp2
-rw-r--r--src/mame/video/seibu_crtc.cpp2
-rw-r--r--src/mame/video/vtvideo.cpp6
-rw-r--r--src/osd/modules/debugger/debugimgui.cpp10
-rw-r--r--src/osd/modules/diagnostics/diagnostics_win32.cpp2
-rw-r--r--src/osd/modules/file/posixdir.cpp10
-rw-r--r--src/osd/modules/file/windir.cpp2
-rw-r--r--src/osd/modules/font/font_dwrite.cpp2
-rw-r--r--src/osd/modules/input/input_sdl.cpp2
-rw-r--r--src/osd/modules/input/input_windows.cpp4
-rw-r--r--src/osd/modules/input/input_xinput.cpp2
-rw-r--r--src/osd/modules/lib/osdlib.h1
-rw-r--r--src/osd/modules/lib/osdlib_macosx.cpp5
-rw-r--r--src/osd/modules/lib/osdlib_unix.cpp5
-rw-r--r--src/osd/modules/lib/osdlib_win32.cpp5
-rw-r--r--src/osd/modules/netdev/pcap.cpp2
-rw-r--r--src/osd/modules/output/output_module.h2
-rw-r--r--src/osd/modules/render/bgfx/chain.cpp50
-rw-r--r--src/osd/modules/render/bgfx/chain.h6
-rw-r--r--src/osd/modules/render/bgfx/chainmanager.cpp46
-rw-r--r--src/osd/modules/render/bgfx/targetmanager.cpp4
-rw-r--r--src/osd/modules/render/d3d/d3dhlsl.cpp2
-rw-r--r--src/osd/modules/render/drawd3d.cpp22
-rw-r--r--src/osd/modules/render/winglcontext.h2
-rwxr-xr-xsrc/osd/modules/sound/xaudio2_sound.cpp4
-rw-r--r--src/osd/osdcore.h20
-rw-r--r--src/osd/sdl/window.h4
-rw-r--r--src/osd/windows/window.cpp2
283 files changed, 6074 insertions, 6164 deletions
diff --git a/android-project/app/src/main/AndroidManifest.xml b/android-project/app/src/main/AndroidManifest.xml
index b1984995b6b..2397b5e01e8 100644
--- a/android-project/app/src/main/AndroidManifest.xml
+++ b/android-project/app/src/main/AndroidManifest.xml
@@ -4,8 +4,8 @@
-->
<manifest xmlns:android="http://schemas.android.com/apk/res/android"
package="org.mamedev.mame"
- android:versionCode="174"
- android:versionName="0.174"
+ android:versionCode="175"
+ android:versionName="0.175"
android:installLocation="auto">
<!-- Android 4.0 -->
diff --git a/hash/bbca_cass.xml b/hash/bbca_cass.xml
index a463cf8c40d..a8e593716e3 100644
--- a/hash/bbca_cass.xml
+++ b/hash/bbca_cass.xml
@@ -61,7 +61,7 @@
</dataarea>
</part>
</software>
-
+
<software name="beebtrek">
<description>Beebtrek</description>
<year>1982</year>
diff --git a/hash/cdi.xml b/hash/cdi.xml
index 18243f3c8b7..d796e9e6314 100644
--- a/hash/cdi.xml
+++ b/hash/cdi.xml
@@ -2,9 +2,9 @@
<!DOCTYPE softwarelist SYSTEM "softwarelist.dtd">
<softwarelist name="cdi" description="CD-i CD-ROMs">
-<!--
- These are converted from old TOSEC set (I think v2009-04-05), but a double check is being performed, at
- least for discs that can still be found for this set
+<!--
+ These are converted from old TOSEC set (I think v2009-04-05), but a double check is being performed, at
+ least for discs that can still be found for this set
-->
<software name="3degree">
@@ -10591,7 +10591,7 @@
<!--
- These are converted from rips released on the web
+ These are converted from rips released on the web
-->
<software name="frogfeas">
@@ -10647,7 +10647,7 @@
Origin: Unknown
<rom name="voyeur ii (v1.04)(11-06-96)(testing-beta)(access code 3333) (disc1).bin" size="601528704" crc="0a337e76" sha1="10c15630f7cbcfc7751e7ae1948947cad48850b2" offset="0" />
<rom name="voyeur ii (v1.04)(11-06-96)(testing-beta)(access code 3333) (disc1).cue" size="133" crc="7d9bbe3f" sha1="fc746593b61ac9d3d24296a0c1ab7101b25db49d" offset="0" />
-
+
<rom name="voyeur ii (v1.04)(11-06-96)(testing-beta)(access code 3333) (disc2).bin" size="595354704" crc="8024edf4" sha1="ba86e8850304afb918e2a4c7411e8648b3f90a4a" offset="0" />
<rom name="voyeur ii (v1.04)(11-06-96)(testing-beta)(access code 3333) (disc2).cue" size="133" crc="7cc698ee" sha1="3622939d9c37f43749907cc964cc4738e58ad3b7" offset="0" />
-->
@@ -10670,7 +10670,7 @@
<!--
- These are non-tosec sourced, and could be bad
+ These are non-tosec sourced, and could be bad
-->
diff --git a/hash/fmtowns_cd.xml b/hash/fmtowns_cd.xml
index b63da2e8367..e637afc8f29 100644
--- a/hash/fmtowns_cd.xml
+++ b/hash/fmtowns_cd.xml
@@ -6,7 +6,7 @@
Known undumped discs (possibly more exist, and some CDs marked as FMT could actually be for Marty and vice versa), based on Blitzkrieg's researches
-
+
FM-Towns Marty CDs
==================
? 0 Hoshi Uranai Jutsu Dai Rei Gen Feb-90 Victor (CDx1)
@@ -100,186 +100,186 @@
High School War Sep-94 I.S.C. (CDx1)
Hiouden 2 Mar-94 Telenet Japan (CDx1)
If Jun-93 Active (CDx1)
- If 2 Nov-93 Active (CDx1)
- If 3 Apr-95 Active (CDx1)
+ If 2 Nov-93 Active (CDx1)
+ If 3 Apr-95 Active (CDx1)
Igo Doujou Shodan Kaigan! Kyuu Karadane no Chousen May-91 Fujitsu (CDx1)
Igo Doujou Yaburi Menkyokaiden!! Mezase 7-Kyuu Oct-90 Fujitsu (CDx1)
- Inindou: Datou Nobunaga Feb-92 Koei (CDx1)
- Introduction to Go Dojo Jun-91 GAM (CDx1)
- Intruder: Sakura Yashiki no Tansaku XXX-89 Alice Soft (CDx1)
- Irisu-tei Sayokyoku Nov-92 Agumix (CDx1)
- Ishin no Arashi Mar-90 Koei (CDx1)
- J-League Professional Soccer 1994 Sep-94 Victor (CDx1)
- Jinmon Yuugi Aug-95 Fairytale - Red Zone (CDx1)
- Joker Towns Jul-92 Birdy Soft (CDx1)
- Joshikou Seifuku Monogatari Apr-95 KSS (CDx1)
- JYB Apr-93 Cocktail Soft (CDx1)
- Kamigami No Daichi: Kojiki Gaiden Oct-93 Koei (CDx1)
+ Inindou: Datou Nobunaga Feb-92 Koei (CDx1)
+ Introduction to Go Dojo Jun-91 GAM (CDx1)
+ Intruder: Sakura Yashiki no Tansaku XXX-89 Alice Soft (CDx1)
+ Irisu-tei Sayokyoku Nov-92 Agumix (CDx1)
+ Ishin no Arashi Mar-90 Koei (CDx1)
+ J-League Professional Soccer 1994 Sep-94 Victor (CDx1)
+ Jinmon Yuugi Aug-95 Fairytale - Red Zone (CDx1)
+ Joker Towns Jul-92 Birdy Soft (CDx1)
+ Joshikou Seifuku Monogatari Apr-95 KSS (CDx1)
+ JYB Apr-93 Cocktail Soft (CDx1)
+ Kamigami No Daichi: Kojiki Gaiden Oct-93 Koei (CDx1)
Kero Kero Keroppi to Origami no Tabibito Jul-95 Fujitsu (CDx1)
- Kikou Shidan 2 Mar-93 Artdink (CDx1)
- Kouryuuki Oct-93 Koei (CDx1)
- Kousoku Choujin Aug-96 Foster Japan (CDx1)
- KU2++ Nov-93 Panther Software (CDx1)
- Kusuriyubi no Kyoukasho Apr-96 Active (CDx1)
- Kyouko no Ijiwaru! Oct-94 Ponytail Soft (CDx1)
- L'Empereur Jan-91 Koei (CDx1)
- Leading Company Apr-92 Koei (CDx1)
- Lemon Cocktail Collection Mar-93 Cocktail Soft (CDx1)
- Lipstick Adventure 3 May-93 Fairytale (CDx1)
- Little Big Adventure Dec-95 Electronic Arts (CDx1)
- Lord of the Rings 2: The Two Towers Apr-93 Star Craft (CDx1)
+ Kikou Shidan 2 Mar-93 Artdink (CDx1)
+ Kouryuuki Oct-93 Koei (CDx1)
+ Kousoku Choujin Aug-96 Foster Japan (CDx1)
+ KU2++ Nov-93 Panther Software (CDx1)
+ Kusuriyubi no Kyoukasho Apr-96 Active (CDx1)
+ Kyouko no Ijiwaru! Oct-94 Ponytail Soft (CDx1)
+ L'Empereur Jan-91 Koei (CDx1)
+ Leading Company Apr-92 Koei (CDx1)
+ Lemon Cocktail Collection Mar-93 Cocktail Soft (CDx1)
+ Lipstick Adventure 3 May-93 Fairytale (CDx1)
+ Little Big Adventure Dec-95 Electronic Arts (CDx1)
+ Lord of the Rings 2: The Two Towers Apr-93 Star Craft (CDx1)
Lord of the Rings: The Fellowship of the Ring Mar-92 Star Craft (CDx1)
- Lua Jun-93 Inter Heart (CDx1)
- Mahjong Bishoujo Den Rippuru Feb-95 Foresight (CDx1)
- Mahjong Fantasia 2 Sep-93 Active (CDx1)
- Mahjong Fantasia 3 Nov-95 Active (CDx1)
- Mahjong Goku Apr-89 ASCII (CDx1)
- Mahjong Musashi XXX-89 Computer Cosmos (CDx1)
- Manami no Doko made Iku no May-95 Wendy Magazine (CDx1)
+ Lua Jun-93 Inter Heart (CDx1)
+ Mahjong Bishoujo Den Rippuru Feb-95 Foresight (CDx1)
+ Mahjong Fantasia 2 Sep-93 Active (CDx1)
+ Mahjong Fantasia 3 Nov-95 Active (CDx1)
+ Mahjong Goku Apr-89 ASCII (CDx1)
+ Mahjong Musashi XXX-89 Computer Cosmos (CDx1)
+ Manami no Doko made Iku no May-95 Wendy Magazine (CDx1)
Manami no Doko made Iku no 2: Return of the Kuro Pack May-95 Wendy Magazine (CDx1)
- Manami: Ai to Koukan no Hibi XXX-95 Fairytale - Red Zone (CDx1)
- Marionette Mind Mar-94 Studio Milk (CDx1)
- Mega Lo Mania Mar-93 Imagineer (CDx1)
- Meisou Toshi Dec-95 Tiare (CDx1)
- Might & Magic: World of Xeen Oct-92 Star Craft (CDx1)
- Mirage 2 Dec-94 Discovery (CDx1)
- Misato-chan no Yume Nikki Apr-97 Active (CDx1)
- Moeru Asoko no Pai Pai Yuugi Dec-93 Illusion (CDx1)
- Mokkori Man RPG Jun-94 Illusion (CDx1)
- Monoshiri ji Yuugaku Hyakunin Ichishuhen Oct-94 Shinko Human Request (CDx1)
- Moonlight Energy Dec-92 Inter Heart (CDx1)
- Murder Club DX May-92 Riverhill Soft (CDx1)
- Naru Mahjong Apr-95 Libido (CDx1)
- Nemurenu Yoru no Chisana Ohanashi Dec-93 Amuse (CDx1)
- Never Land Mar-96 Tips (CDx1)
- NHK Hitori de Dekiru Mon! Mar-95 Rei (CDx1)
- Niko 2 Nov-91 Telenet Japan (CDx1)
- Nippon Mukashibanashi Nov-90 Gyosei (CDx1)
- Nippon Mukashibanashi 2 Jul-91 Gyosei (CDx1)
- Nippon Mukashibanashi 3 Dec-93 Gyosei (CDx1)
- Nippon Mukashibanashi 4 Dec-93 Gyosei (CDx1)
- Nippon Mukashibanashi 5 Mar-94 Gyosei (CDx1)
- Nobunaga no Yabou: Bushou Fuunroku Jul-91 Koei (CDx1)
- Nobunaga no Yabou: Sengoku Gunyuu Den Dec-89 Koei (CDx1)
- Nostalgia 1907 May-92 Sur de Wave (CDx1)
- Obachan no Chiebukuro Nov-91 Gyosei (CDx1)
- Oku man Choja 2 Jul-91 Computer Cosmos (CDx1)
- Only You: Juliet of the Century Jan-96 Alice Soft (CDx1)
- Orient Express Dec-94 Gyosei (CDx1)
- Palamedes XXX-91 Ving (CDx1)
- Para Para Paradise Dec-95 Family Soft (CDx2)
- Phobos Aug-95 Himeya Soft, Inc (CDx1)
- Pocky & Ponyon Jun-94 Ponytail Soft (CDx1)
- Populous 2 Feb-93 Imagineer (CDx1)
- Presence Dec-92 Sur de Wave (CDx1)
- Private Slave Aug-93 Raccoon (CDx1)
- ProYakyuu Family Stadium '90 Sep-90 Game Arts (CDx1)
- Reijou Monogatari Apr-95 Inter Heart (CDx1)
- Rinkan Gakkou Feb-96 Foster Japan (CDx1)
- Royal Blood May-92 Koei (CDx1)
- Ryuutatakaden Jun-94 Fujitsu (CDx1)
- Sakura no Mori XXX-95 Active (CDx1)
- Sangokushi 2 Jun-90 Koei (CDx1)
- Sangokushi 3 Jun-92 Koei (CDx1)
- Sargon 5 Nov-92 GAM (CDx1)
- Sayonara no Mukougawa Aug-97 Foster Japan (CDx1)
- Seikatsu Simulation Watashi no Machi May-95 Cocktail Soft (CDx1)
- Sekai no o Hanashi May-92 Gyosei (CDx1)
- Sekigahara Apr-92 Artdink (CDx1)
- Sensual Angels Jan-94 JHV (CDx1)
- Sexy P/K Part 2: World Cup Hen May-95 Birdy Soft (CDx1)
- Sexy P/K Part Nihon Apr-95 Birdy Soft (CDx1)
- Shanghai Dec-90 ASCII (CDx1)
- Shanghai: Great Wall Sep-95 Electronic Arts (CDx1)
- Shooting Towns Mar-90 Amorphous (CDx1)
- SL o mitai! Uruwashi no Joki Kikan-sha Jul-95 Gyosei (CDx1)
- Soft de Hard na Monogatari Apr-89 System Sacom (CDx1)
- Soft de Hard na Monogatari 2 Jul-89 System Sacom (CDx1)
- Sokoban Perfect Jul-90 Thinking Rabbit (CDx1)
- Space Odyssey Galaxy Mar-91 Fujitsu (CDx1)
- Space Odyssey Galaxy 2 Apr-92 Fujitsu (CDx1)
- Steepia Jun-93 Fujitsu (CDx1)
- Steepia Lite Mar-93 Fujitsu (CDx1)
- Suikoden: Tenmei no Chikai Feb-90 Koei (CDx1)
- Super Real Mahjong P2 & P3 + Mar-93 Ving (CDx1)
- Suzaku Oct-92 Wolf Team (CDx1)
- Tactical Tank Corps DX Feb-95 GAM (CDx1)
- Tamashi no Mon: Dante Shinkyoku Yori Jun-93 Koei (CDx1)
- Tania Nov-96 Tips (CDx1)
- Teito Taisen Dec-89 Supersonic (CDx1)
- Teitoku no Ketsudan Apr-90 Koei (CDx1)
- Tenshi-Tachi no Gogo Collection 2 Nov-95 Jast (CDx1)
- Tenshin Ranma May-92 Elf (CDx1)
- Teo: Another Earth Sep-95 Fujitsu (CDx1)
- Teo: Another Earth 2 Jul-96 Fujitsu (CDx1)
- The Playroom Feb-95 Fujitsu (CDx1)
- The Queen of Duellist Alpha Mar-94 Agumix (CDx1)
- The Queen of Duellist Alpha Light Apr-94 Agumix (CDx1)
- Theme Park Sep-95 Electronic Arts (CDx1)
- Time Stripper Mako-chan Jan-96 Foster Japan (CDx1)
- Tokyo Sexy Ave. Jul-94 HOP (CDx1)
- Tokyo-to Dai 24-Ku Dec-92 Artdink (CDx1)
- Tom Snyder's Puppy Love Jul-89 Fujitsu (CDx1)
- Tom Snyder's Puppy Love 2 Mar-93 Fujitsu (CDx1)
- Toushin Toshi Apr-95 Alice Soft (CDx1)
- Trigger Jun-94 ZyX (CDx1)
- Trigger 2 Sep-95 ZyX (CDx1)
- Vampire High School Jun-93 Inter Heart (CDx1)
- Vanishing Point XXX-95 Tiare (CDx1)
- Viper GTS Nov-95 Sogna (CDx1)
- Viper V12 Dec-95 Sogna (CDx1)
- Viper V8 Turbo RS Jun-95 Sogna (CDx1)
- Winning Post May-93 Koei (CDx1)
- Yayo 1-2-3 Jul-93 Hado (CDx1)
- Yayo 4 Feb-93 Hado (CDx1)
- Yes! HG Dec-95 Himeya Soft, Inc (CDx1)
- Youjuu Senki 2 Reimei no Senshi Feb-94 D.O. (CDx1)
- Youjuu Senki: Sajin no Mokushiroku Feb-94 D.O. (CDx1)
- Yume Utsutsu: Dreamy May-92 Megami (CDx1)
- Zan 3 Apr-94 Telenet Japan (CDx1)
- Zenith Feb-95 Himeya Soft, Inc 1
+ Manami: Ai to Koukan no Hibi XXX-95 Fairytale - Red Zone (CDx1)
+ Marionette Mind Mar-94 Studio Milk (CDx1)
+ Mega Lo Mania Mar-93 Imagineer (CDx1)
+ Meisou Toshi Dec-95 Tiare (CDx1)
+ Might & Magic: World of Xeen Oct-92 Star Craft (CDx1)
+ Mirage 2 Dec-94 Discovery (CDx1)
+ Misato-chan no Yume Nikki Apr-97 Active (CDx1)
+ Moeru Asoko no Pai Pai Yuugi Dec-93 Illusion (CDx1)
+ Mokkori Man RPG Jun-94 Illusion (CDx1)
+ Monoshiri ji Yuugaku Hyakunin Ichishuhen Oct-94 Shinko Human Request (CDx1)
+ Moonlight Energy Dec-92 Inter Heart (CDx1)
+ Murder Club DX May-92 Riverhill Soft (CDx1)
+ Naru Mahjong Apr-95 Libido (CDx1)
+ Nemurenu Yoru no Chisana Ohanashi Dec-93 Amuse (CDx1)
+ Never Land Mar-96 Tips (CDx1)
+ NHK Hitori de Dekiru Mon! Mar-95 Rei (CDx1)
+ Niko 2 Nov-91 Telenet Japan (CDx1)
+ Nippon Mukashibanashi Nov-90 Gyosei (CDx1)
+ Nippon Mukashibanashi 2 Jul-91 Gyosei (CDx1)
+ Nippon Mukashibanashi 3 Dec-93 Gyosei (CDx1)
+ Nippon Mukashibanashi 4 Dec-93 Gyosei (CDx1)
+ Nippon Mukashibanashi 5 Mar-94 Gyosei (CDx1)
+ Nobunaga no Yabou: Bushou Fuunroku Jul-91 Koei (CDx1)
+ Nobunaga no Yabou: Sengoku Gunyuu Den Dec-89 Koei (CDx1)
+ Nostalgia 1907 May-92 Sur de Wave (CDx1)
+ Obachan no Chiebukuro Nov-91 Gyosei (CDx1)
+ Oku man Choja 2 Jul-91 Computer Cosmos (CDx1)
+ Only You: Juliet of the Century Jan-96 Alice Soft (CDx1)
+ Orient Express Dec-94 Gyosei (CDx1)
+ Palamedes XXX-91 Ving (CDx1)
+ Para Para Paradise Dec-95 Family Soft (CDx2)
+ Phobos Aug-95 Himeya Soft, Inc (CDx1)
+ Pocky & Ponyon Jun-94 Ponytail Soft (CDx1)
+ Populous 2 Feb-93 Imagineer (CDx1)
+ Presence Dec-92 Sur de Wave (CDx1)
+ Private Slave Aug-93 Raccoon (CDx1)
+ ProYakyuu Family Stadium '90 Sep-90 Game Arts (CDx1)
+ Reijou Monogatari Apr-95 Inter Heart (CDx1)
+ Rinkan Gakkou Feb-96 Foster Japan (CDx1)
+ Royal Blood May-92 Koei (CDx1)
+ Ryuutatakaden Jun-94 Fujitsu (CDx1)
+ Sakura no Mori XXX-95 Active (CDx1)
+ Sangokushi 2 Jun-90 Koei (CDx1)
+ Sangokushi 3 Jun-92 Koei (CDx1)
+ Sargon 5 Nov-92 GAM (CDx1)
+ Sayonara no Mukougawa Aug-97 Foster Japan (CDx1)
+ Seikatsu Simulation Watashi no Machi May-95 Cocktail Soft (CDx1)
+ Sekai no o Hanashi May-92 Gyosei (CDx1)
+ Sekigahara Apr-92 Artdink (CDx1)
+ Sensual Angels Jan-94 JHV (CDx1)
+ Sexy P/K Part 2: World Cup Hen May-95 Birdy Soft (CDx1)
+ Sexy P/K Part Nihon Apr-95 Birdy Soft (CDx1)
+ Shanghai Dec-90 ASCII (CDx1)
+ Shanghai: Great Wall Sep-95 Electronic Arts (CDx1)
+ Shooting Towns Mar-90 Amorphous (CDx1)
+ SL o mitai! Uruwashi no Joki Kikan-sha Jul-95 Gyosei (CDx1)
+ Soft de Hard na Monogatari Apr-89 System Sacom (CDx1)
+ Soft de Hard na Monogatari 2 Jul-89 System Sacom (CDx1)
+ Sokoban Perfect Jul-90 Thinking Rabbit (CDx1)
+ Space Odyssey Galaxy Mar-91 Fujitsu (CDx1)
+ Space Odyssey Galaxy 2 Apr-92 Fujitsu (CDx1)
+ Steepia Jun-93 Fujitsu (CDx1)
+ Steepia Lite Mar-93 Fujitsu (CDx1)
+ Suikoden: Tenmei no Chikai Feb-90 Koei (CDx1)
+ Super Real Mahjong P2 & P3 + Mar-93 Ving (CDx1)
+ Suzaku Oct-92 Wolf Team (CDx1)
+ Tactical Tank Corps DX Feb-95 GAM (CDx1)
+ Tamashi no Mon: Dante Shinkyoku Yori Jun-93 Koei (CDx1)
+ Tania Nov-96 Tips (CDx1)
+ Teito Taisen Dec-89 Supersonic (CDx1)
+ Teitoku no Ketsudan Apr-90 Koei (CDx1)
+ Tenshi-Tachi no Gogo Collection 2 Nov-95 Jast (CDx1)
+ Tenshin Ranma May-92 Elf (CDx1)
+ Teo: Another Earth Sep-95 Fujitsu (CDx1)
+ Teo: Another Earth 2 Jul-96 Fujitsu (CDx1)
+ The Playroom Feb-95 Fujitsu (CDx1)
+ The Queen of Duellist Alpha Mar-94 Agumix (CDx1)
+ The Queen of Duellist Alpha Light Apr-94 Agumix (CDx1)
+ Theme Park Sep-95 Electronic Arts (CDx1)
+ Time Stripper Mako-chan Jan-96 Foster Japan (CDx1)
+ Tokyo Sexy Ave. Jul-94 HOP (CDx1)
+ Tokyo-to Dai 24-Ku Dec-92 Artdink (CDx1)
+ Tom Snyder's Puppy Love Jul-89 Fujitsu (CDx1)
+ Tom Snyder's Puppy Love 2 Mar-93 Fujitsu (CDx1)
+ Toushin Toshi Apr-95 Alice Soft (CDx1)
+ Trigger Jun-94 ZyX (CDx1)
+ Trigger 2 Sep-95 ZyX (CDx1)
+ Vampire High School Jun-93 Inter Heart (CDx1)
+ Vanishing Point XXX-95 Tiare (CDx1)
+ Viper GTS Nov-95 Sogna (CDx1)
+ Viper V12 Dec-95 Sogna (CDx1)
+ Viper V8 Turbo RS Jun-95 Sogna (CDx1)
+ Winning Post May-93 Koei (CDx1)
+ Yayo 1-2-3 Jul-93 Hado (CDx1)
+ Yayo 4 Feb-93 Hado (CDx1)
+ Yes! HG Dec-95 Himeya Soft, Inc (CDx1)
+ Youjuu Senki 2 Reimei no Senshi Feb-94 D.O. (CDx1)
+ Youjuu Senki: Sajin no Mokushiroku Feb-94 D.O. (CDx1)
+ Yume Utsutsu: Dreamy May-92 Megami (CDx1)
+ Zan 3 Apr-94 Telenet Japan (CDx1)
+ Zenith Feb-95 Himeya Soft, Inc 1
FM-Towns Marty CDs
==================
- 4D Boxing Jul-93 Electronic Arts (CDx1)
- 4D Driving Jul-93 Electronic Arts (CDx1)
- Psychic Detective Vol.1: Invitation Nov-93 Data West (CDx1)
- Psychic Detective Vol.2: Memories Apr-94 Data West (CDx1)
- Psychic Detective Vol.3: Aya Jul-94 Data West (CDx1)
- Psychic Detective Vol.4: Orgel Dec-94 Data West (CDx1)
- Psychic Detective Vol.5: Nightmare Apr-95 Data West (CDx1)
- Bible Master 2 Jan-95 Glodia (CDx1)
- Custom Mate Dec-94 Cocktail Soft (CDx1)
- Demon City Mar-94 Cocktail Soft (CDx1)
- Dengeki Nurse 2: More Sexy Dec-94 Cocktail Soft (CDx1)
- Doki Doki Vacation Mar-95 Cocktail Soft (CDx1)
- DOR Best Collection Chapter 1 Apr-93 D.O. (CDx2)
- DOR Best Collection Chapter 2 May-93 D.O. (CDx2)
- Dracula Hakushaku Mar-93 Fairytale (CDx1)
- Emit Vol.1 Mar-94 Koei (CDx1)
- Emit Vol.2 Jul-94 Koei (CDx1)
- Emit Vol.3 Sep-94 Koei (CDx1)
- Fujitsu Habitat 2 May-94 Fujitsu (CDx1)
- Gokko Vol.1: Doctor Nov-94 Mink (CDx1)
- Gokko Vol.2: School Gals Dec-94 Mink (CDx1)
- Gokko Vol.3: Etcetera Dec-94 Mink (CDx1)
- Gokuraku Mandala Feb-94 Fairytale (CDx1)
- Joshikousei Shoujo Densetsu Apr-94 Byakuya Shobou (CDx1)
- Ms. Detective XXX-93 Data West (CDx1)
- Nijiiro Denshoku Musume Aug-94 I.S.C. (CDx1)
- Noushuku Angel 120% Apr-95 Cocktail Soft (CDx1)
- Record of Lodoss War 2 Jun-94 MAC (CDx1)
- Sangokushi 4 Jun-94 Koei (CDx1)
- Shamhat: The Holy Circlet Apr-93 Data West (CDx1)
- Shinjuku Labyrinth ==== Tokuma Shoten (CDx1)
- Teitoku no Ketsudan 2 Jun-94 Koei (CDx1)
- Tokyo Labyrinth Dec-94 Tokuma Shoten (CDx1)
- True Heart Feb-95 Cocktail Soft (CDx1)
- Two Shot Diary Oct-94 Mink 1
- URM Dec-94 JHV (CDx1)
- Virtuacall 2 Dec-95 Fairytale (CDx1)
- Wonpara Wars Feb-95 Mink (CDx1)
- Wonpara Wars 2 Apr-95 Mink (CDx1)
+ 4D Boxing Jul-93 Electronic Arts (CDx1)
+ 4D Driving Jul-93 Electronic Arts (CDx1)
+ Psychic Detective Vol.1: Invitation Nov-93 Data West (CDx1)
+ Psychic Detective Vol.2: Memories Apr-94 Data West (CDx1)
+ Psychic Detective Vol.3: Aya Jul-94 Data West (CDx1)
+ Psychic Detective Vol.4: Orgel Dec-94 Data West (CDx1)
+ Psychic Detective Vol.5: Nightmare Apr-95 Data West (CDx1)
+ Bible Master 2 Jan-95 Glodia (CDx1)
+ Custom Mate Dec-94 Cocktail Soft (CDx1)
+ Demon City Mar-94 Cocktail Soft (CDx1)
+ Dengeki Nurse 2: More Sexy Dec-94 Cocktail Soft (CDx1)
+ Doki Doki Vacation Mar-95 Cocktail Soft (CDx1)
+ DOR Best Collection Chapter 1 Apr-93 D.O. (CDx2)
+ DOR Best Collection Chapter 2 May-93 D.O. (CDx2)
+ Dracula Hakushaku Mar-93 Fairytale (CDx1)
+ Emit Vol.1 Mar-94 Koei (CDx1)
+ Emit Vol.2 Jul-94 Koei (CDx1)
+ Emit Vol.3 Sep-94 Koei (CDx1)
+ Fujitsu Habitat 2 May-94 Fujitsu (CDx1)
+ Gokko Vol.1: Doctor Nov-94 Mink (CDx1)
+ Gokko Vol.2: School Gals Dec-94 Mink (CDx1)
+ Gokko Vol.3: Etcetera Dec-94 Mink (CDx1)
+ Gokuraku Mandala Feb-94 Fairytale (CDx1)
+ Joshikousei Shoujo Densetsu Apr-94 Byakuya Shobou (CDx1)
+ Ms. Detective XXX-93 Data West (CDx1)
+ Nijiiro Denshoku Musume Aug-94 I.S.C. (CDx1)
+ Noushuku Angel 120% Apr-95 Cocktail Soft (CDx1)
+ Record of Lodoss War 2 Jun-94 MAC (CDx1)
+ Sangokushi 4 Jun-94 Koei (CDx1)
+ Shamhat: The Holy Circlet Apr-93 Data West (CDx1)
+ Shinjuku Labyrinth ==== Tokuma Shoten (CDx1)
+ Teitoku no Ketsudan 2 Jun-94 Koei (CDx1)
+ Tokyo Labyrinth Dec-94 Tokuma Shoten (CDx1)
+ True Heart Feb-95 Cocktail Soft (CDx1)
+ Two Shot Diary Oct-94 Mink 1
+ URM Dec-94 JHV (CDx1)
+ Virtuacall 2 Dec-95 Fairytale (CDx1)
+ Wonpara Wars Feb-95 Mink (CDx1)
+ Wonpara Wars 2 Apr-95 Mink (CDx1)
-->
@@ -326,7 +326,7 @@ User/save disks that can be created from the game itself are not included.
</diskarea>
</part>
</software>
-
+
<software name="fbas2110">
<!--
Origin: Neo Kobe Collection
@@ -344,7 +344,7 @@ User/save disks that can be created from the game itself are not included.
</diskarea>
</part>
</software>
-
+
<software name="gnutowns">
<!--
Origin: Neo Kobe Collection
@@ -362,13 +362,13 @@ User/save disks that can be created from the game itself are not included.
</diskarea>
</part>
</software>
-
+
<software name="linuxje3">
<!--
Origin: Neo Kobe Collection
<rom name="[OS] Linux + JE3.mdf" size="760707360" crc="2c93db2b" sha1="992b0e991a6bde293edf059e529ee2321ab6469b"/>
<rom name="[OS] Linux + JE3.mds" size="486" crc="9f8751b3" sha1="bea414de9da5a391b5256855d1ec4beee60e677d"/>
-
+
*after conversion with IsoBuster+EAC *
<rom name="[os] linux + je3.bin" size="760707360" crc="2c93db2b" sha1="992b0e991a6bde293edf059e529ee2321ab6469b"/>
<rom name="[os] linux + je3.cue" size="77" crc="6f8db5a8" sha1="987a7967fd60cba6f61cc3a4246881b2c4119deb"/>
@@ -382,7 +382,7 @@ User/save disks that can be created from the game itself are not included.
</diskarea>
</part>
</software>
-
+
<software name="linuxje4">
<!--
Origin: Neo Kobe Collection
@@ -390,12 +390,12 @@ User/save disks that can be created from the game itself are not included.
<rom name="[OS] Linux + JE4 1995-12 (Disc 1).cue" size="97" crc="7a4e430d" sha1="07ae5837929038f79dfe589f03d264fb88c1f631"/>
<rom name="[OS] Linux + JE4 1995-12 (Disc 1).img" size="577110240" crc="cb8e970c" sha1="8598c7f6c5493c27a2a9b9dcacce04eafcea266d"/>
<rom name="[OS] Linux + JE4 1995-12 (Disc 1).sub" size="23555520" crc="08f228a2" sha1="3c3805ed5ad7567b2c812c30534d3f5906b7c017"/>
-
+
<rom name="[OS] Linux + JE4 1995-12 (Disc 2).ccd" size="772" crc="d0c4f348" sha1="ecf9a17f635112709cff2243b3311508b4b376ed"/>
<rom name="[OS] Linux + JE4 1995-12 (Disc 2).cue" size="97" crc="fe4bd6dd" sha1="93a497c59463ba022523475d4f9b228570086bbf"/>
<rom name="[OS] Linux + JE4 1995-12 (Disc 2).img" size="621911136" crc="4b4045cc" sha1="b88837ead4cdafff6830de34e10cc85994d6957a"/>
<rom name="[OS] Linux + JE4 1995-12 (Disc 2).sub" size="25384128" crc="b2994c95" sha1="7f53ee98031a618a7a06f5f4ba3d51857a6f41a7"/>
-
+
<rom name="[OS] Linux + JE4 1995-12 (Disc 3).ccd" size="772" crc="477cf66e" sha1="cbfe790b5e67fe104bd787f5a654270f75e5ce9b"/>
<rom name="[OS] Linux + JE4 1995-12 (Disc 3).cue" size="97" crc="34985852" sha1="019d58702b954623ff7832e46aebf4d43c38e134"/>
<rom name="[OS] Linux + JE4 1995-12 (Disc 3).img" size="631723680" crc="5c9440f4" sha1="8ee8a9cebe00a45c908bba88ef453e3d426d6260"/>
@@ -420,7 +420,7 @@ User/save disks that can be created from the game itself are not included.
</diskarea>
</part>
</software>
-
+
<software name="oasyswin">
<!--
Origin: Neo Kobe Collection
@@ -436,7 +436,7 @@ User/save disks that can be created from the game itself are not included.
</diskarea>
</part>
</software>
-
+
<software name="tss1110">
<!--
Origin: Neo Kobe Collection
@@ -452,7 +452,7 @@ User/save disks that can be created from the game itself are not included.
</diskarea>
</part>
</software>
-
+
<software name="tss1120">
<!--
Origin: Neo Kobe Collection
@@ -488,7 +488,7 @@ User/save disks that can be created from the game itself are not included.
</diskarea>
</part>
</software>
-
+
<software name="tss1130">
<!--
Origin: Neo Kobe Collection
@@ -504,7 +504,7 @@ User/save disks that can be created from the game itself are not included.
</diskarea>
</part>
</software>
-
+
<software name="tss2110a">
<!--
Origin: Neo Kobe Collection
@@ -530,7 +530,7 @@ User/save disks that can be created from the game itself are not included.
</diskarea>
</part>
</software>
-
+
<software name="tss2151">
<!--
Origin: Neo Kobe Collection
@@ -548,7 +548,7 @@ User/save disks that can be created from the game itself are not included.
</diskarea>
</part>
</software>
-
+
<!-- Missing a floppy disk -->
<software name="win31">
<!--
@@ -572,7 +572,7 @@ User/save disks that can be created from the game itself are not included.
</diskarea>
</part>
</software>
-
+
<software name="win95">
<!--
Origin: Neo Kobe Collection
@@ -588,12 +588,12 @@ User/save disks that can be created from the game itself are not included.
</diskarea>
</part>
</software>
-
-
-
+
+
+
<!-- Game (& Utility) Disks -->
-
-
+
+
<software name="100isshu">
<!--
Origin: Neo Kobe Collection
@@ -5148,7 +5148,7 @@ User/save disks that can be created from the game itself are not included.
Origin: Tokugawa Corporate Forums (yukin)
<rom name="MM3.mdf" size="15523200" crc="926d169b" sha1="107090bdd34e831f27ea979e3fd6a24c86aa418a"/>
<rom name="MM3.mds" size="500" crc="99adcc2f" sha1="1d6b9f2257f821d06d0f85a021e5be5a2f448f03"/>
-
+
CUE file used for CHD conversion:
<rom name="MM3.cue" size="64" crc="5c30fa2b" sha1="7b53d089cbc4fb4fa0d517adafd8f74f8c94a652"/>
-->
diff --git a/hash/gba.xml b/hash/gba.xml
index a28a781dd93..c75e18f84c7 100644
--- a/hash/gba.xml
+++ b/hash/gba.xml
@@ -12327,7 +12327,7 @@
</dataarea>
</part>
</software>
-
+
<software name="v_sharkt" supported="no">
<description>Game Boy Advance Video - Shark Tale (USA, Rev. 6)</description>
<year>2004?</year>
@@ -12340,7 +12340,7 @@
</dataarea>
</part>
</software>
-
+
<software name="v_sharkta" cloneof="v_sharkt" supported="no">
<description>Game Boy Advance Video - Shark Tale (USA, Rev. 5)</description>
<year>2004?</year>
@@ -12379,7 +12379,7 @@
</dataarea>
</part>
</software>
-
+
<software name="v_2shrst" supported="no">
<description>Game Boy Advance Video - Shrek + Shark Tale (USA)</description>
<year>2004?</year>
@@ -30364,7 +30364,7 @@
<publisher>Infogrames</publisher>
<info name="serial" value="AGB-ASOP-(EUR,UKV)"/>
<part name="cart" interface="gba_cart">
- <feature name="pcb" value="AGB-E02-30" /> <!-- Also found on AGB-E02-20 -->
+ <feature name="pcb" value="AGB-E02-30" /> <!-- Also found on AGB-E02-20 -->
<feature name="u1" value="U1 GPIO MASKROM" />
<feature name="u2" value="U2 512K/1M FLASH [39VF512]" />
<feature name="slot" value="gba_flash" />
@@ -32407,7 +32407,7 @@ The cart also contained a non-empty SRAM save which we currently include in the
<publisher>Nintendo</publisher>
<info name="serial" value="AGB-AMAE-USA, AGB-AMAP"/>
<part name="cart" interface="gba_cart">
- <feature name="pcb" value="AGB-E03-01" /> <!-- Also found on AGB-E03-10 -->
+ <feature name="pcb" value="AGB-E03-01" /> <!-- Also found on AGB-E03-10 -->
<feature name="u1" value="U1 MASK ROM" />
<feature name="u2" value="U2 4K/64K EEPROM [9853]" />
<feature name="slot" value="gba_eeprom_4k" />
diff --git a/hash/intv.xml b/hash/intv.xml
index 5156c513b6b..7eb10395850 100644
--- a/hash/intv.xml
+++ b/hash/intv.xml
@@ -958,7 +958,7 @@
</dataarea>
</part>
</software>
-
+
<software name="mspacman" supported="no">
<description>Ms. Pac-Man</description>
<year>1986</year>
diff --git a/hash/leapster.xml b/hash/leapster.xml
index fcbe2c23210..9716b87bc51 100644
--- a/hash/leapster.xml
+++ b/hash/leapster.xml
@@ -188,7 +188,7 @@
</dataarea>
</part>
</software>
-
+
<software name="princwen">
<description>Disney Princess - Worlds of Enchantment (USA)</description>
<year>2007?</year>
@@ -212,7 +212,7 @@
</dataarea>
</part>
</software>
-
+
<software name="findnemo">
<description>Finding Nemo (USA)</description>
<year>2005?</year>
@@ -260,7 +260,7 @@
</dataarea>
</part>
</software>
-
+
<software name="diegogo">
<description>Go Diego Go! - Animal Rescuer (USA)</description>
<year>2007?</year>
@@ -320,7 +320,7 @@
</dataarea>
</part>
</software>
-
+
<software name="brunobls">
<description>Lernst du Malen &amp; Schreiben - Mit Bruno Bleistift (Ger)</description>
<year>2004?</year>
@@ -440,7 +440,7 @@
</dataarea>
</part>
</software>
-
+
<software name="spidermn">
<description>Spider-Man - The Case of the Sinister Speller (USA)</description>
<year>2003</year>
@@ -488,7 +488,7 @@
</dataarea>
</part>
</software>
-
+
<software name="toystor3">
<description>Toy Story 3 (USA)</description>
<year>2010?</year>
diff --git a/hash/megadriv.xml b/hash/megadriv.xml
index c0ac8aac745..1d9703a2736 100644
--- a/hash/megadriv.xml
+++ b/hash/megadriv.xml
@@ -9761,7 +9761,7 @@ but dumps still have to be confirmed.
</dataarea>
</part>
</software>
-
+
<software name="16mj2">
<description>Shi Liu Zhang Ma Jiang II</description>
<year>199?</year>
@@ -13806,7 +13806,7 @@ but dumps still have to be confirmed.
</dataarea>
</part>
</software>
-
+
<software name="deathdlp" cloneof="deathdl">
<description>Death Duel (USA, Prototype 19920506)</description>
<year>1992</year>
@@ -16602,7 +16602,7 @@ but dumps still have to be confirmed.
</dataarea>
</part>
</software>
-
+
<!-- This is the same as the final, but without the padding up to 512Kb and with different checksum in the internal header -->
<software name="homea2p" cloneof="homea2">
<description>Home Alone 2 - Lost in New York (USA, Prototype 19930929)</description>
@@ -21462,7 +21462,7 @@ Notice that these are not working on real hardware due to bugged code with VDP i
</dataarea>
</part>
</software>
-
+
<software name="paperboyp" cloneof="paperboy">
<description>Paperboy (USA, Prototype 19911028)</description>
<year>1992</year>
@@ -22861,7 +22861,7 @@ Notice that these are not working on real hardware due to bugged code with VDP i
</dataarea>
</part>
</software>
-
+
<!-- This is the same as the final, but without the padding up to 1Mb and with no checksum in the internal header -->
<software name="renstimp" cloneof="renstim">
<description>Stimpy's Invention Starring Starring Ren Hoëk &amp; Stimpy (Euro, Prototype 19931209)</description>
@@ -23248,7 +23248,7 @@ Notice that these are not working on real hardware due to bugged code with VDP i
</dataarea>
</part>
</software>
-
+
<software name="roadblstp" cloneof="roadblst">
<description>RoadBlasters (USA, Prototype 19910627)</description>
<year>1992</year>
@@ -25222,7 +25222,7 @@ Notice that these are not working on real hardware due to bugged code with VDP i
</dataarea>
</part>
</software>
-
+
<software name="speedbl2up" cloneof="speedbl2">
<description>Speedball 2 - Brutal Deluxe (USA, Prototype 19910607)</description>
<year>1991</year>
@@ -26377,7 +26377,7 @@ Notice that these are not working on real hardware due to bugged code with VDP i
</dataarea>
</part>
</software>
-
+
<software name="lasordap" cloneof="suprleag">
<description>Tommy Lasorda Baseball (USA, Prototype 19890430)</description>
<year>1989</year>
@@ -27537,7 +27537,7 @@ Notice that these are not working on real hardware due to bugged code with VDP i
</dataarea>
</part>
</software>
-
+
<!-- This is the same as the final, but with "Sega_Channel" XORed at the end. -->
<software name="toejam2p2" cloneof="toejam2">
<description>Toe Jam &amp; Earl in Panic on Funkotron (Prototype 19930911)</description>
@@ -30378,7 +30378,7 @@ Notice that these are not working on real hardware due to bugged code with VDP i
</dataarea>
</part>
</software>
-
+
<software name="xinqig1" cloneof="beggarp">
<description>Xin Qi Gai Wang Zi (Chi, Alt)</description>
<year>1996</year>
@@ -31285,7 +31285,7 @@ Notice that these are not working on real hardware due to bugged code with VDP i
</dataarea>
</part>
</software>
-
+
<software name="cjmjclub">
<description>Chaoji Majiang Club (Tw)</description>
<year>1995</year>
@@ -31360,7 +31360,7 @@ Notice that these are not working on real hardware due to bugged code with VDP i
</dataarea>
</part>
</software>
-
+
<software name="jujimj2">
<description>Ju Ji Ma Jiang II</description>
<year>199?</year>
diff --git a/hash/n64.xml b/hash/n64.xml
index 97c620f58dc..79bfc6a0bfe 100644
--- a/hash/n64.xml
+++ b/hash/n64.xml
@@ -2510,7 +2510,7 @@ patched out (+ a fix for internal checksum)
</part>
</software>
-<!--
+<!--
This cart features a RTC, currently unemulated
-->
<software name="doubutsu">
@@ -5745,7 +5745,7 @@ This cart features a RTC, currently unemulated
</part>
</software>
-<!--
+<!--
This cart features two SmartMedia slots to import pictures to manipulate in the game, currently unemulated
-->
<software name="mariopho">
@@ -6281,7 +6281,7 @@ This cart features two SmartMedia slots to import pictures to manipulate in the
</part>
</software>
-<!--
+<!--
This cart features a built-in RJ-42 Modem Connection port to play online, currently unemulated
-->
<software name="moritash">
@@ -9874,7 +9874,7 @@ patched out (+ a fix for internal checksum)
<part name="cart" interface="n64_cart">
<feature name="pcb" value="NUS-01A-01" />
<feature name="u1" value="NUS-NSMP-0" />
- <feature name="u2" value="BU9850" /> <!-- also found with BK4D-NUS -->
+ <feature name="u2" value="BU9850" /> <!-- also found with BK4D-NUS -->
<feature name="u3" value="CIC-NUS-7101" />
<feature name="cart_model" value="NUS-006(EUR)" />
<feature name="cart_back_label" value="NUS-EUR" />
@@ -10211,9 +10211,9 @@ patched out (+ a fix for internal checksum)
</part>
</software>
-<!--
-The game came with the Nintendo-Seta Bio Sensor, a special controller with a clip on the end, to measure
-user's heart beat. One end of the sensor plugs into the extension port on the controller, and the other end
+<!--
+The game came with the Nintendo-Seta Bio Sensor, a special controller with a clip on the end, to measure
+user's heart beat. One end of the sensor plugs into the extension port on the controller, and the other end
clips onto the player's ear.
-->
<software name="tetris64">
diff --git a/hash/pc98.xml b/hash/pc98.xml
index 77d64bcb512..22b43270c4d 100644
--- a/hash/pc98.xml
+++ b/hash/pc98.xml
@@ -27836,7 +27836,7 @@ Requires MS-DOS 5.00H plus an unknown procedure (HDD install?)
</dataarea>
</part>
</software>
-
+
<!-- confirmed as good by peter_j -->
<software name="3dgolfb" cloneof="3dgolf">
<description>New 3D Golf Simulation - Harukanaru Augusta (Alt Format)</description>
@@ -27872,7 +27872,7 @@ Requires MS-DOS 5.00H plus an unknown procedure (HDD install?)
</dataarea>
</part>
</software>
-
+
<!-- confirmed as good by peter_j -->
<software name="3dgolf8la" cloneof="3dgolf">
<description>New 3D Golf Simulation - Eight Lakes G.C. (Alt Format)</description>
@@ -27917,7 +27917,7 @@ Requires MS-DOS 5.00H plus an unknown procedure (HDD install?)
</dataarea>
</part>
</software>
-
+
<!-- confirmed as good by peter_j -->
<software name="3dgolfwka" cloneof="3dgolf">
<description>New 3D Golf Simulation - Waialae no Kiseki (Alt Format)</description>
diff --git a/hash/pc98_cd.xml b/hash/pc98_cd.xml
index d98f8e69456..ad359b9d292 100644
--- a/hash/pc98_cd.xml
+++ b/hash/pc98_cd.xml
@@ -2,15 +2,15 @@
<!DOCTYPE softwarelist SYSTEM "softwarelist.dtd">
<softwarelist name="pc98_cd" description="NEC PC-9801 CD-ROMs">
- <!--
+ <!--
Partial list of PC-9801/PC-9821 CD-ROMs.
-
+
Floppy disks are also included where needed. They are attached to the floppy_5_25 interface
for convenience, as the PC-98x1 driver always emulates 5.25" drives. This isn't realistic,
though, as CD-ROM software was generally released very late in the life of the plaform,
when 3.5" floppies were much more common.
-
+
-->
<!-- OS disks -->
@@ -20,9 +20,9 @@
<!--
Origin: Unknown
<rom name="Windows 2000 Professional (PC-9821) - W2PCCP_JA.iso" size="409946112" crc="ffffffff" sha1="f0ad97e933a8fe835fdb7211ef9034862b68d7f9"/>
-
+
CUE file used for conversion:
- <rom name="Windows 2000 Professional (PC-9821) - W2PCCP_JA.cue" size="108" crc="5e4281a4" sha1="60b45b2155b2bce7d550f7ed99d4b95247e2c786"/>
+ <rom name="Windows 2000 Professional (PC-9821) - W2PCCP_JA.cue" size="108" crc="5e4281a4" sha1="60b45b2155b2bce7d550f7ed99d4b95247e2c786"/>
-->
<description>Windows 2000 Professional (Upgrade, W2PCCP)</description>
<year>2000</year>
@@ -38,7 +38,7 @@
<!--
Origin: Unknown
<rom name="Windows 2000 Professional (PC-9821) - W2PFPP_JA.iso" size="409946112" crc="ffffffff" sha1="ef5035b8c6b566552eba9f16e085272632e259b4"/>
-
+
CUE file used for conversion:
<rom name="Windows 2000 Professional (PC-9821) - W2PFPP_JA.cue" size="108" crc="90edbbcd" sha1="a2b214d641906d27172e10d35094e652647d4194"/>
-->
@@ -56,7 +56,7 @@
<!--
Origin: Unknown
<rom name="Windows 2000 Professional (PC-9821) - W2PSEL_JA.iso" size="409946112" crc="ffffffff" sha1="b48ebce2da480ab8a7e7b1e82b33bb01543b2b21"/>
-
+
CUE file used for conversion:
<rom name="Windows 2000 Professional (PC-9821) - W2PSEL_JA.cue" size="108" crc="9c9e146b" sha1="0be47b35ebfa297868cadc79bb77bdd56f3aa1ef"/>
-->
@@ -74,7 +74,7 @@
<!--
Origin: Unknown
<rom name="Windows 2000 Professional with SP4 (PC-9821) - ZRMPFPP_JA.iso" size="420202496" crc="ffffffff" sha1="8bf88f199b4919c8d340cd40a80bfb9b6e001f49"/>
-
+
CUE file used for conversion:
<rom name="Windows 2000 Professional with SP4 (PC-9821) - ZRMPFPP_JA.cue" size="118" crc="f4714a5e" sha1="b1890c27ba93ac56e4e7bed741c5323f3695da58"/>
-->
@@ -92,7 +92,7 @@
<!--
Origin: Unknown
<rom name="Windows 2000 Server (PC-9821) - W2SFPP_JA.iso" size="479168512" crc="ffffffff" sha1="57ec6c59bf0d5918031e5e4aa115743616fc5200"/>
-
+
CUE file used for conversion:
<rom name="Windows 2000 Server (PC-9821) - W2SFPP_JA.cue" size="102" crc="a2b02fad" sha1="3086c000c75d4a3a254caa867f7adab8b74ad09f"/>
-->
@@ -110,7 +110,7 @@
<!--
Origin: Unknown
<rom name="Windows 2000 Server (PC-9821) - W2SSEL_JA.iso" size="479168512" crc="ffffffff" sha1="325e1f718981603fc21b88f34643efb71e0ee7e1"/>
-
+
CUE file used for conversion:
<rom name="Windows 2000 Server (PC-9821) - W2SSEL_JA.cue" size="102" crc="aec3800b" sha1="6a64d6297d6906ce672ce77967d3bde940202eac"/>
-->
@@ -128,7 +128,7 @@
<!--
Origin: Unknown
<rom name="Windows 2000 Server with SP4 (PC-9821) - ZRMSFPP_JA.iso" size="488269824" crc="ffffffff" sha1="f43c06cfa45289228ce47f815aa96efb8b9d1574"/>
-
+
CUE file used for conversion:
<rom name="Windows 2000 Server with SP4 (PC-9821) - ZRMSFPP_JA.cue" size="112" crc="6b01db5c" sha1="8b58fb3e2bbfc31d201b4c58e905075da7eb8031"/>
-->
@@ -148,7 +148,7 @@
Origin: Unknown
<rom name="disc2.ISO" size="434356224" crc="ffffffff" sha1="e2db9d9e3aab1401979d103d2d6109bfe3eff3ed"/>
<rom name="image.ISO" size="531824640" crc="ffffffff" sha1="e906c512ec2ab1e6244eec85388551a993bee0a7"/>
-
+
CUE files used for conversion:
<rom name="disc2.cue" size="66" crc="2cabba7b" sha1="38cfe76167cf3065478036c386c69693fa0bf5f3"/>
<rom name="image.cue" size="66" crc="3f846e22" sha1="d3d798255e5d26cd8485a5c5f7aa086a51368ebe"/>
@@ -172,7 +172,7 @@
<!--
Origin: Unknown
<rom name="Microsoft Windows 95 PC-98 (JPN).iso" size="81395712" crc="d402c155" sha1="14d10f62db11397ea46bdf02d1619f1b8e1ff345"/>
-
+
CUE file used for conversion:
<rom name="Microsoft Windows 95 PC-98 (JPN).cue" size="93" crc="c4113669" sha1="3ee6d0113b8efe9cf0ee19fe6054165233fa9906"/>
-->
@@ -191,7 +191,7 @@
<!--
Origin: Unknown
<rom name="Microsoft Windows 98 x86 &amp; PC-98 (JPN).iso" size="508647424" crc="f82c51a9" sha1="3607d2cc8fea57ca915954e9ff2e2cbc82a02fff"/>
-
+
CUE file used for conversion:
<rom name="Microsoft Windows 98 x86 &amp; PC-98 (JPN).cue" size="99" crc="1229745f" sha1="5181dc844bf7f7d5acd3e2fad4ad2e2c8af70297"/>
-->
@@ -309,7 +309,7 @@
</diskarea>
</part>
</software>
-
+
<software name="akikogld">
<!--
Origin: peter_j (Super Lonely Terminal)
@@ -361,13 +361,13 @@
<rom name="Image.cue" size="1488" crc="5585f53a" sha1="ab10e702dcca182e12a551b0fa11c419704dccae"/>
<rom name="Image.img" size="658393008" crc="f3b99e90" sha1="9fcdc50989886636f074354745bbf16bbed24b67"/>
<rom name="Image.sub" size="26873184" crc="eed944ab" sha1="1b486d3f029634da68bd1a2465b6a8a43e75b6c5"/>
-
+
The original CUE indicates MODE1/2352 for the data track, but this seems to be wrong, as all the data
sectors in track 1 are actually mode 2, and MS-DOS doesn't recognize the file system. To avoid this, the
CHD was converted through a modified CUE with MODE2/2352.
-
+
Also, this disc has a PlayStation header in sector 16. Bad dump or just a mastering mistake?
-
+
<rom name="Image_mode2.cue" size="1488" crc="2f235ede" sha1="ecc220ebebb859889406b95d5538f025321e4991"/>
-->
<description>Appare-den - Fukuryuu no Shou</description>
@@ -422,9 +422,9 @@
<!--
Origin: P2P
<rom name="br1.iso" size="4431168" crc="28ca5237" sha1="6de45ad7c24195e9eed8b3f578305698150671aa"/>
-
+
CUE file used for conversion:
- <rom name="br1.cue" size="64" crc="55b42ab8" sha1="f1f3e6612d5c205bbe3c771506ac3a95febe6067"/>
+ <rom name="br1.cue" size="64" crc="55b42ab8" sha1="f1f3e6612d5c205bbe3c771506ac3a95febe6067"/>
-->
<description>Brandish Campaign-ban</description>
<year>1996</year>
@@ -473,9 +473,9 @@
<!--
Origin: P2P
<rom name="br3.iso" size="11275488" crc="8cdbb15b" sha1="692df1bae5459c16469e79b581fb5deb212665e3"/>
-
+
CUE file used for conversion:
- <rom name="br3.cue" size="64" crc="6e9e0d16" sha1="f17c32e361745b7a93fc231826a9af4160692fb4"/>
+ <rom name="br3.cue" size="64" crc="6e9e0d16" sha1="f17c32e361745b7a93fc231826a9af4160692fb4"/>
-->
<description>Brandish 3 - Spirit of Balcan - Campaign-ban</description>
<year>1996</year>
@@ -548,9 +548,9 @@
<!--
Origin: P2P
<rom name="美少女パソコンソフト大全 デジ・パラ Vol.1.iso" size="219504640" crc="e92a4b2a" sha1="10c86cd519a28fc583fd01473eed9d9b3baee789"/>
-
+
CUE file used for conversion:
- <rom name="美少女パソコンソフト大全 デジ・パラ Vol.1.cue" size="119" crc="91bd2775" sha1="ee1f59ef736d2243a75ef86e5c471a72ba9fa222"/>
+ <rom name="美少女パソコンソフト大全 デジ・パラ Vol.1.cue" size="119" crc="91bd2775" sha1="ee1f59ef736d2243a75ef86e5c471a72ba9fa222"/>
-->
<description>Bishoujo Pasocom Soft Taizen - Digi-para - Digital Paradise - Vol. 1</description>
<year>1996</year>
@@ -644,7 +644,7 @@
</diskarea>
</part>
</software>
-
+
<software name="emit1">
<!--
Origin: peter_j (Super Lonely Terminal)
@@ -675,7 +675,7 @@
</diskarea>
</part>
</software>
-
+
<software name="emit2">
<!--
Origin: peter_j (Super Lonely Terminal)
@@ -698,7 +698,7 @@
</diskarea>
</part>
</software>
-
+
<software name="emit3">
<!--
Origin: peter_j (Super Lonely Terminal)
@@ -784,7 +784,7 @@
<rom name="galpani (1995)(kaneko - creo i).ccd" size="3120" crc="788eda2a" sha1="12dd368e864857dc3d206dae6890621536d322da"/>
<rom name="galpani (1995)(kaneko - creo i).img" size="497229264" crc="8b3ce23e" sha1="9bd91b2e62d5847cc65bd363e7a59bd7bda15613"/>
<rom name="galpani (1995)(kaneko - creo i).sub" size="20295072" crc="c2670009" sha1="c0cf2725384ef328682d5c28f017f9dddbc6f28b"/>
-
+
After conversion with IsoBuster + EAC:
<rom name="galpani.cue" size="1725" crc="17aa363e" sha1="4cb40d4ec35eff243114029f3ddc90d81eb646d3"/>
<rom name="track01.bin" size="103473888" crc="18ce00b3" sha1="3d6ed2ff296d77ad8df3e76c2765f1cc5ca69115"/>
@@ -816,7 +816,7 @@
<!--
Origin: P2P
<rom name="GIRI GIRI PARADISE (1996)(May-Be Soft).ISO" size="75416880" crc="881e38b6" sha1="a836803d3af8d9554edfa304d9007bf9176a92db"/>
-
+
CUE file used for conversion:
<rom name="GIRI GIRI PARADISE (1996)(May-Be Soft).cue" size="99" crc="bdb48d15" sha1="f52ce65cbb8f7ee719a6c7874b45149f1a9ac5cd"/>
-->
@@ -866,7 +866,7 @@
</diskarea>
</part>
</software>
-
+
<software name="inhearth">
<!--
Origin unknwon
@@ -941,7 +941,7 @@
</diskarea>
</part>
</software>
-
+
<software name="lodoss">
<!--
Origin unknwon
@@ -1161,9 +1161,9 @@
<!--
Origin: P2P
<rom name="Ponytail Anthology vol.1 (1996)(Ponytail Soft).iso" size="16652288" crc="0c2af0dc" sha1="392fdfdf0de6bc0d469f802b207b38fbd7fef9f6"/>
-
+
CUE file used for conversion:
- <rom name="Ponytail Anthology vol.1 (1996)(Ponytail Soft).cue" size="107" crc="1a019c62" sha1="0ad502b5a8be7e178c05de19d8a74a4542a588e3"/>
+ <rom name="Ponytail Anthology vol.1 (1996)(Ponytail Soft).cue" size="107" crc="1a019c62" sha1="0ad502b5a8be7e178c05de19d8a74a4542a588e3"/>
-->
<description>Ponytail Anthology Vol. 1</description>
<year>1996</year>
@@ -1180,9 +1180,9 @@
<!--
Origin: P2P
<rom name="Ponytail Anthology vol.2 (1996)(Ponytail Soft).iso" size="12025856" crc="216080b4" sha1="42402615993baea8b09987463c6c2ebe08ff93d0"/>
-
+
CUE file used for conversion:
- <rom name="Ponytail Anthology vol.2 (1996)(Ponytail Soft).cue" size="107" crc="c795a04c" sha1="4fef4206c9ee3bb2cae2207313aebbdc21369b39"/>
+ <rom name="Ponytail Anthology vol.2 (1996)(Ponytail Soft).cue" size="107" crc="c795a04c" sha1="4fef4206c9ee3bb2cae2207313aebbdc21369b39"/>
-->
<description>Ponytail Anthology Vol. 2</description>
<year>1996</year>
@@ -1199,9 +1199,9 @@
<!--
Origin: P2P
<rom name="Ponytail Anthology vol.3 (1996)(Ponytail Soft).iso" size="19972096" crc="798581ae" sha1="52b663b863017e21e25c8855ad0da39a89a382d9"/>
-
+
CUE file used for conversion:
- <rom name="Ponytail Anthology vol.3 (1996)(Ponytail Soft).cue" size="107" crc="3a36b669" sha1="9b446abf11350f2d0ea8640f43a3f93784f1e2ce"/>
+ <rom name="Ponytail Anthology vol.3 (1996)(Ponytail Soft).cue" size="107" crc="3a36b669" sha1="9b446abf11350f2d0ea8640f43a3f93784f1e2ce"/>
-->
<description>Ponytail Anthology Vol. 3</description>
<year>1996</year>
@@ -1221,11 +1221,11 @@
<rom name="Image.cue" size="1611" crc="426e02ab" sha1="b41aca944329184740ae31642d209e13123132d7"/>
<rom name="Image.img" size="333958128" crc="26163a8c" sha1="b18171ceba72e72d23ca502e05173158c4de5538"/>
<rom name="Image.sub" size="13630944" crc="5c783df4" sha1="f17dd7023dc4ffad27e4741ba000326e49329bc9"/>
-
+
The original CUE indicates MODE1/2352 for the data track, but this seems to be wrong, as all the data
sectors in track 1 are actually mode 2, and MS-DOS doesn't recognize the file system. To avoid this, the
CHD was converted through a modified CUE with MODE2/2352.
-
+
<rom name="Image_mode2.cue" size="1611" crc="6071e32b" sha1="be8aaa23a63272e7a5b7f3f5972d982345c1d65d"/>
-->
<description>Professional Baseball 1996</description>
@@ -1332,9 +1332,9 @@
<!--
Origin: P2P
<rom name="Ryouki no Ori 1 (1996)(PLANTECH-ZEROSYSTEM).ISO" size="119138304" crc="193e09d1" sha1="caffe3f19e618cc10af3fcbe6df7c48ab717a928"/>
-
+
CUE file used for conversion:
- <rom name="Ryouki no Ori 1 (1996)(PLANTECH-ZEROSYSTEM).cue" size="104" crc="176f9e3f" sha1="22080c96d5566c7de03beb349c5fa026c677fa94"/>
+ <rom name="Ryouki no Ori 1 (1996)(PLANTECH-ZEROSYSTEM).cue" size="104" crc="176f9e3f" sha1="22080c96d5566c7de03beb349c5fa026c677fa94"/>
-->
<description>Ryouki no Ori</description>
<year>1995</year>
@@ -1352,9 +1352,9 @@
<!--
Origin: P2P
<rom name="Ryouki no Ori 2 (1997)(PLANTECH-ZEROSYSTEM).ISO" size="119138304" crc="193e09d1" sha1="caffe3f19e618cc10af3fcbe6df7c48ab717a928"/>
-
+
CUE file used for conversion:
- <rom name="Ryouki no Ori 2 (1997)(PLANTECH-ZEROSYSTEM).cue" size="104" crc="50b6c537" sha1="b64354c20cddc43c21c9e406320e1fd673ee5912"/>
+ <rom name="Ryouki no Ori 2 (1997)(PLANTECH-ZEROSYSTEM).cue" size="104" crc="50b6c537" sha1="b64354c20cddc43c21c9e406320e1fd673ee5912"/>
-->
<description>Ryouki no Ori Dai-2-Shou</description>
<year>1996</year>
@@ -1488,12 +1488,12 @@
</diskarea>
</part>
</software>
-
+
<software name="sela">
<!--
Origin: peter_j (Super Lonely Terminal)
<rom name="sela_cd.iso" size="198440960" crc="82598cf7" sha1="366f4c38b16d865c1e826b447dc566d94633aa7b"/>
-
+
<rom name="sela_music_cd.bin" size="511383600" crc="53c9cd59" sha1="9955790be92eb99d54c449b808e0ccc5e42111d7"/>
<rom name="sela_music_cd.cue" size="714" crc="e92f82d0" sha1="e0d88a3d6d36b69268e0f471db540508e708f26c"/>
-->
@@ -1556,7 +1556,7 @@
</diskarea>
</part>
</software>
-
+
<software name="srmp4f">
<!--
Origin unknwon
@@ -1580,7 +1580,7 @@
<!--
Origin: Unknown
<rom name="strike commander plus.iso" size="86388960" crc="d8953dae" sha1="80f27e2682f41ee5d82a3c8cad59bb5aeb7e9817"/>
-
+
CUE file used for conversion:
<rom name="strike commander plus.cue" size="82" crc="0f9a2f59" sha1="90970d4595d29c7efd90f39e07dea9e46b5e297f"/>
-->
@@ -1595,7 +1595,7 @@
</diskarea>
</part>
</software>
-
+
<!-- This contains some doujin games for PC-98 and some for Windows3.1/95 -->
<software name="takerud1">
<!--
@@ -1712,7 +1712,7 @@
</diskarea>
</part>
</software>
-
+
<software name="usnf">
<!--
Origin: peter_j (Super Lonely Terminal)
@@ -1803,9 +1803,9 @@
<!--
Origin: Unknown
<rom name="ZAI_METAJO CD (1996)(ANJIN).ISO" size="40092192" crc="c41f199f" sha1="08aae335ff1fff2a674a1012be423720f3273535"/>
-
+
CUE file used for conversion:
- <rom name="ZAI_METAJO CD (1996)(ANJIN).cue" size="88" crc="3c3cbf79" sha1="504effcd208f11f867c340d2bc046d46f5519ab5"/>
+ <rom name="ZAI_METAJO CD (1996)(ANJIN).cue" size="88" crc="3c3cbf79" sha1="504effcd208f11f867c340d2bc046d46f5519ab5"/>
-->
<description>Zai Metajo</description>
<year>1996</year>
diff --git a/hash/pce_tourvision.xml b/hash/pce_tourvision.xml
index 1900535d47e..6c3d736309c 100644
--- a/hash/pce_tourvision.xml
+++ b/hash/pce_tourvision.xml
@@ -553,7 +553,7 @@ Notes:
</part>
</software>
-
+
<!--Override -->
<software name="override">
<description>Override (Tourvision PCE bootleg)</description>
diff --git a/hash/pippin.xml b/hash/pippin.xml
index 1f32db3bcb8..80b13e46ad2 100644
--- a/hash/pippin.xml
+++ b/hash/pippin.xml
@@ -106,7 +106,7 @@ NOTE: This list is here only to document available dumps and it's not used (yet)
<software name="hanshind">
<description>1995.1.17 Hanshin Daishinsai (Jpn)</description>
<year>1996</year>
- <publisher>Keikakudo</publisher> <!-- 計画堂 -->
+ <publisher>Keikakudo</publisher> <!-- 計画堂 -->
<info name="serial" value="BDS-20005" />
<info name="alt_title" value="1995.1.17 阪神大震災" />
<part name="cdrom" interface="pippin_cdrom">
@@ -236,7 +236,7 @@ NOTE: This list is here only to document available dumps and it's not used (yet)
<software name="chisatom">
<description>Chisato Moritaka CD-Rom Watarase Bashi (Jpn)</description>
<year>1996</year>
- <publisher>Oracion</publisher> <!-- オラシオン -->
+ <publisher>Oracion</publisher> <!-- オラシオン -->
<info name="serial" value="BDE-10007" />
<info name="alt_title" value="森高千里CD-ROM 渡良瀬橋" />
<part name="cdrom" interface="pippin_cdrom">
@@ -249,7 +249,7 @@ NOTE: This list is here only to document available dumps and it's not used (yet)
<software name="circus">
<description>Circus! (Jpn)</description>
<year>1996</year>
- <publisher>Voyager</publisher> <!-- ボイジャー -->
+ <publisher>Voyager</publisher> <!-- ボイジャー -->
<info name="serial" value="BDS-20031" />
<info name="alt_title" value="サーカス!" />
<part name="cdrom" interface="pippin_cdrom">
@@ -274,7 +274,7 @@ NOTE: This list is here only to document available dumps and it's not used (yet)
<software name="dazzloid">
<description>Dazzeloids (Jpn)</description>
<year>1996</year>
- <publisher>Voyager</publisher> <!-- ボイジャー -->
+ <publisher>Voyager</publisher> <!-- ボイジャー -->
<info name="serial" value="BDS-20030" />
<info name="alt_title" value="ダズロイド" />
<part name="cdrom" interface="pippin_cdrom">
@@ -336,7 +336,7 @@ NOTE: This list is here only to document available dumps and it's not used (yet)
<software name="ffaliens">
<description>Funky Funny Aliens (Jpn)</description>
<year>1996</year>
- <publisher>Amuse</publisher> <!-- アミューズ -->
+ <publisher>Amuse</publisher> <!-- アミューズ -->
<info name="serial" value="BDS-20014" />
<info name="alt_title" value="ファンキー ファニー エイリアンズ" />
<part name="cdrom" interface="pippin_cdrom">
@@ -349,7 +349,7 @@ NOTE: This list is here only to document available dumps and it's not used (yet)
<software name="gadget">
<description>Gadget (Jpn)</description>
<year>1996</year>
- <publisher>Synergy Ikunangaku</publisher> <!-- シナジー幾何学 -->
+ <publisher>Synergy Ikunangaku</publisher> <!-- シナジー幾何学 -->
<info name="serial" value="BDS-20033" />
<part name="cdrom" interface="pippin_cdrom">
<diskarea name="cdrom">
@@ -361,7 +361,7 @@ NOTE: This list is here only to document available dumps and it's not used (yet)
<software name="gakkoku">
<description>Gakko no Kowai Uwasa - Hanako-san ga Kita!! (Jpn)</description>
<year>1996</year>
- <publisher>Amuse</publisher> <!-- アミューズ -->
+ <publisher>Amuse</publisher> <!-- アミューズ -->
<info name="serial" value="BDS-20012" />
<info name="alt_title" value="学校のコワイうわさ 花子さんがきた!!" />
<part name="cdrom" interface="pippin_cdrom">
@@ -425,7 +425,7 @@ NOTE: This list is here only to document available dumps and it's not used (yet)
<software name="kidsbox">
<description>Kids Box (Jpn)</description>
<year>1996</year>
- <publisher>Ask Kodansha</publisher> <!-- アスク講談社 -->
+ <publisher>Ask Kodansha</publisher> <!-- アスク講談社 -->
<info name="serial" value="BDS-20003" />
<info name="alt_title" value="キッズ・ボックス" />
<part name="cdrom" interface="pippin_cdrom">
@@ -475,7 +475,7 @@ NOTE: This list is here only to document available dumps and it's not used (yet)
<software name="lzone">
<description>L-Zone (Jpn)</description>
<year>1996</year>
- <publisher>Synergy Ikunangaku</publisher> <!-- シナジー幾何学 -->
+ <publisher>Synergy Ikunangaku</publisher> <!-- シナジー幾何学 -->
<info name="serial" value="BDS-20017" />
<part name="cdrom" interface="pippin_cdrom">
<diskarea name="cdrom">
@@ -561,7 +561,7 @@ NOTE: This list is here only to document available dumps and it's not used (yet)
<software name="music1">
<description>Music Island Vol. 1 (Prokofiev Peter &amp; the Wolf) (Jpn)</description>
<year>1996</year>
- <publisher>Oracion</publisher> <!-- オラシオン -->
+ <publisher>Oracion</publisher> <!-- オラシオン -->
<info name="serial" value="BDS-20007" />
<info name="alt_title" value="MUSIC ISLAND プロコフィエフ ピーターと狼 PETER AND THE WOLF" />
<part name="cdrom" interface="pippin_cdrom">
@@ -574,7 +574,7 @@ NOTE: This list is here only to document available dumps and it's not used (yet)
<software name="music2">
<description>Music Island Vol. 2 (Tchaikovsky The Nutcracker) (Jpn)</description>
<year>1996</year>
- <publisher>Oracion</publisher> <!-- オラシオン -->
+ <publisher>Oracion</publisher> <!-- オラシオン -->
<info name="serial" value="BDS-20027" />
<info name="alt_title" value="MUSIC ISLAND チャイコフスキー くるみわり人形 The Nutcracker" />
<part name="cdrom" interface="pippin_cdrom">
@@ -587,7 +587,7 @@ NOTE: This list is here only to document available dumps and it's not used (yet)
<software name="music3">
<description>Music Island Vol. 3 (Vivaldi The Four Seasons) (Jpn)</description>
<year>1996</year>
- <publisher>Oracion</publisher> <!-- オラシオン -->
+ <publisher>Oracion</publisher> <!-- オラシオン -->
<info name="serial" value="BDS-20028" />
<info name="alt_title" value="MUSIC ISLAND ヴィヴァルディ 四季 The Four Seasons" />
<part name="cdrom" interface="pippin_cdrom">
@@ -600,7 +600,7 @@ NOTE: This list is here only to document available dumps and it's not used (yet)
<software name="music4">
<description>Music Island Vol. 4 (Saint-Saens Carnival of the Animals) (Jpn)</description>
<year>1996</year>
- <publisher>Oracion</publisher> <!-- オラシオン -->
+ <publisher>Oracion</publisher> <!-- オラシオン -->
<info name="serial" value="BDS-20029" />
<info name="alt_title" value="MUSIC ISLAND サン=サーンス 動物の謝肉祭 Carnival of the Animals" />
<part name="cdrom" interface="pippin_cdrom">
@@ -613,7 +613,7 @@ NOTE: This list is here only to document available dumps and it's not used (yet)
<software name="nemuyoru">
<description>Nemurenu Yoru no Chiisana Ohanashi (Jpn)</description>
<year>1996</year>
- <publisher>Amuse</publisher> <!-- アミューズ -->
+ <publisher>Amuse</publisher> <!-- アミューズ -->
<info name="serial" value="BDS-20015" />
<info name="alt_title" value="眠れぬ夜の小さなお話" />
<part name="cdrom" interface="pippin_cdrom">
@@ -809,7 +809,7 @@ NOTE: This list is here only to document available dumps and it's not used (yet)
<software name="seesawc1">
<description>SeesawC 1 - My favorite things - Sukinamonodake Eitango 120 (Jpn)</description>
<year>1996</year>
- <publisher>Aigaareba Daijoubu</publisher> <!-- 愛があれば大丈夫 -->
+ <publisher>Aigaareba Daijoubu</publisher> <!-- 愛があれば大丈夫 -->
<info name="serial" value="BDE-10006" />
<info name="alt_title" value="シーソーシー1" />
<part name="cdrom" interface="pippin_cdrom">
@@ -822,7 +822,7 @@ NOTE: This list is here only to document available dumps and it's not used (yet)
<software name="seesawc2">
<description>SeesawC 2 - My favorite places - Sukinatokorode Eitango 400 (Jpn)</description>
<year>1996</year>
- <publisher>Aigaareba Daijoubu</publisher> <!-- 愛があれば大丈夫 -->
+ <publisher>Aigaareba Daijoubu</publisher> <!-- 愛があれば大丈夫 -->
<info name="serial" value="BDE-10023" />
<info name="alt_title" value="シーソーシー2" />
<part name="cdrom" interface="pippin_cdrom">
@@ -835,7 +835,7 @@ NOTE: This list is here only to document available dumps and it's not used (yet)
<software name="shichiso">
<description>Shichisokusen (Jpn)</description>
<year>1996</year>
- <publisher>Media Five</publisher> <!-- メディアファイブ -->
+ <publisher>Media Five</publisher> <!-- メディアファイブ -->
<info name="serial" value="BDS-20019" />
<info name="alt_title" value="死地則戦 ビジネスエデュテイメントソフト" />
<part name="cdrom" interface="pippin_cdrom">
@@ -885,7 +885,7 @@ NOTE: This list is here only to document available dumps and it's not used (yet)
<software name="tbreak">
<description>T-Break (Jpn)</description>
<year>1996</year>
- <publisher>Infocity</publisher> <!-- インフォシティ -->
+ <publisher>Infocity</publisher> <!-- インフォシティ -->
<info name="serial" value="BDS-20026" />
<info name="alt_title" value="ティ・ブレイク" />
<part name="cdrom" interface="pippin_cdrom">
@@ -912,7 +912,7 @@ NOTE: This list is here only to document available dumps and it's not used (yet)
<software name="tropicis">
<description>Tropic Island (Jpn)</description>
<year>1996</year>
- <publisher>Momoderazu Brand</publisher> <!-- モモデラーズブランド -->
+ <publisher>Momoderazu Brand</publisher> <!-- モモデラーズブランド -->
<info name="serial" value="BDS-20011" />
<info name="alt_title" value="トロピック アイランド" />
<part name="cdrom" interface="pippin_cdrom">
@@ -1069,7 +1069,7 @@ NOTE: This list is here only to document available dumps and it's not used (yet)
<software name="yellow1">
<description>Yellow Brick Road I (Jpn)</description>
<year>1996</year>
- <publisher>Synergy Ikunangaku</publisher> <!-- シナジー幾何学 -->
+ <publisher>Synergy Ikunangaku</publisher> <!-- シナジー幾何学 -->
<info name="serial" value="BDS-20022" />
<info name="alt_title" value="イエロー・ブリック・ロード I" />
<part name="cdrom" interface="pippin_cdrom">
@@ -1082,7 +1082,7 @@ NOTE: This list is here only to document available dumps and it's not used (yet)
<software name="yellow2">
<description>Yellow Brick Road II - Glinda to Nishi no Majo (Jpn)</description>
<year>1996</year>
- <publisher>Synergy Ikunangaku</publisher> <!-- シナジー幾何学 -->
+ <publisher>Synergy Ikunangaku</publisher> <!-- シナジー幾何学 -->
<info name="serial" value="BDS-20023" />
<info name="alt_title" value="イエロー・ブリック・ロード II グリンダと西の魔女" />
<part name="cdrom1" interface="scd_cdrom">
@@ -1102,7 +1102,7 @@ NOTE: This list is here only to document available dumps and it's not used (yet)
<software name="yellows">
<description>Yellows - Akira Gomi Photographs (Jpn)</description>
<year>1996</year>
- <publisher>Digitalogue</publisher> <!-- デジタローグ -->
+ <publisher>Digitalogue</publisher> <!-- デジタローグ -->
<info name="serial" value="BDS-20001" />
<part name="cdrom" interface="pippin_cdrom">
<diskarea name="cdrom">
@@ -1114,7 +1114,7 @@ NOTE: This list is here only to document available dumps and it's not used (yet)
<software name="yellws2">
<description>Yellows 2.0 - Tokyo 1993 Akira Gomi Photographs (Jpn)</description>
<year>1996</year>
- <publisher>Digitalogue</publisher> <!-- デジタローグ -->
+ <publisher>Digitalogue</publisher> <!-- デジタローグ -->
<info name="serial" value="BDS-20002" />
<info name="alt_title" value="イエローズ 2.0" />
<part name="cdrom" interface="pippin_cdrom">
@@ -1127,7 +1127,7 @@ NOTE: This list is here only to document available dumps and it's not used (yet)
<software name="yokumite">
<description>Yoku Mite Goran! (Jpn)</description>
<year>1996</year>
- <publisher>Voyager</publisher> <!-- ボイジャー -->
+ <publisher>Voyager</publisher> <!-- ボイジャー -->
<info name="serial" value="BDS-20018" />
<info name="alt_title" value="よく見てごらん!美術館へ行こう" />
<part name="cdrom" interface="pippin_cdrom">
diff --git a/hash/pofo.xml b/hash/pofo.xml
index 3255a1aaaba..e12a0b04cdc 100644
--- a/hash/pofo.xml
+++ b/hash/pofo.xml
@@ -21,8 +21,8 @@
Undumped 3rd party cartridges:
- Adcalc AAC-1000
- Alpha Paging Interface SAMpage
+ Adcalc AAC-1000
+ Alpha Paging Interface SAMpage
Business Contacts and Information Manager BCIM
Checkwriter
Colossal Cave Adventure
diff --git a/hash/snes.xml b/hash/snes.xml
index 8f4b5efaafd..056e738dd60 100644
--- a/hash/snes.xml
+++ b/hash/snes.xml
@@ -1357,7 +1357,7 @@ Beyond that last category are the roms waiting to be classified.
<feature name="u1" value="U1 EPROM" />
<feature name="u2" value="U2 EPROM" />
<feature name="u3" value="U3 EPROM" />
- <feature name="u4" value="U4 EPROM" /> <!-- empty socket -->
+ <feature name="u4" value="U4 EPROM" /> <!-- empty socket -->
<feature name="u5" value="U5 SRAM" />
<feature name="u6" value="U6 PLD" />
<feature name="u7" value="U7 74LS157" />
@@ -34238,7 +34238,7 @@ List of unclassified roms
</dataarea>
</part>
</software>
-
+
<software name="arabianp" cloneof="arabian">
<description>Arabian Nights - Sabaku no Seirei Ou (Jpn, Prototype)</description>
<year>1996</year>
@@ -37664,7 +37664,7 @@ List of unclassified roms
</dataarea>
</part>
</software>
-
+
<software name="downwrldd" cloneof="downwrld">
<description>Down the World - Mervil's Ambition (Jpn, Rolling Demo)</description>
<year>1994</year>
@@ -40283,7 +40283,7 @@ List of unclassified roms
</dataarea>
</part>
</software>
-
+
<software name="ganpurup" cloneof="ganpuru">
<description>Ganpuru - Gunman's Proof (Jpn, Prototype)</description>
<year>1997</year>
@@ -61015,7 +61015,7 @@ to ensure nothing has been touched in the Retro Quest cart production in 2013/20
</dataarea>
</part>
</software>
-
+
<software name="tougedenp" cloneof="tougeden">
<description>Touge Densetsu - Saisoku Battle (Jpn, Prototype)</description>
<year>1996</year>
@@ -61911,7 +61911,7 @@ to ensure nothing has been touched in the Retro Quest cart production in 2013/20
</dataarea>
</part>
</software>
-
+
<software name="umizurimp" cloneof="umizurim">
<description>Umizuri Meijin - Suzuki Hen (Jpn, Prototype)</description>
<year>1994</year>
diff --git a/hash/vsmile_cart.xml b/hash/vsmile_cart.xml
index a5d13ac1ac3..fea4e6a5dda 100644
--- a/hash/vsmile_cart.xml
+++ b/hash/vsmile_cart.xml
@@ -901,7 +901,7 @@ V.Baby (NOT V.Smile Baby)
</dataarea>
</part>
</software>
-
+
<software name="cinderlaa" cloneof="cinderla" supported="no">
<description>Cinderella - Cinderella's Magic Wishes (USA, Alt)</description>
<year>200?</year>
@@ -912,7 +912,7 @@ V.Baby (NOT V.Smile Baby)
</dataarea>
</part>
</software>
-
+
<software name="cinderlaf" cloneof="cinderla" supported="no">
<description>Cendrillon - Le Rêve Enchanté de Cendrillon (Fra)</description>
<year>200?</year>
@@ -1056,7 +1056,7 @@ V.Baby (NOT V.Smile Baby)
</dataarea>
</part>
</software>
-
+
<software name="kleinstn" supported="no">
<description>Kleine Einsteins (Ger)</description>
<year>200?</year>
@@ -1122,7 +1122,7 @@ V.Baby (NOT V.Smile Baby)
</dataarea>
</part>
</software>
-
+
<software name="mickymag" supported="no">
<description>Disney's Mickey Mouse - Mickey's Magical Adventure (USA)</description>
<year>200?</year>
@@ -1342,7 +1342,7 @@ V.Baby (NOT V.Smile Baby)
</dataarea>
</part>
</software>
-
+
<software name="shrekf" cloneof="shrek" supported="no">
<description>Shrek - Le Rhume de Dragonne (Fra)</description>
<year>200?</year>
@@ -1463,7 +1463,7 @@ V.Baby (NOT V.Smile Baby)
</dataarea>
</part>
</software>
-
+
<software name="tingelng" supported="no">
<description>Tingeling (Swe)</description>
<year>200?</year>
@@ -1474,7 +1474,7 @@ V.Baby (NOT V.Smile Baby)
</dataarea>
</part>
</software>
-
+
<software name="toystor2" supported="no">
<description>Toy Story 2 - Operation: Rescue Woody! (USA)</description>
<year>2005</year>
@@ -1540,7 +1540,7 @@ V.Baby (NOT V.Smile Baby)
</dataarea>
</part>
</software>
-
+
<software name="pooh1" cloneof="pooh" supported="no">
<description>My Friends Tigger &amp; Pooh - Die Honigjagd (Ger)</description>
<year>200?</year>
@@ -1617,7 +1617,7 @@ V.Baby (NOT V.Smile Baby)
</dataarea>
</part>
</software>
-
+
<software name="zayzoo" supported="no">
<description>Zayzoo - My Alien Classmate (USA)</description>
<year>200?</year>
@@ -1665,7 +1665,7 @@ V.Baby (NOT V.Smile Baby)
</dataarea>
</part>
</software>
-
+
<software name="poohhawa" supported="no">
<description>Pooh's Hundred Acre Wood Adventure (USA) (V.Smile Baby)</description>
<year>2007</year>
@@ -1713,7 +1713,7 @@ V.Baby (NOT V.Smile Baby)
</dataarea>
</part>
</software>
-
+
<software name="kleinsvm" supported="no">
<description>Kleine Einsteins (Ger) (V.Smile Motion)</description>
<year>200?</year>
diff --git a/hash/vsmile_cd.xml b/hash/vsmile_cd.xml
index e079d2b8543..adc7d683f47 100644
--- a/hash/vsmile_cd.xml
+++ b/hash/vsmile_cd.xml
@@ -117,7 +117,7 @@ Language:
</diskarea>
</part>
</software>
-
+
<software name="bratz" supported="no">
<!--
Original files:
@@ -135,7 +135,7 @@ Language:
</diskarea>
</part>
</software>
-
+
<software name="cars" supported="no">
<!--
Original files:
@@ -153,7 +153,7 @@ Language:
</diskarea>
</part>
</software>
-
+
<software name="carsg" cloneof="cars" supported="no">
<!--
Original files (from TeamEurope)
@@ -170,7 +170,7 @@ Language:
</diskarea>
</part>
</software>
-
+
<software name="princess" supported="no">
<!--
Original files:
@@ -188,7 +188,7 @@ Language:
</diskarea>
</part>
</software>
-
+
<software name="princessg" cloneof="princess" supported="no">
<!--
Original files (from TeamEurope)
@@ -225,7 +225,7 @@ Language:
</diskarea>
</part>
</software>
-
+
<software name="incredibg" cloneof="incredib" supported="no">
<!--
Original files (from TeamEurope)
@@ -242,7 +242,7 @@ Language:
</diskarea>
</part>
</software>
-
+
<software name="msportg" supported="no">
<!--
Original files (from TeamEurope)
@@ -279,7 +279,7 @@ Language:
</diskarea>
</part>
</software>
-
+
<software name="shrek3" supported="no">
<!--
Original files:
@@ -297,7 +297,7 @@ Language:
</diskarea>
</part>
</software>
-
+
<software name="shrek3g" cloneof="shrek3" supported="no">
<!--
Original files (from TeamEurope)
@@ -314,7 +314,7 @@ Language:
</diskarea>
</part>
</software>
-
+
<software name="spongeis" supported="no">
<!--
Original files:
@@ -349,7 +349,7 @@ Language:
</diskarea>
</part>
</software>
-
+
<!-- disk mounted as 93120_003 -->
<software name="wackyrac" supported="no">
<!--
diff --git a/makefile b/makefile
index ecb7995e7fa..d3c8c1d6a17 100644
--- a/makefile
+++ b/makefile
@@ -1486,14 +1486,14 @@ endif
ifeq (posix,$(SHELLTYPE))
$(GENDIR)/version.cpp: $(GENDIR)/git_desc | $(GEN_FOLDERS)
- @echo '#define BARE_BUILD_VERSION "0.174"' > $@
+ @echo '#define BARE_BUILD_VERSION "0.175"' > $@
@echo 'extern const char bare_build_version[];' >> $@
@echo 'extern const char build_version[];' >> $@
@echo 'const char bare_build_version[] = BARE_BUILD_VERSION;' >> $@
@echo 'const char build_version[] = BARE_BUILD_VERSION " ($(NEW_GIT_VERSION))";' >> $@
else
$(GENDIR)/version.cpp: $(GENDIR)/git_desc
- @echo #define BARE_BUILD_VERSION "0.174" > $@
+ @echo #define BARE_BUILD_VERSION "0.175" > $@
@echo extern const char bare_build_version[]; >> $@
@echo extern const char build_version[]; >> $@
@echo const char bare_build_version[] = BARE_BUILD_VERSION; >> $@
diff --git a/src/devices/bus/electron/exp.cpp b/src/devices/bus/electron/exp.cpp
index b13f6534002..ced8056d2eb 100644
--- a/src/devices/bus/electron/exp.cpp
+++ b/src/devices/bus/electron/exp.cpp
@@ -2,7 +2,7 @@
// copyright-holders:Nigel Barnes
/**********************************************************************
- Electron Expansion Port emulation
+ Electron Expansion Port emulation
**********************************************************************/
diff --git a/src/devices/bus/electron/exp.h b/src/devices/bus/electron/exp.h
index cfcb7478a10..2f59faec38a 100644
--- a/src/devices/bus/electron/exp.h
+++ b/src/devices/bus/electron/exp.h
@@ -2,84 +2,84 @@
// copyright-holders:Nigel Barnes
/**********************************************************************
- Electron Expansion Port emulation
+ Electron Expansion Port emulation
**********************************************************************
- Pinout:
-
- 18V AC 2 1 18V AC
- AC RETURN 4 3 AC RETURN
- -5V 6 5 -5V
- 0V 8 7 0V
- +5V 10 9 +5V
- 16MHz 12 11 SOUND O/P
- PHI OUT 14 13 13 IN
- NMI 16 15 RST
- R/W 18 17 IRQ
- D6 20 19 D7
- D4 22 21 D5
- D2 24 23 D3
- D0 26 25 D1
- NC 28 27 RDY
- SLOT 30 29 SLOT
- A14 32 31 A15
- A12 34 33 A13
- A10 36 35 A11
- A0 38 37 A9
- A2 40 39 A1
- A4 42 41 A3
- A6 44 43 A5
- A8 46 45 A7
- 0V 48 47 0V
- +5V 50 49 +5V
-
- Signal Definitions:
-
- 18V AC (pins 1,2) - These lines are connected directly to the output from the Electron mains power
+ Pinout:
+
+ 18V AC 2 1 18V AC
+ AC RETURN 4 3 AC RETURN
+ -5V 6 5 -5V
+ 0V 8 7 0V
+ +5V 10 9 +5V
+ 16MHz 12 11 SOUND O/P
+ PHI OUT 14 13 13 IN
+ NMI 16 15 RST
+ R/W 18 17 IRQ
+ D6 20 19 D7
+ D4 22 21 D5
+ D2 24 23 D3
+ D0 26 25 D1
+ NC 28 27 RDY
+ SLOT 30 29 SLOT
+ A14 32 31 A15
+ A12 34 33 A13
+ A10 36 35 A11
+ A0 38 37 A9
+ A2 40 39 A1
+ A4 42 41 A3
+ A6 44 43 A5
+ A8 46 45 A7
+ 0V 48 47 0V
+ +5V 50 49 +5V
+
+ Signal Definitions:
+
+ 18V AC (pins 1,2) - These lines are connected directly to the output from the Electron mains power
AC RETURNS (pins 3,4) - adaptor. A total of 6W may be drawn from these lines as long as no power is
- taken from +5V (pins 9,10,49,50). For safety reasons these lines must never
- be used as an AC input to the Electron.
- -5V (pins 5,6) - A -5V supply from the Electron. Up to 20mA (total) may safely be drawn
- from this line by expansion modules.
- 0V (pins 7,8,47,48) - Ground. Expansion modules with their own power supply must have the 0V
- lines commoned with the Electron.
+ taken from +5V (pins 9,10,49,50). For safety reasons these lines must never
+ be used as an AC input to the Electron.
+ -5V (pins 5,6) - A -5V supply from the Electron. Up to 20mA (total) may safely be drawn
+ from this line by expansion modules.
+ 0V (pins 7,8,47,48) - Ground. Expansion modules with their own power supply must have the 0V
+ lines commoned with the Electron.
+5V (pins 9,10,49,50) - A +5V supply from the Electron. Up to 500mA (total) may safely be drawn
- from this line by expansion modules as long as no power is taken from 18V
- AC (pins 1,2,3,4).
- SOUND O/P (pin 11) - Sound output. A 3V peak to peak source via a 1K series resistor from the
- Electron ULA.
- 16 MHz (pin 12) - 16 Megahertz from the Electron main oscillator. This output may be used
- for clock generation within an expansion module.
- /13 IN (pin 13) - 16 Megahertz divided by 13. This output may be used for baud rate
- generation. If divided by 1024 it will give approximately 1200Hz.
- PHI OUT (pin 14) - The 6502 input clock. The low time is nominally 250ns. The high time may
- be 250ns (2MHz operation when reading ROMs) or 750ns or 1250ns
- (stretched clock for a 1MHz access, the length depending on the phase of the
- 2MHz clock) or up to 40us (if in modes 0-3)
- RST (pin 15) - Reset (active low). This is an OUTPUT ONLY for the system reset line. It
- may be used to initialise expansion modules on power up and when the
- BREAK key is pressed.
- NMI (pin 16) - Non-Maskable Interrupt (negative edge triggered). This is the system NMI
- line which is open collector (wire-OR) and may be asserted by an expansion
- module. The pull-up resistor on this line inside the ULA is 3k3. Care must
- be taken to avoid masking other interrupts by holding the line low. Using
- NMI on the Electron requires knowledge of operating system protocols.
- IRQ (pin 17) - Interrupt Request (active low). This is the system IRQ line which is open
- collector (wire-OR) and may be asserted by an expansion module. The pull-
- up resistor on this line inside the ULA is 3k3. It is essential for the correct
- operation of the machine that interrupts to not occur until the software is
- capable of dealing with them. Interrupts on the Electron expansion bus should
- therefore be disabled on power-up and reset. Significant use of interrupt
- service time may affect other machine functions, eg the real time clock.
- R/W (pin 18) - The system read/write line from the 6502.
- D7-D0 (pins 19-26) - Bi-directional data bus. The direction of data is determined by R/W.
- RDY (pin 27) - 6502 ready line (active low). May be asserted by an expansion module to
- stop the processor when reading slow memory. This line works on read only
- (R/W=1).
- (pin 28) - No connection
- (pins 29,30) - Polarising key connector.
- A0-A15 (pins 31-46) - 6502 address bus.
+ from this line by expansion modules as long as no power is taken from 18V
+ AC (pins 1,2,3,4).
+ SOUND O/P (pin 11) - Sound output. A 3V peak to peak source via a 1K series resistor from the
+ Electron ULA.
+ 16 MHz (pin 12) - 16 Megahertz from the Electron main oscillator. This output may be used
+ for clock generation within an expansion module.
+ /13 IN (pin 13) - 16 Megahertz divided by 13. This output may be used for baud rate
+ generation. If divided by 1024 it will give approximately 1200Hz.
+ PHI OUT (pin 14) - The 6502 input clock. The low time is nominally 250ns. The high time may
+ be 250ns (2MHz operation when reading ROMs) or 750ns or 1250ns
+ (stretched clock for a 1MHz access, the length depending on the phase of the
+ 2MHz clock) or up to 40us (if in modes 0-3)
+ RST (pin 15) - Reset (active low). This is an OUTPUT ONLY for the system reset line. It
+ may be used to initialise expansion modules on power up and when the
+ BREAK key is pressed.
+ NMI (pin 16) - Non-Maskable Interrupt (negative edge triggered). This is the system NMI
+ line which is open collector (wire-OR) and may be asserted by an expansion
+ module. The pull-up resistor on this line inside the ULA is 3k3. Care must
+ be taken to avoid masking other interrupts by holding the line low. Using
+ NMI on the Electron requires knowledge of operating system protocols.
+ IRQ (pin 17) - Interrupt Request (active low). This is the system IRQ line which is open
+ collector (wire-OR) and may be asserted by an expansion module. The pull-
+ up resistor on this line inside the ULA is 3k3. It is essential for the correct
+ operation of the machine that interrupts to not occur until the software is
+ capable of dealing with them. Interrupts on the Electron expansion bus should
+ therefore be disabled on power-up and reset. Significant use of interrupt
+ service time may affect other machine functions, eg the real time clock.
+ R/W (pin 18) - The system read/write line from the 6502.
+ D7-D0 (pins 19-26) - Bi-directional data bus. The direction of data is determined by R/W.
+ RDY (pin 27) - 6502 ready line (active low). May be asserted by an expansion module to
+ stop the processor when reading slow memory. This line works on read only
+ (R/W=1).
+ (pin 28) - No connection
+ (pins 29,30) - Polarising key connector.
+ A0-A15 (pins 31-46) - 6502 address bus.
**********************************************************************/
diff --git a/src/devices/bus/gameboy/mbc.cpp b/src/devices/bus/gameboy/mbc.cpp
index 3192bcda9ce..cf5a6f44a98 100644
--- a/src/devices/bus/gameboy/mbc.cpp
+++ b/src/devices/bus/gameboy/mbc.cpp
@@ -452,7 +452,7 @@ void gb_rom_mbc3_device::update_rtc()
{
system_time curtime;
machine().current_datetime(curtime);
-
+
m_rtc_regs[0] = curtime.local_time.second;
m_rtc_regs[1] = curtime.local_time.minute;
m_rtc_regs[2] = curtime.local_time.hour;
@@ -700,7 +700,7 @@ WRITE8_MEMBER(gb_rom_m161_device::write_bank)
{
// the mapper (74HC161A) only has data lines D2..D0
data &= 0x07;
-
+
// A15 is connected to #LOAD and overwritten by QD (m_load_disable)
switch (offset & 0x8000)
{
@@ -719,31 +719,30 @@ WRITE8_MEMBER(gb_rom_m161_device::write_bank)
READ8_MEMBER(gb_rom_mmm01_device::read_rom)
{
-
UINT16 romb = m_romb & ~m_romb_nwe;
UINT16 romb_base = m_romb & (0x1e0 | m_romb_nwe);
UINT8 ramb_masked = ((offset & 0x4000) | m_mode ? m_ramb : m_ramb & ~0x03);
-
+
// zero-adjust RA18..RA14
romb = (romb ? romb : 0x01);
// if unmapped, force
romb = (m_map ? romb : 0x01);
-
+
// RB 0 logic
if (!(offset & 0x4000))
romb = 0x00;
-
+
// combine with base
romb |= romb_base;
-
+
// multiplex with AA14..AA13
if (m_mux)
romb = (romb & ~0x60) | ((ramb_masked & 0x03) << 5);
-
+
// if unmapped, force
if (!m_map)
romb |= 0x1fe;
-
+
return m_rom[rom_bank_map[romb] * 0x4000 + (offset & 0x3fff)];
}
@@ -751,7 +750,7 @@ WRITE8_MEMBER(gb_rom_mmm01_device::write_bank)
{
// the mapper only has data lines D6..D0
data &= 0x7f;
-
+
// the mapper only uses inputs A15..A13
switch (offset & 0xe000)
{
@@ -765,7 +764,7 @@ WRITE8_MEMBER(gb_rom_mmm01_device::write_bank)
case 0x2000: // RA20..RA19 RA18..RA14
if (!m_map)
m_romb = (m_romb & ~0x60) | (data & 0x60);
-
+
m_romb = (m_romb & (~0x1f | m_romb_nwe)) | (data & (0x1f & ~m_romb_nwe));
break;
case 0x4000: // Mode #WE, RA22..RA21, AA16..AA15, AA14..AA13
@@ -774,7 +773,7 @@ WRITE8_MEMBER(gb_rom_mmm01_device::write_bank)
m_romb = (m_romb & ~0x180) | ((data & 0x30) << 3);
m_ramb = (m_ramb & ~0x0c) | (data & 0x0c);
}
-
+
m_ramb = (m_ramb & (~0x03 | m_ramb_nwe)) | (data & (0x03 & ~m_ramb_nwe));
break;
case 0x6000: // Mux, RA18..RA15 #WE/Mask, ???, MBC1 Mode
@@ -783,7 +782,7 @@ WRITE8_MEMBER(gb_rom_mmm01_device::write_bank)
// m_romb_nwe is aligned to RA14, hence >> 1 instead of >> 2
m_romb_nwe = (data & 0x3c) >> 1;
}
-
+
if (!m_mode_nwe)
m_mode = data & 0x01;
break;
@@ -796,11 +795,11 @@ READ8_MEMBER(gb_rom_mmm01_device::read_ram)
{
UINT8 ramb_masked = ((offset & 0x4000) | m_mode ? m_ramb : m_ramb & ~0x03);
UINT8 ramb = ramb_masked;
-
+
// multiplex with RA20..RA19
if (m_mux)
ramb = (ramb & ~0x03) | ((m_romb & 0x60) >> 5);
-
+
if (!m_ram.empty() && m_ram_enable)
{
return m_ram[ram_bank_map[ramb] * 0x2000 + (offset & 0x1fff)];
@@ -813,11 +812,11 @@ WRITE8_MEMBER(gb_rom_mmm01_device::write_ram)
{
UINT8 ramb_masked = ((offset & 0x4000) | m_mode ? m_ramb : m_ramb & ~0x03);
UINT8 ramb = ramb_masked;
-
+
// multiplex with RA20..RA19
if (m_mux)
ramb = (ramb & ~0x03) | ((m_romb & 0x60) >> 5);
-
+
if (!m_ram.empty() && m_ram_enable)
{
m_ram[ram_bank_map[ramb] * 0x2000 + (offset & 0x1fff)] = data;
diff --git a/src/devices/bus/gameboy/mbc.h b/src/devices/bus/gameboy/mbc.h
index 1dcc43875bd..827d42c392d 100644
--- a/src/devices/bus/gameboy/mbc.h
+++ b/src/devices/bus/gameboy/mbc.h
@@ -195,7 +195,7 @@ public:
virtual DECLARE_WRITE8_MEMBER(write_bank) override;
virtual DECLARE_READ8_MEMBER(read_ram) override;
virtual DECLARE_WRITE8_MEMBER(write_ram) override;
-
+
UINT16 m_romb;
UINT8 m_romb_nwe;
UINT8 m_ramb;
diff --git a/src/devices/bus/gba/gba_slot.h b/src/devices/bus/gba/gba_slot.h
index 03b9ca4f653..62c25bc6674 100644
--- a/src/devices/bus/gba/gba_slot.h
+++ b/src/devices/bus/gba/gba_slot.h
@@ -607,7 +607,7 @@ static const gba_chip_fix_item gba_chip_fix_rumble_list[] =
{ "KYGP" }, // Yoshi's Universal Gravitation (EUR)
{ "KYGE" }, // Yoshi - Topsy-Turvy (USA)
{ "KYGJ" }, // Yoshi no Banyuuinryoku (JPN)
- { "KHPJ" } // Koro Koro Puzzle - Happy Panechu! (JPN)
+ { "KHPJ" } // Koro Koro Puzzle - Happy Panechu! (JPN)
};
diff --git a/src/devices/bus/gba/rom.cpp b/src/devices/bus/gba/rom.cpp
index 5fc4798f1d7..4f10bbb0733 100644
--- a/src/devices/bus/gba/rom.cpp
+++ b/src/devices/bus/gba/rom.cpp
@@ -268,7 +268,7 @@ void gba_rom_3dmatrix_device::device_reset()
This is a preliminary implementation of the
General Purpose I/O Port embedded in the GBA PCBs
as described at : http://problemkaputt.de/gbatek.htm#gbacartioportgpio
-
+
Functions read_gpio/write_gpio only give the
I/O interface while the actual on-cart devices
are read and written through gpio_dev_read/gpio_dev_write
@@ -400,7 +400,7 @@ void gba_rom_wariotws_device::gpio_dev_write(UINT16 data, int gpio_dirs)
if (data & 1)
m_counter = 15;
-
+
m_last_val = data & 0x0b;
}
}
@@ -586,19 +586,19 @@ WRITE32_MEMBER(gba_rom_eeprom64_device::write_ram)
/*-------------------------------------------------
Carts with EEPROM + Tilt Sensor
-
- Note about the calibration: this can seem a bit
+
+ Note about the calibration: this can seem a bit
tricky at first, because the emulated screen
does not turn as the GBA would...
In order to properly calibrate the sensor, just
keep pressed right for a few seconds when requested
- to calibrate right inclination (first calibration
- screen in Yoshi Universal Gravitation) so to get the
- full right range; then keep pressed for left for a
+ to calibrate right inclination (first calibration
+ screen in Yoshi Universal Gravitation) so to get the
+ full right range; then keep pressed for left for a
few seconds when requested to calibrate left
- inclination (second calibration screen in Yoshi
+ inclination (second calibration screen in Yoshi
Universal Gravitation) so to get the full left range
-
+
-------------------------------------------------*/
static INPUT_PORTS_START( yoshiug_tilt )
@@ -700,14 +700,14 @@ void gba_rom_boktai_device::gpio_dev_write(UINT16 data, int gpio_dirs)
{
if (data & 2)
m_counter = 0;
-
+
if ((data & 1) && !(m_last_val & 1))
{
m_counter++;
if (m_counter == 0x100)
m_counter = 0;
}
-
+
m_last_val = data & 7;
}
}
@@ -775,7 +775,7 @@ WRITE32_MEMBER(gba_rom_3dmatrix_device::write_mapper)
/*-------------------------------------------------
Seiko S-3511 RTC implementation
-
+
TODO: transform this into a separate device, using
also dirtc.cpp!
-------------------------------------------------*/
@@ -789,7 +789,7 @@ gba_s3511_device::gba_s3511_device(running_machine &machine) :
m_command = 0;
m_data_len = 1;
m_data[0] = 0;
-
+
m_machine.save().save_item(m_phase, "GBA_RTC/m_phase");
m_machine.save().save_item(m_data, "GBA_RTC/m_data");
m_machine.save().save_item(m_last_val, "GBA_RTC/m_last_val");
@@ -808,7 +808,7 @@ void gba_s3511_device::update_time(int len)
{
system_time curtime;
m_machine.current_datetime(curtime);
-
+
if (len == 7)
{
m_data[0] = convert_to_bcd(curtime.local_time.year);
@@ -840,7 +840,7 @@ int gba_s3511_device::read_line()
if (m_bits == 8 * m_data_len)
{
//for (int i = 0; i < m_data_len; i++)
- // printf("RTC DATA OUT COMPLETE %X (reg %d) \n", m_data[i], i);
+ // printf("RTC DATA OUT COMPLETE %X (reg %d) \n", m_data[i], i);
m_bits = 0;
m_phase = S3511_RTC_IDLE;
}
@@ -852,7 +852,7 @@ int gba_s3511_device::read_line()
void gba_s3511_device::write(UINT16 data, int gpio_dirs)
{
-// printf("gpio_dev_write data %X\n", data);
+// printf("gpio_dev_write data %X\n", data);
if (m_phase == S3511_RTC_IDLE && (m_last_val & 5) == 1 && (data & 5) == 5)
{
m_phase = S3511_RTC_COMMAND;
@@ -861,8 +861,8 @@ void gba_s3511_device::write(UINT16 data, int gpio_dirs)
}
else
{
-// if (m_phase == 3)
-// printf("RTC command OK\n");
+// if (m_phase == 3)
+// printf("RTC command OK\n");
if (!(m_last_val & 1) && (data & 1))
{
// bit transfer
@@ -877,7 +877,7 @@ void gba_s3511_device::write(UINT16 data, int gpio_dirs)
if (m_bits == 8 * m_data_len)
{
//for (int i = 0; i < m_data_len; i++)
- // printf("RTC DATA IN COMPLETE %X (reg %d) \n", m_data[i], i);
+ // printf("RTC DATA IN COMPLETE %X (reg %d) \n", m_data[i], i);
m_bits = 0;
m_phase = S3511_RTC_IDLE;
}
@@ -940,7 +940,7 @@ void gba_s3511_device::write(UINT16 data, int gpio_dirs)
/*-------------------------------------------------
GBA EEPROM Device
-
+
TODO: can this sketchy EEPROM device be merged
with the core implementation?
-------------------------------------------------*/
@@ -954,7 +954,7 @@ gba_eeprom_device::gba_eeprom_device(running_machine &machine, UINT8 *eeprom, UI
m_data = eeprom;
m_data_size = size;
m_addr_bits = addr_bits;
-
+
m_machine.save().save_item(m_state, "GBA_EEPROM/m_state");
m_machine.save().save_item(m_command, "GBA_EEPROM/m_command");
m_machine.save().save_item(m_count, "GBA_EEPROM/m_count");
@@ -966,16 +966,16 @@ gba_eeprom_device::gba_eeprom_device(running_machine &machine, UINT8 *eeprom, UI
UINT32 gba_eeprom_device::read()
{
UINT32 out;
-
+
switch (m_state)
{
case EEP_IDLE:
// printf("eeprom_r: @ %x, mask %08x (state %d) (PC=%x) = %d\n", offset, ~mem_mask, m_state, activecpu_get_pc(), 1);
return 0x00010001; // "ready"
-
+
case EEP_READFIRST:
m_count--;
-
+
if (!m_count)
{
m_count = 64;
@@ -996,19 +996,19 @@ UINT32 gba_eeprom_device::read()
m_addr++;
m_bits = 8;
}
-
+
out = (m_eep_data & 0x80) ? 1 : 0;
out |= (out<<16);
m_eep_data <<= 1;
-
+
m_bits--;
m_count--;
-
+
if (!m_count)
{
m_state = EEP_IDLE;
}
-
+
// printf("out = %08x\n", out);
// printf("eeprom_r: @ %x, mask %08x (state %d) (PC=%x) = %08x\n", offset, ~mem_mask, m_state, activecpu_get_pc(), out);
return out;
@@ -1026,7 +1026,7 @@ void gba_eeprom_device::write(UINT32 data)
if (data == 1)
m_state++;
break;
-
+
case EEP_COMMAND:
if (data == 1)
m_command = EEP_READFIRST;
@@ -1036,7 +1036,7 @@ void gba_eeprom_device::write(UINT32 data)
m_count = m_addr_bits;
m_addr = 0;
break;
-
+
case EEP_ADDR:
m_addr <<= 1;
m_addr |= (data & 1);
@@ -1055,7 +1055,7 @@ void gba_eeprom_device::write(UINT32 data)
}
}
break;
-
+
case EEP_AFTERADDR:
m_state = m_command;
m_count = 64;
@@ -1064,32 +1064,31 @@ void gba_eeprom_device::write(UINT32 data)
if (m_state == EEP_READFIRST)
m_count = 4;
break;
-
+
case EEP_WRITE:
m_eep_data <<= 1;
m_eep_data |= (data & 1);
m_bits--;
m_count--;
-
+
if (m_bits == 0)
{
osd_printf_verbose("%08x: EEPROM: %02x to %x\n", machine().device("maincpu")->safe_pc(), m_eep_data, m_addr);
if (m_addr >= m_data_size)
fatalerror("eeprom: invalid address (%x)\n", m_addr);
-
+
m_data[m_addr] = m_eep_data;
m_addr++;
m_eep_data = 0;
m_bits = 8;
}
-
+
if (!m_count)
m_state = EEP_AFTERWRITE;
break;
-
+
case EEP_AFTERWRITE:
m_state = EEP_IDLE;
break;
}
}
-
diff --git a/src/devices/bus/gba/rom.h b/src/devices/bus/gba/rom.h
index 4a1850c5fa2..13a69c44a65 100644
--- a/src/devices/bus/gba/rom.h
+++ b/src/devices/bus/gba/rom.h
@@ -20,19 +20,19 @@ class gba_s3511_device
public:
gba_s3511_device(running_machine &machine);
running_machine &machine() const { return m_machine; }
-
+
void update_time(int len);
UINT8 convert_to_bcd(int val);
-
+
int read_line();
void write(UINT16 data, int gpio_dirs);
-
+
protected:
int m_phase;
UINT8 m_last_val, m_bits, m_command;
int m_data_len;
UINT8 m_data[7];
-
+
running_machine& m_machine;
};
@@ -58,10 +58,10 @@ class gba_eeprom_device
public:
gba_eeprom_device(running_machine &machine, UINT8 *eeprom, UINT32 size, int addr_bits);
running_machine &machine() const { return m_machine; }
-
+
UINT32 read();
void write(UINT32 data);
-
+
protected:
UINT8 *m_data;
UINT32 m_data_size;
@@ -72,7 +72,7 @@ protected:
int m_bits;
int m_addr_bits;
UINT8 m_eep_data;
-
+
running_machine& m_machine;
};
@@ -97,7 +97,7 @@ public:
virtual DECLARE_READ32_MEMBER(read_gpio) override;
virtual DECLARE_WRITE32_MEMBER(write_gpio) override;
-
+
virtual UINT16 gpio_dev_read(int gpio_dirs) { return 0; }
virtual void gpio_dev_write(UINT16 data, int gpio_dirs) {}
@@ -129,7 +129,7 @@ class gba_rom_drilldoz_device : public gba_rom_sram_device
public:
// construction/destruction
gba_rom_drilldoz_device(const machine_config &mconfig, const char *tag, device_t *owner, UINT32 clock);
-
+
// device-level overrides
virtual void gpio_dev_write(UINT16 data, int gpio_dirs) override;
};
@@ -190,12 +190,12 @@ class gba_rom_flash_rtc_device : public gba_rom_flash_device
public:
// construction/destruction
gba_rom_flash_rtc_device(const machine_config &mconfig, const char *tag, device_t *owner, UINT32 clock);
-
+
// device-level overrides
virtual void device_start() override;
virtual UINT16 gpio_dev_read(int gpio_dirs) override;
virtual void gpio_dev_write(UINT16 data, int gpio_dirs) override;
-
+
private:
std::unique_ptr<gba_s3511_device> m_rtc;
};
@@ -232,7 +232,7 @@ class gba_rom_flash1m_rtc_device : public gba_rom_flash1m_device
public:
// construction/destruction
gba_rom_flash1m_rtc_device(const machine_config &mconfig, const char *tag, device_t *owner, UINT32 clock);
-
+
// device-level overrides
virtual void device_start() override;
virtual UINT16 gpio_dev_read(int gpio_dirs) override;
@@ -271,16 +271,16 @@ class gba_rom_yoshiug_device : public gba_rom_eeprom_device
public:
// construction/destruction
gba_rom_yoshiug_device(const machine_config &mconfig, const char *tag, device_t *owner, UINT32 clock);
-
+
// device-level overrides
virtual void device_start() override;
virtual void device_reset() override;
virtual ioport_constructor device_input_ports() const override;
-
+
// reading and writing
virtual DECLARE_READ32_MEMBER(read_tilt) override;
virtual DECLARE_WRITE32_MEMBER(write_tilt) override;
-
+
private:
int m_tilt_ready;
UINT16 m_xpos, m_ypos;
@@ -317,7 +317,7 @@ class gba_rom_boktai_device : public gba_rom_eeprom64_device
public:
// construction/destruction
gba_rom_boktai_device(const machine_config &mconfig, const char *tag, device_t *owner, UINT32 clock);
-
+
// device-level overrides
virtual void device_start() override;
virtual void device_reset() override;
@@ -325,7 +325,7 @@ public:
virtual UINT16 gpio_dev_read(int gpio_dirs) override;
virtual void gpio_dev_write(UINT16 data, int gpio_dirs) override;
-
+
private:
std::unique_ptr<gba_s3511_device> m_rtc;
required_ioport m_sensor;
diff --git a/src/devices/bus/isa/cga.cpp b/src/devices/bus/isa/cga.cpp
index 2dc3a5cd300..71e924dab84 100644
--- a/src/devices/bus/isa/cga.cpp
+++ b/src/devices/bus/isa/cga.cpp
@@ -1814,12 +1814,12 @@ WRITE8_MEMBER( isa8_ec1841_0002_device::io_write )
m_p3df = data;
if (data & 1) {
m_isa->install_memory(0xb8000, 0xb9fff,
- read8_delegate( FUNC(isa8_ec1841_0002_device::char_ram_read), this),
- write8_delegate(FUNC(isa8_ec1841_0002_device::char_ram_write), this) );
+ read8_delegate( FUNC(isa8_ec1841_0002_device::char_ram_read), this),
+ write8_delegate(FUNC(isa8_ec1841_0002_device::char_ram_write), this) );
if(m_vram_size == 0x4000)
m_isa->install_memory(0xbc000, 0xbdfff,
- read8_delegate( FUNC(isa8_ec1841_0002_device::char_ram_read), this),
- write8_delegate(FUNC(isa8_ec1841_0002_device::char_ram_write), this) );
+ read8_delegate( FUNC(isa8_ec1841_0002_device::char_ram_read), this),
+ write8_delegate(FUNC(isa8_ec1841_0002_device::char_ram_write), this) );
} else {
m_isa->install_bank(0xb8000, 0xb8000 + MIN(0x8000,m_vram_size) - 1, "bank_cga", &m_vram[0]);
if(m_vram_size == 0x4000)
diff --git a/src/devices/bus/macpds/macpds.h b/src/devices/bus/macpds/macpds.h
index 511355f6e42..9e42e47b3c1 100644
--- a/src/devices/bus/macpds/macpds.h
+++ b/src/devices/bus/macpds/macpds.h
@@ -83,7 +83,7 @@ public:
void add_macpds_card(device_macpds_card_interface *card);
void install_device(offs_t start, offs_t end, read8_delegate rhandler, write8_delegate whandler, UINT32 mask=0xffffffff);
void install_device(offs_t start, offs_t end, read16_delegate rhandler, write16_delegate whandler, UINT32 mask=0xffffffff);
- void install_bank(offs_t start, offs_t end, const char *tag, UINT8 *data);
+ void install_bank(offs_t start, offs_t end, const char *tag, UINT8 *data);
void set_irq_line(int line, int state);
protected:
diff --git a/src/devices/bus/megadrive/rom.cpp b/src/devices/bus/megadrive/rom.cpp
index ed17cfff044..039574487ca 100644
--- a/src/devices/bus/megadrive/rom.cpp
+++ b/src/devices/bus/megadrive/rom.cpp
@@ -930,7 +930,7 @@ READ16_MEMBER(md_rom_cjmjclub_device::read)
{
if (offset == 0x400000/2) return 0x9000;
if (offset == 0x400002/2) return 0xd300;
-
+
// non-protection accesses
if (offset < 0x400000/2)
return m_rom[MD_ADDR(offset)];
diff --git a/src/devices/bus/megadrive/rom.h b/src/devices/bus/megadrive/rom.h
index 3bafead4346..d640242ff3c 100644
--- a/src/devices/bus/megadrive/rom.h
+++ b/src/devices/bus/megadrive/rom.h
@@ -270,7 +270,7 @@ class md_rom_cjmjclub_device : public md_std_rom_device
public:
// construction/destruction
md_rom_cjmjclub_device(const machine_config &mconfig, const char *tag, device_t *owner, UINT32 clock);
-
+
// reading and writing
virtual DECLARE_READ16_MEMBER(read) override;
};
diff --git a/src/devices/bus/nes/bootleg.cpp b/src/devices/bus/nes/bootleg.cpp
index fbd00b7fadf..f21db4454ff 100644
--- a/src/devices/bus/nes/bootleg.cpp
+++ b/src/devices/bus/nes/bootleg.cpp
@@ -1238,7 +1238,7 @@ READ8_MEMBER(nes_lh32_device::read_m)
READ8_MEMBER(nes_lh32_device::read_h)
{
-// LOG_MMC(("lh32 read_h, offset: %04x\n", offset));
+// LOG_MMC(("lh32 read_h, offset: %04x\n", offset));
if (offset >= 0x4000 && offset < 0x6000)
return m_prgram[offset & 0x1fff];
@@ -1294,7 +1294,7 @@ READ8_MEMBER(nes_lh10_device::read_m)
READ8_MEMBER(nes_lh10_device::read_h)
{
-// LOG_MMC(("lh10 read_h, offset: %04x\n", offset));
+// LOG_MMC(("lh10 read_h, offset: %04x\n", offset));
if (offset >= 0x4000 && offset < 0x6000)
return m_prgram[offset & 0x1fff];
@@ -1363,7 +1363,7 @@ READ8_MEMBER(nes_lh53_device::read_m)
READ8_MEMBER(nes_lh53_device::read_h)
{
-// LOG_MMC(("lh53 read_h, offset: %04x\n", offset));
+// LOG_MMC(("lh53 read_h, offset: %04x\n", offset));
if (offset >= 0x3800 && offset < 0x5800)
return m_battery[offset & 0x1fff];
@@ -1431,7 +1431,7 @@ WRITE8_MEMBER(nes_2708_device::write_m)
READ8_MEMBER(nes_2708_device::read_h)
{
-// LOG_MMC(("btl-2708 read_h, offset: %04x\n", offset));
+// LOG_MMC(("btl-2708 read_h, offset: %04x\n", offset));
if (offset >= 0x3800 && offset < 0x5800 && !m_reg[1])
return m_prgram[0x2000 + ((offset - 0x3800) & 0x1fff)]; // higher 8K of WRAM
@@ -1656,30 +1656,29 @@ READ8_MEMBER(nes_shuiguan_device::read_m)
/*-------------------------------------------------
-
+
RT-01
-
+
Games: Russian test cart
-
- The PRG EPROM has copy protected areas with
+
+ The PRG EPROM has copy protected areas with
"weak bits", which is tested at some points (info
from Cah4e3).
-
+
iNES:
-
+
In MESS:
-
+
-------------------------------------------------*/
READ8_MEMBER(nes_rt01_device::read_h)
{
-// LOG_MMC(("rt01 read_h, offset: %04x\n", offset));
+// LOG_MMC(("rt01 read_h, offset: %04x\n", offset));
if ((offset >= 0x4e80) && (offset < 0x4f00))
return 0xf2 | (machine().rand() & 0x0d);
if ((offset >= 0x7e80) && (offset < 0x7f00))
return 0xf2 | (machine().rand() & 0x0d);
-
+
return hi_access_rom(offset);
}
-
diff --git a/src/devices/bus/nes/bootleg.h b/src/devices/bus/nes/bootleg.h
index 30b40b589a4..59f02a476a5 100644
--- a/src/devices/bus/nes/bootleg.h
+++ b/src/devices/bus/nes/bootleg.h
@@ -460,11 +460,11 @@ class nes_rt01_device : public nes_nrom_device
public:
// construction/destruction
nes_rt01_device(const machine_config &mconfig, const char *tag, device_t *owner, UINT32 clock);
-
+
// device-level overrides
virtual void device_start() override;
virtual DECLARE_READ8_MEMBER(read_h) override;
-
+
virtual void pcb_reset() override;
};
diff --git a/src/devices/bus/nes/kaiser.cpp b/src/devices/bus/nes/kaiser.cpp
index 340aca500cc..e335681157d 100644
--- a/src/devices/bus/nes/kaiser.cpp
+++ b/src/devices/bus/nes/kaiser.cpp
@@ -252,7 +252,7 @@ void nes_ks7016_device::pcb_reset()
prg8_cd(0xe);
prg8_ef(0xf);
chr8(0, CHRRAM);
-
+
m_reg = 4;
}
@@ -270,7 +270,7 @@ void nes_ks7037_device::pcb_reset()
prg8_cd(0);
prg8_ef(0x1f);
chr8(0, CHRRAM);
-
+
memset(m_reg, 0, sizeof(m_reg));
m_latch = 0;
}
@@ -637,15 +637,15 @@ WRITE8_MEMBER(nes_ks7031_device::write_h)
/*-------------------------------------------------
-
+
Kaiser Board KS7016
-
+
Games: Exciting Basket FDS Conversion
-
+
iNES:
-
+
In MESS: Unsupported.
-
+
-------------------------------------------------*/
READ8_MEMBER(nes_ks7016_device::read_m)
@@ -666,20 +666,20 @@ WRITE8_MEMBER(nes_ks7016_device::write_h)
/*-------------------------------------------------
-
+
Kaiser Board KS7037
-
+
Games: Metroid (FDS conversion)
-
+
This PCB maps PRG in 0x7000-0x7fff in a very
similar fashion to LH10 (see bootleg.cpp)
but with WRAM split between 0x6000-0x6fff
and 0xb000-0xbfff.
-
+
iNES:
-
+
In MESS: Unsupported.
-
+
-------------------------------------------------*/
void nes_ks7037_device::update_prg()
@@ -696,7 +696,7 @@ void nes_ks7037_device::update_prg()
READ8_MEMBER(nes_ks7037_device::read_m)
{
-// LOG_MMC(("ks7037 read_m, offset: %04x\n", offset));
+// LOG_MMC(("ks7037 read_m, offset: %04x\n", offset));
if (offset < 0x1000)
return m_prgram[offset & 0x0fff];
else
@@ -712,18 +712,18 @@ WRITE8_MEMBER(nes_ks7037_device::write_m)
READ8_MEMBER(nes_ks7037_device::read_h)
{
-// LOG_MMC(("ks7037 read_h, offset: %04x\n", offset));
-
+// LOG_MMC(("ks7037 read_h, offset: %04x\n", offset));
+
if (offset >= 0x3000 && offset < 0x4000)
return m_prgram[0x1000 + (offset & 0x0fff)];
-
+
return hi_access_rom(offset);
}
WRITE8_MEMBER(nes_ks7037_device::write_h)
{
LOG_MMC(("ks7037 write_h, offset: %04x, data: %02x\n", offset, data));
-
+
if (offset >= 0x3000 && offset < 0x4000)
m_prgram[0x1000 + (offset & 0x0fff)] = data;
else
@@ -740,4 +740,3 @@ WRITE8_MEMBER(nes_ks7037_device::write_h)
}
}
}
-
diff --git a/src/devices/bus/nes/kaiser.h b/src/devices/bus/nes/kaiser.h
index e5ad8628436..6d58ff134fe 100644
--- a/src/devices/bus/nes/kaiser.h
+++ b/src/devices/bus/nes/kaiser.h
@@ -177,14 +177,14 @@ class nes_ks7016_device : public nes_nrom_device
public:
// construction/destruction
nes_ks7016_device(const machine_config &mconfig, const char *tag, device_t *owner, UINT32 clock);
-
+
// device-level overrides
virtual void device_start() override;
virtual DECLARE_READ8_MEMBER(read_m) override;
virtual DECLARE_WRITE8_MEMBER(write_h) override;
-
+
virtual void pcb_reset() override;
-
+
private:
UINT8 m_reg;
};
@@ -196,16 +196,16 @@ class nes_ks7037_device : public nes_nrom_device
public:
// construction/destruction
nes_ks7037_device(const machine_config &mconfig, const char *tag, device_t *owner, UINT32 clock);
-
+
// device-level overrides
virtual void device_start() override;
virtual DECLARE_READ8_MEMBER(read_m) override;
virtual DECLARE_READ8_MEMBER(read_h) override;
virtual DECLARE_WRITE8_MEMBER(write_m) override;
virtual DECLARE_WRITE8_MEMBER(write_h) override;
-
+
virtual void pcb_reset() override;
-
+
private:
void update_prg();
UINT8 m_latch;
diff --git a/src/devices/bus/nubus/nubus_image.h b/src/devices/bus/nubus/nubus_image.h
index 6badecd4f0d..54fe5dbb39b 100644
--- a/src/devices/bus/nubus/nubus_image.h
+++ b/src/devices/bus/nubus/nubus_image.h
@@ -18,7 +18,7 @@ struct nbfilectx {
UINT32 curcmd;
UINT8 filename[128];
UINT8 curdir[1024];
- osd::directory::ptr dirp;
+ osd::directory::ptr dirp;
osd_file::ptr fd;
UINT64 filelen;
UINT32 bytecount;
diff --git a/src/devices/bus/pofo/exp.h b/src/devices/bus/pofo/exp.h
index 3b1e936dca5..81777cf9852 100644
--- a/src/devices/bus/pofo/exp.h
+++ b/src/devices/bus/pofo/exp.h
@@ -65,16 +65,16 @@
MCFG_DEVICE_SLOT_INTERFACE(_slot_intf, _def_slot, false)
#define MCFG_PORTFOLIO_EXPANSION_SLOT_IINT_CALLBACK(_write) \
- devcb = &portfolio_expansion_slot_t::set_iint_wr_callback(*device, DEVCB_##_write);
+ devcb = &portfolio_expansion_slot_t::set_iint_wr_callback(*device, DEVCB_##_write);
#define MCFG_PORTFOLIO_EXPANSION_SLOT_EINT_CALLBACK(_write) \
- devcb = &portfolio_expansion_slot_t::set_eint_wr_callback(*device, DEVCB_##_write);
+ devcb = &portfolio_expansion_slot_t::set_eint_wr_callback(*device, DEVCB_##_write);
#define MCFG_PORTFOLIO_EXPANSION_SLOT_NMIO_CALLBACK(_write) \
- devcb = &portfolio_expansion_slot_t::set_nmio_wr_callback(*device, DEVCB_##_write);
+ devcb = &portfolio_expansion_slot_t::set_nmio_wr_callback(*device, DEVCB_##_write);
#define MCFG_PORTFOLIO_EXPANSION_SLOT_WAKE_CALLBACK(_write) \
- devcb = &portfolio_expansion_slot_t::set_wake_wr_callback(*device, DEVCB_##_write);
+ devcb = &portfolio_expansion_slot_t::set_wake_wr_callback(*device, DEVCB_##_write);
@@ -89,71 +89,71 @@ class portfolio_expansion_slot_t;
class device_portfolio_expansion_slot_interface : public device_slot_card_interface
{
public:
- // construction/destruction
- device_portfolio_expansion_slot_interface(const machine_config &mconfig, device_t &device);
- virtual ~device_portfolio_expansion_slot_interface() { }
+ // construction/destruction
+ device_portfolio_expansion_slot_interface(const machine_config &mconfig, device_t &device);
+ virtual ~device_portfolio_expansion_slot_interface() { }
- virtual bool nmd1() { return 1; }
- virtual bool pdet() { return 0; }
- virtual bool cdet() { return 1; }
+ virtual bool nmd1() { return 1; }
+ virtual bool pdet() { return 0; }
+ virtual bool cdet() { return 1; }
- virtual UINT8 iack_r() { return 0xff; }
- virtual UINT8 eack_r() { return 0xff; }
+ virtual UINT8 iack_r() { return 0xff; }
+ virtual UINT8 eack_r() { return 0xff; }
- virtual UINT8 nrdi_r(address_space &space, offs_t offset, UINT8 data, bool iom, bool bcom, bool ncc1) { return data; };
- virtual void nwri_w(address_space &space, offs_t offset, UINT8 data, bool iom, bool bcom, bool ncc1) { };
+ virtual UINT8 nrdi_r(address_space &space, offs_t offset, UINT8 data, bool iom, bool bcom, bool ncc1) { return data; };
+ virtual void nwri_w(address_space &space, offs_t offset, UINT8 data, bool iom, bool bcom, bool ncc1) { };
- DECLARE_WRITE_LINE_MEMBER( iint_w );
- DECLARE_WRITE_LINE_MEMBER( eint_w );
- DECLARE_WRITE_LINE_MEMBER( nmio_w );
- DECLARE_WRITE_LINE_MEMBER( wake_w );
+ DECLARE_WRITE_LINE_MEMBER( iint_w );
+ DECLARE_WRITE_LINE_MEMBER( eint_w );
+ DECLARE_WRITE_LINE_MEMBER( nmio_w );
+ DECLARE_WRITE_LINE_MEMBER( wake_w );
protected:
- portfolio_expansion_slot_t *m_slot;
+ portfolio_expansion_slot_t *m_slot;
};
// ======================> portfolio_expansion_slot_t
class portfolio_expansion_slot_t : public device_t,
- public device_slot_interface
+ public device_slot_interface
{
public:
// construction/destruction
portfolio_expansion_slot_t(const machine_config &mconfig, const char *tag, device_t *owner, UINT32 clock);
virtual ~portfolio_expansion_slot_t() { }
- template<class _Object> static devcb_base &set_iint_wr_callback(device_t &device, _Object object) { return downcast<portfolio_expansion_slot_t &>(device).m_write_iint.set_callback(object); }
- template<class _Object> static devcb_base &set_eint_wr_callback(device_t &device, _Object object) { return downcast<portfolio_expansion_slot_t &>(device).m_write_eint.set_callback(object); }
- template<class _Object> static devcb_base &set_nmio_wr_callback(device_t &device, _Object object) { return downcast<portfolio_expansion_slot_t &>(device).m_write_nmio.set_callback(object); }
- template<class _Object> static devcb_base &set_wake_wr_callback(device_t &device, _Object object) { return downcast<portfolio_expansion_slot_t &>(device).m_write_wake.set_callback(object); }
+ template<class _Object> static devcb_base &set_iint_wr_callback(device_t &device, _Object object) { return downcast<portfolio_expansion_slot_t &>(device).m_write_iint.set_callback(object); }
+ template<class _Object> static devcb_base &set_eint_wr_callback(device_t &device, _Object object) { return downcast<portfolio_expansion_slot_t &>(device).m_write_eint.set_callback(object); }
+ template<class _Object> static devcb_base &set_nmio_wr_callback(device_t &device, _Object object) { return downcast<portfolio_expansion_slot_t &>(device).m_write_nmio.set_callback(object); }
+ template<class _Object> static devcb_base &set_wake_wr_callback(device_t &device, _Object object) { return downcast<portfolio_expansion_slot_t &>(device).m_write_wake.set_callback(object); }
// computer interface
- bool nmd1_r() { return (m_card != nullptr) ? m_card->nmd1() : 1; }
- bool pdet_r() { return (m_card != nullptr) ? m_card->pdet() : 0; }
- bool cdet_r() { return (m_card != nullptr) ? m_card->cdet() : 1; }
+ bool nmd1_r() { return (m_card != nullptr) ? m_card->nmd1() : 1; }
+ bool pdet_r() { return (m_card != nullptr) ? m_card->pdet() : 0; }
+ bool cdet_r() { return (m_card != nullptr) ? m_card->cdet() : 1; }
- UINT8 iack_r() { return (m_card != nullptr) ? m_card->iack_r() : 0xff; };
- UINT8 eack_r() { return (m_card != nullptr) ? m_card->eack_r() : 0xff; };
+ UINT8 iack_r() { return (m_card != nullptr) ? m_card->iack_r() : 0xff; };
+ UINT8 eack_r() { return (m_card != nullptr) ? m_card->eack_r() : 0xff; };
UINT8 nrdi_r(address_space &space, offs_t offset, UINT8 data, bool iom, bool bcom, bool ncc1) { return (m_card != nullptr) ? m_card->nrdi_r(space, offset, data, iom, bcom, ncc1) : data; }
void nwri_w(address_space &space, offs_t offset, UINT8 data, bool iom, bool bcom, bool ncc1) { if (m_card != nullptr) m_card->nwri_w(space, offset, data, iom, bcom, ncc1); }
- // peripheral interface
- WRITE_LINE_MEMBER( iint_w ) { m_write_iint(state); }
- WRITE_LINE_MEMBER( eint_w ) { m_write_eint(state); }
- WRITE_LINE_MEMBER( nmio_w ) { m_write_nmio(state); }
- WRITE_LINE_MEMBER( wake_w ) { m_write_wake(state); }
+ // peripheral interface
+ WRITE_LINE_MEMBER( iint_w ) { m_write_iint(state); }
+ WRITE_LINE_MEMBER( eint_w ) { m_write_eint(state); }
+ WRITE_LINE_MEMBER( nmio_w ) { m_write_nmio(state); }
+ WRITE_LINE_MEMBER( wake_w ) { m_write_wake(state); }
protected:
// device-level overrides
virtual void device_start() override;
virtual void device_reset() override;
- devcb_write_line m_write_iint;
- devcb_write_line m_write_eint;
- devcb_write_line m_write_nmio;
- devcb_write_line m_write_wake;
+ devcb_write_line m_write_iint;
+ devcb_write_line m_write_eint;
+ devcb_write_line m_write_nmio;
+ devcb_write_line m_write_wake;
device_portfolio_expansion_slot_interface *m_card;
};
diff --git a/src/devices/bus/pofo/hpc101.h b/src/devices/bus/pofo/hpc101.h
index 36b4129049b..7fbdd58a1a9 100644
--- a/src/devices/bus/pofo/hpc101.h
+++ b/src/devices/bus/pofo/hpc101.h
@@ -25,7 +25,7 @@
// ======================> hpc101_t
class hpc101_t : public device_t,
- public device_portfolio_expansion_slot_interface
+ public device_portfolio_expansion_slot_interface
{
public:
// construction/destruction
@@ -42,8 +42,8 @@ protected:
// device_portfolio_expansion_slot_interface overrides
bool pdet() override { return 1; }
- virtual UINT8 nrdi_r(address_space &space, offs_t offset, UINT8 data, bool iom, bool bcom, bool ncc1) override;
- virtual void nwri_w(address_space &space, offs_t offset, UINT8 data, bool iom, bool bcom, bool ncc1) override;
+ virtual UINT8 nrdi_r(address_space &space, offs_t offset, UINT8 data, bool iom, bool bcom, bool ncc1) override;
+ virtual void nwri_w(address_space &space, offs_t offset, UINT8 data, bool iom, bool bcom, bool ncc1) override;
private:
required_device<i8255_device> m_ppi;
diff --git a/src/devices/bus/pofo/hpc102.h b/src/devices/bus/pofo/hpc102.h
index c1fb91305af..fc251b2e87b 100644
--- a/src/devices/bus/pofo/hpc102.h
+++ b/src/devices/bus/pofo/hpc102.h
@@ -25,7 +25,7 @@
// ======================> hpc102_t
class hpc102_t : public device_t,
- public device_portfolio_expansion_slot_interface
+ public device_portfolio_expansion_slot_interface
{
public:
// construction/destruction
@@ -42,10 +42,10 @@ protected:
// device_portfolio_expansion_slot_interface overrides
bool pdet() override { return 1; }
- virtual UINT8 eack_r() override;
+ virtual UINT8 eack_r() override;
- virtual UINT8 nrdi_r(address_space &space, offs_t offset, UINT8 data, bool iom, bool bcom, bool ncc1) override;
- virtual void nwri_w(address_space &space, offs_t offset, UINT8 data, bool iom, bool bcom, bool ncc1) override;
+ virtual UINT8 nrdi_r(address_space &space, offs_t offset, UINT8 data, bool iom, bool bcom, bool ncc1) override;
+ virtual void nwri_w(address_space &space, offs_t offset, UINT8 data, bool iom, bool bcom, bool ncc1) override;
private:
required_device<ins8250_device> m_uart;
@@ -63,4 +63,4 @@ extern const device_type HPC102;
/*
-*/ \ No newline at end of file
+*/
diff --git a/src/devices/bus/sg1000_exp/fm_unit.cpp b/src/devices/bus/sg1000_exp/fm_unit.cpp
index 935346e17de..46e7b036704 100644
--- a/src/devices/bus/sg1000_exp/fm_unit.cpp
+++ b/src/devices/bus/sg1000_exp/fm_unit.cpp
@@ -74,7 +74,7 @@ READ8_MEMBER(sega_fm_unit_device::peripheral_r)
return m_audio_control & 0x01;
}
// will not be called for other offsets.
- return 0xff;
+ return 0xff;
}
//-------------------------------------------------
@@ -116,4 +116,3 @@ bool sega_fm_unit_device::is_writeable(UINT8 offset)
{
return (offset <= 2) ? true : false;
}
-
diff --git a/src/devices/bus/sg1000_exp/sk1100.cpp b/src/devices/bus/sg1000_exp/sk1100.cpp
index 3c5726f96dc..aee9e3c09f7 100644
--- a/src/devices/bus/sg1000_exp/sk1100.cpp
+++ b/src/devices/bus/sg1000_exp/sk1100.cpp
@@ -334,4 +334,3 @@ WRITE8_MEMBER( sega_sk1100_device::ppi_pc_w )
/* TODO printer */
}
-
diff --git a/src/devices/cpu/asap/asapdasm.cpp b/src/devices/cpu/asap/asapdasm.cpp
index fd204c68a94..ded3a24e17b 100644
--- a/src/devices/cpu/asap/asapdasm.cpp
+++ b/src/devices/cpu/asap/asapdasm.cpp
@@ -91,7 +91,7 @@ CPU_DISASSEMBLE( asap )
sprintf(buffer, "mov%s %s,%s", setcond[cond], reg[rsrc1], reg[rdst]);
else
sprintf(buffer, "add%s %s,%s,%s", setcond[cond], reg[rsrc1], src2(op,0), reg[rdst]);
- break;
+ break;
case 0x09: sprintf(buffer, "sub%s %s,%s,%s", setcond[cond], reg[rsrc1], src2(op,0), reg[rdst]); break;
case 0x0a: sprintf(buffer, "addc%s %s,%s,%s", setcond[cond], reg[rsrc1], src2(op,0), reg[rdst]); break;
case 0x0b: sprintf(buffer, "subc%s %s,%s,%s", setcond[cond], reg[rsrc1], src2(op,0), reg[rdst]); break;
diff --git a/src/devices/cpu/avr8/avr8.cpp b/src/devices/cpu/avr8/avr8.cpp
index 2d2dd04824d..f0e790083f7 100644
--- a/src/devices/cpu/avr8/avr8.cpp
+++ b/src/devices/cpu/avr8/avr8.cpp
@@ -2915,7 +2915,7 @@ READ8_MEMBER( avr8_device::regs_r )
default:
printf("[%08X] AVR8: Unknown Register Read: 0x%03X\n", m_shifted_pc, offset);
-// machine().debug_break();
+// machine().debug_break();
return 0;
}
}
diff --git a/src/devices/cpu/drcbex64.cpp b/src/devices/cpu/drcbex64.cpp
index e1d41783a25..df5fc335599 100644
--- a/src/devices/cpu/drcbex64.cpp
+++ b/src/devices/cpu/drcbex64.cpp
@@ -175,7 +175,6 @@
// This is a trick to make it build on Android where the ARM SDK declares ::REG_Rn
namespace drc {
-
using namespace uml;
using namespace x64emit;
diff --git a/src/devices/cpu/drcbex64.h b/src/devices/cpu/drcbex64.h
index 2dcca934ddd..fc8b3cae1af 100644
--- a/src/devices/cpu/drcbex64.h
+++ b/src/devices/cpu/drcbex64.h
@@ -22,7 +22,6 @@
namespace drc {
-
//**************************************************************************
// TYPE DEFINITIONS
//**************************************************************************
diff --git a/src/devices/cpu/m6502/odeco16.lst b/src/devices/cpu/m6502/odeco16.lst
index 3fbc2409789..367f1c00704 100644
--- a/src/devices/cpu/m6502/odeco16.lst
+++ b/src/devices/cpu/m6502/odeco16.lst
@@ -92,7 +92,7 @@ vbl_zpg
TMP2 = read_pc();
A = io->read_byte(0);
//if(DECO16_VERBOSE)
- // logerror("%s: VBL %02x (%04x)\n", tag(), NPC, TMP2);
+ // logerror("%s: VBL %02x (%04x)\n", tag(), NPC, TMP2);
prefetch();
# exceptions
diff --git a/src/devices/cpu/mb86235/mb86235d.cpp b/src/devices/cpu/mb86235/mb86235d.cpp
index 34771cd346e..58dcfc047b6 100644
--- a/src/devices/cpu/mb86235/mb86235d.cpp
+++ b/src/devices/cpu/mb86235/mb86235d.cpp
@@ -6,14 +6,14 @@
static const char *regname[128] =
{
- "MA0", "MA1", "MA2", "MA3", "MA4", "MA5", "MA6", "MA7",
- "AA0", "AA1", "AA2", "AA3", "AA4", "AA5", "AA6", "AA7",
- "EB", "EBU", "EBL", "EO", "SP", "ST", "MOD", "LRPC",
- "AR0", "AR1", "AR2", "AR3", "AR4", "AR5", "AR6", "AR7",
- "MB0", "MB1", "MB2", "MB3", "MB4", "MB5", "MB6", "MB7",
- "AB0", "AB1", "AB2", "AB3", "AB4", "AB5", "AB6", "AB7",
- "PR", "FI", "FO0", "FO1", "PDR", "DDR", "PRP", "PWP",
- "???", "???", "???", "???", "???", "???", "???", "???"
+ "MA0", "MA1", "MA2", "MA3", "MA4", "MA5", "MA6", "MA7",
+ "AA0", "AA1", "AA2", "AA3", "AA4", "AA5", "AA6", "AA7",
+ "EB", "EBU", "EBL", "EO", "SP", "ST", "MOD", "LRPC",
+ "AR0", "AR1", "AR2", "AR3", "AR4", "AR5", "AR6", "AR7",
+ "MB0", "MB1", "MB2", "MB3", "MB4", "MB5", "MB6", "MB7",
+ "AB0", "AB1", "AB2", "AB3", "AB4", "AB5", "AB6", "AB7",
+ "PR", "FI", "FO0", "FO1", "PDR", "DDR", "PRP", "PWP",
+ "???", "???", "???", "???", "???", "???", "???", "???"
};
static const char *db_mnemonic[64] =
@@ -69,22 +69,22 @@ static const char *mi1_field[16] =
static const char *mi2_field[32] =
{ "MA0", "MA1", "MA2", "MA3", "MA4", "MA5", "MA6", "MA7", "MB0", "MB1", "MB2", "MB3", "MB4", "MB5", "MB6", "MB7",
- "PR", "PR++", "PR--", "PR#0", "???", "???", "???", "???", "-1.0E+0", "0.0E+0", "0.5E+0", "1.0E+0", "1.5E+0", "2.0E+0", "3.0E+0", "5.0E+0" };
+ "PR", "PR++", "PR--", "PR#0", "???", "???", "???", "???", "-1.0E+0", "0.0E+0", "0.5E+0", "1.0E+0", "1.5E+0", "2.0E+0", "3.0E+0", "5.0E+0" };
-static const char *mo_field[32] =
+static const char *mo_field[32] =
{ "MA0", "MA1", "MA2", "MA3", "MA4", "MA5", "MA6", "MA7", "MB0", "MB1", "MB2", "MB3", "MB4", "MB5", "MB6", "MB7",
- "AA0", "AA1", "AA2", "AA3", "AA4", "AA5", "AA6", "AA7", "AB0", "AB1", "AB2", "AB3", "AB4", "AB5", "AB6", "AB7" };
+ "AA0", "AA1", "AA2", "AA3", "AA4", "AA5", "AA6", "AA7", "AB0", "AB1", "AB2", "AB3", "AB4", "AB5", "AB6", "AB7" };
-static const char *ai1_field[16] =
+static const char *ai1_field[16] =
{ "AA0", "AA1", "AA2", "AA3", "AA4", "AA5", "AA6", "AA7", "AB0", "AB1", "AB2", "AB3", "AB4", "AB5", "AB6", "AB7" };
static const char *ai2_field[32] =
{ "AA0", "AA1", "AA2", "AA3", "AA4", "AA5", "AA6", "AA7", "AB0", "AB1", "AB2", "AB3", "AB4", "AB5", "AB6", "AB7",
- "PR", "PR++", "PR--", "PR#0", "???", "???", "???", "???", "0", "1", "-1", "???", "???", "???", "???", "???" };
+ "PR", "PR++", "PR--", "PR#0", "???", "???", "???", "???", "0", "1", "-1", "???", "???", "???", "???", "???" };
static const char *ai2f_field[32] =
{ "AA0", "AA1", "AA2", "AA3", "AA4", "AA5", "AA6", "AA7", "AB0", "AB1", "AB2", "AB3", "AB4", "AB5", "AB6", "AB7",
- "PR", "PR++", "PR--", "PR#0", "???", "???", "???", "???", "-1.0E+0", "0.0E+0", "0.5E+0", "1.0E+0", "1.5E+0", "2.0E+0", "3.0E+0", "5.0E+0" };
+ "PR", "PR++", "PR--", "PR#0", "???", "???", "???", "???", "-1.0E+0", "0.0E+0", "0.5E+0", "1.0E+0", "1.5E+0", "2.0E+0", "3.0E+0", "5.0E+0" };
static char* get_ea(int md, int arx, int ary, int disp)
{
@@ -196,7 +196,7 @@ static char* dasm_alu_mul(UINT64 opcode, bool twoop)
break;
}
}
-
+
// multiplication
if (twoop)
{
@@ -211,7 +211,7 @@ static char* dasm_alu_mul(UINT64 opcode, bool twoop)
else
{
if (ma == 0)
- {
+ {
if (opcode & ((UINT64)(1) << 56))
p += sprintf(p, "FMUL %s, %s, %s", mi1_field[i1], mi2_field[i2], mo_field[o]);
else
@@ -296,12 +296,12 @@ static char* dasm_control(UINT32 pc, UINT64 opcode)
p += sprintf(p, "DRET");
break;
- case 0x10: // DBcc
- case 0x11: // DBNcc
- case 0x18: // DCcc
- case 0x19: // DCNcc
- case 0x1a: // DCALL
- case 0x12: // DJMP
+ case 0x10: // DBcc
+ case 0x11: // DBNcc
+ case 0x18: // DCcc
+ case 0x19: // DCNcc
+ case 0x1a: // DCALL
+ case 0x12: // DJMP
{
if (cop == 0x10)
p += sprintf(p, "%s ", db_mnemonic[ef1]);
@@ -798,25 +798,25 @@ static unsigned dasm_mb86235(char *buffer, UINT32 pc, UINT64 opcode)
switch ((opcode >> 61) & 7)
{
- case 0: // ALU / MUL / double transfer (type 1)
+ case 0: // ALU / MUL / double transfer (type 1)
p += sprintf(p, "%s : %s", dasm_alu_mul(opcode, true), dasm_double_xfer1(opcode));
break;
- case 1: // ALU / MYL / transfer (type 1)
+ case 1: // ALU / MYL / transfer (type 1)
p += sprintf(p, "%s : %s", dasm_alu_mul(opcode, true), dasm_xfer1(opcode));
break;
- case 2: // ALU / MUL / control
+ case 2: // ALU / MUL / control
p += sprintf(p, "%s : %s", dasm_alu_mul(opcode, true), dasm_control(pc, opcode));
break;
- case 4: // ALU or MUL / double transfer (type 2)
+ case 4: // ALU or MUL / double transfer (type 2)
p += sprintf(p, "%s : %s", dasm_alu_mul(opcode, false), dasm_double_xfer2(opcode));
break;
- case 5: // ALU or MUL / transfer (type 2)
+ case 5: // ALU or MUL / transfer (type 2)
p += sprintf(p, "%s : %s", dasm_alu_mul(opcode, false), dasm_xfer2(opcode));
break;
- case 6: // ALU or MUL / control
+ case 6: // ALU or MUL / control
p += sprintf(p, "%s : %s", dasm_alu_mul(opcode, false), dasm_control(pc, opcode));
break;
- case 7: // transfer (type 3)
+ case 7: // transfer (type 3)
p += sprintf(p, "%s", dasm_xfer3(opcode));
break;
diff --git a/src/devices/cpu/nec/v25.h b/src/devices/cpu/nec/v25.h
index 6f0fa25eeb6..f170ad03b8f 100644
--- a/src/devices/cpu/nec/v25.h
+++ b/src/devices/cpu/nec/v25.h
@@ -31,7 +31,7 @@ enum
#define MCFG_V25_PORT_P1_READ_CB(_devcb) \
devcb = &v25_common_device::set_p1_in_cb(*device, DEVCB_##_devcb);
-
+
#define MCFG_V25_PORT_P2_READ_CB(_devcb) \
devcb = &v25_common_device::set_p2_in_cb(*device, DEVCB_##_devcb);
@@ -53,7 +53,7 @@ public:
// static configuration helpers
static void set_decryption_table(device_t &device, const UINT8 *decryption_table) { downcast<v25_common_device &>(device).m_v25v35_decryptiontable = decryption_table; }
-
+
template<class _Object> static devcb_base & set_pt_in_cb(device_t &device, _Object object) { return downcast<v25_common_device &>(device).m_pt_in.set_callback(object); }
template<class _Object> static devcb_base & set_p0_in_cb(device_t &device, _Object object) { return downcast<v25_common_device &>(device).m_p0_in.set_callback(object); }
template<class _Object> static devcb_base & set_p1_in_cb(device_t &device, _Object object) { return downcast<v25_common_device &>(device).m_p1_in.set_callback(object); }
diff --git a/src/devices/cpu/patinhofeio/patinho_feio.cpp b/src/devices/cpu/patinhofeio/patinho_feio.cpp
index 8482db59c41..a040d243916 100644
--- a/src/devices/cpu/patinhofeio/patinho_feio.cpp
+++ b/src/devices/cpu/patinhofeio/patinho_feio.cpp
@@ -1,7 +1,7 @@
// license:GPL-2.0+
// copyright-holders:Felipe Sanches
/*
- CPU emulation for Patinho Feio, the first computer designed and manufactured in Brazil
+ CPU emulation for Patinho Feio, the first computer designed and manufactured in Brazil
*/
#include "emu.h"
@@ -91,11 +91,11 @@ void patinho_feio_cpu_device::device_start()
//TODO: implement handling of these special purpose registers
// which are also mapped to the first few main memory positions:
//
-// ERI: "Endereço de Retorno de Interrupção"
+// ERI: "Endereco de Retorno de Interrupcao"
// "Interrupt Return Address"
// stored at addresses 002 and 003
//
-// ETI: "início de uma rotina de tratamento de interrupção (se houver)"
+// ETI: "inicio de uma rotina de tratamento de interrupcao (se houver)"
// "start of an interrupt service routine (if any)"
// stored at address 004 (and 005 as well?)
//
@@ -333,7 +333,7 @@ void patinho_feio_cpu_device::execute_instruction()
case 0x90:
//ST 0 = "Se T=0, Pula"
// If T is zero, skip the next instruction
- if ((FLAGS & T) == 0)
+ if ((FLAGS & T) == 0)
INCREMENT_PC_4K; //skip
return;
case 0x91:
@@ -348,7 +348,7 @@ void patinho_feio_cpu_device::execute_instruction()
case 0x92:
//ST 1 = "Se T=1, Pula"
// If T is one, skip the next instruction
- if ((FLAGS & T) == 1)
+ if ((FLAGS & T) == 1)
INCREMENT_PC_4K; //skip
return;
case 0x93:
@@ -363,7 +363,7 @@ void patinho_feio_cpu_device::execute_instruction()
case 0x94:
//SV 0 = "Se V=0, Pula"
// If V is zero, skip the next instruction
- if ((FLAGS & V) == 0)
+ if ((FLAGS & V) == 0)
INCREMENT_PC_4K; //skip
return;
case 0x95:
@@ -378,7 +378,7 @@ void patinho_feio_cpu_device::execute_instruction()
case 0x96:
//SV 1 = "Se V=1, Pula"
// If V is one, skip the next instruction
- if ((FLAGS & V) == 1)
+ if ((FLAGS & V) == 1)
INCREMENT_PC_4K; //skip
return;
case 0x97:
@@ -391,17 +391,17 @@ void patinho_feio_cpu_device::execute_instruction()
}
return;
case 0x98:
- //PUL="Pula para /002 a limpa estado de interrupção"
+ //PUL="Pula para /002 a limpa estado de interrupcao"
// Jump to address /002 and disables interrupts
- PC = 0x002;
+ PC = 0x002;
m_interrupts_enabled = false;
return;
case 0x99:
- //TRE="Troca conteúdos de ACC e EXT"
+ //TRE="Troca conteudos de ACC e EXT"
// Exchange the value of the accumulator with the ACC extension register
- value = ACC;
- ACC = READ_ACC_EXTENSION_REG();
- WRITE_ACC_EXTENSION_REG(value);
+ value = ACC;
+ ACC = READ_ACC_EXTENSION_REG();
+ WRITE_ACC_EXTENSION_REG(value);
return;
case 0x9A:
//INIB="Inibe"
@@ -621,7 +621,7 @@ void patinho_feio_cpu_device::execute_instruction()
{
case 0:
// FNC /n0: Desliga flip-flop PERMITE/IMPEDE para
- // o dispositivo n (isto é, impede inter-
+ // o dispositivo n (isto e, impede inter-
// -rupcao do dispositivo n).
//
// Turns off the interrupt ENABLE/DISABLE
@@ -654,7 +654,7 @@ void patinho_feio_cpu_device::execute_instruction()
break;
case 5:
// FNC /n5: Liga flip-flop PERMITE/IMPEDE para o
- // dispositivo n (isto é, permite inter-
+ // dispositivo n (isto e, permite inter-
// -rupcao do dispositivo n).
//
// Turns on the interrupt ENABLE/DISABLE
@@ -681,7 +681,7 @@ void patinho_feio_cpu_device::execute_instruction()
m_iodev_control[channel] = NO_REQUEST;
break;
case 8:
- // FNC /n8: Só funciona na leitora de fita, ca-
+ // FNC /n8: So funciona na leitora de fita, ca-
// nal /E. Ignora todos os "feed-fra-
// -mes" ("bytes" nulos) da fita, ate' a
// proxima perfuracao (1o "byte" nao
@@ -695,7 +695,7 @@ void patinho_feio_cpu_device::execute_instruction()
//TODO: Implement-me!
} else {
printf("Function 8 of the /FNC instruction can only be used with"\
- "the papertape reader device at channel /E.\n");
+ "the papertape reader device at channel /E.\n");
}
break;
default:
@@ -705,7 +705,7 @@ void patinho_feio_cpu_device::execute_instruction()
case 0x20:
//SAL="Salta"
// Skips a couple bytes if a condition is met
- skip = false;
+ skip = false;
switch(function)
{
case 1:
diff --git a/src/devices/cpu/patinhofeio/patinhofeio_cpu.h b/src/devices/cpu/patinhofeio/patinhofeio_cpu.h
index b8e6919273d..5d3a1745f53 100644
--- a/src/devices/cpu/patinhofeio/patinhofeio_cpu.h
+++ b/src/devices/cpu/patinhofeio/patinhofeio_cpu.h
@@ -35,18 +35,18 @@ enum
#define REQUEST true
#define NO_REQUEST false
-#define BUTTON_NORMAL (1 << 0) /* normal CPU execution */
-#define BUTTON_CICLO_UNICO (1 << 1) /* single-cycle step */
-#define BUTTON_INSTRUCAO_UNICA (1 << 2) /* single-instruction step */
-#define BUTTON_ENDERECAMENTO (1 << 3) /* addressing action */
-#define BUTTON_ARMAZENAMENTO (1 << 4) /* storage action */
-#define BUTTON_EXPOSICAO (1 << 5) /* memory viewing action */
-#define BUTTON_ESPERA (1 << 6) /* wait */
-#define BUTTON_INTERRUPCAO (1 << 7) /* interrupt */
-#define BUTTON_PARTIDA (1 << 8) /* startup */
-#define BUTTON_PREPARACAO (1 << 9) /* reset */
-#define BUTTON_TIPO_DE_ENDERECAMENTO (1 << 10) /* Addressing mode (0: Fixed / 1: Sequential) */
-#define BUTTON_PROTECAO_DE_MEMORIA (1 << 11) /* Memory protection (in the address range 0xF80-0xFFF (1: write-only / 0: read-write) */
+#define BUTTON_NORMAL (1 << 0) /* normal CPU execution */
+#define BUTTON_CICLO_UNICO (1 << 1) /* single-cycle step */
+#define BUTTON_INSTRUCAO_UNICA (1 << 2) /* single-instruction step */
+#define BUTTON_ENDERECAMENTO (1 << 3) /* addressing action */
+#define BUTTON_ARMAZENAMENTO (1 << 4) /* storage action */
+#define BUTTON_EXPOSICAO (1 << 5) /* memory viewing action */
+#define BUTTON_ESPERA (1 << 6) /* wait */
+#define BUTTON_INTERRUPCAO (1 << 7) /* interrupt */
+#define BUTTON_PARTIDA (1 << 8) /* startup */
+#define BUTTON_PREPARACAO (1 << 9) /* reset */
+#define BUTTON_TIPO_DE_ENDERECAMENTO (1 << 10) /* Addressing mode (0: Fixed / 1: Sequential) */
+#define BUTTON_PROTECAO_DE_MEMORIA (1 << 11) /* Memory protection (in the address range 0xF80-0xFFF (1: write-only / 0: read-write) */
class patinho_feio_cpu_device : public cpu_device {
public:
@@ -76,14 +76,14 @@ protected:
/* processor registers */
unsigned char m_acc; /* accumulator (8 bits) */
unsigned int m_pc; /* program counter (12 bits)
- * Actual register name is CI, which
- * stands for "Contador de Instrucao"
- * or "instructions counter".
- */
+ * Actual register name is CI, which
+ * stands for "Contador de Instrucao"
+ * or "instructions counter".
+ */
unsigned int m_rc; /* RC = "Registrador de Chaves" (Keys Register)
- * It represents the 12 bits of input data
- * from toggle switches in the computer panel
- */
+ * It represents the 12 bits of input data
+ * from toggle switches in the computer panel
+ */
unsigned char m_idx; /* IDX = Index Register */
unsigned char m_ext; /* EXT = Accumulator Extension Register */
diff --git a/src/devices/cpu/sharc/sharc.cpp b/src/devices/cpu/sharc/sharc.cpp
index 4123da67594..44a7c650d7d 100644
--- a/src/devices/cpu/sharc/sharc.cpp
+++ b/src/devices/cpu/sharc/sharc.cpp
@@ -11,7 +11,7 @@
#include "sharcfe.h"
-#define DISABLE_FAST_REGISTERS 1
+#define DISABLE_FAST_REGISTERS 1
@@ -336,7 +336,7 @@ void adsp21062_device::external_dma_write(UINT32 address, UINT64 data)
void adsp21062_device::device_start()
{
int saveindex;
-
+
m_core = (sharc_internal_state *)m_cache.alloc_near(sizeof(sharc_internal_state));
memset(m_core, 0, sizeof(sharc_internal_state));
@@ -356,7 +356,7 @@ void adsp21062_device::device_start()
// add UML symbols
m_drcuml->symbol_add(&m_core->pc, sizeof(m_core->pc), "pc");
m_drcuml->symbol_add(&m_core->icount, sizeof(m_core->icount), "icount");
-
+
for (int i=0; i < 16; i++)
{
char buf[10];
@@ -412,7 +412,7 @@ void adsp21062_device::device_start()
m_drcuml->symbol_add(&m_core->astat_drc.sz, sizeof(m_core->astat_drc.sz), "astat_sz");
m_drcuml->symbol_add(&m_core->astat_drc.sv, sizeof(m_core->astat_drc.sv), "astat_sv");
m_drcuml->symbol_add(&m_core->astat_drc.ss, sizeof(m_core->astat_drc.ss), "astat_ss");
-
+
m_drcuml->symbol_add(&m_core->arg0, sizeof(m_core->arg0), "arg0");
m_drcuml->symbol_add(&m_core->arg1, sizeof(m_core->arg1), "arg1");
m_drcuml->symbol_add(&m_core->arg2, sizeof(m_core->arg2), "arg2");
diff --git a/src/devices/cpu/sharc/sharc.h b/src/devices/cpu/sharc/sharc.h
index 215135390e0..1eb2dc8972b 100644
--- a/src/devices/cpu/sharc/sharc.h
+++ b/src/devices/cpu/sharc/sharc.h
@@ -111,25 +111,25 @@ struct SHARC_DMA_OP
#define MODE2_CAFRZ 0x80000 /* Cache freeze */
-#define SIGN_EXTEND6(x) (((x) & 0x20) ? (0xffffffc0 | (x)) : (x))
-#define SIGN_EXTEND24(x) (((x) & 0x800000) ? (0xff000000 | (x)) : (x))
+#define SIGN_EXTEND6(x) (((x) & 0x20) ? (0xffffffc0 | (x)) : (x))
+#define SIGN_EXTEND24(x) (((x) & 0x800000) ? (0xff000000 | (x)) : (x))
#define MAKE_EXTRACT_MASK(start_bit, length) ((0xffffffff << start_bit) & (((UINT32)0xffffffff) >> (32 - (start_bit + length))))
-#define OP_USERFLAG_COUNTER_LOOP 0x00000001
-#define OP_USERFLAG_COND_LOOP 0x00000002
-#define OP_USERFLAG_COND_FIELD 0x000003fc
-#define OP_USERFLAG_COND_FIELD_SHIFT 2
-#define OP_USERFLAG_ASTAT_DELAY_COPY_AZ 0x00001000
-#define OP_USERFLAG_ASTAT_DELAY_COPY_AN 0x00002000
-#define OP_USERFLAG_ASTAT_DELAY_COPY_AC 0x00004000
-#define OP_USERFLAG_ASTAT_DELAY_COPY_AV 0x00008000
-#define OP_USERFLAG_ASTAT_DELAY_COPY_MV 0x00010000
-#define OP_USERFLAG_ASTAT_DELAY_COPY_MN 0x00020000
-#define OP_USERFLAG_ASTAT_DELAY_COPY_SV 0x00040000
-#define OP_USERFLAG_ASTAT_DELAY_COPY_SZ 0x00080000
-#define OP_USERFLAG_ASTAT_DELAY_COPY_BTF 0x00100000
-#define OP_USERFLAG_ASTAT_DELAY_COPY 0x001ff000
-#define OP_USERFLAG_CALL 0x10000000
+#define OP_USERFLAG_COUNTER_LOOP 0x00000001
+#define OP_USERFLAG_COND_LOOP 0x00000002
+#define OP_USERFLAG_COND_FIELD 0x000003fc
+#define OP_USERFLAG_COND_FIELD_SHIFT 2
+#define OP_USERFLAG_ASTAT_DELAY_COPY_AZ 0x00001000
+#define OP_USERFLAG_ASTAT_DELAY_COPY_AN 0x00002000
+#define OP_USERFLAG_ASTAT_DELAY_COPY_AC 0x00004000
+#define OP_USERFLAG_ASTAT_DELAY_COPY_AV 0x00008000
+#define OP_USERFLAG_ASTAT_DELAY_COPY_MV 0x00010000
+#define OP_USERFLAG_ASTAT_DELAY_COPY_MN 0x00020000
+#define OP_USERFLAG_ASTAT_DELAY_COPY_SV 0x00040000
+#define OP_USERFLAG_ASTAT_DELAY_COPY_SZ 0x00080000
+#define OP_USERFLAG_ASTAT_DELAY_COPY_BTF 0x00100000
+#define OP_USERFLAG_ASTAT_DELAY_COPY 0x001ff000
+#define OP_USERFLAG_CALL 0x10000000
#define MCFG_SHARC_BOOT_MODE(boot_mode) \
@@ -439,7 +439,7 @@ private:
uml::code_handle *m_pop_loop;
uml::code_handle *m_push_status;
uml::code_handle *m_pop_status;
- uml::code_handle *m_exception[EXCEPTION_COUNT]; // exception handlers
+ uml::code_handle *m_exception[EXCEPTION_COUNT]; // exception handlers
uml::code_handle *m_swap_dag1_0_3;
uml::code_handle *m_swap_dag1_4_7;
uml::code_handle *m_swap_dag2_0_3;
@@ -596,7 +596,7 @@ private:
{
UINT32 cycles; /* accumulated cycles */
UINT8 checkints; /* need to check interrupts before next instruction */
- uml::code_label labelnum; /* index for local labels */
+ uml::code_label labelnum; /* index for local labels */
struct
{
int counter;
diff --git a/src/devices/cpu/sharc/sharcdrc.cpp b/src/devices/cpu/sharc/sharcdrc.cpp
index 2850f91da67..a40586cac23 100644
--- a/src/devices/cpu/sharc/sharcdrc.cpp
+++ b/src/devices/cpu/sharc/sharcdrc.cpp
@@ -17,7 +17,7 @@
using namespace uml;
-#define USE_SWAPDQ 0
+#define USE_SWAPDQ 0
#define WRITE_SNOOP 0
@@ -25,85 +25,85 @@ using namespace uml;
#define MAPVAR_PC M0
#define MAPVAR_CYCLES M1
-// exit codes
+// exit codes
#define EXECUTE_OUT_OF_CYCLES 0
#define EXECUTE_MISSING_CODE 1
#define EXECUTE_UNMAPPED_CODE 2
#define EXECUTE_RESET_CACHE 3
-#define REG(reg) m_regmap[reg]
-#define DM_I(reg) mem(&m_core->dag1.i[reg])
-#define DM_M(reg) mem(&m_core->dag1.m[reg])
-#define DM_L(reg) mem(&m_core->dag1.l[reg])
-#define DM_B(reg) mem(&m_core->dag1.b[reg])
-#define PM_I(reg) mem(&m_core->dag2.i[reg])
-#define PM_M(reg) mem(&m_core->dag2.m[reg])
-#define PM_L(reg) mem(&m_core->dag2.l[reg])
-#define PM_B(reg) mem(&m_core->dag2.b[reg])
-#define ASTAT_AZ mem(&m_core->astat_drc.az)
-#define ASTAT_AV mem(&m_core->astat_drc.av)
-#define ASTAT_AN mem(&m_core->astat_drc.an)
-#define ASTAT_AC mem(&m_core->astat_drc.ac)
-#define ASTAT_AS mem(&m_core->astat_drc.as)
-#define ASTAT_AI mem(&m_core->astat_drc.ai)
-#define ASTAT_AF mem(&m_core->astat_drc.af)
-#define ASTAT_MN mem(&m_core->astat_drc.mn)
-#define ASTAT_MV mem(&m_core->astat_drc.mv)
-#define ASTAT_MU mem(&m_core->astat_drc.mu)
-#define ASTAT_MI mem(&m_core->astat_drc.mi)
-#define ASTAT_SV mem(&m_core->astat_drc.sv)
-#define ASTAT_SZ mem(&m_core->astat_drc.sz)
-#define ASTAT_SS mem(&m_core->astat_drc.ss)
-#define ASTAT_BTF mem(&m_core->astat_drc.btf)
-#define FLAG0 mem(&m_core->flag[0])
-#define FLAG1 mem(&m_core->flag[1])
-#define FLAG2 mem(&m_core->flag[2])
-#define FLAG3 mem(&m_core->flag[3])
-#define CURLCNTR mem(&m_core->curlcntr)
-#define LCNTR mem(&m_core->lcntr)
-#define PCSTK mem(&m_core->pcstk)
-#define PCSTKP mem(&m_core->pcstkp)
-#define STKY mem(&m_core->stky)
-#define LSTKP mem(&m_core->lstkp)
-#define USTAT1 mem(&m_core->ustat1)
-#define USTAT2 mem(&m_core->ustat2)
-#define IRPTL mem(&m_core->irptl)
-#define MODE1 mem(&m_core->mode1)
-#define MODE2 mem(&m_core->mode2)
-#define IMASK mem(&m_core->imask)
-#define IMASKP mem(&m_core->imaskp)
-#define MRF mem(&m_core->mrf)
-#define MRB mem(&m_core->mrb)
-
-#define AZ_CALC_REQUIRED ((desc->regreq[0] & 0x00010000) || desc->flags & OPFLAG_IN_DELAY_SLOT)
-#define AV_CALC_REQUIRED ((desc->regreq[0] & 0x00020000) || desc->flags & OPFLAG_IN_DELAY_SLOT)
-#define AN_CALC_REQUIRED ((desc->regreq[0] & 0x00040000) || desc->flags & OPFLAG_IN_DELAY_SLOT)
-#define AC_CALC_REQUIRED ((desc->regreq[0] & 0x00080000) || desc->flags & OPFLAG_IN_DELAY_SLOT)
-#define AS_CALC_REQUIRED ((desc->regreq[0] & 0x00100000) || desc->flags & OPFLAG_IN_DELAY_SLOT)
-#define AI_CALC_REQUIRED ((desc->regreq[0] & 0x00200000) || desc->flags & OPFLAG_IN_DELAY_SLOT)
-#define MN_CALC_REQUIRED ((desc->regreq[0] & 0x00400000) || desc->flags & OPFLAG_IN_DELAY_SLOT)
-#define MV_CALC_REQUIRED ((desc->regreq[0] & 0x00800000) || desc->flags & OPFLAG_IN_DELAY_SLOT)
-#define MU_CALC_REQUIRED ((desc->regreq[0] & 0x01000000) || desc->flags & OPFLAG_IN_DELAY_SLOT)
-#define MI_CALC_REQUIRED ((desc->regreq[0] & 0x02000000) || desc->flags & OPFLAG_IN_DELAY_SLOT)
-#define SV_CALC_REQUIRED ((desc->regreq[0] & 0x04000000) || desc->flags & OPFLAG_IN_DELAY_SLOT)
-#define SZ_CALC_REQUIRED ((desc->regreq[0] & 0x08000000) || desc->flags & OPFLAG_IN_DELAY_SLOT)
-#define SS_CALC_REQUIRED ((desc->regreq[0] & 0x10000000) || desc->flags & OPFLAG_IN_DELAY_SLOT)
-#define BTF_CALC_REQUIRED ((desc->regreq[0] & 0x20000000) || desc->flags & OPFLAG_IN_DELAY_SLOT)
-#define AF_CALC_REQUIRED ((desc->regreq[0] & 0x40000000) || desc->flags & OPFLAG_IN_DELAY_SLOT)
-
-
-#define IRAM_BLOCK0_START 0x20000
-#define IRAM_BLOCK0_END 0x27fff
-#define IRAM_BLOCK1_START 0x28000
-#define IRAM_BLOCK1_END 0x3ffff
-#define IRAM_SHORT_BLOCK0_START 0x40000
-#define IRAM_SHORT_BLOCK0_END 0x4ffff
-#define IRAM_SHORT_BLOCK1_START 0x50000
-#define IRAM_SHORT_BLOCK1_END 0x7ffff
-#define IOP_REGISTER_START 0x00000
-#define IOP_REGISTER_END 0x000ff
-#define IRAM_END 0x7ffff
+#define REG(reg) m_regmap[reg]
+#define DM_I(reg) mem(&m_core->dag1.i[reg])
+#define DM_M(reg) mem(&m_core->dag1.m[reg])
+#define DM_L(reg) mem(&m_core->dag1.l[reg])
+#define DM_B(reg) mem(&m_core->dag1.b[reg])
+#define PM_I(reg) mem(&m_core->dag2.i[reg])
+#define PM_M(reg) mem(&m_core->dag2.m[reg])
+#define PM_L(reg) mem(&m_core->dag2.l[reg])
+#define PM_B(reg) mem(&m_core->dag2.b[reg])
+#define ASTAT_AZ mem(&m_core->astat_drc.az)
+#define ASTAT_AV mem(&m_core->astat_drc.av)
+#define ASTAT_AN mem(&m_core->astat_drc.an)
+#define ASTAT_AC mem(&m_core->astat_drc.ac)
+#define ASTAT_AS mem(&m_core->astat_drc.as)
+#define ASTAT_AI mem(&m_core->astat_drc.ai)
+#define ASTAT_AF mem(&m_core->astat_drc.af)
+#define ASTAT_MN mem(&m_core->astat_drc.mn)
+#define ASTAT_MV mem(&m_core->astat_drc.mv)
+#define ASTAT_MU mem(&m_core->astat_drc.mu)
+#define ASTAT_MI mem(&m_core->astat_drc.mi)
+#define ASTAT_SV mem(&m_core->astat_drc.sv)
+#define ASTAT_SZ mem(&m_core->astat_drc.sz)
+#define ASTAT_SS mem(&m_core->astat_drc.ss)
+#define ASTAT_BTF mem(&m_core->astat_drc.btf)
+#define FLAG0 mem(&m_core->flag[0])
+#define FLAG1 mem(&m_core->flag[1])
+#define FLAG2 mem(&m_core->flag[2])
+#define FLAG3 mem(&m_core->flag[3])
+#define CURLCNTR mem(&m_core->curlcntr)
+#define LCNTR mem(&m_core->lcntr)
+#define PCSTK mem(&m_core->pcstk)
+#define PCSTKP mem(&m_core->pcstkp)
+#define STKY mem(&m_core->stky)
+#define LSTKP mem(&m_core->lstkp)
+#define USTAT1 mem(&m_core->ustat1)
+#define USTAT2 mem(&m_core->ustat2)
+#define IRPTL mem(&m_core->irptl)
+#define MODE1 mem(&m_core->mode1)
+#define MODE2 mem(&m_core->mode2)
+#define IMASK mem(&m_core->imask)
+#define IMASKP mem(&m_core->imaskp)
+#define MRF mem(&m_core->mrf)
+#define MRB mem(&m_core->mrb)
+
+#define AZ_CALC_REQUIRED ((desc->regreq[0] & 0x00010000) || desc->flags & OPFLAG_IN_DELAY_SLOT)
+#define AV_CALC_REQUIRED ((desc->regreq[0] & 0x00020000) || desc->flags & OPFLAG_IN_DELAY_SLOT)
+#define AN_CALC_REQUIRED ((desc->regreq[0] & 0x00040000) || desc->flags & OPFLAG_IN_DELAY_SLOT)
+#define AC_CALC_REQUIRED ((desc->regreq[0] & 0x00080000) || desc->flags & OPFLAG_IN_DELAY_SLOT)
+#define AS_CALC_REQUIRED ((desc->regreq[0] & 0x00100000) || desc->flags & OPFLAG_IN_DELAY_SLOT)
+#define AI_CALC_REQUIRED ((desc->regreq[0] & 0x00200000) || desc->flags & OPFLAG_IN_DELAY_SLOT)
+#define MN_CALC_REQUIRED ((desc->regreq[0] & 0x00400000) || desc->flags & OPFLAG_IN_DELAY_SLOT)
+#define MV_CALC_REQUIRED ((desc->regreq[0] & 0x00800000) || desc->flags & OPFLAG_IN_DELAY_SLOT)
+#define MU_CALC_REQUIRED ((desc->regreq[0] & 0x01000000) || desc->flags & OPFLAG_IN_DELAY_SLOT)
+#define MI_CALC_REQUIRED ((desc->regreq[0] & 0x02000000) || desc->flags & OPFLAG_IN_DELAY_SLOT)
+#define SV_CALC_REQUIRED ((desc->regreq[0] & 0x04000000) || desc->flags & OPFLAG_IN_DELAY_SLOT)
+#define SZ_CALC_REQUIRED ((desc->regreq[0] & 0x08000000) || desc->flags & OPFLAG_IN_DELAY_SLOT)
+#define SS_CALC_REQUIRED ((desc->regreq[0] & 0x10000000) || desc->flags & OPFLAG_IN_DELAY_SLOT)
+#define BTF_CALC_REQUIRED ((desc->regreq[0] & 0x20000000) || desc->flags & OPFLAG_IN_DELAY_SLOT)
+#define AF_CALC_REQUIRED ((desc->regreq[0] & 0x40000000) || desc->flags & OPFLAG_IN_DELAY_SLOT)
+
+
+#define IRAM_BLOCK0_START 0x20000
+#define IRAM_BLOCK0_END 0x27fff
+#define IRAM_BLOCK1_START 0x28000
+#define IRAM_BLOCK1_END 0x3ffff
+#define IRAM_SHORT_BLOCK0_START 0x40000
+#define IRAM_SHORT_BLOCK0_END 0x4ffff
+#define IRAM_SHORT_BLOCK1_START 0x50000
+#define IRAM_SHORT_BLOCK1_END 0x7ffff
+#define IOP_REGISTER_START 0x00000
+#define IOP_REGISTER_END 0x000ff
+#define IRAM_END 0x7ffff
inline void adsp21062_device::alloc_handle(drcuml_state *drcuml, code_handle **handleptr, const char *name)
@@ -267,26 +267,26 @@ UINT32 adsp21062_device::do_condition_astat_bits(int condition)
UINT32 r = 0;
switch (condition)
{
- case 0x00: r = AZ; break; // EQ
- case 0x01: r = AZ | AN; break; // LT
- case 0x02: r = AZ | AN; break; // LE
- case 0x03: r = AC; break; // AC
- case 0x04: r = AV; break; // AV
- case 0x05: r = MV; break; // MV
- case 0x06: r = MN; break; // MS
- case 0x07: r = SV; break; // SV
- case 0x08: r = SZ; break; // SZ
- case 0x0d: r = BTF; break; // TF
- case 0x10: r = AZ; break; // NOT EQUAL
- case 0x11: r = AZ | AN; break; // GE
- case 0x12: r = AZ | AN; break; // GT
- case 0x13: r = AC; break; // NOT AC
- case 0x14: r = AV; break; // NOT AV
- case 0x15: r = MV; break; // NOT MV
- case 0x16: r = MN; break; // NOT MS
- case 0x17: r = SV; break; // NOT SV
- case 0x18: r = SZ; break; // NOT SZ
- case 0x1d: r = BTF; break; // NOT TF
+ case 0x00: r = AZ; break; // EQ
+ case 0x01: r = AZ | AN; break; // LT
+ case 0x02: r = AZ | AN; break; // LE
+ case 0x03: r = AC; break; // AC
+ case 0x04: r = AV; break; // AV
+ case 0x05: r = MV; break; // MV
+ case 0x06: r = MN; break; // MS
+ case 0x07: r = SV; break; // SV
+ case 0x08: r = SZ; break; // SZ
+ case 0x0d: r = BTF; break; // TF
+ case 0x10: r = AZ; break; // NOT EQUAL
+ case 0x11: r = AZ | AN; break; // GE
+ case 0x12: r = AZ | AN; break; // GT
+ case 0x13: r = AC; break; // NOT AC
+ case 0x14: r = AV; break; // NOT AV
+ case 0x15: r = MV; break; // NOT MV
+ case 0x16: r = MN; break; // NOT MS
+ case 0x17: r = SV; break; // NOT SV
+ case 0x18: r = SZ; break; // NOT SZ
+ case 0x1d: r = BTF; break; // NOT TF
}
return r;
@@ -354,220 +354,220 @@ void adsp21062_device::static_generate_memory_accessor(MEM_ACCESSOR_TYPE type, c
switch (type)
{
case MEM_ACCESSOR_PM_READ48:
- UML_CMP(block, I1, IRAM_BLOCK0_START); // cmp i1,IRAM_BLOCK0_START
- UML_JMPc(block, COND_B, label); // jb label1
- UML_CMP(block, I1, IRAM_BLOCK0_END); // cmp i1,IRAM_BLOCK0_END
- UML_JMPc(block, COND_A, label); // ja label1
-
+ UML_CMP(block, I1, IRAM_BLOCK0_START); // cmp i1,IRAM_BLOCK0_START
+ UML_JMPc(block, COND_B, label); // jb label1
+ UML_CMP(block, I1, IRAM_BLOCK0_END); // cmp i1,IRAM_BLOCK0_END
+ UML_JMPc(block, COND_A, label); // ja label1
+
// 0x20000 ... 0x27fff
- UML_AND(block, I1, I1, 0x7fff); // and i1,i1,0x7fff
- UML_MULS(block, I1, I1, I1, 3); // muls i1,3
- UML_DLOAD(block, I0, block0, I1, SIZE_WORD, SCALE_x2); // dload i0,[block0],i1,word,scale_x2
- UML_DSHL(block, I0, I0, 32); // dshl i0,i0,32
- UML_DLOAD(block, I2, block0_1, I1, SIZE_WORD, SCALE_x2); // dload i2,[block0_1],i1,word,scale_x2
- UML_DSHL(block, I2, I2, 16); // dshl i2,i2,16
- UML_DOR(block, I0, I0, I2); // dor i0,i0,i2
- UML_DLOAD(block, I2, block0_2, I1, SIZE_WORD, SCALE_x2); // dload i2,[block0_2],i1,word,scale_x2
- UML_DOR(block, I0, I0, I2); // dor i0,i0,i2
- UML_RET(block); // ret
-
- UML_LABEL(block, label++); // label1:
- UML_CMP(block, I1, IRAM_BLOCK1_START); // cmp i1,IRAM_BLOCK1_START
- UML_JMPc(block, COND_B, label); // jb label2
- UML_CMP(block, I1, IRAM_BLOCK1_END); // cmp i1,IRAM_BLOCK1_END
- UML_JMPc(block, COND_A, label); // ja label2
+ UML_AND(block, I1, I1, 0x7fff); // and i1,i1,0x7fff
+ UML_MULS(block, I1, I1, I1, 3); // muls i1,3
+ UML_DLOAD(block, I0, block0, I1, SIZE_WORD, SCALE_x2); // dload i0,[block0],i1,word,scale_x2
+ UML_DSHL(block, I0, I0, 32); // dshl i0,i0,32
+ UML_DLOAD(block, I2, block0_1, I1, SIZE_WORD, SCALE_x2); // dload i2,[block0_1],i1,word,scale_x2
+ UML_DSHL(block, I2, I2, 16); // dshl i2,i2,16
+ UML_DOR(block, I0, I0, I2); // dor i0,i0,i2
+ UML_DLOAD(block, I2, block0_2, I1, SIZE_WORD, SCALE_x2); // dload i2,[block0_2],i1,word,scale_x2
+ UML_DOR(block, I0, I0, I2); // dor i0,i0,i2
+ UML_RET(block); // ret
+
+ UML_LABEL(block, label++); // label1:
+ UML_CMP(block, I1, IRAM_BLOCK1_START); // cmp i1,IRAM_BLOCK1_START
+ UML_JMPc(block, COND_B, label); // jb label2
+ UML_CMP(block, I1, IRAM_BLOCK1_END); // cmp i1,IRAM_BLOCK1_END
+ UML_JMPc(block, COND_A, label); // ja label2
// 0x28000 ... 0x3ffff
- UML_AND(block, I1, I1, 0x7fff); // and i1,i1,0x7fff (block 1 is mirrored in 0x28000...2ffff, 0x30000...0x37fff and 0x38000...3ffff)
- UML_MULS(block, I1, I1, I1, 3); // muls i1,3
- UML_DLOAD(block, I0, block1, I1, SIZE_WORD, SCALE_x2); // dload i0,[block1],i1,word,scale_x2
- UML_DSHL(block, I0, I0, 32); // dshl i0,i0,32
- UML_DLOAD(block, I2, block1_1, I1, SIZE_WORD, SCALE_x2); // dload i2,[block1_1],i1,word,scale_x2
- UML_DSHL(block, I2, I2, 16); // dshl i2,i2,16
- UML_DOR(block, I0, I0, I2); // dor i0,i0,i2
- UML_DLOAD(block, I2, block1_2, I1, SIZE_WORD, SCALE_x2); // dload i2,[block1_2],i1,word,scale_x2
- UML_DOR(block, I0, I0, I2); // dor i0,i0,i2
- UML_RET(block); // ret
-
- UML_LABEL(block, label++); // label2:
+ UML_AND(block, I1, I1, 0x7fff); // and i1,i1,0x7fff (block 1 is mirrored in 0x28000...2ffff, 0x30000...0x37fff and 0x38000...3ffff)
+ UML_MULS(block, I1, I1, I1, 3); // muls i1,3
+ UML_DLOAD(block, I0, block1, I1, SIZE_WORD, SCALE_x2); // dload i0,[block1],i1,word,scale_x2
+ UML_DSHL(block, I0, I0, 32); // dshl i0,i0,32
+ UML_DLOAD(block, I2, block1_1, I1, SIZE_WORD, SCALE_x2); // dload i2,[block1_1],i1,word,scale_x2
+ UML_DSHL(block, I2, I2, 16); // dshl i2,i2,16
+ UML_DOR(block, I0, I0, I2); // dor i0,i0,i2
+ UML_DLOAD(block, I2, block1_2, I1, SIZE_WORD, SCALE_x2); // dload i2,[block1_2],i1,word,scale_x2
+ UML_DOR(block, I0, I0, I2); // dor i0,i0,i2
+ UML_RET(block); // ret
+
+ UML_LABEL(block, label++); // label2:
break;
case MEM_ACCESSOR_PM_WRITE48:
- UML_CMP(block, I1, IRAM_BLOCK0_START); // cmp i1,IRAM_BLOCK0_START
- UML_JMPc(block, COND_B, label); // jb label1
- UML_CMP(block, I1, IRAM_BLOCK0_END); // cmp i1,IRAM_BLOCK0_END
- UML_JMPc(block, COND_A, label); // ja label1
+ UML_CMP(block, I1, IRAM_BLOCK0_START); // cmp i1,IRAM_BLOCK0_START
+ UML_JMPc(block, COND_B, label); // jb label1
+ UML_CMP(block, I1, IRAM_BLOCK0_END); // cmp i1,IRAM_BLOCK0_END
+ UML_JMPc(block, COND_A, label); // ja label1
// 0x20000 ... 0x27fff
- UML_AND(block, I1, I1, 0x7fff); // and i1,i1,0x7fff
- UML_MULS(block, I1, I1, I1, 3); // muls i1,3
- UML_DSTORE(block, block0_2, I1, I0, SIZE_WORD, SCALE_x2); // dstore [block0_2],i1,i0,word,scale_x2
- UML_DSHR(block, I0, I0, 16); // dshr i0,i0,16
- UML_DSTORE(block, block0_1, I1, I0, SIZE_WORD, SCALE_x2); // dstore [block0_1],i1,i0,word,scale_x2
- UML_DSHR(block, I0, I0, 16); // dshr i0,i0,16
- UML_DSTORE(block, block0, I1, I0, SIZE_WORD, SCALE_x2); // dstore [block0],i1,i0,word,scale_x2
+ UML_AND(block, I1, I1, 0x7fff); // and i1,i1,0x7fff
+ UML_MULS(block, I1, I1, I1, 3); // muls i1,3
+ UML_DSTORE(block, block0_2, I1, I0, SIZE_WORD, SCALE_x2); // dstore [block0_2],i1,i0,word,scale_x2
+ UML_DSHR(block, I0, I0, 16); // dshr i0,i0,16
+ UML_DSTORE(block, block0_1, I1, I0, SIZE_WORD, SCALE_x2); // dstore [block0_1],i1,i0,word,scale_x2
+ UML_DSHR(block, I0, I0, 16); // dshr i0,i0,16
+ UML_DSTORE(block, block0, I1, I0, SIZE_WORD, SCALE_x2); // dstore [block0],i1,i0,word,scale_x2
UML_MOV(block, mem(&m_core->force_recompile), 1);
- UML_RET(block); // ret
+ UML_RET(block); // ret
- UML_LABEL(block, label++); // label1:
- UML_CMP(block, I1, IRAM_BLOCK1_START); // cmp i1,IRAM_BLOCK1_START
- UML_JMPc(block, COND_B, label); // jb label2
- UML_CMP(block, I1, IRAM_BLOCK1_END); // cmp i1,IRAM_BLOCK1_END
- UML_JMPc(block, COND_A, label); // ja label2
+ UML_LABEL(block, label++); // label1:
+ UML_CMP(block, I1, IRAM_BLOCK1_START); // cmp i1,IRAM_BLOCK1_START
+ UML_JMPc(block, COND_B, label); // jb label2
+ UML_CMP(block, I1, IRAM_BLOCK1_END); // cmp i1,IRAM_BLOCK1_END
+ UML_JMPc(block, COND_A, label); // ja label2
// 0x28000 ... 0x3ffff
- UML_AND(block, I1, I1, 0x7fff); // and i1,i1,0x7fff (block 1 is mirrored in 0x28000...2ffff, 0x30000...0x37fff and 0x38000...3ffff)
- UML_MULS(block, I1, I1, I1, 3); // muls i1,3
- UML_DSTORE(block, block1_2, I1, I0, SIZE_WORD, SCALE_x2); // dstore [block1_2],i1,i0,word,scale_x2
- UML_DSHR(block, I0, I0, 16); // dshr i0,i0,16
- UML_DSTORE(block, block1_1, I1, I0, SIZE_WORD, SCALE_x2); // dstore [block1_1],i1,i0,word,scale_x2
- UML_DSHR(block, I0, I0, 16); // dshr i0,i0,16
- UML_DSTORE(block, block1, I1, I0, SIZE_WORD, SCALE_x2); // dstore [block1],i1,i0,word,scale_x2
- UML_RET(block); // ret
-
- UML_LABEL(block, label++); // label2:
+ UML_AND(block, I1, I1, 0x7fff); // and i1,i1,0x7fff (block 1 is mirrored in 0x28000...2ffff, 0x30000...0x37fff and 0x38000...3ffff)
+ UML_MULS(block, I1, I1, I1, 3); // muls i1,3
+ UML_DSTORE(block, block1_2, I1, I0, SIZE_WORD, SCALE_x2); // dstore [block1_2],i1,i0,word,scale_x2
+ UML_DSHR(block, I0, I0, 16); // dshr i0,i0,16
+ UML_DSTORE(block, block1_1, I1, I0, SIZE_WORD, SCALE_x2); // dstore [block1_1],i1,i0,word,scale_x2
+ UML_DSHR(block, I0, I0, 16); // dshr i0,i0,16
+ UML_DSTORE(block, block1, I1, I0, SIZE_WORD, SCALE_x2); // dstore [block1],i1,i0,word,scale_x2
+ UML_RET(block); // ret
+
+ UML_LABEL(block, label++); // label2:
break;
case MEM_ACCESSOR_PM_READ32:
- UML_CMP(block, I1, IRAM_BLOCK0_START); // cmp i1,IRAM_BLOCK0_START
- UML_JMPc(block, COND_B, label); // jb label1
- UML_CMP(block, I1, IRAM_BLOCK0_END); // cmp i1,IRAM_BLOCK0_END
- UML_JMPc(block, COND_A, label); // ja label1
-
+ UML_CMP(block, I1, IRAM_BLOCK0_START); // cmp i1,IRAM_BLOCK0_START
+ UML_JMPc(block, COND_B, label); // jb label1
+ UML_CMP(block, I1, IRAM_BLOCK0_END); // cmp i1,IRAM_BLOCK0_END
+ UML_JMPc(block, COND_A, label); // ja label1
+
// 0x20000 ... 0x27fff
- UML_AND(block, I1, I1, 0x7fff); // and i1,i1,0x7fff
- UML_MULS(block, I1, I1, I1, 3); // muls i1,3
- UML_LOAD(block, I0, block0, I1, SIZE_WORD, SCALE_x2); // load i0,[block0],i1,word,scale_x2
- UML_SHL(block, I0, I0, 16); // shl i0,i0,16
- UML_LOAD(block, I2, block0_1, I1, SIZE_WORD, SCALE_x2); // load i2,[block0_1],i1,word,scale_x2
- UML_OR(block, I0, I0, I2); // or i0,i0,i2
- UML_RET(block); // ret
-
- UML_LABEL(block, label++); // label1:
- UML_CMP(block, I1, IRAM_BLOCK1_START); // cmp i1,IRAM_BLOCK1_START
- UML_JMPc(block, COND_B, label); // jb label2
- UML_CMP(block, I1, IRAM_BLOCK1_END); // cmp i1,IRAM_BLOCK1_END
- UML_JMPc(block, COND_A, label); // ja label2
+ UML_AND(block, I1, I1, 0x7fff); // and i1,i1,0x7fff
+ UML_MULS(block, I1, I1, I1, 3); // muls i1,3
+ UML_LOAD(block, I0, block0, I1, SIZE_WORD, SCALE_x2); // load i0,[block0],i1,word,scale_x2
+ UML_SHL(block, I0, I0, 16); // shl i0,i0,16
+ UML_LOAD(block, I2, block0_1, I1, SIZE_WORD, SCALE_x2); // load i2,[block0_1],i1,word,scale_x2
+ UML_OR(block, I0, I0, I2); // or i0,i0,i2
+ UML_RET(block); // ret
+
+ UML_LABEL(block, label++); // label1:
+ UML_CMP(block, I1, IRAM_BLOCK1_START); // cmp i1,IRAM_BLOCK1_START
+ UML_JMPc(block, COND_B, label); // jb label2
+ UML_CMP(block, I1, IRAM_BLOCK1_END); // cmp i1,IRAM_BLOCK1_END
+ UML_JMPc(block, COND_A, label); // ja label2
// 0x28000 ... 0x3ffff
- UML_AND(block, I1, I1, 0x7fff); // and i1,i1,0x7fff (block 1 is mirrored in 0x28000...2ffff, 0x30000...0x37fff and 0x38000...3ffff)
- UML_MULS(block, I1, I1, I1, 3); // muls i1,3
- UML_LOAD(block, I0, block1, I1, SIZE_WORD, SCALE_x2); // load i0,[block1],i1,word,scale_x2
- UML_SHL(block, I0, I0, 16); // shl i0,i0,16
- UML_LOAD(block, I2, block1_1, I1, SIZE_WORD, SCALE_x2); // load i2,[block1_1],i1,word,scale_x2
- UML_OR(block, I0, I0, I2); // or i0,i0,i2
- UML_RET(block); // ret
-
- UML_LABEL(block, label++); // label2:
+ UML_AND(block, I1, I1, 0x7fff); // and i1,i1,0x7fff (block 1 is mirrored in 0x28000...2ffff, 0x30000...0x37fff and 0x38000...3ffff)
+ UML_MULS(block, I1, I1, I1, 3); // muls i1,3
+ UML_LOAD(block, I0, block1, I1, SIZE_WORD, SCALE_x2); // load i0,[block1],i1,word,scale_x2
+ UML_SHL(block, I0, I0, 16); // shl i0,i0,16
+ UML_LOAD(block, I2, block1_1, I1, SIZE_WORD, SCALE_x2); // load i2,[block1_1],i1,word,scale_x2
+ UML_OR(block, I0, I0, I2); // or i0,i0,i2
+ UML_RET(block); // ret
+
+ UML_LABEL(block, label++); // label2:
break;
case MEM_ACCESSOR_PM_WRITE32:
- UML_CMP(block, I1, IRAM_BLOCK0_START); // cmp i1,IRAM_BLOCK0_START
- UML_JMPc(block, COND_B, label); // jb label1
- UML_CMP(block, I1, IRAM_BLOCK0_END); // cmp i1,IRAM_BLOCK0_END
- UML_JMPc(block, COND_A, label); // ja label1
+ UML_CMP(block, I1, IRAM_BLOCK0_START); // cmp i1,IRAM_BLOCK0_START
+ UML_JMPc(block, COND_B, label); // jb label1
+ UML_CMP(block, I1, IRAM_BLOCK0_END); // cmp i1,IRAM_BLOCK0_END
+ UML_JMPc(block, COND_A, label); // ja label1
// 0x20000 ... 0x27fff
- UML_AND(block, I1, I1, 0x7fff); // and i1,i1,0x7fff
- UML_MULS(block, I1, I1, I1, 3); // muls i1,3
- UML_STORE(block, block0_1, I1, I0, SIZE_WORD, SCALE_x2); // store [block0_1],i1,i0,word,scale_x2
- UML_SHR(block, I0, I0, 16); // shr i0,i0,16
- UML_STORE(block, block0, I1, I0, SIZE_WORD, SCALE_x2); // store [block0],i1,i0,word,scale_x2
- UML_RET(block); // ret
-
- UML_LABEL(block, label++); // label1:
- UML_CMP(block, I1, IRAM_BLOCK1_START); // cmp i1,IRAM_BLOCK1_START
- UML_JMPc(block, COND_B, label); // jb label2
- UML_CMP(block, I1, IRAM_BLOCK1_END); // cmp i1,IRAM_BLOCK1_END
- UML_JMPc(block, COND_A, label); // ja label2
+ UML_AND(block, I1, I1, 0x7fff); // and i1,i1,0x7fff
+ UML_MULS(block, I1, I1, I1, 3); // muls i1,3
+ UML_STORE(block, block0_1, I1, I0, SIZE_WORD, SCALE_x2); // store [block0_1],i1,i0,word,scale_x2
+ UML_SHR(block, I0, I0, 16); // shr i0,i0,16
+ UML_STORE(block, block0, I1, I0, SIZE_WORD, SCALE_x2); // store [block0],i1,i0,word,scale_x2
+ UML_RET(block); // ret
+
+ UML_LABEL(block, label++); // label1:
+ UML_CMP(block, I1, IRAM_BLOCK1_START); // cmp i1,IRAM_BLOCK1_START
+ UML_JMPc(block, COND_B, label); // jb label2
+ UML_CMP(block, I1, IRAM_BLOCK1_END); // cmp i1,IRAM_BLOCK1_END
+ UML_JMPc(block, COND_A, label); // ja label2
// 0x28000 ... 0x3ffff
- UML_AND(block, I1, I1, 0x7fff); // and i1,i1,0x7fff (block 1 is mirrored in 0x28000...2ffff, 0x30000...0x37fff and 0x38000...3ffff)
- UML_MULS(block, I1, I1, I1, 3); // muls i1,3
- UML_STORE(block, block1_1, I1, I0, SIZE_WORD, SCALE_x2); // store [block1_1],i1,i0,word,scale_x2
- UML_SHR(block, I0, I0, 16); // shr i0,i0,16
- UML_STORE(block, block1, I1, I0, SIZE_WORD, SCALE_x2); // store [block1],i1,i0,word,scale_x2
- UML_RET(block); // ret
-
- UML_LABEL(block, label++); // label2:
+ UML_AND(block, I1, I1, 0x7fff); // and i1,i1,0x7fff (block 1 is mirrored in 0x28000...2ffff, 0x30000...0x37fff and 0x38000...3ffff)
+ UML_MULS(block, I1, I1, I1, 3); // muls i1,3
+ UML_STORE(block, block1_1, I1, I0, SIZE_WORD, SCALE_x2); // store [block1_1],i1,i0,word,scale_x2
+ UML_SHR(block, I0, I0, 16); // shr i0,i0,16
+ UML_STORE(block, block1, I1, I0, SIZE_WORD, SCALE_x2); // store [block1],i1,i0,word,scale_x2
+ UML_RET(block); // ret
+
+ UML_LABEL(block, label++); // label2:
break;
case MEM_ACCESSOR_DM_READ32:
- UML_CMP(block, I1, IRAM_END); // cmp i1,IRAM_END
- UML_JMPc(block, COND_BE, label); // jbe label1
+ UML_CMP(block, I1, IRAM_END); // cmp i1,IRAM_END
+ UML_JMPc(block, COND_BE, label); // jbe label1
// 0x80000 ...
- UML_SHL(block, I1, I1, 2); // shl i1,i1,2
- UML_READ(block, I0, I1, SIZE_DWORD, SPACE_DATA); // read i0,i1,dword,SPACE_DATA
+ UML_SHL(block, I1, I1, 2); // shl i1,i1,2
+ UML_READ(block, I0, I1, SIZE_DWORD, SPACE_DATA); // read i0,i1,dword,SPACE_DATA
UML_RET(block);
- UML_LABEL(block, label++); // label1:
- UML_CMP(block, I1, IRAM_BLOCK0_START); // cmp i1,IRAM_BLOCK0_START
- UML_JMPc(block, COND_B, label); // jb label2
- UML_CMP(block, I1, IRAM_BLOCK0_END); // cmp i1,IRAM_BLOCK0_END
- UML_JMPc(block, COND_A, label); // ja label2
+ UML_LABEL(block, label++); // label1:
+ UML_CMP(block, I1, IRAM_BLOCK0_START); // cmp i1,IRAM_BLOCK0_START
+ UML_JMPc(block, COND_B, label); // jb label2
+ UML_CMP(block, I1, IRAM_BLOCK0_END); // cmp i1,IRAM_BLOCK0_END
+ UML_JMPc(block, COND_A, label); // ja label2
// 0x20000 ... 0x27fff
- UML_AND(block, I1, I1, 0x7fff); // and i1,i1,0x7fff
- UML_LOAD(block, I0, block0, I1, SIZE_WORD, SCALE_x4); // load i0,[block0],i1,word,scale_x4
- UML_SHL(block, I0, I0, 16); // shl i0,i0,16
- UML_LOAD(block, I2, block0_1, I1, SIZE_WORD, SCALE_x4); // load i2,[block0_1],i1,word,scale_x4
- UML_OR(block, I0, I0, I2); // or i0,i0,i2
+ UML_AND(block, I1, I1, 0x7fff); // and i1,i1,0x7fff
+ UML_LOAD(block, I0, block0, I1, SIZE_WORD, SCALE_x4); // load i0,[block0],i1,word,scale_x4
+ UML_SHL(block, I0, I0, 16); // shl i0,i0,16
+ UML_LOAD(block, I2, block0_1, I1, SIZE_WORD, SCALE_x4); // load i2,[block0_1],i1,word,scale_x4
+ UML_OR(block, I0, I0, I2); // or i0,i0,i2
UML_RET(block);
- UML_LABEL(block, label++); // label2:
- UML_CMP(block, I1, IRAM_BLOCK1_START); // cmp i1,IRAM_BLOCK1_START
- UML_JMPc(block, COND_B, label); // jb label3
- UML_CMP(block, I1, IRAM_BLOCK1_END); // cmp i1,IRAM_BLOCK1_END
- UML_JMPc(block, COND_A, label); // ja label3
+ UML_LABEL(block, label++); // label2:
+ UML_CMP(block, I1, IRAM_BLOCK1_START); // cmp i1,IRAM_BLOCK1_START
+ UML_JMPc(block, COND_B, label); // jb label3
+ UML_CMP(block, I1, IRAM_BLOCK1_END); // cmp i1,IRAM_BLOCK1_END
+ UML_JMPc(block, COND_A, label); // ja label3
// 0x28000 ... 0x3ffff
- UML_AND(block, I1, I1, 0x7fff); // and i1,i1,0x7fff
- UML_LOAD(block, I0, block1, I1, SIZE_WORD, SCALE_x4); // load i0,[block1],i1,word,scale_x4
- UML_SHL(block, I0, I0, 16); // shl i0,i0,16
- UML_LOAD(block, I2, block1_1, I1, SIZE_WORD, SCALE_x4); // load i2,[block1_1],i1,word,scale_x4
- UML_OR(block, I0, I0, I2); // or i0,i0,i2
+ UML_AND(block, I1, I1, 0x7fff); // and i1,i1,0x7fff
+ UML_LOAD(block, I0, block1, I1, SIZE_WORD, SCALE_x4); // load i0,[block1],i1,word,scale_x4
+ UML_SHL(block, I0, I0, 16); // shl i0,i0,16
+ UML_LOAD(block, I2, block1_1, I1, SIZE_WORD, SCALE_x4); // load i2,[block1_1],i1,word,scale_x4
+ UML_OR(block, I0, I0, I2); // or i0,i0,i2
UML_RET(block);
- UML_LABEL(block, label++); // Label3:
- UML_CMP(block, I1, IOP_REGISTER_END); // cmp i1,IOP_REGISTER_END
- UML_JMPc(block, COND_A, label); // ja label4
+ UML_LABEL(block, label++); // Label3:
+ UML_CMP(block, I1, IOP_REGISTER_END); // cmp i1,IOP_REGISTER_END
+ UML_JMPc(block, COND_A, label); // ja label4
// IOP registers
- UML_MOV(block, mem(&m_core->arg0), I1); // mov [m_core->arg0],i1
- UML_CALLC(block, cfunc_read_iop, this); // callc cfunc_read_iop
- UML_MOV(block, I0, mem(&m_core->arg1)); // mov i0,[m_core->arg1]
+ UML_MOV(block, mem(&m_core->arg0), I1); // mov [m_core->arg0],i1
+ UML_CALLC(block, cfunc_read_iop, this); // callc cfunc_read_iop
+ UML_MOV(block, I0, mem(&m_core->arg1)); // mov i0,[m_core->arg1]
UML_RET(block);
- UML_LABEL(block, label++); // label4:
- UML_CMP(block, I1, IRAM_SHORT_BLOCK0_START); // cmp i1,IRAM_SHORT_BLOCK0_START
- UML_JMPc(block, COND_B, label+1); // jb label6
- UML_CMP(block, I1, IRAM_SHORT_BLOCK0_END); // cmp i1,IRAM_SHORT_BLOCK0_END
- UML_JMPc(block, COND_A, label+1); // ja label6
+ UML_LABEL(block, label++); // label4:
+ UML_CMP(block, I1, IRAM_SHORT_BLOCK0_START); // cmp i1,IRAM_SHORT_BLOCK0_START
+ UML_JMPc(block, COND_B, label+1); // jb label6
+ UML_CMP(block, I1, IRAM_SHORT_BLOCK0_END); // cmp i1,IRAM_SHORT_BLOCK0_END
+ UML_JMPc(block, COND_A, label+1); // ja label6
// 0x40000 ... 0x4ffff
- UML_AND(block, I1, I1, 0xffff); // and i1,i1,0xffff
- UML_XOR(block, I1, I1, 1); // xor i1,i1,1
- UML_TEST(block, mem(&m_core->mode1), 0x4000); // test [m_core->mode1],0x4000
- UML_JMPc(block, COND_Z, label); // jz label5
- UML_LOADS(block, I0, block0, I1, SIZE_WORD, SCALE_x2); // loads i0,[block0],i1,word,scale_x2
+ UML_AND(block, I1, I1, 0xffff); // and i1,i1,0xffff
+ UML_XOR(block, I1, I1, 1); // xor i1,i1,1
+ UML_TEST(block, mem(&m_core->mode1), 0x4000); // test [m_core->mode1],0x4000
+ UML_JMPc(block, COND_Z, label); // jz label5
+ UML_LOADS(block, I0, block0, I1, SIZE_WORD, SCALE_x2); // loads i0,[block0],i1,word,scale_x2
UML_RET(block);
- UML_LABEL(block, label++); // label5:
- UML_LOAD(block, I0, block0, I1, SIZE_WORD, SCALE_x2); // load i0,[block0],i1,word,scale_x2
+ UML_LABEL(block, label++); // label5:
+ UML_LOAD(block, I0, block0, I1, SIZE_WORD, SCALE_x2); // load i0,[block0],i1,word,scale_x2
UML_RET(block);
- UML_LABEL(block, label++); // label6:
- UML_CMP(block, I1, IRAM_SHORT_BLOCK1_START); // cmp i1,IRAM_SHORT_BLOCK1_START
- UML_JMPc(block, COND_B, label+1); // jb label8
- UML_CMP(block, I1, IRAM_SHORT_BLOCK1_END); // cmp i1,IRAM_SHORT_BLOCK1_END
- UML_JMPc(block, COND_A, label+1); // ja label8
+ UML_LABEL(block, label++); // label6:
+ UML_CMP(block, I1, IRAM_SHORT_BLOCK1_START); // cmp i1,IRAM_SHORT_BLOCK1_START
+ UML_JMPc(block, COND_B, label+1); // jb label8
+ UML_CMP(block, I1, IRAM_SHORT_BLOCK1_END); // cmp i1,IRAM_SHORT_BLOCK1_END
+ UML_JMPc(block, COND_A, label+1); // ja label8
// 0x50000 ... 0x7ffff
- UML_AND(block, I1, I1, 0xffff); // and i1,i1,0xffff
- UML_XOR(block, I1, I1, 1); // xor i1,i1,1
- UML_TEST(block, mem(&m_core->mode1), 0x4000); // test [m_core->mode1],0x4000
- UML_JMPc(block, COND_Z, label); // jz label7
- UML_LOADS(block, I0, block1, I1, SIZE_WORD, SCALE_x2); // loads i0,[block1],i1,word,scale_x2
+ UML_AND(block, I1, I1, 0xffff); // and i1,i1,0xffff
+ UML_XOR(block, I1, I1, 1); // xor i1,i1,1
+ UML_TEST(block, mem(&m_core->mode1), 0x4000); // test [m_core->mode1],0x4000
+ UML_JMPc(block, COND_Z, label); // jz label7
+ UML_LOADS(block, I0, block1, I1, SIZE_WORD, SCALE_x2); // loads i0,[block1],i1,word,scale_x2
UML_RET(block);
- UML_LABEL(block, label++); // label7:
- UML_LOAD(block, I0, block1, I1, SIZE_WORD, SCALE_x2); // load i0,[block1],i1,word,scale_x2
+ UML_LABEL(block, label++); // label7:
+ UML_LOAD(block, I0, block1, I1, SIZE_WORD, SCALE_x2); // load i0,[block1],i1,word,scale_x2
UML_RET(block);
- UML_LABEL(block, label++); // label8:
+ UML_LABEL(block, label++); // label8:
break;
case MEM_ACCESSOR_DM_WRITE32:
@@ -583,69 +583,69 @@ void adsp21062_device::static_generate_memory_accessor(MEM_ACCESSOR_TYPE type, c
#endif
- UML_CMP(block, I1, IRAM_END); // cmp i1,IRAM_END
- UML_JMPc(block, COND_BE, label); // jbe label1
+ UML_CMP(block, I1, IRAM_END); // cmp i1,IRAM_END
+ UML_JMPc(block, COND_BE, label); // jbe label1
// 0x80000 ...
- UML_SHL(block, I1, I1, 2); // shl i1,i1,2
- UML_WRITE(block, I1, I0, SIZE_DWORD, SPACE_DATA); // write i1,i0,dword,SPACE_DATA
+ UML_SHL(block, I1, I1, 2); // shl i1,i1,2
+ UML_WRITE(block, I1, I0, SIZE_DWORD, SPACE_DATA); // write i1,i0,dword,SPACE_DATA
UML_RET(block);
- UML_LABEL(block, label++); // label1:
- UML_CMP(block, I1, IRAM_BLOCK0_START); // cmp i1,IRAM_BLOCK0_START
- UML_JMPc(block, COND_B, label); // jb label2
- UML_CMP(block, I1, IRAM_BLOCK0_END); // cmp i1,IRAM_BLOCK0_END
- UML_JMPc(block, COND_A, label); // ja label2
+ UML_LABEL(block, label++); // label1:
+ UML_CMP(block, I1, IRAM_BLOCK0_START); // cmp i1,IRAM_BLOCK0_START
+ UML_JMPc(block, COND_B, label); // jb label2
+ UML_CMP(block, I1, IRAM_BLOCK0_END); // cmp i1,IRAM_BLOCK0_END
+ UML_JMPc(block, COND_A, label); // ja label2
// 0x20000 ... 0x27fff
- UML_AND(block, I1, I1, 0x7fff); // and i1,i1,0x7fff
- UML_STORE(block, block0_1, I1, I0, SIZE_WORD, SCALE_x4); // store [block0_1],i1,i0,word,scale_x4
- UML_SHR(block, I0, I0, 16); // shr i0,i0,16
- UML_STORE(block, block0, I1, I0, SIZE_WORD, SCALE_x4); // store [block0],i1,i0,word,scale_x4
+ UML_AND(block, I1, I1, 0x7fff); // and i1,i1,0x7fff
+ UML_STORE(block, block0_1, I1, I0, SIZE_WORD, SCALE_x4); // store [block0_1],i1,i0,word,scale_x4
+ UML_SHR(block, I0, I0, 16); // shr i0,i0,16
+ UML_STORE(block, block0, I1, I0, SIZE_WORD, SCALE_x4); // store [block0],i1,i0,word,scale_x4
UML_RET(block);
- UML_LABEL(block, label++); // label2:
- UML_CMP(block, I1, IRAM_BLOCK1_START); // cmp i1,IRAM_BLOCK1_START
- UML_JMPc(block, COND_B, label); // jb label3
- UML_CMP(block, I1, IRAM_BLOCK1_END); // cmp i1,IRAM_BLOCK1_END
- UML_JMPc(block, COND_A, label); // ja label3
+ UML_LABEL(block, label++); // label2:
+ UML_CMP(block, I1, IRAM_BLOCK1_START); // cmp i1,IRAM_BLOCK1_START
+ UML_JMPc(block, COND_B, label); // jb label3
+ UML_CMP(block, I1, IRAM_BLOCK1_END); // cmp i1,IRAM_BLOCK1_END
+ UML_JMPc(block, COND_A, label); // ja label3
// 0x28000 ... 0x3ffff
- UML_AND(block, I1, I1, 0x7fff); // and i1,i1,0x7fff
- UML_STORE(block, block1_1, I1, I0, SIZE_WORD, SCALE_x4); // store [block1_1],i1,i0,word,scale_x4
- UML_SHR(block, I0, I0, 16); // shr i0,i0,16
- UML_STORE(block, block1, I1, I0, SIZE_WORD, SCALE_x4); // store [block1],i1,i0,word,scale_x4
+ UML_AND(block, I1, I1, 0x7fff); // and i1,i1,0x7fff
+ UML_STORE(block, block1_1, I1, I0, SIZE_WORD, SCALE_x4); // store [block1_1],i1,i0,word,scale_x4
+ UML_SHR(block, I0, I0, 16); // shr i0,i0,16
+ UML_STORE(block, block1, I1, I0, SIZE_WORD, SCALE_x4); // store [block1],i1,i0,word,scale_x4
UML_RET(block);
- UML_LABEL(block, label++); // Label3:
- UML_CMP(block, I1, IOP_REGISTER_END); // cmp i1,IOP_REGISTER_END
- UML_JMPc(block, COND_A, label); // ja label4
+ UML_LABEL(block, label++); // Label3:
+ UML_CMP(block, I1, IOP_REGISTER_END); // cmp i1,IOP_REGISTER_END
+ UML_JMPc(block, COND_A, label); // ja label4
// IOP registers
- UML_MOV(block, mem(&m_core->arg0), I1); // mov [m_core->arg0],i1
- UML_MOV(block, mem(&m_core->arg1), I0); // mov [m_core->arg1],i0
- UML_CALLC(block, cfunc_write_iop, this); // callc cfunc_write_iop
+ UML_MOV(block, mem(&m_core->arg0), I1); // mov [m_core->arg0],i1
+ UML_MOV(block, mem(&m_core->arg1), I0); // mov [m_core->arg1],i0
+ UML_CALLC(block, cfunc_write_iop, this); // callc cfunc_write_iop
UML_RET(block);
- UML_LABEL(block, label++); // label4:
- UML_CMP(block, I1, IRAM_SHORT_BLOCK0_START); // cmp i1,IRAM_SHORT_BLOCK0_START
- UML_JMPc(block, COND_B, label); // jb label5
- UML_CMP(block, I1, IRAM_SHORT_BLOCK0_END); // cmp i1,IRAM_SHORT_BLOCK0_END
- UML_JMPc(block, COND_A, label); // ja label5
+ UML_LABEL(block, label++); // label4:
+ UML_CMP(block, I1, IRAM_SHORT_BLOCK0_START); // cmp i1,IRAM_SHORT_BLOCK0_START
+ UML_JMPc(block, COND_B, label); // jb label5
+ UML_CMP(block, I1, IRAM_SHORT_BLOCK0_END); // cmp i1,IRAM_SHORT_BLOCK0_END
+ UML_JMPc(block, COND_A, label); // ja label5
// 0x40000 ... 0x4ffff
- UML_AND(block, I1, I1, 0xffff); // and i1,i1,0xffff
- UML_XOR(block, I1, I1, 1); // xor i1,i1,1
- UML_STORE(block, block0, I1, I0, SIZE_WORD, SCALE_x2); // store [block0],i1,i0,word,scale_x2
+ UML_AND(block, I1, I1, 0xffff); // and i1,i1,0xffff
+ UML_XOR(block, I1, I1, 1); // xor i1,i1,1
+ UML_STORE(block, block0, I1, I0, SIZE_WORD, SCALE_x2); // store [block0],i1,i0,word,scale_x2
UML_RET(block);
- UML_LABEL(block, label++); // label5:
- UML_CMP(block, I1, IRAM_SHORT_BLOCK1_START); // cmp i1,IRAM_SHORT_BLOCK1_START
- UML_JMPc(block, COND_B, label); // jb label6
- UML_CMP(block, I1, IRAM_SHORT_BLOCK1_END); // cmp i1,IRAM_SHORT_BLOCK1_END
- UML_JMPc(block, COND_A, label); // ja label6
+ UML_LABEL(block, label++); // label5:
+ UML_CMP(block, I1, IRAM_SHORT_BLOCK1_START); // cmp i1,IRAM_SHORT_BLOCK1_START
+ UML_JMPc(block, COND_B, label); // jb label6
+ UML_CMP(block, I1, IRAM_SHORT_BLOCK1_END); // cmp i1,IRAM_SHORT_BLOCK1_END
+ UML_JMPc(block, COND_A, label); // ja label6
// 0x50000 ... 0x7ffff
- UML_AND(block, I1, I1, 0xffff); // and i1,i1,0xffff
- UML_XOR(block, I1, I1, 1); // xor i1,i1,1
- UML_STORE(block, block1, I1, I0, SIZE_WORD, SCALE_x2); // store [block1],i1,i0,word,scale_x2
+ UML_AND(block, I1, I1, 0xffff); // and i1,i1,0xffff
+ UML_XOR(block, I1, I1, 1); // xor i1,i1,1
+ UML_STORE(block, block1, I1, I0, SIZE_WORD, SCALE_x2); // store [block1],i1,i0,word,scale_x2
UML_RET(block);
- UML_LABEL(block, label++); // label6:
+ UML_LABEL(block, label++); // label6:
break;
}
@@ -664,26 +664,26 @@ void adsp21062_device::static_generate_push_pc()
// add a global entry for this
alloc_handle(m_drcuml.get(), &m_push_pc, "push_pc");
- UML_HANDLE(block, *m_push_pc); // handle *m_push_pc
-
- UML_MOV(block, I1, PCSTKP); // mov i1,PCSTKP
- UML_ADD(block, I1, I1, 1); // add i1,i1,1
- UML_CMP(block, I1, 32); // cmp i1,32
- UML_JMPc(block, COND_L,label); // jl label1
- UML_CALLC(block, cfunc_pcstack_overflow, this); // callc cfunc_pcstack_overflow
-
- UML_LABEL(block, label++); // label1:
- UML_CMP(block, I1, 0); // cmp i1,0
- UML_JMPc(block, COND_E, label); // je label2
- UML_AND(block, STKY, STKY, ~0x400000); // and STKY,~0x400000
- UML_JMP(block, label + 1); // jmp label3
- UML_LABEL(block, label++); // label2:
- UML_OR(block, STKY, STKY, 0x400000); // or STKY,0x400000
-
- UML_LABEL(block, label++); // label3:
- UML_MOV(block, PCSTK, I0); // mov PCSTK,pc
- UML_STORE(block, &m_core->pcstack, I1, I0, SIZE_DWORD, SCALE_x4); // store [m_core->pcstack],i1,i0,dword,scale_x4
- UML_MOV(block, PCSTKP, I1); // mov PCSTKP,i1
+ UML_HANDLE(block, *m_push_pc); // handle *m_push_pc
+
+ UML_MOV(block, I1, PCSTKP); // mov i1,PCSTKP
+ UML_ADD(block, I1, I1, 1); // add i1,i1,1
+ UML_CMP(block, I1, 32); // cmp i1,32
+ UML_JMPc(block, COND_L,label); // jl label1
+ UML_CALLC(block, cfunc_pcstack_overflow, this); // callc cfunc_pcstack_overflow
+
+ UML_LABEL(block, label++); // label1:
+ UML_CMP(block, I1, 0); // cmp i1,0
+ UML_JMPc(block, COND_E, label); // je label2
+ UML_AND(block, STKY, STKY, ~0x400000); // and STKY,~0x400000
+ UML_JMP(block, label + 1); // jmp label3
+ UML_LABEL(block, label++); // label2:
+ UML_OR(block, STKY, STKY, 0x400000); // or STKY,0x400000
+
+ UML_LABEL(block, label++); // label3:
+ UML_MOV(block, PCSTK, I0); // mov PCSTK,pc
+ UML_STORE(block, &m_core->pcstack, I1, I0, SIZE_DWORD, SCALE_x4); // store [m_core->pcstack],i1,i0,dword,scale_x4
+ UML_MOV(block, PCSTKP, I1); // mov PCSTKP,i1
UML_RET(block);
@@ -700,26 +700,26 @@ void adsp21062_device::static_generate_pop_pc()
// add a global entry for this
alloc_handle(m_drcuml.get(), &m_pop_pc, "pop_pc");
- UML_HANDLE(block, *m_pop_pc); // handle *m_pop_pc
-
- UML_MOV(block, I1, PCSTKP); // mov i0,PCSTKP
- UML_LOAD(block, I0, &m_core->pcstack, I1, SIZE_DWORD, SCALE_x4); // load i1,[m_core->pcstack],i0,dword,scale_x4
- UML_CMP(block, I1, 0); // cmp i1,0
- UML_JMPc(block, COND_NE, label); // jne label1
- UML_CALLC(block, cfunc_pcstack_underflow, this); // callc cfunc_pcstack_underflow
-
- UML_LABEL(block, label++); // label1:
- UML_SUB(block, I1, I1, 1); // sub i1,i1,1
- UML_CMP(block, I1, 0); // cmp i1,0
- UML_JMPc(block, COND_E, label); // je label2
- UML_AND(block, STKY, STKY, ~0x400000); // and STKY,~0x400000
- UML_JMP(block, label + 1); // jmp label3
- UML_LABEL(block, label++); // label2:
- UML_OR(block, STKY, STKY, 0x400000); // or STKY,0x400000
-
- UML_LABEL(block, label++); // label3:
- UML_MOV(block, PCSTKP, I1); // mov PCSTKP,i1
- UML_MOV(block, PCSTK, I0); // mov PCSTK,i0
+ UML_HANDLE(block, *m_pop_pc); // handle *m_pop_pc
+
+ UML_MOV(block, I1, PCSTKP); // mov i0,PCSTKP
+ UML_LOAD(block, I0, &m_core->pcstack, I1, SIZE_DWORD, SCALE_x4); // load i1,[m_core->pcstack],i0,dword,scale_x4
+ UML_CMP(block, I1, 0); // cmp i1,0
+ UML_JMPc(block, COND_NE, label); // jne label1
+ UML_CALLC(block, cfunc_pcstack_underflow, this); // callc cfunc_pcstack_underflow
+
+ UML_LABEL(block, label++); // label1:
+ UML_SUB(block, I1, I1, 1); // sub i1,i1,1
+ UML_CMP(block, I1, 0); // cmp i1,0
+ UML_JMPc(block, COND_E, label); // je label2
+ UML_AND(block, STKY, STKY, ~0x400000); // and STKY,~0x400000
+ UML_JMP(block, label + 1); // jmp label3
+ UML_LABEL(block, label++); // label2:
+ UML_OR(block, STKY, STKY, 0x400000); // or STKY,0x400000
+
+ UML_LABEL(block, label++); // label3:
+ UML_MOV(block, PCSTKP, I1); // mov PCSTKP,i1
+ UML_MOV(block, PCSTK, I0); // mov PCSTK,i0
UML_RET(block);
@@ -737,28 +737,28 @@ void adsp21062_device::static_generate_push_loop()
// add a global entry for this
alloc_handle(m_drcuml.get(), &m_push_loop, "push_loop");
- UML_HANDLE(block, *m_push_loop); // handle *m_push_loop
+ UML_HANDLE(block, *m_push_loop); // handle *m_push_loop
- UML_MOV(block, I2, LSTKP); // mov i2,LSTKP
- UML_ADD(block, I2, I2, 1); // add i2,1
- UML_CMP(block, I2, 6); // cmp i2,6
- UML_JMPc(block, COND_L, label); // jl label1
- UML_CALLC(block, cfunc_loopstack_overflow, this); // callc cfunc_loopstack_overflow
+ UML_MOV(block, I2, LSTKP); // mov i2,LSTKP
+ UML_ADD(block, I2, I2, 1); // add i2,1
+ UML_CMP(block, I2, 6); // cmp i2,6
+ UML_JMPc(block, COND_L, label); // jl label1
+ UML_CALLC(block, cfunc_loopstack_overflow, this); // callc cfunc_loopstack_overflow
- UML_LABEL(block, label++); // label1:
- UML_CMP(block, I2, 0); // cmp i2,0
- UML_JMPc(block, COND_E, label); // je label2
- UML_AND(block, STKY, STKY, ~0x4000000); // and STKY,~0x4000000
- UML_JMP(block, label + 1); // jmp label3
- UML_LABEL(block, label++); // label2:
- UML_OR(block, STKY, STKY, 0x4000000); // or STKY,0x4000000
+ UML_LABEL(block, label++); // label1:
+ UML_CMP(block, I2, 0); // cmp i2,0
+ UML_JMPc(block, COND_E, label); // je label2
+ UML_AND(block, STKY, STKY, ~0x4000000); // and STKY,~0x4000000
+ UML_JMP(block, label + 1); // jmp label3
+ UML_LABEL(block, label++); // label2:
+ UML_OR(block, STKY, STKY, 0x4000000); // or STKY,0x4000000
- UML_LABEL(block, label++); // label3:
+ UML_LABEL(block, label++); // label3:
- UML_STORE(block, m_core->lcstack, I2, I0, SIZE_DWORD, SCALE_x4); // store m_core->lcstack,i2,i0,dword,scale_x4
- UML_STORE(block, m_core->lastack, I2, I1, SIZE_DWORD, SCALE_x4); // store m_core->lastack,i2,i1,dword,scale_x4
- UML_MOV(block, CURLCNTR, I0); // mov CURLCNTR,i0
- UML_MOV(block, LSTKP, I2); // mov LSTKP,i2
+ UML_STORE(block, m_core->lcstack, I2, I0, SIZE_DWORD, SCALE_x4); // store m_core->lcstack,i2,i0,dword,scale_x4
+ UML_STORE(block, m_core->lastack, I2, I1, SIZE_DWORD, SCALE_x4); // store m_core->lastack,i2,i1,dword,scale_x4
+ UML_MOV(block, CURLCNTR, I0); // mov CURLCNTR,i0
+ UML_MOV(block, LSTKP, I2); // mov LSTKP,i2
UML_RET(block);
@@ -774,26 +774,26 @@ void adsp21062_device::static_generate_pop_loop()
// add a global entry for this
alloc_handle(m_drcuml.get(), &m_pop_loop, "pop_loop");
- UML_HANDLE(block, *m_pop_loop); // handle *m_pop_loop
-
- UML_MOV(block, I2, LSTKP); // mov i2,LSTKP
- UML_CMP(block, I2, 0); // cmp i2,0
- UML_JMPc(block, COND_NE, label); // jne label1
- UML_CALLC(block, cfunc_loopstack_underflow, this); // callc cfunc_loopstack_underflow
-
- UML_LABEL(block, label++); // label1:
- UML_SUB(block, I2, I2, 1); // sub i2,i2,1
- UML_CMP(block, I2, 0); // cmp i2,0
- UML_JMPc(block, COND_E, label); // je label2
- UML_AND(block, STKY, STKY, ~0x4000000); // and STKY,~0x4000000
- UML_JMP(block, label + 1); // jmp label3
- UML_LABEL(block, label++); // label2:
- UML_OR(block, STKY, STKY, 0x4000000); // or STKY,0x4000000
-
- UML_LABEL(block, label++); // label3:
- UML_LOAD(block, I0, m_core->lcstack, I2, SIZE_DWORD, SCALE_x4); // load i0,m_core->lcstack,i2,dword,scale_x4
- UML_MOV(block, CURLCNTR, I0); // mov CURLCNTR,i0
- UML_MOV(block, LSTKP, I2); // mov LSTKP,i2
+ UML_HANDLE(block, *m_pop_loop); // handle *m_pop_loop
+
+ UML_MOV(block, I2, LSTKP); // mov i2,LSTKP
+ UML_CMP(block, I2, 0); // cmp i2,0
+ UML_JMPc(block, COND_NE, label); // jne label1
+ UML_CALLC(block, cfunc_loopstack_underflow, this); // callc cfunc_loopstack_underflow
+
+ UML_LABEL(block, label++); // label1:
+ UML_SUB(block, I2, I2, 1); // sub i2,i2,1
+ UML_CMP(block, I2, 0); // cmp i2,0
+ UML_JMPc(block, COND_E, label); // je label2
+ UML_AND(block, STKY, STKY, ~0x4000000); // and STKY,~0x4000000
+ UML_JMP(block, label + 1); // jmp label3
+ UML_LABEL(block, label++); // label2:
+ UML_OR(block, STKY, STKY, 0x4000000); // or STKY,0x4000000
+
+ UML_LABEL(block, label++); // label3:
+ UML_LOAD(block, I0, m_core->lcstack, I2, SIZE_DWORD, SCALE_x4); // load i0,m_core->lcstack,i2,dword,scale_x4
+ UML_MOV(block, CURLCNTR, I0); // mov CURLCNTR,i0
+ UML_MOV(block, LSTKP, I2); // mov LSTKP,i2
UML_RET(block);
@@ -809,24 +809,24 @@ void adsp21062_device::static_generate_push_status()
// add a global entry for this
alloc_handle(m_drcuml.get(), &m_push_status, "push_status");
- UML_HANDLE(block, *m_push_status); // handle *m_push_status
+ UML_HANDLE(block, *m_push_status); // handle *m_push_status
- UML_MOV(block, I2, mem(&m_core->status_stkp)); // mov i2,[status_stkp]
- UML_ADD(block, I2, I2, 1); // add i2,1
- UML_CMP(block, I2, 5); // cmp i2,5
- UML_JMPc(block, COND_L, label); // jl label1
- UML_CALLC(block, cfunc_statusstack_overflow, this); // callc cfunc_statusstack_overflow
+ UML_MOV(block, I2, mem(&m_core->status_stkp)); // mov i2,[status_stkp]
+ UML_ADD(block, I2, I2, 1); // add i2,1
+ UML_CMP(block, I2, 5); // cmp i2,5
+ UML_JMPc(block, COND_L, label); // jl label1
+ UML_CALLC(block, cfunc_statusstack_overflow, this); // callc cfunc_statusstack_overflow
- UML_LABEL(block, label++); // label1:
- UML_CMP(block, I2, 0); // cmp i2,0
- UML_JMPc(block, COND_E, label); // je label2
- UML_AND(block, STKY, STKY, ~0x1000000); // and STKY,~0x1000000
- UML_JMP(block, label + 1); // jmp label3
- UML_LABEL(block, label++); // label2:
- UML_OR(block, STKY, STKY, 0x1000000); // or STKY,0x1000000
+ UML_LABEL(block, label++); // label1:
+ UML_CMP(block, I2, 0); // cmp i2,0
+ UML_JMPc(block, COND_E, label); // je label2
+ UML_AND(block, STKY, STKY, ~0x1000000); // and STKY,~0x1000000
+ UML_JMP(block, label + 1); // jmp label3
+ UML_LABEL(block, label++); // label2:
+ UML_OR(block, STKY, STKY, 0x1000000); // or STKY,0x1000000
- UML_LABEL(block, label++); // label3:
- UML_MOV(block, mem(&m_core->status_stkp), I2); // mov [status_stkp],i2
+ UML_LABEL(block, label++); // label3:
+ UML_MOV(block, mem(&m_core->status_stkp), I2); // mov [status_stkp],i2
//TODO: load MODE1
//TODO: load ASTAT
@@ -845,27 +845,27 @@ void adsp21062_device::static_generate_pop_status()
// add a global entry for this
alloc_handle(m_drcuml.get(), &m_pop_status, "pop_status");
- UML_HANDLE(block, *m_pop_status); // handle *m_pop_status
+ UML_HANDLE(block, *m_pop_status); // handle *m_pop_status
//TODO: store MODE1
//TODO: store ASTAT
-
- UML_MOV(block, I2, mem(&m_core->status_stkp)); // mov i2,[status_stkp]
- UML_CMP(block, I2, 0); // cmp i2,0
- UML_JMPc(block, COND_NE, label); // jl label1
- UML_CALLC(block, cfunc_statusstack_underflow, this); // callc cfunc_statusstack_underflow
-
- UML_LABEL(block, label++); // label1:
- UML_SUB(block, I2, I2, 1); // sub i2,1
- UML_CMP(block, I2, 0); // cmp i2,0
- UML_JMPc(block, COND_E, label); // je label2
- UML_AND(block, STKY, STKY, ~0x1000000); // and STKY,~0x1000000
- UML_JMP(block, label + 1); // jmp label3
- UML_LABEL(block, label++); // label2:
- UML_OR(block, STKY, STKY, 0x1000000); // or STKY,0x1000000
-
- UML_LABEL(block, label++); // label3:
- UML_MOV(block, mem(&m_core->status_stkp), I2); // mov [status_stkp],i2
+
+ UML_MOV(block, I2, mem(&m_core->status_stkp)); // mov i2,[status_stkp]
+ UML_CMP(block, I2, 0); // cmp i2,0
+ UML_JMPc(block, COND_NE, label); // jl label1
+ UML_CALLC(block, cfunc_statusstack_underflow, this); // callc cfunc_statusstack_underflow
+
+ UML_LABEL(block, label++); // label1:
+ UML_SUB(block, I2, I2, 1); // sub i2,1
+ UML_CMP(block, I2, 0); // cmp i2,0
+ UML_JMPc(block, COND_E, label); // je label2
+ UML_AND(block, STKY, STKY, ~0x1000000); // and STKY,~0x1000000
+ UML_JMP(block, label + 1); // jmp label3
+ UML_LABEL(block, label++); // label2:
+ UML_OR(block, STKY, STKY, 0x1000000); // or STKY,0x1000000
+
+ UML_LABEL(block, label++); // label3:
+ UML_MOV(block, mem(&m_core->status_stkp), I2); // mov [status_stkp],i2
UML_RET(block);
@@ -886,30 +886,30 @@ void adsp21062_device::static_generate_exception(UINT8 exception, const char *na
/* add a global entry for this */
alloc_handle(m_drcuml.get(), &exception_handle, name);
- UML_HANDLE(block, *exception_handle); // handle name
+ UML_HANDLE(block, *exception_handle); // handle name
- UML_AND(block, I3, mem(&m_core->irq_pending), IMASK); // and i3,[irq_pending],IMASK
- UML_TZCNT(block, I3, I3); // tzcnt i3,i3
+ UML_AND(block, I3, mem(&m_core->irq_pending), IMASK); // and i3,[irq_pending],IMASK
+ UML_TZCNT(block, I3, I3); // tzcnt i3,i3
- UML_MOV(block, I2, 1); // mov i2,1
- UML_SHL(block, I2, I2, I3); // shl i2,i2,i3
- UML_OR(block, IRPTL, IRPTL, I2); // or IRPTL,i2
+ UML_MOV(block, I2, 1); // mov i2,1
+ UML_SHL(block, I2, I2, I3); // shl i2,i2,i3
+ UML_OR(block, IRPTL, IRPTL, I2); // or IRPTL,i2
UML_XOR(block, mem(&m_core->irq_pending), mem(&m_core->irq_pending), I2); // xor [irq_pending],i2
- UML_MOV(block, mem(&m_core->active_irq_num), I3); // mov [active_irq_num],i3
- UML_MOV(block, mem(&m_core->interrupt_active), 1); // mov [interrupt_active],1
+ UML_MOV(block, mem(&m_core->active_irq_num), I3); // mov [active_irq_num],i3
+ UML_MOV(block, mem(&m_core->interrupt_active), 1); // mov [interrupt_active],1
- UML_CALLH(block, *m_push_pc); // callh m_push_pc
+ UML_CALLH(block, *m_push_pc); // callh m_push_pc
- UML_CMP(block, I3, 6); // cmp i3,6
- UML_JMPc(block, COND_L, label_nopush); // jl label_nopush
- UML_CMP(block, I3, 8); // cmp i3,8
- UML_JMPc(block, COND_G, label_nopush); // jg label_nopush
- UML_CALLH(block, *m_push_status); // callh m_push_status
+ UML_CMP(block, I3, 6); // cmp i3,6
+ UML_JMPc(block, COND_L, label_nopush); // jl label_nopush
+ UML_CMP(block, I3, 8); // cmp i3,8
+ UML_JMPc(block, COND_G, label_nopush); // jg label_nopush
+ UML_CALLH(block, *m_push_status); // callh m_push_status
- UML_LABEL(block, label_nopush); // label_nopush:
- UML_SHL(block, I0, I3, 2); // shl i0,i3,2
- UML_ADD(block, I0, I0, 0x20000); // add i0,0x20000
- UML_HASHJMP(block, 0, I0, *m_nocode); // hashjmp i0,m_nocode
+ UML_LABEL(block, label_nopush); // label_nopush:
+ UML_SHL(block, I0, I3, 2); // shl i0,i3,2
+ UML_ADD(block, I0, I0, 0x20000); // add i0,0x20000
+ UML_HASHJMP(block, 0, I0, *m_nocode); // hashjmp i0,m_nocode
block->end();
}
@@ -924,7 +924,7 @@ void adsp21062_device::static_generate_mode1_ops()
block = m_drcuml->begin_block(128);
alloc_handle(m_drcuml.get(), &m_swap_dag1_0_3, "swap_dag1_0_3");
- UML_HANDLE(block, *m_swap_dag1_0_3); // handle name
+ UML_HANDLE(block, *m_swap_dag1_0_3); // handle name
#if !USE_SWAPDQ
for (int i = 0; i < 4; i++)
{
@@ -956,7 +956,7 @@ void adsp21062_device::static_generate_mode1_ops()
block = m_drcuml->begin_block(128);
alloc_handle(m_drcuml.get(), &m_swap_dag1_4_7, "swap_dag1_4_7");
- UML_HANDLE(block, *m_swap_dag1_4_7); // handle name
+ UML_HANDLE(block, *m_swap_dag1_4_7); // handle name
#if !USE_SWAPDQ
for (int i = 4; i < 8; i++)
{
@@ -988,7 +988,7 @@ void adsp21062_device::static_generate_mode1_ops()
block = m_drcuml->begin_block(128);
alloc_handle(m_drcuml.get(), &m_swap_dag2_0_3, "swap_dag2_0_3");
- UML_HANDLE(block, *m_swap_dag2_0_3); // handle name
+ UML_HANDLE(block, *m_swap_dag2_0_3); // handle name
#if !USE_SWAPDQ
for (int i = 0; i < 4; i++)
{
@@ -1020,7 +1020,7 @@ void adsp21062_device::static_generate_mode1_ops()
block = m_drcuml->begin_block(128);
alloc_handle(m_drcuml.get(), &m_swap_dag2_4_7, "swap_dag2_4_7");
- UML_HANDLE(block, *m_swap_dag2_4_7); // handle name
+ UML_HANDLE(block, *m_swap_dag2_4_7); // handle name
#if !USE_SWAPDQ
for (int i = 4; i < 8; i++)
{
@@ -1052,7 +1052,7 @@ void adsp21062_device::static_generate_mode1_ops()
block = m_drcuml->begin_block(64);
alloc_handle(m_drcuml.get(), &m_swap_r0_7, "swap_r0_7");
- UML_HANDLE(block, *m_swap_r0_7); // handle name
+ UML_HANDLE(block, *m_swap_r0_7); // handle name
#if !USE_SWAPDQ
for (int i = 0; i < 8; i++)
{
@@ -1070,7 +1070,7 @@ void adsp21062_device::static_generate_mode1_ops()
block = m_drcuml->begin_block(64);
alloc_handle(m_drcuml.get(), &m_swap_r8_15, "swap_r8_15");
- UML_HANDLE(block, *m_swap_r8_15); // handle name
+ UML_HANDLE(block, *m_swap_r8_15); // handle name
#if !USE_SWAPDQ
for (int i = 8; i < 16; i++)
{
@@ -1095,8 +1095,8 @@ void adsp21062_device::execute_run_drc()
drcuml_state *drcuml = m_drcuml.get();
int execute_result;
-// if (m_cache_dirty)
-// printf("SHARC cache reset\n");
+// if (m_cache_dirty)
+// printf("SHARC cache reset\n");
/* reset the cache if dirty */
if (m_cache_dirty)
@@ -1173,7 +1173,7 @@ void adsp21062_device::compile_block(offs_t pc)
else
{
UML_LABEL(block, seqhead->pc | 0x80000000); // label seqhead->pc
- UML_HASHJMP(block, 0, seqhead->pc, *m_nocode); // hashjmp <0>,seqhead->pc,nocode
+ UML_HASHJMP(block, 0, seqhead->pc, *m_nocode); // hashjmp <0>,seqhead->pc,nocode
continue;
}
@@ -1202,10 +1202,10 @@ void adsp21062_device::compile_block(offs_t pc)
/* count off cycles and go there */
- generate_update_cycles(block, &compiler, nextpc, TRUE); // <subtract cycles>
+ generate_update_cycles(block, &compiler, nextpc, TRUE); // <subtract cycles>
if (seqlast->next() == nullptr || seqlast->next()->pc != nextpc)
- UML_HASHJMP(block, 0, nextpc, *m_nocode); // hashjmp <mode>,nextpc,nocode
+ UML_HASHJMP(block, 0, nextpc, *m_nocode); // hashjmp <mode>,nextpc,nocode
}
block->end();
@@ -1271,23 +1271,23 @@ void adsp21062_device::static_generate_entry_point()
alloc_handle(m_drcuml.get(), &m_exception[EXCEPTION_INTERRUPT], "exception_interrupt");
alloc_handle(m_drcuml.get(), &m_entry, "entry");
- UML_HANDLE(block, *m_entry); // handle entry
+ UML_HANDLE(block, *m_entry); // handle entry
- load_fast_iregs(block); // <load fastregs>
+ load_fast_iregs(block); // <load fastregs>
- /* check for interrupts */
- UML_CMP(block, mem(&m_core->irq_pending), 0); // cmp [irq_pending],0
- UML_JMPc(block, COND_E, skip); // je skip
- UML_CMP(block, mem(&m_core->interrupt_active), 0); // cmp [interrupt_active],0
- UML_JMPc(block, COND_NE, skip); // jne skip
- UML_TEST(block, mem(&m_core->irq_pending), IMASK); // test [irq_pending],IMASK
- UML_JMPc(block, COND_Z, skip); // jz skip
- UML_TEST(block, mem(&m_core->mode1), MODE1_IRPTEN); // test MODE1,MODE1_IRPTEN
- UML_JMPc(block, COND_Z, skip); // jz skip
+ /* check for interrupts */
+ UML_CMP(block, mem(&m_core->irq_pending), 0); // cmp [irq_pending],0
+ UML_JMPc(block, COND_E, skip); // je skip
+ UML_CMP(block, mem(&m_core->interrupt_active), 0); // cmp [interrupt_active],0
+ UML_JMPc(block, COND_NE, skip); // jne skip
+ UML_TEST(block, mem(&m_core->irq_pending), IMASK); // test [irq_pending],IMASK
+ UML_JMPc(block, COND_Z, skip); // jz skip
+ UML_TEST(block, mem(&m_core->mode1), MODE1_IRPTEN); // test MODE1,MODE1_IRPTEN
+ UML_JMPc(block, COND_Z, skip); // jz skip
- UML_MOV(block, I0, mem(&m_core->pc)); // mov i0,nextpc
- UML_MOV(block, I1, 0); // mov i1,0
- UML_CALLH(block, *m_exception[EXCEPTION_INTERRUPT]); // callh m_exception[EXCEPTION_INTERRUPT]
+ UML_MOV(block, I0, mem(&m_core->pc)); // mov i0,nextpc
+ UML_MOV(block, I1, 0); // mov i1,0
+ UML_CALLH(block, *m_exception[EXCEPTION_INTERRUPT]); // callh m_exception[EXCEPTION_INTERRUPT]
UML_LABEL(block, skip);
@@ -1307,11 +1307,11 @@ void adsp21062_device::static_generate_nocode_handler()
/* generate a hash jump via the current mode and PC */
alloc_handle(m_drcuml.get(), &m_nocode, "nocode");
- UML_HANDLE(block, *m_nocode); // handle nocode
- UML_GETEXP(block, I0); // getexp i0
- UML_MOV(block, mem(&m_core->pc), I0); // mov [pc],i0
- save_fast_iregs(block); // <save fastregs>
- UML_EXIT(block, EXECUTE_MISSING_CODE); // exit EXECUTE_MISSING_CODE
+ UML_HANDLE(block, *m_nocode); // handle nocode
+ UML_GETEXP(block, I0); // getexp i0
+ UML_MOV(block, mem(&m_core->pc), I0); // mov [pc],i0
+ save_fast_iregs(block); // <save fastregs>
+ UML_EXIT(block, EXECUTE_MISSING_CODE); // exit EXECUTE_MISSING_CODE
block->end();
}
@@ -1325,11 +1325,11 @@ void adsp21062_device::static_generate_out_of_cycles()
/* generate a hash jump via the current mode and PC */
alloc_handle(m_drcuml.get(), &m_out_of_cycles, "out_of_cycles");
- UML_HANDLE(block, *m_out_of_cycles); // handle out_of_cycles
- UML_GETEXP(block, I0); // getexp i0
- UML_MOV(block, mem(&m_core->pc), I0); // mov <pc>,i0
- save_fast_iregs(block); // <save fastregs>
- UML_EXIT(block, EXECUTE_OUT_OF_CYCLES); // exit EXECUTE_OUT_OF_CYCLES
+ UML_HANDLE(block, *m_out_of_cycles); // handle out_of_cycles
+ UML_GETEXP(block, I0); // getexp i0
+ UML_MOV(block, mem(&m_core->pc), I0); // mov <pc>,i0
+ save_fast_iregs(block); // <save fastregs>
+ UML_EXIT(block, EXECUTE_OUT_OF_CYCLES); // exit EXECUTE_OUT_OF_CYCLES
block->end();
}
@@ -1338,8 +1338,8 @@ void adsp21062_device::static_generate_out_of_cycles()
void adsp21062_device::generate_sequence_instruction(drcuml_block *block, compiler_state *compiler, const opcode_desc *desc, bool last_delayslot)
{
/* add an entry for the log */
-// if (m_drcuml->logging() && !(desc->flags & OPFLAG_VIRTUAL_NOOP))
-// log_add_disasm_comment(block, desc->pc, desc->opptr.l[0]);
+// if (m_drcuml->logging() && !(desc->flags & OPFLAG_VIRTUAL_NOOP))
+// log_add_disasm_comment(block, desc->pc, desc->opptr.l[0]);
/* set the PC map variable */
UML_MAPVAR(block, MAPVAR_PC, desc->pc); // mapvar PC,desc->pc
@@ -1353,17 +1353,17 @@ void adsp21062_device::generate_sequence_instruction(drcuml_block *block, compil
/* if we are debugging, call the debugger */
if ((machine().debug_flags & DEBUG_FLAG_ENABLED) != 0)
{
- UML_MOV(block, mem(&m_core->pc), desc->pc); // mov [pc],desc->pc
- save_fast_iregs(block); // <save fastregs>
- UML_DEBUG(block, desc->pc); // debug desc->pc
+ UML_MOV(block, mem(&m_core->pc), desc->pc); // mov [pc],desc->pc
+ save_fast_iregs(block); // <save fastregs>
+ UML_DEBUG(block, desc->pc); // debug desc->pc
}
/* if we hit an unmapped address, fatal error */
if (desc->flags & OPFLAG_COMPILER_UNMAPPED)
{
- UML_MOV(block, mem(&m_core->pc), desc->pc); // mov [pc],desc->pc
- save_fast_iregs(block); // <save fastregs>
- UML_EXIT(block, EXECUTE_UNMAPPED_CODE); // exit EXECUTE_UNMAPPED_CODE
+ UML_MOV(block, mem(&m_core->pc), desc->pc); // mov [pc],desc->pc
+ save_fast_iregs(block); // <save fastregs>
+ UML_EXIT(block, EXECUTE_UNMAPPED_CODE); // exit EXECUTE_UNMAPPED_CODE
}
// handle a special case where call is used as the last operation in a loop
@@ -1377,19 +1377,19 @@ void adsp21062_device::generate_sequence_instruction(drcuml_block *block, compil
UML_JMPc(block, COND_NE, end);
code_label label_expire = compiler->labelnum++;
- UML_MOV(block, I1, mem(&m_core->lstkp)); // mov i1,[m_core->lstkp]
- UML_LOAD(block, I0, m_core->lcstack, I1, SIZE_DWORD, SCALE_x4); // load i0,m_core->lcstack,i1,dword,scale_x4
- UML_SUB(block, I0, I0, 1); // sub i0,1
- UML_STORE(block, m_core->lcstack, I1, I0, SIZE_DWORD, SCALE_x4); // store m_core->lcstack,i1,i0,dword,scale_x4
- UML_SUB(block, CURLCNTR, CURLCNTR, 1); // sub CURLCNTR,1
- UML_JMPc(block, COND_E, label_expire); // jne label_expire
+ UML_MOV(block, I1, mem(&m_core->lstkp)); // mov i1,[m_core->lstkp]
+ UML_LOAD(block, I0, m_core->lcstack, I1, SIZE_DWORD, SCALE_x4); // load i0,m_core->lcstack,i1,dword,scale_x4
+ UML_SUB(block, I0, I0, 1); // sub i0,1
+ UML_STORE(block, m_core->lcstack, I1, I0, SIZE_DWORD, SCALE_x4); // store m_core->lcstack,i1,i0,dword,scale_x4
+ UML_SUB(block, CURLCNTR, CURLCNTR, 1); // sub CURLCNTR,1
+ UML_JMPc(block, COND_E, label_expire); // jne label_expire
UML_MOV(block, mem(&m_core->temp_return), desc->userdata0);
UML_JMP(block, end);
- UML_LABEL(block, label_expire); // label_expire:
- UML_CALLH(block, *m_pop_pc); // callh m_pop_pc
- UML_CALLH(block, *m_pop_loop); // callh m_pop_loop
+ UML_LABEL(block, label_expire); // label_expire:
+ UML_CALLH(block, *m_pop_pc); // callh m_pop_pc
+ UML_CALLH(block, *m_pop_loop); // callh m_pop_loop
UML_MOV(block, mem(&m_core->temp_return), desc->pc + 1);
UML_LABEL(block, end);
@@ -1418,8 +1418,8 @@ void adsp21062_device::generate_sequence_instruction(drcuml_block *block, compil
}
/* if this is an invalid opcode, generate the exception now */
-// if (desc->flags & OPFLAG_INVALID_OPCODE)
-// UML_EXH(block, *m_exception[EXCEPTION_PROGRAM], 0x80000); // exh exception_program,0x80000
+// if (desc->flags & OPFLAG_INVALID_OPCODE)
+// UML_EXH(block, *m_exception[EXCEPTION_PROGRAM], 0x80000); // exh exception_program,0x80000
/* unless this is a virtual no-op, it's a regular instruction */
if (!(desc->flags & OPFLAG_VIRTUAL_NOOP))
@@ -1427,9 +1427,9 @@ void adsp21062_device::generate_sequence_instruction(drcuml_block *block, compil
/* compile the instruction */
if (!generate_opcode(block, compiler, desc))
{
- UML_MOV(block, mem(&m_core->pc), desc->pc); // mov [pc],desc->pc
- UML_DMOV(block, mem(&m_core->arg64), desc->opptr.q[0]); // dmov [arg64],*desc->opptr.q
- UML_CALLC(block, cfunc_unimplemented, this); // callc cfunc_unimplemented,ppc
+ UML_MOV(block, mem(&m_core->pc), desc->pc); // mov [pc],desc->pc
+ UML_DMOV(block, mem(&m_core->arg64), desc->opptr.q[0]); // dmov [arg64],*desc->opptr.q
+ UML_CALLC(block, cfunc_unimplemented, this); // callc cfunc_unimplemented,ppc
}
}
@@ -1438,7 +1438,7 @@ void adsp21062_device::generate_sequence_instruction(drcuml_block *block, compil
if (compiler->mode1_delay.counter > 0)
{
compiler->mode1_delay.counter--;
-
+
// delayed operation in the last delay slot needs to be done before the branch is taken
if (last_delayslot)
compiler->mode1_delay.counter = 0;
@@ -1467,7 +1467,7 @@ void adsp21062_device::generate_sequence_instruction(drcuml_block *block, compil
}
- // insert loop check at this instruction if needed
+ // insert loop check at this instruction if needed
if (desc->userflags & OP_USERFLAG_COUNTER_LOOP)
{
code_label label_skip_loop = compiler->labelnum++;
@@ -1476,18 +1476,18 @@ void adsp21062_device::generate_sequence_instruction(drcuml_block *block, compil
UML_JMPc(block, COND_NE, label_skip_loop);
code_label label_expire = compiler->labelnum++;
- UML_MOV(block, I1, mem(&m_core->lstkp)); // mov i1,[m_core->lstkp]
- UML_LOAD(block, I0, m_core->lcstack, I1, SIZE_DWORD, SCALE_x4); // load i0,m_core->lcstack,i1,dword,scale_x4
- UML_SUB(block, I0, I0, 1); // sub i0,1
- UML_STORE(block, m_core->lcstack, I1, I0, SIZE_DWORD, SCALE_x4); // store m_core->lcstack,i1,i0,dword,scale_x4
- UML_SUB(block, CURLCNTR, CURLCNTR, 1); // sub CURLCNTR,1
- UML_JMPc(block, COND_E, label_expire); // jne label_expire
+ UML_MOV(block, I1, mem(&m_core->lstkp)); // mov i1,[m_core->lstkp]
+ UML_LOAD(block, I0, m_core->lcstack, I1, SIZE_DWORD, SCALE_x4); // load i0,m_core->lcstack,i1,dword,scale_x4
+ UML_SUB(block, I0, I0, 1); // sub i0,1
+ UML_STORE(block, m_core->lcstack, I1, I0, SIZE_DWORD, SCALE_x4); // store m_core->lcstack,i1,i0,dword,scale_x4
+ UML_SUB(block, CURLCNTR, CURLCNTR, 1); // sub CURLCNTR,1
+ UML_JMPc(block, COND_E, label_expire); // jne label_expire
generate_loop_jump(block, compiler, desc);
- UML_LABEL(block, label_expire); // label_expire:
- UML_CALLH(block, *m_pop_pc); // callh m_pop_pc
- UML_CALLH(block, *m_pop_loop); // callh m_pop_loop
+ UML_LABEL(block, label_expire); // label_expire:
+ UML_CALLH(block, *m_pop_pc); // callh m_pop_pc
+ UML_CALLH(block, *m_pop_loop); // callh m_pop_loop
UML_LABEL(block, label_skip_loop);
}
@@ -1544,18 +1544,18 @@ void adsp21062_device::generate_update_cycles(drcuml_block *block, compiler_stat
code_label skip = compiler->labelnum++;
compiler->checkints = FALSE;
- UML_CMP(block, mem(&m_core->irq_pending), 0); // cmp [irq_pending],0
- UML_JMPc(block, COND_E, skip); // je skip
- UML_CMP(block, mem(&m_core->interrupt_active), 0); // cmp [interrupt_active],0
- UML_JMPc(block, COND_NE, skip); // jne skip
- UML_TEST(block, mem(&m_core->irq_pending), IMASK); // test [irq_pending],IMASK
- UML_JMPc(block, COND_Z, skip); // jz skip
- UML_TEST(block, mem(&m_core->mode1), MODE1_IRPTEN); // test MODE1,MODE1_IRPTEN
- UML_JMPc(block, COND_Z, skip); // jz skip
+ UML_CMP(block, mem(&m_core->irq_pending), 0); // cmp [irq_pending],0
+ UML_JMPc(block, COND_E, skip); // je skip
+ UML_CMP(block, mem(&m_core->interrupt_active), 0); // cmp [interrupt_active],0
+ UML_JMPc(block, COND_NE, skip); // jne skip
+ UML_TEST(block, mem(&m_core->irq_pending), IMASK); // test [irq_pending],IMASK
+ UML_JMPc(block, COND_Z, skip); // jz skip
+ UML_TEST(block, mem(&m_core->mode1), MODE1_IRPTEN); // test MODE1,MODE1_IRPTEN
+ UML_JMPc(block, COND_Z, skip); // jz skip
- UML_MOV(block, I0, param); // mov i0,nextpc
- UML_MOV(block, I1, compiler->cycles); // mov i1,cycles
- UML_CALLH(block, *m_exception[EXCEPTION_INTERRUPT]); // callh m_exception[EXCEPTION_INTERRUPT]
+ UML_MOV(block, I0, param); // mov i0,nextpc
+ UML_MOV(block, I1, compiler->cycles); // mov i1,cycles
+ UML_CALLH(block, *m_exception[EXCEPTION_INTERRUPT]); // callh m_exception[EXCEPTION_INTERRUPT]
UML_LABEL(block, skip);
}
@@ -1563,10 +1563,10 @@ void adsp21062_device::generate_update_cycles(drcuml_block *block, compiler_stat
/* account for cycles */
if (compiler->cycles > 0)
{
- UML_SUB(block, mem(&m_core->icount), mem(&m_core->icount), MAPVAR_CYCLES); // sub icount,icount,cycles
- UML_MAPVAR(block, MAPVAR_CYCLES, 0); // mapvar cycles,0
+ UML_SUB(block, mem(&m_core->icount), mem(&m_core->icount), MAPVAR_CYCLES); // sub icount,icount,cycles
+ UML_MAPVAR(block, MAPVAR_CYCLES, 0); // mapvar cycles,0
if (allow_exception)
- UML_EXHc(block, COND_S, *m_out_of_cycles, param); // exh out_of_cycles,nextpc
+ UML_EXHc(block, COND_S, *m_out_of_cycles, param); // exh out_of_cycles,nextpc
}
compiler->cycles = 0;
}
@@ -1586,42 +1586,42 @@ void adsp21062_device::generate_write_mode1_imm(drcuml_block *block, compiler_st
// DAG1 regs 4-7
skip = compiler->labelnum++;
UML_TEST(block, MODE1, 0x8);
- UML_JMPc(block, (data & 0x8) ? COND_NZ : COND_Z, skip); // don't swap if the bits are same
+ UML_JMPc(block, (data & 0x8) ? COND_NZ : COND_Z, skip); // don't swap if the bits are same
UML_CALLH(block, *m_swap_dag1_4_7);
UML_LABEL(block, skip);
// DAG1 regs 0-3
skip = compiler->labelnum++;
UML_TEST(block, MODE1, 0x10);
- UML_JMPc(block, (data & 0x10) ? COND_NZ : COND_Z, skip); // don't swap if the bits are same
+ UML_JMPc(block, (data & 0x10) ? COND_NZ : COND_Z, skip); // don't swap if the bits are same
UML_CALLH(block, *m_swap_dag1_0_3);
UML_LABEL(block, skip);
// DAG2 regs 4-7
skip = compiler->labelnum++;
UML_TEST(block, MODE1, 0x20);
- UML_JMPc(block, (data & 0x20) ? COND_NZ : COND_Z, skip); // don't swap if the bits are same
+ UML_JMPc(block, (data & 0x20) ? COND_NZ : COND_Z, skip); // don't swap if the bits are same
UML_CALLH(block, *m_swap_dag2_4_7);
UML_LABEL(block, skip);
// DAG2 regs 0-3
skip = compiler->labelnum++;
UML_TEST(block, MODE1, 0x40);
- UML_JMPc(block, (data & 0x40) ? COND_NZ : COND_Z, skip); // don't swap if the bits are same
+ UML_JMPc(block, (data & 0x40) ? COND_NZ : COND_Z, skip); // don't swap if the bits are same
UML_CALLH(block, *m_swap_dag2_0_3);
UML_LABEL(block, skip);
// REG 8-15
skip = compiler->labelnum++;
UML_TEST(block, MODE1, 0x80);
- UML_JMPc(block, (data & 0x80) ? COND_NZ : COND_Z, skip); // don't swap if the bits are same
+ UML_JMPc(block, (data & 0x80) ? COND_NZ : COND_Z, skip); // don't swap if the bits are same
UML_CALLH(block, *m_swap_r8_15);
UML_LABEL(block, skip);
// REG 0-7
skip = compiler->labelnum++;
UML_TEST(block, MODE1, 0x400);
- UML_JMPc(block, (data & 0x400) ? COND_NZ : COND_Z, skip); // don't swap if the bits are same
+ UML_JMPc(block, (data & 0x400) ? COND_NZ : COND_Z, skip); // don't swap if the bits are same
UML_CALLH(block, *m_swap_r0_7);
UML_LABEL(block, skip);
@@ -1636,51 +1636,51 @@ void adsp21062_device::generate_set_mode1_imm(drcuml_block *block, compiler_stat
fatalerror("generate_set_mode1_imm: tried to enable I0 bit reversing");
if (data & 0x4)
fatalerror("generate_set_mode1_imm: tried to enable MR alternate");
- if (data & 0x8) // DAG1 regs 4-7
+ if (data & 0x8) // DAG1 regs 4-7
{
code_label skip = compiler->labelnum++;
UML_TEST(block, MODE1, 0x8);
- UML_JMPc(block, COND_NZ, skip); // don't swap if the bit is already 1
+ UML_JMPc(block, COND_NZ, skip); // don't swap if the bit is already 1
UML_CALLH(block, *m_swap_dag1_4_7);
UML_LABEL(block, skip);
}
- if (data & 0x10) // DAG1 regs 0-3
+ if (data & 0x10) // DAG1 regs 0-3
{
code_label skip = compiler->labelnum++;
UML_TEST(block, MODE1, 0x10);
- UML_JMPc(block, COND_NZ, skip); // don't swap if the bit is already 1
+ UML_JMPc(block, COND_NZ, skip); // don't swap if the bit is already 1
UML_CALLH(block, *m_swap_dag1_0_3);
UML_LABEL(block, skip);
}
- if (data & 0x20) // DAG2 regs 4-7
+ if (data & 0x20) // DAG2 regs 4-7
{
code_label skip = compiler->labelnum++;
UML_TEST(block, MODE1, 0x20);
- UML_JMPc(block, COND_NZ, skip); // don't swap if the bit is already 1
+ UML_JMPc(block, COND_NZ, skip); // don't swap if the bit is already 1
UML_CALLH(block, *m_swap_dag2_4_7);
UML_LABEL(block, skip);
}
- if (data & 0x40) // DAG1 regs 0-3
+ if (data & 0x40) // DAG1 regs 0-3
{
code_label skip = compiler->labelnum++;
UML_TEST(block, MODE1, 0x40);
- UML_JMPc(block, COND_NZ, skip); // don't swap if the bit is already 1
+ UML_JMPc(block, COND_NZ, skip); // don't swap if the bit is already 1
UML_CALLH(block, *m_swap_dag2_0_3);
UML_LABEL(block, skip);
}
- if (data & 0x80) // REG 8-15
+ if (data & 0x80) // REG 8-15
{
code_label skip = compiler->labelnum++;
UML_TEST(block, MODE1, 0x80);
- UML_JMPc(block, COND_NZ, skip); // don't swap if the bit is already 1
+ UML_JMPc(block, COND_NZ, skip); // don't swap if the bit is already 1
UML_CALLH(block, *m_swap_r8_15);
UML_LABEL(block, skip);
}
- if (data & 0x400) // REG 0-7
+ if (data & 0x400) // REG 0-7
{
code_label skip = compiler->labelnum++;
UML_TEST(block, MODE1, 0x400);
- UML_JMPc(block, COND_NZ, skip); // don't swap if the bit is already 1
+ UML_JMPc(block, COND_NZ, skip); // don't swap if the bit is already 1
UML_CALLH(block, *m_swap_r0_7);
UML_LABEL(block, skip);
}
@@ -1696,51 +1696,51 @@ void adsp21062_device::generate_clear_mode1_imm(drcuml_block *block, compiler_st
fatalerror("generate_clear_mode1_imm: tried to disable I0 bit reversing");
if (data & 0x4)
fatalerror("generate_clear_mode1_imm: tried to disable MR alternate");
- if (data & 0x8) // DAG1 regs 4-7
+ if (data & 0x8) // DAG1 regs 4-7
{
code_label skip = compiler->labelnum++;
UML_TEST(block, MODE1, 0x8);
- UML_JMPc(block, COND_Z, skip); // don't swap if the bit is already 0
+ UML_JMPc(block, COND_Z, skip); // don't swap if the bit is already 0
UML_CALLH(block, *m_swap_dag1_4_7);
UML_LABEL(block, skip);
}
- if (data & 0x10) // DAG1 regs 0-3
+ if (data & 0x10) // DAG1 regs 0-3
{
code_label skip = compiler->labelnum++;
UML_TEST(block, MODE1, 0x10);
- UML_JMPc(block, COND_Z, skip); // don't swap if the bit is already 0
+ UML_JMPc(block, COND_Z, skip); // don't swap if the bit is already 0
UML_CALLH(block, *m_swap_dag1_0_3);
UML_LABEL(block, skip);
}
- if (data & 0x20) // DAG2 regs 4-7
+ if (data & 0x20) // DAG2 regs 4-7
{
code_label skip = compiler->labelnum++;
UML_TEST(block, MODE1, 0x20);
- UML_JMPc(block, COND_Z, skip); // don't swap if the bit is already 0
+ UML_JMPc(block, COND_Z, skip); // don't swap if the bit is already 0
UML_CALLH(block, *m_swap_dag2_4_7);
UML_LABEL(block, skip);
}
- if (data & 0x40) // DAG1 regs 0-3
+ if (data & 0x40) // DAG1 regs 0-3
{
code_label skip = compiler->labelnum++;
UML_TEST(block, MODE1, 0x40);
- UML_JMPc(block, COND_Z, skip); // don't swap if the bit is already 0
+ UML_JMPc(block, COND_Z, skip); // don't swap if the bit is already 0
UML_CALLH(block, *m_swap_dag2_0_3);
UML_LABEL(block, skip);
}
- if (data & 0x80) // REG 8-15
+ if (data & 0x80) // REG 8-15
{
code_label skip = compiler->labelnum++;
UML_TEST(block, MODE1, 0x80);
- UML_JMPc(block, COND_Z, skip); // don't swap if the bit is already 0
+ UML_JMPc(block, COND_Z, skip); // don't swap if the bit is already 0
UML_CALLH(block, *m_swap_r8_15);
UML_LABEL(block, skip);
}
- if (data & 0x400) // REG 0-7
+ if (data & 0x400) // REG 0-7
{
code_label skip = compiler->labelnum++;
UML_TEST(block, MODE1, 0x400);
- UML_JMPc(block, COND_Z, skip); // don't swap if the bit is already 0
+ UML_JMPc(block, COND_Z, skip); // don't swap if the bit is already 0
UML_CALLH(block, *m_swap_r0_7);
UML_LABEL(block, skip);
}
@@ -1827,7 +1827,7 @@ void adsp21062_device::generate_call(drcuml_block *block, compiler_state *compil
// save branch target
if (desc->targetpc == BRANCH_TARGET_DYNAMIC)
{
- UML_MOV(block, mem(&m_core->jmpdest), I0); // mov [jmpdest],i0
+ UML_MOV(block, mem(&m_core->jmpdest), I0); // mov [jmpdest],i0
}
// compile delay slots if needed
@@ -1847,7 +1847,7 @@ void adsp21062_device::generate_call(drcuml_block *block, compiler_state *compil
if (delayslot)
UML_MOV(block, I0, desc->pc + 3);
else
- UML_MOV(block, I0, desc->pc + 1);
+ UML_MOV(block, I0, desc->pc + 1);
}
UML_CALLH(block, *m_push_pc);
@@ -1856,14 +1856,14 @@ void adsp21062_device::generate_call(drcuml_block *block, compiler_state *compil
{
generate_update_cycles(block, &compiler_temp, desc->targetpc, TRUE);
if (desc->flags & OPFLAG_INTRABLOCK_BRANCH)
- UML_JMP(block, desc->targetpc | 0x80000000); // jmp targetpc | 0x80000000
+ UML_JMP(block, desc->targetpc | 0x80000000); // jmp targetpc | 0x80000000
else
- UML_HASHJMP(block, 0, desc->targetpc, *m_nocode); // hashjmp 0,targetpc,nocode
+ UML_HASHJMP(block, 0, desc->targetpc, *m_nocode); // hashjmp 0,targetpc,nocode
}
else
{
generate_update_cycles(block, &compiler_temp, mem(&m_core->jmpdest), TRUE);
- UML_HASHJMP(block, 0, mem(&m_core->jmpdest), *m_nocode); // hashjmp 0,jmpdest,nocode
+ UML_HASHJMP(block, 0, mem(&m_core->jmpdest), *m_nocode); // hashjmp 0,jmpdest,nocode
}
// update compiler label
@@ -1871,7 +1871,7 @@ void adsp21062_device::generate_call(drcuml_block *block, compiler_state *compil
/* reset the mapvar to the current cycles and account for skipped slots */
compiler->cycles += desc->skipslots;
- UML_MAPVAR(block, MAPVAR_CYCLES, compiler->cycles); // mapvar CYCLES,compiler->cycles
+ UML_MAPVAR(block, MAPVAR_CYCLES, compiler->cycles); // mapvar CYCLES,compiler->cycles
}
void adsp21062_device::generate_jump(drcuml_block *block, compiler_state *compiler, const opcode_desc *desc, bool delayslot, bool loopabort, bool clearint)
@@ -1883,7 +1883,7 @@ void adsp21062_device::generate_jump(drcuml_block *block, compiler_state *compil
// save branch target
if (desc->targetpc == BRANCH_TARGET_DYNAMIC)
{
- UML_MOV(block, mem(&m_core->jmpdest), I0); // mov [jmpdest],i0
+ UML_MOV(block, mem(&m_core->jmpdest), I0); // mov [jmpdest],i0
}
// compile delay slots if needed
@@ -1898,13 +1898,13 @@ void adsp21062_device::generate_jump(drcuml_block *block, compiler_state *compil
{
code_label skip_pop = compiler_temp.labelnum++;
- UML_MOV(block, mem(&m_core->interrupt_active), 0); // mov [interrupt_active],0
- UML_SHL(block, I1, 1, mem(&m_core->active_irq_num)); // shl i1,1,[active_irq_num]
- UML_XOR(block, IRPTL, IRPTL, I1); // xor IRPTL,i1
- UML_CMP(block, mem(&m_core->status_stkp), 0); // cmp [status_stkp],0
- UML_JMPc(block, COND_Z, skip_pop); // jz skip_pop
- UML_CALLH(block, *m_pop_status); // callh m_pop_status
- UML_LABEL(block, skip_pop); // skip_pop:
+ UML_MOV(block, mem(&m_core->interrupt_active), 0); // mov [interrupt_active],0
+ UML_SHL(block, I1, 1, mem(&m_core->active_irq_num)); // shl i1,1,[active_irq_num]
+ UML_XOR(block, IRPTL, IRPTL, I1); // xor IRPTL,i1
+ UML_CMP(block, mem(&m_core->status_stkp), 0); // cmp [status_stkp],0
+ UML_JMPc(block, COND_Z, skip_pop); // jz skip_pop
+ UML_CALLH(block, *m_pop_status); // callh m_pop_status
+ UML_LABEL(block, skip_pop); // skip_pop:
}
// loop abort
@@ -1919,14 +1919,14 @@ void adsp21062_device::generate_jump(drcuml_block *block, compiler_state *compil
{
generate_update_cycles(block, &compiler_temp, desc->targetpc, TRUE);
if (desc->flags & OPFLAG_INTRABLOCK_BRANCH)
- UML_JMP(block, desc->targetpc | 0x80000000); // jmp targetpc | 0x80000000
+ UML_JMP(block, desc->targetpc | 0x80000000); // jmp targetpc | 0x80000000
else
- UML_HASHJMP(block, 0, desc->targetpc, *m_nocode); // hashjmp 0,targetpc,nocode
+ UML_HASHJMP(block, 0, desc->targetpc, *m_nocode); // hashjmp 0,targetpc,nocode
}
else
{
generate_update_cycles(block, &compiler_temp, mem(&m_core->jmpdest), TRUE);
- UML_HASHJMP(block, 0, mem(&m_core->jmpdest), *m_nocode); // hashjmp 0,jmpdest,nocode
+ UML_HASHJMP(block, 0, mem(&m_core->jmpdest), *m_nocode); // hashjmp 0,jmpdest,nocode
}
// update compiler label
@@ -1934,7 +1934,7 @@ void adsp21062_device::generate_jump(drcuml_block *block, compiler_state *compil
/* reset the mapvar to the current cycles and account for skipped slots */
compiler->cycles += desc->skipslots;
- UML_MAPVAR(block, MAPVAR_CYCLES, compiler->cycles); // mapvar CYCLES,compiler->cycles
+ UML_MAPVAR(block, MAPVAR_CYCLES, compiler->cycles); // mapvar CYCLES,compiler->cycles
}
void adsp21062_device::generate_loop_jump(drcuml_block *block, compiler_state *compiler, const opcode_desc *desc)
@@ -1943,15 +1943,15 @@ void adsp21062_device::generate_loop_jump(drcuml_block *block, compiler_state *c
generate_update_cycles(block, compiler, desc->userdata0, TRUE);
/*
if (desc->flags & OPFLAG_INTRABLOCK_BRANCH)
- UML_JMP(block, desc->targetpc | 0x80000000); // jmp targetpc | 0x80000000
+ UML_JMP(block, desc->targetpc | 0x80000000); // jmp targetpc | 0x80000000
else
- UML_HASHJMP(block, 0, desc->targetpc, *m_nocode); // hashjmp 0,targetpc,nocode
- */
+ UML_HASHJMP(block, 0, desc->targetpc, *m_nocode); // hashjmp 0,targetpc,nocode
+ */
UML_HASHJMP(block, 0, desc->userdata0, *m_nocode);
/* reset the mapvar to the current cycles and account for skipped slots */
compiler->cycles += desc->skipslots;
- UML_MAPVAR(block, MAPVAR_CYCLES, compiler->cycles); // mapvar CYCLES,compiler->cycles
+ UML_MAPVAR(block, MAPVAR_CYCLES, compiler->cycles); // mapvar CYCLES,compiler->cycles
}
/*-------------------------------------------------
@@ -2002,25 +2002,25 @@ void adsp21062_device::generate_read_ureg(drcuml_block *block, compiler_state *c
UML_MOV(block, I0, mem(&m_core->dag2.b[ureg & 7]));
break;
- case 0x64: // PCSTK
+ case 0x64: // PCSTK
UML_LOAD(block, I0, &m_core->pcstack, PCSTKP, SIZE_DWORD, SCALE_x4);
break;
- case 0x70: // USTAT1
+ case 0x70: // USTAT1
UML_MOV(block, I0, mem(&m_core->ustat1));
break;
- case 0x71: // USTAT2
+ case 0x71: // USTAT2
UML_MOV(block, I0, mem(&m_core->ustat2));
break;
- case 0x79: // IRPTL
+ case 0x79: // IRPTL
UML_MOV(block, I0, mem(&m_core->irptl));
break;
- case 0x7a: // MODE2
+ case 0x7a: // MODE2
UML_MOV(block, I0, mem(&m_core->mode2));
break;
- case 0x7b: // MODE1
+ case 0x7b: // MODE1
UML_MOV(block, I0, mem(&m_core->mode1));
break;
- case 0x7c: // ASTAT
+ case 0x7c: // ASTAT
// construct from bits
if (!has_compute)
{
@@ -2111,20 +2111,20 @@ void adsp21062_device::generate_read_ureg(drcuml_block *block, compiler_state *c
UML_OR(block, I0, I0, I1);
}
break;
- case 0x7d: // IMASK
+ case 0x7d: // IMASK
UML_MOV(block, I0, mem(&m_core->imask));
break;
- case 0x7e: // STKY
+ case 0x7e: // STKY
UML_MOV(block, I0, mem(&m_core->stky));
break;
- case 0xdb: // PX
- UML_DMOV(block, I0, mem(&m_core->px)); // NOTE: this returns 64 bits
+ case 0xdb: // PX
+ UML_DMOV(block, I0, mem(&m_core->px)); // NOTE: this returns 64 bits
break;
- case 0xdc: // PX1 (bits 0-15 of PX)
+ case 0xdc: // PX1 (bits 0-15 of PX)
UML_MOV(block, I0, mem(&m_core->px));
UML_AND(block, I0, I0, 0xffff);
break;
- case 0xdd: // PX2 (bits 16-47 of PX)
+ case 0xdd: // PX2 (bits 16-47 of PX)
UML_DMOV(block, I0, mem(&m_core->px));
UML_DSHR(block, I0, I0, 16);
UML_DAND(block, I0, I0, 0xffffffff);
@@ -2138,7 +2138,7 @@ void adsp21062_device::generate_read_ureg(drcuml_block *block, compiler_state *c
/*-------------------------------------------------
- generate_write_ureg - contents of register I0 or 32-bit immediate data are written into UREG
+ generate_write_ureg - contents of register I0 or 32-bit immediate data are written into UREG
-------------------------------------------------*/
void adsp21062_device::generate_write_ureg(drcuml_block *block, compiler_state *compiler, const opcode_desc *desc, int ureg, bool imm, UINT32 data)
@@ -2187,31 +2187,31 @@ void adsp21062_device::generate_write_ureg(drcuml_block *block, compiler_state *
UML_MOV(block, PM_B(ureg & 7), imm ? data : I0);
break;
- case 0x64: // PCSTK
+ case 0x64: // PCSTK
fatalerror("generate_write_ureg: PCSTK");
break;
- case 0x65: // PCSTKP
+ case 0x65: // PCSTKP
UML_MOV(block, PCSTKP, imm ? data : I0);
break;
- case 0x67: // CURLCNTR
+ case 0x67: // CURLCNTR
UML_MOV(block, CURLCNTR, imm ? data : I0);
break;
- case 0x68: // LCNTR
+ case 0x68: // LCNTR
UML_MOV(block, LCNTR, imm ? data : I0);
break;
- case 0x70: // USTAT1
+ case 0x70: // USTAT1
UML_MOV(block, mem(&m_core->ustat1), imm ? data : I0);
break;
- case 0x71: // USTAT2
+ case 0x71: // USTAT2
UML_MOV(block, mem(&m_core->ustat2), imm ? data : I0);
break;
- case 0x79: // IRPTL
+ case 0x79: // IRPTL
UML_MOV(block, mem(&m_core->irptl), imm ? data : I0);
break;
- case 0x7a: // MODE2
+ case 0x7a: // MODE2
UML_MOV(block, mem(&m_core->mode2), imm ? data : I0);
break;
- case 0x7b: // MODE1
+ case 0x7b: // MODE1
// MODE1 needs to be written delayed
if (imm)
{
@@ -2226,17 +2226,17 @@ void adsp21062_device::generate_write_ureg(drcuml_block *block, compiler_state *
UML_MOV(block, mem(&m_core->mode1_delay_data), I0);
}
break;
- case 0x7c: // ASTAT
+ case 0x7c: // ASTAT
// TODO: needs bit break up
fatalerror("generate_write_ureg: ASTAT");
break;
- case 0x7d: // IMASK
+ case 0x7d: // IMASK
UML_MOV(block, mem(&m_core->imask), imm ? data : I0);
break;
- case 0x7e: // STKY
+ case 0x7e: // STKY
UML_MOV(block, mem(&m_core->stky), imm ? data : I0);
break;
- case 0xdb: // PX
+ case 0xdb: // PX
if (imm)
{
fatalerror("generate_write_ureg %02X with immediate!", ureg);
@@ -2246,7 +2246,7 @@ void adsp21062_device::generate_write_ureg(drcuml_block *block, compiler_state *
UML_DMOV(block, mem(&m_core->px), I0);
}
break;
- case 0xdc: // PX1 (bits 0-15 of PX)
+ case 0xdc: // PX1 (bits 0-15 of PX)
if (imm)
{
UML_DAND(block, mem(&m_core->px), mem(&m_core->px), ~0xffff);
@@ -2260,7 +2260,7 @@ void adsp21062_device::generate_write_ureg(drcuml_block *block, compiler_state *
UML_DOR(block, mem(&m_core->px), mem(&m_core->px), I1);
}
break;
- case 0xdd: // PX2 (bits 16-47 of PX)
+ case 0xdd: // PX2 (bits 16-47 of PX)
if (imm)
{
UML_DAND(block, mem(&m_core->px), mem(&m_core->px), 0xffff);
@@ -2268,7 +2268,7 @@ void adsp21062_device::generate_write_ureg(drcuml_block *block, compiler_state *
}
else
{
- UML_DAND(block, mem(&m_core->px), mem(&m_core->px), 0xffff);
+ UML_DAND(block, mem(&m_core->px), mem(&m_core->px), 0xffff);
UML_DSHL(block, I0, I0, 16);
UML_DOR(block, mem(&m_core->px), mem(&m_core->px), I0);
}
@@ -2286,12 +2286,12 @@ int adsp21062_device::generate_opcode(drcuml_block *block, compiler_state *compi
switch ((opcode >> 45) & 7)
{
- case 0: // subops
+ case 0: // subops
{
UINT32 subop = (opcode >> 40) & 0x1f;
switch (subop)
{
- case 0x00: // NOP / idle |000|00000|
+ case 0x00: // NOP / idle |000|00000|
if (opcode & U64(0x008000000000))
{
// IDLE
@@ -2306,7 +2306,7 @@ int adsp21062_device::generate_opcode(drcuml_block *block, compiler_state *compi
}
break;
- case 0x01: // compute |000|00001|
+ case 0x01: // compute |000|00001|
{
int cond = (opcode >> 33) & 0x1f;
@@ -2326,7 +2326,7 @@ int adsp21062_device::generate_opcode(drcuml_block *block, compiler_state *compi
return TRUE;
}
- case 0x02: // immediate shift |000|00010|
+ case 0x02: // immediate shift |000|00010|
{
int shiftop = (opcode >> 16) & 0x3f;
int rn = (opcode >> 4) & 0xf;
@@ -2342,15 +2342,15 @@ int adsp21062_device::generate_opcode(drcuml_block *block, compiler_state *compi
skip_label = compiler->labelnum++;
generate_if_condition(block, compiler, desc, cond, skip_label);
}
-
+
generate_shift_imm(block, compiler, desc, data, shiftop, rn, rx);
-
- if (has_condition)
- UML_LABEL(block, skip_label);
+
+ if (has_condition)
+ UML_LABEL(block, skip_label);
return TRUE;
}
- case 0x04: // compute / modify |000|00100|
+ case 0x04: // compute / modify |000|00100|
{
int cond = (opcode >> 33) & 0x1f;
int g = (opcode >> 38) & 0x1;
@@ -2387,7 +2387,7 @@ int adsp21062_device::generate_opcode(drcuml_block *block, compiler_state *compi
return TRUE;
}
- case 0x06: // direct jump|call |000|00110|
+ case 0x06: // direct jump|call |000|00110|
{
int b = (opcode >> 39) & 0x1;
int j = (opcode >> 26) & 0x1;
@@ -2405,7 +2405,7 @@ int adsp21062_device::generate_opcode(drcuml_block *block, compiler_state *compi
}
if (b) // call
{
- generate_call(block, compiler, desc, j != 0);
+ generate_call(block, compiler, desc, j != 0);
}
else // jump
{
@@ -2416,7 +2416,7 @@ int adsp21062_device::generate_opcode(drcuml_block *block, compiler_state *compi
return TRUE;
}
- case 0x07: // direct jump|call |000|00111|
+ case 0x07: // direct jump|call |000|00111|
{
int b = (opcode >> 39) & 0x1;
int j = (opcode >> 26) & 0x1;
@@ -2445,7 +2445,7 @@ int adsp21062_device::generate_opcode(drcuml_block *block, compiler_state *compi
return TRUE;
}
- case 0x08: // indirect jump|call / compute |000|01000|
+ case 0x08: // indirect jump|call / compute |000|01000|
{
int la = (opcode >> 38) & 0x1;
int ci = (opcode >> 24) & 0x1;
@@ -2508,7 +2508,7 @@ int adsp21062_device::generate_opcode(drcuml_block *block, compiler_state *compi
return TRUE;
}
- case 0x09: // indirect jump|call / compute |000|01001|
+ case 0x09: // indirect jump|call / compute |000|01001|
{
int la = (opcode >> 38) & 0x1;
int ci = (opcode >> 24) & 0x1;
@@ -2532,7 +2532,7 @@ int adsp21062_device::generate_opcode(drcuml_block *block, compiler_state *compi
{
generate_jump(block, compiler, desc, j != 0, la != 0, ci != 0);
}
-
+
UML_LABEL(block, label_else);
generate_compute(block, compiler, desc);
}
@@ -2565,12 +2565,12 @@ int adsp21062_device::generate_opcode(drcuml_block *block, compiler_state *compi
return TRUE;
}
- case 0x0a: // return from subroutine / compute |000|01010|
+ case 0x0a: // return from subroutine / compute |000|01010|
{
int cond = (opcode >> 33) & 0x1f;
int j = (opcode >> 26) & 0x1;
int e = (opcode >> 25) & 0x1;
- //int lr = (opcode >> 24) & 0x1;
+ //int lr = (opcode >> 24) & 0x1;
// TODO: loop re-entry
@@ -2583,7 +2583,7 @@ int adsp21062_device::generate_opcode(drcuml_block *block, compiler_state *compi
UML_CALLH(block, *m_pop_pc);
generate_jump(block, compiler, desc, j != 0, false, false);
-
+
UML_LABEL(block, label_else);
generate_compute(block, compiler, desc);
}
@@ -2610,7 +2610,7 @@ int adsp21062_device::generate_opcode(drcuml_block *block, compiler_state *compi
return TRUE;
}
- case 0x0b: // return from interrupt / compute |000|01011|
+ case 0x0b: // return from interrupt / compute |000|01011|
{
int cond = (opcode >> 33) & 0x1f;
int j = (opcode >> 26) & 0x1;
@@ -2619,15 +2619,15 @@ int adsp21062_device::generate_opcode(drcuml_block *block, compiler_state *compi
code_label skip_pop = compiler->labelnum++;
- UML_MOV(block, mem(&m_core->interrupt_active), 0); // mov [interrupt_active],0
- UML_MOV(block, I0, 1); // mov i0,1
- UML_SHL(block, I0, I0, mem(&m_core->active_irq_num)); // shl i0,[active_irq_num]
- UML_XOR(block, IRPTL, IRPTL, I0); // xor IRPTL,i0
- UML_CMP(block, mem(&m_core->status_stkp), 0); // cmp [status_stkp],0
- UML_JMPc(block, COND_Z, skip_pop); // jz skip_pop
- UML_CALLH(block, *m_pop_status); // callh m_pop_status
+ UML_MOV(block, mem(&m_core->interrupt_active), 0); // mov [interrupt_active],0
+ UML_MOV(block, I0, 1); // mov i0,1
+ UML_SHL(block, I0, I0, mem(&m_core->active_irq_num)); // shl i0,[active_irq_num]
+ UML_XOR(block, IRPTL, IRPTL, I0); // xor IRPTL,i0
+ UML_CMP(block, mem(&m_core->status_stkp), 0); // cmp [status_stkp],0
+ UML_JMPc(block, COND_Z, skip_pop); // jz skip_pop
+ UML_CALLH(block, *m_pop_status); // callh m_pop_status
- UML_LABEL(block, skip_pop); // skip_pop:
+ UML_LABEL(block, skip_pop); // skip_pop:
// TODO: check interrupts
@@ -2667,7 +2667,7 @@ int adsp21062_device::generate_opcode(drcuml_block *block, compiler_state *compi
return TRUE;
}
- case 0x0c: // do until counter expired |000|01100|
+ case 0x0c: // do until counter expired |000|01100|
{
UINT16 data = (UINT16)(opcode >> 24);
int offset = SIGN_EXTEND24(opcode & 0xffffff);
@@ -2680,7 +2680,7 @@ int adsp21062_device::generate_opcode(drcuml_block *block, compiler_state *compi
UML_MOV(block, I0, desc->pc + 1);
UML_CALLH(block, *m_push_pc);
- // push loop
+ // push loop
UML_MOV(block, I0, data);
UML_MOV(block, I1, address);
UML_CALLH(block, *m_push_loop);
@@ -2688,7 +2688,7 @@ int adsp21062_device::generate_opcode(drcuml_block *block, compiler_state *compi
return TRUE;
}
- case 0x0d: // do until counter expired |000|01101|
+ case 0x0d: // do until counter expired |000|01101|
{
int ureg = (opcode >> 32) & 0xff;
int offset = SIGN_EXTEND24(opcode & 0xffffff);
@@ -2703,14 +2703,14 @@ int adsp21062_device::generate_opcode(drcuml_block *block, compiler_state *compi
UML_MOV(block, I0, desc->pc + 1);
UML_CALLH(block, *m_push_pc);
- // push loop
+ // push loop
UML_MOV(block, I0, I3);
UML_MOV(block, I1, address);
UML_CALLH(block, *m_push_loop);
return TRUE;
}
- case 0x0e: // do until |000|01110|
+ case 0x0e: // do until |000|01110|
{
int offset = SIGN_EXTEND24(opcode & 0xffffff);
UINT32 address = desc->pc + offset;
@@ -2726,7 +2726,7 @@ int adsp21062_device::generate_opcode(drcuml_block *block, compiler_state *compi
return TRUE;
}
- case 0x0f: // immediate data -> ureg |000|01111|
+ case 0x0f: // immediate data -> ureg |000|01111|
{
int ureg = (opcode >> 32) & 0xff;
UINT32 data = (UINT32)opcode;
@@ -2735,7 +2735,7 @@ int adsp21062_device::generate_opcode(drcuml_block *block, compiler_state *compi
return TRUE;
}
- case 0x10: // ureg <-> DM|PM (direct) |000|100|G|D|
+ case 0x10: // ureg <-> DM|PM (direct) |000|100|G|D|
case 0x11:
case 0x12:
case 0x13:
@@ -2754,7 +2754,7 @@ int adsp21062_device::generate_opcode(drcuml_block *block, compiler_state *compi
if (g)
{
// PM
- if (ureg == 0xdb) // PX is 48-bit
+ if (ureg == 0xdb) // PX is 48-bit
UML_CALLH(block, *m_pm_write48);
else
UML_CALLH(block, *m_pm_write32);
@@ -2771,7 +2771,7 @@ int adsp21062_device::generate_opcode(drcuml_block *block, compiler_state *compi
if (g)
{
// PM
- if (ureg == 0xdb) // PX is 48-bit
+ if (ureg == 0xdb) // PX is 48-bit
UML_CALLH(block, *m_pm_read48);
else
UML_CALLH(block, *m_pm_read32);
@@ -2787,7 +2787,7 @@ int adsp21062_device::generate_opcode(drcuml_block *block, compiler_state *compi
return TRUE;
}
- case 0x14: // system register bit manipulation |000|10100|
+ case 0x14: // system register bit manipulation |000|10100|
{
int bop = (opcode >> 37) & 0x7;
int sreg = (opcode >> 32) & 0xf;
@@ -2795,7 +2795,7 @@ int adsp21062_device::generate_opcode(drcuml_block *block, compiler_state *compi
switch (bop)
{
- case 0: // SET
+ case 0: // SET
{
switch (sreg)
{
@@ -2816,7 +2816,7 @@ int adsp21062_device::generate_opcode(drcuml_block *block, compiler_state *compi
compiler->mode1_delay.data = data;
compiler->mode1_delay.mode = MODE1_SET;
break;
- case 0xc: // ASTAT
+ case 0xc: // ASTAT
// TODO: does this need delay?
if (data & ASTAT_FLAGS::AZ)
UML_MOV(block, ASTAT_AZ, 1);
@@ -2876,7 +2876,7 @@ int adsp21062_device::generate_opcode(drcuml_block *block, compiler_state *compi
}
return TRUE;
}
- case 1: // CLEAR
+ case 1: // CLEAR
{
switch (sreg)
{
@@ -2957,7 +2957,7 @@ int adsp21062_device::generate_opcode(drcuml_block *block, compiler_state *compi
}
return TRUE;
}
- case 2: // TOGGLE
+ case 2: // TOGGLE
{
switch (sreg)
{
@@ -2995,7 +2995,7 @@ int adsp21062_device::generate_opcode(drcuml_block *block, compiler_state *compi
}
return TRUE;
}
- case 4: // TEST
+ case 4: // TEST
{
switch (sreg)
{
@@ -3047,7 +3047,7 @@ int adsp21062_device::generate_opcode(drcuml_block *block, compiler_state *compi
}
return TRUE;
}
- case 5: // XOR
+ case 5: // XOR
{
return FALSE;
}
@@ -3058,13 +3058,13 @@ int adsp21062_device::generate_opcode(drcuml_block *block, compiler_state *compi
return TRUE;
}
- case 0x16: // I register modify / bit-reverse |000|10110|
+ case 0x16: // I register modify / bit-reverse |000|10110|
{
- if (opcode & U64(0x008000000000)) // bit reverse
+ if (opcode & U64(0x008000000000)) // bit reverse
{
return FALSE;
}
- else // modify
+ else // modify
{
int g = (opcode >> 38) & 0x1;
int i = (opcode >> 32) & 0x7;
@@ -3085,7 +3085,7 @@ int adsp21062_device::generate_opcode(drcuml_block *block, compiler_state *compi
}
}
- case 0x17: // push|pop stacks / flush cache |000|10111|
+ case 0x17: // push|pop stacks / flush cache |000|10111|
{
if (opcode & U64(0x008000000000))
{
@@ -3115,10 +3115,10 @@ int adsp21062_device::generate_opcode(drcuml_block *block, compiler_state *compi
return TRUE;
}
- case 0x18: // cjump |000|11000|
+ case 0x18: // cjump |000|11000|
return FALSE;
- case 0x19: // rframe |000|11001|
+ case 0x19: // rframe |000|11001|
return FALSE;
default:
@@ -3127,7 +3127,7 @@ int adsp21062_device::generate_opcode(drcuml_block *block, compiler_state *compi
break;
}
- case 1: // compute / dreg <-> DM / dreg <-> PM |001|
+ case 1: // compute / dreg <-> DM / dreg <-> PM |001|
{
int pm_dreg = (opcode >> 23) & 0xf;
int pmm = (opcode >> 27) & 0x7;
@@ -3202,7 +3202,7 @@ int adsp21062_device::generate_opcode(drcuml_block *block, compiler_state *compi
return TRUE;
}
- case 2: // compute / ureg <-> DM|PM, register modify |010|
+ case 2: // compute / ureg <-> DM|PM, register modify |010|
{
int u = (opcode >> 44) & 0x1;
int i = (opcode >> 41) & 0x7;
@@ -3245,18 +3245,18 @@ int adsp21062_device::generate_opcode(drcuml_block *block, compiler_state *compi
generate_compute(block, compiler, desc);
// transfer
- UML_MOV(block, I1, (g) ? PM_I(i) : DM_I(i)); // mov i1,dm|pm[i]
- if (u == 0) // pre-modify without update
- UML_ADD(block, I1, I1, (g) ? PM_M(m) : DM_M(m)); // add i1,i1,dm|pm[m]
+ UML_MOV(block, I1, (g) ? PM_I(i) : DM_I(i)); // mov i1,dm|pm[i]
+ if (u == 0) // pre-modify without update
+ UML_ADD(block, I1, I1, (g) ? PM_M(m) : DM_M(m)); // add i1,i1,dm|pm[m]
if (temp_ureg)
- UML_MOV(block, I0, mem(&m_core->dreg_temp)); // mov i0,[m_core->dreg_temp]
+ UML_MOV(block, I0, mem(&m_core->dreg_temp)); // mov i0,[m_core->dreg_temp]
else
generate_read_ureg(block, compiler, desc, ureg, ureg_is_astat);
- if (ureg == 0xdb && (g)) // PX is 48-bit when writing to PM
- UML_CALLH(block, *m_pm_write48); // callh pm_write48
+ if (ureg == 0xdb && (g)) // PX is 48-bit when writing to PM
+ UML_CALLH(block, *m_pm_write48); // callh pm_write48
else
- UML_CALLH(block, (g) ? *m_pm_write32 : *m_dm_write32); // callh dm|pm_write32
+ UML_CALLH(block, (g) ? *m_pm_write32 : *m_dm_write32); // callh dm|pm_write32
}
else
{
@@ -3266,23 +3266,23 @@ int adsp21062_device::generate_opcode(drcuml_block *block, compiler_state *compi
generate_compute(block, compiler, desc);
// transfer
- UML_MOV(block, I1, (g) ? PM_I(i) : DM_I(i)); // mov i1,dm|pm[i]
- if (u == 0) // pre-modify without update
- UML_ADD(block, I1, I1, (g) ? PM_M(m) : DM_M(m)); // add i1,i1,dm|pm[m]
+ UML_MOV(block, I1, (g) ? PM_I(i) : DM_I(i)); // mov i1,dm|pm[i]
+ if (u == 0) // pre-modify without update
+ UML_ADD(block, I1, I1, (g) ? PM_M(m) : DM_M(m)); // add i1,i1,dm|pm[m]
- if (ureg == 0xdb && (g)) // PX is 48-bit when reading from PM
- UML_CALLH(block, *m_pm_read48); // callh pm_read48
+ if (ureg == 0xdb && (g)) // PX is 48-bit when reading from PM
+ UML_CALLH(block, *m_pm_read48); // callh pm_read48
else
- UML_CALLH(block, (g) ? *m_pm_read32 : *m_dm_read32); // callh dm|pm_read32
+ UML_CALLH(block, (g) ? *m_pm_read32 : *m_dm_read32); // callh dm|pm_read32
generate_write_ureg(block, compiler, desc, ureg, false, 0);
}
- if (u != 0) // post-modify with update
+ if (u != 0) // post-modify with update
{
if (g)
- UML_ADD(block, PM_I(i), PM_I(i), PM_M(m)); // add pm[i],pm[m]
+ UML_ADD(block, PM_I(i), PM_I(i), PM_M(m)); // add pm[i],pm[m]
else
- UML_ADD(block, DM_I(i), DM_I(i), DM_M(m)); // add dm[i],dm[m]
+ UML_ADD(block, DM_I(i), DM_I(i), DM_M(m)); // add dm[i],dm[m]
generate_update_circular_buffer(block, compiler, desc, g, i);
}
@@ -3295,7 +3295,7 @@ int adsp21062_device::generate_opcode(drcuml_block *block, compiler_state *compi
case 3:
{
- if (opcode & U64(0x100000000000)) // compute / ureg <-> ureg |011|1|
+ if (opcode & U64(0x100000000000)) // compute / ureg <-> ureg |011|1|
{
int src_ureg = (opcode >> 36) & 0xff;
int dst_ureg = (opcode >> 23) & 0xff;
@@ -3343,7 +3343,7 @@ int adsp21062_device::generate_opcode(drcuml_block *block, compiler_state *compi
return TRUE;
}
- else // compute / dreg <-> DM|PM, immediate modify |011|0|
+ else // compute / dreg <-> DM|PM, immediate modify |011|0|
{
int cond = (opcode >> 33) & 0x1f;
int u = (opcode >> 38) & 0x1;
@@ -3362,7 +3362,7 @@ int adsp21062_device::generate_opcode(drcuml_block *block, compiler_state *compi
skip_label = compiler->labelnum++;
generate_if_condition(block, compiler, desc, cond, skip_label);
}
- if (d)
+ if (d)
{
// DREG -> DM|PM
bool temp_dreg = false;
@@ -3377,14 +3377,14 @@ int adsp21062_device::generate_opcode(drcuml_block *block, compiler_state *compi
generate_compute(block, compiler, desc);
// transfer
- UML_MOV(block, I1, (g) ? PM_I(i) : DM_I(i)); // mov i1,dm|pm[i]
- if (u == 0) // pre-modify without update
- UML_ADD(block, I1, I1, mod); // add i1,i1,mod
+ UML_MOV(block, I1, (g) ? PM_I(i) : DM_I(i)); // mov i1,dm|pm[i]
+ if (u == 0) // pre-modify without update
+ UML_ADD(block, I1, I1, mod); // add i1,i1,mod
if (temp_dreg)
- UML_MOV(block, I0, mem(&m_core->dreg_temp)); // mov i0,[m_core->dreg_temp]
+ UML_MOV(block, I0, mem(&m_core->dreg_temp)); // mov i0,[m_core->dreg_temp]
else
- UML_MOV(block, I0, REG(dreg)); // mov i0,reg[dreg]
- UML_CALLH(block, (g) ? *m_pm_write32 : *m_dm_write32); // callh dm|pm_write32
+ UML_MOV(block, I0, REG(dreg)); // mov i0,reg[dreg]
+ UML_CALLH(block, (g) ? *m_pm_write32 : *m_dm_write32); // callh dm|pm_write32
}
else
{
@@ -3394,19 +3394,19 @@ int adsp21062_device::generate_opcode(drcuml_block *block, compiler_state *compi
generate_compute(block, compiler, desc);
// transfer
- UML_MOV(block, I1, (g) ? PM_I(i) : DM_I(i)); // mov i1,dm|pm[i]
- if (u == 0) // pre-modify without update
- UML_ADD(block, I1, I1, mod); // add i1,i1,mod
- UML_CALLH(block, (g) ? *m_pm_read32 : *m_dm_read32); // callh dm|pm_read32
- UML_MOV(block, REG(dreg), I0); // mov reg[dreg],i0
+ UML_MOV(block, I1, (g) ? PM_I(i) : DM_I(i)); // mov i1,dm|pm[i]
+ if (u == 0) // pre-modify without update
+ UML_ADD(block, I1, I1, mod); // add i1,i1,mod
+ UML_CALLH(block, (g) ? *m_pm_read32 : *m_dm_read32); // callh dm|pm_read32
+ UML_MOV(block, REG(dreg), I0); // mov reg[dreg],i0
}
- if (u != 0) // post-modify with update
+ if (u != 0) // post-modify with update
{
if (g)
- UML_ADD(block, PM_I(i), PM_I(i), mod); // add pm[i],mod
+ UML_ADD(block, PM_I(i), PM_I(i), mod); // add pm[i],mod
else
- UML_ADD(block, DM_I(i), DM_I(i), mod); // add dm[i],mod
+ UML_ADD(block, DM_I(i), DM_I(i), mod); // add dm[i],mod
generate_update_circular_buffer(block, compiler, desc, g, i);
}
@@ -3420,7 +3420,7 @@ int adsp21062_device::generate_opcode(drcuml_block *block, compiler_state *compi
case 4:
{
- if (opcode & U64(0x100000000000)) // immediate data -> DM|PM |100|1|
+ if (opcode & U64(0x100000000000)) // immediate data -> DM|PM |100|1|
{
int i = (opcode >> 41) & 0x7;
int m = (opcode >> 38) & 0x7;
@@ -3441,14 +3441,14 @@ int adsp21062_device::generate_opcode(drcuml_block *block, compiler_state *compi
UML_MOV(block, I0, data);
UML_MOV(block, I1, DM_I(i));
UML_CALLH(block, *m_dm_write32);
- UML_ADD(block, DM_I(i), DM_I(i), DM_M(m));
+ UML_ADD(block, DM_I(i), DM_I(i), DM_M(m));
}
generate_update_circular_buffer(block, compiler, desc, g, i);
return TRUE;
}
- else // immediate shift / dreg <-> DM|PM |100|0|
+ else // immediate shift / dreg <-> DM|PM |100|0|
{
int i = (opcode >> 41) & 0x7;
int m = (opcode >> 38) & 0x7;
@@ -3484,12 +3484,12 @@ int adsp21062_device::generate_opcode(drcuml_block *block, compiler_state *compi
generate_shift_imm(block, compiler, desc, data, shiftop, rn, rx);
// transfer
- UML_MOV(block, I1, (g) ? PM_I(i) : DM_I(i)); // mov i1,dm|pm[i]
+ UML_MOV(block, I1, (g) ? PM_I(i) : DM_I(i)); // mov i1,dm|pm[i]
if (temp_dreg)
- UML_MOV(block, I0, mem(&m_core->dreg_temp)); // mov i0,[m_core->dreg_temp]
+ UML_MOV(block, I0, mem(&m_core->dreg_temp)); // mov i0,[m_core->dreg_temp]
else
- UML_MOV(block, I0, REG(dreg)); // mov i0,reg[dreg]
- UML_CALLH(block, (g) ? *m_pm_write32 : *m_dm_write32); // callh dm|pm_write32
+ UML_MOV(block, I0, REG(dreg)); // mov i0,reg[dreg]
+ UML_CALLH(block, (g) ? *m_pm_write32 : *m_dm_write32); // callh dm|pm_write32
}
else
{
@@ -3499,9 +3499,9 @@ int adsp21062_device::generate_opcode(drcuml_block *block, compiler_state *compi
generate_shift_imm(block, compiler, desc, data, shiftop, rn, rx);
// transfer
- UML_MOV(block, I1, (g) ? PM_I(i) : DM_I(i)); // mov i1,dm|pm[i]
- UML_CALLH(block, (g) ? *m_pm_read32 : *m_dm_read32); // callh dm|pm_read32
- UML_MOV(block, REG(dreg), I0); // mov reg[dreg],i0
+ UML_MOV(block, I1, (g) ? PM_I(i) : DM_I(i)); // mov i1,dm|pm[i]
+ UML_CALLH(block, (g) ? *m_pm_read32 : *m_dm_read32); // callh dm|pm_read32
+ UML_MOV(block, REG(dreg), I0); // mov reg[dreg],i0
}
// update I
@@ -3520,42 +3520,42 @@ int adsp21062_device::generate_opcode(drcuml_block *block, compiler_state *compi
break;
}
- case 5: // ureg <-> DM|PM (indirect) |101|
+ case 5: // ureg <-> DM|PM (indirect) |101|
{
int g = (opcode >> 44) & 1;
int d = (opcode >> 40) & 1;
int i = (opcode >> 41) & 0x7;
int ureg = (opcode >> 32) & 0xff;
UINT32 offset = (UINT32)opcode;
-
+
if (d)
{
// UREG -> DM|PM
- UML_ADD(block, I1, (g) ? PM_I(i) : DM_I(i), offset); // add i1,dm|pm[i],offset
+ UML_ADD(block, I1, (g) ? PM_I(i) : DM_I(i), offset); // add i1,dm|pm[i],offset
generate_read_ureg(block, compiler, desc, ureg, false);
- if (ureg == 0xdb && (g)) // PX is 48-bit when writing to PM
- UML_CALLH(block, *m_pm_write48); // callh pm_write48
+ if (ureg == 0xdb && (g)) // PX is 48-bit when writing to PM
+ UML_CALLH(block, *m_pm_write48); // callh pm_write48
else
- UML_CALLH(block, (g) ? *m_pm_write32 : *m_dm_write32); // callh dm|pm_write32
+ UML_CALLH(block, (g) ? *m_pm_write32 : *m_dm_write32); // callh dm|pm_write32
}
else
{
// DM|PM -> UREG
- UML_ADD(block, I1, (g) ? PM_I(i) : DM_I(i), offset); // add i1,dm|pm[i],offset
+ UML_ADD(block, I1, (g) ? PM_I(i) : DM_I(i), offset); // add i1,dm|pm[i],offset
- if (ureg == 0xdb && (g)) // PX is 48-bit when reading from PM
- UML_CALLH(block, *m_pm_read48); // callh pm_read48
+ if (ureg == 0xdb && (g)) // PX is 48-bit when reading from PM
+ UML_CALLH(block, *m_pm_read48); // callh pm_read48
else
- UML_CALLH(block, (g) ? *m_pm_read32 : *m_dm_read32); // callh dm|pm_read32
+ UML_CALLH(block, (g) ? *m_pm_read32 : *m_dm_read32); // callh dm|pm_read32
generate_write_ureg(block, compiler, desc, ureg, false, 0);
}
return TRUE;
}
- case 6: // indirect jump / compute / dreg <-> DM |110|
+ case 6: // indirect jump / compute / dreg <-> DM |110|
{
int d = (opcode >> 44) & 0x1;
int dmi = (opcode >> 41) & 0x7;
@@ -3616,7 +3616,7 @@ int adsp21062_device::generate_opcode(drcuml_block *block, compiler_state *compi
return TRUE;
}
- case 7: // indirect jump / compute / dreg <-> DM |111|
+ case 7: // indirect jump / compute / dreg <-> DM |111|
{
int d = (opcode >> 44) & 0x1;
int dmi = (opcode >> 41) & 0x7;
@@ -3698,7 +3698,7 @@ void adsp21062_device::generate_compute(drcuml_block *block, compiler_state *com
int ry = (opcode >> 0) & 0xf;
int ps = (opcode >> 16) & 0xf;
- if (opcode & 0x400000) // multi-function operation
+ if (opcode & 0x400000) // multi-function operation
{
UINT32 multiop = (opcode >> 16) & 0x3f;
int fm = rs;
@@ -3710,65 +3710,65 @@ void adsp21062_device::generate_compute(drcuml_block *block, compiler_state *com
switch (multiop)
{
- case 0x00: // Rn = MRxx
- {
+ case 0x00: // Rn = MRxx
+ {
generate_unimplemented_compute(block, compiler, desc);
return;
}
- case 0x01: // MRxx = Rn
+ case 0x01: // MRxx = Rn
{
int ai = rs;
switch (ai)
{
- case 0x00: // MR0F
+ case 0x00: // MR0F
UML_DAND(block, MRF, MRF, U64(0xffffffff00000000));
UML_AND(block, I0, REG(rn), 0xffffffff);
UML_DOR(block, MRF, MRF, I0);
break;
- case 0x01: // MR1F
+ case 0x01: // MR1F
UML_DAND(block, MRF, MRF, U64(0x00000000ffffffff));
UML_DSHL(block, I0, REG(rn), 32);
UML_DOR(block, MRF, MRF, I0);
- break;
- case 0x04: // MR0B
+ break;
+ case 0x04: // MR0B
UML_DAND(block, MRB, MRB, U64(0xffffffff00000000));
UML_AND(block, I0, REG(rn), 0xffffffff);
UML_DOR(block, MRB, MRB, I0);
break;
- case 0x05: // MR1B
+ case 0x05: // MR1B
UML_DAND(block, MRB, MRB, U64(0x00000000ffffffff));
UML_DSHL(block, I0, REG(rn), 32);
UML_DOR(block, MRB, MRB, I0);
break;
- case 0x02: // MR2F
- case 0x06: // MR2B
+ case 0x02: // MR2F
+ case 0x06: // MR2B
generate_unimplemented_compute(block, compiler, desc);
return;
}
return;
}
- case 0x07: // Ra = Rx + Ry, Rs = Rx - Ry
- case 0x0f: // Fa = Fx + Fy, Fs = Fx - Fy
- case 0x06: // Rm = R3-0 * R7-4 (SSFR), Ra = (R11-8 + R15-12) / 2
- case 0x08: // MRF = MRF + R3-0 * R7-4 (SSF), Ra = R11-8 + R15-12
- case 0x09: // MRF = MRF + R3-0 * R7-4 (SSF), Ra = R11-8 - R15-12
- case 0x0a: // MRF = MRF + R3-0 * R7-4 (SSF), Ra = (R11-8 + R15-12) / 2
- case 0x0c: // Rm = MRF + R3-0 * R7-4 (SSFR), Ra = R11-8 + R15-12
- case 0x0d: // Rm = MRF + R3-0 * R7-4 (SSFR), Ra = R11-8 - R15-12
- case 0x0e: // Rm = MRF + R3-0 * R7-4 (SSFR), Ra = (R11-8 + R15-12) / 2
- case 0x10: // MRF = MRF - R3-0 * R7-4 (SSF), Ra = R11-8 + R15-12
- case 0x11: // MRF = MRF - R3-0 * R7-4 (SSF), Ra = R11-8 - R15-12
- case 0x12: // MRF = MRF - R3-0 * R7-4 (SSF), Ra = (R11-8 + R15-12) / 2
- case 0x14: // Rm = MRF - R3-0 * R7-4 (SSFR), Ra = R11-8 + R15-12
- case 0x15: // Rm = MRF - R3-0 * R7-4 (SSFR), Ra = R11-8 - R15-12
- case 0x16: // Rm = MRF - R3-0 * R7-4 (SSFR), Ra = (R11-8 + R15-12) / 2
+ case 0x07: // Ra = Rx + Ry, Rs = Rx - Ry
+ case 0x0f: // Fa = Fx + Fy, Fs = Fx - Fy
+ case 0x06: // Rm = R3-0 * R7-4 (SSFR), Ra = (R11-8 + R15-12) / 2
+ case 0x08: // MRF = MRF + R3-0 * R7-4 (SSF), Ra = R11-8 + R15-12
+ case 0x09: // MRF = MRF + R3-0 * R7-4 (SSF), Ra = R11-8 - R15-12
+ case 0x0a: // MRF = MRF + R3-0 * R7-4 (SSF), Ra = (R11-8 + R15-12) / 2
+ case 0x0c: // Rm = MRF + R3-0 * R7-4 (SSFR), Ra = R11-8 + R15-12
+ case 0x0d: // Rm = MRF + R3-0 * R7-4 (SSFR), Ra = R11-8 - R15-12
+ case 0x0e: // Rm = MRF + R3-0 * R7-4 (SSFR), Ra = (R11-8 + R15-12) / 2
+ case 0x10: // MRF = MRF - R3-0 * R7-4 (SSF), Ra = R11-8 + R15-12
+ case 0x11: // MRF = MRF - R3-0 * R7-4 (SSF), Ra = R11-8 - R15-12
+ case 0x12: // MRF = MRF - R3-0 * R7-4 (SSF), Ra = (R11-8 + R15-12) / 2
+ case 0x14: // Rm = MRF - R3-0 * R7-4 (SSFR), Ra = R11-8 + R15-12
+ case 0x15: // Rm = MRF - R3-0 * R7-4 (SSFR), Ra = R11-8 - R15-12
+ case 0x16: // Rm = MRF - R3-0 * R7-4 (SSFR), Ra = (R11-8 + R15-12) / 2
generate_unimplemented_compute(block, compiler, desc);
return;
- case 0x1c: // Fm = F3-0 * F7-4, Fa = (F11-8 + F15-12) / 2
+ case 0x1c: // Fm = F3-0 * F7-4, Fa = (F11-8 + F15-12) / 2
generate_unimplemented_compute(block, compiler, desc);
return;
@@ -3802,10 +3802,10 @@ void adsp21062_device::generate_compute(drcuml_block *block, compiler_state *com
if (AZ_CALC_REQUIRED) UML_OR(block, ASTAT_AZ, ASTAT_AZ, I0);
if (AN_CALC_REQUIRED) UML_OR(block, ASTAT_AN, ASTAT_AN, I1);
- if (AV_CALC_REQUIRED) UML_MOV(block, ASTAT_AV, 0); // TODO
+ if (AV_CALC_REQUIRED) UML_MOV(block, ASTAT_AV, 0); // TODO
if (AC_CALC_REQUIRED) UML_MOV(block, ASTAT_AC, 0);
if (AS_CALC_REQUIRED) UML_MOV(block, ASTAT_AS, 0);
- if (AI_CALC_REQUIRED) UML_MOV(block, ASTAT_AI, 0); // TODO
+ if (AI_CALC_REQUIRED) UML_MOV(block, ASTAT_AI, 0); // TODO
if (MN_CALC_REQUIRED)
UML_FSCMP(block, F0, mem(&m_core->fp0));
@@ -3817,7 +3817,7 @@ void adsp21062_device::generate_compute(drcuml_block *block, compiler_state *com
UML_ICOPYFS(block, REG(ps), F5);
return;
- case 0x04: // Rm = R3-0 * R7-4 (SSFR), Ra = R11-8 + R15-12
+ case 0x04: // Rm = R3-0 * R7-4 (SSFR), Ra = R11-8 + R15-12
UML_DSEXT(block, I0, REG(fxm), SIZE_DWORD);
UML_DSEXT(block, I1, REG(fym), SIZE_DWORD);
UML_DMULS(block, I0, I0, I0, I1);
@@ -3837,7 +3837,7 @@ void adsp21062_device::generate_compute(drcuml_block *block, compiler_state *com
UML_MOV(block, REG(fa), I2);
return;
- case 0x05: // Rm = R3-0 * R7-4 (SSFR), Ra = R11-8 - R15-12
+ case 0x05: // Rm = R3-0 * R7-4 (SSFR), Ra = R11-8 - R15-12
UML_DSEXT(block, I0, REG(fxm), SIZE_DWORD);
UML_DSEXT(block, I1, REG(fym), SIZE_DWORD);
UML_DMULS(block, I0, I0, I0, I1);
@@ -3857,7 +3857,7 @@ void adsp21062_device::generate_compute(drcuml_block *block, compiler_state *com
UML_MOV(block, REG(fa), I2);
return;
- case 0x18: // Fm = F3-0 * F7-4, Fa = F11-8 + F15-12
+ case 0x18: // Fm = F3-0 * F7-4, Fa = F11-8 + F15-12
// TODO: denormals
UML_FSCOPYI(block, F0, REG(fxm));
UML_FSCOPYI(block, F1, REG(fym));
@@ -3870,11 +3870,11 @@ void adsp21062_device::generate_compute(drcuml_block *block, compiler_state *com
UML_FSCMP(block, F2, mem(&m_core->fp0));
if (AZ_CALC_REQUIRED) UML_SETc(block, COND_Z, ASTAT_AZ);
if (AN_CALC_REQUIRED) UML_SETc(block, COND_C, ASTAT_AN);
- if (AV_CALC_REQUIRED) UML_MOV(block, ASTAT_AV, 0); // TODO
+ if (AV_CALC_REQUIRED) UML_MOV(block, ASTAT_AV, 0); // TODO
if (AC_CALC_REQUIRED) UML_MOV(block, ASTAT_AC, 0);
if (AS_CALC_REQUIRED) UML_MOV(block, ASTAT_AS, 0);
- if (AI_CALC_REQUIRED) UML_MOV(block, ASTAT_AI, 0); // TODO
-
+ if (AI_CALC_REQUIRED) UML_MOV(block, ASTAT_AI, 0); // TODO
+
if (MN_CALC_REQUIRED)
UML_FSCMP(block, F0, mem(&m_core->fp0));
if (MN_CALC_REQUIRED) UML_SETc(block, COND_C, ASTAT_MN);
@@ -3884,7 +3884,7 @@ void adsp21062_device::generate_compute(drcuml_block *block, compiler_state *com
UML_ICOPYFS(block, REG(fa), F2);
return;
- case 0x19: // Fm = F3-0 * F7-4, Fa = F11-8 - F15-12
+ case 0x19: // Fm = F3-0 * F7-4, Fa = F11-8 - F15-12
// TODO: denormals
UML_FSCOPYI(block, F0, REG(fxm));
UML_FSCOPYI(block, F1, REG(fym));
@@ -3897,10 +3897,10 @@ void adsp21062_device::generate_compute(drcuml_block *block, compiler_state *com
UML_FSCMP(block, F2, mem(&m_core->fp0));
if (AZ_CALC_REQUIRED) UML_SETc(block, COND_Z, ASTAT_AZ);
if (AN_CALC_REQUIRED) UML_SETc(block, COND_C, ASTAT_AN);
- if (AV_CALC_REQUIRED) UML_MOV(block, ASTAT_AV, 0); // TODO
+ if (AV_CALC_REQUIRED) UML_MOV(block, ASTAT_AV, 0); // TODO
if (AC_CALC_REQUIRED) UML_MOV(block, ASTAT_AC, 0);
if (AS_CALC_REQUIRED) UML_MOV(block, ASTAT_AS, 0);
- if (AI_CALC_REQUIRED) UML_MOV(block, ASTAT_AI, 0); // TODO
+ if (AI_CALC_REQUIRED) UML_MOV(block, ASTAT_AI, 0); // TODO
if (MN_CALC_REQUIRED)
UML_FSCMP(block, F0, mem(&m_core->fp0));
@@ -3911,7 +3911,7 @@ void adsp21062_device::generate_compute(drcuml_block *block, compiler_state *com
UML_ICOPYFS(block, REG(fa), F2);
return;
- case 0x1a: // Fm = F3-0 * F7-4, Fa = FLOAT F11-8 BY R15-12
+ case 0x1a: // Fm = F3-0 * F7-4, Fa = FLOAT F11-8 BY R15-12
{
code_label denormal = compiler->labelnum++;
code_label end = compiler->labelnum++;
@@ -3937,7 +3937,7 @@ void adsp21062_device::generate_compute(drcuml_block *block, compiler_state *com
UML_OR(block, I0, I0, I1);
if (AZ_CALC_REQUIRED) UML_SETc(block, COND_Z, ASTAT_AZ);
if (AN_CALC_REQUIRED) UML_SETc(block, COND_S, ASTAT_AN);
- if (AV_CALC_REQUIRED) UML_MOV(block, ASTAT_AV, 0); // TODO
+ if (AV_CALC_REQUIRED) UML_MOV(block, ASTAT_AV, 0); // TODO
if (AC_CALC_REQUIRED) UML_MOV(block, ASTAT_AC, 0);
if (AS_CALC_REQUIRED) UML_MOV(block, ASTAT_AS, 0);
if (AI_CALC_REQUIRED) UML_MOV(block, ASTAT_AI, 0);
@@ -3947,7 +3947,7 @@ void adsp21062_device::generate_compute(drcuml_block *block, compiler_state *com
UML_AND(block, I0, I1, 0x80000000);
if (AZ_CALC_REQUIRED) UML_MOV(block, ASTAT_AZ, 1);
if (AN_CALC_REQUIRED) UML_MOV(block, ASTAT_AN, 0);
- if (AV_CALC_REQUIRED) UML_MOV(block, ASTAT_AV, 0); // TODO
+ if (AV_CALC_REQUIRED) UML_MOV(block, ASTAT_AV, 0); // TODO
if (AC_CALC_REQUIRED) UML_MOV(block, ASTAT_AC, 0);
if (AS_CALC_REQUIRED) UML_MOV(block, ASTAT_AS, 0);
if (AI_CALC_REQUIRED) UML_MOV(block, ASTAT_AI, 0);
@@ -3964,7 +3964,7 @@ void adsp21062_device::generate_compute(drcuml_block *block, compiler_state *com
return;
}
- case 0x1b: // Fm = F3-0 * F7-4, Fa = FIX F11-8 BY R15-12
+ case 0x1b: // Fm = F3-0 * F7-4, Fa = FIX F11-8 BY R15-12
{
code_label denormal = compiler->labelnum++;
code_label end = compiler->labelnum++;
@@ -3989,7 +3989,7 @@ void adsp21062_device::generate_compute(drcuml_block *block, compiler_state *com
UML_OR(block, I0, I0, I1);
if (AZ_CALC_REQUIRED) UML_SETc(block, COND_Z, ASTAT_AZ);
if (AN_CALC_REQUIRED) UML_SETc(block, COND_S, ASTAT_AN);
- if (AV_CALC_REQUIRED) UML_MOV(block, ASTAT_AV, 0); // TODO
+ if (AV_CALC_REQUIRED) UML_MOV(block, ASTAT_AV, 0); // TODO
if (AC_CALC_REQUIRED) UML_MOV(block, ASTAT_AC, 0);
if (AS_CALC_REQUIRED) UML_MOV(block, ASTAT_AS, 0);
if (AI_CALC_REQUIRED) UML_MOV(block, ASTAT_AI, 0);
@@ -3999,7 +3999,7 @@ void adsp21062_device::generate_compute(drcuml_block *block, compiler_state *com
UML_AND(block, I0, I1, 0x80000000);
if (AZ_CALC_REQUIRED) UML_MOV(block, ASTAT_AZ, 1);
if (AN_CALC_REQUIRED) UML_MOV(block, ASTAT_AN, 0);
- if (AV_CALC_REQUIRED) UML_MOV(block, ASTAT_AV, 0); // TODO
+ if (AV_CALC_REQUIRED) UML_MOV(block, ASTAT_AV, 0); // TODO
if (AC_CALC_REQUIRED) UML_MOV(block, ASTAT_AC, 0);
if (AS_CALC_REQUIRED) UML_MOV(block, ASTAT_AS, 0);
if (AI_CALC_REQUIRED) UML_MOV(block, ASTAT_AI, 0);
@@ -4025,18 +4025,18 @@ void adsp21062_device::generate_compute(drcuml_block *block, compiler_state *com
return;
}
- case 0x1d: // Fm = F3-0 * F7-4, Fa = ABS F11-8
+ case 0x1d: // Fm = F3-0 * F7-4, Fa = ABS F11-8
UML_FSCOPYI(block, F0, REG(fxm));
UML_FSCOPYI(block, F1, REG(fym));
UML_AND(block, I0, REG(fxa), 0x7fffffff);
UML_FSMUL(block, F0, F0, F1);
- if (AZ_CALC_REQUIRED) UML_MOV(block, ASTAT_AZ, 0); // TODO
+ if (AZ_CALC_REQUIRED) UML_MOV(block, ASTAT_AZ, 0); // TODO
if (AN_CALC_REQUIRED) UML_MOV(block, ASTAT_AN, 0);
if (AV_CALC_REQUIRED) UML_MOV(block, ASTAT_AV, 0);
if (AC_CALC_REQUIRED) UML_MOV(block, ASTAT_AC, 0);
- if (AS_CALC_REQUIRED) UML_MOV(block, ASTAT_AS, 0); // TODO
- if (AI_CALC_REQUIRED) UML_MOV(block, ASTAT_AI, 0); // TODO
+ if (AS_CALC_REQUIRED) UML_MOV(block, ASTAT_AS, 0); // TODO
+ if (AI_CALC_REQUIRED) UML_MOV(block, ASTAT_AI, 0); // TODO
if (MN_CALC_REQUIRED)
UML_FSCMP(block, F0, mem(&m_core->fp0));
@@ -4047,7 +4047,7 @@ void adsp21062_device::generate_compute(drcuml_block *block, compiler_state *com
UML_MOV(block, REG(fa), I0);
return;
- case 0x1e: // Fm = F3-0 * F7-4, Fa = MAX(F11-8, F15-12)
+ case 0x1e: // Fm = F3-0 * F7-4, Fa = MAX(F11-8, F15-12)
// TODO: denormals
UML_FSCOPYI(block, F0, REG(fxm));
UML_FSCOPYI(block, F1, REG(fym));
@@ -4063,10 +4063,10 @@ void adsp21062_device::generate_compute(drcuml_block *block, compiler_state *com
UML_FSCMP(block, F4, mem(&m_core->fp0));
if (AZ_CALC_REQUIRED) UML_SETc(block, COND_Z, ASTAT_AZ);
if (AN_CALC_REQUIRED) UML_SETc(block, COND_C, ASTAT_AN);
- if (AV_CALC_REQUIRED) UML_MOV(block, ASTAT_AV, 0); // TODO
+ if (AV_CALC_REQUIRED) UML_MOV(block, ASTAT_AV, 0); // TODO
if (AC_CALC_REQUIRED) UML_MOV(block, ASTAT_AC, 0);
if (AS_CALC_REQUIRED) UML_MOV(block, ASTAT_AS, 0);
- if (AI_CALC_REQUIRED) UML_MOV(block, ASTAT_AI, 0); // TODO
+ if (AI_CALC_REQUIRED) UML_MOV(block, ASTAT_AI, 0); // TODO
if (MN_CALC_REQUIRED)
UML_FSCMP(block, F0, mem(&m_core->fp0));
@@ -4077,7 +4077,7 @@ void adsp21062_device::generate_compute(drcuml_block *block, compiler_state *com
UML_ICOPYFS(block, REG(fa), F4);
return;
- case 0x1f: // Fm = F3-0 * F7-4, Fa = MIN(F11-8, F15-12)
+ case 0x1f: // Fm = F3-0 * F7-4, Fa = MIN(F11-8, F15-12)
// TODO: denormals
UML_FSCOPYI(block, F0, REG(fxm));
UML_FSCOPYI(block, F1, REG(fym));
@@ -4093,10 +4093,10 @@ void adsp21062_device::generate_compute(drcuml_block *block, compiler_state *com
UML_FSCMP(block, F4, mem(&m_core->fp0));
if (AZ_CALC_REQUIRED) UML_SETc(block, COND_Z, ASTAT_AZ);
if (AN_CALC_REQUIRED) UML_SETc(block, COND_C, ASTAT_AN);
- if (AV_CALC_REQUIRED) UML_MOV(block, ASTAT_AV, 0); // TODO
+ if (AV_CALC_REQUIRED) UML_MOV(block, ASTAT_AV, 0); // TODO
if (AC_CALC_REQUIRED) UML_MOV(block, ASTAT_AC, 0);
if (AS_CALC_REQUIRED) UML_MOV(block, ASTAT_AS, 0);
- if (AI_CALC_REQUIRED) UML_MOV(block, ASTAT_AI, 0); // TODO
+ if (AI_CALC_REQUIRED) UML_MOV(block, ASTAT_AI, 0); // TODO
if (MN_CALC_REQUIRED)
UML_FSCMP(block, F0, mem(&m_core->fp0));
@@ -4112,35 +4112,35 @@ void adsp21062_device::generate_compute(drcuml_block *block, compiler_state *com
return;
}
}
- else // single-function operation
+ else // single-function operation
{
UINT32 operation = (opcode >> 12) & 0xff;
switch ((opcode >> 20) & 3)
{
- case 0: // ALU operations
+ case 0: // ALU operations
{
switch (operation)
{
- case 0x09: // Rn = (Rx + Ry) / 2
- case 0x63: // Rn = CLIP Rx BY Ry
- case 0x92: // Fn = ABS(Fx - Fy)
- case 0x89: // Fn = (Fx + Fy) / 2
- case 0xdd: // Rn = TRUNC Fx BY Ry
- case 0xe0: // Fn = Fx COPYSIGN Fy
- case 0x05: // Rn = Rx + Ry + CI
- case 0x06: // Rn = Rx - Ry + CI - 1
- case 0x25: // Rn = Rx + CI
- case 0x26: // Rn = Rx + CI - 1
- case 0x30: // Rn = ABS Rx
- case 0x43: // Rn = NOT Rx
- case 0xa5: // Fn = RND Fx
- case 0xad: // Rn = MANT Fx
- case 0xcd: // Rn = TRUNC Fx
+ case 0x09: // Rn = (Rx + Ry) / 2
+ case 0x63: // Rn = CLIP Rx BY Ry
+ case 0x92: // Fn = ABS(Fx - Fy)
+ case 0x89: // Fn = (Fx + Fy) / 2
+ case 0xdd: // Rn = TRUNC Fx BY Ry
+ case 0xe0: // Fn = Fx COPYSIGN Fy
+ case 0x05: // Rn = Rx + Ry + CI
+ case 0x06: // Rn = Rx - Ry + CI - 1
+ case 0x25: // Rn = Rx + CI
+ case 0x26: // Rn = Rx + CI - 1
+ case 0x30: // Rn = ABS Rx
+ case 0x43: // Rn = NOT Rx
+ case 0xa5: // Fn = RND Fx
+ case 0xad: // Rn = MANT Fx
+ case 0xcd: // Rn = TRUNC Fx
generate_unimplemented_compute(block, compiler, desc);
return;
- case 0x01: // Rn = Rx + Ry
+ case 0x01: // Rn = Rx + Ry
UML_ADD(block, REG(rn), REG(rx), REG(ry));
if (AZ_CALC_REQUIRED) UML_SETc(block, COND_Z, ASTAT_AZ);
if (AN_CALC_REQUIRED) UML_SETc(block, COND_S, ASTAT_AN);
@@ -4150,7 +4150,7 @@ void adsp21062_device::generate_compute(drcuml_block *block, compiler_state *com
if (AI_CALC_REQUIRED) UML_MOV(block, ASTAT_AI, 0);
return;
- case 0x02: // Rn = Rx - Ry
+ case 0x02: // Rn = Rx - Ry
UML_SUB(block, REG(rn), REG(rx), REG(ry));
if (AZ_CALC_REQUIRED) UML_SETc(block, COND_Z, ASTAT_AZ);
if (AN_CALC_REQUIRED) UML_SETc(block, COND_S, ASTAT_AN);
@@ -4160,7 +4160,7 @@ void adsp21062_device::generate_compute(drcuml_block *block, compiler_state *com
if (AI_CALC_REQUIRED) UML_MOV(block, ASTAT_AI, 0);
return;
- case 0x0a: // COMP(Rx, Ry)
+ case 0x0a: // COMP(Rx, Ry)
UML_CMP(block, REG(rx), REG(ry));
UML_SETc(block, COND_Z, I0);
UML_SETc(block, COND_L, I1);
@@ -4182,7 +4182,7 @@ void adsp21062_device::generate_compute(drcuml_block *block, compiler_state *com
if (AI_CALC_REQUIRED) UML_MOV(block, ASTAT_AI, 0);
return;
- case 0x21: // Rn = PASS Rx
+ case 0x21: // Rn = PASS Rx
UML_MOV(block, REG(rn), REG(rx));
if (AZ_CALC_REQUIRED || AN_CALC_REQUIRED)
UML_CMP(block, REG(rn), 0);
@@ -4194,7 +4194,7 @@ void adsp21062_device::generate_compute(drcuml_block *block, compiler_state *com
if (AI_CALC_REQUIRED) UML_MOV(block, ASTAT_AI, 0);
return;
- case 0x22: // Rn = -Rx
+ case 0x22: // Rn = -Rx
UML_SUB(block, REG(rn), 0, REG(rx));
if (AZ_CALC_REQUIRED) UML_SETc(block, COND_Z, ASTAT_AZ);
if (AN_CALC_REQUIRED) UML_SETc(block, COND_S, ASTAT_AN);
@@ -4204,7 +4204,7 @@ void adsp21062_device::generate_compute(drcuml_block *block, compiler_state *com
if (AI_CALC_REQUIRED) UML_MOV(block, ASTAT_AI, 0);
return;
- case 0x29: // Rn = Rx + 1
+ case 0x29: // Rn = Rx + 1
UML_ADD(block, REG(rn), REG(rx), 1);
if (AZ_CALC_REQUIRED) UML_SETc(block, COND_Z, ASTAT_AZ);
if (AN_CALC_REQUIRED) UML_SETc(block, COND_S, ASTAT_AN);
@@ -4214,7 +4214,7 @@ void adsp21062_device::generate_compute(drcuml_block *block, compiler_state *com
if (AI_CALC_REQUIRED) UML_MOV(block, ASTAT_AI, 0);
return;
- case 0x2a: // Rn = Rx - 1
+ case 0x2a: // Rn = Rx - 1
UML_SUB(block, REG(rn), REG(rx), 1);
if (AZ_CALC_REQUIRED) UML_SETc(block, COND_Z, ASTAT_AZ);
if (AN_CALC_REQUIRED) UML_SETc(block, COND_S, ASTAT_AN);
@@ -4224,7 +4224,7 @@ void adsp21062_device::generate_compute(drcuml_block *block, compiler_state *com
if (AI_CALC_REQUIRED) UML_MOV(block, ASTAT_AI, 0);
return;
- case 0x40: // Rn = Rx AND Ry
+ case 0x40: // Rn = Rx AND Ry
UML_AND(block, REG(rn), REG(rx), REG(ry));
if (AZ_CALC_REQUIRED) UML_SETc(block, COND_Z, ASTAT_AZ);
if (AN_CALC_REQUIRED) UML_SETc(block, COND_S, ASTAT_AN);
@@ -4234,7 +4234,7 @@ void adsp21062_device::generate_compute(drcuml_block *block, compiler_state *com
if (AI_CALC_REQUIRED) UML_MOV(block, ASTAT_AI, 0);
return;
- case 0x41: // Rn = Rx OR Ry
+ case 0x41: // Rn = Rx OR Ry
UML_OR(block, REG(rn), REG(rx), REG(ry));
if (AZ_CALC_REQUIRED) UML_SETc(block, COND_Z, ASTAT_AZ);
if (AN_CALC_REQUIRED) UML_SETc(block, COND_S, ASTAT_AN);
@@ -4244,7 +4244,7 @@ void adsp21062_device::generate_compute(drcuml_block *block, compiler_state *com
if (AI_CALC_REQUIRED) UML_MOV(block, ASTAT_AI, 0);
return;
- case 0x42: // Rn = Rx XOR Ry
+ case 0x42: // Rn = Rx XOR Ry
UML_XOR(block, REG(rn), REG(rx), REG(ry));
if (AZ_CALC_REQUIRED) UML_SETc(block, COND_Z, ASTAT_AZ);
if (AN_CALC_REQUIRED) UML_SETc(block, COND_S, ASTAT_AN);
@@ -4254,7 +4254,7 @@ void adsp21062_device::generate_compute(drcuml_block *block, compiler_state *com
if (AI_CALC_REQUIRED) UML_MOV(block, ASTAT_AI, 0);
return;
- case 0x61: // Rn = MIN(Rx, Ry)
+ case 0x61: // Rn = MIN(Rx, Ry)
UML_MOV(block, REG(rn), REG(rx));
UML_CMP(block, REG(rx), REG(ry));
UML_MOVc(block, COND_G, REG(rn), REG(ry));
@@ -4268,7 +4268,7 @@ void adsp21062_device::generate_compute(drcuml_block *block, compiler_state *com
if (AI_CALC_REQUIRED) UML_MOV(block, ASTAT_AI, 0);
return;
- case 0x62: // Rn = MAX(Rx, Ry)
+ case 0x62: // Rn = MAX(Rx, Ry)
UML_MOV(block, REG(rn), REG(rx));
UML_CMP(block, REG(rx), REG(ry));
UML_MOVc(block, COND_L, REG(rn), REG(ry));
@@ -4286,7 +4286,7 @@ void adsp21062_device::generate_compute(drcuml_block *block, compiler_state *com
case 0x78: case 0x79: case 0x7a: case 0x7b: case 0x7c: case 0x7d: case 0x7e: case 0x7f:
{
/* Fixed-point Dual Add/Subtract */
- UML_ADD(block, I0, REG(rx), REG(ry));
+ UML_ADD(block, I0, REG(rx), REG(ry));
if (AZ_CALC_REQUIRED) UML_SETc(block, COND_Z, ASTAT_AZ);
if (AN_CALC_REQUIRED) UML_SETc(block, COND_S, ASTAT_AN);
if (AV_CALC_REQUIRED) UML_SETc(block, COND_V, ASTAT_AV);
@@ -4307,7 +4307,7 @@ void adsp21062_device::generate_compute(drcuml_block *block, compiler_state *com
return;
}
- case 0x81: // Fn = Fx + Fy
+ case 0x81: // Fn = Fx + Fy
// TODO: denormals
UML_FSCOPYI(block, F0, REG(rx));
UML_FSCOPYI(block, F1, REG(ry));
@@ -4316,14 +4316,14 @@ void adsp21062_device::generate_compute(drcuml_block *block, compiler_state *com
UML_FSCMP(block, F0, mem(&m_core->fp0));
if (AZ_CALC_REQUIRED) UML_SETc(block, COND_Z, ASTAT_AZ);
if (AN_CALC_REQUIRED) UML_SETc(block, COND_C, ASTAT_AN);
- if (AV_CALC_REQUIRED) UML_MOV(block, ASTAT_AV, 0); // TODO
+ if (AV_CALC_REQUIRED) UML_MOV(block, ASTAT_AV, 0); // TODO
if (AC_CALC_REQUIRED) UML_MOV(block, ASTAT_AC, 0);
if (AS_CALC_REQUIRED) UML_MOV(block, ASTAT_AS, 0);
- if (AI_CALC_REQUIRED) UML_MOV(block, ASTAT_AI, 0); // TODO
+ if (AI_CALC_REQUIRED) UML_MOV(block, ASTAT_AI, 0); // TODO
UML_ICOPYFS(block, REG(rn), F0);
return;
- case 0x82: // Fn = Fx - Fy
+ case 0x82: // Fn = Fx - Fy
// TODO: denormals
UML_FSCOPYI(block, F0, REG(rx));
UML_FSCOPYI(block, F1, REG(ry));
@@ -4332,14 +4332,14 @@ void adsp21062_device::generate_compute(drcuml_block *block, compiler_state *com
UML_FSCMP(block, F0, mem(&m_core->fp0));
if (AZ_CALC_REQUIRED) UML_SETc(block, COND_Z, ASTAT_AZ);
if (AN_CALC_REQUIRED) UML_SETc(block, COND_C, ASTAT_AN);
- if (AV_CALC_REQUIRED) UML_MOV(block, ASTAT_AV, 0); // TODO
+ if (AV_CALC_REQUIRED) UML_MOV(block, ASTAT_AV, 0); // TODO
if (AC_CALC_REQUIRED) UML_MOV(block, ASTAT_AC, 0);
if (AS_CALC_REQUIRED) UML_MOV(block, ASTAT_AS, 0);
- if (AI_CALC_REQUIRED) UML_MOV(block, ASTAT_AI, 0); // TODO
+ if (AI_CALC_REQUIRED) UML_MOV(block, ASTAT_AI, 0); // TODO
UML_ICOPYFS(block, REG(rn), F0);
return;
- case 0x8a: // COMP(Fx, Fy)
+ case 0x8a: // COMP(Fx, Fy)
UML_FSCOPYI(block, F0, REG(rx));
UML_FSCOPYI(block, F1, REG(ry));
UML_FSCMP(block, F0, F1);
@@ -4356,29 +4356,29 @@ void adsp21062_device::generate_compute(drcuml_block *block, compiler_state *com
UML_SHR(block, I2, I2, 1);
UML_OR(block, I2, I2, I0);
UML_MOV(block, mem(&m_core->astat_drc.cacc), I2);
-
+
if (AV_CALC_REQUIRED) UML_MOV(block, ASTAT_AV, 0);
if (AC_CALC_REQUIRED) UML_MOV(block, ASTAT_AC, 0);
if (AS_CALC_REQUIRED) UML_MOV(block, ASTAT_AS, 0);
- if (AI_CALC_REQUIRED) UML_MOV(block, ASTAT_AI, 0); // TODO
+ if (AI_CALC_REQUIRED) UML_MOV(block, ASTAT_AI, 0); // TODO
return;
- case 0x91: // Fn = ABS(Fx + Fy)
+ case 0x91: // Fn = ABS(Fx + Fy)
// TODO: denormals
UML_FSCOPYI(block, F0, REG(rx));
UML_FSCOPYI(block, F1, REG(ry));
UML_FSADD(block, F0, F0, F1);
UML_FSABS(block, F0, F0);
UML_ICOPYFS(block, REG(rn), F0);
- if (AZ_CALC_REQUIRED) UML_MOV(block, ASTAT_AZ, 0); // TODO
+ if (AZ_CALC_REQUIRED) UML_MOV(block, ASTAT_AZ, 0); // TODO
if (AN_CALC_REQUIRED) UML_MOV(block, ASTAT_AN, 0);
- if (AV_CALC_REQUIRED) UML_MOV(block, ASTAT_AV, 0); // TODO
+ if (AV_CALC_REQUIRED) UML_MOV(block, ASTAT_AV, 0); // TODO
if (AC_CALC_REQUIRED) UML_MOV(block, ASTAT_AC, 0);
if (AS_CALC_REQUIRED) UML_MOV(block, ASTAT_AS, 0);
- if (AI_CALC_REQUIRED) UML_MOV(block, ASTAT_AI, 0); // TODO
+ if (AI_CALC_REQUIRED) UML_MOV(block, ASTAT_AI, 0); // TODO
return;
- case 0xa1: // Fn = PASS Fx
+ case 0xa1: // Fn = PASS Fx
UML_MOV(block, REG(rn), REG(rx));
if (AZ_CALC_REQUIRED || AN_CALC_REQUIRED)
{
@@ -4390,10 +4390,10 @@ void adsp21062_device::generate_compute(drcuml_block *block, compiler_state *com
if (AV_CALC_REQUIRED) UML_MOV(block, ASTAT_AV, 0);
if (AC_CALC_REQUIRED) UML_MOV(block, ASTAT_AC, 0);
if (AS_CALC_REQUIRED) UML_MOV(block, ASTAT_AS, 0);
- if (AI_CALC_REQUIRED) UML_MOV(block, ASTAT_AI, 0); // TODO
+ if (AI_CALC_REQUIRED) UML_MOV(block, ASTAT_AI, 0); // TODO
return;
- case 0xa2: // Fn = -Fx
+ case 0xa2: // Fn = -Fx
UML_FSCOPYI(block, F0, REG(rx));
UML_FSNEG(block, F0, F0);
UML_ICOPYFS(block, REG(rn), F0);
@@ -4404,23 +4404,23 @@ void adsp21062_device::generate_compute(drcuml_block *block, compiler_state *com
if (AV_CALC_REQUIRED) UML_MOV(block, ASTAT_AV, 0);
if (AC_CALC_REQUIRED) UML_MOV(block, ASTAT_AC, 0);
if (AS_CALC_REQUIRED) UML_MOV(block, ASTAT_AS, 0);
- if (AI_CALC_REQUIRED) UML_MOV(block, ASTAT_AI, 0); // TODO
+ if (AI_CALC_REQUIRED) UML_MOV(block, ASTAT_AI, 0); // TODO
return;
- case 0xb0: // Fn = ABS(Fx)
+ case 0xb0: // Fn = ABS(Fx)
UML_FSCOPYI(block, F0, REG(rx));
UML_FSABS(block, F0, F0);
UML_ICOPYFS(block, REG(rn), F0);
- if (AZ_CALC_REQUIRED) UML_MOV(block, ASTAT_AZ, 0); // TODO
+ if (AZ_CALC_REQUIRED) UML_MOV(block, ASTAT_AZ, 0); // TODO
if (AN_CALC_REQUIRED) UML_MOV(block, ASTAT_AN, 0);
if (AV_CALC_REQUIRED) UML_MOV(block, ASTAT_AV, 0);
if (AC_CALC_REQUIRED) UML_MOV(block, ASTAT_AC, 0);
- if (AS_CALC_REQUIRED) UML_MOV(block, ASTAT_AS, 0); // TODO
- if (AI_CALC_REQUIRED) UML_MOV(block, ASTAT_AI, 0); // TODO
+ if (AS_CALC_REQUIRED) UML_MOV(block, ASTAT_AS, 0); // TODO
+ if (AI_CALC_REQUIRED) UML_MOV(block, ASTAT_AI, 0); // TODO
return;
- case 0xbd: // Fn = SCALB Fx BY Ry
+ case 0xbd: // Fn = SCALB Fx BY Ry
// TODO: source = nan, result = denormal
UML_MOV(block, I1, REG(rx));
UML_AND(block, I0, I1, 0x7f800000);
@@ -4434,26 +4434,26 @@ void adsp21062_device::generate_compute(drcuml_block *block, compiler_state *com
UML_OR(block, REG(rn), I0, I1);
if (AZ_CALC_REQUIRED) UML_SETc(block, COND_Z, ASTAT_AZ);
if (AN_CALC_REQUIRED) UML_SETc(block, COND_S, ASTAT_AN);
- if (AV_CALC_REQUIRED) UML_MOV(block, ASTAT_AV, 0); // TODO
+ if (AV_CALC_REQUIRED) UML_MOV(block, ASTAT_AV, 0); // TODO
if (AC_CALC_REQUIRED) UML_MOV(block, ASTAT_AC, 0);
if (AS_CALC_REQUIRED) UML_MOV(block, ASTAT_AS, 0);
- if (AI_CALC_REQUIRED) UML_MOV(block, ASTAT_AI, 0); // TODO
+ if (AI_CALC_REQUIRED) UML_MOV(block, ASTAT_AI, 0); // TODO
return;
- case 0xc1: // Rn = LOGB Fx
+ case 0xc1: // Rn = LOGB Fx
// TODO: source = zero, infinity, nan
UML_SHR(block, I0, REG(rx), 23);
UML_AND(block, I0, I0, 0xff);
UML_SUB(block, REG(rn), I0, 127);
if (AZ_CALC_REQUIRED) UML_SETc(block, COND_Z, ASTAT_AZ);
if (AN_CALC_REQUIRED) UML_SETc(block, COND_S, ASTAT_AN);
- if (AV_CALC_REQUIRED) UML_MOV(block, ASTAT_AV, 0); // TODO
+ if (AV_CALC_REQUIRED) UML_MOV(block, ASTAT_AV, 0); // TODO
if (AC_CALC_REQUIRED) UML_MOV(block, ASTAT_AC, 0);
if (AS_CALC_REQUIRED) UML_MOV(block, ASTAT_AS, 0);
if (AI_CALC_REQUIRED) UML_MOV(block, ASTAT_AI, 0);
return;
- case 0xc4: // Fn = RECIPS Fx
+ case 0xc4: // Fn = RECIPS Fx
// TODO: denormals
// TODO: use the bit accurate method from interpreter?
UML_FSCOPYI(block, F0, REG(rx));
@@ -4470,11 +4470,11 @@ void adsp21062_device::generate_compute(drcuml_block *block, compiler_state *com
if (AZ_CALC_REQUIRED) UML_SETc(block, COND_Z, ASTAT_AZ);
if (AC_CALC_REQUIRED) UML_MOV(block, ASTAT_AC, 0);
if (AS_CALC_REQUIRED) UML_MOV(block, ASTAT_AS, 0);
- if (AI_CALC_REQUIRED) UML_MOV(block, ASTAT_AI, 0); // TODO
+ if (AI_CALC_REQUIRED) UML_MOV(block, ASTAT_AI, 0); // TODO
UML_ICOPYFS(block, REG(rn), F0);
return;
- case 0xc5: // Fn = RSQRTS Fx
+ case 0xc5: // Fn = RSQRTS Fx
// TODO: denormals
// TODO: use the bit accurate method from interpreter?
UML_FSCOPYI(block, F0, REG(rx));
@@ -4488,7 +4488,7 @@ void adsp21062_device::generate_compute(drcuml_block *block, compiler_state *com
if (AS_CALC_REQUIRED) UML_MOV(block, ASTAT_AS, 0);
return;
- case 0xca: // Fn = FLOAT Rx
+ case 0xca: // Fn = FLOAT Rx
UML_FSFRINT(block, F0, REG(rx), SIZE_DWORD);
UML_ICOPYFS(block, REG(rn), F0);
if (AZ_CALC_REQUIRED)
@@ -4500,7 +4500,7 @@ void adsp21062_device::generate_compute(drcuml_block *block, compiler_state *com
if (AI_CALC_REQUIRED) UML_MOV(block, ASTAT_AI, 0);
return;
- case 0xc9: // Rn = FIX Fx
+ case 0xc9: // Rn = FIX Fx
UML_FSCOPYI(block, F0, REG(rx));
UML_TEST(block, MODE1, MODE1_TRUNCATE);
UML_JMPc(block, COND_Z, compiler->labelnum);
@@ -4514,14 +4514,14 @@ void adsp21062_device::generate_compute(drcuml_block *block, compiler_state *com
UML_CMP(block, I0, 0);
if (AZ_CALC_REQUIRED) UML_SETc(block, COND_Z, ASTAT_AZ);
if (AN_CALC_REQUIRED) UML_SETc(block, COND_S, ASTAT_AN);
- if (AV_CALC_REQUIRED) UML_MOV(block, ASTAT_AV, 0); // TODO
+ if (AV_CALC_REQUIRED) UML_MOV(block, ASTAT_AV, 0); // TODO
if (AC_CALC_REQUIRED) UML_MOV(block, ASTAT_AC, 0);
if (AS_CALC_REQUIRED) UML_MOV(block, ASTAT_AS, 0);
- if (AI_CALC_REQUIRED) UML_MOV(block, ASTAT_AI, 0); // TODO
+ if (AI_CALC_REQUIRED) UML_MOV(block, ASTAT_AI, 0); // TODO
UML_MOV(block, REG(rn), I0);
- return;
+ return;
- case 0xd9: // Rn = FIX Fx BY Ry
+ case 0xd9: // Rn = FIX Fx BY Ry
{
code_label denormal = compiler->labelnum++;
code_label end = compiler->labelnum++;
@@ -4553,10 +4553,10 @@ void adsp21062_device::generate_compute(drcuml_block *block, compiler_state *com
UML_CMP(block, I0, 0);
if (AZ_CALC_REQUIRED) UML_SETc(block, COND_Z, ASTAT_AZ);
if (AN_CALC_REQUIRED) UML_SETc(block, COND_S, ASTAT_AN);
- if (AV_CALC_REQUIRED) UML_MOV(block, ASTAT_AV, 0); // TODO
+ if (AV_CALC_REQUIRED) UML_MOV(block, ASTAT_AV, 0); // TODO
if (AC_CALC_REQUIRED) UML_MOV(block, ASTAT_AC, 0);
if (AS_CALC_REQUIRED) UML_MOV(block, ASTAT_AS, 0);
- if (AI_CALC_REQUIRED) UML_MOV(block, ASTAT_AI, 0); // TODO
+ if (AI_CALC_REQUIRED) UML_MOV(block, ASTAT_AI, 0); // TODO
UML_MOV(block, REG(rn), I0);
UML_JMP(block, end);
@@ -4564,7 +4564,7 @@ void adsp21062_device::generate_compute(drcuml_block *block, compiler_state *com
UML_AND(block, I0, I1, 0x80000000);
if (AZ_CALC_REQUIRED) UML_MOV(block, ASTAT_AZ, 1);
if (AN_CALC_REQUIRED) UML_MOV(block, ASTAT_AN, 0);
- if (AV_CALC_REQUIRED) UML_MOV(block, ASTAT_AV, 0); // TODO
+ if (AV_CALC_REQUIRED) UML_MOV(block, ASTAT_AV, 0); // TODO
if (AC_CALC_REQUIRED) UML_MOV(block, ASTAT_AC, 0);
if (AS_CALC_REQUIRED) UML_MOV(block, ASTAT_AS, 0);
if (AI_CALC_REQUIRED) UML_MOV(block, ASTAT_AI, 0);
@@ -4574,7 +4574,7 @@ void adsp21062_device::generate_compute(drcuml_block *block, compiler_state *com
return;
}
- case 0xda: // Fn = FLOAT Rx BY Ry
+ case 0xda: // Fn = FLOAT Rx BY Ry
{
code_label denormal = compiler->labelnum++;
code_label end = compiler->labelnum++;
@@ -4594,27 +4594,27 @@ void adsp21062_device::generate_compute(drcuml_block *block, compiler_state *com
UML_OR(block, REG(rn), I0, I1);
if (AZ_CALC_REQUIRED) UML_SETc(block, COND_Z, ASTAT_AZ);
if (AN_CALC_REQUIRED) UML_SETc(block, COND_S, ASTAT_AN);
- if (AV_CALC_REQUIRED) UML_MOV(block, ASTAT_AV, 0); // TODO
+ if (AV_CALC_REQUIRED) UML_MOV(block, ASTAT_AV, 0); // TODO
if (AC_CALC_REQUIRED) UML_MOV(block, ASTAT_AC, 0);
if (AS_CALC_REQUIRED) UML_MOV(block, ASTAT_AS, 0);
if (AI_CALC_REQUIRED) UML_MOV(block, ASTAT_AI, 0);
UML_JMP(block, end);
-
+
UML_LABEL(block, denormal);
UML_AND(block, I0, I1, 0x80000000);
if (AZ_CALC_REQUIRED) UML_MOV(block, ASTAT_AZ, 1);
if (AN_CALC_REQUIRED) UML_MOV(block, ASTAT_AN, 0);
- if (AV_CALC_REQUIRED) UML_MOV(block, ASTAT_AV, 0); // TODO
+ if (AV_CALC_REQUIRED) UML_MOV(block, ASTAT_AV, 0); // TODO
if (AC_CALC_REQUIRED) UML_MOV(block, ASTAT_AC, 0);
if (AS_CALC_REQUIRED) UML_MOV(block, ASTAT_AS, 0);
if (AI_CALC_REQUIRED) UML_MOV(block, ASTAT_AI, 0);
UML_MOV(block, REG(rn), I0);
-
+
UML_LABEL(block, end);
return;
}
- case 0xe1: // Fn = MIN(Fx, Fy)
+ case 0xe1: // Fn = MIN(Fx, Fy)
UML_FSCOPYI(block, F2, REG(rx));
UML_FSCOPYI(block, F3, REG(ry));
UML_FSMOV(block, F4, F2);
@@ -4625,14 +4625,14 @@ void adsp21062_device::generate_compute(drcuml_block *block, compiler_state *com
UML_FSCMP(block, F4, mem(&m_core->fp0));
if (AZ_CALC_REQUIRED) UML_SETc(block, COND_Z, ASTAT_AZ);
if (AN_CALC_REQUIRED) UML_SETc(block, COND_C, ASTAT_AN);
- if (AV_CALC_REQUIRED) UML_MOV(block, ASTAT_AV, 0); // TODO
+ if (AV_CALC_REQUIRED) UML_MOV(block, ASTAT_AV, 0); // TODO
if (AC_CALC_REQUIRED) UML_MOV(block, ASTAT_AC, 0);
if (AS_CALC_REQUIRED) UML_MOV(block, ASTAT_AS, 0);
- if (AI_CALC_REQUIRED) UML_MOV(block, ASTAT_AI, 0); // TODO
+ if (AI_CALC_REQUIRED) UML_MOV(block, ASTAT_AI, 0); // TODO
UML_ICOPYFS(block, REG(rn), F4);
return;
- case 0xe2: // Fn = MAX(Fx, Fy)
+ case 0xe2: // Fn = MAX(Fx, Fy)
UML_FSCOPYI(block, F2, REG(rx));
UML_FSCOPYI(block, F3, REG(ry));
UML_FSMOV(block, F4, F2);
@@ -4643,14 +4643,14 @@ void adsp21062_device::generate_compute(drcuml_block *block, compiler_state *com
UML_FSCMP(block, F4, mem(&m_core->fp0));
if (AZ_CALC_REQUIRED) UML_SETc(block, COND_Z, ASTAT_AZ);
if (AN_CALC_REQUIRED) UML_SETc(block, COND_C, ASTAT_AN);
- if (AV_CALC_REQUIRED) UML_MOV(block, ASTAT_AV, 0); // TODO
+ if (AV_CALC_REQUIRED) UML_MOV(block, ASTAT_AV, 0); // TODO
if (AC_CALC_REQUIRED) UML_MOV(block, ASTAT_AC, 0);
if (AS_CALC_REQUIRED) UML_MOV(block, ASTAT_AS, 0);
- if (AI_CALC_REQUIRED) UML_MOV(block, ASTAT_AI, 0); // TODO
+ if (AI_CALC_REQUIRED) UML_MOV(block, ASTAT_AI, 0); // TODO
UML_ICOPYFS(block, REG(rn), F4);
return;
- case 0xe3: // Fn = CLIP Fx BY Fy
+ case 0xe3: // Fn = CLIP Fx BY Fy
{
code_label label_1 = compiler->labelnum++;
code_label label_2 = compiler->labelnum++;
@@ -4675,7 +4675,7 @@ void adsp21062_device::generate_compute(drcuml_block *block, compiler_state *com
if (AV_CALC_REQUIRED) UML_MOV(block, ASTAT_AV, 0);
if (AC_CALC_REQUIRED) UML_MOV(block, ASTAT_AC, 0);
if (AS_CALC_REQUIRED) UML_MOV(block, ASTAT_AS, 0);
- if (AI_CALC_REQUIRED) UML_MOV(block, ASTAT_AI, 0); // TODO
+ if (AI_CALC_REQUIRED) UML_MOV(block, ASTAT_AI, 0); // TODO
UML_ICOPYFS(block, REG(rn), F0);
return;
}
@@ -4698,10 +4698,10 @@ void adsp21062_device::generate_compute(drcuml_block *block, compiler_state *com
if (AN_CALC_REQUIRED) UML_SETc(block, COND_C, I1);
if (AZ_CALC_REQUIRED) UML_OR(block, ASTAT_AZ, ASTAT_AZ, I0);
if (AN_CALC_REQUIRED) UML_OR(block, ASTAT_AN, ASTAT_AN, I1);
- if (AV_CALC_REQUIRED) UML_MOV(block, ASTAT_AV, 0); // TODO
+ if (AV_CALC_REQUIRED) UML_MOV(block, ASTAT_AV, 0); // TODO
if (AC_CALC_REQUIRED) UML_MOV(block, ASTAT_AC, 0);
if (AS_CALC_REQUIRED) UML_MOV(block, ASTAT_AS, 0);
- if (AI_CALC_REQUIRED) UML_MOV(block, ASTAT_AI, 0); // TODO
+ if (AI_CALC_REQUIRED) UML_MOV(block, ASTAT_AI, 0); // TODO
UML_ICOPYFS(block, REG(ra), F2);
UML_ICOPYFS(block, REG(rs), F3);
return;
@@ -4714,166 +4714,166 @@ void adsp21062_device::generate_compute(drcuml_block *block, compiler_state *com
break;
}
- case 1: // multiplier operations
+ case 1: // multiplier operations
{
switch (operation)
{
- case 0x48: // Rn = Rx * Ry (UUF)
- case 0x49: // Rn = Rx * Ry (UUFR)
- case 0x50: // Rn = Rx * Ry (SUI)
- case 0x58: // Rn = Rx * Ry (SUF)
- case 0x59: // Rn = Rx * Ry (SUFR)
- case 0x60: // Rn = Rx * Ry (USI)
- case 0x68: // Rn = Rx * Ry (USF)
- case 0x69: // Rn = Rx * Ry (USFR)
- case 0x78: // Rn = Rx * Ry (SSF)
- case 0x79: // Rn = Rx * Ry (SSFR)
- case 0x44: // MRF = Rx * Ry (UUI)
- case 0x4c: // MRF = Rx * Ry (UUF)
- case 0x4d: // MRF = Rx * Ry (UUFR)
- case 0x54: // MRF = Rx * Ry (SUI)
- case 0x5c: // MRF = Rx * Ry (SUF)
- case 0x5d: // MRF = Rx * Ry (SUFR)
- case 0x64: // MRF = Rx * Ry (USI)
- case 0x6c: // MRF = Rx * Ry (USF)
- case 0x6d: // MRF = Rx * Ry (USFR)
- case 0x74: // MRF = Rx * Ry (SSI)
- case 0x7c: // MRF = Rx * Ry (SSF)
- case 0x7d: // MRF = Rx * Ry (SSFR)
- case 0x46: // MRB = Rx * Ry (UUI)
- case 0x4e: // MRB = Rx * Ry (UUF)
- case 0x4f: // MRB = Rx * Ry (UUFR)
- case 0x56: // MRB = Rx * Ry (SUI)
- case 0x5e: // MRB = Rx * Ry (SUF)
- case 0x5f: // MRB = Rx * Ry (SUFR)
- case 0x66: // MRB = Rx * Ry (USI)
- case 0x6e: // MRB = Rx * Ry (USF)
- case 0x6f: // MRB = Rx * Ry (USFR)
- case 0x76: // MRB = Rx * Ry (SSI)
- case 0x7e: // MRB = Rx * Ry (SSF)
- case 0x7f: // MRB = Rx * Ry (SSFR)
- case 0x80: // Rn = MRF + Rx * Ry (UUI)
- case 0x88: // Rn = MRF + Rx * Ry (UUF)
- case 0x89: // Rn = MRF + Rx * Ry (UUFR)
- case 0x90: // Rn = MRF + Rx * Ry (SUI)
- case 0x98: // Rn = MRF + Rx * Ry (SUF)
- case 0x99: // Rn = MRF + Rx * Ry (SUFR)
- case 0xa0: // Rn = MRF + Rx * Ry (USI)
- case 0xa8: // Rn = MRF + Rx * Ry (USF)
- case 0xa9: // Rn = MRF + Rx * Ry (USFR)
- case 0xb8: // Rn = MRF + Rx * Ry (SSF)
- case 0xb9: // Rn = MRF + Rx * Ry (SSFR)
- case 0x82: // Rn = MRB + Rx * Ry (UUI)
- case 0x8a: // Rn = MRB + Rx * Ry (UUF)
- case 0x8b: // Rn = MRB + Rx * Ry (UUFR)
- case 0x92: // Rn = MRB + Rx * Ry (SUI)
- case 0x9a: // Rn = MRB + Rx * Ry (SUF)
- case 0x9b: // Rn = MRB + Rx * Ry (SUFR)
- case 0xa2: // Rn = MRB + Rx * Ry (USI)
- case 0xaa: // Rn = MRB + Rx * Ry (USF)
- case 0xab: // Rn = MRB + Rx * Ry (USFR)
- case 0xba: // Rn = MRB + Rx * Ry (SSF)
- case 0xbb: // Rn = MRB + Rx * Ry (SSFR)
- case 0x84: // MRF = MRF + Rx * Ry (UUI)
- case 0x8c: // MRF = MRF + Rx * Ry (UUF)
- case 0x8d: // MRF = MRF + Rx * Ry (UUFR)
- case 0x94: // MRF = MRF + Rx * Ry (SUI)
- case 0x9c: // MRF = MRF + Rx * Ry (SUF)
- case 0x9d: // MRF = MRF + Rx * Ry (SUFR)
- case 0xa4: // MRF = MRF + Rx * Ry (USI)
- case 0xac: // MRF = MRF + Rx * Ry (USF)
- case 0xad: // MRF = MRF + Rx * Ry (USFR)
- case 0xb4: // MRF = MRF + Rx * Ry (SSI)
- case 0xbc: // MRF = MRF + Rx * Ry (SSF)
- case 0xbd: // MRF = MRF + Rx * Ry (SSFR)
- case 0x86: // MRB = MRB + Rx * Ry (UUI)
- case 0x8e: // MRB = MRB + Rx * Ry (UUF)
- case 0x8f: // MRB = MRB + Rx * Ry (UUFR)
- case 0x96: // MRB = MRB + Rx * Ry (SUI)
- case 0x9e: // MRB = MRB + Rx * Ry (SUF)
- case 0x9f: // MRB = MRB + Rx * Ry (SUFR)
- case 0xa6: // MRB = MRB + Rx * Ry (USI)
- case 0xae: // MRB = MRB + Rx * Ry (USF)
- case 0xaf: // MRB = MRB + Rx * Ry (USFR)
- case 0xb6: // MRB = MRB + Rx * Ry (SSI)
- case 0xbe: // MRB = MRB + Rx * Ry (SSF)
- case 0xbf: // MRB = MRB + Rx * Ry (SSFR)
- case 0xc0: // Rn = MRF - Rx * Ry (UUI)
- case 0xc8: // Rn = MRF - Rx * Ry (UUF)
- case 0xc9: // Rn = MRF - Rx * Ry (UUFR)
- case 0xd0: // Rn = MRF - Rx * Ry (SUI)
- case 0xd8: // Rn = MRF - Rx * Ry (SUF)
- case 0xd9: // Rn = MRF - Rx * Ry (SUFR)
- case 0xe0: // Rn = MRF - Rx * Ry (USI)
- case 0xe8: // Rn = MRF - Rx * Ry (USF)
- case 0xe9: // Rn = MRF - Rx * Ry (USFR)
- case 0xf0: // Rn = MRF - Rx * Ry (SSI)
- case 0xf8: // Rn = MRF - Rx * Ry (SSF)
- case 0xf9: // Rn = MRF - Rx * Ry (SSFR)
- case 0xc2: // Rn = MRB - Rx * Ry (UUI)
- case 0xca: // Rn = MRB - Rx * Ry (UUF)
- case 0xcb: // Rn = MRB - Rx * Ry (UUFR)
- case 0xd2: // Rn = MRB - Rx * Ry (SUI)
- case 0xda: // Rn = MRB - Rx * Ry (SUF)
- case 0xdb: // Rn = MRB - Rx * Ry (SUFR)
- case 0xe2: // Rn = MRB - Rx * Ry (USI)
- case 0xea: // Rn = MRB - Rx * Ry (USF)
- case 0xeb: // Rn = MRB - Rx * Ry (USFR)
- case 0xf2: // Rn = MRB - Rx * Ry (SSI)
- case 0xfa: // Rn = MRB - Rx * Ry (SSF)
- case 0xfb: // Rn = MRB - Rx * Ry (SSFR)
- case 0xc4: // MRF = MRF - Rx * Ry (UUI)
- case 0xcc: // MRF = MRF - Rx * Ry (UUF)
- case 0xcd: // MRF = MRF - Rx * Ry (UUFR)
- case 0xd4: // MRF = MRF - Rx * Ry (SUI)
- case 0xdc: // MRF = MRF - Rx * Ry (SUF)
- case 0xdd: // MRF = MRF - Rx * Ry (SUFR)
- case 0xe4: // MRF = MRF - Rx * Ry (USI)
- case 0xec: // MRF = MRF - Rx * Ry (USF)
- case 0xed: // MRF = MRF - Rx * Ry (USFR)
- case 0xf4: // MRF = MRF - Rx * Ry (SSI)
- case 0xfc: // MRF = MRF - Rx * Ry (SSF)
- case 0xfd: // MRF = MRF - Rx * Ry (SSFR)
- case 0xc6: // MRB = MRB - Rx * Ry (UUI)
- case 0xce: // MRB = MRB - Rx * Ry (UUF)
- case 0xcf: // MRB = MRB - Rx * Ry (UUFR)
- case 0xd6: // MRB = MRB - Rx * Ry (SUI)
- case 0xde: // MRB = MRB - Rx * Ry (SUF)
- case 0xdf: // MRB = MRB - Rx * Ry (SUFR)
- case 0xe6: // MRB = MRB - Rx * Ry (USI)
- case 0xee: // MRB = MRB - Rx * Ry (USF)
- case 0xef: // MRB = MRB - Rx * Ry (USFR)
- case 0xf6: // MRB = MRB - Rx * Ry (SSI)
- case 0xfe: // MRB = MRB - Rx * Ry (SSF)
- case 0xff: // MRB = MRB - Rx * Ry (SSFR)
- case 0x00: // Rn = SAT MRF (UI)
- case 0x01: // Rn = SAT MRF (SI)
- case 0x08: // Rn = SAT MRF (UF)
- case 0x09: // Rn = SAT MRF (SF)
- case 0x02: // Rn = SAT MRB (UI)
- case 0x03: // Rn = SAT MRB (SI)
- case 0x0a: // Rn = SAT MRB (UF)
- case 0x0b: // Rn = SAT MRB (SF)
- case 0x04: // MRF = SAT MRF (UI)
- case 0x05: // MRF = SAT MRF (SI)
- case 0x0c: // MRF = SAT MRF (UF)
- case 0x0d: // MRF = SAT MRF (SF)
- case 0x06: // MRB = SAT MRB (UI)
- case 0x07: // MRB = SAT MRB (SI)
- case 0x0e: // MRB = SAT MRB (UF)
- case 0x0f: // MRB = SAT MRB (SF)
- case 0x18: // Rn = RND MRF (U)
- case 0x19: // Rn = RND MRF (S)
- case 0x1a: // Rn = RND MRB (U)
- case 0x1b: // Rn = RND MRB (S)
- case 0x1c: // MRF = RND MRF (U)
- case 0x1d: // MRF = RND MRF (S)
- case 0x1e: // MRB = RND MRB (U)
- case 0x1f: // MRB = RND MRB (S)
+ case 0x48: // Rn = Rx * Ry (UUF)
+ case 0x49: // Rn = Rx * Ry (UUFR)
+ case 0x50: // Rn = Rx * Ry (SUI)
+ case 0x58: // Rn = Rx * Ry (SUF)
+ case 0x59: // Rn = Rx * Ry (SUFR)
+ case 0x60: // Rn = Rx * Ry (USI)
+ case 0x68: // Rn = Rx * Ry (USF)
+ case 0x69: // Rn = Rx * Ry (USFR)
+ case 0x78: // Rn = Rx * Ry (SSF)
+ case 0x79: // Rn = Rx * Ry (SSFR)
+ case 0x44: // MRF = Rx * Ry (UUI)
+ case 0x4c: // MRF = Rx * Ry (UUF)
+ case 0x4d: // MRF = Rx * Ry (UUFR)
+ case 0x54: // MRF = Rx * Ry (SUI)
+ case 0x5c: // MRF = Rx * Ry (SUF)
+ case 0x5d: // MRF = Rx * Ry (SUFR)
+ case 0x64: // MRF = Rx * Ry (USI)
+ case 0x6c: // MRF = Rx * Ry (USF)
+ case 0x6d: // MRF = Rx * Ry (USFR)
+ case 0x74: // MRF = Rx * Ry (SSI)
+ case 0x7c: // MRF = Rx * Ry (SSF)
+ case 0x7d: // MRF = Rx * Ry (SSFR)
+ case 0x46: // MRB = Rx * Ry (UUI)
+ case 0x4e: // MRB = Rx * Ry (UUF)
+ case 0x4f: // MRB = Rx * Ry (UUFR)
+ case 0x56: // MRB = Rx * Ry (SUI)
+ case 0x5e: // MRB = Rx * Ry (SUF)
+ case 0x5f: // MRB = Rx * Ry (SUFR)
+ case 0x66: // MRB = Rx * Ry (USI)
+ case 0x6e: // MRB = Rx * Ry (USF)
+ case 0x6f: // MRB = Rx * Ry (USFR)
+ case 0x76: // MRB = Rx * Ry (SSI)
+ case 0x7e: // MRB = Rx * Ry (SSF)
+ case 0x7f: // MRB = Rx * Ry (SSFR)
+ case 0x80: // Rn = MRF + Rx * Ry (UUI)
+ case 0x88: // Rn = MRF + Rx * Ry (UUF)
+ case 0x89: // Rn = MRF + Rx * Ry (UUFR)
+ case 0x90: // Rn = MRF + Rx * Ry (SUI)
+ case 0x98: // Rn = MRF + Rx * Ry (SUF)
+ case 0x99: // Rn = MRF + Rx * Ry (SUFR)
+ case 0xa0: // Rn = MRF + Rx * Ry (USI)
+ case 0xa8: // Rn = MRF + Rx * Ry (USF)
+ case 0xa9: // Rn = MRF + Rx * Ry (USFR)
+ case 0xb8: // Rn = MRF + Rx * Ry (SSF)
+ case 0xb9: // Rn = MRF + Rx * Ry (SSFR)
+ case 0x82: // Rn = MRB + Rx * Ry (UUI)
+ case 0x8a: // Rn = MRB + Rx * Ry (UUF)
+ case 0x8b: // Rn = MRB + Rx * Ry (UUFR)
+ case 0x92: // Rn = MRB + Rx * Ry (SUI)
+ case 0x9a: // Rn = MRB + Rx * Ry (SUF)
+ case 0x9b: // Rn = MRB + Rx * Ry (SUFR)
+ case 0xa2: // Rn = MRB + Rx * Ry (USI)
+ case 0xaa: // Rn = MRB + Rx * Ry (USF)
+ case 0xab: // Rn = MRB + Rx * Ry (USFR)
+ case 0xba: // Rn = MRB + Rx * Ry (SSF)
+ case 0xbb: // Rn = MRB + Rx * Ry (SSFR)
+ case 0x84: // MRF = MRF + Rx * Ry (UUI)
+ case 0x8c: // MRF = MRF + Rx * Ry (UUF)
+ case 0x8d: // MRF = MRF + Rx * Ry (UUFR)
+ case 0x94: // MRF = MRF + Rx * Ry (SUI)
+ case 0x9c: // MRF = MRF + Rx * Ry (SUF)
+ case 0x9d: // MRF = MRF + Rx * Ry (SUFR)
+ case 0xa4: // MRF = MRF + Rx * Ry (USI)
+ case 0xac: // MRF = MRF + Rx * Ry (USF)
+ case 0xad: // MRF = MRF + Rx * Ry (USFR)
+ case 0xb4: // MRF = MRF + Rx * Ry (SSI)
+ case 0xbc: // MRF = MRF + Rx * Ry (SSF)
+ case 0xbd: // MRF = MRF + Rx * Ry (SSFR)
+ case 0x86: // MRB = MRB + Rx * Ry (UUI)
+ case 0x8e: // MRB = MRB + Rx * Ry (UUF)
+ case 0x8f: // MRB = MRB + Rx * Ry (UUFR)
+ case 0x96: // MRB = MRB + Rx * Ry (SUI)
+ case 0x9e: // MRB = MRB + Rx * Ry (SUF)
+ case 0x9f: // MRB = MRB + Rx * Ry (SUFR)
+ case 0xa6: // MRB = MRB + Rx * Ry (USI)
+ case 0xae: // MRB = MRB + Rx * Ry (USF)
+ case 0xaf: // MRB = MRB + Rx * Ry (USFR)
+ case 0xb6: // MRB = MRB + Rx * Ry (SSI)
+ case 0xbe: // MRB = MRB + Rx * Ry (SSF)
+ case 0xbf: // MRB = MRB + Rx * Ry (SSFR)
+ case 0xc0: // Rn = MRF - Rx * Ry (UUI)
+ case 0xc8: // Rn = MRF - Rx * Ry (UUF)
+ case 0xc9: // Rn = MRF - Rx * Ry (UUFR)
+ case 0xd0: // Rn = MRF - Rx * Ry (SUI)
+ case 0xd8: // Rn = MRF - Rx * Ry (SUF)
+ case 0xd9: // Rn = MRF - Rx * Ry (SUFR)
+ case 0xe0: // Rn = MRF - Rx * Ry (USI)
+ case 0xe8: // Rn = MRF - Rx * Ry (USF)
+ case 0xe9: // Rn = MRF - Rx * Ry (USFR)
+ case 0xf0: // Rn = MRF - Rx * Ry (SSI)
+ case 0xf8: // Rn = MRF - Rx * Ry (SSF)
+ case 0xf9: // Rn = MRF - Rx * Ry (SSFR)
+ case 0xc2: // Rn = MRB - Rx * Ry (UUI)
+ case 0xca: // Rn = MRB - Rx * Ry (UUF)
+ case 0xcb: // Rn = MRB - Rx * Ry (UUFR)
+ case 0xd2: // Rn = MRB - Rx * Ry (SUI)
+ case 0xda: // Rn = MRB - Rx * Ry (SUF)
+ case 0xdb: // Rn = MRB - Rx * Ry (SUFR)
+ case 0xe2: // Rn = MRB - Rx * Ry (USI)
+ case 0xea: // Rn = MRB - Rx * Ry (USF)
+ case 0xeb: // Rn = MRB - Rx * Ry (USFR)
+ case 0xf2: // Rn = MRB - Rx * Ry (SSI)
+ case 0xfa: // Rn = MRB - Rx * Ry (SSF)
+ case 0xfb: // Rn = MRB - Rx * Ry (SSFR)
+ case 0xc4: // MRF = MRF - Rx * Ry (UUI)
+ case 0xcc: // MRF = MRF - Rx * Ry (UUF)
+ case 0xcd: // MRF = MRF - Rx * Ry (UUFR)
+ case 0xd4: // MRF = MRF - Rx * Ry (SUI)
+ case 0xdc: // MRF = MRF - Rx * Ry (SUF)
+ case 0xdd: // MRF = MRF - Rx * Ry (SUFR)
+ case 0xe4: // MRF = MRF - Rx * Ry (USI)
+ case 0xec: // MRF = MRF - Rx * Ry (USF)
+ case 0xed: // MRF = MRF - Rx * Ry (USFR)
+ case 0xf4: // MRF = MRF - Rx * Ry (SSI)
+ case 0xfc: // MRF = MRF - Rx * Ry (SSF)
+ case 0xfd: // MRF = MRF - Rx * Ry (SSFR)
+ case 0xc6: // MRB = MRB - Rx * Ry (UUI)
+ case 0xce: // MRB = MRB - Rx * Ry (UUF)
+ case 0xcf: // MRB = MRB - Rx * Ry (UUFR)
+ case 0xd6: // MRB = MRB - Rx * Ry (SUI)
+ case 0xde: // MRB = MRB - Rx * Ry (SUF)
+ case 0xdf: // MRB = MRB - Rx * Ry (SUFR)
+ case 0xe6: // MRB = MRB - Rx * Ry (USI)
+ case 0xee: // MRB = MRB - Rx * Ry (USF)
+ case 0xef: // MRB = MRB - Rx * Ry (USFR)
+ case 0xf6: // MRB = MRB - Rx * Ry (SSI)
+ case 0xfe: // MRB = MRB - Rx * Ry (SSF)
+ case 0xff: // MRB = MRB - Rx * Ry (SSFR)
+ case 0x00: // Rn = SAT MRF (UI)
+ case 0x01: // Rn = SAT MRF (SI)
+ case 0x08: // Rn = SAT MRF (UF)
+ case 0x09: // Rn = SAT MRF (SF)
+ case 0x02: // Rn = SAT MRB (UI)
+ case 0x03: // Rn = SAT MRB (SI)
+ case 0x0a: // Rn = SAT MRB (UF)
+ case 0x0b: // Rn = SAT MRB (SF)
+ case 0x04: // MRF = SAT MRF (UI)
+ case 0x05: // MRF = SAT MRF (SI)
+ case 0x0c: // MRF = SAT MRF (UF)
+ case 0x0d: // MRF = SAT MRF (SF)
+ case 0x06: // MRB = SAT MRB (UI)
+ case 0x07: // MRB = SAT MRB (SI)
+ case 0x0e: // MRB = SAT MRB (UF)
+ case 0x0f: // MRB = SAT MRB (SF)
+ case 0x18: // Rn = RND MRF (U)
+ case 0x19: // Rn = RND MRF (S)
+ case 0x1a: // Rn = RND MRB (U)
+ case 0x1b: // Rn = RND MRB (S)
+ case 0x1c: // MRF = RND MRF (U)
+ case 0x1d: // MRF = RND MRF (S)
+ case 0x1e: // MRB = RND MRB (U)
+ case 0x1f: // MRB = RND MRB (S)
generate_unimplemented_compute(block, compiler, desc);
return;
- case 0x14: // MRF = 0
+ case 0x14: // MRF = 0
UML_DMOV(block, mem(&m_core->mrf), 0);
if (MN_CALC_REQUIRED) UML_MOV(block, ASTAT_MN, 0);
if (MV_CALC_REQUIRED) UML_MOV(block, ASTAT_MV, 0);
@@ -4881,7 +4881,7 @@ void adsp21062_device::generate_compute(drcuml_block *block, compiler_state *com
if (MI_CALC_REQUIRED) UML_MOV(block, ASTAT_MI, 0);
return;
- case 0x16: // MRB = 0
+ case 0x16: // MRB = 0
UML_DMOV(block, mem(&m_core->mrb), 0);
if (MN_CALC_REQUIRED) UML_MOV(block, ASTAT_MN, 0);
if (MV_CALC_REQUIRED) UML_MOV(block, ASTAT_MV, 0);
@@ -4889,7 +4889,7 @@ void adsp21062_device::generate_compute(drcuml_block *block, compiler_state *com
if (MI_CALC_REQUIRED) UML_MOV(block, ASTAT_MI, 0);
return;
- case 0x30: // Fn = Fx * Fy
+ case 0x30: // Fn = Fx * Fy
UML_FSCOPYI(block, F0, REG(rx));
UML_FSCOPYI(block, F1, REG(ry));
UML_FSMUL(block, F0, F0, F1);
@@ -4900,19 +4900,19 @@ void adsp21062_device::generate_compute(drcuml_block *block, compiler_state *com
// TODO: MV, MU, MI flags
return;
- case 0x40: // Rn = Rx * Ry (UUI)
+ case 0x40: // Rn = Rx * Ry (UUI)
UML_MULU(block, I0, I0, REG(rx), REG(ry));
UML_MOV(block, REG(rn), I0);
// TODO: flags
return;
- case 0x70: // Rn = Rx * Ry (SSI)
+ case 0x70: // Rn = Rx * Ry (SSI)
UML_MULS(block, I0, I0, REG(rx), REG(ry));
UML_MOV(block, REG(rn), I0);
// TODO: flags
return;
- case 0xb0: // Rn = MRF + Rx * Ry (SSI)
+ case 0xb0: // Rn = MRF + Rx * Ry (SSI)
UML_DSEXT(block, I0, REG(rx), SIZE_DWORD);
UML_DSEXT(block, I1, REG(ry), SIZE_DWORD);
UML_DMULS(block, I0, I0, I0, I1);
@@ -4921,7 +4921,7 @@ void adsp21062_device::generate_compute(drcuml_block *block, compiler_state *com
// TODO: flags!
return;
- case 0xb2: // Rn = MRB + Rx * Ry (SSI)
+ case 0xb2: // Rn = MRB + Rx * Ry (SSI)
UML_DSEXT(block, I0, REG(rx), SIZE_DWORD);
UML_DSEXT(block, I1, REG(ry), SIZE_DWORD);
UML_DMULS(block, I0, I0, I0, I1);
@@ -4937,25 +4937,25 @@ void adsp21062_device::generate_compute(drcuml_block *block, compiler_state *com
break;
}
- case 2: // shifter operations
+ case 2: // shifter operations
{
switch (operation)
{
- case 0x04: // Rn = ASHIFT Rx BY Ry | <data8>
- case 0x44: // Rn = FDEP Rx BY Ry | <bit6>:<len6>
- case 0x4c: // Rn = FDEP Rx BY Ry | <bit6>:<len6> (SE)
- case 0x24: // Rn = Rn OR ASHIFT Rx BY Ry | <data8>
- case 0x6c: // Rn = Rn OR FDEP Rx BY Ry | <bit6>:<len6> (SE)
- case 0x80: // Rn = EXP Rx
- case 0x84: // Rn = EXP Rx (EX)
- case 0x88: // Rn = LEFTZ Rx
- case 0x8c: // Rn = LEFTO Rx
- case 0x90: // Rn = FPACK Fx
- case 0x94: // Fn = FUNPACK Rx
+ case 0x04: // Rn = ASHIFT Rx BY Ry | <data8>
+ case 0x44: // Rn = FDEP Rx BY Ry | <bit6>:<len6>
+ case 0x4c: // Rn = FDEP Rx BY Ry | <bit6>:<len6> (SE)
+ case 0x24: // Rn = Rn OR ASHIFT Rx BY Ry | <data8>
+ case 0x6c: // Rn = Rn OR FDEP Rx BY Ry | <bit6>:<len6> (SE)
+ case 0x80: // Rn = EXP Rx
+ case 0x84: // Rn = EXP Rx (EX)
+ case 0x88: // Rn = LEFTZ Rx
+ case 0x8c: // Rn = LEFTO Rx
+ case 0x90: // Rn = FPACK Fx
+ case 0x94: // Fn = FUNPACK Rx
generate_unimplemented_compute(block, compiler, desc);
return;
- case 0x00: // Rn = LSHIFT Rx BY Ry | <data8>
+ case 0x00: // Rn = LSHIFT Rx BY Ry | <data8>
{
code_label shift_neg = compiler->labelnum++;
code_label shift_end = compiler->labelnum++;
@@ -4980,7 +4980,7 @@ void adsp21062_device::generate_compute(drcuml_block *block, compiler_state *com
return;
}
- case 0x08: // Rn = ROT Rx BY Ry | <data8>
+ case 0x08: // Rn = ROT Rx BY Ry | <data8>
{
code_label shift_neg = compiler->labelnum++;
code_label shift_end = compiler->labelnum++;
@@ -5001,7 +5001,7 @@ void adsp21062_device::generate_compute(drcuml_block *block, compiler_state *com
return;
}
- case 0x20: // Rn = Rn OR LSHIFT Rx BY Ry | <data8>
+ case 0x20: // Rn = Rn OR LSHIFT Rx BY Ry | <data8>
{
code_label shift_neg = compiler->labelnum++;
code_label shift_end = compiler->labelnum++;
@@ -5027,12 +5027,12 @@ void adsp21062_device::generate_compute(drcuml_block *block, compiler_state *com
return;
}
- case 0x40: // Rn = FEXT Rx BY Ry | <bit6>:<len6>
+ case 0x40: // Rn = FEXT Rx BY Ry | <bit6>:<len6>
// extraction mask
UML_MOV(block, I0, REG(ry));
UML_SHR(block, I1, I0, 6);
- UML_AND(block, I1, I1, 0x3f); // i1 = len6
- UML_AND(block, I0, I0, 0x3f); // i0 = bit6
+ UML_AND(block, I1, I1, 0x3f); // i1 = len6
+ UML_AND(block, I0, I0, 0x3f); // i0 = bit6
UML_MOV(block, I3, 0xffffffff);
UML_SUB(block, I2, 32, I1);
UML_SHR(block, I3, I3, I2);
@@ -5050,12 +5050,12 @@ void adsp21062_device::generate_compute(drcuml_block *block, compiler_state *com
if (SS_CALC_REQUIRED) UML_MOV(block, ASTAT_SS, 0);
return;
- case 0x48: // Rn = FEXT Rx BY Ry | <bit6>:<len6> (SE)
+ case 0x48: // Rn = FEXT Rx BY Ry | <bit6>:<len6> (SE)
// extraction mask
UML_MOV(block, I0, REG(ry));
UML_SHR(block, I1, I0, 6);
- UML_AND(block, I1, I1, 0x3f); // i1 = len6
- UML_AND(block, I0, I0, 0x3f); // i0 = bit6
+ UML_AND(block, I1, I1, 0x3f); // i1 = len6
+ UML_AND(block, I0, I0, 0x3f); // i0 = bit6
UML_MOV(block, I3, 0xffffffff);
UML_SUB(block, I2, 32, I1);
UML_SHR(block, I3, I3, I2);
@@ -5079,12 +5079,12 @@ void adsp21062_device::generate_compute(drcuml_block *block, compiler_state *com
if (SS_CALC_REQUIRED) UML_MOV(block, ASTAT_SS, 0);
return;
- case 0x64: // Rn = Rn OR FDEP Rx BY Ry | <bit6>:<len6>
+ case 0x64: // Rn = Rn OR FDEP Rx BY Ry | <bit6>:<len6>
// extraction mask
UML_MOV(block, I0, REG(ry));
UML_SHR(block, I1, I0, 6);
- UML_AND(block, I1, I1, 0x3f); // i1 = len6
- UML_AND(block, I0, I0, 0x3f); // i0 = bit6
+ UML_AND(block, I1, I1, 0x3f); // i1 = len6
+ UML_AND(block, I0, I0, 0x3f); // i0 = bit6
UML_MOV(block, I3, 0xffffffff);
UML_SUB(block, I2, 32, I1);
UML_SHR(block, I3, I3, I2);
@@ -5102,7 +5102,7 @@ void adsp21062_device::generate_compute(drcuml_block *block, compiler_state *com
if (SS_CALC_REQUIRED) UML_MOV(block, ASTAT_SS, 0);
return;
- case 0xc0: // Rn = BSET Rx BY Ry | <data8>
+ case 0xc0: // Rn = BSET Rx BY Ry | <data8>
{
UML_MOV(block, I0, REG(ry));
UML_SHL(block, I1, 1, I0);
@@ -5117,7 +5117,7 @@ void adsp21062_device::generate_compute(drcuml_block *block, compiler_state *com
return;
}
- case 0xc4: // Rn = BCLR Rx BY Ry | <data8>
+ case 0xc4: // Rn = BCLR Rx BY Ry | <data8>
{
UML_MOV(block, I0, REG(ry));
UML_SHL(block, I1, 1, I0);
@@ -5133,14 +5133,14 @@ void adsp21062_device::generate_compute(drcuml_block *block, compiler_state *com
return;
}
- case 0xcc: // BTST Rx BY Ry | <data8>
+ case 0xcc: // BTST Rx BY Ry | <data8>
{
UML_MOV(block, I0, REG(ry));
UML_SHL(block, I1, 1, I0);
UML_TEST(block, REG(rx), I1);
if (SZ_CALC_REQUIRED) UML_SETc(block, COND_Z, ASTAT_SZ);
- if (SV_CALC_REQUIRED)
- UML_CMP(block, I0, 31);
+ if (SV_CALC_REQUIRED)
+ UML_CMP(block, I0, 31);
if (SV_CALC_REQUIRED) UML_SETc(block, COND_G, ASTAT_SV);
if (SS_CALC_REQUIRED) UML_MOV(block, ASTAT_SS, 0);
return;
@@ -5383,7 +5383,7 @@ void adsp21062_device::generate_do_condition(drcuml_block *block, compiler_state
// infinite loop
break;
case 0x0f: /* LCE */
- fatalerror("generate_do_condition 0x0f"); // this should only be used with counter loops
+ fatalerror("generate_do_condition 0x0f"); // this should only be used with counter loops
break;
case 0x10: /* NOT EQUAL */
UML_TEST(block, mem(&m_core->astat_delay_copy.az), 1);
@@ -5465,16 +5465,16 @@ void adsp21062_device::generate_shift_imm(drcuml_block *block, compiler_state *c
int len = (data >> 6) & 0x3f;
switch (shiftop)
- {
- case 0x11: // FDEP Rx BY <bit6>:<len6>
- case 0x13: // FDEP Rx BY <bit6>:<len6> (SE)
- case 0x1b: // Rn = Rn OR FDEP Rx BY <bit6>:<len6> (SE)
+ {
+ case 0x11: // FDEP Rx BY <bit6>:<len6>
+ case 0x13: // FDEP Rx BY <bit6>:<len6> (SE)
+ case 0x1b: // Rn = Rn OR FDEP Rx BY <bit6>:<len6> (SE)
UML_MOV(block, mem(&m_core->pc), desc->pc);
UML_DMOV(block, mem(&m_core->arg64), desc->opptr.q[0]);
UML_CALLC(block, cfunc_unimplemented_shiftimm, this);
break;
- case 0x00: // LSHIFT Rx BY <data8>
+ case 0x00: // LSHIFT Rx BY <data8>
if (abs(shift) >= 32)
{
UML_MOV(block, REG(rn), 0);
@@ -5495,7 +5495,7 @@ void adsp21062_device::generate_shift_imm(drcuml_block *block, compiler_state *c
}
return;
- case 0x01: // ASHIFT Rx BY <data8>
+ case 0x01: // ASHIFT Rx BY <data8>
if (abs(shift) >= 32)
{
UML_MOV(block, REG(rn), 0);
@@ -5518,7 +5518,7 @@ void adsp21062_device::generate_shift_imm(drcuml_block *block, compiler_state *c
}
return;
- case 0x02: // ROT Rx BY <data8>
+ case 0x02: // ROT Rx BY <data8>
if (shift < 0)
UML_ROR(block, REG(rn), REG(rx), (-shift) & 0x1f);
else
@@ -5528,7 +5528,7 @@ void adsp21062_device::generate_shift_imm(drcuml_block *block, compiler_state *c
if (SS_CALC_REQUIRED) UML_MOV(block, ASTAT_SS, 0);
return;
- case 0x08: // Rn = Rn OR LSHIFT Rx BY <data8>
+ case 0x08: // Rn = Rn OR LSHIFT Rx BY <data8>
if (abs(shift) >= 32)
{
UML_MOV(block, I0, 0);
@@ -5551,7 +5551,7 @@ void adsp21062_device::generate_shift_imm(drcuml_block *block, compiler_state *c
}
return;
- case 0x10: // FEXT Rx BY <bit6>:<len6>
+ case 0x10: // FEXT Rx BY <bit6>:<len6>
if (bit == 0)
{
UML_AND(block, REG(rn), REG(rx), MAKE_EXTRACT_MASK(bit, len));
@@ -5567,7 +5567,7 @@ void adsp21062_device::generate_shift_imm(drcuml_block *block, compiler_state *c
if (SS_CALC_REQUIRED) UML_MOV(block, ASTAT_SS, 0);
return;
- case 0x12: // FEXT Rx BY <bit6>:<len6> (SE)
+ case 0x12: // FEXT Rx BY <bit6>:<len6> (SE)
UML_AND(block, I0, REG(rx), MAKE_EXTRACT_MASK(bit, len));
UML_SHL(block, I0, I0, 32 - (bit + len));
UML_SAR(block, REG(rn), I0, 32 - (bit + len) + bit);
@@ -5577,7 +5577,7 @@ void adsp21062_device::generate_shift_imm(drcuml_block *block, compiler_state *c
if (SS_CALC_REQUIRED) UML_MOV(block, ASTAT_SS, 0);
return;
- case 0x19: // Rn = Rn OR FDEP Rx BY <bit6>:<len6>
+ case 0x19: // Rn = Rn OR FDEP Rx BY <bit6>:<len6>
UML_AND(block, I0, REG(rx), MAKE_EXTRACT_MASK(0, len));
if (bit > 0)
UML_SHL(block, I0, I0, bit);
@@ -5586,10 +5586,10 @@ void adsp21062_device::generate_shift_imm(drcuml_block *block, compiler_state *c
if (SZ_CALC_REQUIRED) UML_SETc(block, COND_Z, ASTAT_SZ);
if (SV_CALC_REQUIRED && (bit + len) > 32) UML_MOV(block, ASTAT_SV, 1);
if (SV_CALC_REQUIRED && (bit + len) <= 32) UML_MOV(block, ASTAT_SV, 0);
- if (SS_CALC_REQUIRED) UML_MOV(block, ASTAT_SS, 0);
+ if (SS_CALC_REQUIRED) UML_MOV(block, ASTAT_SS, 0);
return;
- case 0x30: // BSET Rx BY <data8>
+ case 0x30: // BSET Rx BY <data8>
UML_OR(block, REG(rn), REG(rx), 1 << data);
if (SZ_CALC_REQUIRED) UML_SETc(block, COND_Z, ASTAT_SZ);
if (SV_CALC_REQUIRED && data > 31) UML_MOV(block, ASTAT_SV, 1);
@@ -5597,7 +5597,7 @@ void adsp21062_device::generate_shift_imm(drcuml_block *block, compiler_state *c
if (SS_CALC_REQUIRED) UML_MOV(block, ASTAT_SS, 0);
return;
- case 0x31: // BCLR Rx By <data8>
+ case 0x31: // BCLR Rx By <data8>
UML_AND(block, REG(rn), REG(rx), ~(1 << data));
if (SZ_CALC_REQUIRED) UML_SETc(block, COND_Z, ASTAT_SZ);
if (SV_CALC_REQUIRED && data > 31) UML_MOV(block, ASTAT_SV, 1);
@@ -5605,7 +5605,7 @@ void adsp21062_device::generate_shift_imm(drcuml_block *block, compiler_state *c
if (SS_CALC_REQUIRED) UML_MOV(block, ASTAT_SS, 0);
return;
- case 0x32: // BTGL Rx BY <data8>
+ case 0x32: // BTGL Rx BY <data8>
UML_XOR(block, REG(rn), REG(rx), 1 << data);
if (SZ_CALC_REQUIRED) UML_SETc(block, COND_Z, ASTAT_SZ);
if (SV_CALC_REQUIRED && data > 31) UML_MOV(block, ASTAT_SV, 1);
@@ -5613,8 +5613,8 @@ void adsp21062_device::generate_shift_imm(drcuml_block *block, compiler_state *c
if (SS_CALC_REQUIRED) UML_MOV(block, ASTAT_SS, 0);
return;
- case 0x33: // BTST Rx BY <data8>
- UML_TEST(block, REG(rx), 1 << data);
+ case 0x33: // BTST Rx BY <data8>
+ UML_TEST(block, REG(rx), 1 << data);
if (SZ_CALC_REQUIRED) UML_SETc(block, COND_Z, ASTAT_SZ);
if (SV_CALC_REQUIRED && data > 31) UML_MOV(block, ASTAT_SV, 1);
if (SV_CALC_REQUIRED && data <= 31) UML_MOV(block, ASTAT_SV, 0);
@@ -5627,4 +5627,4 @@ void adsp21062_device::generate_shift_imm(drcuml_block *block, compiler_state *c
UML_CALLC(block, cfunc_unimplemented_compute, this);
return;
}
-} \ No newline at end of file
+}
diff --git a/src/devices/cpu/sharc/sharcfe.cpp b/src/devices/cpu/sharc/sharcfe.cpp
index bae9014ee33..105eea6c66c 100644
--- a/src/devices/cpu/sharc/sharcfe.cpp
+++ b/src/devices/cpu/sharc/sharcfe.cpp
@@ -10,62 +10,62 @@
#include "emu.h"
#include "sharcfe.h"
-#define REG_USED(desc,x) do { (desc).regin[0] |= 1 << (x); } while(0)
-#define REG_MODIFIED(desc,x) do { (desc).regout[0] |= 1 << (x); } while(0)
-
-#define AZ_USED(desc) do { (desc).regin[0] |= 1 << 16; } while(0)
-#define AZ_MODIFIED(desc) do { (desc).regout[0] |= 1 << 16; } while(0)
-#define AV_USED(desc) do { (desc).regin[0] |= 1 << 17; } while(0)
-#define AV_MODIFIED(desc) do { (desc).regout[0] |= 1 << 17; } while(0)
-#define AN_USED(desc) do { (desc).regin[0] |= 1 << 18; } while(0)
-#define AN_MODIFIED(desc) do { (desc).regout[0] |= 1 << 18; } while(0)
-#define AC_USED(desc) do { (desc).regin[0] |= 1 << 19; } while(0)
-#define AC_MODIFIED(desc) do { (desc).regout[0] |= 1 << 19; } while(0)
-#define AS_USED(desc) do { (desc).regin[0] |= 1 << 20; } while(0)
-#define AS_MODIFIED(desc) do { (desc).regout[0] |= 1 << 20; } while(0)
-#define AI_USED(desc) do { (desc).regin[0] |= 1 << 21; } while(0)
-#define AI_MODIFIED(desc) do { (desc).regout[0] |= 1 << 21; } while(0)
-#define MN_USED(desc) do { (desc).regin[0] |= 1 << 22; } while(0)
-#define MN_MODIFIED(desc) do { (desc).regout[0] |= 1 << 22; } while(0)
-#define MV_USED(desc) do { (desc).regin[0] |= 1 << 23; } while(0)
-#define MV_MODIFIED(desc) do { (desc).regout[0] |= 1 << 23; } while(0)
-#define MU_USED(desc) do { (desc).regin[0] |= 1 << 24; } while(0)
-#define MU_MODIFIED(desc) do { (desc).regout[0] |= 1 << 24; } while(0)
-#define MI_USED(desc) do { (desc).regin[0] |= 1 << 25; } while(0)
-#define MI_MODIFIED(desc) do { (desc).regout[0] |= 1 << 25; } while(0)
-#define SV_USED(desc) do { (desc).regin[0] |= 1 << 26; } while(0)
-#define SV_MODIFIED(desc) do { (desc).regout[0] |= 1 << 26; } while(0)
-#define SZ_USED(desc) do { (desc).regin[0] |= 1 << 27; } while(0)
-#define SZ_MODIFIED(desc) do { (desc).regout[0] |= 1 << 27; } while(0)
-#define SS_USED(desc) do { (desc).regin[0] |= 1 << 28; } while(0)
-#define SS_MODIFIED(desc) do { (desc).regout[0] |= 1 << 28; } while(0)
-#define BTF_USED(desc) do { (desc).regin[0] |= 1 << 29; } while(0)
-#define BTF_MODIFIED(desc) do { (desc).regout[0] |= 1 << 29; } while(0)
-#define AF_USED(desc) do { (desc).regin[0] |= 1 << 30; } while(0)
-#define AF_MODIFIED(desc) do { (desc).regout[0] |= 1 << 30; } while(0)
-
-#define ALU_FLAGS_MODIFIED(desc) do { AZ_MODIFIED(desc);AN_MODIFIED(desc);AV_MODIFIED(desc);AC_MODIFIED(desc);AS_MODIFIED(desc);AI_MODIFIED(desc); } while(0)
-#define MULT_FLAGS_MODIFIED(desc) do { MN_MODIFIED(desc);MV_MODIFIED(desc);MU_MODIFIED(desc);MI_MODIFIED(desc); } while(0)
-#define SHIFT_FLAGS_MODIFIED(desc) do { SZ_MODIFIED(desc);SV_MODIFIED(desc);SS_MODIFIED(desc); } while(0)
-
-
-#define PM_I_USED(desc,x) do { (desc).regin[1] |= 1 << (x); } while(0)
-#define PM_I_MODIFIED(desc,x) do { (desc).regout[1] |= 1 << (x); } while(0)
-#define PM_M_USED(desc,x) do { (desc).regin[1] |= 1 << ((x) + 8); } while(0)
-#define PM_M_MODIFIED(desc,x) do { (desc).regout[1] |= 1 << ((x) + 8); } while(0)
-#define PM_B_USED(desc,x) do { (desc).regin[1] |= 1 << ((x) + 16); } while(0)
-#define PM_B_MODIFIED(desc,x) do { (desc).regout[1] |= 1 << ((x) + 16); } while(0)
-#define PM_L_USED(desc,x) do { (desc).regin[1] |= 1 << ((x) + 24); } while(0)
-#define PM_L_MODIFIED(desc,x) do { (desc).regout[1] |= 1 << ((x) + 24); } while(0)
-
-#define DM_I_USED(desc,x) do { (desc).regin[2] |= 1 << (x); } while(0)
-#define DM_I_MODIFIED(desc,x) do { (desc).regout[2] |= 1 << (x); } while(0)
-#define DM_M_USED(desc,x) do { (desc).regin[2] |= 1 << ((x) + 8); } while(0)
-#define DM_M_MODIFIED(desc,x) do { (desc).regout[2] |= 1 << ((x) + 8); } while(0)
-#define DM_B_USED(desc,x) do { (desc).regin[2] |= 1 << ((x) + 16); } while(0)
-#define DM_B_MODIFIED(desc,x) do { (desc).regout[2] |= 1 << ((x) + 16); } while(0)
-#define DM_L_USED(desc,x) do { (desc).regin[2] |= 1 << ((x) + 24); } while(0)
-#define DM_L_MODIFIED(desc,x) do { (desc).regout[2] |= 1 << ((x) + 24); } while(0)
+#define REG_USED(desc,x) do { (desc).regin[0] |= 1 << (x); } while(0)
+#define REG_MODIFIED(desc,x) do { (desc).regout[0] |= 1 << (x); } while(0)
+
+#define AZ_USED(desc) do { (desc).regin[0] |= 1 << 16; } while(0)
+#define AZ_MODIFIED(desc) do { (desc).regout[0] |= 1 << 16; } while(0)
+#define AV_USED(desc) do { (desc).regin[0] |= 1 << 17; } while(0)
+#define AV_MODIFIED(desc) do { (desc).regout[0] |= 1 << 17; } while(0)
+#define AN_USED(desc) do { (desc).regin[0] |= 1 << 18; } while(0)
+#define AN_MODIFIED(desc) do { (desc).regout[0] |= 1 << 18; } while(0)
+#define AC_USED(desc) do { (desc).regin[0] |= 1 << 19; } while(0)
+#define AC_MODIFIED(desc) do { (desc).regout[0] |= 1 << 19; } while(0)
+#define AS_USED(desc) do { (desc).regin[0] |= 1 << 20; } while(0)
+#define AS_MODIFIED(desc) do { (desc).regout[0] |= 1 << 20; } while(0)
+#define AI_USED(desc) do { (desc).regin[0] |= 1 << 21; } while(0)
+#define AI_MODIFIED(desc) do { (desc).regout[0] |= 1 << 21; } while(0)
+#define MN_USED(desc) do { (desc).regin[0] |= 1 << 22; } while(0)
+#define MN_MODIFIED(desc) do { (desc).regout[0] |= 1 << 22; } while(0)
+#define MV_USED(desc) do { (desc).regin[0] |= 1 << 23; } while(0)
+#define MV_MODIFIED(desc) do { (desc).regout[0] |= 1 << 23; } while(0)
+#define MU_USED(desc) do { (desc).regin[0] |= 1 << 24; } while(0)
+#define MU_MODIFIED(desc) do { (desc).regout[0] |= 1 << 24; } while(0)
+#define MI_USED(desc) do { (desc).regin[0] |= 1 << 25; } while(0)
+#define MI_MODIFIED(desc) do { (desc).regout[0] |= 1 << 25; } while(0)
+#define SV_USED(desc) do { (desc).regin[0] |= 1 << 26; } while(0)
+#define SV_MODIFIED(desc) do { (desc).regout[0] |= 1 << 26; } while(0)
+#define SZ_USED(desc) do { (desc).regin[0] |= 1 << 27; } while(0)
+#define SZ_MODIFIED(desc) do { (desc).regout[0] |= 1 << 27; } while(0)
+#define SS_USED(desc) do { (desc).regin[0] |= 1 << 28; } while(0)
+#define SS_MODIFIED(desc) do { (desc).regout[0] |= 1 << 28; } while(0)
+#define BTF_USED(desc) do { (desc).regin[0] |= 1 << 29; } while(0)
+#define BTF_MODIFIED(desc) do { (desc).regout[0] |= 1 << 29; } while(0)
+#define AF_USED(desc) do { (desc).regin[0] |= 1 << 30; } while(0)
+#define AF_MODIFIED(desc) do { (desc).regout[0] |= 1 << 30; } while(0)
+
+#define ALU_FLAGS_MODIFIED(desc) do { AZ_MODIFIED(desc);AN_MODIFIED(desc);AV_MODIFIED(desc);AC_MODIFIED(desc);AS_MODIFIED(desc);AI_MODIFIED(desc); } while(0)
+#define MULT_FLAGS_MODIFIED(desc) do { MN_MODIFIED(desc);MV_MODIFIED(desc);MU_MODIFIED(desc);MI_MODIFIED(desc); } while(0)
+#define SHIFT_FLAGS_MODIFIED(desc) do { SZ_MODIFIED(desc);SV_MODIFIED(desc);SS_MODIFIED(desc); } while(0)
+
+
+#define PM_I_USED(desc,x) do { (desc).regin[1] |= 1 << (x); } while(0)
+#define PM_I_MODIFIED(desc,x) do { (desc).regout[1] |= 1 << (x); } while(0)
+#define PM_M_USED(desc,x) do { (desc).regin[1] |= 1 << ((x) + 8); } while(0)
+#define PM_M_MODIFIED(desc,x) do { (desc).regout[1] |= 1 << ((x) + 8); } while(0)
+#define PM_B_USED(desc,x) do { (desc).regin[1] |= 1 << ((x) + 16); } while(0)
+#define PM_B_MODIFIED(desc,x) do { (desc).regout[1] |= 1 << ((x) + 16); } while(0)
+#define PM_L_USED(desc,x) do { (desc).regin[1] |= 1 << ((x) + 24); } while(0)
+#define PM_L_MODIFIED(desc,x) do { (desc).regout[1] |= 1 << ((x) + 24); } while(0)
+
+#define DM_I_USED(desc,x) do { (desc).regin[2] |= 1 << (x); } while(0)
+#define DM_I_MODIFIED(desc,x) do { (desc).regout[2] |= 1 << (x); } while(0)
+#define DM_M_USED(desc,x) do { (desc).regin[2] |= 1 << ((x) + 8); } while(0)
+#define DM_M_MODIFIED(desc,x) do { (desc).regout[2] |= 1 << ((x) + 8); } while(0)
+#define DM_B_USED(desc,x) do { (desc).regin[2] |= 1 << ((x) + 16); } while(0)
+#define DM_B_MODIFIED(desc,x) do { (desc).regout[2] |= 1 << ((x) + 16); } while(0)
+#define DM_L_USED(desc,x) do { (desc).regin[2] |= 1 << ((x) + 24); } while(0)
+#define DM_L_MODIFIED(desc,x) do { (desc).regout[2] |= 1 << ((x) + 24); } while(0)
sharc_frontend::sharc_frontend(adsp21062_device *sharc, UINT32 window_start, UINT32 window_end, UINT32 max_sequence)
@@ -221,12 +221,12 @@ bool sharc_frontend::describe(opcode_desc &desc, const opcode_desc *prev)
switch ((opcode >> 45) & 7)
{
- case 0: // subops
+ case 0: // subops
{
UINT32 subop = (opcode >> 40) & 0x1f;
switch (subop)
{
- case 0x00: // NOP / idle |000|00000|
+ case 0x00: // NOP / idle |000|00000|
if (opcode & U64(0x008000000000))
{
// IDLE
@@ -236,9 +236,9 @@ bool sharc_frontend::describe(opcode_desc &desc, const opcode_desc *prev)
{
// NOP
}
- break;
+ break;
- case 0x01: // compute |000|00001|
+ case 0x01: // compute |000|00001|
{
int cond = (opcode >> 33) & 0x1f;
describe_if_condition(desc, cond);
@@ -248,7 +248,7 @@ bool sharc_frontend::describe(opcode_desc &desc, const opcode_desc *prev)
break;
}
- case 0x02: // immediate shift |000|00010|
+ case 0x02: // immediate shift |000|00010|
{
int shiftop = (opcode >> 16) & 0x3f;
int rn = (opcode >> 4) & 0xf;
@@ -261,8 +261,8 @@ bool sharc_frontend::describe(opcode_desc &desc, const opcode_desc *prev)
return false;
break;
}
-
- case 0x04: // compute / modify |000|00100|
+
+ case 0x04: // compute / modify |000|00100|
{
int g = (opcode >> 38) & 0x1;
int m = (opcode >> 27) & 0x7;
@@ -291,8 +291,8 @@ bool sharc_frontend::describe(opcode_desc &desc, const opcode_desc *prev)
break;
}
- case 0x06: // direct jump|call |000|00110|
- {
+ case 0x06: // direct jump|call |000|00110|
+ {
int j = (opcode >> 26) & 0x1;
int b = (opcode >> 39) & 0x1;
int cond = (opcode >> 33) & 0x1f;
@@ -312,7 +312,7 @@ bool sharc_frontend::describe(opcode_desc &desc, const opcode_desc *prev)
break;
}
- case 0x07: // direct jump|call |000|00111|
+ case 0x07: // direct jump|call |000|00111|
{
int j = (opcode >> 26) & 0x1;
int b = (opcode >> 39) & 0x1;
@@ -333,8 +333,8 @@ bool sharc_frontend::describe(opcode_desc &desc, const opcode_desc *prev)
break;
}
- case 0x08: // indirect jump|call / compute |000|01000|
- {
+ case 0x08: // indirect jump|call / compute |000|01000|
+ {
int j = (opcode >> 26) & 0x1;
int b = (opcode >> 39) & 0x1;
int pmi = (opcode >> 30) & 0x7;
@@ -361,12 +361,12 @@ bool sharc_frontend::describe(opcode_desc &desc, const opcode_desc *prev)
break;
}
- case 0x09: // indirect jump|call / compute |000|01001|
+ case 0x09: // indirect jump|call / compute |000|01001|
{
int j = (opcode >> 26) & 0x1;
int b = (opcode >> 39) & 0x1;
int cond = (opcode >> 33) & 0x1f;
-
+
if (!describe_compute(desc, opcode))
return false;
@@ -384,7 +384,7 @@ bool sharc_frontend::describe(opcode_desc &desc, const opcode_desc *prev)
break;
}
- case 0x0a: // return from subroutine / compute |000|01010|
+ case 0x0a: // return from subroutine / compute |000|01010|
{
int cond = (opcode >> 33) & 0x1f;
int j = (opcode >> 26) & 0x1;
@@ -404,7 +404,7 @@ bool sharc_frontend::describe(opcode_desc &desc, const opcode_desc *prev)
break;
}
- case 0x0b: // return from interrupt / compute |000|01011|
+ case 0x0b: // return from interrupt / compute |000|01011|
{
int cond = (opcode >> 33) & 0x1f;
int j = (opcode >> 26) & 0x1;
@@ -424,7 +424,7 @@ bool sharc_frontend::describe(opcode_desc &desc, const opcode_desc *prev)
break;
}
- case 0x0c: // do until counter expired |000|01100|
+ case 0x0c: // do until counter expired |000|01100|
{
int offset = SIGN_EXTEND24(opcode & 0xffffff);
@@ -439,7 +439,7 @@ bool sharc_frontend::describe(opcode_desc &desc, const opcode_desc *prev)
break;
}
- case 0x0d: // do until counter expired |000|01101|
+ case 0x0d: // do until counter expired |000|01101|
{
int ureg = (opcode >> 32) & 0xff;
if (!describe_ureg_access(desc, ureg, UREG_READ))
@@ -458,7 +458,7 @@ bool sharc_frontend::describe(opcode_desc &desc, const opcode_desc *prev)
break;
}
- case 0x0e: // do until |000|01110|
+ case 0x0e: // do until |000|01110|
{
int offset = SIGN_EXTEND24(opcode & 0xffffff);
int cond = (opcode >> 33) & 0x1f;
@@ -472,8 +472,8 @@ bool sharc_frontend::describe(opcode_desc &desc, const opcode_desc *prev)
/*
loop.astat_check_pc = loop.end_pc - 2;
if (loop.astat_check_pc < loop.start_pc)
- fatalerror("describe_compute: conditional loop < 2 at %08X", desc.pc);
- */
+ fatalerror("describe_compute: conditional loop < 2 at %08X", desc.pc);
+ */
int jump_diff = loop.end_pc - loop.start_pc;
if (jump_diff >= 2)
@@ -488,7 +488,7 @@ bool sharc_frontend::describe(opcode_desc &desc, const opcode_desc *prev)
break;
}
- case 0x0f: // immediate data -> ureg |000|01111|
+ case 0x0f: // immediate data -> ureg |000|01111|
{
int ureg = (opcode >> 32) & 0xff;
if (!describe_ureg_access(desc, ureg, UREG_WRITE))
@@ -496,7 +496,7 @@ bool sharc_frontend::describe(opcode_desc &desc, const opcode_desc *prev)
break;
}
- case 0x10: // ureg <-> DM|PM (direct) |000|100|G|D|
+ case 0x10: // ureg <-> DM|PM (direct) |000|100|G|D|
case 0x11:
case 0x12:
case 0x13:
@@ -518,7 +518,7 @@ bool sharc_frontend::describe(opcode_desc &desc, const opcode_desc *prev)
break;
}
- case 0x14: // system register bit manipulation |000|10100|
+ case 0x14: // system register bit manipulation |000|10100|
{
int bop = (opcode >> 37) & 0x7;
int sreg = (opcode >> 32) & 0xf;
@@ -526,10 +526,10 @@ bool sharc_frontend::describe(opcode_desc &desc, const opcode_desc *prev)
switch (bop)
{
- case 0: // SET
- case 1: // CLEAR
- case 2: // TOGGLE
- if (sreg == 0x7c) // ASTAT
+ case 0: // SET
+ case 1: // CLEAR
+ case 2: // TOGGLE
+ if (sreg == 0x7c) // ASTAT
{
if (data & adsp21062_device::AZ)
{
@@ -594,8 +594,8 @@ bool sharc_frontend::describe(opcode_desc &desc, const opcode_desc *prev)
}
break;
- case 4: // TEST
- case 5: // XOR
+ case 4: // TEST
+ case 5: // XOR
BTF_MODIFIED(desc);
break;
@@ -606,13 +606,13 @@ bool sharc_frontend::describe(opcode_desc &desc, const opcode_desc *prev)
break;
}
- case 0x16: // I register modify / bit-reverse |000|10110|
+ case 0x16: // I register modify / bit-reverse |000|10110|
{
- if (opcode & U64(0x008000000000)) // bit reverse
+ if (opcode & U64(0x008000000000)) // bit reverse
{
fatalerror("sharc_frontend::describe: bit reverse unimplemented");
}
- else // modify
+ else // modify
{
int g = (opcode >> 38) & 0x1;
int i = (opcode >> 32) & 0x7;
@@ -625,17 +625,17 @@ bool sharc_frontend::describe(opcode_desc &desc, const opcode_desc *prev)
break;
}
- case 0x17: // push|pop stacks / flush cache |000|10111|
+ case 0x17: // push|pop stacks / flush cache |000|10111|
break;
- case 0x18: // cjump |000|11000|
+ case 0x18: // cjump |000|11000|
fatalerror("sharc_frontend::describe: cjump unimplemented");
break;
- case 0x19: // rframe |000|11001|
+ case 0x19: // rframe |000|11001|
fatalerror("sharc_frontend::describe: rframe unimplemented");
break;
-
+
default:
fatalerror("sharc_frontend::describe: unknown subop %02X in opcode %04X%08X", subop, (UINT16)(opcode >> 32), (UINT32)(opcode));
return false;
@@ -643,7 +643,7 @@ bool sharc_frontend::describe(opcode_desc &desc, const opcode_desc *prev)
break;
}
- case 1: // compute / dreg <-> DM / dreg <-> PM |001|
+ case 1: // compute / dreg <-> DM / dreg <-> PM |001|
{
if (!describe_compute(desc, opcode))
return false;
@@ -689,7 +689,7 @@ bool sharc_frontend::describe(opcode_desc &desc, const opcode_desc *prev)
break;
}
- case 2: // compute / ureg <-> DM|PM, register modify |010|
+ case 2: // compute / ureg <-> DM|PM, register modify |010|
{
if (!describe_compute(desc, opcode))
return false;
@@ -737,7 +737,7 @@ bool sharc_frontend::describe(opcode_desc &desc, const opcode_desc *prev)
if (!describe_compute(desc, opcode))
return false;
- if (opcode & U64(0x100000000000)) // compute / ureg <-> ureg |011|1|
+ if (opcode & U64(0x100000000000)) // compute / ureg <-> ureg |011|1|
{
int src_ureg = (opcode >> 36) & 0xff;
int dst_ureg = (opcode >> 23) & 0xff;
@@ -750,7 +750,7 @@ bool sharc_frontend::describe(opcode_desc &desc, const opcode_desc *prev)
if (!describe_ureg_access(desc, dst_ureg, UREG_WRITE))
return false;
}
- else // compute / dreg <-> DM|PM, immediate modify |011|0|
+ else // compute / dreg <-> DM|PM, immediate modify |011|0|
{
int u = (opcode >> 38) & 0x1;
int d = (opcode >> 39) & 0x1;
@@ -771,13 +771,13 @@ bool sharc_frontend::describe(opcode_desc &desc, const opcode_desc *prev)
REG_MODIFIED(desc, dreg);
desc.flags |= OPFLAG_READS_MEMORY;
}
-
+
if (g)
{
// PM
PM_I_USED(desc, i);
- if (u) // post-modify with update
+ if (u) // post-modify with update
{
PM_I_MODIFIED(desc, i);
}
@@ -787,7 +787,7 @@ bool sharc_frontend::describe(opcode_desc &desc, const opcode_desc *prev)
// DM
DM_I_USED(desc, i);
- if (u) // post-modify with update
+ if (u) // post-modify with update
{
DM_I_MODIFIED(desc, i);
}
@@ -798,7 +798,7 @@ bool sharc_frontend::describe(opcode_desc &desc, const opcode_desc *prev)
case 4:
{
- if (opcode & U64(0x100000000000)) // immediate data -> DM|PM |100|1|
+ if (opcode & U64(0x100000000000)) // immediate data -> DM|PM |100|1|
{
int i = (opcode >> 41) & 0x7;
int m = (opcode >> 38) & 0x7;
@@ -821,7 +821,7 @@ bool sharc_frontend::describe(opcode_desc &desc, const opcode_desc *prev)
DM_M_USED(desc, m);
}
}
- else // immediate shift / dreg <-> DM|PM |100|0|
+ else // immediate shift / dreg <-> DM|PM |100|0|
{
int i = (opcode >> 41) & 0x7;
int m = (opcode >> 38) & 0x7;
@@ -867,7 +867,7 @@ bool sharc_frontend::describe(opcode_desc &desc, const opcode_desc *prev)
break;
}
- case 5: // ureg <-> DM|PM (indirect) |101|
+ case 5: // ureg <-> DM|PM (indirect) |101|
{
int ureg = (opcode >> 32) & 0xff;
int d = (opcode >> 40) & 1;
@@ -890,11 +890,11 @@ bool sharc_frontend::describe(opcode_desc &desc, const opcode_desc *prev)
if (g)
PM_I_USED(desc, i);
else
- DM_I_USED(desc, i);
+ DM_I_USED(desc, i);
break;
}
- case 6: // indirect jump / compute / dreg <-> DM |110|
+ case 6: // indirect jump / compute / dreg <-> DM |110|
{
int d = (opcode >> 44) & 0x1;
int dmi = (opcode >> 41) & 0x7;
@@ -936,7 +936,7 @@ bool sharc_frontend::describe(opcode_desc &desc, const opcode_desc *prev)
break;
}
- case 7: // indirect jump / compute / dreg <-> DM |111|
+ case 7: // indirect jump / compute / dreg <-> DM |111|
{
int d = (opcode >> 44) & 0x1;
int dmi = (opcode >> 41) & 0x7;
@@ -990,7 +990,7 @@ bool sharc_frontend::describe_compute(opcode_desc &desc, UINT64 opcode)
int rx = (opcode >> 4) & 0xf;
int ry = (opcode >> 0) & 0xf;
- if (opcode & 0x400000) // multi-function operation
+ if (opcode & 0x400000) // multi-function operation
{
UINT32 multiop = (opcode >> 16) & 0x3f;
int fm = rs;
@@ -1002,15 +1002,15 @@ bool sharc_frontend::describe_compute(opcode_desc &desc, UINT64 opcode)
switch (multiop)
{
- case 0x00: // Rn = MRxx
+ case 0x00: // Rn = MRxx
REG_MODIFIED(desc, rn);
break;
- case 0x01: // MRxx = Rn
+ case 0x01: // MRxx = Rn
REG_USED(desc, rn);
break;
- case 0x07: // Ra = Rx + Ry, Rs = Rx - Ry
- case 0x0f: // Fa = Fx + Fy, Fs = Fx - Fy
+ case 0x07: // Ra = Rx + Ry, Rs = Rx - Ry
+ case 0x0f: // Fa = Fx + Fy, Fs = Fx - Fy
REG_USED(desc, rx);
REG_USED(desc, ry);
REG_MODIFIED(desc, ra);
@@ -1018,9 +1018,9 @@ bool sharc_frontend::describe_compute(opcode_desc &desc, UINT64 opcode)
ALU_FLAGS_MODIFIED(desc);
break;
- case 0x04: // Rm = R3-0 * R7-4 (SSFR), Ra = R11-8 + R15-12
- case 0x05: // Rm = R3-0 * R7-4 (SSFR), Ra = R11-8 - R15-12
- case 0x06: // Rm = R3-0 * R7-4 (SSFR), Ra = (R11-8 + R15-12) / 2
+ case 0x04: // Rm = R3-0 * R7-4 (SSFR), Ra = R11-8 + R15-12
+ case 0x05: // Rm = R3-0 * R7-4 (SSFR), Ra = R11-8 - R15-12
+ case 0x06: // Rm = R3-0 * R7-4 (SSFR), Ra = (R11-8 + R15-12) / 2
REG_USED(desc, fxm);
REG_USED(desc, fym);
REG_USED(desc, fxa);
@@ -1031,9 +1031,9 @@ bool sharc_frontend::describe_compute(opcode_desc &desc, UINT64 opcode)
MULT_FLAGS_MODIFIED(desc);
break;
- case 0x08: // MRF = MRF + R3-0 * R7-4 (SSF), Ra = R11-8 + R15-12
- case 0x09: // MRF = MRF + R3-0 * R7-4 (SSF), Ra = R11-8 - R15-12
- case 0x0a: // MRF = MRF + R3-0 * R7-4 (SSF), Ra = (R11-8 + R15-12) / 2
+ case 0x08: // MRF = MRF + R3-0 * R7-4 (SSF), Ra = R11-8 + R15-12
+ case 0x09: // MRF = MRF + R3-0 * R7-4 (SSF), Ra = R11-8 - R15-12
+ case 0x0a: // MRF = MRF + R3-0 * R7-4 (SSF), Ra = (R11-8 + R15-12) / 2
REG_USED(desc, fxm);
REG_USED(desc, fym);
REG_USED(desc, fxa);
@@ -1042,9 +1042,9 @@ bool sharc_frontend::describe_compute(opcode_desc &desc, UINT64 opcode)
MULT_FLAGS_MODIFIED(desc);
break;
- case 0x0c: // Rm = MRF + R3-0 * R7-4 (SSFR), Ra = R11-8 + R15-12
- case 0x0d: // Rm = MRF + R3-0 * R7-4 (SSFR), Ra = R11-8 - R15-12
- case 0x0e: // Rm = MRF + R3-0 * R7-4 (SSFR), Ra = (R11-8 + R15-12) / 2
+ case 0x0c: // Rm = MRF + R3-0 * R7-4 (SSFR), Ra = R11-8 + R15-12
+ case 0x0d: // Rm = MRF + R3-0 * R7-4 (SSFR), Ra = R11-8 - R15-12
+ case 0x0e: // Rm = MRF + R3-0 * R7-4 (SSFR), Ra = (R11-8 + R15-12) / 2
REG_USED(desc, fxm);
REG_USED(desc, fym);
REG_USED(desc, fxa);
@@ -1055,9 +1055,9 @@ bool sharc_frontend::describe_compute(opcode_desc &desc, UINT64 opcode)
MULT_FLAGS_MODIFIED(desc);
break;
- case 0x10: // MRF = MRF - R3-0 * R7-4 (SSF), Ra = R11-8 + R15-12
- case 0x11: // MRF = MRF - R3-0 * R7-4 (SSF), Ra = R11-8 - R15-12
- case 0x12: // MRF = MRF - R3-0 * R7-4 (SSF), Ra = (R11-8 + R15-12) / 2
+ case 0x10: // MRF = MRF - R3-0 * R7-4 (SSF), Ra = R11-8 + R15-12
+ case 0x11: // MRF = MRF - R3-0 * R7-4 (SSF), Ra = R11-8 - R15-12
+ case 0x12: // MRF = MRF - R3-0 * R7-4 (SSF), Ra = (R11-8 + R15-12) / 2
REG_USED(desc, fxm);
REG_USED(desc, fym);
REG_USED(desc, fxa);
@@ -1066,9 +1066,9 @@ bool sharc_frontend::describe_compute(opcode_desc &desc, UINT64 opcode)
MULT_FLAGS_MODIFIED(desc);
break;
- case 0x14: // Rm = MRF - R3-0 * R7-4 (SSFR), Ra = R11-8 + R15-12
- case 0x15: // Rm = MRF - R3-0 * R7-4 (SSFR), Ra = R11-8 - R15-12
- case 0x16: // Rm = MRF - R3-0 * R7-4 (SSFR), Ra = (R11-8 + R15-12) / 2
+ case 0x14: // Rm = MRF - R3-0 * R7-4 (SSFR), Ra = R11-8 + R15-12
+ case 0x15: // Rm = MRF - R3-0 * R7-4 (SSFR), Ra = R11-8 - R15-12
+ case 0x16: // Rm = MRF - R3-0 * R7-4 (SSFR), Ra = (R11-8 + R15-12) / 2
REG_USED(desc, fxm);
REG_USED(desc, fym);
REG_USED(desc, fxa);
@@ -1079,13 +1079,13 @@ bool sharc_frontend::describe_compute(opcode_desc &desc, UINT64 opcode)
MULT_FLAGS_MODIFIED(desc);
break;
- case 0x18: // Fm = F3-0 * F7-4, Fa = F11-8 + F15-12
- case 0x19: // Fm = F3-0 * F7-4, Fa = F11-8 - F15-12
- case 0x1a: // Fm = F3-0 * F7-4, Fa = FLOAT F11-8 BY R15-12
- case 0x1b: // Fm = F3-0 * F7-4, Fa = FIX F11-8 BY R15-12
- case 0x1c: // Fm = F3-0 * F7-4, Fa = (F11-8 + F15-12) / 2
- case 0x1e: // Fm = F3-0 * F7-4, Fa = MAX(F11-8, F15-12)
- case 0x1f: // Fm = F3-0 * F7-4, Fa = MIN(F11-8, F15-12)
+ case 0x18: // Fm = F3-0 * F7-4, Fa = F11-8 + F15-12
+ case 0x19: // Fm = F3-0 * F7-4, Fa = F11-8 - F15-12
+ case 0x1a: // Fm = F3-0 * F7-4, Fa = FLOAT F11-8 BY R15-12
+ case 0x1b: // Fm = F3-0 * F7-4, Fa = FIX F11-8 BY R15-12
+ case 0x1c: // Fm = F3-0 * F7-4, Fa = (F11-8 + F15-12) / 2
+ case 0x1e: // Fm = F3-0 * F7-4, Fa = MAX(F11-8, F15-12)
+ case 0x1f: // Fm = F3-0 * F7-4, Fa = MIN(F11-8, F15-12)
REG_USED(desc, fxm);
REG_USED(desc, fym);
REG_USED(desc, fxa);
@@ -1096,7 +1096,7 @@ bool sharc_frontend::describe_compute(opcode_desc &desc, UINT64 opcode)
MULT_FLAGS_MODIFIED(desc);
break;
- case 0x1d: // Fm = F3-0 * F7-4, Fa = ABS F11-8
+ case 0x1d: // Fm = F3-0 * F7-4, Fa = ABS F11-8
REG_USED(desc, fxm);
REG_USED(desc, fym);
REG_USED(desc, fxa);
@@ -1139,48 +1139,48 @@ bool sharc_frontend::describe_compute(opcode_desc &desc, UINT64 opcode)
return false;
}
}
- else // single-function operation
+ else // single-function operation
{
UINT32 operation = (opcode >> 12) & 0xff;
switch ((opcode >> 20) & 3)
{
- case 0: // ALU operations
+ case 0: // ALU operations
{
switch (operation)
{
- case 0x01: // Rn = Rx + Ry
- case 0x02: // Rn = Rx - Ry
- case 0x09: // Rn = (Rx + Ry) / 2
- case 0x40: // Rn = Rx AND Ry
- case 0x41: // Rn = Rx OR Ry
- case 0x42: // Rn = Rx XOR Ry
- case 0x61: // Rn = MIN(Rx, Ry)
- case 0x62: // Rn = MAX(Rx, Ry)
- case 0x63: // Rn = CLIP Rx BY Ry
- case 0x81: // Fn = Fx + Fy
- case 0x82: // Fn = Fx - Fy
- case 0x91: // Fn = ABS(Fx + Fy)
- case 0x92: // Fn = ABS(Fx - Fy)
- case 0x89: // Fn = (Fx + Fy) / 2
- case 0xbd: // Fn = SCALB Fx BY Ry
- case 0xd9: // Rn = FIX Fx BY Ry
- case 0xdd: // Rn = TRUNC Fx BY Ry
- case 0xda: // Fn = FLOAT Rx BY Ry
- case 0xe1: // Fn = MIN(Fx, Fy)
- case 0xe2: // Fn = MAX(Fx, Fy)
- case 0xe3: // Fn = CLIP Fx BY Fy
- case 0xe0: // Fn = Fx COPYSIGN Fy
+ case 0x01: // Rn = Rx + Ry
+ case 0x02: // Rn = Rx - Ry
+ case 0x09: // Rn = (Rx + Ry) / 2
+ case 0x40: // Rn = Rx AND Ry
+ case 0x41: // Rn = Rx OR Ry
+ case 0x42: // Rn = Rx XOR Ry
+ case 0x61: // Rn = MIN(Rx, Ry)
+ case 0x62: // Rn = MAX(Rx, Ry)
+ case 0x63: // Rn = CLIP Rx BY Ry
+ case 0x81: // Fn = Fx + Fy
+ case 0x82: // Fn = Fx - Fy
+ case 0x91: // Fn = ABS(Fx + Fy)
+ case 0x92: // Fn = ABS(Fx - Fy)
+ case 0x89: // Fn = (Fx + Fy) / 2
+ case 0xbd: // Fn = SCALB Fx BY Ry
+ case 0xd9: // Rn = FIX Fx BY Ry
+ case 0xdd: // Rn = TRUNC Fx BY Ry
+ case 0xda: // Fn = FLOAT Rx BY Ry
+ case 0xe1: // Fn = MIN(Fx, Fy)
+ case 0xe2: // Fn = MAX(Fx, Fy)
+ case 0xe3: // Fn = CLIP Fx BY Fy
+ case 0xe0: // Fn = Fx COPYSIGN Fy
REG_USED(desc, rx);
REG_USED(desc, ry);
REG_MODIFIED(desc, rn);
ALU_FLAGS_MODIFIED(desc);
break;
- case 0x05: // Rn = Rx + Ry + CI
- case 0x06: // Rn = Rx - Ry + CI - 1
- case 0x25: // Rn = Rx + CI
- case 0x26: // Rn = Rx + CI - 1
+ case 0x05: // Rn = Rx + Ry + CI
+ case 0x06: // Rn = Rx - Ry + CI - 1
+ case 0x25: // Rn = Rx + CI
+ case 0x26: // Rn = Rx + CI - 1
REG_USED(desc, rx);
REG_USED(desc, ry);
REG_MODIFIED(desc, rn);
@@ -1188,30 +1188,30 @@ bool sharc_frontend::describe_compute(opcode_desc &desc, UINT64 opcode)
ALU_FLAGS_MODIFIED(desc);
break;
- case 0x0a: // COMP(Rx, Ry)
- case 0x8a: // COMP(Fx, Fy)
+ case 0x0a: // COMP(Rx, Ry)
+ case 0x8a: // COMP(Fx, Fy)
REG_USED(desc, rx);
REG_USED(desc, ry);
ALU_FLAGS_MODIFIED(desc);
break;
- case 0x29: // Rn = Rx + 1
- case 0x2a: // Rn = Rx - 1
- case 0x22: // Rn = -Rx
- case 0x30: // Rn = ABS Rx
- case 0x21: // Rn = PASS Rx
- case 0x43: // Rn = NOT Rx
- case 0xb0: // Fn = ABS(Fx)
- case 0xa1: // Fn = PASS Fx
- case 0xa2: // Fn = -Fx
- case 0xa5: // Fn = RND Fx
- case 0xad: // Rn = MANT Fx
- case 0xc1: // Rn = LOGB Fx
- case 0xc9: // Rn = FIX Fx
- case 0xcd: // Rn = TRUNC Fx
- case 0xca: // Fn = FLOAT Rx
- case 0xc4: // Fn = RECIPS Fx
- case 0xc5: // Fn = RSQRTS Fx
+ case 0x29: // Rn = Rx + 1
+ case 0x2a: // Rn = Rx - 1
+ case 0x22: // Rn = -Rx
+ case 0x30: // Rn = ABS Rx
+ case 0x21: // Rn = PASS Rx
+ case 0x43: // Rn = NOT Rx
+ case 0xb0: // Fn = ABS(Fx)
+ case 0xa1: // Fn = PASS Fx
+ case 0xa2: // Fn = -Fx
+ case 0xa5: // Fn = RND Fx
+ case 0xad: // Rn = MANT Fx
+ case 0xc1: // Rn = LOGB Fx
+ case 0xc9: // Rn = FIX Fx
+ case 0xcd: // Rn = TRUNC Fx
+ case 0xca: // Fn = FLOAT Rx
+ case 0xc4: // Fn = RECIPS Fx
+ case 0xc5: // Fn = RSQRTS Fx
REG_USED(desc, rx);
REG_MODIFIED(desc, rn);
ALU_FLAGS_MODIFIED(desc);
@@ -1248,76 +1248,76 @@ bool sharc_frontend::describe_compute(opcode_desc &desc, UINT64 opcode)
break;
}
- case 1: // multiplier operations
+ case 1: // multiplier operations
{
switch (operation)
{
- case 0x40: // Rn = Rx * Ry (UUI)
- case 0x48: // Rn = Rx * Ry (UUF)
- case 0x49: // Rn = Rx * Ry (UUFR)
- case 0x50: // Rn = Rx * Ry (SUI)
- case 0x58: // Rn = Rx * Ry (SUF)
- case 0x59: // Rn = Rx * Ry (SUFR)
- case 0x60: // Rn = Rx * Ry (USI)
- case 0x68: // Rn = Rx * Ry (USF)
- case 0x69: // Rn = Rx * Ry (USFR)
- case 0x70: // Rn = Rx * Ry (SSI)
- case 0x78: // Rn = Rx * Ry (SSF)
- case 0x79: // Rn = Rx * Ry (SSFR)
+ case 0x40: // Rn = Rx * Ry (UUI)
+ case 0x48: // Rn = Rx * Ry (UUF)
+ case 0x49: // Rn = Rx * Ry (UUFR)
+ case 0x50: // Rn = Rx * Ry (SUI)
+ case 0x58: // Rn = Rx * Ry (SUF)
+ case 0x59: // Rn = Rx * Ry (SUFR)
+ case 0x60: // Rn = Rx * Ry (USI)
+ case 0x68: // Rn = Rx * Ry (USF)
+ case 0x69: // Rn = Rx * Ry (USFR)
+ case 0x70: // Rn = Rx * Ry (SSI)
+ case 0x78: // Rn = Rx * Ry (SSF)
+ case 0x79: // Rn = Rx * Ry (SSFR)
REG_USED(desc, rx);
REG_USED(desc, ry);
REG_MODIFIED(desc, rn);
MULT_FLAGS_MODIFIED(desc);
break;
- case 0x44: // MRF = Rx * Ry (UUI)
- case 0x4c: // MRF = Rx * Ry (UUF)
- case 0x4d: // MRF = Rx * Ry (UUFR)
- case 0x54: // MRF = Rx * Ry (SUI)
- case 0x5c: // MRF = Rx * Ry (SUF)
- case 0x5d: // MRF = Rx * Ry (SUFR)
- case 0x64: // MRF = Rx * Ry (USI)
- case 0x6c: // MRF = Rx * Ry (USF)
- case 0x6d: // MRF = Rx * Ry (USFR)
- case 0x74: // MRF = Rx * Ry (SSI)
- case 0x7c: // MRF = Rx * Ry (SSF)
- case 0x7d: // MRF = Rx * Ry (SSFR)
+ case 0x44: // MRF = Rx * Ry (UUI)
+ case 0x4c: // MRF = Rx * Ry (UUF)
+ case 0x4d: // MRF = Rx * Ry (UUFR)
+ case 0x54: // MRF = Rx * Ry (SUI)
+ case 0x5c: // MRF = Rx * Ry (SUF)
+ case 0x5d: // MRF = Rx * Ry (SUFR)
+ case 0x64: // MRF = Rx * Ry (USI)
+ case 0x6c: // MRF = Rx * Ry (USF)
+ case 0x6d: // MRF = Rx * Ry (USFR)
+ case 0x74: // MRF = Rx * Ry (SSI)
+ case 0x7c: // MRF = Rx * Ry (SSF)
+ case 0x7d: // MRF = Rx * Ry (SSFR)
// TODO: track MRF?
REG_USED(desc, rx);
REG_USED(desc, ry);
MULT_FLAGS_MODIFIED(desc);
break;
- case 0x46: // MRB = Rx * Ry (UUI)
- case 0x4e: // MRB = Rx * Ry (UUF)
- case 0x4f: // MRB = Rx * Ry (UUFR)
- case 0x56: // MRB = Rx * Ry (SUI)
- case 0x5e: // MRB = Rx * Ry (SUF)
- case 0x5f: // MRB = Rx * Ry (SUFR)
- case 0x66: // MRB = Rx * Ry (USI)
- case 0x6e: // MRB = Rx * Ry (USF)
- case 0x6f: // MRB = Rx * Ry (USFR)
- case 0x76: // MRB = Rx * Ry (SSI)
- case 0x7e: // MRB = Rx * Ry (SSF)
- case 0x7f: // MRB = Rx * Ry (SSFR)
+ case 0x46: // MRB = Rx * Ry (UUI)
+ case 0x4e: // MRB = Rx * Ry (UUF)
+ case 0x4f: // MRB = Rx * Ry (UUFR)
+ case 0x56: // MRB = Rx * Ry (SUI)
+ case 0x5e: // MRB = Rx * Ry (SUF)
+ case 0x5f: // MRB = Rx * Ry (SUFR)
+ case 0x66: // MRB = Rx * Ry (USI)
+ case 0x6e: // MRB = Rx * Ry (USF)
+ case 0x6f: // MRB = Rx * Ry (USFR)
+ case 0x76: // MRB = Rx * Ry (SSI)
+ case 0x7e: // MRB = Rx * Ry (SSF)
+ case 0x7f: // MRB = Rx * Ry (SSFR)
// TODO: track MRB?
REG_USED(desc, rx);
REG_USED(desc, ry);
MULT_FLAGS_MODIFIED(desc);
break;
- case 0x80: // Rn = MRF + Rx * Ry (UUI)
- case 0x88: // Rn = MRF + Rx * Ry (UUF)
- case 0x89: // Rn = MRF + Rx * Ry (UUFR)
- case 0x90: // Rn = MRF + Rx * Ry (SUI)
- case 0x98: // Rn = MRF + Rx * Ry (SUF)
- case 0x99: // Rn = MRF + Rx * Ry (SUFR)
- case 0xa0: // Rn = MRF + Rx * Ry (USI)
- case 0xa8: // Rn = MRF + Rx * Ry (USF)
- case 0xa9: // Rn = MRF + Rx * Ry (USFR)
- case 0xb0: // Rn = MRF + Rx * Ry (SSI)
- case 0xb8: // Rn = MRF + Rx * Ry (SSF)
- case 0xb9: // Rn = MRF + Rx * Ry (SSFR)
+ case 0x80: // Rn = MRF + Rx * Ry (UUI)
+ case 0x88: // Rn = MRF + Rx * Ry (UUF)
+ case 0x89: // Rn = MRF + Rx * Ry (UUFR)
+ case 0x90: // Rn = MRF + Rx * Ry (SUI)
+ case 0x98: // Rn = MRF + Rx * Ry (SUF)
+ case 0x99: // Rn = MRF + Rx * Ry (SUFR)
+ case 0xa0: // Rn = MRF + Rx * Ry (USI)
+ case 0xa8: // Rn = MRF + Rx * Ry (USF)
+ case 0xa9: // Rn = MRF + Rx * Ry (USFR)
+ case 0xb0: // Rn = MRF + Rx * Ry (SSI)
+ case 0xb8: // Rn = MRF + Rx * Ry (SSF)
+ case 0xb9: // Rn = MRF + Rx * Ry (SSFR)
// TODO: track MRF?
REG_USED(desc, rx);
REG_USED(desc, ry);
@@ -1325,18 +1325,18 @@ bool sharc_frontend::describe_compute(opcode_desc &desc, UINT64 opcode)
MULT_FLAGS_MODIFIED(desc);
break;
- case 0x82: // Rn = MRB + Rx * Ry (UUI)
- case 0x8a: // Rn = MRB + Rx * Ry (UUF)
- case 0x8b: // Rn = MRB + Rx * Ry (UUFR)
- case 0x92: // Rn = MRB + Rx * Ry (SUI)
- case 0x9a: // Rn = MRB + Rx * Ry (SUF)
- case 0x9b: // Rn = MRB + Rx * Ry (SUFR)
- case 0xa2: // Rn = MRB + Rx * Ry (USI)
- case 0xaa: // Rn = MRB + Rx * Ry (USF)
- case 0xab: // Rn = MRB + Rx * Ry (USFR)
- case 0xb2: // Rn = MRB + Rx * Ry (SSI)
- case 0xba: // Rn = MRB + Rx * Ry (SSF)
- case 0xbb: // Rn = MRB + Rx * Ry (SSFR)
+ case 0x82: // Rn = MRB + Rx * Ry (UUI)
+ case 0x8a: // Rn = MRB + Rx * Ry (UUF)
+ case 0x8b: // Rn = MRB + Rx * Ry (UUFR)
+ case 0x92: // Rn = MRB + Rx * Ry (SUI)
+ case 0x9a: // Rn = MRB + Rx * Ry (SUF)
+ case 0x9b: // Rn = MRB + Rx * Ry (SUFR)
+ case 0xa2: // Rn = MRB + Rx * Ry (USI)
+ case 0xaa: // Rn = MRB + Rx * Ry (USF)
+ case 0xab: // Rn = MRB + Rx * Ry (USFR)
+ case 0xb2: // Rn = MRB + Rx * Ry (SSI)
+ case 0xba: // Rn = MRB + Rx * Ry (SSF)
+ case 0xbb: // Rn = MRB + Rx * Ry (SSFR)
// TODO: track MRB?
REG_USED(desc, rx);
REG_USED(desc, ry);
@@ -1344,55 +1344,55 @@ bool sharc_frontend::describe_compute(opcode_desc &desc, UINT64 opcode)
MULT_FLAGS_MODIFIED(desc);
break;
- case 0x84: // MRF = MRF + Rx * Ry (UUI)
- case 0x8c: // MRF = MRF + Rx * Ry (UUF)
- case 0x8d: // MRF = MRF + Rx * Ry (UUFR)
- case 0x94: // MRF = MRF + Rx * Ry (SUI)
- case 0x9c: // MRF = MRF + Rx * Ry (SUF)
- case 0x9d: // MRF = MRF + Rx * Ry (SUFR)
- case 0xa4: // MRF = MRF + Rx * Ry (USI)
- case 0xac: // MRF = MRF + Rx * Ry (USF)
- case 0xad: // MRF = MRF + Rx * Ry (USFR)
- case 0xb4: // MRF = MRF + Rx * Ry (SSI)
- case 0xbc: // MRF = MRF + Rx * Ry (SSF)
- case 0xbd: // MRF = MRF + Rx * Ry (SSFR)
+ case 0x84: // MRF = MRF + Rx * Ry (UUI)
+ case 0x8c: // MRF = MRF + Rx * Ry (UUF)
+ case 0x8d: // MRF = MRF + Rx * Ry (UUFR)
+ case 0x94: // MRF = MRF + Rx * Ry (SUI)
+ case 0x9c: // MRF = MRF + Rx * Ry (SUF)
+ case 0x9d: // MRF = MRF + Rx * Ry (SUFR)
+ case 0xa4: // MRF = MRF + Rx * Ry (USI)
+ case 0xac: // MRF = MRF + Rx * Ry (USF)
+ case 0xad: // MRF = MRF + Rx * Ry (USFR)
+ case 0xb4: // MRF = MRF + Rx * Ry (SSI)
+ case 0xbc: // MRF = MRF + Rx * Ry (SSF)
+ case 0xbd: // MRF = MRF + Rx * Ry (SSFR)
// TODO: track MRF?
REG_USED(desc, rx);
REG_USED(desc, ry);
MULT_FLAGS_MODIFIED(desc);
break;
- case 0x86: // MRB = MRB + Rx * Ry (UUI)
- case 0x8e: // MRB = MRB + Rx * Ry (UUF)
- case 0x8f: // MRB = MRB + Rx * Ry (UUFR)
- case 0x96: // MRB = MRB + Rx * Ry (SUI)
- case 0x9e: // MRB = MRB + Rx * Ry (SUF)
- case 0x9f: // MRB = MRB + Rx * Ry (SUFR)
- case 0xa6: // MRB = MRB + Rx * Ry (USI)
- case 0xae: // MRB = MRB + Rx * Ry (USF)
- case 0xaf: // MRB = MRB + Rx * Ry (USFR)
- case 0xb6: // MRB = MRB + Rx * Ry (SSI)
- case 0xbe: // MRB = MRB + Rx * Ry (SSF)
- case 0xbf: // MRB = MRB + Rx * Ry (SSFR)
+ case 0x86: // MRB = MRB + Rx * Ry (UUI)
+ case 0x8e: // MRB = MRB + Rx * Ry (UUF)
+ case 0x8f: // MRB = MRB + Rx * Ry (UUFR)
+ case 0x96: // MRB = MRB + Rx * Ry (SUI)
+ case 0x9e: // MRB = MRB + Rx * Ry (SUF)
+ case 0x9f: // MRB = MRB + Rx * Ry (SUFR)
+ case 0xa6: // MRB = MRB + Rx * Ry (USI)
+ case 0xae: // MRB = MRB + Rx * Ry (USF)
+ case 0xaf: // MRB = MRB + Rx * Ry (USFR)
+ case 0xb6: // MRB = MRB + Rx * Ry (SSI)
+ case 0xbe: // MRB = MRB + Rx * Ry (SSF)
+ case 0xbf: // MRB = MRB + Rx * Ry (SSFR)
break;
// TODO: track MRB?
REG_USED(desc, rx);
REG_USED(desc, ry);
MULT_FLAGS_MODIFIED(desc);
break;
-
- case 0xc0: // Rn = MRF - Rx * Ry (UUI)
- case 0xc8: // Rn = MRF - Rx * Ry (UUF)
- case 0xc9: // Rn = MRF - Rx * Ry (UUFR)
- case 0xd0: // Rn = MRF - Rx * Ry (SUI)
- case 0xd8: // Rn = MRF - Rx * Ry (SUF)
- case 0xd9: // Rn = MRF - Rx * Ry (SUFR)
- case 0xe0: // Rn = MRF - Rx * Ry (USI)
- case 0xe8: // Rn = MRF - Rx * Ry (USF)
- case 0xe9: // Rn = MRF - Rx * Ry (USFR)
- case 0xf0: // Rn = MRF - Rx * Ry (SSI)
- case 0xf8: // Rn = MRF - Rx * Ry (SSF)
- case 0xf9: // Rn = MRF - Rx * Ry (SSFR)
+
+ case 0xc0: // Rn = MRF - Rx * Ry (UUI)
+ case 0xc8: // Rn = MRF - Rx * Ry (UUF)
+ case 0xc9: // Rn = MRF - Rx * Ry (UUFR)
+ case 0xd0: // Rn = MRF - Rx * Ry (SUI)
+ case 0xd8: // Rn = MRF - Rx * Ry (SUF)
+ case 0xd9: // Rn = MRF - Rx * Ry (SUFR)
+ case 0xe0: // Rn = MRF - Rx * Ry (USI)
+ case 0xe8: // Rn = MRF - Rx * Ry (USF)
+ case 0xe9: // Rn = MRF - Rx * Ry (USFR)
+ case 0xf0: // Rn = MRF - Rx * Ry (SSI)
+ case 0xf8: // Rn = MRF - Rx * Ry (SSF)
+ case 0xf9: // Rn = MRF - Rx * Ry (SSFR)
// TODO: track MRF?
REG_USED(desc, rx);
REG_USED(desc, ry);
@@ -1400,18 +1400,18 @@ bool sharc_frontend::describe_compute(opcode_desc &desc, UINT64 opcode)
MULT_FLAGS_MODIFIED(desc);
break;
- case 0xc2: // Rn = MRB - Rx * Ry (UUI)
- case 0xca: // Rn = MRB - Rx * Ry (UUF)
- case 0xcb: // Rn = MRB - Rx * Ry (UUFR)
- case 0xd2: // Rn = MRB - Rx * Ry (SUI)
- case 0xda: // Rn = MRB - Rx * Ry (SUF)
- case 0xdb: // Rn = MRB - Rx * Ry (SUFR)
- case 0xe2: // Rn = MRB - Rx * Ry (USI)
- case 0xea: // Rn = MRB - Rx * Ry (USF)
- case 0xeb: // Rn = MRB - Rx * Ry (USFR)
- case 0xf2: // Rn = MRB - Rx * Ry (SSI)
- case 0xfa: // Rn = MRB - Rx * Ry (SSF)
- case 0xfb: // Rn = MRB - Rx * Ry (SSFR)
+ case 0xc2: // Rn = MRB - Rx * Ry (UUI)
+ case 0xca: // Rn = MRB - Rx * Ry (UUF)
+ case 0xcb: // Rn = MRB - Rx * Ry (UUFR)
+ case 0xd2: // Rn = MRB - Rx * Ry (SUI)
+ case 0xda: // Rn = MRB - Rx * Ry (SUF)
+ case 0xdb: // Rn = MRB - Rx * Ry (SUFR)
+ case 0xe2: // Rn = MRB - Rx * Ry (USI)
+ case 0xea: // Rn = MRB - Rx * Ry (USF)
+ case 0xeb: // Rn = MRB - Rx * Ry (USFR)
+ case 0xf2: // Rn = MRB - Rx * Ry (SSI)
+ case 0xfa: // Rn = MRB - Rx * Ry (SSF)
+ case 0xfb: // Rn = MRB - Rx * Ry (SSFR)
// TODO: track MRB?
REG_USED(desc, rx);
REG_USED(desc, ry);
@@ -1419,106 +1419,106 @@ bool sharc_frontend::describe_compute(opcode_desc &desc, UINT64 opcode)
MULT_FLAGS_MODIFIED(desc);
break;
- case 0xc4: // MRF = MRF - Rx * Ry (UUI)
- case 0xcc: // MRF = MRF - Rx * Ry (UUF)
- case 0xcd: // MRF = MRF - Rx * Ry (UUFR)
- case 0xd4: // MRF = MRF - Rx * Ry (SUI)
- case 0xdc: // MRF = MRF - Rx * Ry (SUF)
- case 0xdd: // MRF = MRF - Rx * Ry (SUFR)
- case 0xe4: // MRF = MRF - Rx * Ry (USI)
- case 0xec: // MRF = MRF - Rx * Ry (USF)
- case 0xed: // MRF = MRF - Rx * Ry (USFR)
- case 0xf4: // MRF = MRF - Rx * Ry (SSI)
- case 0xfc: // MRF = MRF - Rx * Ry (SSF)
- case 0xfd: // MRF = MRF - Rx * Ry (SSFR)
+ case 0xc4: // MRF = MRF - Rx * Ry (UUI)
+ case 0xcc: // MRF = MRF - Rx * Ry (UUF)
+ case 0xcd: // MRF = MRF - Rx * Ry (UUFR)
+ case 0xd4: // MRF = MRF - Rx * Ry (SUI)
+ case 0xdc: // MRF = MRF - Rx * Ry (SUF)
+ case 0xdd: // MRF = MRF - Rx * Ry (SUFR)
+ case 0xe4: // MRF = MRF - Rx * Ry (USI)
+ case 0xec: // MRF = MRF - Rx * Ry (USF)
+ case 0xed: // MRF = MRF - Rx * Ry (USFR)
+ case 0xf4: // MRF = MRF - Rx * Ry (SSI)
+ case 0xfc: // MRF = MRF - Rx * Ry (SSF)
+ case 0xfd: // MRF = MRF - Rx * Ry (SSFR)
// TODO: track MRF?
REG_USED(desc, rx);
REG_USED(desc, ry);
MULT_FLAGS_MODIFIED(desc);
break;
- case 0xc6: // MRB = MRB - Rx * Ry (UUI)
- case 0xce: // MRB = MRB - Rx * Ry (UUF)
- case 0xcf: // MRB = MRB - Rx * Ry (UUFR)
- case 0xd6: // MRB = MRB - Rx * Ry (SUI)
- case 0xde: // MRB = MRB - Rx * Ry (SUF)
- case 0xdf: // MRB = MRB - Rx * Ry (SUFR)
- case 0xe6: // MRB = MRB - Rx * Ry (USI)
- case 0xee: // MRB = MRB - Rx * Ry (USF)
- case 0xef: // MRB = MRB - Rx * Ry (USFR)
- case 0xf6: // MRB = MRB - Rx * Ry (SSI)
- case 0xfe: // MRB = MRB - Rx * Ry (SSF)
- case 0xff: // MRB = MRB - Rx * Ry (SSFR)
+ case 0xc6: // MRB = MRB - Rx * Ry (UUI)
+ case 0xce: // MRB = MRB - Rx * Ry (UUF)
+ case 0xcf: // MRB = MRB - Rx * Ry (UUFR)
+ case 0xd6: // MRB = MRB - Rx * Ry (SUI)
+ case 0xde: // MRB = MRB - Rx * Ry (SUF)
+ case 0xdf: // MRB = MRB - Rx * Ry (SUFR)
+ case 0xe6: // MRB = MRB - Rx * Ry (USI)
+ case 0xee: // MRB = MRB - Rx * Ry (USF)
+ case 0xef: // MRB = MRB - Rx * Ry (USFR)
+ case 0xf6: // MRB = MRB - Rx * Ry (SSI)
+ case 0xfe: // MRB = MRB - Rx * Ry (SSF)
+ case 0xff: // MRB = MRB - Rx * Ry (SSFR)
// TODO: track MRB?
REG_USED(desc, rx);
REG_USED(desc, ry);
MULT_FLAGS_MODIFIED(desc);
break;
-
- case 0x00: // Rn = SAT MRF (UI)
- case 0x01: // Rn = SAT MRF (SI)
- case 0x08: // Rn = SAT MRF (UF)
- case 0x09: // Rn = SAT MRF (SF)
+
+ case 0x00: // Rn = SAT MRF (UI)
+ case 0x01: // Rn = SAT MRF (SI)
+ case 0x08: // Rn = SAT MRF (UF)
+ case 0x09: // Rn = SAT MRF (SF)
// TODO: track MRF?
REG_MODIFIED(desc, rn);
MULT_FLAGS_MODIFIED(desc);
break;
- case 0x02: // Rn = SAT MRB (UI)
- case 0x03: // Rn = SAT MRB (SI)
- case 0x0a: // Rn = SAT MRB (UF)
- case 0x0b: // Rn = SAT MRB (SF)
+ case 0x02: // Rn = SAT MRB (UI)
+ case 0x03: // Rn = SAT MRB (SI)
+ case 0x0a: // Rn = SAT MRB (UF)
+ case 0x0b: // Rn = SAT MRB (SF)
// TODO: track MRB?
REG_MODIFIED(desc, rn);
MULT_FLAGS_MODIFIED(desc);
break;
- case 0x04: // MRF = SAT MRF (UI)
- case 0x05: // MRF = SAT MRF (SI)
- case 0x0c: // MRF = SAT MRF (UF)
- case 0x0d: // MRF = SAT MRF (SF)
+ case 0x04: // MRF = SAT MRF (UI)
+ case 0x05: // MRF = SAT MRF (SI)
+ case 0x0c: // MRF = SAT MRF (UF)
+ case 0x0d: // MRF = SAT MRF (SF)
// TODO: track MRF?
MULT_FLAGS_MODIFIED(desc);
break;
- case 0x06: // MRB = SAT MRB (UI)
- case 0x07: // MRB = SAT MRB (SI)
- case 0x0e: // MRB = SAT MRB (UF)
- case 0x0f: // MRB = SAT MRB (SF)
+ case 0x06: // MRB = SAT MRB (UI)
+ case 0x07: // MRB = SAT MRB (SI)
+ case 0x0e: // MRB = SAT MRB (UF)
+ case 0x0f: // MRB = SAT MRB (SF)
// TODO: track MRB?
MULT_FLAGS_MODIFIED(desc);
break;
- case 0x18: // Rn = RND MRF (U)
- case 0x19: // Rn = RND MRF (S)
+ case 0x18: // Rn = RND MRF (U)
+ case 0x19: // Rn = RND MRF (S)
REG_MODIFIED(desc, rn);
MULT_FLAGS_MODIFIED(desc);
break;
- case 0x1a: // Rn = RND MRB (U)
- case 0x1b: // Rn = RND MRB (S)
+ case 0x1a: // Rn = RND MRB (U)
+ case 0x1b: // Rn = RND MRB (S)
REG_MODIFIED(desc, rn);
MULT_FLAGS_MODIFIED(desc);
break;
- case 0x1c: // MRF = RND MRF (U)
- case 0x1d: // MRF = RND MRF (S)
+ case 0x1c: // MRF = RND MRF (U)
+ case 0x1d: // MRF = RND MRF (S)
MULT_FLAGS_MODIFIED(desc);
break;
- case 0x1e: // MRB = RND MRB (U)
- case 0x1f: // MRB = RND MRB (S)
+ case 0x1e: // MRB = RND MRB (U)
+ case 0x1f: // MRB = RND MRB (S)
MULT_FLAGS_MODIFIED(desc);
break;
- case 0x14: // MRF = 0
+ case 0x14: // MRF = 0
MULT_FLAGS_MODIFIED(desc);
break;
- case 0x16: // MRB = 0
+ case 0x16: // MRB = 0
MULT_FLAGS_MODIFIED(desc);
break;
- case 0x30: // Fn = Fx * Fy
+ case 0x30: // Fn = Fx * Fy
REG_USED(desc, rx);
REG_USED(desc, ry);
REG_MODIFIED(desc, rn);
@@ -1531,48 +1531,48 @@ bool sharc_frontend::describe_compute(opcode_desc &desc, UINT64 opcode)
break;
}
- case 2: // shifter operations
+ case 2: // shifter operations
{
switch (operation)
{
- case 0x00: // Rn = LSHIFT Rx BY Ry | <data8>
- case 0x04: // Rn = ASHIFT Rx BY Ry | <data8>
- case 0x08: // Rn = ROT Rx BY Ry | <data8>
- case 0xc4: // Rn = BCLR Rx BY Ry | <data8>
- case 0xc0: // Rn = BSET Rx BY Ry | <data8>
- case 0x44: // Rn = FDEP Rx BY Ry | <bit6>:<len6>
- case 0x4c: // Rn = FDEP Rx BY Ry | <bit6>:<len6> (SE)
- case 0x40: // Rn = FEXT Rx BY Ry | <bit6>:<len6>
- case 0x48: // Rn = FEXT Rx BY Ry | <bit6>:<len6> (SE)
+ case 0x00: // Rn = LSHIFT Rx BY Ry | <data8>
+ case 0x04: // Rn = ASHIFT Rx BY Ry | <data8>
+ case 0x08: // Rn = ROT Rx BY Ry | <data8>
+ case 0xc4: // Rn = BCLR Rx BY Ry | <data8>
+ case 0xc0: // Rn = BSET Rx BY Ry | <data8>
+ case 0x44: // Rn = FDEP Rx BY Ry | <bit6>:<len6>
+ case 0x4c: // Rn = FDEP Rx BY Ry | <bit6>:<len6> (SE)
+ case 0x40: // Rn = FEXT Rx BY Ry | <bit6>:<len6>
+ case 0x48: // Rn = FEXT Rx BY Ry | <bit6>:<len6> (SE)
REG_USED(desc, rx);
REG_USED(desc, ry);
REG_MODIFIED(desc, rn);
SHIFT_FLAGS_MODIFIED(desc);
break;
- case 0x20: // Rn = Rn OR LSHIFT Rx BY Ry | <data8>
- case 0x24: // Rn = Rn OR ASHIFT Rx BY Ry | <data8>
- case 0x64: // Rn = Rn OR FDEP Rx BY Ry | <bit6>:<len6>
- case 0x6c: // Rn = Rn OR FDEP Rx BY Ry | <bit6>:<len6> (SE)
+ case 0x20: // Rn = Rn OR LSHIFT Rx BY Ry | <data8>
+ case 0x24: // Rn = Rn OR ASHIFT Rx BY Ry | <data8>
+ case 0x64: // Rn = Rn OR FDEP Rx BY Ry | <bit6>:<len6>
+ case 0x6c: // Rn = Rn OR FDEP Rx BY Ry | <bit6>:<len6> (SE)
REG_USED(desc, rx);
REG_USED(desc, ry);
REG_USED(desc, rn);
REG_MODIFIED(desc, rn);
SHIFT_FLAGS_MODIFIED(desc);
break;
-
- case 0xcc: // BTST Rx BY Ry | <data8>
+
+ case 0xcc: // BTST Rx BY Ry | <data8>
REG_USED(desc, rx);
REG_USED(desc, ry);
SHIFT_FLAGS_MODIFIED(desc);
break;
-
- case 0x80: // Rn = EXP Rx
- case 0x84: // Rn = EXP Rx (EX)
- case 0x88: // Rn = LEFTZ Rx
- case 0x8c: // Rn = LEFTO Rx
- case 0x90: // Rn = FPACK Fx
- case 0x94: // Fn = FUNPACK Rx
+
+ case 0x80: // Rn = EXP Rx
+ case 0x84: // Rn = EXP Rx (EX)
+ case 0x88: // Rn = LEFTZ Rx
+ case 0x8c: // Rn = LEFTO Rx
+ case 0x90: // Rn = FPACK Fx
+ case 0x94: // Fn = FUNPACK Rx
REG_USED(desc, rx);
REG_MODIFIED(desc, rn);
SHIFT_FLAGS_MODIFIED(desc);
@@ -1657,34 +1657,34 @@ bool sharc_frontend::describe_ureg_access(opcode_desc &desc, int reg, UREG_ACCES
PM_B_MODIFIED(desc, reg & 7);
break;
- case 0x60: // FADDR
+ case 0x60: // FADDR
break;
- case 0x61: // DADDR
+ case 0x61: // DADDR
break;
- case 0x63: // PC
+ case 0x63: // PC
break;
- case 0x64: // PCSTK
+ case 0x64: // PCSTK
break;
- case 0x65: // PCSTKP
+ case 0x65: // PCSTKP
break;
- case 0x66: // LADDR
+ case 0x66: // LADDR
break;
- case 0x67: // CURLCNTR
+ case 0x67: // CURLCNTR
break;
- case 0x68: // LCNTR
+ case 0x68: // LCNTR
break;
- case 0x70: // USTAT1
+ case 0x70: // USTAT1
break;
- case 0x71: // USTAT2
+ case 0x71: // USTAT2
break;
- case 0x79: // IRPTL
+ case 0x79: // IRPTL
break;
- case 0x7a: // MODE1
+ case 0x7a: // MODE1
break;
- case 0x7b: // MODE2
+ case 0x7b: // MODE2
break;
- case 0x7c: // ASTAT
+ case 0x7c: // ASTAT
if (access == UREG_READ)
{
AZ_USED(desc);
@@ -1713,17 +1713,17 @@ bool sharc_frontend::describe_ureg_access(opcode_desc &desc, int reg, UREG_ACCES
}
break;
- case 0x7d: // IMASK
+ case 0x7d: // IMASK
break;
- case 0x7e: // STKY
+ case 0x7e: // STKY
break;
- case 0x7f: // IMASKP
+ case 0x7f: // IMASKP
break;
- case 0xdb: // PX
+ case 0xdb: // PX
break;
- case 0xdc: // PX1
+ case 0xdc: // PX1
break;
- case 0xdd: // PX2
+ case 0xdd: // PX2
break;
default:
@@ -1738,31 +1738,31 @@ bool sharc_frontend::describe_shiftop_imm(opcode_desc &desc, int shiftop, int rn
{
switch (shiftop)
{
- case 0x00: // LSHIFT Rx BY <data8>
- case 0x01: // ASHIFT Rx BY <data8>
- case 0x02: // ROT Rx BY <data8>
- case 0x10: // FEXT Rx BY <data8>
- case 0x11: // FDEP Rx BY <data8>
- case 0x12: // FEXT Rx BY <bit6>:<len6> (SE)
- case 0x13: // FDEP Rx BY <bit6>:<len6> (SE)
- case 0x30: // BSET Rx BY <data8>
- case 0x31: // BCLR Rx By <data8>
- case 0x32: // BTGL Rx BY <data8>
+ case 0x00: // LSHIFT Rx BY <data8>
+ case 0x01: // ASHIFT Rx BY <data8>
+ case 0x02: // ROT Rx BY <data8>
+ case 0x10: // FEXT Rx BY <data8>
+ case 0x11: // FDEP Rx BY <data8>
+ case 0x12: // FEXT Rx BY <bit6>:<len6> (SE)
+ case 0x13: // FDEP Rx BY <bit6>:<len6> (SE)
+ case 0x30: // BSET Rx BY <data8>
+ case 0x31: // BCLR Rx By <data8>
+ case 0x32: // BTGL Rx BY <data8>
REG_USED(desc, rx);
REG_MODIFIED(desc, rn);
SHIFT_FLAGS_MODIFIED(desc);
break;
- case 0x08: // Rn = Rn OR LSHIFT Rx BY <data8>
- case 0x19: // Rn = Rn OR FDEP Rx BY <bit6>:<len6>
- case 0x1b: // Rn = Rn OR FDEP Rx BY <bit6>:<len6> (SE)
+ case 0x08: // Rn = Rn OR LSHIFT Rx BY <data8>
+ case 0x19: // Rn = Rn OR FDEP Rx BY <bit6>:<len6>
+ case 0x1b: // Rn = Rn OR FDEP Rx BY <bit6>:<len6> (SE)
REG_USED(desc, rx);
REG_USED(desc, rn);
REG_MODIFIED(desc, rn);
SHIFT_FLAGS_MODIFIED(desc);
break;
- case 0x33: // BTST Rx BY <data8>
+ case 0x33: // BTST Rx BY <data8>
REG_USED(desc, rx);
SHIFT_FLAGS_MODIFIED(desc);
break;
@@ -1800,4 +1800,4 @@ void sharc_frontend::describe_if_condition(opcode_desc &desc, int condition)
case 0x18: SZ_USED(desc); break; /* NOT SZ */
case 0x1d: BTF_USED(desc); break; /* NOT TF */
}
-} \ No newline at end of file
+}
diff --git a/src/devices/cpu/sparc/mb86901.cpp b/src/devices/cpu/sparc/mb86901.cpp
index 0a1bf03938b..2bf8e1ba284 100644
--- a/src/devices/cpu/sparc/mb86901.cpp
+++ b/src/devices/cpu/sparc/mb86901.cpp
@@ -10,8 +10,8 @@
//
// To-Do:
// - Ops: FBFcc, LDF, STF
-// - Test: SPARCv8 ops are untested
-// - Test: Traps are untested
+// - Test: SPARCv8 ops are untested
+// - Test: Traps are untested
// - FPU support
// - Coprocessor support
//
@@ -155,17 +155,17 @@ void mb86901_device::device_start()
#endif
// register our state for the debugger
- state_add(STATE_GENPC, "GENPC", m_pc).noshow();
- state_add(STATE_GENFLAGS, "GENFLAGS", m_psr).callimport().callexport().formatstr("%6s").noshow();
- state_add(SPARC_PC, "PC", m_pc).formatstr("%08X");
- state_add(SPARC_NPC, "nPC", m_npc).formatstr("%08X");
- state_add(SPARC_PSR, "PSR", m_psr).formatstr("%08X");
- state_add(SPARC_WIM, "WIM", m_wim).formatstr("%08X");
- state_add(SPARC_TBR, "TBR", m_tbr).formatstr("%08X");
- state_add(SPARC_Y, "Y", m_y).formatstr("%08X");
- state_add(SPARC_ANNUL, "ANNUL", m_annul).formatstr("%01d");
- state_add(SPARC_ICC, "icc", m_icc).formatstr("%4s");
- state_add(SPARC_CWP, "CWP", m_cwp).formatstr("%2d");
+ state_add(STATE_GENPC, "GENPC", m_pc).noshow();
+ state_add(STATE_GENFLAGS, "GENFLAGS", m_psr).callimport().callexport().formatstr("%6s").noshow();
+ state_add(SPARC_PC, "PC", m_pc).formatstr("%08X");
+ state_add(SPARC_NPC, "nPC", m_npc).formatstr("%08X");
+ state_add(SPARC_PSR, "PSR", m_psr).formatstr("%08X");
+ state_add(SPARC_WIM, "WIM", m_wim).formatstr("%08X");
+ state_add(SPARC_TBR, "TBR", m_tbr).formatstr("%08X");
+ state_add(SPARC_Y, "Y", m_y).formatstr("%08X");
+ state_add(SPARC_ANNUL, "ANNUL", m_annul).formatstr("%01d");
+ state_add(SPARC_ICC, "icc", m_icc).formatstr("%4s");
+ state_add(SPARC_CWP, "CWP", m_cwp).formatstr("%2d");
char regname[3] = "g0";
for (int i = 0; i < 8; i++)
{
@@ -192,12 +192,12 @@ void mb86901_device::device_start()
state_add(SPARC_I0 + i, regname, m_dbgregs[16+i]).formatstr("%08X");
}
- state_add(SPARC_EC, "EC", m_ec).formatstr("%1d");
- state_add(SPARC_EF, "EF", m_ef).formatstr("%1d");
- state_add(SPARC_ET, "ET", m_et).formatstr("%1d");
- state_add(SPARC_PIL, "PIL", m_pil).formatstr("%2d");
- state_add(SPARC_S, "S", m_s).formatstr("%1d");
- state_add(SPARC_PS, "PS", m_ps).formatstr("%1d");
+ state_add(SPARC_EC, "EC", m_ec).formatstr("%1d");
+ state_add(SPARC_EF, "EF", m_ef).formatstr("%1d");
+ state_add(SPARC_ET, "ET", m_et).formatstr("%1d");
+ state_add(SPARC_PIL, "PIL", m_pil).formatstr("%2d");
+ state_add(SPARC_S, "S", m_s).formatstr("%1d");
+ state_add(SPARC_PS, "PS", m_ps).formatstr("%1d");
char rname[5];
for (int i = 0; i < 120; i++)
@@ -415,13 +415,13 @@ void mb86901_device::state_string_export(const device_state_entry &entry, std::s
case SPARC_ICC:
str = string_format("%c%c%c%c", ICC_N_SET ? 'n' : ' ', ICC_Z_SET ? 'z' : ' ', ICC_V_SET ? 'v' : ' ', ICC_C_SET ? 'c' : ' ');
break;
- case SPARC_O0: case SPARC_O1: case SPARC_O2: case SPARC_O3: case SPARC_O4: case SPARC_O5: case SPARC_O6: case SPARC_O7:
+ case SPARC_O0: case SPARC_O1: case SPARC_O2: case SPARC_O3: case SPARC_O4: case SPARC_O5: case SPARC_O6: case SPARC_O7:
str = string_format("%08X", m_dbgregs[entry.index() - SPARC_O0]);
break;
- case SPARC_L0: case SPARC_L1: case SPARC_L2: case SPARC_L3: case SPARC_L4: case SPARC_L5: case SPARC_L6: case SPARC_L7:
+ case SPARC_L0: case SPARC_L1: case SPARC_L2: case SPARC_L3: case SPARC_L4: case SPARC_L5: case SPARC_L6: case SPARC_L7:
str = string_format("%08X", m_dbgregs[8 + (entry.index() - SPARC_L0)]);
break;
- case SPARC_I0: case SPARC_I1: case SPARC_I2: case SPARC_I3: case SPARC_I4: case SPARC_I5: case SPARC_I6: case SPARC_I7:
+ case SPARC_I0: case SPARC_I1: case SPARC_I2: case SPARC_I3: case SPARC_I4: case SPARC_I5: case SPARC_I6: case SPARC_I7:
str = string_format("%08X", m_dbgregs[16 + (entry.index() - SPARC_I0)]);
break;
}
@@ -524,21 +524,21 @@ void mb86901_device::execute_add(UINT32 op)
operand2 := if (i = 0) then r[rs2] else sign_extend(simm13);
if (ADD or ADDcc) then
- result <- r[rs1] + operand2;
+ result <- r[rs1] + operand2;
else if (ADDX or ADDXcc) then
- result <= r[rs1] + operand2 + C;
+ result <= r[rs1] + operand2 + C;
next;
if (rd != 0) then
- r[rd] <- result;
+ r[rd] <- result;
if (ADDcc or ADDXcc) then (
- N <- result<31>;
- Z <- if (result = 0) then 1 else 0;
- V <- (r[rs1]<31> and operand2<31> and (not result<31>)) or
- ((not r[rs1]<31>) and (not operand2<31>) and result<31>);
- C <- (r[rs1]<31> and operand2<31>) or
- ((not result<31>) and (r[rs1]<31> or operand2<31>))
+ N <- result<31>;
+ Z <- if (result = 0) then 1 else 0;
+ V <- (r[rs1]<31> and operand2<31> and (not result<31>)) or
+ ((not r[rs1]<31>) and (not operand2<31>) and result<31>);
+ C <- (r[rs1]<31> and operand2<31>) or
+ ((not result<31>) and (r[rs1]<31> or operand2<31>))
);
*/
UINT32 operand2 = USEIMM ? SIMM13 : RS2REG;
@@ -559,9 +559,9 @@ void mb86901_device::execute_add(UINT32 op)
PSR |= (BIT31(result)) ? PSR_N_MASK : 0;
PSR |= (result == 0) ? PSR_Z_MASK : 0;
PSR |= ((BIT31(RS1REG) && BIT31(operand2) && !BIT31(result)) ||
- (!BIT31(RS1REG) && !BIT31(operand2) && BIT31(result))) ? PSR_V_MASK : 0;
+ (!BIT31(RS1REG) && !BIT31(operand2) && BIT31(result))) ? PSR_V_MASK : 0;
PSR |= ((BIT31(RS1REG) && BIT31(operand2)) ||
- (!BIT31(result) && (BIT31(RS1REG) || BIT31(operand2)))) ? PSR_C_MASK : 0;
+ (!BIT31(result) && (BIT31(RS1REG) || BIT31(operand2)))) ? PSR_C_MASK : 0;
}
}
@@ -586,16 +586,16 @@ void mb86901_device::execute_taddcc(UINT32 op)
next;
if (TADDccTV and (temp_V = 1)) then (
- trap <- 1;
- tag_overflow <- 1
+ trap <- 1;
+ tag_overflow <- 1
) else (
- N <- result<31>;
- Z <- if (result = 0) then 1 else 0;
- V <- temp_V;
- C <- (r[rs1]<31> and operand2<31>) or
- ((not result<31>) and (r[rs1]<31> or operand2<31>));
- if (rd != 0) then
- r[rd] <- result;
+ N <- result<31>;
+ Z <- if (result = 0) then 1 else 0;
+ V <- temp_V;
+ C <- (r[rs1]<31> and operand2<31>) or
+ ((not result<31>) and (r[rs1]<31> or operand2<31>));
+ if (rd != 0) then
+ r[rd] <- result;
);
*/
UINT32 operand2 = USEIMM ? SIMM13 : RS2REG;
@@ -603,8 +603,8 @@ void mb86901_device::execute_taddcc(UINT32 op)
UINT32 result = RS1REG + operand2;
bool temp_v = (BIT31(RS1REG) && BIT31(operand2) && !BIT31(result)) ||
- (!BIT31(RS1REG) && !BIT31(operand2) && BIT31(result)) ||
- ((RS1REG & 3) != 0 || (RS1REG & 3) != 0) ? true : false;
+ (!BIT31(RS1REG) && !BIT31(operand2) && BIT31(result)) ||
+ ((RS1REG & 3) != 0 || (RS1REG & 3) != 0) ? true : false;
if (TADDCCTV && temp_v)
{
@@ -618,7 +618,7 @@ void mb86901_device::execute_taddcc(UINT32 op)
PSR |= (result == 0) ? PSR_Z_MASK : 0;
PSR |= temp_v ? PSR_V_MASK : 0;
PSR |= ((BIT31(RS1REG) && BIT31(operand2)) ||
- (!BIT31(result) && (BIT31(RS1REG) || BIT31(operand2)))) ? PSR_C_MASK : 0;
+ (!BIT31(result) && (BIT31(RS1REG) || BIT31(operand2)))) ? PSR_C_MASK : 0;
if (RD != 0)
RDREG = result;
@@ -638,21 +638,21 @@ void mb86901_device::execute_sub(UINT32 op)
operand2 := if (i = 0) then r[rs2] else sign_extend(simm13);
if (SUB or SUBcc) then
- result <- r[rs1] - operand2;
+ result <- r[rs1] - operand2;
else if (SUBX or SUBXcc) then
- result <= r[rs1] - operand2 - C;
+ result <= r[rs1] - operand2 - C;
next;
if (rd != 0) then
- r[rd] <- result;
+ r[rd] <- result;
if (SUBcc or SUBXcc) then (
- N <- result<31>;
- Z <- if (result = 0) then 1 else 0;
- V <- (r[rs1]<31> and (not operand2<31>) and (not result<31>)) or
- ((not r[rs1]<31>) and operand2<31> and result<31>);
- C <- ((not r[rs1]<31>) and operand2<31>) or
- (result<31> and ((not r[rs1]<31>) or operand2<31>))
+ N <- result<31>;
+ Z <- if (result = 0) then 1 else 0;
+ V <- (r[rs1]<31> and (not operand2<31>) and (not result<31>)) or
+ ((not r[rs1]<31>) and operand2<31> and result<31>);
+ C <- ((not r[rs1]<31>) and operand2<31>) or
+ (result<31> and ((not r[rs1]<31>) or operand2<31>))
);
*/
UINT32 operand2 = USEIMM ? SIMM13 : RS2REG;
@@ -672,9 +672,9 @@ void mb86901_device::execute_sub(UINT32 op)
PSR |= (BIT31(result)) ? PSR_N_MASK : 0;
PSR |= (result == 0) ? PSR_Z_MASK : 0;
PSR |= ((BIT31(RS1REG) && !BIT31(operand2) && !BIT31(result)) ||
- (!BIT31(RS1REG) && BIT31(operand2) && BIT31(result))) ? PSR_V_MASK : 0;
+ (!BIT31(RS1REG) && BIT31(operand2) && BIT31(result))) ? PSR_V_MASK : 0;
PSR |= ((!BIT31(RS1REG) && BIT31(operand2)) ||
- (BIT31(result) && (!BIT31(RS1REG) || BIT31(operand2)))) ? PSR_C_MASK : 0;
+ (BIT31(result) && (!BIT31(RS1REG) || BIT31(operand2)))) ? PSR_C_MASK : 0;
}
}
@@ -699,16 +699,16 @@ void mb86901_device::execute_tsubcc(UINT32 op)
next;
if (TSUBccTV and (temp_V = 1)) then (
- trap <- 1;
- tag_overflow <- 1
+ trap <- 1;
+ tag_overflow <- 1
) else (
- N <- result<31>;
- Z <- if (result = 0) then 1 else 0;
- V <- temp_V;
- C <- ((not r[rs1]<31>) and operand2<31>) or
- (result<31> and ((not r[rs1]<31>) or operand2<31>));
- if (rd != 0) then
- r[rd] <- result;
+ N <- result<31>;
+ Z <- if (result = 0) then 1 else 0;
+ V <- temp_V;
+ C <- ((not r[rs1]<31>) and operand2<31>) or
+ (result<31> and ((not r[rs1]<31>) or operand2<31>));
+ if (rd != 0) then
+ r[rd] <- result;
);
*/
@@ -717,8 +717,8 @@ void mb86901_device::execute_tsubcc(UINT32 op)
UINT32 result = RS1REG - operand2;
bool temp_v = (BIT31(RS1REG) && !BIT31(operand2) && !BIT31(result)) ||
- (!BIT31(RS1REG) && BIT31(operand2) && BIT31(result)) ||
- ((RS1REG & 3) != 0 || (RS1REG & 3) != 0) ? true : false;
+ (!BIT31(RS1REG) && BIT31(operand2) && BIT31(result)) ||
+ ((RS1REG & 3) != 0 || (RS1REG & 3) != 0) ? true : false;
if (TSUBCCTV && temp_v)
{
@@ -732,7 +732,7 @@ void mb86901_device::execute_tsubcc(UINT32 op)
PSR |= (result == 0) ? PSR_Z_MASK : 0;
PSR |= temp_v ? PSR_V_MASK : 0;
PSR |= ((!BIT31(RS1REG) && BIT31(operand2)) ||
- (BIT31(result) && (!BIT31(RS1REG) || BIT31(operand2)))) ? PSR_C_MASK : 0;
+ (BIT31(result) && (!BIT31(RS1REG) || BIT31(operand2)))) ? PSR_C_MASK : 0;
if (RD != 0)
RDREG = result;
@@ -762,10 +762,10 @@ void mb86901_device::execute_logical(UINT32 op)
if (rd != 0) then r[rd] <- result;
if (ANDcccc or ANDNcc or ORcc or ORNcc or XORcc or XNORcc) then (
- N <- result<31>;
- Z <- if (result = 0) then 1 else 0;
- V <- 0
- C <- 0
+ N <- result<31>;
+ Z <- if (result = 0) then 1 else 0;
+ V <- 0
+ C <- 0
);
*/
@@ -824,11 +824,11 @@ void mb86901_device::execute_shift(UINT32 op)
shift_count := if (i = 0) then r[rs2]<4:0> else shcnt;
if (SLL and (rd != 0) ) then
- r[rd] <- shift_left_logical(r[rs1], shift_count)
+ r[rd] <- shift_left_logical(r[rs1], shift_count)
else if (SRL and (rd != 0) ) then
- r[rd] <- shift_right_logical(r[rs1], shift_count)
+ r[rd] <- shift_right_logical(r[rs1], shift_count)
else if (SRA and (rd != 0) ) then
- r[rd] <- shift_right_arithmetic(r[rs1], shift_count)
+ r[rd] <- shift_right_arithmetic(r[rs1], shift_count)
*/
UINT32 shift_count = USEIMM ? (SIMM13 & 31) : (RS2REG & 31);
@@ -852,8 +852,8 @@ void mb86901_device::execute_mulscc(UINT32 op)
operand1 := (N xor V) [] (r[rs1]<31:1>);
operand2 := (
- if (Y<0> = 0) then 0
- else if (i = 0) then r[rs2] else sign_extend(simm13)
+ if (Y<0> = 0) then 0
+ else if (i = 0) then r[rs2] else sign_extend(simm13)
);
result <- operand1 + operand2;
@@ -861,7 +861,7 @@ void mb86901_device::execute_mulscc(UINT32 op)
next;
if (rd != 0) then (
- r[rd] <- result;
+ r[rd] <- result;
)
N <- result<31>;
Z <- if (result = 0) then 1 else 0;
@@ -884,9 +884,9 @@ void mb86901_device::execute_mulscc(UINT32 op)
PSR |= (BIT31(result)) ? PSR_N_MASK : 0;
PSR |= (result == 0) ? PSR_Z_MASK : 0;
PSR |= ((BIT31(operand1) && BIT31(operand2) && !BIT31(result)) ||
- (!BIT31(operand1) && !BIT31(operand2) && BIT31(result))) ? PSR_V_MASK : 0;
+ (!BIT31(operand1) && !BIT31(operand2) && BIT31(result))) ? PSR_V_MASK : 0;
PSR |= ((BIT31(operand1) && BIT31(operand2)) ||
- (!BIT31(result) && (BIT31(operand1) || BIT31(operand2)))) ? PSR_C_MASK : 0;
+ (!BIT31(result) && (BIT31(operand1) || BIT31(operand2)))) ? PSR_C_MASK : 0;
}
@@ -901,17 +901,17 @@ void mb86901_device::execute_rdsr(UINT32 op)
if ((RDPSR or RDWIM or RDBTR
or (RDASR and (privileged_ASR(rs1) = 1))) and (S = 0)) then (
- trap <- 1;
- privileged_instruction <- 1;
+ trap <- 1;
+ privileged_instruction <- 1;
else if (illegal_instruction_ASR(rs1) = 1) then (
- trap <- 1;
- illegal_instruction <- 1
+ trap <- 1;
+ illegal_instruction <- 1
else if (rd != 0) then (
- if (RDY) then r[rd] <- Y
- else if (RDASR) then r[rd] <- ASR[rs1]
- else if (RDPSR) then r[rd] <- PSR
- else if (RDWIM) then r[rd] <- WIM
- else if (RDTBR) then r[rd] <- TBR;
+ if (RDY) then r[rd] <- Y
+ else if (RDASR) then r[rd] <- ASR[rs1]
+ else if (RDPSR) then r[rd] <- PSR
+ else if (RDWIM) then r[rd] <- WIM
+ else if (RDTBR) then r[rd] <- TBR;
);
*/
@@ -957,41 +957,41 @@ void mb86901_device::execute_wrsr(UINT32 op)
result := r[rs1] xor operand2;
if (WRY) then (
- Y'''' <- result
+ Y'''' <- result
) else if (WRASR) then (
- if ( (privileged_ASR(rd) = 1) and (S = 0) ) then (
- trap <- 1;
- privileged_instruction <- 1
- ) else if (illegal_instruction_ASR(rd) = 1) then (
- trap <- 1;
- illegal_instruction <- 1
- ) else (
- ASR[rd]'''' <- result
- )
+ if ( (privileged_ASR(rd) = 1) and (S = 0) ) then (
+ trap <- 1;
+ privileged_instruction <- 1
+ ) else if (illegal_instruction_ASR(rd) = 1) then (
+ trap <- 1;
+ illegal_instruction <- 1
+ ) else (
+ ASR[rd]'''' <- result
+ )
) else if (WRPSR) then (
- if (S = 0) then (
- trap <- 1;
- privileged_instruction <- 1
- ) else if (result<4:0> >= NWINDOWS) then (
- trap <- 1;
- illegal_instruction <- 1
- ) else (
- PSR'''' <- result
- )
+ if (S = 0) then (
+ trap <- 1;
+ privileged_instruction <- 1
+ ) else if (result<4:0> >= NWINDOWS) then (
+ trap <- 1;
+ illegal_instruction <- 1
+ ) else (
+ PSR'''' <- result
+ )
) else if (WRWIM) then (
- if (S = 0) then (
- trap <- 1;
- privileged_instruction <- 1
- ) else (
- WIM'''' <- result
- )
+ if (S = 0) then (
+ trap <- 1;
+ privileged_instruction <- 1
+ ) else (
+ WIM'''' <- result
+ )
) else if (WRBTR) then (
- if (S = 0) then (
- trap <- 1;
- privileged_instruction <- 1
- ) else (
- WIM'''' <- result
- )
+ if (S = 0) then (
+ trap <- 1;
+ privileged_instruction <- 1
+ ) else (
+ WIM'''' <- result
+ )
);
*/
UINT32 operand2 = USEIMM ? SIMM13 : RS2REG;
@@ -1009,8 +1009,8 @@ void mb86901_device::execute_wrsr(UINT32 op)
m_trap = 1;
m_privileged_instruction = 1;
}
- else if (m_illegal_instruction_asr[RD])
- {
+ else if (m_illegal_instruction_asr[RD])
+ {
m_trap = 1;
m_illegal_instruction = 1;
}
@@ -1043,8 +1043,8 @@ void mb86901_device::execute_wrsr(UINT32 op)
m_trap = 1;
m_privileged_instruction = 1;
}
- else
- {
+ else
+ {
WIM = result & 0x7f;
}
}
@@ -1055,8 +1055,8 @@ void mb86901_device::execute_wrsr(UINT32 op)
m_trap = 1;
m_privileged_instruction = 1;
}
- else
- {
+ else
+ {
TBR = result & 0xfffff000;
}
}
@@ -1076,33 +1076,33 @@ void mb86901_device::execute_rett(UINT32 op)
address <- r[rs1] + (if (i = 0) then r[rs2] else sign_extend(simm13));
next;
if (ET = 1) then (
- trap <- 1;
- if (S = 0) then privileged_instruction <- 1
- else if (S != 0) then illegal_instruction <- 1
+ trap <- 1;
+ if (S = 0) then privileged_instruction <- 1
+ else if (S != 0) then illegal_instruction <- 1
) else if (S = 0) then (
- trap <- 1;
- privileged_instruction <- 1
- tt <- 00000011; { trap type for privileged_instruction }
- execute_mode <- 0;
- error_mode = 1
+ trap <- 1;
+ privileged_instruction <- 1
+ tt <- 00000011; { trap type for privileged_instruction }
+ execute_mode <- 0;
+ error_mode = 1
) else if ((WIM and (1 << new_cwp)) != 0) then (
- trap <- 1;
- window_underflow <- 1;
- tt <- 00000110; { trap type for window_underflow }
- execute_mode = 0;
- error_mode = 1
+ trap <- 1;
+ window_underflow <- 1;
+ tt <- 00000110; { trap type for window_underflow }
+ execute_mode = 0;
+ error_mode = 1
) else if (address<1:0> != 0) then (
- trap = 1;
- mem_address_not_aligned = 1;
- tt = 7; { trap type for mem_address_not_aligned }
- execute_mode = 0;
- error_mode = 1
+ trap = 1;
+ mem_address_not_aligned = 1;
+ tt = 7; { trap type for mem_address_not_aligned }
+ execute_mode = 0;
+ error_mode = 1
) else (
- ET <- 1;
- PC <- nPC;
- nPC <- address;
- CWP <- new_cwp;
- S <- PS
+ ET <- 1;
+ PC <- nPC;
+ nPC <- address;
+ CWP <- new_cwp;
+ S <- PS
)
*/
@@ -1166,29 +1166,29 @@ void mb86901_device::execute_saverestore(UINT32 op)
operand2 := if (i = 0) then r[rs2] else sign_extend(simm13);
if (SAVE) then (
- new_cwp <- (CWP - 1) modulo NWINDOWS;
- next;
- if ((WIM and (1 << new_cwp)) != 0) then (
- trap <- 1;
- window_overflow <- 1
- ) else (
- result <- r[rs1] + operand2; { operands from old window }
- CWP <- new_cwp
- )
+ new_cwp <- (CWP - 1) modulo NWINDOWS;
+ next;
+ if ((WIM and (1 << new_cwp)) != 0) then (
+ trap <- 1;
+ window_overflow <- 1
+ ) else (
+ result <- r[rs1] + operand2; { operands from old window }
+ CWP <- new_cwp
+ )
) else if (RESTORE) then (
- new_cwp <- (CWP + 1) modulo NWINDOWS;
- next;
- if ((WIM and (1 << new_cwp)) != 0) then (
- trap <- 1;
- window_overflow <- 1
- ) else (
- result <- r[rs1] + operand2; { operands from old window }
- CWP <- new_cwp
- )
+ new_cwp <- (CWP + 1) modulo NWINDOWS;
+ next;
+ if ((WIM and (1 << new_cwp)) != 0) then (
+ trap <- 1;
+ window_overflow <- 1
+ ) else (
+ result <- r[rs1] + operand2; { operands from old window }
+ CWP <- new_cwp
+ )
);
next;
if ((trap = 0) and (rd != 0)) then
- r[rd] <- result { destination in new window }
+ r[rd] <- result { destination in new window }
*/
UINT32 rs1 = RS1REG;
@@ -1243,12 +1243,12 @@ void mb86901_device::execute_jmpl(UINT32 op)
jump_address <- r[rs1] + (if (i = 0) then r[rs2] else sign_extend(simm13));
next;
if (jump_address<1:0> != 0) then (
- trap <- 1;
- mem_address_not_aligned <- 1
+ trap <- 1;
+ mem_address_not_aligned <- 1
) else (
- if (rd != 0) then r[rd] <- PC;
- PC <- nPC;
- nPC <- jump_address
+ if (rd != 0) then r[rd] <- PC;
+ PC <- nPC;
+ nPC <- jump_address
)
*/
@@ -1417,119 +1417,119 @@ void mb86901_device::execute_store(UINT32 op)
/* The SPARC Instruction Manual: Version 8, page 165, "Appendix C - ISP Descriptions - Store Instructions" (SPARCv8.pdf, pg. 162)
if ( (S = 0) and (STDA or STA or STHA or STBA or STDFQ or STDCQ) ) then (
- trap <- 1;
- privileged_instruction <- 1
+ trap <- 1;
+ privileged_instruction <- 1
) else if ((i = 1) and (STDA or STA or STHA or STBA)) then (
- trap <- 1;
- illegal_instruction <- 1
+ trap <- 1;
+ illegal_instruction <- 1
);
next;
if (trap = 0) then (
- if (STD or ST or STH or STB or STF or STDF or STFSR or STDFQ or STCSR or STC or STDC or STDCQ) then (
- address <- r[rs1] + (if (i = 0) then r[rs2] else sign_extend(simm13));
- addr_space <- (if (S = 0) then 10 else 11)
- ) else if (STDA or STA or STHA or STBA) then (
- address <- r[rs1] + r[rs2];
- addr_space <- asi
- );
- if ((STF or STDF or STFSR or STDFQ) and
- ((EF = 0) or (bp_FPU_present = 0)) ) then (
- trap <- 1;
- fp_disabled <- 1;
- );
- if ((STC or STDC or STCSR or STDCQ) and
- ((EC = 0) or (bp_CP_present = 0)) ) then (
- trap <- 1;
- cp_disabled <- 1;
- )
+ if (STD or ST or STH or STB or STF or STDF or STFSR or STDFQ or STCSR or STC or STDC or STDCQ) then (
+ address <- r[rs1] + (if (i = 0) then r[rs2] else sign_extend(simm13));
+ addr_space <- (if (S = 0) then 10 else 11)
+ ) else if (STDA or STA or STHA or STBA) then (
+ address <- r[rs1] + r[rs2];
+ addr_space <- asi
+ );
+ if ((STF or STDF or STFSR or STDFQ) and
+ ((EF = 0) or (bp_FPU_present = 0)) ) then (
+ trap <- 1;
+ fp_disabled <- 1;
+ );
+ if ((STC or STDC or STCSR or STDCQ) and
+ ((EC = 0) or (bp_CP_present = 0)) ) then (
+ trap <- 1;
+ cp_disabled <- 1;
+ )
);
next;
if (trap = 0) then (
- if ((STH or STHA) and (address<0> != 0)) then (
- trap <- 1;
- mem_address_not_aligned <- 1
- ) else if ((ST or STA or STF or STFSR or STC or STCSR) and (address<1:0> != 0)) then (
- trap <- 1;
- mem_address_not_aligned <- 1
- ) else if ((STD or STDA or STDF or STDFQ or STDC or STDCQ) and (address<2:0> != 0)) then (
- trap <- 1;
- mem_address_not_aligned <- 1
- ) else (
- if (STDFQ and ((implementation has no floating-point queue) or (FSR.qne = 0))) then (
- trap <- 1;
- fp_exception <- 1;
- ftt <- sequence_error;
- );
- if (STDCQ and ((implementation has no coprocessor queue)) then (
- trap <- 1;
- cp_exception <- 1;
- { possibly additional implementation-dependent actions }
- );
- if (STDF and (rd<0> != 0)) then (
- trap <- 1;
- fp_exception <- 1;
- ftt <- invalid_fp_register;
- )
- )
+ if ((STH or STHA) and (address<0> != 0)) then (
+ trap <- 1;
+ mem_address_not_aligned <- 1
+ ) else if ((ST or STA or STF or STFSR or STC or STCSR) and (address<1:0> != 0)) then (
+ trap <- 1;
+ mem_address_not_aligned <- 1
+ ) else if ((STD or STDA or STDF or STDFQ or STDC or STDCQ) and (address<2:0> != 0)) then (
+ trap <- 1;
+ mem_address_not_aligned <- 1
+ ) else (
+ if (STDFQ and ((implementation has no floating-point queue) or (FSR.qne = 0))) then (
+ trap <- 1;
+ fp_exception <- 1;
+ ftt <- sequence_error;
+ );
+ if (STDCQ and ((implementation has no coprocessor queue)) then (
+ trap <- 1;
+ cp_exception <- 1;
+ { possibly additional implementation-dependent actions }
+ );
+ if (STDF and (rd<0> != 0)) then (
+ trap <- 1;
+ fp_exception <- 1;
+ ftt <- invalid_fp_register;
+ )
+ )
);
next;
if (trap = 0) then (
- if (STF) then ( byte_mask <- 1111; data0 <- f[rd] )
- else if (STC) then ( byte_mask <- 1111; data0 <- implementation_dependent_value )
- else if (STDF) then ( byte_mask <- 1111; data0 <- f[rd & 0x1e] )
- else if (STDC) then ( byte_mask <- 1111; data0 <- implementation_dependent_value )
- else if (STD or STDA) then ( byte_mask <- 1111; data0 <- r[rd & 0x1e] )
- else if (STDFQ) then ( byte_mask <- 1111; data0 <- implementation_dependent_value )
- else if (STDCQ) then ( byte_mask <- 1111; data0 <- implementation_dependent_value )
- else if (STFSR) then (
- while ((FSR.qne = 1) and (trap = 0)) (
- // wait for pending floating-point instructions to complete
- )
- next;
- byte_mask <- 1111; data0 <- FSR
- ) else if (STCSR) then (
- { implementation-dependent actions }
- byte_mask <- 1111; data0 <- CSR
- ) else if (ST or STA) then ( byte_mask <- 1111; data0 = r[rd] )
- else if (STH or STHA) then (
- if (address<1:0> = 0) then (
- byte_mask <- 1100; data0 <- shift_left_logical(r[rd], 16) )
- else if (address<1:0> = 2) then (
- byte_mask <- 0011; data0 <- r[rd] )
- ) else if (STB or STBA) then (
- if (address<1:0> = 0) then (
- byte_mask <- 1000; data0 <- shift_left_logical(r[rd], 24) )
- ) else if (address<1:0> = 1) then (
- byte_mask <- 0100; data0 <- shift_left_logical(r[rd], 16) )
- ) else if (address<1:0> = 2) then (
- byte_mask <- 0010; data0 <- shift_left_logical(r[rd], 8) )
- ) else if (address<1:0> = 3) then (
- byte_mask <- 0001; data0 <- r[rd] )
- )
- );
+ if (STF) then ( byte_mask <- 1111; data0 <- f[rd] )
+ else if (STC) then ( byte_mask <- 1111; data0 <- implementation_dependent_value )
+ else if (STDF) then ( byte_mask <- 1111; data0 <- f[rd & 0x1e] )
+ else if (STDC) then ( byte_mask <- 1111; data0 <- implementation_dependent_value )
+ else if (STD or STDA) then ( byte_mask <- 1111; data0 <- r[rd & 0x1e] )
+ else if (STDFQ) then ( byte_mask <- 1111; data0 <- implementation_dependent_value )
+ else if (STDCQ) then ( byte_mask <- 1111; data0 <- implementation_dependent_value )
+ else if (STFSR) then (
+ while ((FSR.qne = 1) and (trap = 0)) (
+ // wait for pending floating-point instructions to complete
+ )
+ next;
+ byte_mask <- 1111; data0 <- FSR
+ ) else if (STCSR) then (
+ { implementation-dependent actions }
+ byte_mask <- 1111; data0 <- CSR
+ ) else if (ST or STA) then ( byte_mask <- 1111; data0 = r[rd] )
+ else if (STH or STHA) then (
+ if (address<1:0> = 0) then (
+ byte_mask <- 1100; data0 <- shift_left_logical(r[rd], 16) )
+ else if (address<1:0> = 2) then (
+ byte_mask <- 0011; data0 <- r[rd] )
+ ) else if (STB or STBA) then (
+ if (address<1:0> = 0) then (
+ byte_mask <- 1000; data0 <- shift_left_logical(r[rd], 24) )
+ ) else if (address<1:0> = 1) then (
+ byte_mask <- 0100; data0 <- shift_left_logical(r[rd], 16) )
+ ) else if (address<1:0> = 2) then (
+ byte_mask <- 0010; data0 <- shift_left_logical(r[rd], 8) )
+ ) else if (address<1:0> = 3) then (
+ byte_mask <- 0001; data0 <- r[rd] )
+ )
+ );
);
next;
if (trap = 0) then (
- MAE <- memory_write(addr_space, address, byte_mask, data1);
- next;
- if (MAE = 1) then (
- trap <- 1;
- data_access_exception <- 1
- )
+ MAE <- memory_write(addr_space, address, byte_mask, data1);
+ next;
+ if (MAE = 1) then (
+ trap <- 1;
+ data_access_exception <- 1
+ )
);
if ((trap = 0) and (STD or STDA or STDF or STDC or STDFQ or STDCQ)) then (
- if (STD or STDA) then ( data1 <- r[rd or 00001] )
- else if (STDF) then ( data1 <- f[rd or 00001] )
- else if (STDC) then ( data1 <- implementation_dependent_value }
- else if (STDFQ) then ( data1 <- implementation_dependent_value }
- else if (STDCQ) then ( data1 <- implementation_dependent_value }
- next;
- MAE <- memory_write(addr_space, address + 4, 1111, data1);
- next;
- if (MAE = 1) then ( { MAE = 1 only due to a "non-resumable machine-check error" }
- trap <- 1;
- data_access_exception <- 1
- )
+ if (STD or STDA) then ( data1 <- r[rd or 00001] )
+ else if (STDF) then ( data1 <- f[rd or 00001] )
+ else if (STDC) then ( data1 <- implementation_dependent_value }
+ else if (STDFQ) then ( data1 <- implementation_dependent_value }
+ else if (STDCQ) then ( data1 <- implementation_dependent_value }
+ next;
+ MAE <- memory_write(addr_space, address + 4, 1111, data1);
+ next;
+ if (MAE = 1) then ( { MAE = 1 only due to a "non-resumable machine-check error" }
+ trap <- 1;
+ data_access_exception <- 1
+ )
);
*/
@@ -1760,100 +1760,100 @@ void mb86901_device::execute_load(UINT32 op)
/* The SPARC Instruction Manual: Version 8, page 163, "Appendix C - ISP Descriptions - C.9. Instruction Defintions - Load Instructions" (SPARCv8.pdf, pg. 160)
if (LDD or LD or LDSH or LDUH or LDSB or LDUB or LDDF or LDF or LDFSR or LDDC or LDC or LDCSR) then (
- address <- r[rs1] + (if (i = 0) then r[rs2] else sign_extend(simm13));
- addr_space <- (if (S = 0) then 10 else 11)
+ address <- r[rs1] + (if (i = 0) then r[rs2] else sign_extend(simm13));
+ addr_space <- (if (S = 0) then 10 else 11)
) else if (LDDA or LDA or LDSHA or LDUHA or LDSBA or LDUBA) then (
- if (S = 0) then (
- trap <- 1;
- privileged_instruction <- 1
- ) else if (i = 1) then (
- trap <- 1;
- illegal_instruction <- 1
- ) else (
- address <- r[rs1] + r[rs2];
- addr_space <- asi
- )
+ if (S = 0) then (
+ trap <- 1;
+ privileged_instruction <- 1
+ ) else if (i = 1) then (
+ trap <- 1;
+ illegal_instruction <- 1
+ ) else (
+ address <- r[rs1] + r[rs2];
+ addr_space <- asi
+ )
)
next;
if (trap = 0) then (
- if ( (LDF or LDDF or LDFSR) and ((EF = 0) or (bp_FPU_present = 0)) then (
- trap <- 1;
- fp_disabled <- 1
- ) else if ( (LDC or LDDC or LDCSR) and ((EC = 0) or (bp_CP_present = 0)) then (
- trap <- 1;
- cp_disabled <- 1
- ) else if ( ( (LDD or LDDA or LDDF or LDDC) and (address<2:0> != 0)) or
- ((LD or LDA or LDF or LDFSR or LDC or LDCSR) and (address<1:0> != 0)) or
- ((LDSH or LDSHA or LDUH or LDUHA) and address<0> != 0) ) then (
- trap <- 1;
- mem_address_not_aligned <- 1
- ) else if (LDDF and (rd<0> != 0)) then (
- trap <- 1;
- fp_exception <- 1;
- ftt <- invalid_fpr_register
- ) else if ((LDF or LDDF or LDFSR) and (an FPU sequence error is detected)) then (
- trap <- 1;
- fp_exception <- 1;
- ftt <- sequence_error
- ) else if ((LDC or LDDC or LDCSR) and (a CP sequence error is detected)) then (
- trap <- 1;
- cp_exception <- 1;
- { possibly additional implementation-dependent actions }
- )
+ if ( (LDF or LDDF or LDFSR) and ((EF = 0) or (bp_FPU_present = 0)) then (
+ trap <- 1;
+ fp_disabled <- 1
+ ) else if ( (LDC or LDDC or LDCSR) and ((EC = 0) or (bp_CP_present = 0)) then (
+ trap <- 1;
+ cp_disabled <- 1
+ ) else if ( ( (LDD or LDDA or LDDF or LDDC) and (address<2:0> != 0)) or
+ ((LD or LDA or LDF or LDFSR or LDC or LDCSR) and (address<1:0> != 0)) or
+ ((LDSH or LDSHA or LDUH or LDUHA) and address<0> != 0) ) then (
+ trap <- 1;
+ mem_address_not_aligned <- 1
+ ) else if (LDDF and (rd<0> != 0)) then (
+ trap <- 1;
+ fp_exception <- 1;
+ ftt <- invalid_fpr_register
+ ) else if ((LDF or LDDF or LDFSR) and (an FPU sequence error is detected)) then (
+ trap <- 1;
+ fp_exception <- 1;
+ ftt <- sequence_error
+ ) else if ((LDC or LDDC or LDCSR) and (a CP sequence error is detected)) then (
+ trap <- 1;
+ cp_exception <- 1;
+ { possibly additional implementation-dependent actions }
+ )
);
next;
if (trap = 0) then {
- (data, MAE) <- memory_read(addr_space, address);
- next;
- if (MAE = 1) then (
- trap <- 1;
- data_access_exception <- 1;
- ) else (
- if (LDSB or LDSBA or LDUB or LDUBA) then (
- if (address<1:0> = 0) then byte <- data<31:24>
- else if (address<1:0> = 1) then byte <- data<23:16>
- else if (address<1:0> = 2) then byte <- data<15: 8>
- else if (address<1:0> = 3) then byte <- data< 7: 0>
- next;
- if (LDSB or LDSBA) then
- word0 <- sign_extend_byte(byte)
- else
- word0 <- zero_extend_byte(byte)
- ) else if (LDSH or LDSHA or LDUH or LDUHA) then (
- if (address<1:0> = 0) then halfword <- data<31:16>
- else if (address<1:0> = 2) then halfword <- data<15: 0>
- next;
- if (LDSH or LDSHA) then
- word0 <- sign_extend_halfword(halfword)
- else
- word0 <- zero_extend_halfword(halfword)
- ) else
- word0 <- data
- )
+ (data, MAE) <- memory_read(addr_space, address);
+ next;
+ if (MAE = 1) then (
+ trap <- 1;
+ data_access_exception <- 1;
+ ) else (
+ if (LDSB or LDSBA or LDUB or LDUBA) then (
+ if (address<1:0> = 0) then byte <- data<31:24>
+ else if (address<1:0> = 1) then byte <- data<23:16>
+ else if (address<1:0> = 2) then byte <- data<15: 8>
+ else if (address<1:0> = 3) then byte <- data< 7: 0>
+ next;
+ if (LDSB or LDSBA) then
+ word0 <- sign_extend_byte(byte)
+ else
+ word0 <- zero_extend_byte(byte)
+ ) else if (LDSH or LDSHA or LDUH or LDUHA) then (
+ if (address<1:0> = 0) then halfword <- data<31:16>
+ else if (address<1:0> = 2) then halfword <- data<15: 0>
+ next;
+ if (LDSH or LDSHA) then
+ word0 <- sign_extend_halfword(halfword)
+ else
+ word0 <- zero_extend_halfword(halfword)
+ ) else
+ word0 <- data
+ )
);
next;
if (trap = 0) then (
- if ( (rd != 0) and (LD or LDA or LDSH or LDSHA
- or LDUHA or LDUH or LDSB or LDSBA or LDUB or LDUBA) ) then
- r[rd] <- word0
- else if (LDF) then f[rd] <- word0
- else if (LDC) then { implementation-dependent actions }
- else if (LDFSR) then FSR <- word0
- else if (LDCSR) then CSR <- word0
- else if (LDD or LDDA) then r[rd and 11110] <- word0
- else if (LDDF) then f[rd and 11110] <- word0
- else if (LDDC) then { implementation-dependent actions }
+ if ( (rd != 0) and (LD or LDA or LDSH or LDSHA
+ or LDUHA or LDUH or LDSB or LDSBA or LDUB or LDUBA) ) then
+ r[rd] <- word0
+ else if (LDF) then f[rd] <- word0
+ else if (LDC) then { implementation-dependent actions }
+ else if (LDFSR) then FSR <- word0
+ else if (LDCSR) then CSR <- word0
+ else if (LDD or LDDA) then r[rd and 11110] <- word0
+ else if (LDDF) then f[rd and 11110] <- word0
+ else if (LDDC) then { implementation-dependent actions }
);
next;
if (((trap = 0) and (LDD or LDDA or LDDF or LDDC)) then (
- (word1, MAE) <- memory_read(addr_space, address + 4);
- next;
- if (MAE = 1) then ( { MAE = 1 only due to a "non-resumable machine-check error" }
- trap <- 1;
- data_access_exception <- 1 )
- else if (LDD or LDDA) then r[rd or 1] <- word1
- else if (LDDF) then f[rd or 1] <- word1
- else if (LDDC) then { implementation-dependent actions }
+ (word1, MAE) <- memory_read(addr_space, address + 4);
+ next;
+ if (MAE = 1) then ( { MAE = 1 only due to a "non-resumable machine-check error" }
+ trap <- 1;
+ data_access_exception <- 1 )
+ else if (LDD or LDDA) then r[rd or 1] <- word1
+ else if (LDDF) then f[rd or 1] <- word1
+ else if (LDDC) then { implementation-dependent actions }
);
*/
@@ -2008,59 +2008,59 @@ void mb86901_device::execute_ldstub(UINT32 op)
/* The SPARC Instruction Manual: Version 8, page 169, "Appendix C - ISP Descriptions - Atomic Load-Store Unsigned Byte Instructions" (SPARCv8.pdf, pg. 166)
if (LDSTUB) then (
- address <- r[rs1] + (if (i = 0) then r[rs2] else sign_extend(simm13));
- addr_space <- (if (S = 0) then 10 else 11)
+ address <- r[rs1] + (if (i = 0) then r[rs2] else sign_extend(simm13));
+ addr_space <- (if (S = 0) then 10 else 11)
} else if (LDSTUBA) then (
- if (S = 0) then (
- trap <- 1;
- privileged_instruction <- 1
- ) else if (i = 1) then (
- trap <- 1;
- illegal_instruction <- 1
- ) else (
- address <- r[rs1] + r[rs2];
- addr_space <- asi
- )
+ if (S = 0) then (
+ trap <- 1;
+ privileged_instruction <- 1
+ ) else if (i = 1) then (
+ trap <- 1;
+ illegal_instruction <- 1
+ ) else (
+ address <- r[rs1] + r[rs2];
+ addr_space <- asi
+ )
);
next;
if (trap = 0) then (
- while ( (pb_block_ldst_byte = 1) or (pb_block_ldst_word = 1) ) then (
- { wait for lock(s) to be lifted }
- { an implementation actually need only block when another LDSTUB or SWAP
- is pending on the same byte in memory as the one addressed by this LDSTUB }
- };
- next;
- pb_block_ldst_byte <- 1;
- next;
- (data, MAE) <- memory_read(addr_space, address);
- next;
- if (MAE = 1) then (
- trap <- 1;
- data_access_exception <- 1
- )
+ while ( (pb_block_ldst_byte = 1) or (pb_block_ldst_word = 1) ) then (
+ { wait for lock(s) to be lifted }
+ { an implementation actually need only block when another LDSTUB or SWAP
+ is pending on the same byte in memory as the one addressed by this LDSTUB }
+ };
+ next;
+ pb_block_ldst_byte <- 1;
+ next;
+ (data, MAE) <- memory_read(addr_space, address);
+ next;
+ if (MAE = 1) then (
+ trap <- 1;
+ data_access_exception <- 1
+ )
)
next;
if (trap = 0) then (
- if (address<1:0> = 0) then ( byte_mask <- 1000 )
- else if (address<1:0> = 1) then ( byte_mask <- 0100 )
- else if (address<1:0> = 2) then ( byte_mask <- 0010 )
- else if (address<1:0> = 3) then ( byte_mask <- 0001 )
- ;
- next;
- MAE <- memory_write(addr_space, address, byte_mask, FFFFFFFF);
- next;
- pb_block_ldst_byte <- 0;
- if (MAE = 1) then ( { MAE = 1 only due to a "non-resumable machine-check error" }
- trap <- 1;
- data_access_exception <- 1
- ) else (
- if (address<1:0> = 0) then word <- zero_extend_byte(data<31:24>)
- else if (address<1:0> = 1) then word <- zero_extend_byte(data<23:24>)
- else if (address<1:0> = 2) then word <- zero_extend_byte(data<15: 8>)
- else if (address<1:0> = 3) then word <- zero_extend_byte(data< 7: 0>)
- next;
- if (rd != 0) then r[rd] <- word
- )
+ if (address<1:0> = 0) then ( byte_mask <- 1000 )
+ else if (address<1:0> = 1) then ( byte_mask <- 0100 )
+ else if (address<1:0> = 2) then ( byte_mask <- 0010 )
+ else if (address<1:0> = 3) then ( byte_mask <- 0001 )
+ ;
+ next;
+ MAE <- memory_write(addr_space, address, byte_mask, FFFFFFFF);
+ next;
+ pb_block_ldst_byte <- 0;
+ if (MAE = 1) then ( { MAE = 1 only due to a "non-resumable machine-check error" }
+ trap <- 1;
+ data_access_exception <- 1
+ ) else (
+ if (address<1:0> = 0) then word <- zero_extend_byte(data<31:24>)
+ else if (address<1:0> = 1) then word <- zero_extend_byte(data<23:24>)
+ else if (address<1:0> = 2) then word <- zero_extend_byte(data<15: 8>)
+ else if (address<1:0> = 3) then word <- zero_extend_byte(data< 7: 0>)
+ next;
+ if (rd != 0) then r[rd] <- word
+ )
);
*/
@@ -2258,16 +2258,16 @@ bool mb86901_device::evaluate_condition(UINT32 op)
bool v = ICC_V_SET;
bool c = ICC_C_SET;
- switch(COND & 7) // COND & 8
- { // 0 8
- case 0: take = false; break; // bn ba
- case 1: take = z; break; // bz bne
- case 2: take = z | (n ^ z); break; // ble bg
- case 3: take = n ^ v; break; // bl bge
- case 4: take = c | z; break; // bleu bgu
- case 5: take = c; break; // bcs bcc
- case 6: take = n; break; // bneg bpos
- case 7: take = v; break; // bvs bvc
+ switch(COND & 7) // COND & 8
+ { // 0 8
+ case 0: take = false; break; // bn ba
+ case 1: take = z; break; // bz bne
+ case 2: take = z | (n ^ z); break; // ble bg
+ case 3: take = n ^ v; break; // bl bge
+ case 4: take = c | z; break; // bleu bgu
+ case 5: take = c; break; // bcs bcc
+ case 6: take = n; break; // bneg bpos
+ case 7: take = v; break; // bvs bvc
}
if (COND & 8)
@@ -2286,32 +2286,32 @@ void mb86901_device::execute_bicc(UINT32 op)
/* The SPARC Instruction Manual: Version 8, page 178, "Appendix C - ISP Descriptions - Branch on Integer Condition Instructions" (SPARCv8.pdf, pg. 175)
eval_icc := (
- if (BNE) then (if (Z = 0) then 1 else 0);
- if (BE) then (if (Z = 1) then 1 else 0);
- if (BG) then (if ((Z or (N xor V)) = 0) then 1 else 0);
- if (BLE) then (if ((Z or (N xor V)) = 1) then 1 else 0);
- if (BGE) then (if ((N xor V) = 0) then 1 else 0);
- if (BL) then (if ((N xor V) = 1) then 1 else 0);
- if (BGU) then (if ((C = 0) and (Z = 0)) then 1 else 0);
- if (BLEU) then (if ((C = 1) or (Z = 1)) then 1 else 0);
- if (BCC) then (if (C = 0) then 1 else 0);
- if (BCS) then (if (C = 1) then 1 else 0);
- if (BPOS) then (if (N = 0) then 1 else 0);
- if (BNEG) then (if (N = 1) then 1 else 0);
- if (BVC) then (if (V = 0) then 1 else 0);
- if (BVS) then (if (V = 1) then 1 else 0);
- if (BA) then 1;
- if (BN) then 0;
+ if (BNE) then (if (Z = 0) then 1 else 0);
+ if (BE) then (if (Z = 1) then 1 else 0);
+ if (BG) then (if ((Z or (N xor V)) = 0) then 1 else 0);
+ if (BLE) then (if ((Z or (N xor V)) = 1) then 1 else 0);
+ if (BGE) then (if ((N xor V) = 0) then 1 else 0);
+ if (BL) then (if ((N xor V) = 1) then 1 else 0);
+ if (BGU) then (if ((C = 0) and (Z = 0)) then 1 else 0);
+ if (BLEU) then (if ((C = 1) or (Z = 1)) then 1 else 0);
+ if (BCC) then (if (C = 0) then 1 else 0);
+ if (BCS) then (if (C = 1) then 1 else 0);
+ if (BPOS) then (if (N = 0) then 1 else 0);
+ if (BNEG) then (if (N = 1) then 1 else 0);
+ if (BVC) then (if (V = 0) then 1 else 0);
+ if (BVS) then (if (V = 1) then 1 else 0);
+ if (BA) then 1;
+ if (BN) then 0;
)
PC <- nPC;
if (eval_icc = 1) then (
- nPC <- PC + sign_extend(disp22[]00);
- if (BA and (a = 1)) then
- annul <- 1 { only for annulling Branch-Always }
+ nPC <- PC + sign_extend(disp22[]00);
+ if (BA and (a = 1)) then
+ annul <- 1 { only for annulling Branch-Always }
) else (
- nPC <- nPC + 4;
- if (a = 1) then
- annul <- 1 { only for annulling branches other than BA }
+ nPC <- nPC + 4;
+ if (a = 1) then
+ annul <- 1 { only for annulling branches other than BA }
)
*/
@@ -2342,35 +2342,35 @@ void mb86901_device::execute_ticc(UINT32 op)
/* The SPARC Instruction Manual: Version 8, page 182, "Appendix C - ISP Descriptions - Trap on Integer Condition Instructions" (SPARCv8.pdf, pg. 179)
trap_eval_icc := (
- if (TNE) then (if (Z = 0) then 1 else 0);
- if (TE) then (if (Z = 1) then 1 else 0);
- if (TG) then (if ((Z or (N xor V)) = 0) then 1 else 0);
- if (TLE) then (if ((Z or (N xor V)) = 1) then 1 else 0);
- if (TGE) then (if ((N xor V) = 0) then 1 else 0);
- if (TL) then (if ((N xor V) = 1) then 1 else 0);
- if (TGU) then (if ((C = 0) and (Z = 0)) then 1 else 0);
- if (TLEU) then (if ((C = 1) or (Z = 1)) then 1 else 0);
- if (TCC) then (if (C = 0) then 1 else 0);
- if (TCS) then (if (C = 1) then 1 else 0);
- if (TPOS) then (if (N = 0) then 1 else 0);
- if (TNEG) then (if (N = 1) then 1 else 0);
- if (TVC) then (if (V = 0) then 1 else 0);
- if (TVS) then (if (V = 1) then 1 else 0);
- if (TA) then 1;
- if (TN) then 0;
+ if (TNE) then (if (Z = 0) then 1 else 0);
+ if (TE) then (if (Z = 1) then 1 else 0);
+ if (TG) then (if ((Z or (N xor V)) = 0) then 1 else 0);
+ if (TLE) then (if ((Z or (N xor V)) = 1) then 1 else 0);
+ if (TGE) then (if ((N xor V) = 0) then 1 else 0);
+ if (TL) then (if ((N xor V) = 1) then 1 else 0);
+ if (TGU) then (if ((C = 0) and (Z = 0)) then 1 else 0);
+ if (TLEU) then (if ((C = 1) or (Z = 1)) then 1 else 0);
+ if (TCC) then (if (C = 0) then 1 else 0);
+ if (TCS) then (if (C = 1) then 1 else 0);
+ if (TPOS) then (if (N = 0) then 1 else 0);
+ if (TNEG) then (if (N = 1) then 1 else 0);
+ if (TVC) then (if (V = 0) then 1 else 0);
+ if (TVS) then (if (V = 1) then 1 else 0);
+ if (TA) then 1;
+ if (TN) then 0;
)
trap_number := r[rs1] + (if (i = 0) then r[rs2] else sign_extend(software_trap#));
if (Ticc) then (
- if (trap_eval_icc = 1) then (
- trap <- 1;
- trap_instruction <- 1;
- ticc_trap_type <- trap_number<6:0>
- ) else (
- PC <- nPC;
- nPC <- nPC + 4;
- )
+ if (trap_eval_icc = 1) then (
+ trap <- 1;
+ trap_instruction <- 1;
+ ticc_trap_type <- trap_number<6:0>
+ ) else (
+ PC <- nPC;
+ nPC <- nPC + 4;
+ )
);
*/
@@ -2489,76 +2489,76 @@ void mb86901_device::execute_trap()
next;
if (error_mode = 0) then (
- ET <- 0;
- PS <- S;
- CWP <- (CWP - 1) modulo NWINDOWS;
-
- next;
- if (annul = 0) then (
- r[17] <- PC;
- r[18] <- nPC;
- ) else { annul != 0) } (
- r[17] <- nPC;
- r[18] <- nPC + 4;
- annul <- 0;
- )
-
- next;
- S <- 1;
- if (reset_trap = 0) then (
- PC <- TBR;
- nPC <- TBR + 4;
- ) else { reset_trap = 1 } (
- PC <- 0;
- nPC <- 4;
- reset_trap <- 0;
- )
+ ET <- 0;
+ PS <- S;
+ CWP <- (CWP - 1) modulo NWINDOWS;
+
+ next;
+ if (annul = 0) then (
+ r[17] <- PC;
+ r[18] <- nPC;
+ ) else { annul != 0) } (
+ r[17] <- nPC;
+ r[18] <- nPC + 4;
+ annul <- 0;
+ )
+
+ next;
+ S <- 1;
+ if (reset_trap = 0) then (
+ PC <- TBR;
+ nPC <- TBR + 4;
+ ) else { reset_trap = 1 } (
+ PC <- 0;
+ nPC <- 4;
+ reset_trap <- 0;
+ )
);
select_trap := (
- if (reset_trap = 1) then { ignore ET, and leave tt unchanged }
- else if (ET = 0) then (
- execute_mode <- 0;
- error_mode <- 1 )
- else if (data_store_error = 1) then tt <- 00101011
- else if (instruction_access_error = 1) then tt <- 00100001
- else if (r_register_access_error = 1) then tt <- 00100000
- else if (instruction_access_exception = 1) then tt <- 00000001
- else if (privileged_instruction = 1) then tt <- 00000011
- else if (illegal_instruction = 1) then tt <- 00000010
- else if (fp_disabled = 1) then tt <- 00000100
- else if (cp_disabled = 1) then tt <- 00100100
- else if (unimplemented_FLUSH = 1) then tt <- 00100101
- else if (window_overflow = 1) then tt <- 00000101
- else if (window_underflow = 1) then tt <- 00000110
- else if (mem_address_not_aligned = 1) then tt <- 00000111
- else if (fp_exception = 1) then tt <- 00001000
- else if (cp_exception = 1) then tt <- 00101000
- else if (data_access_error = 1) then tt <- 00101001
- else if (data_access_exception = 1) then tt <- 00001001
- else if (tag_overflow = 1) then tt <- 00001010
- else if (division_by_zero = 1) then tt <- 00101010
- else if (trap_instruction = 1) then tt <- 1[]ticc_trap_type
- else if (interrupt_level > 0) then tt <- 0001[]interrupt_level;
-
- next;
-
- trap <- 0;
- instruction_access_exception <- 0;
- illegal_instruction <- 0;
- privileged_instruction <- 0;
- fp_disabled <- 0;
- cp_disabled <- 0;
- window_overflow <- 0;
- window_underflow <- 0;
- mem_address_not_aligned <- 0;
- fp_exception <- 0;
- cp_exception <- 0;
- data_access_exception <- 0;
- tag_overflow <- 0;
- division_by_zero <- 0;
- trap_instruction <- 0;
- interrupt_level <- 0;
+ if (reset_trap = 1) then { ignore ET, and leave tt unchanged }
+ else if (ET = 0) then (
+ execute_mode <- 0;
+ error_mode <- 1 )
+ else if (data_store_error = 1) then tt <- 00101011
+ else if (instruction_access_error = 1) then tt <- 00100001
+ else if (r_register_access_error = 1) then tt <- 00100000
+ else if (instruction_access_exception = 1) then tt <- 00000001
+ else if (privileged_instruction = 1) then tt <- 00000011
+ else if (illegal_instruction = 1) then tt <- 00000010
+ else if (fp_disabled = 1) then tt <- 00000100
+ else if (cp_disabled = 1) then tt <- 00100100
+ else if (unimplemented_FLUSH = 1) then tt <- 00100101
+ else if (window_overflow = 1) then tt <- 00000101
+ else if (window_underflow = 1) then tt <- 00000110
+ else if (mem_address_not_aligned = 1) then tt <- 00000111
+ else if (fp_exception = 1) then tt <- 00001000
+ else if (cp_exception = 1) then tt <- 00101000
+ else if (data_access_error = 1) then tt <- 00101001
+ else if (data_access_exception = 1) then tt <- 00001001
+ else if (tag_overflow = 1) then tt <- 00001010
+ else if (division_by_zero = 1) then tt <- 00101010
+ else if (trap_instruction = 1) then tt <- 1[]ticc_trap_type
+ else if (interrupt_level > 0) then tt <- 0001[]interrupt_level;
+
+ next;
+
+ trap <- 0;
+ instruction_access_exception <- 0;
+ illegal_instruction <- 0;
+ privileged_instruction <- 0;
+ fp_disabled <- 0;
+ cp_disabled <- 0;
+ window_overflow <- 0;
+ window_underflow <- 0;
+ mem_address_not_aligned <- 0;
+ fp_exception <- 0;
+ cp_exception <- 0;
+ data_access_exception <- 0;
+ tag_overflow <- 0;
+ division_by_zero <- 0;
+ trap_instruction <- 0;
+ interrupt_level <- 0;
);
*/
@@ -2615,7 +2615,7 @@ void mb86901_device::complete_instruction_execution(UINT32 op)
{
switch (OP)
{
- case OP_TYPE0: // Bicc, SETHI, FBfcc
+ case OP_TYPE0: // Bicc, SETHI, FBfcc
switch (OP2)
{
case OP2_UNIMP: // unimp
@@ -2624,7 +2624,7 @@ void mb86901_device::complete_instruction_execution(UINT32 op)
case OP2_BICC: // branch on integer condition codes
execute_bicc(op);
break;
- case OP2_SETHI: // sethi
+ case OP2_SETHI: // sethi
SET_RDREG(IMM22);
break;
case OP2_FBFCC: // branch on floating-point condition codes
@@ -2674,26 +2674,26 @@ void mb86901_device::dispatch_instruction(UINT32 op)
/* The SPARC Instruction Manual: Version 8, page 159, "Appendix C - ISP Descriptions - C.6. Instruction Dispatch" (SPARCv8.pdf, pg. 156)
illegal_IU_instr :- (
- if ( ( (op == 00) and (op2 == 000) ) { UNIMP instruction }
- or
+ if ( ( (op == 00) and (op2 == 000) ) { UNIMP instruction }
+ or
( ((op=11) or (op=10)) and (op3=unassigned) )
- then 1 else 0
+ then 1 else 0
if (illegal_IU_instr = 1) then (
- trap <- 1
- illegal_instruction <- 1
+ trap <- 1
+ illegal_instruction <- 1
);
if ((FPop1 or FPop2 or FBfcc) and ((EF = 0) or (bp_FPU_present = 0))) then (
- trap <- 1;
- fp_disabled <- 1
+ trap <- 1;
+ fp_disabled <- 1
);
if (CPop1 or CPop2 or CBccc) and ((EC = 0) or (bp_CP_present = 0))) then (
- trap <- 1;
- cp_disabled <- 1
+ trap <- 1;
+ cp_disabled <- 1
);
next;
if (trap = 0) then (
- { code for specific instruction, defined below }
+ { code for specific instruction, defined below }
);
*/
bool illegal_IU_instr = (OP == 0 && OP2 == 0) || ((OP == 3 && !m_ldst_op3_assigned[OP3]) || (OP == 2 && !m_alu_op3_assigned[OP3]));
@@ -2742,12 +2742,12 @@ void mb86901_device::execute_step()
/* The SPARC Instruction Manual: Version 8, page 156, "Appendix C - ISP Descriptions - C.5. Processor States and Instruction Dispatch" (SPARCv8.pdf, pg. 153)
if (bp_reset_in = 1) then (
- execute_mode <- 0;
- reset_mode <- 1;
- break { out of while (execute_mode = 1) loop }
+ execute_mode <- 0;
+ reset_mode <- 1;
+ break { out of while (execute_mode = 1) loop }
) else if ((ET = 1) and ((bp_IRL = 15) or (bp_IRL > PIL))) then (
- trap <- 1;
- interrupt_level <- bp_IRL
+ trap <- 1;
+ interrupt_level <- bp_IRL
);
next;
@@ -2755,40 +2755,40 @@ void mb86901_device::execute_step()
if (execute_mode = 1) then ( { execute_trap may have set execute_mode to 0 }
- { the following code emulates the delayed nature of the write-state-register instructions.
- PSR <- PSR'; PSR' <- PSR''; PSR'' <- PSR'''; PSR''' <- PSR'''';
- ASR <- ASR'; ASR' <- ASR''; ASR'' <- ASR'''; ASR''' <- ASR'''';
- TBR <- TBR'; TBR' <- TBR''; TBR'' <- TBR'''; TBR''' <- TBR'''';
- WIM <- WIM'; WIM' <- WIM''; WIM'' <- WIM'''; WIM''' <- WIM'''';
- Y <- Y'; Y' <- Y''; Y'' <- Y'''; Y''' <- Y'''';
- next;
-
- addr_space := (if (S = 0) then 8 else 9);
- (instruction, MAE) <- memory_read(addr_space, PC);
- next;
-
- if ( (MAE = 1) and (annul = 0) ) then (
- trap <- 1;
- instruction_access_exception <- 1
- ) else (
- if (annul = 0) then (
- dispatch_instruction ; { See Section C.6 }
- next;
- if (FPop1 or FPop2) then (
- complete_fp_execution { See Section C.7 }
- )
- next;
- if ( (trap = 0) and
- not (CALL or RETT or JMPL or Bicc or FBfcc or CBccc or Ticc) ) then (
- PC <- nPC;
- nPC <- nPC + 4
- )
- ) else { annul != 0 } (
- annul <- 0;
- PC <- nPC;
- nPC <- nPC + 4
- )
- )
+ { the following code emulates the delayed nature of the write-state-register instructions.
+ PSR <- PSR'; PSR' <- PSR''; PSR'' <- PSR'''; PSR''' <- PSR'''';
+ ASR <- ASR'; ASR' <- ASR''; ASR'' <- ASR'''; ASR''' <- ASR'''';
+ TBR <- TBR'; TBR' <- TBR''; TBR'' <- TBR'''; TBR''' <- TBR'''';
+ WIM <- WIM'; WIM' <- WIM''; WIM'' <- WIM'''; WIM''' <- WIM'''';
+ Y <- Y'; Y' <- Y''; Y'' <- Y'''; Y''' <- Y'''';
+ next;
+
+ addr_space := (if (S = 0) then 8 else 9);
+ (instruction, MAE) <- memory_read(addr_space, PC);
+ next;
+
+ if ( (MAE = 1) and (annul = 0) ) then (
+ trap <- 1;
+ instruction_access_exception <- 1
+ ) else (
+ if (annul = 0) then (
+ dispatch_instruction ; { See Section C.6 }
+ next;
+ if (FPop1 or FPop2) then (
+ complete_fp_execution { See Section C.7 }
+ )
+ next;
+ if ( (trap = 0) and
+ not (CALL or RETT or JMPL or Bicc or FBfcc or CBccc or Ticc) ) then (
+ PC <- nPC;
+ nPC <- nPC + 4
+ )
+ ) else { annul != 0 } (
+ annul <- 0;
+ PC <- nPC;
+ nPC <- nPC + 4
+ )
+ )
)
*/
if (m_bp_reset_in)
@@ -2898,7 +2898,7 @@ void mb86901_device::execute_step()
printf("Opcode at %08x: %04x, handler is at %08x // add 32-bit word (%08x) from handler table to result (%08x + %08x = %08x)\n", REG(5), opcode, handler_offset, value, REG(4), value, REG(4) + value);
}
else if (opcode == 0x003f || opcode == 0x0066 || opcode == 0x0099 || opcode == 0x0121 || opcode == 0x0136 || opcode == 0x014f || opcode == 0x0155 || opcode == 0x01c7 || opcode == 0x01cd ||
- opcode == 0x0217 || opcode == 0x0289 || opcode == 0x0296 || opcode == 0x029d || opcode == 0x02f2 || opcode == 0x0334 || opcode == 0x0381 || opcode == 0x3d38)
+ opcode == 0x0217 || opcode == 0x0289 || opcode == 0x0296 || opcode == 0x029d || opcode == 0x02f2 || opcode == 0x0334 || opcode == 0x0381 || opcode == 0x3d38)
{
switch(opcode)
{
@@ -3093,7 +3093,6 @@ void mb86901_device::execute_step()
}
else
{
-
m_annul = 0;
PC = nPC;
nPC = nPC + 4;
@@ -3112,12 +3111,12 @@ void mb86901_device::reset_step()
/* The SPARC Instruction Manual: Version 8, page 156, "Appendix C - ISP Descriptions - C.5. Processor States and Instruction Dispatch" (SPARCv8.pdf, pg. 153)
while (reset_mode = 1) (
- if (bp_reset_in = 0) then (
- reset_mode <- 0;
- execute_mode <- 1;
- trap <- 1;
- reset_trap <- 1;
- )
+ if (bp_reset_in = 0) then (
+ reset_mode <- 0;
+ execute_mode <- 1;
+ trap <- 1;
+ reset_trap <- 1;
+ )
);
*/
@@ -3140,11 +3139,11 @@ void mb86901_device::error_step()
/* The SPARC Instruction Manual: Version 8, page 157, "Appendix C - ISP Descriptions - C.5. Processor States and Instruction Dispatch" (SPARCv8.pdf, pg. 154)
while (error_mode = 1) (
- if (bp_reset_in = 1) then (
- error_mode <- 0;
- reset_mode <- 1;
- pb_error <- 0
- )
+ if (bp_reset_in = 1) then (
+ error_mode <- 0;
+ reset_mode <- 1;
+ pb_error <- 0
+ )
);
*/
@@ -3193,9 +3192,9 @@ void mb86901_device::execute_run()
{
for (int i = 0; i < 8; i++)
{
- m_dbgregs[i] = *m_regs[8 + i];
- m_dbgregs[8 + i] = *m_regs[16 + i];
- m_dbgregs[16 + i] = *m_regs[24 + i];
+ m_dbgregs[i] = *m_regs[8 + i];
+ m_dbgregs[8 + i] = *m_regs[16 + i];
+ m_dbgregs[16 + i] = *m_regs[24 + i];
}
}
--m_icount;
diff --git a/src/devices/cpu/sparc/sparc.h b/src/devices/cpu/sparc/sparc.h
index da2d0bc7c82..1acc2263854 100644
--- a/src/devices/cpu/sparc/sparc.h
+++ b/src/devices/cpu/sparc/sparc.h
@@ -11,36 +11,36 @@
#include "sparcdasm.h"
-#define SPARCV8 (0)
-
-#define SPARC_NO_TRAP 256
-#define SPARC_RESET 0
-#define SPARC_INSTRUCTION_ACCESS_EXCEPTION 1
-#define SPARC_ILLEGAL_INSTRUCTION 2
-#define SPARC_PRIVILEGED_INSTRUCTION 3
-#define SPARC_FP_DISABLED 4
-#define SPARC_WINDOW_OVERFLOW 5
-#define SPARC_WINDOW_UNDERFLOW 6
-#define SPARC_MEM_ADDRESS_NOT_ALIGNED 7
-#define SPARC_FLOATING_POINT_EXCEPTION 8
-#define SPARC_DATA_ACCESS_EXCEPTION 9
-#define SPARC_TAG_OVERFLOW 10
-#define SPARC_INT1 17
-#define SPARC_INT2 18
-#define SPARC_INT3 19
-#define SPARC_INT4 20
-#define SPARC_INT5 21
-#define SPARC_INT6 22
-#define SPARC_INT7 23
-#define SPARC_INT8 24
-#define SPARC_INT9 25
-#define SPARC_INT10 26
-#define SPARC_INT11 27
-#define SPARC_INT12 28
-#define SPARC_INT13 29
-#define SPARC_INT14 30
-#define SPARC_INT15 31
-#define SPARC_TRAP_INSTRUCTION 128
+#define SPARCV8 (0)
+
+#define SPARC_NO_TRAP 256
+#define SPARC_RESET 0
+#define SPARC_INSTRUCTION_ACCESS_EXCEPTION 1
+#define SPARC_ILLEGAL_INSTRUCTION 2
+#define SPARC_PRIVILEGED_INSTRUCTION 3
+#define SPARC_FP_DISABLED 4
+#define SPARC_WINDOW_OVERFLOW 5
+#define SPARC_WINDOW_UNDERFLOW 6
+#define SPARC_MEM_ADDRESS_NOT_ALIGNED 7
+#define SPARC_FLOATING_POINT_EXCEPTION 8
+#define SPARC_DATA_ACCESS_EXCEPTION 9
+#define SPARC_TAG_OVERFLOW 10
+#define SPARC_INT1 17
+#define SPARC_INT2 18
+#define SPARC_INT3 19
+#define SPARC_INT4 20
+#define SPARC_INT5 21
+#define SPARC_INT6 22
+#define SPARC_INT7 23
+#define SPARC_INT8 24
+#define SPARC_INT9 25
+#define SPARC_INT10 26
+#define SPARC_INT11 27
+#define SPARC_INT12 28
+#define SPARC_INT13 29
+#define SPARC_INT14 30
+#define SPARC_INT15 31
+#define SPARC_TRAP_INSTRUCTION 128
#define SPARC_FPU_SEQUENCE_ERROR
// TODO: when there are more SPARC CPUs, move setter to a base class
@@ -200,16 +200,16 @@ protected:
UINT8 m_cp_sequence_err;
// fields separated out from PSR (Processor State Register)
- UINT8 m_impl; // implementation (always 0 in MB86901)
- UINT8 m_ver; // version (always 0 in MB86901)
- UINT8 m_icc; // integer condition codes
- bool m_ec; // enable coprocessor
- bool m_ef; // enable FPU
- UINT8 m_pil; // processor interrupt level
- bool m_s; // supervisor mode
- bool m_ps; // prior S state
- bool m_et; // enable traps
- UINT8 m_cwp; // current window pointer
+ UINT8 m_impl; // implementation (always 0 in MB86901)
+ UINT8 m_ver; // version (always 0 in MB86901)
+ UINT8 m_icc; // integer condition codes
+ bool m_ec; // enable coprocessor
+ bool m_ef; // enable FPU
+ UINT8 m_pil; // processor interrupt level
+ bool m_s; // supervisor mode
+ bool m_ps; // prior S state
+ bool m_et; // enable traps
+ UINT8 m_cwp; // current window pointer
bool m_alu_op3_assigned[64];
bool m_ldst_op3_assigned[64];
@@ -259,10 +259,10 @@ enum
SPARC_ICC,
SPARC_CWP,
- SPARC_G0, SPARC_G1, SPARC_G2, SPARC_G3, SPARC_G4, SPARC_G5, SPARC_G6, SPARC_G7,
- SPARC_O0, SPARC_O1, SPARC_O2, SPARC_O3, SPARC_O4, SPARC_O5, SPARC_O6, SPARC_O7,
- SPARC_L0, SPARC_L1, SPARC_L2, SPARC_L3, SPARC_L4, SPARC_L5, SPARC_L6, SPARC_L7,
- SPARC_I0, SPARC_I1, SPARC_I2, SPARC_I3, SPARC_I4, SPARC_I5, SPARC_I6, SPARC_I7,
+ SPARC_G0, SPARC_G1, SPARC_G2, SPARC_G3, SPARC_G4, SPARC_G5, SPARC_G6, SPARC_G7,
+ SPARC_O0, SPARC_O1, SPARC_O2, SPARC_O3, SPARC_O4, SPARC_O5, SPARC_O6, SPARC_O7,
+ SPARC_L0, SPARC_L1, SPARC_L2, SPARC_L3, SPARC_L4, SPARC_L5, SPARC_L6, SPARC_L7,
+ SPARC_I0, SPARC_I1, SPARC_I2, SPARC_I3, SPARC_I4, SPARC_I5, SPARC_I6, SPARC_I7,
SPARC_EC,
SPARC_EF,
@@ -271,13 +271,13 @@ enum
SPARC_S,
SPARC_PS,
- SPARC_R0, SPARC_R1, SPARC_R2, SPARC_R3, SPARC_R4, SPARC_R5, SPARC_R6, SPARC_R7, SPARC_R8, SPARC_R9, SPARC_R10, SPARC_R11, SPARC_R12, SPARC_R13, SPARC_R14, SPARC_R15,
- SPARC_R16, SPARC_R17, SPARC_R18, SPARC_R19, SPARC_R20, SPARC_R21, SPARC_R22, SPARC_R23, SPARC_R24, SPARC_R25, SPARC_R26, SPARC_R27, SPARC_R28, SPARC_R29, SPARC_R30, SPARC_R31,
- SPARC_R32, SPARC_R33, SPARC_R34, SPARC_R35, SPARC_R36, SPARC_R37, SPARC_R38, SPARC_R39, SPARC_R40, SPARC_R41, SPARC_R42, SPARC_R43, SPARC_R44, SPARC_R45, SPARC_R46, SPARC_R47,
- SPARC_R48, SPARC_R49, SPARC_R50, SPARC_R51, SPARC_R52, SPARC_R53, SPARC_R54, SPARC_R55, SPARC_R56, SPARC_R57, SPARC_R58, SPARC_R59, SPARC_R60, SPARC_R61, SPARC_R62, SPARC_R63,
- SPARC_R64, SPARC_R65, SPARC_R66, SPARC_R67, SPARC_R68, SPARC_R69, SPARC_R70, SPARC_R71, SPARC_R72, SPARC_R73, SPARC_R74, SPARC_R75, SPARC_R76, SPARC_R77, SPARC_R78, SPARC_R79,
- SPARC_R80, SPARC_R81, SPARC_R82, SPARC_R83, SPARC_R84, SPARC_R85, SPARC_R86, SPARC_R87, SPARC_R88, SPARC_R89, SPARC_R90, SPARC_R91, SPARC_R92, SPARC_R93, SPARC_R94, SPARC_R95,
- SPARC_R96, SPARC_R97, SPARC_R98, SPARC_R99, SPARC_R100, SPARC_R101, SPARC_R102, SPARC_R103, SPARC_R104, SPARC_R105, SPARC_R106, SPARC_R107, SPARC_R108, SPARC_R109, SPARC_R110, SPARC_R111
+ SPARC_R0, SPARC_R1, SPARC_R2, SPARC_R3, SPARC_R4, SPARC_R5, SPARC_R6, SPARC_R7, SPARC_R8, SPARC_R9, SPARC_R10, SPARC_R11, SPARC_R12, SPARC_R13, SPARC_R14, SPARC_R15,
+ SPARC_R16, SPARC_R17, SPARC_R18, SPARC_R19, SPARC_R20, SPARC_R21, SPARC_R22, SPARC_R23, SPARC_R24, SPARC_R25, SPARC_R26, SPARC_R27, SPARC_R28, SPARC_R29, SPARC_R30, SPARC_R31,
+ SPARC_R32, SPARC_R33, SPARC_R34, SPARC_R35, SPARC_R36, SPARC_R37, SPARC_R38, SPARC_R39, SPARC_R40, SPARC_R41, SPARC_R42, SPARC_R43, SPARC_R44, SPARC_R45, SPARC_R46, SPARC_R47,
+ SPARC_R48, SPARC_R49, SPARC_R50, SPARC_R51, SPARC_R52, SPARC_R53, SPARC_R54, SPARC_R55, SPARC_R56, SPARC_R57, SPARC_R58, SPARC_R59, SPARC_R60, SPARC_R61, SPARC_R62, SPARC_R63,
+ SPARC_R64, SPARC_R65, SPARC_R66, SPARC_R67, SPARC_R68, SPARC_R69, SPARC_R70, SPARC_R71, SPARC_R72, SPARC_R73, SPARC_R74, SPARC_R75, SPARC_R76, SPARC_R77, SPARC_R78, SPARC_R79,
+ SPARC_R80, SPARC_R81, SPARC_R82, SPARC_R83, SPARC_R84, SPARC_R85, SPARC_R86, SPARC_R87, SPARC_R88, SPARC_R89, SPARC_R90, SPARC_R91, SPARC_R92, SPARC_R93, SPARC_R94, SPARC_R95,
+ SPARC_R96, SPARC_R97, SPARC_R98, SPARC_R99, SPARC_R100, SPARC_R101, SPARC_R102, SPARC_R103, SPARC_R104, SPARC_R105, SPARC_R106, SPARC_R107, SPARC_R108, SPARC_R109, SPARC_R110, SPARC_R111
};
#endif /* __SPARC_H__ */
diff --git a/src/devices/cpu/sparc/sparcdefs.h b/src/devices/cpu/sparc/sparcdefs.h
index 7fab760e06b..c59282ffa85 100644
--- a/src/devices/cpu/sparc/sparcdefs.h
+++ b/src/devices/cpu/sparc/sparcdefs.h
@@ -12,375 +12,375 @@
#ifndef __MB86901_DEFS_H__
#define __MB86901_DEFS_H__
-#define PSR_CWP_MASK 0x0000001f
-#define PSR_ET_SHIFT 5
-#define PSR_ET_MASK 0x00000020
-#define PSR_PS_SHIFT 6
-#define PSR_PS_MASK 0x00000040
-#define PSR_S_SHIFT 7
-#define PSR_S_MASK 0x00000080
-#define PSR_PIL_SHIFT 8
-#define PSR_PIL_MASK 0x00000f00
-#define PSR_EF_SHIFT 12
-#define PSR_EF_MASK 0x00001000
-#define PSR_EC_SHIFT 13
-#define PSR_EC_MASK 0x00002000
-#define PSR_ICC_SHIFT 20
-#define PSR_RES_MASK 0x000fc000
-#define PSR_ICC_MASK 0x00f00000
-#define PSR_N_MASK 0x00800000
-#define PSR_Z_MASK 0x00400000
-#define PSR_V_MASK 0x00200000
-#define PSR_C_MASK 0x00100000
-#define PSR_VER_SHIFT 24
-#define PSR_VER_MASK 0x0f000000
-#define PSR_VER 0
-#define PSR_IMPL_SHIFT 28
-#define PSR_IMPL_MASK 0xf0000000
-#define PSR_IMPL 0
-#define PSR_ZERO_MASK (PSR_IMPL_MASK | PSR_VER_MASK | PSR_RES_MASK)
-
-#define ICC_N_SET (m_psr & PSR_N_MASK)
-#define ICC_N (ICC_N_SET ? 1 : 0)
-#define ICC_N_CLEAR (!ICC_N_SET)
-#define SET_ICC_N_FLAG do { m_psr |= PSR_N_MASK; } while(0)
-#define CLEAR_ICC_N_FLAG do { m_psr &= ~PSR_N_MASK; } while(0)
-
-#define ICC_Z_SET (m_psr & PSR_Z_MASK)
-#define ICC_Z (ICC_Z_SET ? 1 : 0)
-#define ICC_Z_CLEAR (!ICC_Z_SET)
-#define SET_ICC_Z_FLAG do { m_psr |= PSR_Z_MASK; } while(0)
-#define CLEAR_ICC_Z_FLAG do { m_psr &= ~PSR_Z_MASK; } while(0)
-
-#define ICC_V_SET (m_psr & PSR_V_MASK)
-#define ICC_V (ICC_V_SET ? 1 : 0)
-#define ICC_V_CLEAR (!ICC_V_SET)
-#define SET_ICC_V_FLAG do { m_psr |= PSR_V_MASK; } while(0)
-#define CLEAR_ICC_V_FLAG do { m_psr &= ~PSR_V_MASK; } while(0)
-
-#define ICC_C_SET (m_psr & PSR_C_MASK)
-#define ICC_C (ICC_C_SET ? 1 : 0)
-#define ICC_C_CLEAR (!ICC_C_SET)
-#define SET_ICC_C_FLAG do { m_psr |= PSR_C_MASK; } while(0)
-#define CLEAR_ICC_C_FLAG do { m_psr &= ~PSR_C_MASK; } while(0)
-
-#define CLEAR_ICC do { m_psr &= ~PSR_ICC_MASK; } while(0)
-
-#define TEST_ICC_NZ(x) do { m_psr &= ~PSR_ICC_MASK; m_psr |= (x & 0x80000000) ? PSR_N_MASK : 0; m_psr |= (x == 0) ? PSR_Z_MASK : 0; } while (0)
-
-#define MAKE_PSR do { m_psr = (m_impl << PSR_IMPL_SHIFT) | (m_ver << PSR_VER_SHIFT) | (m_icc << PSR_ICC_SHIFT) | (m_ec ? PSR_EC_MASK : 0) | (m_ef ? PSR_EF_MASK : 0) | (m_pil << PSR_PIL_SHIFT) | (m_s ? PSR_S_MASK : 0) | (m_ps ? PSR_PS_MASK : 0) | (m_et ? PSR_ET_MASK : 0) | m_cwp; } while(0)
-#define BREAK_PSR do { m_icc = (m_psr & PSR_ICC_MASK) >> PSR_ICC_SHIFT; m_ec = m_psr & PSR_EC_MASK; m_ef = m_psr & PSR_EF_MASK; m_pil = (m_psr & PSR_PIL_MASK) >> PSR_PIL_SHIFT; m_s = m_psr & PSR_S_MASK; m_ps = m_psr & PSR_PS_MASK; m_et = m_psr & PSR_ET_MASK; m_cwp = m_psr & PSR_CWP_MASK; } while(0)
-#define MAKE_ICC do { m_icc = (m_psr & PSR_ICC_MASK) >> PSR_ICC_SHIFT; } while(0)
-
-#define CWP m_cwp
-#define S m_s
-#define PS m_ps
-
-#define IS_SUPERVISOR (m_psr & PSR_S_MASK)
-#define IS_USER (!IS_SUPERVISOR)
-
-#define TRAPS_ENABLED (m_psr & PSR_ET_MASK)
-#define TRAPS_DISABLED (!TRAPS_ENABLED)
-
-#define PSR m_psr
-#define WIM m_wim
-#define TBR m_tbr
-
-#define OP (op >> 30) // gangnam style
-#define OP2 ((op >> 22) & 7)
-#define OP3 ((op >> 19) & 63)
-#define OPF ((op >> 5) & 0x1ff)
-#define OPC ((op >> 5) & 0x1ff)
-#define OPFLOW ((op >> 5) & 0x3f)
-
-#define DISP30 (INT32(op << 2))
-#define DISP22 (INT32(op << 10) >> 8)
-#define DISP19 (INT32(op << 13) >> 11)
-#define DISP16 (INT32(((op << 10) & 0xc0000000) | ((op << 16) & 0x3fff0000)) >> 14)
-#define IMM22 (op << 10)
+#define PSR_CWP_MASK 0x0000001f
+#define PSR_ET_SHIFT 5
+#define PSR_ET_MASK 0x00000020
+#define PSR_PS_SHIFT 6
+#define PSR_PS_MASK 0x00000040
+#define PSR_S_SHIFT 7
+#define PSR_S_MASK 0x00000080
+#define PSR_PIL_SHIFT 8
+#define PSR_PIL_MASK 0x00000f00
+#define PSR_EF_SHIFT 12
+#define PSR_EF_MASK 0x00001000
+#define PSR_EC_SHIFT 13
+#define PSR_EC_MASK 0x00002000
+#define PSR_ICC_SHIFT 20
+#define PSR_RES_MASK 0x000fc000
+#define PSR_ICC_MASK 0x00f00000
+#define PSR_N_MASK 0x00800000
+#define PSR_Z_MASK 0x00400000
+#define PSR_V_MASK 0x00200000
+#define PSR_C_MASK 0x00100000
+#define PSR_VER_SHIFT 24
+#define PSR_VER_MASK 0x0f000000
+#define PSR_VER 0
+#define PSR_IMPL_SHIFT 28
+#define PSR_IMPL_MASK 0xf0000000
+#define PSR_IMPL 0
+#define PSR_ZERO_MASK (PSR_IMPL_MASK | PSR_VER_MASK | PSR_RES_MASK)
+
+#define ICC_N_SET (m_psr & PSR_N_MASK)
+#define ICC_N (ICC_N_SET ? 1 : 0)
+#define ICC_N_CLEAR (!ICC_N_SET)
+#define SET_ICC_N_FLAG do { m_psr |= PSR_N_MASK; } while(0)
+#define CLEAR_ICC_N_FLAG do { m_psr &= ~PSR_N_MASK; } while(0)
+
+#define ICC_Z_SET (m_psr & PSR_Z_MASK)
+#define ICC_Z (ICC_Z_SET ? 1 : 0)
+#define ICC_Z_CLEAR (!ICC_Z_SET)
+#define SET_ICC_Z_FLAG do { m_psr |= PSR_Z_MASK; } while(0)
+#define CLEAR_ICC_Z_FLAG do { m_psr &= ~PSR_Z_MASK; } while(0)
+
+#define ICC_V_SET (m_psr & PSR_V_MASK)
+#define ICC_V (ICC_V_SET ? 1 : 0)
+#define ICC_V_CLEAR (!ICC_V_SET)
+#define SET_ICC_V_FLAG do { m_psr |= PSR_V_MASK; } while(0)
+#define CLEAR_ICC_V_FLAG do { m_psr &= ~PSR_V_MASK; } while(0)
+
+#define ICC_C_SET (m_psr & PSR_C_MASK)
+#define ICC_C (ICC_C_SET ? 1 : 0)
+#define ICC_C_CLEAR (!ICC_C_SET)
+#define SET_ICC_C_FLAG do { m_psr |= PSR_C_MASK; } while(0)
+#define CLEAR_ICC_C_FLAG do { m_psr &= ~PSR_C_MASK; } while(0)
+
+#define CLEAR_ICC do { m_psr &= ~PSR_ICC_MASK; } while(0)
+
+#define TEST_ICC_NZ(x) do { m_psr &= ~PSR_ICC_MASK; m_psr |= (x & 0x80000000) ? PSR_N_MASK : 0; m_psr |= (x == 0) ? PSR_Z_MASK : 0; } while (0)
+
+#define MAKE_PSR do { m_psr = (m_impl << PSR_IMPL_SHIFT) | (m_ver << PSR_VER_SHIFT) | (m_icc << PSR_ICC_SHIFT) | (m_ec ? PSR_EC_MASK : 0) | (m_ef ? PSR_EF_MASK : 0) | (m_pil << PSR_PIL_SHIFT) | (m_s ? PSR_S_MASK : 0) | (m_ps ? PSR_PS_MASK : 0) | (m_et ? PSR_ET_MASK : 0) | m_cwp; } while(0)
+#define BREAK_PSR do { m_icc = (m_psr & PSR_ICC_MASK) >> PSR_ICC_SHIFT; m_ec = m_psr & PSR_EC_MASK; m_ef = m_psr & PSR_EF_MASK; m_pil = (m_psr & PSR_PIL_MASK) >> PSR_PIL_SHIFT; m_s = m_psr & PSR_S_MASK; m_ps = m_psr & PSR_PS_MASK; m_et = m_psr & PSR_ET_MASK; m_cwp = m_psr & PSR_CWP_MASK; } while(0)
+#define MAKE_ICC do { m_icc = (m_psr & PSR_ICC_MASK) >> PSR_ICC_SHIFT; } while(0)
+
+#define CWP m_cwp
+#define S m_s
+#define PS m_ps
+
+#define IS_SUPERVISOR (m_psr & PSR_S_MASK)
+#define IS_USER (!IS_SUPERVISOR)
+
+#define TRAPS_ENABLED (m_psr & PSR_ET_MASK)
+#define TRAPS_DISABLED (!TRAPS_ENABLED)
+
+#define PSR m_psr
+#define WIM m_wim
+#define TBR m_tbr
+
+#define OP (op >> 30) // gangnam style
+#define OP2 ((op >> 22) & 7)
+#define OP3 ((op >> 19) & 63)
+#define OPF ((op >> 5) & 0x1ff)
+#define OPC ((op >> 5) & 0x1ff)
+#define OPFLOW ((op >> 5) & 0x3f)
+
+#define DISP30 (INT32(op << 2))
+#define DISP22 (INT32(op << 10) >> 8)
+#define DISP19 (INT32(op << 13) >> 11)
+#define DISP16 (INT32(((op << 10) & 0xc0000000) | ((op << 16) & 0x3fff0000)) >> 14)
+#define IMM22 (op << 10)
#define CONST22 (op & 0x3fffff)
-#define SIMM13 (INT32(op << 19) >> 19)
-#define SIMM11 (INT32(op << 21) >> 21)
-#define SIMM10 (INT32(op << 22) >> 22)
-#define SIMM8 (INT32(op << 24) >> 24)
-#define IMM7 (op & 0x7f)
-#define SIMM7 (INT32(op << 25) >> 25)
-#define SHCNT32 (op & 31)
+#define SIMM13 (INT32(op << 19) >> 19)
+#define SIMM11 (INT32(op << 21) >> 21)
+#define SIMM10 (INT32(op << 22) >> 22)
+#define SIMM8 (INT32(op << 24) >> 24)
+#define IMM7 (op & 0x7f)
+#define SIMM7 (INT32(op << 25) >> 25)
+#define SHCNT32 (op & 31)
#define SHCNT64 (op & 63)
#define IAMODE (op & 0x7)
-#define USEIMM ((op >> 13) & 1)
-#define USEEXT ((op >> 12) & 1)
-
-
-#define COND ((op >> 25) & 15)
-#define RCOND ((op >> 10) & 7)
-#define MOVCOND ((op >> 14) & 15)
-#define PRED ((op >> 19) & 1)
-#define ANNUL ((op >> 29) & 1)
-#define BRCC ((op >> 20) & 3)
-#define MOVCC (((op >> 11) & 3) | ((op >> 16) & 4))
-#define OPFCC ((op >> 11) & 7)
-#define TCCCC ((op >> 11) & 3)
-#define ASI ((op >> 5) & 255)
-#define MMASK (op & 15)
-#define CMASK ((op >> 4) & 7)
-
-#define RD ((op >> 25) & 31)
-#define RS1 ((op >> 14) & 31)
-#define RS2 (op & 31)
-
-#define FREG(x) m_fpr[(x)]
-#define FDREG m_fpr[RD]
-#define FSR m_fsr
-
-#define REG(x) *m_regs[(x)]
-#define RDREG *m_regs[RD]
-#define RS1REG *m_regs[RS1]
-#define RS2REG *m_regs[RS2]
-#define SET_RDREG(x) do { if(RD) { RDREG = (x); } } while (0)
-#define ADDRESS (USEIMM ? (RS1REG + SIMM13) : (RS1REG + RS2REG))
-
-#define PC m_pc
-#define nPC m_npc
-
-#define Y m_y
-
-#define ET m_et
-#define EF m_ef
-#define EC m_ec
-#define PIL m_pil
-
-#define MAE m_mae
-#define HOLD_BUS m_hold_bus
-
-#define BIT31(x) ((x) & 0x80000000)
-
-#define UPDATE_PC true
-#define PC_UPDATED false
-
-#define OP_TYPE0 0
-#define OP_CALL 1
-#define OP_ALU 2
-#define OP_LDST 3
-
-#define OP2_UNIMP 0
-#define OP2_BICC 2
-#define OP2_SETHI 4
-#define OP2_FBFCC 6
-#define OP2_CBCCC 7
-
-#define OP3_ADD 0
-#define OP3_AND 1
-#define OP3_OR 2
-#define OP3_XOR 3
-#define OP3_SUB 4
-#define OP3_ANDN 5
-#define OP3_ORN 6
-#define OP3_XNOR 7
-#define OP3_ADDX 8
-#define OP3_UMUL 10
-#define OP3_SMUL 11
-#define OP3_SUBX 12
-#define OP3_UDIV 14
-#define OP3_SDIV 15
-#define OP3_ADDCC 16
-#define OP3_ANDCC 17
-#define OP3_ORCC 18
-#define OP3_XORCC 19
-#define OP3_SUBCC 20
-#define OP3_ANDNCC 21
-#define OP3_ORNCC 22
-#define OP3_XNORCC 23
-#define OP3_ADDXCC 24
-#define OP3_UMULCC 26
-#define OP3_SMULCC 27
-#define OP3_SUBXCC 28
-#define OP3_UDIVCC 30
-#define OP3_SDIVCC 31
-#define OP3_TADDCC 32
-#define OP3_TSUBCC 33
-#define OP3_TADDCCTV 34
-#define OP3_TSUBCCTV 35
-#define OP3_MULSCC 36
-#define OP3_SLL 37
-#define OP3_SRL 38
-#define OP3_SRA 39
-#define OP3_RDASR 40
-#define OP3_RDPSR 41
-#define OP3_RDWIM 42
-#define OP3_RDTBR 43
-#define OP3_WRASR 48
-#define OP3_WRPSR 49
-#define OP3_WRWIM 50
-#define OP3_WRTBR 51
-#define OP3_FPOP1 52
-#define OP3_FPOP2 53
-#define OP3_JMPL 56
-#define OP3_RETT 57
-#define OP3_TICC 58
-#define OP3_SAVE 60
-#define OP3_RESTORE 61
-
-#define OP3_LD 0
-#define OP3_LDUB 1
-#define OP3_LDUH 2
-#define OP3_LDD 3
-#define OP3_ST 4
-#define OP3_STB 5
-#define OP3_STH 6
-#define OP3_STD 7
-#define OP3_LDSB 9
-#define OP3_LDSH 10
-#define OP3_LDSTUB 13
-#define OP3_SWAP 15
-#define OP3_LDA 16
-#define OP3_LDUBA 17
-#define OP3_LDUHA 18
-#define OP3_LDDA 19
-#define OP3_STA 20
-#define OP3_STBA 21
-#define OP3_STHA 22
-#define OP3_STDA 23
-#define OP3_LDSBA 25
-#define OP3_LDSHA 26
-#define OP3_LDSTUBA 29
-#define OP3_SWAPA 31
-#define OP3_LDFPR 32
-#define OP3_LDFSR 33
-#define OP3_LDDFPR 35
-#define OP3_STFPR 36
-#define OP3_STFSR 37
-#define OP3_STDFQ 38
-#define OP3_STDFPR 39
-#define OP3_LDCPR 40
-#define OP3_LDCSR 41
-#define OP3_LDDCPR 43
-#define OP3_STCPR 44
-#define OP3_STCSR 45
-#define OP3_STDCQ 46
-#define OP3_STDCPR 47
-#define OP3_CPOP1 54
-#define OP3_CPOP2 55
-
-#define COND_BN 0
-#define COND_BE 1
-#define COND_BLE 2
-#define COND_BL 3
-#define COND_BLEU 4
-#define COND_BCS 5
-#define COND_BNEG 6
-#define COND_BVS 7
-#define COND_BA 8
-#define COND_BNE 9
-#define COND_BG 10
-#define COND_BGE 11
-#define COND_BGU 12
-#define COND_BCC 13
-#define COND_BPOS 14
-#define COND_BVC 15
-
-#define LDD (OP3 == OP3_LDD)
-#define LD (OP3 == OP3_LD)
-#define LDSH (OP3 == OP3_LDSH)
-#define LDUH (OP3 == OP3_LDUH)
-#define LDSB (OP3 == OP3_LDSB)
-#define LDUB (OP3 == OP3_LDUB)
-#define LDDF (OP3 == OP3_LDDFPR)
-#define LDF (OP3 == OP3_LDFPR)
-#define LDFSR (OP3 == OP3_LDFSR)
-#define LDDC (OP3 == OP3_LDDCPR)
-#define LDC (OP3 == OP3_LDCPR)
-#define LDCSR (OP3 == OP3_LDCSR)
-#define LDDA (OP3 == OP3_LDDA)
-#define LDA (OP3 == OP3_LDA)
-#define LDSHA (OP3 == OP3_LDSHA)
-#define LDUHA (OP3 == OP3_LDUHA)
-#define LDSBA (OP3 == OP3_LDSBA)
-#define LDUBA (OP3 == OP3_LDUBA)
-
-#define STD (OP3 == OP3_STD)
-#define ST (OP3 == OP3_ST)
-#define STH (OP3 == OP3_STH)
-#define STB (OP3 == OP3_STB)
-#define STDA (OP3 == OP3_STDA)
-#define STA (OP3 == OP3_STA)
-#define STHA (OP3 == OP3_STHA)
-#define STBA (OP3 == OP3_STBA)
-#define STF (OP3 == OP3_STFPR)
-#define STFSR (OP3 == OP3_STFSR)
-#define STDFQ (OP3 == OP3_STDFQ)
-#define STDF (OP3 == OP3_STDFPR)
-#define STC (OP3 == OP3_STCPR)
-#define STCSR (OP3 == OP3_STCSR)
-#define STDCQ (OP3 == OP3_STDCQ)
-#define STDC (OP3 == OP3_STDCPR)
-
-#define JMPL (OP3 == OP3_JMPL)
-#define TICC (OP3 == OP3_TICC)
-#define RETT (OP3 == OP3_RETT)
-
-#define SWAP (OP3 == OP3_SWAP)
-#define SWAPA (OP3 == OP3_SWAPA)
-
-#define FPOP1 (OP3 == OP3_FPOP1)
-#define FPOP2 (OP3 == OP3_FPOP2)
-#define CPOP1 (OP3 == OP3_CPOP1)
-#define CPOP2 (OP3 == OP3_CPOP2)
-
-#define LDSTUB (OP3 == OP3_LDSTUB)
-#define LDSTUBA (OP3 == OP3_LDSTUBA)
-
-#define ADD (OP3 == OP3_ADD)
-#define ADDX (OP3 == OP3_ADDX)
-#define ADDCC (OP3 == OP3_ADDCC)
-#define ADDXCC (OP3 == OP3_ADDXCC)
-
-#define SUB (OP3 == OP3_SUB)
-#define SUBX (OP3 == OP3_SUBX)
-#define SUBCC (OP3 == OP3_SUBCC)
-#define SUBXCC (OP3 == OP3_SUBXCC)
-
-#define TADDCCTV (OP3 == OP3_TADDCCTV)
-#define TSUBCCTV (OP3 == OP3_TSUBCCTV)
-
-#define AND (OP3 == OP3_AND)
-#define OR (OP3 == OP3_OR)
-#define XOR (OP3 == OP3_XOR)
-#define ANDN (OP3 == OP3_ANDN)
-#define ORN (OP3 == OP3_ORN)
-#define XNOR (OP3 == OP3_XNOR)
-#define ANDCC (OP3 == OP3_ANDCC)
-#define ORCC (OP3 == OP3_ORCC)
-#define XORCC (OP3 == OP3_XORCC)
-#define ANDNCC (OP3 == OP3_ANDNCC)
-#define ORNCC (OP3 == OP3_ORNCC)
-#define XNORCC (OP3 == OP3_XNORCC)
-
-#define SLL (OP3 == OP3_SLL)
-#define SRL (OP3 == OP3_SRL)
-#define SRA (OP3 == OP3_SRA)
-
-#define RDASR (OP3 == OP3_RDASR)
-#define RDPSR (OP3 == OP3_RDPSR)
-#define RDWIM (OP3 == OP3_RDWIM)
-#define RDTBR (OP3 == OP3_RDTBR)
-
-#define WRASR (OP3 == OP3_WRASR)
-#define WRPSR (OP3 == OP3_WRPSR)
-#define WRWIM (OP3 == OP3_WRWIM)
-#define WRTBR (OP3 == OP3_WRTBR)
-
-#define SAVE (OP3 == OP3_SAVE)
-#define RESTORE (OP3 == OP3_RESTORE)
-
-#define UMUL (OP3 == OP3_UMUL)
-#define UMULCC (OP3 == OP3_UMULCC)
-#define SMUL (OP3 == OP3_SMUL)
-#define SMULCC (OP3 == OP3_SMULCC)
-
-#define UDIV (OP3 == OP3_UDIV)
-#define UDIVCC (OP3 == OP3_UDIVCC)
-#define SDIV (OP3 == OP3_SDIV)
-#define SDIVCC (OP3 == OP3_SDIVCC)
-
-#endif // __MB86901_DEFS_H__ \ No newline at end of file
+#define USEIMM ((op >> 13) & 1)
+#define USEEXT ((op >> 12) & 1)
+
+
+#define COND ((op >> 25) & 15)
+#define RCOND ((op >> 10) & 7)
+#define MOVCOND ((op >> 14) & 15)
+#define PRED ((op >> 19) & 1)
+#define ANNUL ((op >> 29) & 1)
+#define BRCC ((op >> 20) & 3)
+#define MOVCC (((op >> 11) & 3) | ((op >> 16) & 4))
+#define OPFCC ((op >> 11) & 7)
+#define TCCCC ((op >> 11) & 3)
+#define ASI ((op >> 5) & 255)
+#define MMASK (op & 15)
+#define CMASK ((op >> 4) & 7)
+
+#define RD ((op >> 25) & 31)
+#define RS1 ((op >> 14) & 31)
+#define RS2 (op & 31)
+
+#define FREG(x) m_fpr[(x)]
+#define FDREG m_fpr[RD]
+#define FSR m_fsr
+
+#define REG(x) *m_regs[(x)]
+#define RDREG *m_regs[RD]
+#define RS1REG *m_regs[RS1]
+#define RS2REG *m_regs[RS2]
+#define SET_RDREG(x) do { if(RD) { RDREG = (x); } } while (0)
+#define ADDRESS (USEIMM ? (RS1REG + SIMM13) : (RS1REG + RS2REG))
+
+#define PC m_pc
+#define nPC m_npc
+
+#define Y m_y
+
+#define ET m_et
+#define EF m_ef
+#define EC m_ec
+#define PIL m_pil
+
+#define MAE m_mae
+#define HOLD_BUS m_hold_bus
+
+#define BIT31(x) ((x) & 0x80000000)
+
+#define UPDATE_PC true
+#define PC_UPDATED false
+
+#define OP_TYPE0 0
+#define OP_CALL 1
+#define OP_ALU 2
+#define OP_LDST 3
+
+#define OP2_UNIMP 0
+#define OP2_BICC 2
+#define OP2_SETHI 4
+#define OP2_FBFCC 6
+#define OP2_CBCCC 7
+
+#define OP3_ADD 0
+#define OP3_AND 1
+#define OP3_OR 2
+#define OP3_XOR 3
+#define OP3_SUB 4
+#define OP3_ANDN 5
+#define OP3_ORN 6
+#define OP3_XNOR 7
+#define OP3_ADDX 8
+#define OP3_UMUL 10
+#define OP3_SMUL 11
+#define OP3_SUBX 12
+#define OP3_UDIV 14
+#define OP3_SDIV 15
+#define OP3_ADDCC 16
+#define OP3_ANDCC 17
+#define OP3_ORCC 18
+#define OP3_XORCC 19
+#define OP3_SUBCC 20
+#define OP3_ANDNCC 21
+#define OP3_ORNCC 22
+#define OP3_XNORCC 23
+#define OP3_ADDXCC 24
+#define OP3_UMULCC 26
+#define OP3_SMULCC 27
+#define OP3_SUBXCC 28
+#define OP3_UDIVCC 30
+#define OP3_SDIVCC 31
+#define OP3_TADDCC 32
+#define OP3_TSUBCC 33
+#define OP3_TADDCCTV 34
+#define OP3_TSUBCCTV 35
+#define OP3_MULSCC 36
+#define OP3_SLL 37
+#define OP3_SRL 38
+#define OP3_SRA 39
+#define OP3_RDASR 40
+#define OP3_RDPSR 41
+#define OP3_RDWIM 42
+#define OP3_RDTBR 43
+#define OP3_WRASR 48
+#define OP3_WRPSR 49
+#define OP3_WRWIM 50
+#define OP3_WRTBR 51
+#define OP3_FPOP1 52
+#define OP3_FPOP2 53
+#define OP3_JMPL 56
+#define OP3_RETT 57
+#define OP3_TICC 58
+#define OP3_SAVE 60
+#define OP3_RESTORE 61
+
+#define OP3_LD 0
+#define OP3_LDUB 1
+#define OP3_LDUH 2
+#define OP3_LDD 3
+#define OP3_ST 4
+#define OP3_STB 5
+#define OP3_STH 6
+#define OP3_STD 7
+#define OP3_LDSB 9
+#define OP3_LDSH 10
+#define OP3_LDSTUB 13
+#define OP3_SWAP 15
+#define OP3_LDA 16
+#define OP3_LDUBA 17
+#define OP3_LDUHA 18
+#define OP3_LDDA 19
+#define OP3_STA 20
+#define OP3_STBA 21
+#define OP3_STHA 22
+#define OP3_STDA 23
+#define OP3_LDSBA 25
+#define OP3_LDSHA 26
+#define OP3_LDSTUBA 29
+#define OP3_SWAPA 31
+#define OP3_LDFPR 32
+#define OP3_LDFSR 33
+#define OP3_LDDFPR 35
+#define OP3_STFPR 36
+#define OP3_STFSR 37
+#define OP3_STDFQ 38
+#define OP3_STDFPR 39
+#define OP3_LDCPR 40
+#define OP3_LDCSR 41
+#define OP3_LDDCPR 43
+#define OP3_STCPR 44
+#define OP3_STCSR 45
+#define OP3_STDCQ 46
+#define OP3_STDCPR 47
+#define OP3_CPOP1 54
+#define OP3_CPOP2 55
+
+#define COND_BN 0
+#define COND_BE 1
+#define COND_BLE 2
+#define COND_BL 3
+#define COND_BLEU 4
+#define COND_BCS 5
+#define COND_BNEG 6
+#define COND_BVS 7
+#define COND_BA 8
+#define COND_BNE 9
+#define COND_BG 10
+#define COND_BGE 11
+#define COND_BGU 12
+#define COND_BCC 13
+#define COND_BPOS 14
+#define COND_BVC 15
+
+#define LDD (OP3 == OP3_LDD)
+#define LD (OP3 == OP3_LD)
+#define LDSH (OP3 == OP3_LDSH)
+#define LDUH (OP3 == OP3_LDUH)
+#define LDSB (OP3 == OP3_LDSB)
+#define LDUB (OP3 == OP3_LDUB)
+#define LDDF (OP3 == OP3_LDDFPR)
+#define LDF (OP3 == OP3_LDFPR)
+#define LDFSR (OP3 == OP3_LDFSR)
+#define LDDC (OP3 == OP3_LDDCPR)
+#define LDC (OP3 == OP3_LDCPR)
+#define LDCSR (OP3 == OP3_LDCSR)
+#define LDDA (OP3 == OP3_LDDA)
+#define LDA (OP3 == OP3_LDA)
+#define LDSHA (OP3 == OP3_LDSHA)
+#define LDUHA (OP3 == OP3_LDUHA)
+#define LDSBA (OP3 == OP3_LDSBA)
+#define LDUBA (OP3 == OP3_LDUBA)
+
+#define STD (OP3 == OP3_STD)
+#define ST (OP3 == OP3_ST)
+#define STH (OP3 == OP3_STH)
+#define STB (OP3 == OP3_STB)
+#define STDA (OP3 == OP3_STDA)
+#define STA (OP3 == OP3_STA)
+#define STHA (OP3 == OP3_STHA)
+#define STBA (OP3 == OP3_STBA)
+#define STF (OP3 == OP3_STFPR)
+#define STFSR (OP3 == OP3_STFSR)
+#define STDFQ (OP3 == OP3_STDFQ)
+#define STDF (OP3 == OP3_STDFPR)
+#define STC (OP3 == OP3_STCPR)
+#define STCSR (OP3 == OP3_STCSR)
+#define STDCQ (OP3 == OP3_STDCQ)
+#define STDC (OP3 == OP3_STDCPR)
+
+#define JMPL (OP3 == OP3_JMPL)
+#define TICC (OP3 == OP3_TICC)
+#define RETT (OP3 == OP3_RETT)
+
+#define SWAP (OP3 == OP3_SWAP)
+#define SWAPA (OP3 == OP3_SWAPA)
+
+#define FPOP1 (OP3 == OP3_FPOP1)
+#define FPOP2 (OP3 == OP3_FPOP2)
+#define CPOP1 (OP3 == OP3_CPOP1)
+#define CPOP2 (OP3 == OP3_CPOP2)
+
+#define LDSTUB (OP3 == OP3_LDSTUB)
+#define LDSTUBA (OP3 == OP3_LDSTUBA)
+
+#define ADD (OP3 == OP3_ADD)
+#define ADDX (OP3 == OP3_ADDX)
+#define ADDCC (OP3 == OP3_ADDCC)
+#define ADDXCC (OP3 == OP3_ADDXCC)
+
+#define SUB (OP3 == OP3_SUB)
+#define SUBX (OP3 == OP3_SUBX)
+#define SUBCC (OP3 == OP3_SUBCC)
+#define SUBXCC (OP3 == OP3_SUBXCC)
+
+#define TADDCCTV (OP3 == OP3_TADDCCTV)
+#define TSUBCCTV (OP3 == OP3_TSUBCCTV)
+
+#define AND (OP3 == OP3_AND)
+#define OR (OP3 == OP3_OR)
+#define XOR (OP3 == OP3_XOR)
+#define ANDN (OP3 == OP3_ANDN)
+#define ORN (OP3 == OP3_ORN)
+#define XNOR (OP3 == OP3_XNOR)
+#define ANDCC (OP3 == OP3_ANDCC)
+#define ORCC (OP3 == OP3_ORCC)
+#define XORCC (OP3 == OP3_XORCC)
+#define ANDNCC (OP3 == OP3_ANDNCC)
+#define ORNCC (OP3 == OP3_ORNCC)
+#define XNORCC (OP3 == OP3_XNORCC)
+
+#define SLL (OP3 == OP3_SLL)
+#define SRL (OP3 == OP3_SRL)
+#define SRA (OP3 == OP3_SRA)
+
+#define RDASR (OP3 == OP3_RDASR)
+#define RDPSR (OP3 == OP3_RDPSR)
+#define RDWIM (OP3 == OP3_RDWIM)
+#define RDTBR (OP3 == OP3_RDTBR)
+
+#define WRASR (OP3 == OP3_WRASR)
+#define WRPSR (OP3 == OP3_WRPSR)
+#define WRWIM (OP3 == OP3_WRWIM)
+#define WRTBR (OP3 == OP3_WRTBR)
+
+#define SAVE (OP3 == OP3_SAVE)
+#define RESTORE (OP3 == OP3_RESTORE)
+
+#define UMUL (OP3 == OP3_UMUL)
+#define UMULCC (OP3 == OP3_UMULCC)
+#define SMUL (OP3 == OP3_SMUL)
+#define SMULCC (OP3 == OP3_SMULCC)
+
+#define UDIV (OP3 == OP3_UDIV)
+#define UDIVCC (OP3 == OP3_UDIVCC)
+#define SDIV (OP3 == OP3_SDIV)
+#define SDIVCC (OP3 == OP3_SDIVCC)
+
+#endif // __MB86901_DEFS_H__
diff --git a/src/devices/cpu/tms32010/tms32010.h b/src/devices/cpu/tms32010/tms32010.h
index 61e36279e17..d595b073997 100644
--- a/src/devices/cpu/tms32010/tms32010.h
+++ b/src/devices/cpu/tms32010/tms32010.h
@@ -45,7 +45,7 @@ public:
// construction/destruction
tms32010_device(const machine_config &mconfig, const char *tag, device_t *owner, UINT32 clock);
tms32010_device(const machine_config &mconfig, device_type type, const char *name, const char *tag, device_t *owner, UINT32 clock, const char *shortname, const char *source, int addr_mask);
-
+
// static configuration helpers
template<class _Object> static devcb_base & set_bio_in_cb(device_t &device, _Object object) { return downcast<tms32010_device &>(device).m_bio_in.set_callback(object); }
@@ -78,7 +78,7 @@ private:
address_space_config m_program_config;
address_space_config m_data_config;
address_space_config m_io_config;
-
+
devcb_read_line m_bio_in;
typedef void ( tms32010_device::*opcode_func ) ();
diff --git a/src/devices/cpu/tms32025/tms32025.h b/src/devices/cpu/tms32025/tms32025.h
index 0d414c1cb4f..e112dafde51 100644
--- a/src/devices/cpu/tms32025/tms32025.h
+++ b/src/devices/cpu/tms32025/tms32025.h
@@ -31,7 +31,7 @@
#define MCFG_TMS32025_HOLD_ACK_OUT_CB(_devcb) \
devcb = &tms32025_device::set_hold_ack_out_cb(*device, DEVCB_##_devcb); /* HOLD Acknowledge output */
-
+
#define MCFG_TMS32025_XF_OUT_CB(_devcb) \
devcb = &tms32025_device::set_xf_out_cb(*device, DEVCB_##_devcb); /* XF output */
@@ -41,7 +41,7 @@
#define MCFG_TMS32025_DX_OUT_CB(_devcb) \
devcb = &tms32025_device::set_dx_out_cb(*device, DEVCB_##_devcb); /* Serial Data Transmit output */
-
+
/****************************************************************************
* Interrupt constants
*/
@@ -83,7 +83,7 @@ public:
// construction/destruction
tms32025_device(const machine_config &mconfig, const char *tag, device_t *owner, UINT32 clock);
tms32025_device(const machine_config &mconfig, device_type type, const char *name, const char *tag, device_t *owner, UINT32 clock, const char *shortname, const char *source);
-
+
// static configuration helpers
template<class _Object> static devcb_base & set_bio_in_cb(device_t &device, _Object object) { return downcast<tms32025_device &>(device).m_bio_in.set_callback(object); }
template<class _Object> static devcb_base & set_hold_in_cb(device_t &device, _Object object) { return downcast<tms32025_device &>(device).m_hold_in.set_callback(object); }
diff --git a/src/devices/imagedev/cassette.cpp b/src/devices/imagedev/cassette.cpp
index 5826f0abf58..313ef6b42a2 100644
--- a/src/devices/imagedev/cassette.cpp
+++ b/src/devices/imagedev/cassette.cpp
@@ -359,7 +359,7 @@ void cassette_image_device::call_unload()
//-------------------------------------------------
// display a small tape animation, with the
-// current position in the tape image
+// current position in the tape image
//-------------------------------------------------
std::string cassette_image_device::call_display()
@@ -389,10 +389,10 @@ std::string cassette_image_device::call_display()
? u8"\u25BA"
: u8"\u25CF";
- // Since you can have anything in a BDF file, we will use crude ascii characters instead
+ // Since you can have anything in a BDF file, we will use crude ascii characters instead
result = string_format("%s %s %02d:%02d (%04d) [%02d:%02d (%04d)]",
- shapes[n], // animation
- status_icon, // play or record
+ shapes[n], // animation
+ status_icon, // play or record
((int)position / 60),
((int)position % 60),
(int)position,
diff --git a/src/devices/machine/68230pit.cpp b/src/devices/machine/68230pit.cpp
index fe84888ffbf..ed9cfee7327 100644
--- a/src/devices/machine/68230pit.cpp
+++ b/src/devices/machine/68230pit.cpp
@@ -46,7 +46,7 @@ const device_type PIT68230 = &device_creator<pit68230_device>;
//-------------------------------------------------
pit68230_device::pit68230_device(const machine_config &mconfig, device_type type, const char *name, const char *tag, device_t *owner, UINT32 clock, UINT32 variant, const char *shortname, const char *source)
: device_t (mconfig, type, name, tag, owner, clock, shortname, source),
- device_execute_interface (mconfig, *this)
+ device_execute_interface (mconfig, *this)
, m_icount (0)
, m_pa_out_cb(*this)
, m_pa_in_cb(*this)
@@ -70,9 +70,9 @@ pit68230_device::pit68230_device(const machine_config &mconfig, device_type type
, m_psr(0)
, m_tcr(0)
, m_cpr(0)
- // , m_cprh(0)
- // , m_cprm(0)
- // , m_cprl(0)
+ // , m_cprh(0)
+ // , m_cprm(0)
+ // , m_cprl(0)
, m_cntr(0)
{
}
@@ -80,7 +80,7 @@ pit68230_device::pit68230_device(const machine_config &mconfig, device_type type
pit68230_device::pit68230_device(const machine_config &mconfig, const char *tag, device_t *owner, UINT32 clock)
: device_t (mconfig, PIT68230, "PIT68230", tag, owner, clock, "pit68230", __FILE__),
- device_execute_interface (mconfig, *this)
+ device_execute_interface (mconfig, *this)
, m_icount (0)
, m_pa_out_cb (*this)
, m_pa_in_cb(*this)
@@ -104,9 +104,9 @@ pit68230_device::pit68230_device(const machine_config &mconfig, const char *tag,
, m_psr(0)
, m_tcr(0)
, m_cpr(0)
- // , m_cprh(0)
- // , m_cprm(0)
- // , m_cprl(0)
+ // , m_cprh(0)
+ // , m_cprm(0)
+ // , m_cprl(0)
, m_cntr(0)
{
}
@@ -263,70 +263,70 @@ void pit68230_device::wr_pitreg_psr(UINT8 data)
/* The timer control register (TCR) determines all operations of the timer. Bits 7-5 configure the PC3/TOUT
and PC7/TIACKpins for port C, square wave, vectored interrupt, or autovectored interrupt operation bit
-4 specifies whether the counter receives data from the counter preload register or continues counting when
-zero detect is reached ; bit 3 is unused and is read as zero bits 2 and 1 configure the path from the CLK
-and TINpins to the counter controller ; and bit 0 ena-bles the timer. This register is readable and writable
-at all times. All bits are cleared to zero when the RESET pin is asserted.
+4 specifies whether the counter receives data from the counter preload register or continues counting when
+zero detect is reached ; bit 3 is unused and is read as zero bits 2 and 1 configure the path from the CLK
+and TINpins to the counter controller ; and bit 0 ena-bles the timer. This register is readable and writable
+at all times. All bits are cleared to zero when the RESET pin is asserted.
TCR bits
7 6 5 TOUT/TIACK Control
----------------------------
- 0 0 X The dual-function pins PC3/TOUT and PC7/TIACK carry the port C function.
- 0 1 X The dual-function pinPC3/TOUT carries the TOUT function. In the run state it is used as a squarewave
- output and is toggled on zero detect. The TOUT pin is high while in the halt state. The dualfunction
- pin PC7/TIACK carries the PC7 function.
- 1 0 0 The dual-function pin PC3/TOUT carries the TOUT function. In the run or halt state it is used as
- a timer interrupt request output. The timer interrupt is disabled, thus, the pin is always three stated.
- The dual-function pin PC7/TIACK carries the TIACK function ; however, since interrupt request is
- negated, the PI/T produces no response (i.e., no data or DTACK) to an asserted TIACK. Refer to
- 5.1.3. Timer Interrupt Acknowledge Cycles for details.
- 1 0 1 The dual-function pin PC3/TOUT carries the TOUTfunction and is used as a timer interrupt request
- output. The timer interrupt is enabled ; thus, the pin is low when the timer ZDS status bit is one.
- The dual-function pin PC7/TIACK carries the TIACK function and is used as a timer interrupt acknowledge
- input. Refer to the5.1.3. Timer InterruptAcknowledge Cycles fordetails. Thiscombination
- supports vectored timer interrupts.
- 1 1 0 The dual-function pin PC3/TOUT function. In the run or halt state it is used as a timer interrupt
- request output. The timer interrupt is disabled ; thus, the pin is always three-stated. The dual-function
- pin PC7/TIACK carries the PC7 function.
- 1 1 1 The dual-function pin PC3/TOUT carries the TOUTfunction and is used as a timer interrupt request
- output. The timer interrupt is enabled ; thus, the pin is low when the timer ZDS status bit is one.
- The dual-function pin PC7/TIACK carries the PC7 function and autovectored interrupts are supported.
+ 0 0 X The dual-function pins PC3/TOUT and PC7/TIACK carry the port C function.
+ 0 1 X The dual-function pinPC3/TOUT carries the TOUT function. In the run state it is used as a squarewave
+ output and is toggled on zero detect. The TOUT pin is high while in the halt state. The dualfunction
+ pin PC7/TIACK carries the PC7 function.
+ 1 0 0 The dual-function pin PC3/TOUT carries the TOUT function. In the run or halt state it is used as
+ a timer interrupt request output. The timer interrupt is disabled, thus, the pin is always three stated.
+ The dual-function pin PC7/TIACK carries the TIACK function ; however, since interrupt request is
+ negated, the PI/T produces no response (i.e., no data or DTACK) to an asserted TIACK. Refer to
+ 5.1.3. Timer Interrupt Acknowledge Cycles for details.
+ 1 0 1 The dual-function pin PC3/TOUT carries the TOUTfunction and is used as a timer interrupt request
+ output. The timer interrupt is enabled ; thus, the pin is low when the timer ZDS status bit is one.
+ The dual-function pin PC7/TIACK carries the TIACK function and is used as a timer interrupt acknowledge
+ input. Refer to the5.1.3. Timer InterruptAcknowledge Cycles fordetails. Thiscombination
+ supports vectored timer interrupts.
+ 1 1 0 The dual-function pin PC3/TOUT function. In the run or halt state it is used as a timer interrupt
+ request output. The timer interrupt is disabled ; thus, the pin is always three-stated. The dual-function
+ pin PC7/TIACK carries the PC7 function.
+ 1 1 1 The dual-function pin PC3/TOUT carries the TOUTfunction and is used as a timer interrupt request
+ output. The timer interrupt is enabled ; thus, the pin is low when the timer ZDS status bit is one.
+ The dual-function pin PC7/TIACK carries the PC7 function and autovectored interrupts are supported.
TCR bit 4 - Zero Detect Control
- 0 The counter is loaded fromthe counter preload register on the first clock to the 24-bit counter after
- zero detect, then resumes counting.
- 1 The counter rolls over on zero detect, then continues counting.
+ 0 The counter is loaded fromthe counter preload register on the first clock to the 24-bit counter after
+ zero detect, then resumes counting.
+ 1 The counter rolls over on zero detect, then continues counting.
TCR bit 3 - Unused and is always read as zero.
TCR bits
2 1 Clock Control
0 0 The PC2/TIN input pin carries the port C function, and the CLK pin and prescaler are used. The
- prescaler is decremented on the falling transition of the CLKpin ; the 24-bit counter is decremented,
- rolls over, or is loaded from the counter preload registers when the prescaler rolls over from $OO
- to $1F. The timer enable bit determines whether the timer is in the run or halt state.
- 0 1 The PC2/TIN pin serves as a timer input, and the CLK pin and prescaler are used. The prescaler
- is decremented on the falling transition of the CLK pin ; the 24-bit counter is decremented, rolls
- over, or is loaded from the counter preload registers when the prescaler rolls over from $00 to $1F.
- The timer is in the run state when the timer enable bit is one and the TIN pin is high ; otherwise,
- the timer is in the halt state.
- 1 0 The PC2/TIN pin serves as a timer input and the prescaler is used. The prescaler is decremented
- following the rising transition of the TIN pin after being synchronized with the internal clock. The
- 24-bit counter is decremented, rolls over, or is loaded from the counter preload registers when the
- prescaler rolls over from $00 to $1F. The timer enable bit determines whether the timer is in the
- run or halt state.
- 1 1 The PC2/TIN pin serves as a timer input and the prescaler is not used. The 24-bit counter is decremented,
- rolls over, or is loaded from the counter preload registers following the rising edge of
- the TIN pin after being synchronized with the internal clock. The timer enable bit determines whether
- the timer is in the run or halt state.
+ prescaler is decremented on the falling transition of the CLKpin ; the 24-bit counter is decremented,
+ rolls over, or is loaded from the counter preload registers when the prescaler rolls over from $OO
+ to $1F. The timer enable bit determines whether the timer is in the run or halt state.
+ 0 1 The PC2/TIN pin serves as a timer input, and the CLK pin and prescaler are used. The prescaler
+ is decremented on the falling transition of the CLK pin ; the 24-bit counter is decremented, rolls
+ over, or is loaded from the counter preload registers when the prescaler rolls over from $00 to $1F.
+ The timer is in the run state when the timer enable bit is one and the TIN pin is high ; otherwise,
+ the timer is in the halt state.
+ 1 0 The PC2/TIN pin serves as a timer input and the prescaler is used. The prescaler is decremented
+ following the rising transition of the TIN pin after being synchronized with the internal clock. The
+ 24-bit counter is decremented, rolls over, or is loaded from the counter preload registers when the
+ prescaler rolls over from $00 to $1F. The timer enable bit determines whether the timer is in the
+ run or halt state.
+ 1 1 The PC2/TIN pin serves as a timer input and the prescaler is not used. The 24-bit counter is decremented,
+ rolls over, or is loaded from the counter preload registers following the rising edge of
+ the TIN pin after being synchronized with the internal clock. The timer enable bit determines whether
+ the timer is in the run or halt state.
TCR bit 0 - Timer Enable
- 0 Disabled
- 1 Enabled
+ 0 Disabled
+ 1 Enabled
*/
void pit68230_device::wr_pitreg_tcr(UINT8 data)
{
- LOG(("%s(%02x) \"%s\": %s - %02x Timer %s\n",
- FUNCNAME, data, m_owner->tag(), FUNCNAME, data, data & REG_TCR_ENABLE ? "enabled" : "disabled"));
+ LOG(("%s(%02x) \"%s\": %s - %02x Timer %s\n",
+ FUNCNAME, data, m_owner->tag(), FUNCNAME, data, data & REG_TCR_ENABLE ? "enabled" : "disabled"));
m_tcr = data;
}
@@ -335,7 +335,7 @@ void pit68230_device::wr_pitreg_cprh(UINT8 data)
LOG(("%s(%02x) \"%s\": %s - %02x\n", FUNCNAME, data, m_owner->tag(), FUNCNAME, data));
m_cpr &= ~0xff0000;
m_cpr |= ((data << 16) & 0xff0000);
- // m_cprh = data;
+ // m_cprh = data;
}
void pit68230_device::wr_pitreg_cprm(UINT8 data)
@@ -343,7 +343,7 @@ void pit68230_device::wr_pitreg_cprm(UINT8 data)
LOG(("%s(%02x) \"%s\": %s - %02x\n", FUNCNAME, data, m_owner->tag(), FUNCNAME, data));
m_cpr &= ~0x00ff00;
m_cpr |= ((data << 8) & 0x00ff00);
- // m_cprm = data;
+ // m_cprm = data;
}
void pit68230_device::wr_pitreg_cprl(UINT8 data)
@@ -351,28 +351,28 @@ void pit68230_device::wr_pitreg_cprl(UINT8 data)
LOG(("%s(%02x) \"%s\": %s - %02x\n", FUNCNAME, data, m_owner->tag(), FUNCNAME, data));
m_cpr &= ~0x0000ff;
m_cpr |= ((data << 0) & 0x0000ff);
- // m_cprl = data;
+ // m_cprl = data;
}
WRITE8_MEMBER (pit68230_device::write)
{
LOG(("%s %s \n",tag(), FUNCNAME));
switch (offset) {
- case PIT_68230_PGCR: wr_pitreg_pgcr(data); break;
- case PIT_68230_PSRR: wr_pitreg_psrr(data); break;
- case PIT_68230_PADDR: wr_pitreg_paddr(data); break;
- case PIT_68230_PBDDR: wr_pitreg_pbddr(data); break;
- case PIT_68230_PCDDR: wr_pitreg_pcddr(data); break;
- case PIT_68230_PACR: wr_pitreg_pacr(data); break;
- case PIT_68230_PBCR: wr_pitreg_pbcr(data); break;
- case PIT_68230_PADR: wr_pitreg_padr(data); break;
- case PIT_68230_PAAR: break; // RO register so ignored
- case PIT_68230_PBAR: break; // RO register so ignored
- case PIT_68230_PSR: wr_pitreg_psr(data); break;
- case PIT_68230_TCR: wr_pitreg_tcr(data); break;
- case PIT_68230_CPRH: wr_pitreg_cprh(data); break;
- case PIT_68230_CPRM: wr_pitreg_cprm(data); break;
- case PIT_68230_CPRL: wr_pitreg_cprl(data); break;
+ case PIT_68230_PGCR: wr_pitreg_pgcr(data); break;
+ case PIT_68230_PSRR: wr_pitreg_psrr(data); break;
+ case PIT_68230_PADDR: wr_pitreg_paddr(data); break;
+ case PIT_68230_PBDDR: wr_pitreg_pbddr(data); break;
+ case PIT_68230_PCDDR: wr_pitreg_pcddr(data); break;
+ case PIT_68230_PACR: wr_pitreg_pacr(data); break;
+ case PIT_68230_PBCR: wr_pitreg_pbcr(data); break;
+ case PIT_68230_PADR: wr_pitreg_padr(data); break;
+ case PIT_68230_PAAR: break; // RO register so ignored
+ case PIT_68230_PBAR: break; // RO register so ignored
+ case PIT_68230_PSR: wr_pitreg_psr(data); break;
+ case PIT_68230_TCR: wr_pitreg_tcr(data); break;
+ case PIT_68230_CPRH: wr_pitreg_cprh(data); break;
+ case PIT_68230_CPRM: wr_pitreg_cprm(data); break;
+ case PIT_68230_CPRL: wr_pitreg_cprl(data); break;
default:
LOG (("Unhandled Write of %02x to register %02x", data, offset));
}
@@ -458,22 +458,22 @@ UINT8 pit68230_device::rr_pitreg_pbdr()
return m_pbdr;
}
-/* The port A alternate register is an alternate register for reading the port A pins.
+/* The port A alternate register is an alternate register for reading the port A pins.
It is a read-only address and no other PI/T condition is affected. In all modes,
-the instantaneous pin level is read and no input latching is performed except at the
+the instantaneous pin level is read and no input latching is performed except at the
data bus interface. Writes to this address are answered with DTACK, but the data is ignored.*/
UINT8 pit68230_device::rr_pitreg_paar()
{
- // NOTE: no side effect emulated so using ..padr
+ // NOTE: no side effect emulated so using ..padr
UINT8 ret;
ret = m_pa_in_cb();
LOGR(("%s %s <- %02x\n",tag(), FUNCNAME, ret));
return ret;
}
-/* The port B alternate register is an alternate register for reading the port B pins.
+/* The port B alternate register is an alternate register for reading the port B pins.
It is a read-only address and no other PI/T condition is affected. In all modes,
-the instantaneous pin level is read and no input latching is performed except at the
+the instantaneous pin level is read and no input latching is performed except at the
data bus interface.Writes to this address are answered with DTACK, but the data is ignored.*/
UINT8 pit68230_device::rr_pitreg_pbar()
{
@@ -518,21 +518,21 @@ READ8_MEMBER (pit68230_device::read){
UINT8 data;
switch (offset) {
- case PIT_68230_PGCR: data = rr_pitreg_pgcr(); break;
- case PIT_68230_PSRR: data = rr_pitreg_psrr(); break;
- case PIT_68230_PADDR: data = rr_pitreg_paddr(); break;
- case PIT_68230_PBDDR: data = rr_pitreg_pbddr(); break;
- case PIT_68230_PCDDR: data = rr_pitreg_pcddr(); break;
- case PIT_68230_PACR: data = rr_pitreg_pacr(); break;
- case PIT_68230_PBCR: data = rr_pitreg_pbcr(); break;
- case PIT_68230_PADR: data = rr_pitreg_padr(); break;
- case PIT_68230_PBDR: data = rr_pitreg_pbdr(); break;
- case PIT_68230_PAAR: data = rr_pitreg_paar(); break;
- case PIT_68230_PBAR: data = rr_pitreg_pbar(); break;
- case PIT_68230_PSR: data = rr_pitreg_psr(); break;
- case PIT_68230_CNTRH: data = rr_pitreg_cntrh(); break;
- case PIT_68230_CNTRM: data = rr_pitreg_cntrm(); break;
- case PIT_68230_CNTRL: data = rr_pitreg_cntrl(); break;
+ case PIT_68230_PGCR: data = rr_pitreg_pgcr(); break;
+ case PIT_68230_PSRR: data = rr_pitreg_psrr(); break;
+ case PIT_68230_PADDR: data = rr_pitreg_paddr(); break;
+ case PIT_68230_PBDDR: data = rr_pitreg_pbddr(); break;
+ case PIT_68230_PCDDR: data = rr_pitreg_pcddr(); break;
+ case PIT_68230_PACR: data = rr_pitreg_pacr(); break;
+ case PIT_68230_PBCR: data = rr_pitreg_pbcr(); break;
+ case PIT_68230_PADR: data = rr_pitreg_padr(); break;
+ case PIT_68230_PBDR: data = rr_pitreg_pbdr(); break;
+ case PIT_68230_PAAR: data = rr_pitreg_paar(); break;
+ case PIT_68230_PBAR: data = rr_pitreg_pbar(); break;
+ case PIT_68230_PSR: data = rr_pitreg_psr(); break;
+ case PIT_68230_CNTRH: data = rr_pitreg_cntrh(); break;
+ case PIT_68230_CNTRM: data = rr_pitreg_cntrm(); break;
+ case PIT_68230_CNTRL: data = rr_pitreg_cntrl(); break;
default:
LOG (("Unhandled read register %02x\n", offset));
data = 0;
diff --git a/src/devices/machine/68230pit.h b/src/devices/machine/68230pit.h
index 7712419f7fc..736868afa66 100644
--- a/src/devices/machine/68230pit.h
+++ b/src/devices/machine/68230pit.h
@@ -105,7 +105,7 @@
//**************************************************************************
class pit68230_device : public device_t, public device_execute_interface
{
- public:
+ public:
// construction/destruction
pit68230_device(const machine_config &mconfig, device_type type, const char *name, const char *tag, device_t *owner, UINT32 clock, UINT32 variant, const char *shortname, const char *source);
pit68230_device(const machine_config &mconfig, const char *tag, device_t *owner, UINT32 clock);
@@ -161,7 +161,7 @@ class pit68230_device : public device_t, public device_execute_interface
protected:
enum {
- REG_TCR_ENABLE = 0x01
+ REG_TCR_ENABLE = 0x01
};
// device-level overrides
@@ -171,16 +171,16 @@ protected:
virtual void execute_run () override;
int m_icount;
- devcb_write8 m_pa_out_cb;
- devcb_read8 m_pa_in_cb;
- devcb_write8 m_pb_out_cb;
- devcb_read8 m_pb_in_cb;
- devcb_write8 m_pc_out_cb;
- devcb_read8 m_pc_in_cb;
- devcb_write_line m_h1_out_cb;
- devcb_write_line m_h2_out_cb;
- devcb_write_line m_h3_out_cb;
- devcb_write_line m_h4_out_cb;
+ devcb_write8 m_pa_out_cb;
+ devcb_read8 m_pa_in_cb;
+ devcb_write8 m_pb_out_cb;
+ devcb_read8 m_pb_in_cb;
+ devcb_write8 m_pc_out_cb;
+ devcb_read8 m_pc_in_cb;
+ devcb_write_line m_h1_out_cb;
+ devcb_write_line m_h2_out_cb;
+ devcb_write_line m_h3_out_cb;
+ devcb_write_line m_h4_out_cb;
// peripheral ports
UINT8 m_pgcr; // Port General Control register
@@ -193,12 +193,12 @@ protected:
UINT8 m_padr; // Port A Data register
UINT8 m_pbdr; // Port B Data register
UINT8 m_psr; // Port Status Register
- UINT8 m_tcr; // Timer Control Register
- int m_cpr; // Counter Preload Registers (3 x 8 = 24 bits)
- // UINT8 m_cprh; // Counter Preload Register High
- // UINT8 m_cprm; // Counter Preload Register Mid
- // UINT8 m_cprl; // Counter Preload Register Low
- int m_cntr; // - The 24 bit Counter
+ UINT8 m_tcr; // Timer Control Register
+ int m_cpr; // Counter Preload Registers (3 x 8 = 24 bits)
+ // UINT8 m_cprh; // Counter Preload Register High
+ // UINT8 m_cprm; // Counter Preload Register Mid
+ // UINT8 m_cprl; // Counter Preload Register Low
+ int m_cntr; // - The 24 bit Counter
};
// device type definition
diff --git a/src/devices/machine/8530scc.cpp b/src/devices/machine/8530scc.cpp
index be3bbf6ed6d..bf1c5e09203 100644
--- a/src/devices/machine/8530scc.cpp
+++ b/src/devices/machine/8530scc.cpp
@@ -480,8 +480,8 @@ UINT8 scc8530_t::read_reg(int offset)
switch(offset)
{
- case 0: /* Channel B (Printer Port) Control */
- case 1: /* Channel A (Modem Port) Control */
+ case 0: /* Channel B (Printer Port) Control */
+ case 1: /* Channel A (Modem Port) Control */
if (mode == 1)
mode = 0;
@@ -491,7 +491,7 @@ UINT8 scc8530_t::read_reg(int offset)
result = (offset == 0) ? getbreg() : getareg();
break;
- case 2: /* Channel B (Printer Port) Data */
+ case 2: /* Channel B (Printer Port) Data */
case 3:/* Channel A (Modem Port) Data */
result = channel[offset == 2 ? 1 : 0].rxData;
break;
@@ -527,8 +527,8 @@ void scc8530_t::write_reg(int offset, UINT8 data)
//Chan *pChan;
switch(offset)
{
- case 0: /* Channel B (Printer Port) Control */
- case 1: /* Channel A (Modem Port) Control */
+ case 0: /* Channel B (Printer Port) Control */
+ case 1: /* Channel A (Modem Port) Control */
{
int chan = ((offset == 2) ? 1 : 0);
if (mode == 0)
@@ -537,7 +537,7 @@ void scc8530_t::write_reg(int offset, UINT8 data)
{
mode = 1;
reg = data & 0x0f;
-// putbreg(data & 0xf0);
+// putbreg(data & 0xf0);
}
else if (data == 0x10)
{
@@ -555,8 +555,8 @@ void scc8530_t::write_reg(int offset, UINT8 data)
break;
}
- case 2: /* Channel B (Printer Port) Data */
- case 3: /* Channel A (Modem Port) Data */
+ case 2: /* Channel B (Printer Port) Data */
+ case 3: /* Channel A (Modem Port) Data */
{
int chan = ((offset == 2) ? 1 : 0);
if (channel[chan].txEnable)
diff --git a/src/devices/machine/eeprom.h b/src/devices/machine/eeprom.h
index 02dd2eaf6de..7fdcc8cd473 100644
--- a/src/devices/machine/eeprom.h
+++ b/src/devices/machine/eeprom.h
@@ -44,7 +44,7 @@
// ======================> eeprom_base_device
class eeprom_base_device : public device_t,
- public device_nvram_interface
+ public device_nvram_interface
{
protected:
// construction/destruction
diff --git a/src/devices/machine/ldp1000.cpp b/src/devices/machine/ldp1000.cpp
index abfa23913b0..df211f56d5a 100644
--- a/src/devices/machine/ldp1000.cpp
+++ b/src/devices/machine/ldp1000.cpp
@@ -2,12 +2,12 @@
// copyright-holders:Angelo Salese
/***************************************************************************
- Sony LDP-1000 laserdisc emulation.
+ Sony LDP-1000 laserdisc emulation.
- TODO:
- - Dump BIOSes (seven of them according to docs);
- - Serial interface, needs BIOS dump;
- - Hookup with Sony SMC-70 / SMC-777;
+ TODO:
+ - Dump BIOSes (seven of them according to docs);
+ - Serial interface, needs BIOS dump;
+ - Hookup with Sony SMC-70 / SMC-777;
***************************************************************************/
@@ -71,7 +71,7 @@ void sony_ldp1000_device::device_start()
void sony_ldp1000_device::device_reset()
{
laserdisc_device::device_reset();
-
+
for(int i=0;i<0x10;i++)
m_internal_bcd[i] = 0;
@@ -152,12 +152,12 @@ UINT32 sony_ldp1000_device::bcd_to_raw()
void sony_ldp1000_device::exec_enter_cmd()
{
//const UINT32 saved_frame = bcd_to_raw();
-
+
switch(m_player_state)
{
case player_standby:
throw emu_fatalerror("Unimplemented standby state detected");
-
+
case player_search:
// TODO: move to timer
//advance_slider(1);
@@ -187,18 +187,18 @@ WRITE8_MEMBER( sony_ldp1000_device::command_w )
exec_enter_cmd();
m_status = stat_ack;
break;
-
+
case 0x43: // search
set_new_player_state(player_search);
m_status = stat_ack;
break;
-
+
/*
- audio channels absolute enable / disable
- ---- --x- select channel
- ---- ---x enable channel (active low)
+ audio channels absolute enable / disable
+ ---- --x- select channel
+ ---- ---x enable channel (active low)
*/
- case 0x46:
+ case 0x46:
case 0x47:
case 0x48:
case 0x49:
diff --git a/src/devices/machine/ldp1000.h b/src/devices/machine/ldp1000.h
index 142886da936..e759442fa57 100644
--- a/src/devices/machine/ldp1000.h
+++ b/src/devices/machine/ldp1000.h
@@ -2,7 +2,7 @@
// copyright-holders:Angelo Salese
/***************************************************************************
- Sony LDP-1000 laserdisc emulation.
+ Sony LDP-1000 laserdisc emulation.
***************************************************************************/
@@ -46,27 +46,27 @@ protected:
virtual void device_start() override;
virtual void device_reset() override;
virtual const rom_entry *device_rom_region() const override;
-
+
virtual void player_vsync(const vbi_metadata &vbi, int fieldnum, const attotime &curtime) override;
virtual INT32 player_update(const vbi_metadata &vbi, int fieldnum, const attotime &curtime) override;
virtual void player_overlay(bitmap_yuy16 &bitmap) override { }
enum ldp1000_status {
- stat_undef = 0x00,
- stat_completion = 0x01,
- stat_error = 0x02,
- stat_pgm_end = 0x04,
- stat_not_target = 0x05,
- stat_no_frame = 0x06,
- stat_ack = 0x0a,
- stat_nak = 0x0b
+ stat_undef = 0x00,
+ stat_completion = 0x01,
+ stat_error = 0x02,
+ stat_pgm_end = 0x04,
+ stat_not_target = 0x05,
+ stat_no_frame = 0x06,
+ stat_ack = 0x0a,
+ stat_nak = 0x0b
};
enum ldp1000_player_state {
player_standby = 0,
player_search
};
-
+
private:
UINT8 m_command;
ldp1000_status m_status;
@@ -79,7 +79,7 @@ private:
void exec_enter_cmd();
UINT8 m_internal_bcd[0x10];
UINT8 m_index_state;
-
+
};
diff --git a/src/devices/machine/ldv1000.cpp b/src/devices/machine/ldv1000.cpp
index 27c874eadf7..fb4cec974dd 100644
--- a/src/devices/machine/ldv1000.cpp
+++ b/src/devices/machine/ldv1000.cpp
@@ -176,7 +176,7 @@ void pioneer_ldv1000_device::device_start()
// allocate timers
m_multitimer = timer_alloc(TID_MULTIJUMP);
-
+
m_command_strobe_cb.resolve_safe();
}
@@ -653,7 +653,7 @@ WRITE8_MEMBER( pioneer_ldv1000_device::ppi1_portc_w )
// bit 4 sends a command strobe signal to Host CPU
m_command_strobe_cb(bool(data & 0x10));
-
+
// video squelch is controlled by bit 3
set_video_squelch((data & 0x08) == 0);
diff --git a/src/devices/machine/ldv1000.h b/src/devices/machine/ldv1000.h
index c7d798d89df..36f84f096a1 100644
--- a/src/devices/machine/ldv1000.h
+++ b/src/devices/machine/ldv1000.h
@@ -129,7 +129,7 @@ protected:
UINT8 m_vbi[7*3]; /* VBI data */
bool m_vbiready; /* VBI ready flag */
UINT8 m_vbiindex; /* index within the VBI data */
-
+
};
diff --git a/src/devices/machine/pci-ide.cpp b/src/devices/machine/pci-ide.cpp
index e6c18219e0d..0f3f6f8cbb6 100644
--- a/src/devices/machine/pci-ide.cpp
+++ b/src/devices/machine/pci-ide.cpp
@@ -132,7 +132,6 @@ WRITE_LINE_MEMBER(ide_pci_device::ide_interrupt)
// PCI646U2 Offset 0x50 is interrupt status
if (main_id == 0x10950646) {
-
if (state)
m_config_data[0x10 / 4] |= 0x4;
else
diff --git a/src/devices/machine/scnxx562.cpp b/src/devices/machine/scnxx562.cpp
index 099a8c6cdea..e4e388eade4 100644
--- a/src/devices/machine/scnxx562.cpp
+++ b/src/devices/machine/scnxx562.cpp
@@ -4,37 +4,37 @@
DUSCC Dual Serial Communications Controller emulation
The DUSCC was introduced in the mid 80:ies by Signetics, a part of Philips
- Semiconductor that later became NXP, and apparantly trying to dig into
+ Semiconductor that later became NXP, and apparantly trying to dig into
the huge success of the Zilog SCC with a very similar feature set but not
- software compatible at all.
+ software compatible at all.
The variants in the DUSCC family are as follows:
- Bus type
- Intel Motorola
+ Bus type
+ Intel Motorola
----------------------------------
- NMOS 26562 68562
- CMOS 26C562 68C562
+ NMOS 26562 68562
+ CMOS 26C562 68C562
----------------------------------
- For more info see:
+ For more info see:
page 511: http://bitsavers.informatik.uni-stuttgart.de/pdf/signetics/_dataBooks/1986_Signetics_Microprocessor.pdf
page 514: http://bitsavers.informatik.uni-stuttgart.de/pdf/signetics/_dataBooks/1994_Signetics_Data_Communications.pdf
Designs known of including one or more DUSCCs
------------------------------------------------
- Force Computers
+ Force Computers
CPU VME boards: CPU-22, CPU-26, CPU-30, CPU-33, CPU-386, CPU-40, CPU-41
- Graphics VME boards: AGC-1
+ Graphics VME boards: AGC-1
Serial VME boards: ISIO-1, ISIO-2
Digital Equipment
DEC MicroServer DEMSA, DECrouter-150, DECrouter-250
------------------------------------------------
TODO/ "NDUSCC" "CDUSCC"
-DONE (x) (p=partly) NMOS CMOS
+DONE (x) (p=partly) NMOS CMOS
------------------------------------------------
- Channels 2 FD 2 FD
- Synch data rates 4Mbps 10Mbps
+ Channels 2 FD 2 FD
+ Synch data rates 4Mbps 10Mbps
----- asynchrounous features ------------------
p 5-8 bit per char Y Y
y 1,1.5,2 stop bits Y Y in 1/16 bit increments
@@ -42,7 +42,7 @@ DONE (x) (p=partly) NMOS CMOS
x1,x16 Y Y
break det/gen Y Y
parity, framing & Y Y
- overrun error det
+ overrun error det
-- byte oriented synchrounous features --
Int/ext char sync Y Y
1/2 synch chars ? ?
@@ -58,7 +58,7 @@ DONE (x) (p=partly) NMOS CMOS
--
Receiver FIFO 4 16
Transmitter FIFO 4 16
- NRZ, NRZI, FM1 or Y Y
+ NRZ, NRZI, FM1 or Y Y
FM2 enc/dec
Manchester dec Y Y
Baud gen per chan Y Y
@@ -72,7 +72,7 @@ DONE (x) (p=partly) NMOS CMOS
TxFifo Empty status N Y
Interrupt enable bits N Y
X.21 pattern recogn N Y
- Improved BiSync support N Y
+ Improved BiSync support N Y
-------------------------------------------------------------------------
x/p = Features that has been implemented n/a = features that will not
***************************************************************************/
@@ -88,7 +88,7 @@ DONE (x) (p=partly) NMOS CMOS
#define VERBOSE 2
#define LOG(x) do { if (VERBOSE) logerror x; } while (0)
-#define LOGR(x)
+#define LOGR(x)
#if VERBOSE == 0
#define logerror printf
#endif
@@ -108,12 +108,12 @@ DONE (x) (p=partly) NMOS CMOS
// DEVICE DEFINITIONS
//**************************************************************************
// device type definition
-const device_type DUSCC = &device_creator<duscc_device>;
+const device_type DUSCC = &device_creator<duscc_device>;
const device_type DUSCC_CHANNEL = &device_creator<duscc_channel>;
-const device_type DUSCC26562 = &device_creator<duscc26562_device>;
-const device_type DUSCC26C562 = &device_creator<duscc26C562_device>;
-const device_type DUSCC68562 = &device_creator<duscc68562_device>;
-const device_type DUSCC68C562 = &device_creator<duscc68C562_device>;
+const device_type DUSCC26562 = &device_creator<duscc26562_device>;
+const device_type DUSCC26C562 = &device_creator<duscc26C562_device>;
+const device_type DUSCC68562 = &device_creator<duscc68562_device>;
+const device_type DUSCC68C562 = &device_creator<duscc68C562_device>;
//-------------------------------------------------
// device_mconfig_additions -
@@ -137,7 +137,7 @@ machine_config_constructor duscc_device::device_mconfig_additions() const
//-------------------------------------------------
duscc_device::duscc_device(const machine_config &mconfig, device_type type, const char *name, const char *tag, device_t *owner, UINT32 clock, UINT32 variant, const char *shortname, const char *source)
: device_t(mconfig, type, name, tag, owner, clock, shortname, source),
- // device_z80daisy_interface(mconfig, *this),
+ // device_z80daisy_interface(mconfig, *this),
m_chanA(*this, CHANA_TAG),
m_chanB(*this, CHANB_TAG),
#if 0
@@ -233,7 +233,7 @@ void duscc_device::device_reset()
void duscc_device::check_interrupts()
{
LOG(("%s %s - not implemented\n",tag(), FUNCNAME));
- // m_out_int_cb(state);
+ // m_out_int_cb(state);
}
@@ -313,10 +313,10 @@ duscc_channel::duscc_channel(const machine_config &mconfig, const char *tag, dev
LOG(("%s\n",FUNCNAME));
// Reset all registers
- m_cmr1 = m_cmr2 = m_s1r = m_s2r = m_tpr = m_ttr = m_rpr = m_rtr
- = m_ctprh = m_ctprl = m_ctcr = m_omr = m_cth = m_ctl = m_pcr
+ m_cmr1 = m_cmr2 = m_s1r = m_s2r = m_tpr = m_ttr = m_rpr = m_rtr
+ = m_ctprh = m_ctprl = m_ctcr = m_omr = m_cth = m_ctl = m_pcr
= m_ccr = m_rsr = m_trsr = m_ictsr = m_gsr = m_ier /* = m_rea */
- = m_cid = m_ivr = m_icr = /*m_sea =*/ m_ivrm = m_mrr = m_ier1
+ = m_cid = m_ivr = m_icr = /*m_sea =*/ m_ivrm = m_mrr = m_ier1
= m_ier2 = m_ier3 = m_trcr = m_rflr = m_ftlr = m_trmsr = m_telr = 0;
for (int i = 0; i < sizeof(m_rx_data_fifo); i++)
@@ -373,11 +373,11 @@ void duscc_channel::device_start()
save_item(NAME(m_ictsr));
save_item(NAME(m_gsr)); // TODO: Move this to the device instead, it is a global register
save_item(NAME(m_ier));
- // save_item(NAME(m_rea));
+ // save_item(NAME(m_rea));
save_item(NAME(m_cid));
save_item(NAME(m_ivr));
save_item(NAME(m_icr));
- // save_item(NAME(m_sea));
+ // save_item(NAME(m_sea));
save_item(NAME(m_ivrm));
save_item(NAME(m_mrr));
save_item(NAME(m_ier1));
@@ -422,37 +422,37 @@ void duscc_channel::device_reset()
transmit_register_reset();
// Soft/Channel Reset values according to DUSCC users guide
- m_cmr1 =0x00;
- m_cmr2 =0x00;
- m_s1r =0x00;
- m_s2r =0x00;
- m_tpr =0x00;
- m_ttr =0x00;
- m_rpr =0x00;
- m_rtr =0x00;
- m_ctcr =0x00;
- m_omr =0x00;
- m_pcr =0x00;
- m_ccr =0x00;
- m_rsr =0x00;
- m_trsr =0x00;
- m_ictsr =0x00;
- m_gsr =0x00;
- m_ier =0x00;
- // m_rea =0x00;
- m_ivr =0x0f;
- m_icr =0x00;
- // m_sea =0x00;
- m_ivrm =0x00;
- m_mrr =0x00; // TODO: Need a read after reset to enable CMOS features
- m_ier1 =0x00;
- m_ier2 =0x00;
- m_ier3 =0x00;
- m_trcr =0x00;
- m_rflr =0x00;
- m_ftlr =0x33;
- m_trmsr =0x00;
- m_telr =0x10;
+ m_cmr1 =0x00;
+ m_cmr2 =0x00;
+ m_s1r =0x00;
+ m_s2r =0x00;
+ m_tpr =0x00;
+ m_ttr =0x00;
+ m_rpr =0x00;
+ m_rtr =0x00;
+ m_ctcr =0x00;
+ m_omr =0x00;
+ m_pcr =0x00;
+ m_ccr =0x00;
+ m_rsr =0x00;
+ m_trsr =0x00;
+ m_ictsr =0x00;
+ m_gsr =0x00;
+ m_ier =0x00;
+ // m_rea =0x00;
+ m_ivr =0x0f;
+ m_icr =0x00;
+ // m_sea =0x00;
+ m_ivrm =0x00;
+ m_mrr =0x00; // TODO: Need a read after reset to enable CMOS features
+ m_ier1 =0x00;
+ m_ier2 =0x00;
+ m_ier3 =0x00;
+ m_trcr =0x00;
+ m_rflr =0x00;
+ m_ftlr =0x33;
+ m_trmsr =0x00;
+ m_telr =0x10;
// reset external lines TODO: check relation to control bits and reset
set_rts(1);
@@ -502,7 +502,7 @@ void duscc_channel::tra_callback()
//------------------------------------------
// tra_complete -
-// TODO:
+// TODO:
// - Fix mark and space tx support
//------------------------------------------
@@ -513,7 +513,7 @@ void duscc_channel::tra_complete()
if (m_tx_fifo_rp != m_tx_fifo_wp) // there are more characters to send?
{
transmit_register_setup(m_tx_data_fifo[m_tx_fifo_rp]); // Reload the shift register
- m_tx_fifo_rp_step();
+ m_tx_fifo_rp_step();
}
if (m_omr & REG_OMR_TXRDY_ACTIVATED)// Wait until FIFO empty before ready for more data?
{
@@ -598,7 +598,7 @@ void duscc_channel::set_rts(int state)
* or 2 stop bits. It is also dependent on the data bit length
* TODO: Support finer granularity of stop bits in diserial if/when nessesarry
* ---------------------------------------------------------------------------
- * TPR[4:7] TPR[0:1]
+ * TPR[4:7] TPR[0:1]
* 5 bits 6-8 bits
* 00 01,10,11
* ---------------------------
@@ -622,16 +622,16 @@ void duscc_channel::set_rts(int state)
*/
device_serial_interface::stop_bits_t duscc_channel::get_stop_bits()
{
- const stop_bits_t bits5[] =
+ const stop_bits_t bits5[] =
{ STOP_BITS_1, STOP_BITS_1, STOP_BITS_1, STOP_BITS_1, STOP_BITS_1_5, STOP_BITS_1_5, STOP_BITS_1_5, STOP_BITS_1_5,
- STOP_BITS_1_5, STOP_BITS_1_5, STOP_BITS_1_5, STOP_BITS_2, STOP_BITS_2, STOP_BITS_2, STOP_BITS_2, STOP_BITS_2 };
- const stop_bits_t bits6to8[] =
+ STOP_BITS_1_5, STOP_BITS_1_5, STOP_BITS_1_5, STOP_BITS_2, STOP_BITS_2, STOP_BITS_2, STOP_BITS_2, STOP_BITS_2 };
+ const stop_bits_t bits6to8[] =
{ STOP_BITS_1, STOP_BITS_1, STOP_BITS_1, STOP_BITS_1, STOP_BITS_1, STOP_BITS_1, STOP_BITS_1, STOP_BITS_1,
- STOP_BITS_1, STOP_BITS_1_5, STOP_BITS_1_5, STOP_BITS_2, STOP_BITS_2, STOP_BITS_2, STOP_BITS_2, STOP_BITS_2 };
+ STOP_BITS_1, STOP_BITS_1_5, STOP_BITS_1_5, STOP_BITS_2, STOP_BITS_2, STOP_BITS_2, STOP_BITS_2, STOP_BITS_2 };
/* 5 data bits */
if (get_tx_word_length() == 5)
- {
+ {
return bits5[((m_tpr & REG_TPR_STOP_BITS_MASK) >> 4) & 0x0f];
}
else /* 6-8 data bits */
@@ -651,7 +651,7 @@ int duscc_channel::get_rx_word_length()
int bits = 5;
switch (m_rpr & REG_RPR_DATA_BITS_MASK)
- {
+ {
case REG_RPR_DATA_BITS_5BIT: bits = 5; break;
case REG_RPR_DATA_BITS_6BIT: bits = 6; break;
case REG_RPR_DATA_BITS_7BIT: bits = 7; break;
@@ -671,7 +671,7 @@ int duscc_channel::get_tx_word_length()
int bits = 5;
switch (m_tpr & REG_TPR_DATA_BITS_MASK)
- {
+ {
case REG_TPR_DATA_BITS_5BIT: bits = 5; break;
case REG_TPR_DATA_BITS_6BIT: bits = 6; break;
case REG_TPR_DATA_BITS_7BIT: bits = 7; break;
@@ -700,13 +700,13 @@ UINT8 duscc_channel::do_dusccreg_pcr_r(){ logerror("register access method %s is
/* Commands to the DUSCC are entered through the channel command register.A read of this
register returns the last invoked command (with bits 4 and 5 set to 1). */
UINT8 duscc_channel::do_dusccreg_ccr_r()
-{
+{
LOG(("%s\n", FUNCNAME));
- return (UINT8) m_ccr | 1 << 4 | 1 << 5;
+ return (UINT8) m_ccr | 1 << 4 | 1 << 5;
}
UINT8 duscc_channel::do_dusccreg_rxfifo_r()
-{
+{
UINT8 data = 0;
LOG(("%s\n", FUNCNAME));
@@ -725,48 +725,48 @@ UINT8 duscc_channel::do_dusccreg_rxfifo_r()
LOG(("- RX FIFO empty despite RxREADY\n"));
}
- return (UINT8) data;
+ return (UINT8) data;
}
UINT8 duscc_channel::do_dusccreg_rsr_r(){ logerror("register access method %s is not implemented yet\n", FUNCNAME); return (UINT8) 0; }
UINT8 duscc_channel::do_dusccreg_trsr_r(){ logerror("register access method %s is not implemented yet\n", FUNCNAME); return (UINT8) 0; }
UINT8 duscc_channel::do_dusccreg_ictsr_r()
-{
- logerror("register access method %s is not implemented yet\n", FUNCNAME);
- return (UINT8) m_ictsr;
+{
+ logerror("register access method %s is not implemented yet\n", FUNCNAME);
+ return (UINT8) m_ictsr;
}
/* General Status Register (GSR)
This register provides a 'quick look' at the overall status of both channels of the DUSCC. A write to this register with ls at the
corresponding bit pOSitions causes TxRDY (bits 5 and 1) and/or RxRDY (bits 4 and 0) to be reset. The other status bits can be reset
- only by resetting the individual status bits that they point to.
- [7] Channel B External or Counter/timer Status - This bit indicates that one of the following status bits is asserted: ICTSRB[6:4]
- [6] Channel B Receiver or Transmitter Status - This bit indicates that one of the following status bits is asserted: TRSRB[7:1], TRSRB[7:3].
- [5] Channel B Transmitter Ready - The assertion of this bit indicates that one or more characters may be loaded into the Channel B transmitter
- FIFO to be serialized by the transmit shift register. See description of OMR[4j. This bit can be asserted only when the transmitter is enabled.
- Resetting the transmitter negates TxRDY.
- [4] Channel B Receiver Ready - The assertion of this bit indicates that one or more characters are available in the Channel B receiver
+ only by resetting the individual status bits that they point to.
+ [7] Channel B External or Counter/timer Status - This bit indicates that one of the following status bits is asserted: ICTSRB[6:4]
+ [6] Channel B Receiver or Transmitter Status - This bit indicates that one of the following status bits is asserted: TRSRB[7:1], TRSRB[7:3].
+ [5] Channel B Transmitter Ready - The assertion of this bit indicates that one or more characters may be loaded into the Channel B transmitter
+ FIFO to be serialized by the transmit shift register. See description of OMR[4j. This bit can be asserted only when the transmitter is enabled.
+ Resetting the transmitter negates TxRDY.
+ [4] Channel B Receiver Ready - The assertion of this bit indicates that one or more characters are available in the Channel B receiver
FIFO to be read by the CPU. See deSCription of OMR[3]. RxRDY is initially reset (negated) by a chip reset or when a 'reset Channel B
- receiver' command is invoked.
- [3] Channel A External or Countermmer Status - This bit indicates that one of the following status bits is asserted: ICTSRA[6:4].
- [2] Channel A Receiver or Transmitter Status - This bit indicates that one of the following status bits is asserted: TRSRA[7:0], TRSRA[7:3].
- [1] Channel A Transmitter Ready - The assertion of this bit indicates that one or more characters may be loaded into the Channel A
- transmitter FIFO to be serialized by the transmit shift register. See description of OMR[4]. This bit can be asserted only
- when the transmitter is enabled. Resetting the transmitter negates TxRDY.
- [0] Channel A Receiver Ready - The assertion of this bit indicates that one or more characters are available in the Channel A receiver
- FIFO to be read by the CPU. See description of OMR[3]. RxRDY is initially reset (negated) by a chip reset or when a 'reset Channel A
- receiver' command is invoked.
+ receiver' command is invoked.
+ [3] Channel A External or Countermmer Status - This bit indicates that one of the following status bits is asserted: ICTSRA[6:4].
+ [2] Channel A Receiver or Transmitter Status - This bit indicates that one of the following status bits is asserted: TRSRA[7:0], TRSRA[7:3].
+ [1] Channel A Transmitter Ready - The assertion of this bit indicates that one or more characters may be loaded into the Channel A
+ transmitter FIFO to be serialized by the transmit shift register. See description of OMR[4]. This bit can be asserted only
+ when the transmitter is enabled. Resetting the transmitter negates TxRDY.
+ [0] Channel A Receiver Ready - The assertion of this bit indicates that one or more characters are available in the Channel A receiver
+ FIFO to be read by the CPU. See description of OMR[3]. RxRDY is initially reset (negated) by a chip reset or when a 'reset Channel A
+ receiver' command is invoked.
*/
UINT8 duscc_channel::do_dusccreg_gsr_r()
-{
+{
LOGR(("%s <- %02x\n", FUNCNAME, m_gsr));
- return (UINT8) m_gsr;
+ return (UINT8) m_gsr;
}
UINT8 duscc_channel::do_dusccreg_ier_r(){ logerror("register access method %s is not implemented yet\n", FUNCNAME); return (UINT8) 0; }
UINT8 duscc_channel::do_dusccreg_cid_r()
-{
+{
LOG(("%s\n", FUNCNAME));
if ( m_uart->m_variant != SET_CMOS )
{
@@ -797,186 +797,186 @@ UINT8 duscc_channel::do_dusccreg_telr_r(){ logerror("register access method %s i
// write register handlers
/* CMR1 register
- [7:6] Data Encoding - These bits select the data encoding for the received and transmitted data:
- 00 If the DPLL is set to NRZI mode (see DPLL commands), it selects positive logic (1 = high, 0 = low).
+ [7:6] Data Encoding - These bits select the data encoding for the received and transmitted data:
+ 00 If the DPLL is set to NRZI mode (see DPLL commands), it selects positive logic (1 = high, 0 = low).
If the DPLL is set to FM mode (see DPLL commands), Manchester (bi-phase level) encoding is selected.
- 01 NRZI. Non-return-to-zero inverted.
- 10 FMO. Bi-phase space.
- 11 FM 1. Bi-phase mark.
- [5] Extended Control (BOP) -
- 0 No. A one-octet control field follows the address field.
- 1 Yes. A two-octet control field follows the address field.
- [5] Parity (COP/ ASYNC), Code Select (BISYNC)
- 0 Even parity if with parity is selected by [4:3] or a 0 in the parity bit position if force parity is
- selected by [4:3]. In BISYNC protocol mode, internal character comparisons are made using EBCDIC coding.
- 1 Odd parity if with parity is selected by [4:3] or a 1 in the parity bit position if force parity is selected by [4:3].
- In BISYNC protocol mode, internal character comparisons are made using Bbit ASCII coding.
- [4:3] Address Mode (BOP) -
- This field controls whether a single octet or multiple octets follow the opening FLAG(s) for both the receiver and the transmitter.
- This field is activated by selection of BOP secondary mode through the channel protocol mode bits CMR1_[2:0] (see Detailed Operation).
- 00 Single octet address.
- 01 Extended address.
- 10 Dual octet address.
- 11 Dual octet address with group.
- [4:3] Parity Mode (COP/ASYNC) -
- This field selects the parity mode for both the receiver and the transmitter. A parity bit is added to the programmed character length if
- with parity or force parity is selected:
- 00 No parity. Required when BISYNC protocol mode is programmed.
- 01 Reserved.
- 10 With parity. Odd or even parity is selected by [5].
- 11 Force parity. The parity bit is forced to the state selected by [5].
- [2:0] Channel Protocol Mode -
- This field selects the operational protocol and submode for both the receiver and transmitter:
- 000 - BOP Primary. No address comparison is performed. For receive, all characters received after the opening FLAG(s) are transferred to the FIFO.
- 001 - BOP Secondary. This mode activates the address modes selected by [4:3]. Except in the case of extended address ([4:3]=01), an address comparison
- is performed to determine if a frame should be received. Refer to Detailed Operation for details of the various addressing modes. If a valid comparison
- occurs, the receiver is activated and the address octets and all subsequent received characters of the frame are transferred to the receive FIFO.
- 010 - BOP Loop. The DUSCC acts as a secondary station in a loop. The GO-ON-LOOP and GO-OFF-LOOP commands are used to cause the DUSCC to go on and off the
- loop. Normally, the TXD output echoes the RXD input with a three bit time delay. If the transmitter is enabled and the 'go active on poll' command has been
- asserted, the transmitter will begin sending when an EOP sequence consisting of a zero followed by seven ones is detected. The DUSCC changes the last one of
- the EOP to zero, making it another FLAG, and then operates as described in the detailed operation section. The loop sending status bit (TRSR[6]) is asserted
- concurrent with the beginning of transmission. The frame should normally be terminated with an EOM followed by an echo of the marking RXD line so that secondary
- stations further down the loop can append their messages to the messages from up-loop stations by the same process. If the 'go active on poll'command is not
- asserted, the transmitter remains inactive (other than echOing the received data) even when the EOP sequence is received.
- 011 - BOP Loop without address comparison. Same as normal loop mode except that address field comparisons are disabled. All received frames aretransmitted to the CPU.
- 100 - COP Dual SYN. Character sync is achieved upon receipt of a bit sequence matching the contents of the appropriate bits of SIR and S2R (SYNI-SYN2), including
- parity bits if any.
- 101 - COP Dual SYN (BISYNC). Character sync is achieved upon receipt of a bit sequence matching the contents of the appropriate bits of SI Rand S2R
- (SYN1SYN2). In this mode, special transmitter and receive logic is activated. Transmitter and receiver character length must be programmed to 8 bits and no parity
- 110 - COP Single SYN. Character sync is achieved upon receipt of a bit sequence matching the contents of the appropriate bits of Sl R (SYN1), including parity bit if any.
- This mode is required when the external sync mode is selected.
- 111 Asynchronous. Start/stop format.
+ 01 NRZI. Non-return-to-zero inverted.
+ 10 FMO. Bi-phase space.
+ 11 FM 1. Bi-phase mark.
+ [5] Extended Control (BOP) -
+ 0 No. A one-octet control field follows the address field.
+ 1 Yes. A two-octet control field follows the address field.
+ [5] Parity (COP/ ASYNC), Code Select (BISYNC)
+ 0 Even parity if with parity is selected by [4:3] or a 0 in the parity bit position if force parity is
+ selected by [4:3]. In BISYNC protocol mode, internal character comparisons are made using EBCDIC coding.
+ 1 Odd parity if with parity is selected by [4:3] or a 1 in the parity bit position if force parity is selected by [4:3].
+ In BISYNC protocol mode, internal character comparisons are made using Bbit ASCII coding.
+ [4:3] Address Mode (BOP) -
+ This field controls whether a single octet or multiple octets follow the opening FLAG(s) for both the receiver and the transmitter.
+ This field is activated by selection of BOP secondary mode through the channel protocol mode bits CMR1_[2:0] (see Detailed Operation).
+ 00 Single octet address.
+ 01 Extended address.
+ 10 Dual octet address.
+ 11 Dual octet address with group.
+ [4:3] Parity Mode (COP/ASYNC) -
+ This field selects the parity mode for both the receiver and the transmitter. A parity bit is added to the programmed character length if
+ with parity or force parity is selected:
+ 00 No parity. Required when BISYNC protocol mode is programmed.
+ 01 Reserved.
+ 10 With parity. Odd or even parity is selected by [5].
+ 11 Force parity. The parity bit is forced to the state selected by [5].
+ [2:0] Channel Protocol Mode -
+ This field selects the operational protocol and submode for both the receiver and transmitter:
+ 000 - BOP Primary. No address comparison is performed. For receive, all characters received after the opening FLAG(s) are transferred to the FIFO.
+ 001 - BOP Secondary. This mode activates the address modes selected by [4:3]. Except in the case of extended address ([4:3]=01), an address comparison
+ is performed to determine if a frame should be received. Refer to Detailed Operation for details of the various addressing modes. If a valid comparison
+ occurs, the receiver is activated and the address octets and all subsequent received characters of the frame are transferred to the receive FIFO.
+ 010 - BOP Loop. The DUSCC acts as a secondary station in a loop. The GO-ON-LOOP and GO-OFF-LOOP commands are used to cause the DUSCC to go on and off the
+ loop. Normally, the TXD output echoes the RXD input with a three bit time delay. If the transmitter is enabled and the 'go active on poll' command has been
+ asserted, the transmitter will begin sending when an EOP sequence consisting of a zero followed by seven ones is detected. The DUSCC changes the last one of
+ the EOP to zero, making it another FLAG, and then operates as described in the detailed operation section. The loop sending status bit (TRSR[6]) is asserted
+ concurrent with the beginning of transmission. The frame should normally be terminated with an EOM followed by an echo of the marking RXD line so that secondary
+ stations further down the loop can append their messages to the messages from up-loop stations by the same process. If the 'go active on poll'command is not
+ asserted, the transmitter remains inactive (other than echOing the received data) even when the EOP sequence is received.
+ 011 - BOP Loop without address comparison. Same as normal loop mode except that address field comparisons are disabled. All received frames aretransmitted to the CPU.
+ 100 - COP Dual SYN. Character sync is achieved upon receipt of a bit sequence matching the contents of the appropriate bits of SIR and S2R (SYNI-SYN2), including
+ parity bits if any.
+ 101 - COP Dual SYN (BISYNC). Character sync is achieved upon receipt of a bit sequence matching the contents of the appropriate bits of SI Rand S2R
+ (SYN1?SYN2). In this mode, special transmitter and receive logic is activated. Transmitter and receiver character length must be programmed to 8 bits and no parity
+ 110 - COP Single SYN. Character sync is achieved upon receipt of a bit sequence matching the contents of the appropriate bits of Sl R (SYN1), including parity bit if any.
+ This mode is required when the external sync mode is selected.
+ 111 Asynchronous. Start/stop format.
*/
void duscc_channel::do_dusccreg_cmr1_w(UINT8 data)
-{
+{
LOG(("%s(%02x)\n", FUNCNAME, data));
m_cmr1 = data;
LOG(("- Setting up %s mode\n", (m_cmr1 & REG_CMR1_CPMODE_MASK) == REG_CMR1_CPMODE_ASYNC ? "ASYNC" : "SYNC"));
LOG(("- Parity: %s\n", ((m_cmr1 & REG_CMR1_PMMODE_MASK) == REG_CMR1_PMMODE_PARITY ? (m_cmr1 & REG_CMR1_PARITY ? "odd" : "even") : "none")));
- return;
+ return;
}
/* CMR2 register
- [7:6] Channel Connection - This field selects the mode of operation of the channel. The user must exercise care when switching into and out of the various modes. The
- selected mode will be activated immediately upon mode selection, even if this occurs in the middle of a received or transmitted character.
-
- 00 - Normal mode. The 1ransmitter and receiver operate independently in either half or full-duplex, controlled by the respective enable commands.
-
- 01 - Automatic echo mode. Automatically retransmits the received data with a half-bit time delay (ASYNC, 16X clock mode) or a one-bit time delay (allother modes).
- The following conditions are true while in automatic echo mode:
- 1. Received data is reclocked and retransmitted on the TXD output.
- 2. The receiver clock is used for the transmitter.
- 3. The receiver must be enabled, but the transmitter need not be enabled.
- 4. The TXRDY and underrun status bits are inactive.
- 5. The received parity and/or FCS are checked if required, but are not regenerated for transmission,
- i.e., transmitted parity and/ or FCS are as received.
- 6. In ASYNC mode, character framing is checked, but the stop bits are retransmitted as received.
- A received break is echoed as received.
- 7. CPU to receiver communication continues normally, but the CPU to transmitter link is disabled.
-
- 10 - Local loopback mode. In this mode:
- 1. The transmitter output is internally connected to the receiver input.
- 2. The transmit clock is used for the receiver if NRZI or NRZ encoding is used. For FM or Manchester encoding because the receiver clock is derived from the DPLL,
+ [7:6] Channel Connection - This field selects the mode of operation of the channel. The user must exercise care when switching into and out of the various modes. The
+ selected mode will be activated immediately upon mode selection, even if this occurs in the middle of a received or transmitted character.
+
+ 00 - Normal mode. The 1ransmitter and receiver operate independently in either half or full-duplex, controlled by the respective enable commands.
+
+ 01 - Automatic echo mode. Automatically retransmits the received data with a half-bit time delay (ASYNC, 16X clock mode) or a one-bit time delay (allother modes).
+ The following conditions are true while in automatic echo mode:
+ 1. Received data is reclocked and retransmitted on the TXD output.
+ 2. The receiver clock is used for the transmitter.
+ 3. The receiver must be enabled, but the transmitter need not be enabled.
+ 4. The TXRDY and underrun status bits are inactive.
+ 5. The received parity and/or FCS are checked if required, but are not regenerated for transmission,
+ i.e., transmitted parity and/ or FCS are as received.
+ 6. In ASYNC mode, character framing is checked, but the stop bits are retransmitted as received.
+ A received break is echoed as received.
+ 7. CPU to receiver communication continues normally, but the CPU to transmitter link is disabled.
+
+ 10 - Local loopback mode. In this mode:
+ 1. The transmitter output is internally connected to the receiver input.
+ 2. The transmit clock is used for the receiver if NRZI or NRZ encoding is used. For FM or Manchester encoding because the receiver clock is derived from the DPLL,
the DPLL source clock must be maintained.
- 3. The TXD output is held high.
- 4. The RXD input is ignored.
- 5. The receiver and transmitter must be enabled.
- 6. CPU to transmitter and receiver communications continue normally.
-
- 11 - Reserved.
-
- [5:3] Data Transfer Interface - This field specifies the type of data transfer between the DUSCC's RX and TX FIFOs and the CPU.
- All interrupt and status functions operate normally regardless of the data transfer interface programmed.
- 000 - Half duplex single address DMA.
- 001 - Half duplex dual address DMA.
- 010 - Full duplex single address DMA.
- 011 - Full duplex dual address DMA.
- 100 - Wait on receive only. In this mode a read of a non-empty receive FIFO results in a normal bus cycle. However, if the receive FIFO of the channel
- is empty when a read RX FIFO cycle is initiated, the DTACKN output remains negated until a character is received and loaded into the FIFO.
- DT ACKN is then asserted and the cycle is completed normally.
- 101 - Wait on transmit only. In this mode a write to a non-full transmit FI Fa results in a normal bus cycle. However, if the transmit FIFO of the channel is
- full when a write TX FIFO cycle is initiated, the DTACKN output remains negated until a FI Fa position becomes available for the new character. DT ACKN
- is then asserted and the cycle is completed normally.
- 110 - Wait on transmit and receive. As above for both wait on receive and transmit operations.
- 111 - Polled or interrupt. DMA and wait functions of the channel are not activated. Data transfers to the RX and TX FIFOs are via normal bus read and
- write cycles in response to polling of the status registers and/or interrupts.
-
- [2:0] Frame Check Sequence Select - This field selects the optional frame check sequence (FCS) to be appended at the end of a transmitted frame.
- When CRC is selected in COP, then no parity and 8-bit character length must be used. The selected FCS is transmitted as follows:
- 1. Following the transmission of a FIFO'ed character tagged with the 'send EOM' command.
- 2. If underrun control (TPR[7:6]) is programmed for TEOM, upon occurrence of an underrun.
- 3. If TEOM on zero count or done (TPR[4]) is asserted and the counter/timer is counting transmitted characters, after transmission of the character which
- causes the counter to reach zero count.
- 4. In DMA mode with TEOM on zero count or done (TPR[4]) set, after transmission of a character if DONEN is asserted when that character was loaded into the
- TX FIFO by the DMA controller.
-
- 000 - No frame check sequence.
- 001 - Reserved
- 010 - LRC8: Divisor ~ x8+ 1, dividend preset to zeros. The TX sends the calculated LRC non-inverted. The RX indicates an error if the computed LRC is
- not equal to O. Valid for COP modes only.
- 011 - LRC8: Divisor ~ x8+ 1, dividend preset to ones. The TX sends the calculated LRC non-inverted. The RX indicates
- an error if the computed LRC is not equal to O. Valid for COP modes only.
- 100 - CRCI6: Divisor ~ x16+x15+x2+1, dividend preset to zeros. The TX sends the calculated CRC non-inverted. The RX indicates an error if the
- computed CRC is not equal to O. Not valid for ASYNC mode.
- 101 - CRCI6: Divisor ~ x16+x15+x2+1, dividend preset to ones. The TX sends the calculated CRC non-inverted. The RX indicates an error if the
- computed CRC is not equal to O. Not valid for ASYNC mode.
- 110 - CRC-CCITT: Divisor ~ x16+x12+x5+1, dividend preset to zeros. The TX sends the calculated CRC non-inverted. The RX indicates an error if the
- computed CRC is not equal to O. Not valid for ASYNC mode.
- 111 CRC-CCITT: Divisor ~ x16+x12+x5+1, dividend preset to ones. The TX sends the calculated CRC inverted. The RX indicates an error if the computed
- CRC is not equal to H' FOB8'. Not valid for ASYNC mode.
+ 3. The TXD output is held high.
+ 4. The RXD input is ignored.
+ 5. The receiver and transmitter must be enabled.
+ 6. CPU to transmitter and receiver communications continue normally.
+
+ 11 - Reserved.
+
+ [5:3] Data Transfer Interface - This field specifies the type of data transfer between the DUSCC's RX and TX FIFOs and the CPU.
+ All interrupt and status functions operate normally regardless of the data transfer interface programmed.
+ 000 - Half duplex single address DMA.
+ 001 - Half duplex dual address DMA.
+ 010 - Full duplex single address DMA.
+ 011 - Full duplex dual address DMA.
+ 100 - Wait on receive only. In this mode a read of a non-empty receive FIFO results in a normal bus cycle. However, if the receive FIFO of the channel
+ is empty when a read RX FIFO cycle is initiated, the DTACKN output remains negated until a character is received and loaded into the FIFO.
+ DT ACKN is then asserted and the cycle is completed normally.
+ 101 - Wait on transmit only. In this mode a write to a non-full transmit FI Fa results in a normal bus cycle. However, if the transmit FIFO of the channel is
+ full when a write TX FIFO cycle is initiated, the DTACKN output remains negated until a FI Fa position becomes available for the new character. DT ACKN
+ is then asserted and the cycle is completed normally.
+ 110 - Wait on transmit and receive. As above for both wait on receive and transmit operations.
+ 111 - Polled or interrupt. DMA and wait functions of the channel are not activated. Data transfers to the RX and TX FIFOs are via normal bus read and
+ write cycles in response to polling of the status registers and/or interrupts.
+
+ [2:0] Frame Check Sequence Select - This field selects the optional frame check sequence (FCS) to be appended at the end of a transmitted frame.
+ When CRC is selected in COP, then no parity and 8-bit character length must be used. The selected FCS is transmitted as follows:
+ 1. Following the transmission of a FIFO'ed character tagged with the 'send EOM' command.
+ 2. If underrun control (TPR[7:6]) is programmed for TEOM, upon occurrence of an underrun.
+ 3. If TEOM on zero count or done (TPR[4]) is asserted and the counter/timer is counting transmitted characters, after transmission of the character which
+ causes the counter to reach zero count.
+ 4. In DMA mode with TEOM on zero count or done (TPR[4]) set, after transmission of a character if DONEN is asserted when that character was loaded into the
+ TX FIFO by the DMA controller.
+
+ 000 - No frame check sequence.
+ 001 - Reserved
+ 010 - LRC8: Divisor ~ x8+ 1, dividend preset to zeros. The TX sends the calculated LRC non-inverted. The RX indicates an error if the computed LRC is
+ not equal to O. Valid for COP modes only.
+ 011 - LRC8: Divisor ~ x8+ 1, dividend preset to ones. The TX sends the calculated LRC non-inverted. The RX indicates
+ an error if the computed LRC is not equal to O. Valid for COP modes only.
+ 100 - CRCI6: Divisor ~ x16+x15+x2+1, dividend preset to zeros. The TX sends the calculated CRC non-inverted. The RX indicates an error if the
+ computed CRC is not equal to O. Not valid for ASYNC mode.
+ 101 - CRCI6: Divisor ~ x16+x15+x2+1, dividend preset to ones. The TX sends the calculated CRC non-inverted. The RX indicates an error if the
+ computed CRC is not equal to O. Not valid for ASYNC mode.
+ 110 - CRC-CCITT: Divisor ~ x16+x12+x5+1, dividend preset to zeros. The TX sends the calculated CRC non-inverted. The RX indicates an error if the
+ computed CRC is not equal to O. Not valid for ASYNC mode.
+ 111 CRC-CCITT: Divisor ~ x16+x12+x5+1, dividend preset to ones. The TX sends the calculated CRC inverted. The RX indicates an error if the computed
+ CRC is not equal to H' FOB8'. Not valid for ASYNC mode.
*/
void duscc_channel::do_dusccreg_cmr2_w(UINT8 data)
-{
+{
LOG(("%s(%02x)\n", FUNCNAME, data));
m_cmr2 = data;
LOG(("- Preparing for %s driven transfers\n", (m_cmr2 & REG_CMR2_DTI_MASK) == REG_CMR2_DTI_NODMA ? "polled or interrupt" : "dma"));
- return;
+ return;
}
void duscc_channel::do_dusccreg_s1r_w(UINT8 data){ logerror("register access method %s is not implemented yet\n", FUNCNAME); return; }
void duscc_channel::do_dusccreg_s2r_w(UINT8 data){ logerror("register access method %s is not implemented yet\n", FUNCNAME); return; }
/* Transmitter Parameter Register (TPRA, TPRB)
- SYNC mode
- [7:6] Underrun Control - In BOP and COP modes, this field selects the transmitter response in the event of an underrun (i.e., the TX FIFO is empty).
- 00 - Normal end of message termination. In BOP, the transmitter sends the FCS (if selected by CMR2[2:011 followed by a FLAG and then either MARKs or
- FLAGs, as specified by [5]. In COP, the transmitter sends the FCS (if selected by CMR2[2:0]) and then either MARKs or SYNs, as specified by [5].
- 01 - Reserved.
- l0 - in BOP, the transmitter sends an ABORT (11111111) and then places the TXD output in a marking condition until receipt of further instructions.
- In COP, the transmitter places the TXD output in a marking condition until receipt of further instructions.
- 11 - In BOP, the transmitter sends an ABORT (11111111) and then sends FLAGs until receipt of further instructions. In COP, the transmitter sends
- SYNs until receipt of further instructions.
- [5] Idle - In BOP and COP modes, this bit selects the transmitter output during idle. Idle is defined as the state following a normal end of message until
- receipt of the next transmitter command.
- 0 - Idle in marking condition.
- 1 - Idle sending SYNs (COP) or FLAGs (BOP).
- [4] Transmit EOM on Zero Count or Done - In BOP and COP modes, the assertion of this bit causes the end of message (FCS in COP, FCS-FLAG in BOP) to be transmitted
- upon the following events:
- 1. If the counterltimer is counting transmitted characters, after transmission of the character which causes the counter to reach zero count. (DONEN is also asserted
- as an output if the channel is in a DMA operation.)
- 2. If the channel is operating in DMA mode, after transmission of a character if DONEN was asserted when that character was loaded into the TX FIFO by the DMA controller.
-
- ASYNC mode
- [7:4] Stop Bits per Character - In ASYNC mode, this field programs the length of the stop bit appended to the transmitted character
- Stop bit lengths of 9/16 to 1 and 1-9/16 to 2 bits, in increments of 1/16 bit, can be programmed for character lengths of 6, 7, and 8 bits.
- For a character length of 5 bits, 1-1/16 to 2 stop bits can be programmed in increments of 1/16 bit. The receiver only checks for a 'mark'
- condition at the center of the first stop bit position (one bit time after the last data bit, or after the parity bit if parity is enabled) in all cases.
- If an external 1 X clock is used for the transmitter, [7) = 0 selects one stop bit and [7) = 1 selects two stop bits to be transmitted.
- If Manchester, NRZI, or FM data encoding is selected, only integral stop bit lengths should be used.
- [3] Transmitter Request-to-Send Control - This bit controls the deactivation of the RTS_N output by the transmitter
- 0 - RTS_N is not affected by status of transmitter.
- 1 - RTS_N changes state as a function of transmitter status.
- [2] Clear-ta-Send Enable Transmitter - The state of this bit determines if the CTS N input controls the operation of the channels transmitter
- The duration of CTS level change is described in the discussion of ICTSR[4).
- 0 - CTS_N has no affect on the transmitter.
- 1 - CTS_N affects the state of the transmitter.
- [1:0] Transmitted Bits per Character - This field selects the number of data bits per character to be transmitted. The character length does not
- include the start, parity, and stop bits in ASYNC or the parity bit in COP. In BOP modes the character length for the address and control
- fields is always 8 bits, and the value of this field only applies to the information (I) field, except for the last character of the I field,
- whose length is specified by OMR[7:5).
+ SYNC mode
+ [7:6] Underrun Control - In BOP and COP modes, this field selects the transmitter response in the event of an underrun (i.e., the TX FIFO is empty).
+ 00 - Normal end of message termination. In BOP, the transmitter sends the FCS (if selected by CMR2[2:011 followed by a FLAG and then either MARKs or
+ FLAGs, as specified by [5]. In COP, the transmitter sends the FCS (if selected by CMR2[2:0]) and then either MARKs or SYNs, as specified by [5].
+ 01 - Reserved.
+ l0 - in BOP, the transmitter sends an ABORT (11111111) and then places the TXD output in a marking condition until receipt of further instructions.
+ In COP, the transmitter places the TXD output in a marking condition until receipt of further instructions.
+ 11 - In BOP, the transmitter sends an ABORT (11111111) and then sends FLAGs until receipt of further instructions. In COP, the transmitter sends
+ SYNs until receipt of further instructions.
+ [5] Idle - In BOP and COP modes, this bit selects the transmitter output during idle. Idle is defined as the state following a normal end of message until
+ receipt of the next transmitter command.
+ 0 - Idle in marking condition.
+ 1 - Idle sending SYNs (COP) or FLAGs (BOP).
+ [4] Transmit EOM on Zero Count or Done - In BOP and COP modes, the assertion of this bit causes the end of message (FCS in COP, FCS-FLAG in BOP) to be transmitted
+ upon the following events:
+ 1. If the counterltimer is counting transmitted characters, after transmission of the character which causes the counter to reach zero count. (DONEN is also asserted
+ as an output if the channel is in a DMA operation.)
+ 2. If the channel is operating in DMA mode, after transmission of a character if DONEN was asserted when that character was loaded into the TX FIFO by the DMA controller.
+
+ ASYNC mode
+ [7:4] Stop Bits per Character - In ASYNC mode, this field programs the length of the stop bit appended to the transmitted character
+ Stop bit lengths of 9/16 to 1 and 1-9/16 to 2 bits, in increments of 1/16 bit, can be programmed for character lengths of 6, 7, and 8 bits.
+ For a character length of 5 bits, 1-1/16 to 2 stop bits can be programmed in increments of 1/16 bit. The receiver only checks for a 'mark'
+ condition at the center of the first stop bit position (one bit time after the last data bit, or after the parity bit if parity is enabled) in all cases.
+ If an external 1 X clock is used for the transmitter, [7) = 0 selects one stop bit and [7) = 1 selects two stop bits to be transmitted.
+ If Manchester, NRZI, or FM data encoding is selected, only integral stop bit lengths should be used.
+ [3] Transmitter Request-to-Send Control - This bit controls the deactivation of the RTS_N output by the transmitter
+ 0 - RTS_N is not affected by status of transmitter.
+ 1 - RTS_N changes state as a function of transmitter status.
+ [2] Clear-ta-Send Enable Transmitter - The state of this bit determines if the CTS N input controls the operation of the channels transmitter
+ The duration of CTS level change is described in the discussion of ICTSR[4).
+ 0 - CTS_N has no affect on the transmitter.
+ 1 - CTS_N affects the state of the transmitter.
+ [1:0] Transmitted Bits per Character - This field selects the number of data bits per character to be transmitted. The character length does not
+ include the start, parity, and stop bits in ASYNC or the parity bit in COP. In BOP modes the character length for the address and control
+ fields is always 8 bits, and the value of this field only applies to the information (I) field, except for the last character of the I field,
+ whose length is specified by OMR[7:5).
*/
void duscc_channel::do_dusccreg_tpr_w(UINT8 data)
-{
+{
LOG(("%s(%02x) Setting up Transmit Parameters\n", FUNCNAME, data));
m_tpr = data;
LOG(("- RTS %u\n", (m_tpr & REG_TPR_RTS) ? 1 : 0));
@@ -985,39 +985,39 @@ void duscc_channel::do_dusccreg_tpr_w(UINT8 data)
LOG(("- Data Tx bits %u\n", get_tx_word_length()));
update_serial();
- return;
+ return;
}
/* Transmitter Timing Register (TTRA, TTRB)
- [7] External Source - This bit selects the RTxC pin or the TRxC pin of the channel as the transmitter clock input when [6:4] specifies
- external. When used for input, the selected pin must be programmed as an input in the PCR [4:3] or [2:0].
- 0 External input form RTxC pin.
- 1 External input from TRxC pin.
- [6:4] Transmitter Clock Select - This field selects the clock for the transmitter.
- 000 External clock from TRxC or RTXC at 1 X the shift (baud) rate.
- 001 External clock from TRXC or RTxC at 16X the shift rate.
- 010 Internal clock from the phase-locked loop at IX the bit rate. It should be used only in half-duplex operation since the
- DPLL will periodically resync itself to the received data if in full-duplex operation.
- 0ll Internal clock from the bit rate generator at 32X the shift rate. The clock signal is divided by two before use in the
- transmitter which operates at 16X the baud rate. Rate selected by [3:0].
- 100 Internal clock from counter/timer of other channel. The C/T should be programmed to produce a clock at 2X the shift rate.
- 101 Internal clock from counter/timer of other channel. The C/T should be programmed to produce a clock at 32X the shift rate.
- 110 Internal clock from the counter/timer of own channel. The C/T should be programmed to produce a clock at 2X the shift rate.
- 111 Internal clock from the counter/timer of own channel. The C/T should be programmed to produce a clock at 32X the shift rate.
- [3:0] Bit Rate Select - This field selects an output from the bit rate generator to be used by the transmitter circuits. The actual
- frequency output from the BRG is 32X the bit rate shown in Table 5. With a crystal or external clock of 14.7456MHz the bit rates are as
- given in Table 5 (this input is divided by two before being applied to the oscillator circuit).
-
- Table 5. Receiver/Transmitter Baud Rates
- [3:0] BIT RATE [3:0] BIT RATE
- 0000 50 1000 1050
- 0001 75 1001 1200
- 0010 110 1010 2000
- 0011 134.5 1011 2400
- 0100 150 1100 4800
- 0101 200 1101 9600
- 0110 300 1110 19.2K
- 0111 600 1111 38.4K
+ [7] External Source - This bit selects the RTxC pin or the TRxC pin of the channel as the transmitter clock input when [6:4] specifies
+ external. When used for input, the selected pin must be programmed as an input in the PCR [4:3] or [2:0].
+ 0 External input form RTxC pin.
+ 1 External input from TRxC pin.
+ [6:4] Transmitter Clock Select - This field selects the clock for the transmitter.
+ 000 External clock from TRxC or RTXC at 1 X the shift (baud) rate.
+ 001 External clock from TRXC or RTxC at 16X the shift rate.
+ 010 Internal clock from the phase-locked loop at IX the bit rate. It should be used only in half-duplex operation since the
+ DPLL will periodically resync itself to the received data if in full-duplex operation.
+ 0ll Internal clock from the bit rate generator at 32X the shift rate. The clock signal is divided by two before use in the
+ transmitter which operates at 16X the baud rate. Rate selected by [3:0].
+ 100 Internal clock from counter/timer of other channel. The C/T should be programmed to produce a clock at 2X the shift rate.
+ 101 Internal clock from counter/timer of other channel. The C/T should be programmed to produce a clock at 32X the shift rate.
+ 110 Internal clock from the counter/timer of own channel. The C/T should be programmed to produce a clock at 2X the shift rate.
+ 111 Internal clock from the counter/timer of own channel. The C/T should be programmed to produce a clock at 32X the shift rate.
+ [3:0] Bit Rate Select - This field selects an output from the bit rate generator to be used by the transmitter circuits. The actual
+ frequency output from the BRG is 32X the bit rate shown in Table 5. With a crystal or external clock of 14.7456MHz the bit rates are as
+ given in Table 5 (this input is divided by two before being applied to the oscillator circuit).
+
+ Table 5. Receiver/Transmitter Baud Rates
+ [3:0] BIT RATE [3:0] BIT RATE
+ 0000 50 1000 1050
+ 0001 75 1001 1200
+ 0010 110 1010 2000
+ 0011 134.5 1011 2400
+ 0100 150 1100 4800
+ 0101 200 1101 9600
+ 0110 300 1110 19.2K
+ 0111 600 1111 38.4K
*/
void duscc_channel::do_dusccreg_ttr_w(UINT8 data)
{
@@ -1028,17 +1028,17 @@ void duscc_channel::do_dusccreg_ttr_w(UINT8 data)
#if VERBOSE > 0
switch(m_ttr & REG_TTR_TXCLK_MASK)
{
- case REG_TTR_TXCLK_1XEXT: LOG(("1x External - not implemented\n")); break;
- case REG_TTR_TXCLK_16XEXT: LOG(("16x External - not implemented\n")); break;
- case REG_TTR_TXCLK_DPLL: LOG(("DPLL - not implemented\n")); break;
- case REG_TTR_TXCLK_BRG:
- LOG(("BRG\n"));
+ case REG_TTR_TXCLK_1XEXT: LOG(("1x External - not implemented\n")); break;
+ case REG_TTR_TXCLK_16XEXT: LOG(("16x External - not implemented\n")); break;
+ case REG_TTR_TXCLK_DPLL: LOG(("DPLL - not implemented\n")); break;
+ case REG_TTR_TXCLK_BRG:
+ LOG(("BRG\n"));
m_brg_tx_rate = get_baudrate(m_ttr & REG_TTR_BRG_RATE_MASK);
break;
- case REG_TTR_TXCLK_2X_OTHER: LOG(("2x other channel C/T - not implemented\n")); break;
- case REG_TTR_TXCLK_32X_OTHER: LOG(("32x other channel C/T - not implemented\n")); break;
- case REG_TTR_TXCLK_2X_OWN: LOG(("2x own channel C/T - not implemented\n")); break;
- case REG_TTR_TXCLK_32X_OWN: LOG(("32x own channel C/T - not implemented\n")); break;
+ case REG_TTR_TXCLK_2X_OTHER: LOG(("2x other channel C/T - not implemented\n")); break;
+ case REG_TTR_TXCLK_32X_OTHER: LOG(("32x other channel C/T - not implemented\n")); break;
+ case REG_TTR_TXCLK_2X_OWN: LOG(("2x own channel C/T - not implemented\n")); break;
+ case REG_TTR_TXCLK_32X_OWN: LOG(("32x own channel C/T - not implemented\n")); break;
default: LOG(("Wrong programming\n")); break; // Should never happen
}
#endif
@@ -1046,81 +1046,81 @@ void duscc_channel::do_dusccreg_ttr_w(UINT8 data)
LOG(("- BRG Tx rate %u assuming a 14.7456MHz CLK crystal\n", get_baudrate(m_ttr & REG_TTR_BRG_RATE_MASK)));
update_serial();
- return;
+ return;
}
/* Receiver Parameter Resgister (RPRA, RPRB)
- [7] SYN Stripping - This bit controls the DUSCC processing in COP modes of SYN 'character patterns' that occur after the initial
+ [7] SYN Stripping - This bit controls the DUSCC processing in COP modes of SYN 'character patterns' that occur after the initial
character synchronization. Refer to Detailed Operation of the receiver for details and definition of SYN 'patterns', and their
- accumulation of FCS.
- 0 Strip only leading SYN 'patterns' (i.e. before a message).
- 1 Strip all SYN 'patterns' (including all odd DLE's in BISYNC transparent mode).
-
- [6] Transfer Received FCS to FIFO - In BISYNC and BOP modes, the assertion of this bit causes the received FCS to be loaded into the
- RxFIFO. When this bit is set, BOP mode operates correctly only if a minimum of two extra FLAGs (without shared zeros) are appended
- to the frame. If the FCS is specified to be transferred to the FI FO, the EOM status bit will be tagged onto the last byte of the
- FCS instead of to the last character of the message.
- 0 Do not transfer FCS to RxFIFO.
- 1 Transfer FCS to RxFIFO.
-
- [5] Auto-Hunt and Pad Check (BISYNC) -In BISYNC rnode, the assertion of this bit causes the receiver to go into hunt for character
- sync mode after detecting certain End-Ol-Message (EOM) characters. These are defined in the Detailed Operations section for
- COP receiver operation. After the EOT and NAK sequences, the receiver also does a check for a closing PAD of four 1 s.
- 0 Disable auto-hunt and PAD check.
- 1 Enable auto-hunt and PAD check.
- [5] Overrun Mode (BOP) - The state of this control bit deterrnines the operation of the receiver in the event of a data overrun, i.e.,
- when a character is received while the RxFIFO and the Rx shift register are both full.
- 0 The receiver terrninates receiving the current frame and goes into hunt phase, looking for a FLAG to be received.
- 1 The receiver continues receiving the current frame. The overrunning character is lost. (The five characters already
- assembled in the RxFIFO and Rx shift register are protected).
-
- [4] Receiver Request-to-Send Control (ASYNC)
- 0 Receiver does not control RTSN output.
- 1 Receiver can negate RTSN output.
- [4] External Sync (COP) - In COP single SYN mode, the assertion of this bit enables external character synchronization and
- receipt of SYN patterns is not required. In order to use this feature, the DUSCC must be programmed to COP single SYN mode,
- CMR1[2:0] = 110, which is used to set up the internal data paths. In all other respects, however, the external sync mode operation is
- protocol transparent. A negative signal on the DCDN/SYNIN pin will cause the receiver to establish synchronization on the next rising
- edge of the receiver clock. Character assembly will start at this edge with the RxD input pin considered to have the second bit of
- data. The sync signal can then be negated. Receipt of the Active-High external sync input causes the SYN detect status bit
- (RSR[2]) to be set and the SYNBOUTN pin to be asserted for one bit time. When this mode is enable, the internal SYN (COP mode)
- detection and special character recognition (e.g., IDLE, STX, ETX, etc.) circuits are disabled. Character assembly begins as ~ in the
- I-field with character length as programmed in RPR[I :)]. Incoming COP frames with parity specified optionally can have it stripped by
- programming RPR[3J. The user must wait at least eight bit times after Rx is enabled before applying the SYNIN signal. This time is
- required to flush the internal data paths. The receiver remains in this mode and further external sync pulses are ignored until the
- receiver is disabled and then reenabled to resynchronize or to return to normal mode.
- 0 External sync not enabled.
- 1 External sync enabled.
- Note that EXT SYNC and DCD ENABLE Rx cannot be asserted simultaneously since they use the same pin.
-
- [3] Strip Parity - In COP and ASYNC modes with parity enabled, this bit controls whether the received parity bit is stripped from the
- data placed in the receiver FIFO. It is valid ony for programmed character lengths of 5, 6, and 7 bits. If the bit is stripped, the
- corresponding bit in the received data is set to zero.
- 0 Transfer parity bit as received.
- 1 Stop parity bit from data.
- [3] All Parties Address - In BOP secondary modes, the assertion of this bit causes the receiver to 'wake-up' upon receipt of the
- address H'FF' or H'FF, FF', for single- and dual-octet address modes, respectively, in addition to its normal station address. This
- feature allows all stations to receive a message.
- 0 Don't recognize all parties address.
- 1 Recognize all parties address.
-
- [2] DCD Enable Receiver - If this bit is asserted, the DCDN/SYNIN input must be Low in order for the receiver to operate.
- If the input is negated (goes High) while a character is being received, the receiver terminates receipt of the current message
- (this action in effect disables the receiver). If DCD is subsequently asserted, the receiver will search for the start bit, SYN pattern, or
- FLAG, depending on the channel protocol. (Note that the change of input can be programmed to generate an interrupt; the duration of
- the DCD level change is described in the discussion of the input and counter/timer status register (CTSR[5]).
- 0 DCD not used to enabled receiver.
- 1 DCD used to enabled receiver.
- NOTE that EXT SYNC and DCD ENABLE Rx cannot be asserted simultaneously since they use the same pin.
-
- [1:0] Received Bits per Character - This field selects the number of data bits per character to be assembled by the receiver. The
- character length does not include the start, parity, and stop bits in the ASYNC or the parity bit in COP. In BOP modes, the character
- length for the address and control field is always 8 bits, and the value of this field only applies to the information field. lithe number
- of bits assembled for the last character of the l-field is less than the value programmed in this field, RCL not zero (RSR[O]) is asserted
- and the actual number of bits received is given in TRSR[2:0].
+ accumulation of FCS.
+ 0 Strip only leading SYN 'patterns' (i.e. before a message).
+ 1 Strip all SYN 'patterns' (including all odd DLE's in BISYNC transparent mode).
+
+ [6] Transfer Received FCS to FIFO - In BISYNC and BOP modes, the assertion of this bit causes the received FCS to be loaded into the
+ RxFIFO. When this bit is set, BOP mode operates correctly only if a minimum of two extra FLAGs (without shared zeros) are appended
+ to the frame. If the FCS is specified to be transferred to the FI FO, the EOM status bit will be tagged onto the last byte of the
+ FCS instead of to the last character of the message.
+ 0 Do not transfer FCS to RxFIFO.
+ 1 Transfer FCS to RxFIFO.
+
+ [5] Auto-Hunt and Pad Check (BISYNC) -In BISYNC rnode, the assertion of this bit causes the receiver to go into hunt for character
+ sync mode after detecting certain End-Ol-Message (EOM) characters. These are defined in the Detailed Operations section for
+ COP receiver operation. After the EOT and NAK sequences, the receiver also does a check for a closing PAD of four 1 s.
+ 0 Disable auto-hunt and PAD check.
+ 1 Enable auto-hunt and PAD check.
+ [5] Overrun Mode (BOP) - The state of this control bit deterrnines the operation of the receiver in the event of a data overrun, i.e.,
+ when a character is received while the RxFIFO and the Rx shift register are both full.
+ 0 The receiver terrninates receiving the current frame and goes into hunt phase, looking for a FLAG to be received.
+ 1 The receiver continues receiving the current frame. The overrunning character is lost. (The five characters already
+ assembled in the RxFIFO and Rx shift register are protected).
+
+ [4] Receiver Request-to-Send Control (ASYNC)
+ 0 Receiver does not control RTSN output.
+ 1 Receiver can negate RTSN output.
+ [4] External Sync (COP) - In COP single SYN mode, the assertion of this bit enables external character synchronization and
+ receipt of SYN patterns is not required. In order to use this feature, the DUSCC must be programmed to COP single SYN mode,
+ CMR1[2:0] = 110, which is used to set up the internal data paths. In all other respects, however, the external sync mode operation is
+ protocol transparent. A negative signal on the DCDN/SYNIN pin will cause the receiver to establish synchronization on the next rising
+ edge of the receiver clock. Character assembly will start at this edge with the RxD input pin considered to have the second bit of
+ data. The sync signal can then be negated. Receipt of the Active-High external sync input causes the SYN detect status bit
+ (RSR[2]) to be set and the SYNBOUTN pin to be asserted for one bit time. When this mode is enable, the internal SYN (COP mode)
+ detection and special character recognition (e.g., IDLE, STX, ETX, etc.) circuits are disabled. Character assembly begins as ~ in the
+ I-field with character length as programmed in RPR[I :)]. Incoming COP frames with parity specified optionally can have it stripped by
+ programming RPR[3J. The user must wait at least eight bit times after Rx is enabled before applying the SYNIN signal. This time is
+ required to flush the internal data paths. The receiver remains in this mode and further external sync pulses are ignored until the
+ receiver is disabled and then reenabled to resynchronize or to return to normal mode.
+ 0 External sync not enabled.
+ 1 External sync enabled.
+ Note that EXT SYNC and DCD ENABLE Rx cannot be asserted simultaneously since they use the same pin.
+
+ [3] Strip Parity - In COP and ASYNC modes with parity enabled, this bit controls whether the received parity bit is stripped from the
+ data placed in the receiver FIFO. It is valid ony for programmed character lengths of 5, 6, and 7 bits. If the bit is stripped, the
+ corresponding bit in the received data is set to zero.
+ 0 Transfer parity bit as received.
+ 1 Stop parity bit from data.
+ [3] All Parties Address - In BOP secondary modes, the assertion of this bit causes the receiver to 'wake-up' upon receipt of the
+ address H'FF' or H'FF, FF', for single- and dual-octet address modes, respectively, in addition to its normal station address. This
+ feature allows all stations to receive a message.
+ 0 Don't recognize all parties address.
+ 1 Recognize all parties address.
+
+ [2] DCD Enable Receiver - If this bit is asserted, the DCDN/SYNIN input must be Low in order for the receiver to operate.
+ If the input is negated (goes High) while a character is being received, the receiver terminates receipt of the current message
+ (this action in effect disables the receiver). If DCD is subsequently asserted, the receiver will search for the start bit, SYN pattern, or
+ FLAG, depending on the channel protocol. (Note that the change of input can be programmed to generate an interrupt; the duration of
+ the DCD level change is described in the discussion of the input and counter/timer status register (CTSR[5]).
+ 0 DCD not used to enabled receiver.
+ 1 DCD used to enabled receiver.
+ NOTE that EXT SYNC and DCD ENABLE Rx cannot be asserted simultaneously since they use the same pin.
+
+ [1:0] Received Bits per Character - This field selects the number of data bits per character to be assembled by the receiver. The
+ character length does not include the start, parity, and stop bits in the ASYNC or the parity bit in COP. In BOP modes, the character
+ length for the address and control field is always 8 bits, and the value of this field only applies to the information field. lithe number
+ of bits assembled for the last character of the l-field is less than the value programmed in this field, RCL not zero (RSR[O]) is asserted
+ and the actual number of bits received is given in TRSR[2:0].
*/
void duscc_channel::do_dusccreg_rpr_w(UINT8 data)
-{
+{
LOG(("%s(%02x) Setting up Receiver Parameters\n", FUNCNAME, data));
m_rpr = data;
LOG(("- RTS output %u\n", (m_rpr & REG_RPR_RTS) ? 1 : 0));
@@ -1129,35 +1129,35 @@ void duscc_channel::do_dusccreg_rpr_w(UINT8 data)
LOG(("- Data Rx bits %u\n", get_rx_word_length()));
update_serial();
- return;
+ return;
}
/* Receiver Timing Register (RTRA, RTRB)
- [7] External Source - This M selects the RTxC pin or the TRxC pin of the channel as the receiver or DPLL clock input, when [6:4J
- specifies external. When used for input, the selected pin must be programmed as an input in the PCR [4:3] or [2:0].
- 0 External input form RTxC pin.
- 1 External input form TRxC pin.
- [6:4] Receiver Clock Select- This field selects the clock for the receiver.
- 000 External clock from TRxC or RTxC at 1 X the shift (baud) rate.
- 001 External clock fromTRxC or RTxC at 16X the shift rate. Used for ASYNC mode only.
- 010 Internal clock from the bit rate generator at 32X the shift rate. Clock is divided by two before used by the receiver
- logic, which operates at 16X the baud rate. Rate selected
- by [3:0J. Used for ASYNC mode only.
- 011 Internal clock from counter/timer of own channel. The CIT should be programmed to produce a clock at 32X the shift
- rate. Clock is divided by two before use in the receiver logic. Used for ASYNC mode only.
- 100 Internal clock from the digital phase- locked loop. The clock for the DPLL is a 64X clock from the crystal oscillator or
- system clock input. (The input to the oscillator is divided by two).
- 101 Internal clock from the digital phase- locked loop. The clock for the DPLL is an external 32X clock from the RTxC or
- TRxC pin, as selected by [7J.
- 110 Internal clock from the digital phase- locked loop. The clock for the DPLL is a 32X clock from the BRG. The frequency
- is programmed by [3:0].
- 111 Internal clock from the digital phase- locked loop. The clock for the DPLL is a 32X clock from the counter/timer of the
- channel.
- [3:0] Bit Rate Select- This field selects an output from the bit rate generator to be used by the receiver circuits. The actual frequency
- output from the BRG is 32X the bit rate shown in Table 5.*/
+ [7] External Source - This M selects the RTxC pin or the TRxC pin of the channel as the receiver or DPLL clock input, when [6:4J
+ specifies external. When used for input, the selected pin must be programmed as an input in the PCR [4:3] or [2:0].
+ 0 External input form RTxC pin.
+ 1 External input form TRxC pin.
+ [6:4] Receiver Clock Select- This field selects the clock for the receiver.
+ 000 External clock from TRxC or RTxC at 1 X the shift (baud) rate.
+ 001 External clock fromTRxC or RTxC at 16X the shift rate. Used for ASYNC mode only.
+ 010 Internal clock from the bit rate generator at 32X the shift rate. Clock is divided by two before used by the receiver
+ logic, which operates at 16X the baud rate. Rate selected
+ by [3:0J. Used for ASYNC mode only.
+ 011 Internal clock from counter/timer of own channel. The CIT should be programmed to produce a clock at 32X the shift
+ rate. Clock is divided by two before use in the receiver logic. Used for ASYNC mode only.
+ 100 Internal clock from the digital phase- locked loop. The clock for the DPLL is a 64X clock from the crystal oscillator or
+ system clock input. (The input to the oscillator is divided by two).
+ 101 Internal clock from the digital phase- locked loop. The clock for the DPLL is an external 32X clock from the RTxC or
+ TRxC pin, as selected by [7J.
+ 110 Internal clock from the digital phase- locked loop. The clock for the DPLL is a 32X clock from the BRG. The frequency
+ is programmed by [3:0].
+ 111 Internal clock from the digital phase- locked loop. The clock for the DPLL is a 32X clock from the counter/timer of the
+ channel.
+ [3:0] Bit Rate Select- This field selects an output from the bit rate generator to be used by the receiver circuits. The actual frequency
+ output from the BRG is 32X the bit rate shown in Table 5.*/
void duscc_channel::do_dusccreg_rtr_w(UINT8 data)
-{
+{
LOG(("%s(%02x) Setting up Receiver Timing\n", FUNCNAME, data));
m_rtr = data;
LOG(("- External source: %s\n", (m_rtr & REG_RTR_EXT) ? "TRxC" : "RTxC"));
@@ -1166,17 +1166,17 @@ void duscc_channel::do_dusccreg_rtr_w(UINT8 data)
#if VERBOSE > 0
switch(m_rtr & REG_RTR_RXCLK_MASK)
{
- case REG_RTR_RXCLK_1XEXT: LOG(("1x External - not implemented\n")); break;
- case REG_RTR_RXCLK_16XEXT: LOG(("16x External - not implemented\n")); break;
+ case REG_RTR_RXCLK_1XEXT: LOG(("1x External - not implemented\n")); break;
+ case REG_RTR_RXCLK_16XEXT: LOG(("16x External - not implemented\n")); break;
case REG_RTR_RXCLK_BRG:
- LOG(("BRG\n"));
+ LOG(("BRG\n"));
m_brg_rx_rate = get_baudrate(m_rtr & REG_RTR_BRG_RATE_MASK);
break;
- case REG_RTR_RXCLK_CT: LOG(("C/T of channel - not implemented\n")); break;
- case REG_RTR_RXCLK_DPLL_64X_X1: LOG(("DPLL, source = 64X X1/CLK - not implemented\n")); break;
+ case REG_RTR_RXCLK_CT: LOG(("C/T of channel - not implemented\n")); break;
+ case REG_RTR_RXCLK_DPLL_64X_X1: LOG(("DPLL, source = 64X X1/CLK - not implemented\n")); break;
case REG_RTR_RXCLK_DPLL_32X_EXT:LOG(("DPLL, source = 32X External - not implemented\n")); break;
case REG_RTR_RXCLK_DPLL_32X_BRG:LOG(("DPLL, source = 32X BRG - not implemented\n")); break;
- case REG_RTR_RXCLK_DPLL_32X_CT: LOG(("DPLL, source = 32X C/T - not implemented\n")); break;
+ case REG_RTR_RXCLK_DPLL_32X_CT: LOG(("DPLL, source = 32X C/T - not implemented\n")); break;
default: LOG(("Wrong programming\n")); break; // Should never happen
}
#endif
@@ -1184,7 +1184,7 @@ void duscc_channel::do_dusccreg_rtr_w(UINT8 data)
LOG(("- BRG Rx rate %u assuming a 14.7456MHz CLK crystal\n", get_baudrate(m_rtr & REG_RTR_BRG_RATE_MASK)));
update_serial();
- return;
+ return;
}
void duscc_channel::do_dusccreg_ctprh_w(UINT8 data){ logerror("register access method %s is not implemented yet\n", FUNCNAME); return; }
@@ -1192,44 +1192,44 @@ void duscc_channel::do_dusccreg_ctprl_w(UINT8 data){ logerror("register access m
void duscc_channel::do_dusccreg_ctcr_w(UINT8 data){ logerror("register access method %s is not implemented yet\n", FUNCNAME); return; }
/* Output and Miscellaneous Register (OMRA, OMRB)
- [7:5] Transmitted Residual Character Length - In BOP modes, this field determines the number of bits transmitted for the last
- character in the information field. This length applies to:
- - The character in the transmit FIFO accompanied by the FIFOed TEOM command.
- - The character loaded into the FIFO by the DMA controller if DONEN is simultaneously asserted and TPR(4) is asserted.
- - The character loaded into the FIFO which causes the counter to reach zero count when TPR[4J is asserted.
- The length of all other characters in the frame's information field is selected by TPR[I :OJ. If this field is 111,
- the number of bits in the last character is the same as programmed in TPR[1:0].
- [4] TxRDY Activate Mode -
- 0 FIFO not full. The channel's TxRDY status bit is asserted each time a character is transferred from the transmit FIFO
- to the transmit shift register. If not reset by the CPU, TxRDY remains asserted until the FIFO is full, at which time
- it is automatically negated.
- 1 FIFO empty. The channel's TxRDY status bit is asserted when a character transfer from the transmit FIFO to the
- transmit shift register causes the FI FO to become empty. If not reset by the CPU, TxRDY remains asserted until the
- FIFO is full, at which time it is negated.
- If the TxRDY status bit is reset by the CPU, it will remain negated regardless of the current state of the transmit
- FIFO, until it is asserted again due to the occurrence of one of the above conditions.
- [3] RxRDY Activate Mode -
- 0 FIFO not empty. The channel's RxRDY status bit is asserted each time a character is transferred from the
- receive shift register to the receive FIFO. If not reset by the CPU, RxRDY remains asserted until the receive FIFO is
- empty, at which time it is automatically negated.
- 1 FIFO full. The channel's RxRDY status bit is asserted when a character transfer from the receive shift register to the
- receive FIFO causes the FIFO to become full. If not reset by the CPU, RxRDY reamins asserted until the FIFO is empty,
- at which time it is negated.
- The RxRDY status bit will also be asserted, regardless of the receiver FIFO full condition, when an end-of-message
- character is loaded in the RxFIFO (BOP/BISYNC), when a BREAK condition (ASYNC mode) is detected in RSR[2), or
- when the counterltimer is programmed to count received characters and the character which causes it to reach zero
- is loaded in the FIFO (all modes). If reset by the CPU, the RxRDY status bit will remain negated, regardless of the
- current state of the receiver FIFO, until it is asserted again due to one of the above conditions.
- [2] General Purpose Output 2 -
- This general purpose bit is used to control the TxDRQN/GP02lRTSN pin, when it is used as an output. The output is
- High when the bit is a 0 and is Low when the bit is a 1.
- [1] General Purpose Output 1 - This bit is used to control the RTxDRQN/GPOl N output, which is a general purpose output
- when the channel is not in DMA mode. The output is High when the bit is a 0 and is Low when the bit is a 1.
- [0] Request-to-Send Output - This bit controls the TxDRQN/GP02N/RTSN and SYNOUTN/RTSN pin, when either is
- used as a RTS output. The output is High when the bit is a 0 and is Low when the bit is a 1.
+ [7:5] Transmitted Residual Character Length - In BOP modes, this field determines the number of bits transmitted for the last
+ character in the information field. This length applies to:
+ - The character in the transmit FIFO accompanied by the FIFOed TEOM command.
+ - The character loaded into the FIFO by the DMA controller if DONEN is simultaneously asserted and TPR(4) is asserted.
+ - The character loaded into the FIFO which causes the counter to reach zero count when TPR[4J is asserted.
+ The length of all other characters in the frame's information field is selected by TPR[I :OJ. If this field is 111,
+ the number of bits in the last character is the same as programmed in TPR[1:0].
+ [4] TxRDY Activate Mode -
+ 0 FIFO not full. The channel's TxRDY status bit is asserted each time a character is transferred from the transmit FIFO
+ to the transmit shift register. If not reset by the CPU, TxRDY remains asserted until the FIFO is full, at which time
+ it is automatically negated.
+ 1 FIFO empty. The channel's TxRDY status bit is asserted when a character transfer from the transmit FIFO to the
+ transmit shift register causes the FI FO to become empty. If not reset by the CPU, TxRDY remains asserted until the
+ FIFO is full, at which time it is negated.
+ If the TxRDY status bit is reset by the CPU, it will remain negated regardless of the current state of the transmit
+ FIFO, until it is asserted again due to the occurrence of one of the above conditions.
+ [3] RxRDY Activate Mode -
+ 0 FIFO not empty. The channel's RxRDY status bit is asserted each time a character is transferred from the
+ receive shift register to the receive FIFO. If not reset by the CPU, RxRDY remains asserted until the receive FIFO is
+ empty, at which time it is automatically negated.
+ 1 FIFO full. The channel's RxRDY status bit is asserted when a character transfer from the receive shift register to the
+ receive FIFO causes the FIFO to become full. If not reset by the CPU, RxRDY reamins asserted until the FIFO is empty,
+ at which time it is negated.
+ The RxRDY status bit will also be asserted, regardless of the receiver FIFO full condition, when an end-of-message
+ character is loaded in the RxFIFO (BOP/BISYNC), when a BREAK condition (ASYNC mode) is detected in RSR[2), or
+ when the counterltimer is programmed to count received characters and the character which causes it to reach zero
+ is loaded in the FIFO (all modes). If reset by the CPU, the RxRDY status bit will remain negated, regardless of the
+ current state of the receiver FIFO, until it is asserted again due to one of the above conditions.
+ [2] General Purpose Output 2 -
+ This general purpose bit is used to control the TxDRQN/GP02lRTSN pin, when it is used as an output. The output is
+ High when the bit is a 0 and is Low when the bit is a 1.
+ [1] General Purpose Output 1 - This bit is used to control the RTxDRQN/GPOl N output, which is a general purpose output
+ when the channel is not in DMA mode. The output is High when the bit is a 0 and is Low when the bit is a 1.
+ [0] Request-to-Send Output - This bit controls the TxDRQN/GP02N/RTSN and SYNOUTN/RTSN pin, when either is
+ used as a RTS output. The output is High when the bit is a 0 and is Low when the bit is a 1.
*/
void duscc_channel::do_dusccreg_omr_w(UINT8 data)
-{
+{
LOG(("%s(%02x) Output and Miscellaneous Register\n", FUNCNAME, data));
m_omr = data;
LOG(("- Tx Residual Character Length is "));
@@ -1242,42 +1242,42 @@ void duscc_channel::do_dusccreg_omr_w(UINT8 data)
LOG(("- GP02, if configured as output, is: %u\n", m_omr & REG_OMR_GP02 ? 0 : 1));
LOG(("- GP01, if configured as output, is: %u\n", m_omr & REG_OMR_GP01 ? 0 : 1));
LOG(("- RTS, either pin if configured as output, is: %u\n", m_omr & REG_OMR_RTS ? 0 : 1));
- return;
+ return;
}
/* Pin Configuration Register (PCRA, PCRB)
- This register selects the functions for multipurpose 1/0 pins.
- [7] X2IIDC - This bit is defined only for PCRA. It is not used in PCRB.
- 0 The X2/IDCN pin is used as a crystal connection.
- 1 The X2/IDCN pin is the interrupt daisy chain output.
- [6] GP02/RTS - The function of this pin is programmable only when not operating in full-duplex DMA mode.
- 0 The TxDRQN/GP02N/RTSN pin is a general purpose output. It is Low when OMR[2] is a 1 and High when OMR[2] is a O.
- 1 The pin is a request-to-send output The logical stale of the pin is controlled by OMR[O]. When OMR[O] is set, the output is Low.
- [5] SYNOUT/RTS -
- 0 The SYNOUTN/RTSN pin is an active-Low output which is asserted one bit time after a SYN pattern (COP modes) in HSRH/HSRL or FLAG
- (BOP modes) is detected in CCSR.The output remains asserted for one receiver clock period.
- 1 The pin is a request-to-send output The,logical state of the pin Is controlled by OMR[O] when OMR[O] is set, the output is Low.
- [4:3] RTxC-
- 00 The pin is an input. It must be programmed for input when used as the input for the receiver or transmitter clock, the DPLL, or the CIT.
- 01 The pin is an output for the counterltimer.
- 10 The pin is an output for the transmitter shift register clock.
- 11 The pin is an output for the receiver shift register clock.
- [2:0]TRxC-
- 000 The pin is an input. It must be programmed for input when used as the input for the receiver or transmitter clock, the DPLL, or the CIT.
- 001 The pin is an output from the crystal oscillator divided by two.
- 010 The pin is an outputfor the DPLL output clock.
- 011 The pin is an output for the counterltimer. Refer to CTCRAIB description.
- 100 The pin is an output for the transmitter BRG at 16X the rate selected by TTR [3:0].
- 101 The pin is an output for the receiver BRG at 16X the rate selected by RTR [3:0].
- 110 The pin is an output for the transmitter shift register clock.
- 111 The pin is an output for the receiver shift register clock.
+ This register selects the functions for multipurpose 1/0 pins.
+ [7] X2IIDC - This bit is defined only for PCRA. It is not used in PCRB.
+ 0 The X2/IDCN pin is used as a crystal connection.
+ 1 The X2/IDCN pin is the interrupt daisy chain output.
+ [6] GP02/RTS - The function of this pin is programmable only when not operating in full-duplex DMA mode.
+ 0 The TxDRQN/GP02N/RTSN pin is a general purpose output. It is Low when OMR[2] is a 1 and High when OMR[2] is a O.
+ 1 The pin is a request-to-send output The logical stale of the pin is controlled by OMR[O]. When OMR[O] is set, the output is Low.
+ [5] SYNOUT/RTS -
+ 0 The SYNOUTN/RTSN pin is an active-Low output which is asserted one bit time after a SYN pattern (COP modes) in HSRH/HSRL or FLAG
+ (BOP modes) is detected in CCSR.The output remains asserted for one receiver clock period.
+ 1 The pin is a request-to-send output The,logical state of the pin Is controlled by OMR[O] when OMR[O] is set, the output is Low.
+ [4:3] RTxC-
+ 00 The pin is an input. It must be programmed for input when used as the input for the receiver or transmitter clock, the DPLL, or the CIT.
+ 01 The pin is an output for the counterltimer.
+ 10 The pin is an output for the transmitter shift register clock.
+ 11 The pin is an output for the receiver shift register clock.
+ [2:0]TRxC-
+ 000 The pin is an input. It must be programmed for input when used as the input for the receiver or transmitter clock, the DPLL, or the CIT.
+ 001 The pin is an output from the crystal oscillator divided by two.
+ 010 The pin is an outputfor the DPLL output clock.
+ 011 The pin is an output for the counterltimer. Refer to CTCRAIB description.
+ 100 The pin is an output for the transmitter BRG at 16X the rate selected by TTR [3:0].
+ 101 The pin is an output for the receiver BRG at 16X the rate selected by RTR [3:0].
+ 110 The pin is an output for the transmitter shift register clock.
+ 111 The pin is an output for the receiver shift register clock.
*/
void duscc_channel::do_dusccreg_pcr_w(UINT8 data)
-{
+{
LOG(("%s(%02x) Pin Configuration Register\n", FUNCNAME, data));
m_pcr = data;
- LOG(("- The X2/IDCN pin is %s\n", m_index == duscc_device::CHANNEL_B ? "ignored for channel B" :
- ((m_pcr & REG_PCR_X2_IDC) ? "crystal input" : "daisy chain interrupt output")));
+ LOG(("- The X2/IDCN pin is %s\n", m_index == duscc_device::CHANNEL_B ? "ignored for channel B" :
+ ((m_pcr & REG_PCR_X2_IDC) ? "crystal input" : "daisy chain interrupt output")));
LOG(("- The GP02/RTS pin is %s\n", m_pcr & REG_PCR_GP02_RTS ? "RTS" : "GP02"));
LOG(("- The SYNOUT/RTS pin is %s\n", m_pcr & REG_PCR_SYNOUT_RTS ? "RTS" : "SYNOUT"));
@@ -1285,8 +1285,8 @@ void duscc_channel::do_dusccreg_pcr_w(UINT8 data)
LOG(("- The RTxC pin is "));
switch ( m_pcr & REG_PCR_RTXC_MASK )
{
- case REG_PCR_RTXC_INPUT: LOG(("- an input\n")); break;
- case REG_PCR_RTXC_CNTR_OUT: LOG(("- a counter/timer output\n")); break;
+ case REG_PCR_RTXC_INPUT: LOG(("- an input\n")); break;
+ case REG_PCR_RTXC_CNTR_OUT: LOG(("- a counter/timer output\n")); break;
case REG_PCR_RTXC_TXCLK_OUT:LOG(("- a Tx clock output\n")); break;
case REG_PCR_RTXC_RXCLK_OUT:LOG(("- a Rx clock output\n")); break;
default: LOG(("Wrong programming\n")); break; // Should never happen
@@ -1294,10 +1294,10 @@ void duscc_channel::do_dusccreg_pcr_w(UINT8 data)
LOG(("- The TRxC pin is "));
switch( m_pcr & REG_PCR_TRXC_MASK )
{
- case REG_PCR_TRXC_INPUT: LOG(("- an input\n")); break;
+ case REG_PCR_TRXC_INPUT: LOG(("- an input\n")); break;
case REG_PCR_TRXC_CRYST_OUT:LOG(("- a crystal/2 output\n")); break;
- case REG_PCR_TRXC_DPLL_OUT: LOG(("- a DPLL output\n")); break;
- case REG_PCR_TRXC_CNTR_OUT: LOG(("- a counter/timer output\n")); break;
+ case REG_PCR_TRXC_DPLL_OUT: LOG(("- a DPLL output\n")); break;
+ case REG_PCR_TRXC_CNTR_OUT: LOG(("- a counter/timer output\n")); break;
case REG_PCR_TRXC_TXBRG_OUT:LOG(("- a Tx BRG output\n")); break;
case REG_PCR_TRXC_RXBRG_OUT:LOG(("- a Rx BRG output\n")); break;
case REG_PCR_TRXC_TXCLK_OUT:LOG(("- a Tx CLK output\n")); break;
@@ -1307,14 +1307,14 @@ void duscc_channel::do_dusccreg_pcr_w(UINT8 data)
#endif
- return;
+ return;
}
/*
* Commands to the DUSCC are entered through the CCR channel command register.
*
* TODO:
- * - support enable/disable of Tx/Rx using m_tra/m_rcv respectivelly
+ * - support enable/disable of Tx/Rx using m_tra/m_rcv respectivelly
*/
void duscc_channel::do_dusccreg_ccr_w(UINT8 data)
{
@@ -1322,48 +1322,47 @@ void duscc_channel::do_dusccreg_ccr_w(UINT8 data)
LOG(("%s\n", FUNCNAME));
switch(m_ccr)
{
-
// TRANSMITTER COMMANDS
- /* Reset transmitter. Causes the transmitter to cease operation immediately.
- The transmit FIFO is cleared and the TxD output goes into the marking state.
+ /* Reset transmitter. Causes the transmitter to cease operation immediately.
+ The transmit FIFO is cleared and the TxD output goes into the marking state.
Also clears the transmitter status bits (TRSR[7:4]) and resets the TxRDY
- status bit (GSR[I] or GSR[5] for Channels A and B, respectively).
+ status bit (GSR[I] or GSR[5] for Channels A and B, respectively).
The counter/timer and other registers are not affected*/
- case REG_CCR_RESET_TX: LOG(("- Reset Tx\n"));
+ case REG_CCR_RESET_TX: LOG(("- Reset Tx\n"));
set_tra_rate(0);
m_tx_fifo_wp = m_tx_fifo_rp = 0;
m_trsr &= 0x0f;
m_gsr &= ~(m_index == duscc_device::CHANNEL_A ? REG_GSR_CHAN_A_TXREADY : REG_GSR_CHAN_B_TXREADY);
break;
- /* Enable transmitter. Enables transmitter operation, conditioned by the state of
- the CTS ENABLE Tx bit, TPR[2]. Has no effect if invoked when the transmitter has
+ /* Enable transmitter. Enables transmitter operation, conditioned by the state of
+ the CTS ENABLE Tx bit, TPR[2]. Has no effect if invoked when the transmitter has
previously been enabled.*/
- case REG_CCR_ENABLE_TX: LOG(("- Enable Tx\n"));
+ case REG_CCR_ENABLE_TX: LOG(("- Enable Tx\n"));
m_gsr |= (m_index == duscc_device::CHANNEL_A ? REG_GSR_CHAN_A_TXREADY : REG_GSR_CHAN_B_TXREADY);
m_tra = 1;
set_tra_rate(m_brg_tx_rate);
break;
- /* Disable transmitter. Terminates transmitter operation and places the TXD output in the
- marking state at the next occurrence of a transmit FIFO empty condition. All characters
+ /* Disable transmitter. Terminates transmitter operation and places the TXD output in the
+ marking state at the next occurrence of a transmit FIFO empty condition. All characters
currently in the FIFO, or any loaded subsequently prior to attaining an empty condition,
- will be transmitted.
+ will be transmitted.
TODO: let all the chararcters be transmitted before shutting down shifter */
- case REG_CCR_DISABLE_TX: LOG(("- Disable Tx\n"));
+ case REG_CCR_DISABLE_TX: LOG(("- Disable Tx\n"));
set_tra_rate(0);
m_tra = 0;
m_gsr &= ~(m_index == duscc_device::CHANNEL_A ? REG_GSR_CHAN_A_TXREADY : REG_GSR_CHAN_B_TXREADY);
break;
// RECEIVER COMMANDS
-
- /* Reset Receiver. Causes the receiver to cease operation, clears the receiver FIFO,
+
+ /* Reset Receiver. Causes the receiver to cease operation, clears the receiver FIFO,
clears the data path, and clears t