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author Ted Green <tedgreen99@protonmail.com>2017-09-13 10:32:09 -0600
committer Ted Green <tedgreen99@protonmail.com>2017-09-13 10:32:09 -0600
commit50ae2d7bcfbe485a20d89d6d39a9bc7a3ca70c2b (patch)
treebaf46e57fe7c2df70784d2490827ed65f508e553
parent77153bcb6eeffd7bdf8060e59a30845df8714494 (diff)
iteagle: Promote virtpool from MACHINE_NOT_WORKING to MACHINE_IMPERFECT_GRAPHICS.
iteagle: Update dip settings for bbh series and virtpool. (nw) iteagle: Added new 1.60.01 version of bbh2sc. (nw) iteagle_fpga: Add vblank handling and update gun control. (nw) iteagle_fpga: Add proper eagle1 (virtpool) battery ram functionality. (nw)
-rw-r--r--src/mame/drivers/iteagle.cpp117
-rw-r--r--src/mame/machine/iteagle_fpga.cpp151
-rw-r--r--src/mame/machine/iteagle_fpga.h16
-rw-r--r--src/mame/mame.lst1
4 files changed, 207 insertions, 78 deletions
diff --git a/src/mame/drivers/iteagle.cpp b/src/mame/drivers/iteagle.cpp
index 82f9c71dd9a..74bb9477c85 100644
--- a/src/mame/drivers/iteagle.cpp
+++ b/src/mame/drivers/iteagle.cpp
@@ -41,8 +41,7 @@
* 3DFX Voodoo 1 video
TODO:
- * Add support for Eagle 1 (Virtual Pool) PCBs
- * Add support for later RED boards
+ * Big buck hunter sportmans paradise and shooters challenge only work with secondary targeting (reduced threshold)
Notes:
Sound volume may be muted, it can be adjusted through the service menu or with volume up/down buttons (+/-)
@@ -156,9 +155,10 @@ void iteagle_state::machine_reset()
static MACHINE_CONFIG_START( iteagle )
/* basic machine hardware */
- MCFG_CPU_ADD("maincpu", VR4310LE, 166666666)
+ MCFG_CPU_ADD("maincpu", VR4310LE, 133333333)
MCFG_MIPS3_ICACHE_SIZE(16384)
MCFG_MIPS3_DCACHE_SIZE(8192)
+ MCFG_MIPS3_SYSTEM_CLOCK(66666667)
MCFG_PCI_ROOT_ADD( ":pci")
MCFG_VRC4373_ADD( PCI_ID_NILE, ":maincpu")
@@ -173,8 +173,12 @@ static MACHINE_CONFIG_START( iteagle )
MCFG_SOUND_ROUTE(0, PCI_ID_SOUND":lspeaker", 1.0)
MCFG_SOUND_ROUTE(1, PCI_ID_SOUND":rspeaker", 1.0)
MCFG_ES1373_IRQ_ADD( ":maincpu", MIPS3_IRQ3)
+
MCFG_VOODOO_PCI_ADD( PCI_ID_VIDEO, TYPE_VOODOO_3, ":maincpu")
MCFG_VOODOO_PCI_FBMEM(16)
+ MCFG_DEVICE_MODIFY(PCI_ID_VIDEO":voodoo")
+ MCFG_VOODOO_VBLANK_CB(DEVWRITELINE(PCI_ID_FPGA, iteagle_fpga_device, vblank_update))
+
MCFG_ITEAGLE_EEPROM_ADD( PCI_ID_EEPROM)
MCFG_SCREEN_ADD("screen", RASTER)
@@ -243,23 +247,30 @@ MACHINE_CONFIG_END
static MACHINE_CONFIG_DERIVED( bbh2sp, iteagle )
MCFG_DEVICE_MODIFY(PCI_ID_FPGA)
- MCFG_ITEAGLE_FPGA_INIT(0x02000602, 0x0d0a0a)
+ MCFG_ITEAGLE_FPGA_INIT(0x02010602, 0x0d0a0a)
MCFG_DEVICE_MODIFY(PCI_ID_EEPROM)
MCFG_ITEAGLE_EEPROM_INIT(0x0000, 0x7)
MACHINE_CONFIG_END
static MACHINE_CONFIG_DERIVED( bbhcotw, iteagle )
MCFG_DEVICE_MODIFY(PCI_ID_FPGA)
- MCFG_ITEAGLE_FPGA_INIT(0x02000603, 0x080704)
+ MCFG_ITEAGLE_FPGA_INIT(0x02010603, 0x080704)
MCFG_DEVICE_MODIFY(PCI_ID_EEPROM)
MCFG_ITEAGLE_EEPROM_INIT(0x0603, 0x9)
MACHINE_CONFIG_END
static MACHINE_CONFIG_DERIVED( virtpool, iteagle )
+ // Not sure what the actual value should be
+ // Setting a lower frequency helps delay the tutorial screen premature cut-out
+ MCFG_CPU_MODIFY("maincpu")
+ MCFG_CPU_CLOCK(99999999)
+ MCFG_MIPS3_SYSTEM_CLOCK(33333333)
+
MCFG_DEVICE_REMOVE(PCI_ID_VIDEO)
MCFG_VOODOO_PCI_ADD(PCI_ID_VIDEO, TYPE_VOODOO_1, ":maincpu")
MCFG_VOODOO_PCI_FBMEM(4)
MCFG_VOODOO_PCI_TMUMEM(4, 4)
+
MCFG_DEVICE_MODIFY(PCI_ID_FPGA)
MCFG_ITEAGLE_FPGA_INIT(0x01000202, 0x080808)
MCFG_DEVICE_MODIFY(PCI_ID_EEPROM)
@@ -275,10 +286,16 @@ MACHINE_CONFIG_END
static INPUT_PORTS_START( iteagle )
PORT_START("SW5")
- PORT_DIPNAME( 0xf, 0x1, "Resolution" )
+ PORT_DIPNAME( 0x3, 0x1, "Resolution" )
PORT_DIPSETTING(0x1, "Medium" )
PORT_DIPSETTING(0x0, "Low" )
PORT_DIPSETTING(0x2, "Low_Alt" )
+ PORT_DIPNAME(0x4, 0x0, "SW5-3")
+ PORT_DIPSETTING(0x0, DEF_STR(On))
+ PORT_DIPSETTING(0x4, DEF_STR(Off))
+ PORT_DIPNAME(0x8, 0x0, "SW5-4")
+ PORT_DIPSETTING(0x0, DEF_STR(On))
+ PORT_DIPSETTING(0x8, DEF_STR(Off))
PORT_START("IN1")
PORT_BIT( 0x0001, IP_ACTIVE_LOW, IPT_COIN1 )
@@ -296,14 +313,18 @@ static INPUT_PORTS_START( iteagle )
PORT_BIT( 0x0001, IP_ACTIVE_LOW, IPT_SERVICE ) PORT_NAME( "Service" )
PORT_BIT( 0x0002, IP_ACTIVE_LOW, IPT_SERVICE1 )
PORT_BIT( 0x000c, IP_ACTIVE_LOW, IPT_UNKNOWN )
- PORT_DIPNAME( 0x0010, 0x00, "SW51-1" )
- PORT_DIPSETTING(0x00, "Normal" )
- PORT_DIPSETTING(0x10, "Operator Mode" )
+ PORT_DIPNAME( 0x0010, 0x00, "Operator Mode" )
+ PORT_DIPSETTING(0x00, DEF_STR(No))
+ PORT_DIPSETTING(0x10, DEF_STR(Yes))
PORT_DIPNAME( 0x0020, 0x00, "SW51-2" )
- PORT_DIPSETTING(0x00, "On" )
- PORT_DIPSETTING(0x20, "Off" )
- PORT_DIPNAME( 0xc0, 0x00, "SW51-34" )
- PORT_DIPSETTING(0x00, "On" )
+ PORT_DIPSETTING(0x00, DEF_STR(On))
+ PORT_DIPSETTING(0x20, DEF_STR(Off))
+ PORT_DIPNAME( 0x40, 0x00, "SW51-3" )
+ PORT_DIPSETTING(0x00, DEF_STR(On))
+ PORT_DIPSETTING(0x40, DEF_STR(Off))
+ PORT_DIPNAME(0x80, 0x00, "SW51-4")
+ PORT_DIPSETTING(0x00, DEF_STR(On))
+ PORT_DIPSETTING(0x80, DEF_STR(Off))
PORT_BIT( 0x0100, IP_ACTIVE_LOW, IPT_VOLUME_UP )
PORT_BIT( 0x0200, IP_ACTIVE_LOW, IPT_VOLUME_DOWN )
PORT_BIT( 0x0400, IP_ACTIVE_LOW, IPT_BILL1 )
@@ -328,13 +349,19 @@ static INPUT_PORTS_START( iteagle )
PORT_START("GUNY1")
PORT_BIT( 0x1ff, 0x100, IPT_LIGHTGUN_Y )
- PORT_SENSITIVITY(50) PORT_KEYDELTA(10) PORT_MINMAX(0, 383)
+ PORT_SENSITIVITY(50) PORT_KEYDELTA(10)
INPUT_PORTS_END
static INPUT_PORTS_START( virtpool )
PORT_INCLUDE( iteagle )
+ PORT_MODIFY("SW5")
+ PORT_DIPNAME( 0x3, 0x3, "Resolution" )
+ PORT_DIPSETTING(0x1, "Medium" )
+ PORT_DIPSETTING(0x0, "Low" )
+ PORT_DIPSETTING(0x3, "VGA" )
+
PORT_MODIFY("IN1")
PORT_BIT( 0x0004, IP_ACTIVE_LOW, IPT_BUTTON1 ) PORT_NAME( "English" )
PORT_BIT( 0x0008, IP_ACTIVE_LOW, IPT_BUTTON3 ) PORT_NAME( "Aim" )
@@ -343,30 +370,65 @@ static INPUT_PORTS_START( virtpool )
PORT_MODIFY("SYSTEM")
PORT_BIT( 0x1000, IP_ACTIVE_LOW, IPT_BUTTON2 ) PORT_NAME( "Slop" )
+ PORT_DIPNAME(0x0010, 0x00, "SW51-1") // Turning this on freezes virtpool at boot
+ PORT_DIPSETTING(0x00, DEF_STR(On))
+ PORT_DIPSETTING(0x10, DEF_STR(Off))
+ PORT_DIPNAME(0x80, 0x00, "Operator Mode")
+ PORT_DIPSETTING(0x00, DEF_STR(No))
+ PORT_DIPSETTING(0x80, DEF_STR(Yes))
INPUT_PORTS_END
static INPUT_PORTS_START( bbh )
PORT_INCLUDE( iteagle )
+ // bbhsc is low resolution only, bbhsc version 1.60.01 will set low resolution automatically
+ PORT_MODIFY("SW5")
+ PORT_DIPNAME(0x3, 0x0, "Resolution")
+ PORT_DIPSETTING(0x1, "Medium" )
+ PORT_DIPSETTING(0x0, "Low" )
+ PORT_DIPSETTING(0x2, "Low_Alt" )
+
PORT_MODIFY("IN1")
PORT_BIT( 0x0004, IP_ACTIVE_LOW, IPT_BUTTON1 ) PORT_NAME( "Trigger" )
PORT_BIT( 0x0008, IP_ACTIVE_LOW, IPT_BUTTON3 ) PORT_NAME( "Pump" )
PORT_BIT( 0x0010, IP_ACTIVE_LOW, IPT_UNUSED )
PORT_BIT( 0x0020, IP_ACTIVE_LOW, IPT_UNUSED )
+ PORT_MODIFY("SYSTEM")
+ // bbhsc and bbh2sp only work with seconday targeting
+ PORT_DIPNAME(0x0020, 0x20, "Targeting")
+ PORT_DIPSETTING(0x00, "Regular")
+ PORT_DIPSETTING(0x20, "Secondary")
+
PORT_MODIFY("GUNX1")
- PORT_BIT( 0x1ff, 0x100, IPT_LIGHTGUN_X )
- PORT_SENSITIVITY(50) PORT_KEYDELTA(10)
+ PORT_BIT( 0x3ff, 0x200, IPT_LIGHTGUN_X )
+ PORT_SENSITIVITY(50) PORT_KEYDELTA(24)
PORT_CROSSHAIR(X, 1.0, 0.0, 0)
PORT_MODIFY("GUNY1")
PORT_BIT( 0x1ff, 0x100, IPT_LIGHTGUN_Y )
- PORT_SENSITIVITY(50) PORT_KEYDELTA(10) PORT_MINMAX(0, 383)
+ PORT_SENSITIVITY(50) PORT_KEYDELTA(12)
PORT_CROSSHAIR(Y, 1.0, 0.0, 0)
INPUT_PORTS_END
+static INPUT_PORTS_START( bbh2 )
+ PORT_INCLUDE( bbh )
+
+ // Default bbh2sp and bbhcotw to medium resolution
+ PORT_MODIFY("SW5")
+ PORT_DIPNAME(0x3, 0x1, "Resolution")
+ PORT_DIPSETTING(0x1, "Medium" )
+ PORT_DIPSETTING(0x0, "Low" )
+ PORT_DIPSETTING(0x2, "Low_Alt" )
+
+ PORT_MODIFY("GUNX1")
+ PORT_BIT( 0x1ff, 0x100, IPT_LIGHTGUN_X )
+ PORT_SENSITIVITY(50) PORT_KEYDELTA(12)
+ PORT_CROSSHAIR(X, 1.0, 0.0, 0)
+INPUT_PORTS_END
+
/*************************************
*
* ROM definition(s)
@@ -551,10 +613,18 @@ ROM_START( bbhsc )
ROM_LOAD( "bb15-us.u53", 0x0000, 0x0880, NO_DUMP )
DISK_REGION( PCI_ID_IDE":ide:0:hdd:image" )
+ DISK_IMAGE("bbhsc_v1.60.01", 0, SHA1(8554fdd7193ee27c0fe8ca921aa8db9c0378b313)) /* Build 09:50:13, May 29 2002 */
+ROM_END
+
+ROM_START( bbhsca )
+ EAGLE_BIOS
+
+ ROM_REGION( 0x0880, "atmel", 0 ) /* Atmel 90S2313 AVR internal CPU code */
+ ROM_LOAD( "bb15-us.u53", 0x0000, 0x0880, NO_DUMP )
+
+ DISK_REGION( PCI_ID_IDE":ide:0:hdd:image" )
DISK_IMAGE( "bbhsc_v1.50.07_cf", 0, SHA1(21dcf1f7e5ab901ac64e6afb099c35e273b3bf1f) ) /* Build 16:35:34, Feb 26 2002 - 4gb Compact Flash conversion */
ROM_END
- //DISK_IMAGE( "bbhsc_v1.50.07_cf", 0, SHA1(21dcf1f7e5ab901ac64e6afb099c35e273b3bf1f) ) /* Build 16:35:34, Feb 26 2002 - 4gb Compact Flash conversion */
- //DISK_IMAGE( "bbhsc_v1.60.01", 0, SHA1(8554fdd7193ee27c0fe8ca921aa8db9c0378b313) )
ROM_START( bbh2sp )
EAGLE_BIOS
@@ -586,7 +656,7 @@ ROM_END
*************************************/
GAME( 2000, iteagle, 0, iteagle, iteagle, iteagle_state, 0, ROT0, "Incredible Technologies", "Eagle BIOS", MACHINE_IS_BIOS_ROOT )
-GAME( 1998, virtpool, iteagle, virtpool, virtpool, iteagle_state, 0, ROT0, "Incredible Technologies", "Virtual Pool", MACHINE_NOT_WORKING | MACHINE_SUPPORTS_SAVE ) // random lockups on loading screens
+GAME( 1998, virtpool, iteagle, virtpool, virtpool, iteagle_state, 0, ROT0, "Incredible Technologies", "Virtual Pool", MACHINE_IMPERFECT_GRAPHICS | MACHINE_SUPPORTS_SAVE )
GAME( 2002, carnking, iteagle, carnking, bbh, iteagle_state, 0, ROT0, "Incredible Technologies", "Carnival King (v1.00.11)", MACHINE_SUPPORTS_SAVE )
GAME( 2000, gtfore01, iteagle, gtfore01, iteagle, iteagle_state, 0, ROT0, "Incredible Technologies", "Golden Tee Fore! (v1.00.25)", MACHINE_SUPPORTS_SAVE )
GAME( 2001, gtfore02, iteagle, gtfore02, iteagle, iteagle_state, 0, ROT0, "Incredible Technologies", "Golden Tee Fore! 2002 (v2.01.06)", MACHINE_SUPPORTS_SAVE )
@@ -599,6 +669,7 @@ GAME( 2004, gtfore05a, gtfore05, gtfore05, iteagle, iteagle_state, 0, ROT0, "I
GAME( 2004, gtfore05b, gtfore05, gtfore05, iteagle, iteagle_state, 0, ROT0, "Incredible Technologies", "Golden Tee Fore! 2005 Extra (v5.01.00)", MACHINE_SUPPORTS_SAVE )
GAME( 2004, gtfore05c, gtfore05, gtfore05, iteagle, iteagle_state, 0, ROT0, "Incredible Technologies", "Golden Tee Fore! 2005 Extra (v5.00.00)", MACHINE_SUPPORTS_SAVE )
GAME( 2005, gtfore06, iteagle, gtfore06, iteagle, iteagle_state, 0, ROT0, "Incredible Technologies", "Golden Tee Fore! 2006 Complete (v6.00.01)", MACHINE_SUPPORTS_SAVE )
-GAME( 2002, bbhsc, iteagle, bbhsc, bbh, iteagle_state, 0, ROT0, "Incredible Technologies", "Big Buck Hunter - Shooter's Challenge (v1.50.07)", MACHINE_NOT_WORKING | MACHINE_SUPPORTS_SAVE ) // doesn't boot
-GAME( 2002, bbh2sp, iteagle, bbh2sp, bbh, iteagle_state, 0, ROT0, "Incredible Technologies", "Big Buck Hunter II - Sportsman's Paradise (v2.02.11)", MACHINE_NOT_WORKING | MACHINE_SUPPORTS_SAVE ) // SW51-2 needs to be off
-GAME( 2006, bbhcotw, iteagle, bbhcotw, bbh, iteagle_state, 0, ROT0, "Incredible Technologies", "Big Buck Hunter Call of the Wild (v3.02.5)", MACHINE_NOT_WORKING | MACHINE_SUPPORTS_SAVE ) // random lockups
+GAME( 2002, bbhsc, iteagle, bbhsc, bbh, iteagle_state, 0, ROT0, "Incredible Technologies", "Big Buck Hunter - Shooter's Challenge (v1.60.01)", MACHINE_NOT_WORKING | MACHINE_SUPPORTS_SAVE ) // random lockups
+GAME( 2002, bbhsca, bbhsc, bbhsc, bbh, iteagle_state, 0, ROT0, "Incredible Technologies", "Big Buck Hunter - Shooter's Challenge (v1.50.07)", MACHINE_NOT_WORKING | MACHINE_SUPPORTS_SAVE ) // random lockups
+GAME( 2002, bbh2sp, iteagle, bbh2sp, bbh2, iteagle_state, 0, ROT0, "Incredible Technologies", "Big Buck Hunter II - Sportsman's Paradise (v2.02.11)", MACHINE_NOT_WORKING | MACHINE_SUPPORTS_SAVE ) // SW51-2 needs to be off
+GAME( 2006, bbhcotw, iteagle, bbhcotw, bbh2, iteagle_state, 0, ROT0, "Incredible Technologies", "Big Buck Hunter Call of the Wild (v3.02.5)", MACHINE_NOT_WORKING | MACHINE_SUPPORTS_SAVE ) // random lockups
diff --git a/src/mame/machine/iteagle_fpga.cpp b/src/mame/machine/iteagle_fpga.cpp
index 46920a33874..1de747e9862 100644
--- a/src/mame/machine/iteagle_fpga.cpp
+++ b/src/mame/machine/iteagle_fpga.cpp
@@ -26,17 +26,20 @@ DEVICE_ADDRESS_MAP_START(rtc_map, 32, iteagle_fpga_device)
ADDRESS_MAP_END
DEVICE_ADDRESS_MAP_START(ram_map, 32, iteagle_fpga_device)
- AM_RANGE(0x00000, 0x1ffff) AM_READWRITE(ram_r, ram_w)
+ AM_RANGE(0x00000, 0x40) AM_READWRITE(e1_nvram_r, e1_nvram_w)
+ AM_RANGE(0x10000, 0x1ffff) AM_READWRITE(e1_ram_r, e1_ram_w)
ADDRESS_MAP_END
iteagle_fpga_device::iteagle_fpga_device(const machine_config &mconfig, const char *tag, device_t *owner, uint32_t clock)
: pci_device(mconfig, ITEAGLE_FPGA, tag, owner, clock),
- m_rtc(*this, "eagle2_rtc"), m_scc1(*this, AM85C30_TAG), m_version(0), m_seq_init(0)
+ m_rtc(*this, "eagle2_rtc"), m_e1_nvram(*this, "eagle1_bram"), m_scc1(*this, AM85C30_TAG), m_version(0), m_seq_init(0)
{
}
MACHINE_CONFIG_MEMBER(iteagle_fpga_device::device_add_mconfig)
MCFG_NVRAM_ADD_0FILL("eagle2_rtc")
+ MCFG_NVRAM_ADD_1FILL("eagle1_bram")
+
// RS232 serial ports
// The console terminal (com1) operates at 38400 baud
MCFG_SCC85C30_ADD(AM85C30_TAG, XTAL_7_3728MHz, XTAL_7_3728MHz, 0, XTAL_7_3728MHz, 0)
@@ -57,9 +60,14 @@ MACHINE_CONFIG_END
void iteagle_fpga_device::device_start()
{
+ m_screen = downcast<screen_device *>(machine().device("screen"));
+
// RTC M48T02
m_rtc->set_base(m_rtc_regs, sizeof(m_rtc_regs));
+ // Eagle 1 nvram
+ m_e1_nvram->set_base(m_e1_nv_data, sizeof(m_e1_nv_data));
+
pci_device::device_start();
status = 0x5555;
command = 0x5555;
@@ -72,26 +80,16 @@ void iteagle_fpga_device::device_start()
// RTC defaults to base address 0x000c0000
bank_infos[1].adr = 0x000c0000 & (~(bank_infos[1].size - 1));
- add_map(sizeof(m_ram), M_MEM, FUNC(iteagle_fpga_device::ram_map));
+ add_map(0x20000, M_MEM, FUNC(iteagle_fpga_device::ram_map));
// RAM defaults to base address 0x000e0000
bank_infos[2].adr = 0x000e0000 & (~(bank_infos[2].size - 1));
m_timer = timer_alloc(0, nullptr);
- // virtpool nvram
- memset(m_ram, 0, sizeof(m_ram));
- // byte 0x10 is check sum of first 16 bytes
- // when corrupt the fw writes the following
- m_ram[0x00/4] = 0x00010207;
- m_ram[0x04/4] = 0x04010101;
- m_ram[0x08/4] = 0x01030101;
- m_ram[0x0c/4] = 0x00000001;
- m_ram[0x10/4] = 0x00000018;
-
// Save states
save_item(NAME(m_fpga_regs));
save_item(NAME(m_rtc_regs));
- save_item(NAME(m_ram));
+ save_item(NAME(m_e1_ram));
save_item(NAME(m_prev_reg));
// m_version
save_item(NAME(m_seq_init));
@@ -110,10 +108,11 @@ void iteagle_fpga_device::device_reset()
m_seq_rem2 = 0;
// Nibble starting at bit 20 is resolution, byte 0 is atmel response
+ // Bit 16 is Eagle 1 battery ok
// 0x00080000 and interrupt starts reading from 0x14
// 0x02000000 and interrupt starts reading from 0x18
// Write 0x01000000 is a global interrupt clear
- m_fpga_regs[0x04/4] = 0x00000000;
+ m_fpga_regs[0x04/4] = 0x00010000;
m_prev_reg = 0;
m_serial0_1.reset();
@@ -183,20 +182,41 @@ void iteagle_fpga_device::update_sequence_eg1(uint32_t data)
//-------------------------------------------------
void iteagle_fpga_device::device_timer(emu_timer &timer, device_timer_id tid, int param, void *ptr)
{
- if (m_fpga_regs[0x4/4] & 0x01000000) {
- //m_fpga_regs[0x04/4] |= 0x02080000;
- m_fpga_regs[0x04/4] |= 0x00080000;
- m_cpu->set_input_line(m_irq_num, ASSERT_LINE);
+ //int beamy = m_screen->vpos();
+ //const rectangle &visarea = m_screen->visible_area();
+ //beamy++;
+ //if (beamy <= m_screen->visible_area().max_y && beamy <= m_gun_y + BEAM_DY) {
+ // m_timer->adjust(m_screen->time_until_pos(beamy, std::max(0, m_gun_x - BEAM_DX)));
+ //}
+ //m_fpga_regs[0x04/4] |= 0x02080000;
+ m_fpga_regs[0x04 / 4] |= 0x00080000;
+ m_cpu->set_input_line(m_irq_num, ASSERT_LINE);
+ if (LOG_FPGA)
+ logerror("%s:fpga device_timer Setting interrupt(%i)\n", machine().describe_context(), m_irq_num);
+}
+
+WRITE_LINE_MEMBER(iteagle_fpga_device::vblank_update)
+{
+ m_vblank_state = state;
+ if (state && m_fpga_regs[0x4 / 4] & 0x01000000) {
+ //m_cpu->set_input_line(m_irq_num, ASSERT_LINE);
+ if (1 || (m_fpga_regs[0x14 / 4] & 0x01)) {
+ // Set the gun timer to first fire
+ const rectangle &visarea = m_screen->visible_area();
+ m_gun_x = machine().root_device().ioport("GUNX1")->read() * (visarea.width() - 14) / 512;
+ m_gun_y = machine().root_device().ioport("GUNY1")->read() * visarea.height() / 512;
+ m_timer->adjust(attotime::zero);
+ //m_timer->adjust(m_screen->time_until_pos(std::max(0, m_gun_y - BEAM_DY), std::max(0, m_gun_x - BEAM_DX)));
+ //printf("w: %d h: %d x: %d y: %d\n", visarea.width(), visarea.height(), m_gun_x, m_gun_y);
+ }
if (LOG_FPGA)
- logerror("%s:fpga device_timer Setting interrupt(%i)\n", machine().describe_context(), m_irq_num);
+ logerror("%s:fpga vblank_update Setting interrupt(%i)\n", machine().describe_context(), m_irq_num);
}
-
}
WRITE_LINE_MEMBER(iteagle_fpga_device::serial_interrupt)
{
if (LOG_SERIAL) {
- osd_printf_info("iteagle_fpga_device::serial_interrupt: intr(%i) = %i\n", m_serial_irq_num, state);
logerror("serial_interrupt: intr(%i) = %i\n", m_serial_irq_num, state);
}
m_cpu->set_input_line(m_serial_irq_num, state);
@@ -209,7 +229,6 @@ WRITE8_MEMBER(iteagle_fpga_device::serial_rx_w)
//osd_printf_info("serial_rx_w: %02x\n", data);
m_serial0_1.write_rx_str(1, tmpStr);
if (0 && m_serial0_1.check_interrupt()) {
- osd_printf_info("serial_rx_w: %02x\n", data);
m_cpu->set_input_line(m_serial_irq_num, ASSERT_LINE);
}
}
@@ -235,7 +254,8 @@ READ32_MEMBER( iteagle_fpga_device::fpga_r )
logerror("%s:fpga_r offset %04X = %08X & %08X\n", machine().describe_context(), offset*4, result, mem_mask);
break;
case 0x14/4: // GUN1-- Interrupt & 0x4==0x00080000
- result = ((machine().root_device().ioport("GUNY1")->read())<<16) | (machine().root_device().ioport("GUNX1")->read());
+ //result = ((machine().root_device().ioport("GUNY1")->read())<<16) | (machine().root_device().ioport("GUNX1")->read());
+ result = (m_gun_y << 16) | (m_gun_x << 0);
if (LOG_FPGA)
logerror("%s:fpga_r offset %04X = %08X & %08X\n", machine().describe_context(), offset*4, result, mem_mask);
break;
@@ -266,7 +286,7 @@ READ32_MEMBER( iteagle_fpga_device::fpga_r )
result |= m_scc1->da_r(space, offset) << 24;
if (LOG_SERIAL) m_serial0_1.read_data(0);
}
- if (1 && LOG_FPGA)
+ if (0 && LOG_FPGA && m_prev_reg != offset)
logerror("%s:fpga_r offset %04X = %08X & %08X\n", machine().describe_context(), offset*4, result, mem_mask);
break;
case 0x1c/4:
@@ -325,8 +345,6 @@ WRITE32_MEMBER( iteagle_fpga_device::fpga_w )
} else if (ACCESSING_BITS_24_31 && (data & 0x01000000)) {
// Interrupt clear/enable
m_cpu->set_input_line(m_irq_num, CLEAR_LINE);
- // Not sure what value to use here, needed for lightgun
- m_timer->adjust(attotime::from_hz(59));
if (LOG_FPGA)
logerror("%s:fpga_w offset %04X = %08X & %08X Clearing interrupt(%i)\n", machine().describe_context(), offset*4, data, mem_mask, m_irq_num);
} else {
@@ -468,6 +486,8 @@ void iteagle_am85c30::write_control(uint8_t data, int channel)
m_wr_regs[channel][0] = 0;
// Mirror wr2 to rr2[chan0]
m_rr_regs[0][2] = m_wr_regs[channel][2];
+ if (addr == 12 || addr == 13)
+ m_rr_regs[channel][addr] = data;
}
}
@@ -583,21 +603,38 @@ WRITE32_MEMBER( iteagle_fpga_device::rtc_w )
}
//*************************************
+//* FPGA NV RAM -- Eagle 1 only
+//*************************************
+READ32_MEMBER(iteagle_fpga_device::e1_nvram_r)
+{
+ uint32_t result = m_e1_nv_data[offset];
+ if (LOG_RAM)
+ logerror("FPGA e1_nvram_r from offset %04X = %08X & %08X\n", offset * 4, result, mem_mask);
+ return result;
+}
+
+WRITE32_MEMBER(iteagle_fpga_device::e1_nvram_w)
+{
+ COMBINE_DATA(&m_e1_nv_data[offset]);
+ if (LOG_RAM)
+ logerror("FPGA e1_ram_w to offset %04X = %08X & %08X\n", offset * 4, data, mem_mask);
+}
+//*************************************
//* FPGA RAM -- Eagle 1 only
//*************************************
-READ32_MEMBER( iteagle_fpga_device::ram_r )
+READ32_MEMBER( iteagle_fpga_device::e1_ram_r )
{
- uint32_t result = m_ram[offset];
+ uint32_t result = m_e1_ram[offset];
if (LOG_RAM)
- logerror("%s:FPGA ram_r from offset %04X = %08X & %08X\n", machine().describe_context(), offset*4, result, mem_mask);
+ logerror("%s:FPGA e1_ram_r from offset %04X = %08X & %08X\n", machine().describe_context(), offset*4, result, mem_mask);
return result;
}
-WRITE32_MEMBER( iteagle_fpga_device::ram_w )
+WRITE32_MEMBER( iteagle_fpga_device::e1_ram_w )
{
- COMBINE_DATA(&m_ram[offset]);
+ COMBINE_DATA(&m_e1_ram[offset]);
if (LOG_RAM)
- logerror("%s:FPGA ram_w to offset %04X = %08X & %08X\n", machine().describe_context(), offset*4, data, mem_mask);
+ logerror("%s:FPGA e1_ram_w to offset %04X = %08X & %08X\n", machine().describe_context(), offset*4, data, mem_mask);
}
//************************************
@@ -760,7 +797,11 @@ void iteagle_periph_device::device_reset()
{
pci_device::device_reset();
memset(m_ctrl_regs, 0, sizeof(m_ctrl_regs));
- m_ctrl_regs[0x10/4] = 0x00000000; // 0x6=No SIMM, 0x2, 0x1, 0x0 = SIMM . Top 16 bits are compared to 0x3. Bit 0 might be lan chip present.
+ // Bit 0: might be lan chip present.
+ // Bit 1: 0 == 8 Meg Ram @ 0x0
+ // Bit 1: 1 == 32 Meg Simm @ 0x0, 8 Meg Ram @ 0x02000000
+ // Top 16 bits are compared to 0x3
+ m_ctrl_regs[0x10/4] = 0x00040002;
}
READ32_MEMBER( iteagle_periph_device::ctrl_r )
@@ -775,26 +816,32 @@ READ32_MEMBER( iteagle_periph_device::ctrl_r )
break;
case 0x70/4:
if (ACCESSING_BITS_8_15) {
- // get the current date/time from the core
- machine().current_datetime(systime);
- m_rtc_regs[0] = dec_2_bcd(systime.local_time.second);
- m_rtc_regs[1] = 0x00; // Seconds Alarm
- m_rtc_regs[2] = dec_2_bcd(systime.local_time.minute);
- m_rtc_regs[3] = 0x00; // Minutes Alarm
- m_rtc_regs[4] = dec_2_bcd(systime.local_time.hour);
- m_rtc_regs[5] = 0x00; // Hours Alarm
-
- m_rtc_regs[6] = dec_2_bcd((systime.local_time.weekday != 0) ? systime.local_time.weekday : 7);
- m_rtc_regs[7] = dec_2_bcd(systime.local_time.mday);
- m_rtc_regs[8] = dec_2_bcd(systime.local_time.month + 1);
- m_rtc_regs[9] = dec_2_bcd(systime.local_time.year - 1900); // Epoch is 1900
- //m_rtc_regs[9] = 0x99; // Use 1998
- //m_rtc_regs[0xa] &= ~0x10; // Reg A Status
- //m_ctrl_regs[0xb] &= 0x10; // Reg B Status
- //m_ctrl_regs[0xc] &= 0x10; // Reg C Interrupt Status
- m_rtc_regs[0xd] = 0x80; // Reg D Valid time/ram Status
+ if (m_rtc_regs[m_ctrl_regs[0x70 / 4] & 0xff] < 0x10) {
+ // get the current date/time from the core
+ machine().current_datetime(systime);
+ m_rtc_regs[0] = dec_2_bcd(systime.local_time.second);
+ m_rtc_regs[1] = 0x00; // Seconds Alarm
+ m_rtc_regs[2] = dec_2_bcd(systime.local_time.minute);
+ m_rtc_regs[3] = 0x00; // Minutes Alarm
+ m_rtc_regs[4] = dec_2_bcd(systime.local_time.hour);
+ m_rtc_regs[5] = 0x00; // Hours Alarm
+
+ m_rtc_regs[6] = dec_2_bcd((systime.local_time.weekday != 0) ? systime.local_time.weekday : 7);
+ m_rtc_regs[7] = dec_2_bcd(systime.local_time.mday);
+ m_rtc_regs[8] = dec_2_bcd(systime.local_time.month + 1);
+ m_rtc_regs[9] = dec_2_bcd(systime.local_time.year - 1900); // Epoch is 1900
+ //m_rtc_regs[9] = 0x99; // Use 1998
+ //m_rtc_regs[0xa] &= ~0x10; // Reg A Status
+ //m_ctrl_regs[0xb] &= 0x10; // Reg B Status
+ //m_ctrl_regs[0xc] &= 0x10; // Reg C Interrupt Status
+ m_rtc_regs[0xd] = 0x80; // Reg D Valid time/ram Status
+ }
result = (result & 0xffff00ff) | (m_rtc_regs[m_ctrl_regs[0x70/4]&0xff]<<8);
}
+ else if (ACCESSING_BITS_24_31) {
+ // High 128 bytes of rtc ram
+ result = (result & 0x00ffffff) | (m_rtc_regs[m_ctrl_regs[0x72 / 4] & 0xff] << 24);
+ }
if (LOG_PERIPH)
logerror("%s:fpga ctrl_r from offset %04X = %08X & %08X\n", machine().describe_context(), offset*4, result, mem_mask);
break;
diff --git a/src/mame/machine/iteagle_fpga.h b/src/mame/machine/iteagle_fpga.h
index 5b0e7a76a7a..3de9d831b50 100644
--- a/src/mame/machine/iteagle_fpga.h
+++ b/src/mame/machine/iteagle_fpga.h
@@ -11,6 +11,7 @@
#include "machine/eepromser.h"
#include "machine/z80scc.h"
#include "bus/rs232/rs232.h"
+#include "screen.h"
//MCFG_PCI_DEVICE_ADD(_tag, _type, _main_id, _revision, _pclass, _subsystem_id)
@@ -58,12 +59,15 @@ public:
iteagle_fpga_device(const machine_config &mconfig, const char *tag, device_t *owner, uint32_t clock);
required_device<nvram_device> m_rtc;
+ optional_device<nvram_device> m_e1_nvram;
required_device<scc85c30_device> m_scc1;
+ screen_device *m_screen;
void set_init_info(int version, int seq_init) {m_version=version; m_seq_init=seq_init;}
void set_irq_info(const char *tag, const int irq_num, const int serial_num) {
m_cpu_tag = tag; m_irq_num = irq_num; m_serial_irq_num = serial_num;}
+ DECLARE_WRITE_LINE_MEMBER(vblank_update);
DECLARE_WRITE8_MEMBER(serial_rx_w);
protected:
@@ -81,7 +85,8 @@ private:
uint32_t m_fpga_regs[0x20 / 4];
uint32_t m_rtc_regs[0x800 / 4];
- uint32_t m_ram[0x20000 / 4];
+ uint32_t m_e1_nv_data[0x40 / 4];
+ uint32_t m_e1_ram[0x10000 / 4];
uint32_t m_prev_reg;
uint32_t m_version;
@@ -89,6 +94,9 @@ private:
uint32_t m_seq;
uint32_t m_seq_rem1, m_seq_rem2;
+ int m_vblank_state;
+ int m_gun_x, m_gun_y;
+
iteagle_am85c30 m_serial0_1;
iteagle_am85c30 m_serial2_3;
@@ -104,8 +112,10 @@ private:
DECLARE_READ32_MEMBER( rtc_r );
DECLARE_WRITE32_MEMBER( rtc_w );
- DECLARE_READ32_MEMBER( ram_r );
- DECLARE_WRITE32_MEMBER( ram_w );
+ DECLARE_READ32_MEMBER(e1_nvram_r);
+ DECLARE_WRITE32_MEMBER(e1_nvram_w);
+ DECLARE_READ32_MEMBER( e1_ram_r );
+ DECLARE_WRITE32_MEMBER( e1_ram_w );
DECLARE_WRITE_LINE_MEMBER(serial_interrupt);
};
diff --git a/src/mame/mame.lst b/src/mame/mame.lst
index 7b42a691815..dae13788636 100644
--- a/src/mame/mame.lst
+++ b/src/mame/mame.lst
@@ -15247,6 +15247,7 @@ istreb //
bbh2sp //
bbhcotw //
bbhsc //
+bbhsca //
carnking //
gtfore01 //
gtfore02 //