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author Lord-Nightmare <Lord-Nightmare@users.noreply.github.com>2017-03-17 12:30:20 -0400
committer Lord-Nightmare <Lord-Nightmare@users.noreply.github.com>2017-03-17 12:30:20 -0400
commit4ba2a062cb349722f01a1f76e24db94629538f4f (patch)
treecc6407ea6c216ff4bb118b871d1767acf08a313f
parenta0f580638717fa6892c554b7f358f80409f3a169 (diff)
uPD7725: Fix LSB-first bit ordering for SO reg, not used yet. [Lord Nightmare]
-rw-r--r--src/devices/cpu/upd7725/upd7725.cpp4
1 files changed, 2 insertions, 2 deletions
diff --git a/src/devices/cpu/upd7725/upd7725.cpp b/src/devices/cpu/upd7725/upd7725.cpp
index 8f443bb3973..11ecca2a82a 100644
--- a/src/devices/cpu/upd7725/upd7725.cpp
+++ b/src/devices/cpu/upd7725/upd7725.cpp
@@ -586,8 +586,8 @@ void necdsp_device::exec_ld(uint32_t opcode) {
m_out_p0_cb(regs.sr&0x1);
m_out_p1_cb((regs.sr&0x2)>>1);
break;
- case 8: regs.so = id; break; //LSB
- case 9: regs.so = id; break; //MSB
+ case 8: regs.so = BITSWAP16(id, 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15); break; //LSB first output, output tapped at bit 15 shifting left
+ case 9: regs.so = id; break; //MSB first output, output tapped at bit 15 shifting left
case 10: regs.k = id; break;
case 11: regs.k = id; regs.l = m_data->read_word(regs.rp<<1); break;
case 12: regs.l = id; regs.k = dataRAM[regs.dp | 0x40]; break;