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author angelosa <lordkale4@gmail.com>2018-06-29 00:11:12 +0200
committer angelosa <lordkale4@gmail.com>2018-06-29 04:41:45 +0200
commit4b6a420df5e9f1e928186ebd2fef2df0fec4fe83 (patch)
tree6270de8478dd26de4b8f2466adcc92ad3259b47c
parent5854421008cff352a3cbd82c8e27f9830d15017a (diff)
cischeat.cpp: reworked interrupt generation, fixed attract mode desyncs in Big Run [Angelo Salese]
-rw-r--r--src/mame/drivers/cischeat.cpp29
1 files changed, 19 insertions, 10 deletions
diff --git a/src/mame/drivers/cischeat.cpp b/src/mame/drivers/cischeat.cpp
index 314c0e757c9..20639f5812e 100644
--- a/src/mame/drivers/cischeat.cpp
+++ b/src/mame/drivers/cischeat.cpp
@@ -227,7 +227,7 @@ void cischeat_state::bigrun_map(address_map &map)
map(0x082308, 0x082309).w(FUNC(cischeat_state::cischeat_comms_w));
map(0x082400, 0x082401).w(FUNC(cischeat_state::active_layers_w));
- /* It's actually 0x840000-0x847ff, divided in four banks and shared with other boards.
+ /* It's actually 0x84000-0x847ff, divided in four banks and shared with other boards.
Each board expects reads from the other boards and writes to own bank.
Amusingly, if you run the communication test as ID = X then soft reset -> ID = Y, what was at ID = X gets an OK in the second test
so it's likely to be the only thing needed. */
@@ -421,7 +421,7 @@ void wildplt_state::wildplt_map(address_map &map)
map(0x082308, 0x082309).nopr().w(FUNC(cischeat_state::f1gpstar_comms_w));
map(0x082400, 0x082401).w(FUNC(cischeat_state::active_layers_w));
-// AM_RANGE(0x088000, 0x088fff) AM_RAM // Linking with other units
+// map(0x088000, 0x088fff).ram(); // Linking with other units (not present on this)
map(0x090000, 0x097fff).ram().share("share2"); // Sharedram with sub CPU#2
map(0x098000, 0x09ffff).ram().share("share1"); // Sharedram with sub CPU#1
@@ -1914,22 +1914,31 @@ GFXDECODE_END
Big Run, Cisco Heat, F1 GrandPrix Star
**************************************************************************/
-/*
- irq 1 is comms related, presumably the bridge chip is capable of sending the irq signal at given times. Wild Pilot of course doesn't need it.
- irq 2/4 controls gameplay speed, currently unknown about the timing
- */
+// TODO: irq generation is unknown, as usual with Jaleco/NMK HW
+// - irq 1 is comms related, presumably the bridge chip is capable of sending the irq signal at given times.
+// Wild Pilot of course doesn't need it.
+// - irq 2/4 controls gameplay speed, currently unknown about the timing
+// - 2 updates palettes while 4 is vblank?
+// - Calling 2 every frame causes attract mode to desync in Big Run.
+// - Not calling 1 in Big Run causes service mode to not work at all, so even if the comms doesn't work
+// something still triggers it somehow?
TIMER_DEVICE_CALLBACK_MEMBER(cischeat_state::bigrun_scanline)
{
int scanline = param;
+
+ if(m_screen->frame_number() & 1)
+ {
+ if(scanline == 240)
+ m_cpu1->set_input_line(1, HOLD_LINE);
+
+ return;
+ }
if(scanline == 240) // vblank-out irq
- m_cpu1->set_input_line(m_screen->frame_number() & 1 ? 4 : 1, HOLD_LINE);
+ m_cpu1->set_input_line(4, HOLD_LINE);
if(scanline == 0)
m_cpu1->set_input_line(2, HOLD_LINE);
-
-// if(scanline == 69)
-// m_cpu1->set_input_line(1, HOLD_LINE);
}
WRITE_LINE_MEMBER(cischeat_state::sound_irq)