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authorGravatarGravatar mamehaze <mamehaze@users.noreply.github.com>2014-12-03 14:51:54 +0000
committerGravatarGravatar mamehaze <mamehaze@users.noreply.github.com>2014-12-03 14:51:54 +0000
commit4476c481f4b0af46fb7d4012184451519b0dbe16 (patch) (github)
tree035d55d34a1ad413e46373e71797a04cd4cdaaa1
parentf7f3a6e9d2da2c1943c65fbf13dc3ee3b5cc2dc1 (diff)
downloadmame-4476c481f4b0af46fb7d4012184451519b0dbe16.tar.bz2
mame-4476c481f4b0af46fb7d4012184451519b0dbe16.zip
misc arc (nw)
-rw-r--r--src/emu/cpu/arc/arc.c2
-rw-r--r--src/emu/cpu/arc/arc.h2
-rw-r--r--src/emu/cpu/arc/arcdasm.c4
-rw-r--r--src/emu/cpu/arcompact/arcompact.c22
-rw-r--r--src/emu/cpu/arcompact/arcompact.h6
-rw-r--r--src/emu/cpu/arcompact/arcompactdasm.c131
6 files changed, 153 insertions, 14 deletions
diff --git a/src/emu/cpu/arc/arc.c b/src/emu/cpu/arc/arc.c
index a0c142373df..4bc688ce92d 100644
--- a/src/emu/cpu/arc/arc.c
+++ b/src/emu/cpu/arc/arc.c
@@ -40,7 +40,7 @@ void arc_device::unimplemented_opcode(UINT16 op)
/*****************************************************************************/
-UINT16 arc_device::READ32(UINT32 address)
+UINT32 arc_device::READ32(UINT32 address)
{
return m_program->read_dword(address << 2);
}
diff --git a/src/emu/cpu/arc/arc.h b/src/emu/cpu/arc/arc.h
index 20b1a3e0910..d4783531ff3 100644
--- a/src/emu/cpu/arc/arc.h
+++ b/src/emu/cpu/arc/arc.h
@@ -62,7 +62,7 @@ private:
UINT32 m_debugger_temp;
void unimplemented_opcode(UINT16 op);
- inline UINT16 READ32(UINT32 address);
+ inline UINT32 READ32(UINT32 address);
inline void WRITE32(UINT32 address, UINT32 data);
};
diff --git a/src/emu/cpu/arc/arcdasm.c b/src/emu/cpu/arc/arcdasm.c
index b3b0c2820db..b1fa5d442b1 100644
--- a/src/emu/cpu/arc/arcdasm.c
+++ b/src/emu/cpu/arc/arcdasm.c
@@ -175,13 +175,13 @@ static const char *regnames[0x40] =
/* 0x3f */ "sImm NF",
};
-#define ARC_CONDITION ((op & 0x0000001f) >> 0 )
+#define ARC_CONDITION ((op & 0x0000001f) >> 0 ) // aka Q
// used in jumps
#define ARC_BRANCH_DELAY ((op & 0x00000060) >> 5 ) // aka N
#define ARC_BRANCH_ADDR ((op & 0x07ffff80) >> 7 ) // aka L
-#define ARC_OPERATION ((op & 0xf8000000) >> 27) // aka Q
+#define ARC_OPERATION ((op & 0xf8000000) >> 27)
#define ARC_REGOP_DEST ((op & 0x07e00000) >> 21 ) // aka A
#define ARC_REGOP_OP1 ((op & 0x001f8000) >> 15 ) // aka B
diff --git a/src/emu/cpu/arcompact/arcompact.c b/src/emu/cpu/arcompact/arcompact.c
index 847551ab8c2..703ab5bf94f 100644
--- a/src/emu/cpu/arcompact/arcompact.c
+++ b/src/emu/cpu/arcompact/arcompact.c
@@ -26,7 +26,7 @@ const device_type ARCA5 = &device_creator<arcompact_device>;
arcompact_device::arcompact_device(const machine_config &mconfig, const char *tag, device_t *owner, UINT32 clock)
: cpu_device(mconfig, ARCA5, "ARCtangent-A5", tag, owner, clock, "arca5", __FILE__)
- , m_program_config("program", ENDIANNESS_BIG, 32, 24, 0) // some docs describe these as 'middle endian'?!
+ , m_program_config("program", ENDIANNESS_LITTLE, 32, 32, 0) // some docs describe these as 'middle endian'?!
{
}
@@ -49,7 +49,7 @@ void arcompact_device::unimplemented_opcode(UINT16 op)
/*****************************************************************************/
-UINT16 arcompact_device::READ32(UINT32 address)
+UINT32 arcompact_device::READ32(UINT32 address)
{
return m_program->read_dword(address << 2);
}
@@ -59,6 +59,17 @@ void arcompact_device::WRITE32(UINT32 address, UINT32 data)
m_program->write_dword(address << 2, data);
}
+UINT16 arcompact_device::READ16(UINT32 address)
+{
+ return m_program->read_word(address << 1);
+}
+
+void arcompact_device::WRITE16(UINT32 address, UINT16 data)
+{
+ m_program->write_word(address << 1, data);
+}
+
+
/*****************************************************************************/
void arcompact_device::device_start()
@@ -80,11 +91,11 @@ void arcompact_device::state_export(const device_state_entry &entry)
switch (entry.index())
{
case 0:
- m_debugger_temp = m_pc << 2;
+ m_debugger_temp = m_pc << 1;
break;
case STATE_GENPC:
- m_debugger_temp = m_pc << 2;
+ m_debugger_temp = m_pc << 1;
break;
}
}
@@ -94,7 +105,7 @@ void arcompact_device::state_import(const device_state_entry &entry)
switch (entry.index())
{
case 0:
- m_pc = (m_debugger_temp & 0xfffffffc) >> 2;
+ m_pc = (m_debugger_temp & 0xfffffffe) >> 1;
break;
}
}
@@ -123,6 +134,7 @@ void arcompact_device::execute_run()
//UINT32 op = READ32(m_pc);
+
m_pc++;
m_icount--;
diff --git a/src/emu/cpu/arcompact/arcompact.h b/src/emu/cpu/arcompact/arcompact.h
index 9f91696cec6..bedef23f5d5 100644
--- a/src/emu/cpu/arcompact/arcompact.h
+++ b/src/emu/cpu/arcompact/arcompact.h
@@ -50,8 +50,12 @@ private:
UINT32 m_debugger_temp;
void unimplemented_opcode(UINT16 op);
- inline UINT16 READ32(UINT32 address);
+ inline UINT32 READ32(UINT32 address);
inline void WRITE32(UINT32 address, UINT32 data);
+ inline UINT16 READ16(UINT32 address);
+ inline void WRITE16(UINT32 address, UINT16 data);
+
+
};
diff --git a/src/emu/cpu/arcompact/arcompactdasm.c b/src/emu/cpu/arcompact/arcompactdasm.c
index 92319b7e23c..af8e4256f6b 100644
--- a/src/emu/cpu/arcompact/arcompactdasm.c
+++ b/src/emu/cpu/arcompact/arcompactdasm.c
@@ -25,15 +25,138 @@ static void ATTR_PRINTF(1,2) print(const char *fmt, ...)
/*****************************************************************************/
+static const char *basic[0x20] =
+{
+ /* opcode below are 32-bit mode */
+ /* 00 */ "Bcc",
+ /* 01 */ "BLcc/BRcc",
+ /* 02 */ "LD r+o",
+ /* 03 */ "ST r+o",
+ /* 04 */ "op a,b,c (basecase)", // basecase ops
+ /* 05 */ "op a,b,c (05 ARC ext)", // ARC processor specific extensions
+ /* 06 */ "op a,b,c (06 ARC ext)",
+ /* 07 */ "op a,b,c (07 User ext)", // User speciifc extensions
+ /* 08 */ "op a,b,c (08 User ext)",
+ /* 09 */ "op a,b,c (09 Market ext)", // Market specific extensions
+ /* 0a */ "op a,b,c (0a Market ext)",
+ /* 0b */ "op a,b,c (0b Market ext)",
+ /* opcodes below are 16-bit mode */
+ /* 0c */ "Load/Add reg-reg",
+ /* 0d */ "Add/Sub/Shft imm",
+ /* 0e */ "Mov/Cmp/Add",
+ /* 0f */ "op_S b,b,c", // single ops
+ /* 10 */ "LD_S",
+ /* 11 */ "LDB_S",
+ /* 12 */ "LDW_S",
+ /* 13 */ "LSW_S.X",
+ /* 14 */ "ST_S",
+ /* 15 */ "STB_S",
+ /* 16 */ "STW_S",
+ /* 17 */ "Shift/Sub/Bit",
+ /* 18 */ "Stack Instr",
+ /* 19 */ "GP Instr",
+ /* 1a */ "PCL Instr",
+ /* 1b */ "MOV_S",
+ /* 1c */ "ADD_S/CMP_S",
+ /* 1d */ "BRcc_S",
+ /* 1e */ "Bcc_S",
+ /* 1f */ "BL_S"
+};
+
+// condition codes (basic ones are the same as arc
+static const char *conditions[0x20] =
+{
+ /* 00 */ "AL", // (aka RA - Always)
+ /* 01 */ "EQ", // (aka Z - Zero
+ /* 02 */ "NE", // (aka NZ - Non-Zero)
+ /* 03 */ "PL", // (aka P - Positive)
+ /* 04 */ "MI", // (aka N - Negative)
+ /* 05 */ "CS", // (aka C, LO - Carry set / Lower than) (unsigned)
+ /* 06 */ "CC", // (aka CC, NC, HS - Carry Clear / Higher or Same) (unsigned)
+ /* 07 */ "VS", // (aka V - Overflow set)
+ /* 08 */ "VC", // (aka NV - Overflow clear)
+ /* 09 */ "GT", // ( - Greater than) (signed)
+ /* 0a */ "GE", // ( - Greater than or Equal) (signed)
+ /* 0b */ "LT", // ( - Less than) (signed)
+ /* 0c */ "LE", // ( - Less than or Equal) (signed)
+ /* 0d */ "HI", // ( - Higher than) (unsigned)
+ /* 0e */ "LS", // ( - Lower or Same) (unsigned)
+ /* 0f */ "PNZ",// ( - Positive non-0 value)
+ /* 10 */ "0x10 Reserved", // possible CPU implementation specifics
+ /* 11 */ "0x11 Reserved",
+ /* 12 */ "0x12 Reserved",
+ /* 13 */ "0x13 Reserved",
+ /* 14 */ "0x14 Reserved",
+ /* 15 */ "0x15 Reserved",
+ /* 16 */ "0x16 Reserved",
+ /* 17 */ "0x17 Reserved",
+ /* 18 */ "0x18 Reserved",
+ /* 19 */ "0x19 Reserved",
+ /* 1a */ "0x1a Reserved",
+ /* 1b */ "0x1b Reserved",
+ /* 1c */ "0x1c Reserved",
+ /* 1d */ "0x1d Reserved",
+ /* 1e */ "0x1e Reserved",
+ /* 1f */ "0x1f Reserved"
+};
+
+#define ARCOMPACT_OPERATION ((op & 0xf800) >> 11)
CPU_DISASSEMBLE(arcompact)
{
- UINT32 op = oprom[0] | (oprom[1] << 8) | (oprom[2] << 16) | (oprom[3] << 24);
- op = BIG_ENDIANIZE_INT32(op);
+ int size = 2;
+ UINT32 op = oprom[0] | (oprom[1] << 8);
output = buffer;
- print("<undefined>");
+ UINT8 instruction = ARCOMPACT_OPERATION;
+
+ if (instruction < 0x0c)
+ {
+ size = 4;
+ op <<= 16;
+ op |= oprom[2] | (oprom[3] << 8);
+
+ switch (instruction)
+ {
+ case 0x00:
+ if (op & 0x00010000)
+ { // Branch Unconditionally Far
+ // 00000 ssssssssss 1 SSSSSSSSSS N 0 TTTT
+ UINT32 address = (op & 0x07fe0000) >> 17;
+ address |= ((op & 0x0000ffc0) >> 6) << 10;
+ address |= ((op & 0x0000000f) >> 0) << 20;
+
+ print("B %08x (%08x)", address<<1, op & ~0xffffffcf );
+ }
+ else
+ { // Branch Conditionally
+ // 00000 ssssssssss 0 SSSSSSSSSS N QQQQQ
+ UINT32 address = (op & 0x07fe0000) >> 17;
+ address |= ((op & 0x0000ffc0) >> 6) << 10;
+
+ UINT8 condition = op & 0x0000001f;
+
+ print("B(%s) %08x (%08x)", conditions[condition], address<<1, op & ~0xffffffdf );
+
+ }
+
+ break;
+
+ default:
+ print("%s (%08x)", basic[instruction], op & ~0xf8000000 );
+ break;
+
+ }
+
+
+ }
+ else
+ {
+ size = 2;
+ print("%s (%04x)", basic[instruction], op & ~0xf800 );
+ }
+
- return 4 | DASMFLAG_SUPPORTED;
+ return size | DASMFLAG_SUPPORTED;
}