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author Lord-Nightmare <Lord-Nightmare@users.noreply.github.com>2020-11-08 07:53:41 -0500
committer Lord-Nightmare <Lord-Nightmare@users.noreply.github.com>2020-11-08 07:53:41 -0500
commit4410b37e13a16a8b21758b2ed6785197554d0d35 (patch)
treedad9eff75d208a5c9671fa42439454517f7ad31f
parent5bc88b1af53b4a16c3b487cb7411b5d22c8ff523 (diff)
video/avgdvg.cpp: Fix a bug (pre-dating the recent conversion to bitswap) in the sparkle LFSR preset load value, and add a comment explaining what the source is for bits 4, 5 and 6 of the preset load value. [Lord Nightmare]
-rw-r--r--src/mame/video/avgdvg.cpp2
1 files changed, 1 insertions, 1 deletions
diff --git a/src/mame/video/avgdvg.cpp b/src/mame/video/avgdvg.cpp
index 27d57109897..fe8727d5688 100644
--- a/src/mame/video/avgdvg.cpp
+++ b/src/mame/video/avgdvg.cpp
@@ -771,7 +771,7 @@ int avg_mhavoc_device::handler_6() // mhavoc_strobe2
if (m_dvy & 0x800)
{
m_enspkl = 1;
- m_spkl_shift = bitswap<4>(m_dvy, 1, 1, 2, 3) | ((machine().rand() & 0x7) << 4);
+ m_spkl_shift = bitswap<4>(m_dvy, 0, 1, 2, 3) | ((machine().rand() & 0x7) << 4); // sparkle lfsr bits 4,5,6 here come from address bus bits 0,1,2 from the alpha cpu, they're not truly random.
}
else
{