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author dxl <41547105+hp9k@users.noreply.github.com>2018-11-06 22:15:27 +0100
committer R. Belmont <rb6502@users.noreply.github.com>2018-11-06 16:15:26 -0500
commit407929b50c4d8756c7c619e2021bc39ef1f9cc45 (patch)
tree72d841216ed4fc65ae857f40e95b3370584b98c2
parent31fd4d6a5fa6604c06521159971ddbb56cabec65 (diff)
Hpux final fixes (#4257)
* m68kmmu: Set B bit in ATC on buserror (nw) * m68kmmu: store last logical address for bus error handler (nw) * hp9k_3xx: update /370 to 48MB configuration (nw) It was the maximum configuration on /370, and allows us to have a pretty usable HP VUE Environment.
-rw-r--r--src/devices/cpu/m68000/m68000.h1
-rw-r--r--src/devices/cpu/m68000/m68kmmu.h30
-rw-r--r--src/mame/drivers/hp9k_3xx.cpp6
3 files changed, 29 insertions, 8 deletions
diff --git a/src/devices/cpu/m68000/m68000.h b/src/devices/cpu/m68000/m68000.h
index 64656832919..2edbfa8bdf8 100644
--- a/src/devices/cpu/m68000/m68000.h
+++ b/src/devices/cpu/m68000/m68000.h
@@ -293,6 +293,7 @@ protected:
uint16_t m_mmu_tmp_buserror_sz; /* temporary hack: (first) bus error size` */
bool m_mmu_tablewalk; /* set when MMU walks page tables */
+ uint32_t m_mmu_last_logical_addr;
uint32_t m_ic_address[M68K_IC_SIZE]; /* instruction cache address data */
uint32_t m_ic_data[M68K_IC_SIZE]; /* instruction cache content data */
bool m_ic_valid[M68K_IC_SIZE]; /* instruction cache valid flags */
diff --git a/src/devices/cpu/m68000/m68kmmu.h b/src/devices/cpu/m68000/m68kmmu.h
index 6f87afe27f6..ccc1a061994 100644
--- a/src/devices/cpu/m68000/m68kmmu.h
+++ b/src/devices/cpu/m68000/m68kmmu.h
@@ -500,6 +500,8 @@ uint32_t pmmu_translate_addr_with_fc(uint32_t addr_in, uint8_t fc, bool rw, cons
__func__, addr_in, fc, ptest, rw, limit);
m_mmu_tmp_sr = 0;
+ m_mmu_last_logical_addr = addr_in;
+
if (pmmu_match_tt(addr_in, fc, m_mmu_tt0, rw) ||
pmmu_match_tt(addr_in, fc, m_mmu_tt1, rw) ||
fc == 7)
@@ -1262,13 +1264,31 @@ inline uint32_t hmmu_translate_addr(uint32_t addr_in)
}
public:
-int m68851_buserror()
+int m68851_buserror(uint32_t& addr)
{
- if (!m_mmu_tablewalk)
+ if (!m_pmmu_enabled)
{
return false;
}
- MMULOG("buserror during table walk\n");
- m_mmu_tmp_sr |= M68K_MMU_SR_BUS_ERROR|M68K_MMU_SR_INVALID;
- return true;
+
+ if (m_mmu_tablewalk)
+ {
+ MMULOG("buserror during table walk\n");
+ m_mmu_tmp_sr |= M68K_MMU_SR_BUS_ERROR|M68K_MMU_SR_INVALID;
+ return true;
+ }
+
+
+ const int ps = (m_mmu_tc >> 16) & 0xf;
+ for(int i = 0; i < MMU_ATC_ENTRIES; i++)
+ {
+ if ((m_mmu_atc_tag[i] & M68K_MMU_ATC_VALID) &&
+ ((m_mmu_atc_data[i] >> ps) << (ps -8)) == ((addr >> ps) << (ps == 8)))
+ {
+ MMULOG("%s: set B in ATC entry %d\n", __func__, i);
+ m_mmu_atc_data[i] |= M68K_MMU_ATC_BUSERROR;
+ }
+ }
+ addr = m_mmu_last_logical_addr;
+ return false;
}
diff --git a/src/mame/drivers/hp9k_3xx.cpp b/src/mame/drivers/hp9k_3xx.cpp
index b2e2585f65e..29061c95c82 100644
--- a/src/mame/drivers/hp9k_3xx.cpp
+++ b/src/mame/drivers/hp9k_3xx.cpp
@@ -187,12 +187,12 @@ void hp9k3xx_state::hp9k360_map(address_map &map)
map(0xff000000, 0xffffffff).ram();
}
-// 9000/370 - 8 MB RAM standard
+// 9000/370 - with 48 MB RAM (max. configuration)
void hp9k3xx_state::hp9k370_map(address_map &map)
{
hp9k3xx_common(map);
// main memory
- map(0xff800000, 0xffffffff).ram();
+ map(0xfd000000, 0xffffffff).ram();
}
// 9000/380 - '040
@@ -285,7 +285,7 @@ void hp9k3xx_state::add_dio32_bus(machine_config &config)
void hp9k3xx_state::set_bus_error(uint32_t address, bool rw, uint16_t mem_mask)
{
- if (m_maincpu->m68851_buserror())
+ if (m_maincpu->m68851_buserror(address))
return;
if (m_bus_error)