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author Roberto Fresca <robbie@robertofresca.com>2018-09-02 02:14:29 +0200
committer Roberto Fresca <robbie@robertofresca.com>2018-09-02 02:14:29 +0200
commit30efff8c13c60751781e43122c36fb34e2e6b198 (patch)
tree09bac68b4656ec59243823eac682c0520810de8c
parent40ff8a384e30a3f2e968ab1546606ac039a52b77 (diff)
Lucky Ball 96: Changes to the memory map and banking
after an exhaustive hardware analysis. [Grull Osgo]
-rw-r--r--src/mame/drivers/luckybal.cpp7
1 files changed, 2 insertions, 5 deletions
diff --git a/src/mame/drivers/luckybal.cpp b/src/mame/drivers/luckybal.cpp
index c63a8e5f30c..5527821d3db 100644
--- a/src/mame/drivers/luckybal.cpp
+++ b/src/mame/drivers/luckybal.cpp
@@ -262,7 +262,7 @@
*********************************************************************/
-#define CPU_CLOCK XTAL(12'000'000)
+#define CPU_CLOCK XTAL(12'000'000) // 12MHz. from schematics.
#define MCU_CLOCK XTAL(8'000'000)
#define VID_CLOCK XTAL(21'477'272)
@@ -340,10 +340,7 @@ private:
void luckybal_state::main_map(address_map &map)
{
- map(0x0000, 0x57ff).rom();
- map(0x6000, 0x7fff).bankr("bank1"); // Banked ROM.
- map(0x8000, 0x9fff).bankr("bank1"); // Banked ROM.
- map(0xa000, 0xbfff).bankr("bank1"); // Banked ROM.
+ map(0x0000, 0xbfff).rom();
map(0xc000, 0xdfff).bankr("bank1"); // Banked ROM.
map(0xe000, 0xffff).ram().share("nvram"); // 6264 SRAM
}