diff options
author | Robbbert <Robbbert@users.noreply.github.com> | 2020-06-07 23:36:23 +1000 |
---|---|---|
committer | Robbbert <Robbbert@users.noreply.github.com> | 2020-06-07 23:36:23 +1000 |
commit | 30c89549f8d8018fbd058a6b5a46070be715be1c (patch) | |
tree | ddceeab6f555fb9cd5caa911ea15b41bdf768ac3 | |
parent | e7d7489361ea0aee753a5bf76fa6a6b619474e1b (diff) |
(nw) aussiebyte: don't write to regions
-rw-r--r-- | src/mame/drivers/aussiebyte.cpp | 160 | ||||
-rw-r--r-- | src/mame/includes/aussiebyte.h | 89 | ||||
-rw-r--r-- | src/mame/video/aussiebyte.cpp | 48 |
3 files changed, 138 insertions, 159 deletions
diff --git a/src/mame/drivers/aussiebyte.cpp b/src/mame/drivers/aussiebyte.cpp index a8256bd35eb..2004e423783 100644 --- a/src/mame/drivers/aussiebyte.cpp +++ b/src/mame/drivers/aussiebyte.cpp @@ -43,15 +43,15 @@ ************************************************************/ -void aussiebyte_state::aussiebyte_map(address_map &map) +void aussiebyte_state::mem_map(address_map &map) { map(0x0000, 0x3fff).bankr("bankr0").bankw("bankw0"); map(0x4000, 0x7fff).bankrw("bank1"); map(0x8000, 0xbfff).bankrw("bank2"); - map(0xc000, 0xffff).ram().region("mram", 0x0000); + map(0xc000, 0xffff).bankrw("bank3"); } -void aussiebyte_state::aussiebyte_io(address_map &map) +void aussiebyte_state::io_map(address_map &map) { map.global_mask(0xff); map.unmap_value_high(); @@ -97,7 +97,7 @@ INPUT_PORTS_END I/O Ports ************************************************************/ -void aussiebyte_state::port15_w(uint8_t data) +void aussiebyte_state::port15_w(u8 data) { membank("bankr0")->set_entry(m_port15); // point at ram m_port15 = true; @@ -115,7 +115,7 @@ void aussiebyte_state::port15_w(uint8_t data) 5 Disable 5.25 inch floppy spindle motors. 6 Unused. 7 Enable write precompensation on WD2797 controller. */ -void aussiebyte_state::port16_w(uint8_t data) +void aussiebyte_state::port16_w(u8 data) { floppy_image_device *m_floppy = nullptr; if ((data & 15) == 0) @@ -142,7 +142,7 @@ void aussiebyte_state::port16_w(uint8_t data) 5 - SIO Ch D 6 - Ext ready 1 7 - Ext ready 2 */ -void aussiebyte_state::port17_w(uint8_t data) +void aussiebyte_state::port17_w(u8 data) { m_port17 = data & 7; m_dma->rdy_w(BIT(m_port17_rdy, data)); @@ -151,19 +151,19 @@ void aussiebyte_state::port17_w(uint8_t data) /* FDC params 2 EXC: WD2797 clock frequency. H = 5.25"; L = 8" 3 WIEN: WD2797 Double density select. */ -void aussiebyte_state::port18_w(uint8_t data) +void aussiebyte_state::port18_w(u8 data) { m_fdc->set_unscaled_clock(BIT(data, 2) ? 1e6 : 2e6); m_fdc->dden_w(BIT(data, 3)); } -uint8_t aussiebyte_state::port19_r() +u8 aussiebyte_state::port19_r() { return m_port19; } // Memory banking -void aussiebyte_state::port1a_w(uint8_t data) +void aussiebyte_state::port1a_w(u8 data) { data &= 7; switch (data) @@ -208,23 +208,23 @@ void aussiebyte_state::port1a_w(uint8_t data) } // Winchester control -void aussiebyte_state::port1b_w(uint8_t data) +void aussiebyte_state::port1b_w(u8 data) { } // GPEHB control -void aussiebyte_state::port1c_w(uint8_t data) +void aussiebyte_state::port1c_w(u8 data) { } -void aussiebyte_state::port20_w(uint8_t data) +void aussiebyte_state::port20_w(u8 data) { m_speaker->level_w(BIT(data, 7)); m_rtc->cs_w(BIT(data, 0)); m_rtc->hold_w(BIT(data, 0)); } -uint8_t aussiebyte_state::port28_r() +u8 aussiebyte_state::port28_r() { return m_port28; } @@ -234,16 +234,16 @@ uint8_t aussiebyte_state::port28_r() RTC ************************************************************/ -uint8_t aussiebyte_state::rtc_r(offs_t offset) +u8 aussiebyte_state::rtc_r(offs_t offset) { m_rtc->read_w(1); m_rtc->address_w(offset); - uint8_t data = m_rtc->data_r(); + u8 data = m_rtc->data_r(); m_rtc->read_w(0); return data; } -void aussiebyte_state::rtc_w(offs_t offset, uint8_t data) +void aussiebyte_state::rtc_w(offs_t offset, u8 data) { m_rtc->address_w(offset); m_rtc->data_w(data); @@ -256,25 +256,25 @@ void aussiebyte_state::rtc_w(offs_t offset, uint8_t data) DMA ************************************************************/ -uint8_t aussiebyte_state::memory_read_byte(offs_t offset) +u8 aussiebyte_state::memory_read_byte(offs_t offset) { address_space& prog_space = m_maincpu->space(AS_PROGRAM); return prog_space.read_byte(offset); } -void aussiebyte_state::memory_write_byte(offs_t offset, uint8_t data) +void aussiebyte_state::memory_write_byte(offs_t offset, u8 data) { address_space& prog_space = m_maincpu->space(AS_PROGRAM); prog_space.write_byte(offset, data); } -uint8_t aussiebyte_state::io_read_byte(offs_t offset) +u8 aussiebyte_state::io_read_byte(offs_t offset) { address_space& prog_space = m_maincpu->space(AS_IO); return prog_space.read_byte(offset); } -void aussiebyte_state::io_write_byte(offs_t offset, uint8_t data) +void aussiebyte_state::io_write_byte(offs_t offset, u8 data) { address_space& prog_space = m_maincpu->space(AS_IO); prog_space.write_byte(offset, data); @@ -294,28 +294,28 @@ WRITE_LINE_MEMBER( aussiebyte_state::busreq_w ) ************************************************************/ WRITE_LINE_MEMBER( aussiebyte_state::sio1_rdya_w ) { - m_port17_rdy = (m_port17_rdy & 0xfd) | (uint8_t)(state << 1); + m_port17_rdy = (m_port17_rdy & 0xfd) | (u8)(state << 1); if (m_port17 == 1) m_dma->rdy_w(state); } WRITE_LINE_MEMBER( aussiebyte_state::sio1_rdyb_w ) { - m_port17_rdy = (m_port17_rdy & 0xfb) | (uint8_t)(state << 2); + m_port17_rdy = (m_port17_rdy & 0xfb) | (u8)(state << 2); if (m_port17 == 2) m_dma->rdy_w(state); } WRITE_LINE_MEMBER( aussiebyte_state::sio2_rdya_w ) { - m_port17_rdy = (m_port17_rdy & 0xef) | (uint8_t)(state << 4); + m_port17_rdy = (m_port17_rdy & 0xef) | (u8)(state << 4); if (m_port17 == 4) m_dma->rdy_w(state); } WRITE_LINE_MEMBER( aussiebyte_state::sio2_rdyb_w ) { - m_port17_rdy = (m_port17_rdy & 0xdf) | (uint8_t)(state << 5); + m_port17_rdy = (m_port17_rdy & 0xdf) | (u8)(state << 5); if (m_port17 == 5) m_dma->rdy_w(state); } @@ -365,56 +365,22 @@ static const z80_daisy_config daisy_chain_intf[] = /*********************************************************** - CTC - -************************************************************/ - -// baud rate generator. All inputs are 1.2288MHz. -WRITE_LINE_MEMBER( aussiebyte_state::ctc_z2_w ) -{ - m_ctc->trg3(1); - m_ctc->trg3(0); -} - -/*********************************************************** - - Centronics ack - -************************************************************/ -WRITE_LINE_MEMBER( aussiebyte_state::write_centronics_busy ) -{ - m_centronics_busy = state; -} - -/*********************************************************** - - Speech ack - -************************************************************/ -WRITE_LINE_MEMBER( aussiebyte_state::votrax_w ) -{ - m_port28 = state; -} - - -/*********************************************************** - Floppy Disk ************************************************************/ WRITE_LINE_MEMBER( aussiebyte_state::fdc_intrq_w ) { - uint8_t data = (m_port19 & 0xbf) | (state ? 0x40 : 0); + u8 data = (m_port19 & 0xbf) | (state ? 0x40 : 0); m_port19 = data; } WRITE_LINE_MEMBER( aussiebyte_state::fdc_drq_w ) { - uint8_t data = (m_port19 & 0x7f) | (state ? 0x80 : 0); + u8 data = (m_port19 & 0x7f) | (state ? 0x80 : 0); m_port19 = data; state ^= 1; // inverter on pin38 of fdc - m_port17_rdy = (m_port17_rdy & 0xfe) | (uint8_t)state; + m_port17_rdy = (m_port17_rdy & 0xfe) | (u8)state; if (m_port17 == 0) m_dma->rdy_w(state); } @@ -457,9 +423,9 @@ QUICKLOAD_LOAD_MEMBER(aussiebyte_state::quickload_cb) } /* Load image to the TPA (Transient Program Area) */ - for (uint16_t i = 0; i < quickload_size; i++) + for (u16 i = 0; i < quickload_size; i++) { - uint8_t data; + u8 data; if (image.fread( &data, 1) != 1) return image_init_result::FAIL; prog_space.write_byte(i+0x100, data); @@ -492,15 +458,52 @@ void aussiebyte_state::machine_reset() membank("bankw0")->set_entry(1); // always write to ram membank("bank1")->set_entry(2); membank("bank2")->set_entry(3); + membank("bank3")->set_entry(0); m_maincpu->reset(); } +void aussiebyte_state::machine_start() +{ + m_vram = std::make_unique<u8[]>(0x10000); + m_aram = std::make_unique<u8[]>(0x800); + m_ram = make_unique_clear<u8[]>(0x40000); + save_pointer(NAME(m_vram), 0x10000); + save_pointer(NAME(m_aram), 0x800); + save_pointer(NAME(m_ram), 0x40000); + save_item(NAME(m_port15)); + save_item(NAME(m_port17)); + save_item(NAME(m_port17_rdy)); + save_item(NAME(m_port19)); + save_item(NAME(m_port1a)); + save_item(NAME(m_port28)); + save_item(NAME(m_port34)); + save_item(NAME(m_port35)); + save_item(NAME(m_video_index)); + save_item(NAME(m_cnt)); + save_item(NAME(m_alpha_address)); + save_item(NAME(m_graph_address)); + save_item(NAME(m_centronics_busy)); + + // Main ram is divided into 16k blocks (0-15). The boot rom is block number 16. + // For convenience, bank 0 is permanently assigned to C000-FFFF + u8 *main = memregion("roms")->base(); + u8 *ram = m_ram.get(); + + membank("bankr0")->configure_entries(0, 16, ram, 0x4000); + membank("bankw0")->configure_entries(0, 16, ram, 0x4000); + membank("bank1")->configure_entries(0, 16, ram, 0x4000); + membank("bank2")->configure_entries(0, 16, ram, 0x4000); + membank("bank3")->configure_entries(0, 1, ram, 0x4000); + membank("bankr0")->configure_entry(16, &main[0x0000]); +} + + void aussiebyte_state::aussiebyte(machine_config &config) { /* basic machine hardware */ Z80(config, m_maincpu, 16_MHz_XTAL / 4); - m_maincpu->set_addrmap(AS_PROGRAM, &aussiebyte_state::aussiebyte_map); - m_maincpu->set_addrmap(AS_IO, &aussiebyte_state::aussiebyte_io); + m_maincpu->set_addrmap(AS_PROGRAM, &aussiebyte_state::mem_map); + m_maincpu->set_addrmap(AS_IO, &aussiebyte_state::io_map); m_maincpu->set_daisy_config(daisy_chain_intf); /* video hardware */ @@ -515,13 +518,13 @@ void aussiebyte_state::aussiebyte(machine_config &config) SPEAKER(config, "mono").front_center(); SPEAKER_SOUND(config, m_speaker).add_route(ALL_OUTPUTS, "mono", 0.50); VOTRAX_SC01(config, m_votrax, 720000); // 720kHz? needs verify - m_votrax->ar_callback().set(FUNC(aussiebyte_state::votrax_w)); + m_votrax->ar_callback().set([this] (bool state) { m_port28 = state ? 0 : 1; }); m_votrax->add_route(ALL_OUTPUTS, "mono", 1.00); /* devices */ CENTRONICS(config, m_centronics, centronics_devices, "printer"); m_centronics->set_data_input_buffer("cent_data_in"); - m_centronics->busy_handler().set(FUNC(aussiebyte_state::write_centronics_busy)); + m_centronics->busy_handler().set([this] (bool state) { m_centronics_busy = state; }); INPUT_BUFFER(config, "cent_data_in"); output_latch_device ¢_data_out(OUTPUT_LATCH(config, "cent_data_out")); m_centronics->set_output_latch(cent_data_out); @@ -536,7 +539,7 @@ void aussiebyte_state::aussiebyte(machine_config &config) m_ctc->zc_callback<1>().set("sio1", FUNC(z80sio_device::rxtxcb_w)); m_ctc->zc_callback<1>().append("sio2", FUNC(z80sio_device::rxca_w)); m_ctc->zc_callback<1>().append("sio2", FUNC(z80sio_device::txca_w)); - m_ctc->zc_callback<2>().set(FUNC(aussiebyte_state::ctc_z2_w)); // SIO2 Ch B, CTC Ch 3 + m_ctc->zc_callback<2>().set("ctc", FUNC(z80ctc_device::trg3)); m_ctc->zc_callback<2>().append("sio2", FUNC(z80sio_device::rxtxcb_w)); Z80DMA(config, m_dma, 16_MHz_XTAL / 4); @@ -597,21 +600,6 @@ void aussiebyte_state::aussiebyte(machine_config &config) } -void aussiebyte_state::machine_start() -{ - // Main ram is divided into 16k blocks (0-15). The boot rom is block number 16. - // For convenience, bank 0 is permanently assigned to C000-FFFF - uint8_t *main = memregion("roms")->base(); - uint8_t *ram = memregion("mram")->base(); - - membank("bankr0")->configure_entries(0, 16, &ram[0x0000], 0x4000); - membank("bankw0")->configure_entries(0, 16, &ram[0x0000], 0x4000); - membank("bank1")->configure_entries(0, 16, &ram[0x0000], 0x4000); - membank("bank2")->configure_entries(0, 16, &ram[0x0000], 0x4000); - membank("bankr0")->configure_entry(16, &main[0x0000]); -} - - /*********************************************************** Game driver @@ -625,11 +613,7 @@ ROM_START(aussieby) ROM_REGION(0x800, "chargen", 0) ROM_LOAD( "8002.bin", 0x0000, 0x0800, CRC(fdd6eb13) SHA1(a094d416e66bdab916e72238112a6265a75ca690) ) - - ROM_REGION(0x40000, "mram", ROMREGION_ERASE00) // main ram, 256k dynamic - ROM_REGION(0x10000, "vram", ROMREGION_ERASEFF) // video ram, 64k dynamic - ROM_REGION(0x00800, "aram", ROMREGION_ERASEFF) // attribute ram, 2k static ROM_END // YEAR NAME PARENT COMPAT MACHINE INPUT CLASS INIT COMPANY FULLNAME FLAGS -COMP( 1984, aussieby, 0, 0, aussiebyte, aussiebyte, aussiebyte_state, empty_init, "SME Systems", "Aussie Byte II", MACHINE_IMPERFECT_GRAPHICS ) +COMP( 1984, aussieby, 0, 0, aussiebyte, aussiebyte, aussiebyte_state, empty_init, "SME Systems", "Aussie Byte II", MACHINE_IMPERFECT_GRAPHICS | MACHINE_SUPPORTS_SAVE ) diff --git a/src/mame/includes/aussiebyte.h b/src/mame/includes/aussiebyte.h index 488b8f249ff..856c6f44de1 100644 --- a/src/mame/includes/aussiebyte.h +++ b/src/mame/includes/aussiebyte.h @@ -48,8 +48,6 @@ public: , m_palette(*this, "palette") , m_maincpu(*this, "maincpu") , m_p_chargen(*this, "chargen") - , m_p_videoram(*this, "vram") - , m_p_attribram(*this, "aram") , m_ctc(*this, "ctc") , m_dma(*this, "dma") , m_pio1(*this, "pio1") @@ -69,68 +67,65 @@ public: DECLARE_QUICKLOAD_LOAD_MEMBER(quickload_cb); -protected: - uint8_t memory_read_byte(offs_t offset); - void memory_write_byte(offs_t offset, uint8_t data); - uint8_t io_read_byte(offs_t offset); - void io_write_byte(offs_t offset, uint8_t data); - DECLARE_WRITE_LINE_MEMBER(write_centronics_busy); - void port15_w(uint8_t data); - void port16_w(uint8_t data); - void port17_w(uint8_t data); - void port18_w(uint8_t data); - uint8_t port19_r(); - void port1a_w(uint8_t data); - void port1b_w(uint8_t data); - void port1c_w(uint8_t data); - void port20_w(uint8_t data); - uint8_t port28_r(); - uint8_t port33_r(); - void port34_w(uint8_t data); - void port35_w(uint8_t data); - uint8_t port36_r(); - uint8_t port37_r(); - uint8_t rtc_r(offs_t offset); - void rtc_w(offs_t offset, uint8_t data); +private: + u8 memory_read_byte(offs_t offset); + void memory_write_byte(offs_t offset, u8 data); + u8 io_read_byte(offs_t offset); + void io_write_byte(offs_t offset, u8 data); + void port15_w(u8 data); + void port16_w(u8 data); + void port17_w(u8 data); + void port18_w(u8 data); + u8 port19_r(); + void port1a_w(u8 data); + void port1b_w(u8 data); + void port1c_w(u8 data); + void port20_w(u8 data); + u8 port28_r(); + u8 port33_r(); + void port34_w(u8 data); + void port35_w(u8 data); + u8 port36_r(); + u8 port37_r(); + u8 rtc_r(offs_t offset); + void rtc_w(offs_t offset, u8 data); DECLARE_WRITE_LINE_MEMBER(fdc_intrq_w); DECLARE_WRITE_LINE_MEMBER(fdc_drq_w); DECLARE_WRITE_LINE_MEMBER(busreq_w); - DECLARE_WRITE_LINE_MEMBER(votrax_w); DECLARE_WRITE_LINE_MEMBER(sio1_rdya_w); DECLARE_WRITE_LINE_MEMBER(sio1_rdyb_w); DECLARE_WRITE_LINE_MEMBER(sio2_rdya_w); DECLARE_WRITE_LINE_MEMBER(sio2_rdyb_w); - DECLARE_WRITE_LINE_MEMBER(ctc_z2_w); - void address_w(uint8_t data); - void register_w(uint8_t data); + void address_w(u8 data); + void register_w(u8 data); MC6845_UPDATE_ROW(crtc_update_row); MC6845_ON_UPDATE_ADDR_CHANGED(crtc_update_addr); virtual void machine_start() override; virtual void machine_reset() override; - void aussiebyte_io(address_map &map); - void aussiebyte_map(address_map &map); + void io_map(address_map &map); + void mem_map(address_map &map); -private: - uint8_t crt8002(uint8_t ac_ra, uint8_t ac_chr, uint8_t ac_attr, uint16_t ac_cnt, bool ac_curs); + u8 crt8002(u8 ac_ra, u8 ac_chr, u8 ac_attr, u16 ac_cnt, bool ac_curs); bool m_port15; // rom switched in (0), out (1) - uint8_t m_port17; - uint8_t m_port17_rdy; - uint8_t m_port19; - uint8_t m_port1a; // bank to switch to when write to port 15 happens - uint8_t m_port28; - uint8_t m_port34; - uint8_t m_port35; // byte to be written to vram or aram - uint8_t m_video_index; - uint16_t m_cnt; - uint16_t m_alpha_address; - uint16_t m_graph_address; - int m_centronics_busy; + u8 m_port17; + u8 m_port17_rdy; + u8 m_port19; + u8 m_port1a; // bank to switch to when write to port 15 happens + u8 m_port28; + u8 m_port34; + u8 m_port35; // byte to be written to vram or aram + u8 m_video_index; + u16 m_cnt; + u16 m_alpha_address; + u16 m_graph_address; + bool m_centronics_busy; + std::unique_ptr<u8[]> m_vram; // video ram, 64k dynamic + std::unique_ptr<u8[]> m_aram; // attribute ram, 2k static + std::unique_ptr<u8[]> m_ram; // main ram, 256k dynamic required_device<palette_device> m_palette; required_device<z80_device> m_maincpu; required_region_ptr<u8> m_p_chargen; - required_region_ptr<u8> m_p_videoram; - required_region_ptr<u8> m_p_attribram; required_device<z80ctc_device> m_ctc; required_device<z80dma_device> m_dma; required_device<z80pio_device> m_pio1; diff --git a/src/mame/video/aussiebyte.cpp b/src/mame/video/aussiebyte.cpp index 5a24027e773..faf67b30126 100644 --- a/src/mame/video/aussiebyte.cpp +++ b/src/mame/video/aussiebyte.cpp @@ -21,7 +21,7 @@ ************************************************************/ // dummy read port, forces requested action to happen -uint8_t aussiebyte_state::port33_r() +u8 aussiebyte_state::port33_r() { return 0xff; } @@ -34,30 +34,30 @@ d5 - /SRRD - controls write of data to either vram or aram (1=vram, 0=aram) d6 - /VWR - 0 = enable write vdata to vram, read from aram to vdata ; 1 = enable write to aram from vdata d7 - OE on port 35 */ -void aussiebyte_state::port34_w(uint8_t data) +void aussiebyte_state::port34_w(u8 data) { m_port34 = data; } -void aussiebyte_state::port35_w(uint8_t data) +void aussiebyte_state::port35_w(u8 data) { m_port35 = data; } -uint8_t aussiebyte_state::port36_r() +u8 aussiebyte_state::port36_r() { if (BIT(m_port34, 5)) { - if (BIT(m_p_attribram[m_alpha_address & 0x7ff], 7)) - return m_p_videoram[m_alpha_address]; + if (BIT(m_aram[m_alpha_address & 0x7ff], 7)) + return m_vram[m_alpha_address]; else - return m_p_videoram[m_graph_address]; + return m_vram[m_graph_address]; } else - return m_p_attribram[m_alpha_address & 0x7ff]; + return m_aram[m_alpha_address & 0x7ff]; } -uint8_t aussiebyte_state::port37_r() +u8 aussiebyte_state::port37_r() { return m_crtc->de_r() ? 0xff : 0xfe; } @@ -74,7 +74,7 @@ MC6845_ON_UPDATE_ADDR_CHANGED( aussiebyte_state::crtc_update_addr ) // m_video_address = address;// & 0x7ff; } -void aussiebyte_state::address_w(uint8_t data) +void aussiebyte_state::address_w(u8 data) { m_crtc->address_w(data); @@ -88,20 +88,20 @@ void aussiebyte_state::address_w(uint8_t data) if (BIT(m_port34, 5)) { - if (BIT(m_p_attribram[m_alpha_address & 0x7ff], 7)) - m_p_videoram[m_alpha_address] = m_port35; + if (BIT(m_aram[m_alpha_address & 0x7ff], 7)) + m_vram[m_alpha_address] = m_port35; else - m_p_videoram[m_graph_address] = m_port35; + m_vram[m_graph_address] = m_port35; } else - m_p_attribram[m_alpha_address & 0x7ff] = m_port35; + m_aram[m_alpha_address & 0x7ff] = m_port35; } } -void aussiebyte_state::register_w(uint8_t data) +void aussiebyte_state::register_w(u8 data) { m_crtc->register_w(data); - uint16_t temp = m_alpha_address; + u16 temp = m_alpha_address; // Get transparent address if (m_video_index == 18) @@ -111,9 +111,9 @@ void aussiebyte_state::register_w(uint8_t data) m_alpha_address = data | (temp & 0xff00); } -uint8_t aussiebyte_state::crt8002(uint8_t ac_ra, uint8_t ac_chr, uint8_t ac_attr, uint16_t ac_cnt, bool ac_curs) +u8 aussiebyte_state::crt8002(u8 ac_ra, u8 ac_chr, u8 ac_attr, u16 ac_cnt, bool ac_curs) { - uint8_t gfx = 0; + u8 gfx = 0; switch (ac_attr & 3) { case 0: // lores gfx @@ -167,20 +167,20 @@ uint8_t aussiebyte_state::crt8002(uint8_t ac_ra, uint8_t ac_chr, uint8_t ac_attr MC6845_UPDATE_ROW( aussiebyte_state::crtc_update_row ) { const rgb_t *palette = m_palette->palette()->entry_list_raw(); - uint8_t chr,gfx,attr; - uint16_t mem,x; - uint32_t *p = &bitmap.pix32(y); + u8 chr,gfx,attr; + u16 mem,x; + u32 *p = &bitmap.pix32(y); ra &= 15; m_cnt++; for (x = 0; x < x_count; x++) { mem = ma + x; - attr = m_p_attribram[mem & 0x7ff]; + attr = m_aram[mem & 0x7ff]; if (BIT(attr, 7)) - chr = m_p_videoram[mem & 0x3fff]; // alpha + chr = m_vram[mem & 0x3fff]; // alpha else - chr = m_p_videoram[(mem << 4) | ra]; // gfx + chr = m_vram[(mem << 4) | ra]; // gfx gfx = crt8002(ra, chr, attr, m_cnt, (x==cursor_x)); |