diff options
author | 2008-12-06 16:56:22 +0000 | |
---|---|---|
committer | 2008-12-06 16:56:22 +0000 | |
commit | 282c1db11081839a532aa147f7809789bd5ac107 (patch) | |
tree | 72bf31c30193edb3247cf548621ef3a7efd2641d | |
parent | 8c09fe8b03f9479de15e4f489cfbc8c4c19a7f95 (diff) |
activecpu_count -= 133
Removed mostly silly uses of activecpu from the CPU cores.
-rw-r--r-- | src/emu/cpu/g65816/g65816op.h | 2 | ||||
-rw-r--r-- | src/emu/cpu/h6280/h6280ops.h | 6 | ||||
-rw-r--r-- | src/emu/cpu/h83002/h8periph.c | 6 | ||||
-rw-r--r-- | src/emu/cpu/i86/instrv30.c | 34 | ||||
-rw-r--r-- | src/emu/cpu/m37710/m37710.c | 4 | ||||
-rw-r--r-- | src/emu/cpu/m6502/tdeco16.c | 32 | ||||
-rw-r--r-- | src/emu/cpu/mips/mips3.c | 6 | ||||
-rw-r--r-- | src/emu/cpu/mips/mips3drc.c | 12 | ||||
-rw-r--r-- | src/emu/cpu/nec/nec.c | 56 | ||||
-rw-r--r-- | src/emu/cpu/nec/nec.h | 6 | ||||
-rw-r--r-- | src/emu/cpu/sh2/sh2drc.c | 2 | ||||
-rw-r--r-- | src/emu/cpu/tlcs90/tlcs90.c | 40 | ||||
-rw-r--r-- | src/emu/cpu/tms7000/tms7000.c | 22 | ||||
-rw-r--r-- | src/emu/cpu/tms7000/tms7000.h | 2 | ||||
-rw-r--r-- | src/emu/cpu/v30mz/v30mz.c | 58 | ||||
-rw-r--r-- | src/emu/cpu/v30mz/v30mz.h | 6 | ||||
-rw-r--r-- | src/emu/debug/debugcmd.c | 2 |
17 files changed, 150 insertions, 146 deletions
diff --git a/src/emu/cpu/g65816/g65816op.h b/src/emu/cpu/g65816/g65816op.h index 7bf685201f1..e952f334f88 100644 --- a/src/emu/cpu/g65816/g65816op.h +++ b/src/emu/cpu/g65816/g65816op.h @@ -83,7 +83,7 @@ INLINE uint g65816i_read_8_direct(g65816i_cpu_struct *cpustate, uint address) INLINE uint g65816i_read_8_vector(g65816i_cpu_struct *cpustate, uint address) { if (READ_VECTOR) - return READ_VECTOR(cpu_get_address_space(Machine->activecpu, ADDRESS_SPACE_PROGRAM), address); + return READ_VECTOR(cpustate->program, address); else return g65816i_read_8_normal(cpustate, address); } diff --git a/src/emu/cpu/h6280/h6280ops.h b/src/emu/cpu/h6280/h6280ops.h index 0467336a56f..25c16d47840 100644 --- a/src/emu/cpu/h6280/h6280ops.h +++ b/src/emu/cpu/h6280/h6280ops.h @@ -556,12 +556,12 @@ INLINE void WRMEM(offs_t addr, UINT8 data) { * set I flag, reset D flag and jump via IRQ vector ***************************************************************/ #define BRK \ - logerror("BRK %04x\n",cpu_get_pc(Machine->activecpu)); \ + logerror("BRK %04x\n",PCW); \ CLEAR_T; \ PCW++; \ PUSH(PCH); \ PUSH(PCL); \ - PUSH(P); \ + PUSH(P); \ P = (P & ~_fD) | _fI; \ PCL = RDMEM(H6280_IRQ2_VEC); \ PCH = RDMEM(H6280_IRQ2_VEC+1); \ @@ -1098,7 +1098,7 @@ INLINE void WRMEM(offs_t addr, UINT8 data) { ***************************************************************/ #define SET \ P |= _fT; \ - logerror("%04x: WARNING H6280 SET\n",cpu_get_pc(Machine->activecpu)) + logerror("%04x: WARNING H6280 SET\n",PCW) /* 6280 ******************************************************** * SMB Set memory bit diff --git a/src/emu/cpu/h83002/h8periph.c b/src/emu/cpu/h83002/h8periph.c index ea46628db30..2c1ca3ac04c 100644 --- a/src/emu/cpu/h83002/h8periph.c +++ b/src/emu/cpu/h83002/h8periph.c @@ -574,7 +574,7 @@ UINT8 h8_3007_itu_read8(h83xx_state *h8, UINT8 reg) void h8_3007_itu_write8(h83xx_state *h8, UINT8 reg, UINT8 val) { - //logerror("%06x: h8/3007 reg %02x = %02x\n",cpu_get_pc(machine->activecpu),reg,val); + //logerror("%06x: h8/3007 reg %02x = %02x\n",h8->pc,reg,val); h8->per_regs[reg] = val; switch(reg) { @@ -746,7 +746,7 @@ UINT8 h8_3007_register1_read8(h83xx_state *h8, UINT32 address) case 0xfee018: return h8->per_regs[0xF8]; // IPRA } - logerror("cpu '%s' (PC=%08X): unmapped I/O(1) byte read from %08X\n",h8->device->tag,cpu_get_pc(h8->device->machine->activecpu),address); + logerror("cpu '%s' (PC=%08X): unmapped I/O(1) byte read from %08X\n",h8->device->tag,h8->pc,address); return 0; } @@ -758,7 +758,7 @@ void h8_3007_register1_write8(h83xx_state *h8, UINT32 address, UINT8 val) case 0xfee016: h8_ISR_w(h8, val); return; // ISR case 0xfee018: h8->per_regs[0xF8] = val; return; // IPRA } - logerror("cpu '%s' (PC=%08X): unmapped I/O(1) byte write to %08X = %02X\n",h8->device->tag,cpu_get_pc(h8->device->machine->activecpu),address,val); + logerror("cpu '%s' (PC=%08X): unmapped I/O(1) byte write to %08X = %02X\n",h8->device->tag,h8->pc,address,val); } void h8_3007_itu_init(h83xx_state *h8) diff --git a/src/emu/cpu/i86/instrv30.c b/src/emu/cpu/i86/instrv30.c index ca66207abf3..bb167d1b4b7 100644 --- a/src/emu/cpu/i86/instrv30.c +++ b/src/emu/cpu/i86/instrv30.c @@ -301,7 +301,7 @@ static void PREFIXV30(_0fpre) (void) /* Opcode 0x0f */ break; case 0x1D: /* 0F 1D C6 - SET1 si,cl */ - /* logerror("PC=%06x : Set1 ",cpu_get_pc(machine->activecpu)-2); */ + /* logerror("PC=%06x : Set1 ",I.pc-2); */ ModRM = FETCH; if (ModRM >= 0xc0) { @@ -477,7 +477,7 @@ static void PREFIXV30(_0fpre) (void) /* Opcode 0x0f */ * * Clocks: 16 */ - logerror("PC=%06x : MOVSPA\n", cpu_get_pc(machine->activecpu) - 2); + logerror("PC=%06x : MOVSPA\n", I.pc - 2); nec_ICount -= 16; break; case 0x26: /* 0F 22 59 - cmp4s */ @@ -567,7 +567,7 @@ static void PREFIXV30(_0fpre) (void) /* Opcode 0x0f */ * tmp &= 0xffff; * PutbackRMWord(ModRM,tmp); */ - logerror("PC=%06x : ROL4 %02x\n", cpu_get_pc(machine->activecpu) - 3, ModRM); + logerror("PC=%06x : ROL4 %02x\n", I.pc - 3, ModRM); break; case 0x2A: /* 0F 2a c2 - ROR4 bh */ @@ -612,7 +612,7 @@ static void PREFIXV30(_0fpre) (void) /* Opcode 0x0f */ * tmp = tmp2 | (tmp>>4); * PutbackRMWord(ModRM,tmp); */ - logerror("PC=%06x : ROR4 %02x\n", cpu_get_pc(machine->activecpu) - 3, ModRM); + logerror("PC=%06x : ROR4 %02x\n", I.pc - 3, ModRM); break; case 0x2D: /* 0Fh 2Dh <1111 1RRR> */ @@ -677,13 +677,13 @@ static void PREFIXV30(_0fpre) (void) /* Opcode 0x0f */ * Flags Affected: None */ ModRM = FETCH; - logerror("PC=%06x : BRKCS %02x\n", cpu_get_pc(machine->activecpu) - 3, ModRM); + logerror("PC=%06x : BRKCS %02x\n", I.pc - 3, ModRM); nec_ICount -= 15; /* checked ! */ break; case 0x31: /* 0F 31 [mod:reg:r/m] - INS reg8,reg8 or INS reg8,imm4 */ ModRM = FETCH; - logerror("PC=%06x : INS ", cpu_get_pc(machine->activecpu) - 2); + logerror("PC=%06x : INS ", I.pc - 2); if (ModRM >= 0xc0) { tmp = I.regs.b[Mod_RM.RM.b[ModRM]]; @@ -739,7 +739,7 @@ static void PREFIXV30(_0fpre) (void) /* Opcode 0x0f */ case 0x33: /* 0F 33 [mod:reg:r/m] - EXT reg8,reg8 or EXT reg8,imm4 */ ModRM = FETCH; - logerror("PC=%06x : EXT ", cpu_get_pc(machine->activecpu) - 2); + logerror("PC=%06x : EXT ", I.pc - 2); if (ModRM >= 0xc0) { tmp = I.regs.b[Mod_RM.RM.b[ModRM]]; @@ -823,7 +823,7 @@ static void PREFIXV30(_0fpre) (void) /* Opcode 0x0f */ * * Clocks: 12 */ - logerror("PC=%06x : RETRBI\n", cpu_get_pc(machine->activecpu) - 2); + logerror("PC=%06x : RETRBI\n", I.pc - 2); nec_ICount -= 12; break; @@ -856,7 +856,7 @@ static void PREFIXV30(_0fpre) (void) /* Opcode 0x0f */ */ ModRM = FETCH; - logerror("PC=%06x : TSCSW %02x\n", cpu_get_pc(machine->activecpu) - 3, ModRM); + logerror("PC=%06x : TSCSW %02x\n", I.pc - 3, ModRM); nec_ICount -= 11; break; @@ -889,7 +889,7 @@ static void PREFIXV30(_0fpre) (void) /* Opcode 0x0f */ * Clocks: 11 */ ModRM = FETCH; - logerror("PC=%06x : MOVSPB %02x\n", cpu_get_pc(machine->activecpu) - 3, ModRM); + logerror("PC=%06x : MOVSPB %02x\n", I.pc - 3, ModRM); nec_ICount -= 11; break; @@ -917,7 +917,7 @@ static void PREFIXV30(_0fpre) (void) /* Opcode 0x0f */ * * Clocks: N/A */ - logerror("PC=%06x : STOP\n", cpu_get_pc(machine->activecpu) - 2); + logerror("PC=%06x : STOP\n", I.pc - 2); nec_ICount -= 2; /* of course this is crap */ break; @@ -990,7 +990,7 @@ static void PREFIXV30(_0fpre) (void) /* Opcode 0x0f */ */ ModRM = FETCH; - logerror("PC=%06x : BRKXA %02x\n", cpu_get_pc(machine->activecpu) - 3, ModRM); + logerror("PC=%06x : BRKXA %02x\n", I.pc - 3, ModRM); nec_ICount -= 12; break; @@ -1027,7 +1027,7 @@ static void PREFIXV30(_0fpre) (void) /* Opcode 0x0f */ * Clocks: 12 */ ModRM = FETCH; - logerror("PC=%06x : RETXA %02x\n", cpu_get_pc(machine->activecpu) - 3, ModRM); + logerror("PC=%06x : RETXA %02x\n", I.pc - 3, ModRM); nec_ICount -= 12; break; @@ -1058,7 +1058,7 @@ static void PREFIXV30(_0fpre) (void) /* Opcode 0x0f */ */ ModRM = FETCH; nec_ICount -= 38; - logerror("PC=%06x : BRKEM %02x\n", cpu_get_pc(machine->activecpu) - 3, ModRM); + logerror("PC=%06x : BRKEM %02x\n", I.pc - 3, ModRM); PREFIXV30(_interrupt) (ModRM, 1); break; } @@ -1099,7 +1099,7 @@ static void PREFIXV30(_brkn) (void) /* Opcode 0x63 BRKN - Break to Native Mode unsigned int_vector; int_vector = FETCH; - logerror("PC=%06x : BRKN %02x\n", cpu_get_pc(machine->activecpu) - 2, int_vector); + logerror("PC=%06x : BRKN %02x\n", I.pc - 2, int_vector); } static void PREFIXV30(repc) (int flagval) @@ -1269,7 +1269,7 @@ static void PREFIXV30(_setalc) (void) /* Opcode 0xd6 */ */ I.regs.b[AL] = (CF) ? 0xff : 0x00; nec_ICount -= 3; // V30 - logerror("PC=%06x : SETALC\n", cpu_get_pc(machine->activecpu) - 1); + logerror("PC=%06x : SETALC\n", I.pc - 1); } #if 0 @@ -1306,6 +1306,6 @@ static void PREFIXV30(_brks) (void) /* Opcode 0xf1 - Break to Security Mode */ unsigned int_vector; int_vector = FETCH; - logerror("PC=%06x : BRKS %02x\n", cpu_get_pc(machine->activecpu) - 2, int_vector); + logerror("PC=%06x : BRKS %02x\n", I.pc - 2, int_vector); } #endif diff --git a/src/emu/cpu/m37710/m37710.c b/src/emu/cpu/m37710/m37710.c index 704e815e082..393a799bb1d 100644 --- a/src/emu/cpu/m37710/m37710.c +++ b/src/emu/cpu/m37710/m37710.c @@ -327,7 +327,7 @@ static void m37710_recalc_timer(m37710i_cpu_struct *cpustate, running_machine *m switch (cpustate->m37710_regs[0x56+timer] & 0x3) { case 0: // timer mode - time = attotime_mul(ATTOTIME_IN_HZ(cpu_get_clock(machine->activecpu)), tscales[cpustate->m37710_regs[tcr[timer]]>>6]); + time = attotime_mul(ATTOTIME_IN_HZ(cpu_get_clock(cpustate->device)), tscales[cpustate->m37710_regs[tcr[timer]]>>6]); time = attotime_mul(time, tval + 1); #if M37710_DEBUG @@ -362,7 +362,7 @@ static void m37710_recalc_timer(m37710i_cpu_struct *cpustate, running_machine *m switch (cpustate->m37710_regs[0x56+timer] & 0x3) { case 0: // timer mode - time = attotime_mul(ATTOTIME_IN_HZ(cpu_get_clock(machine->activecpu)), tscales[cpustate->m37710_regs[tcr[timer]]>>6]); + time = attotime_mul(ATTOTIME_IN_HZ(cpu_get_clock(cpustate->device)), tscales[cpustate->m37710_regs[tcr[timer]]>>6]); time = attotime_mul(time, tval + 1); #if M37710_DEBUG diff --git a/src/emu/cpu/m6502/tdeco16.c b/src/emu/cpu/m6502/tdeco16.c index 865102439c9..bf94935cfb8 100644 --- a/src/emu/cpu/m6502/tdeco16.c +++ b/src/emu/cpu/m6502/tdeco16.c @@ -9,13 +9,13 @@ #define OP(nn) INLINE void deco16_##nn(m6502_Regs *cpustate) #define DECO16_BRK \ - logerror("%04x: BRK\n",cpu_get_pc(Machine->activecpu)); \ - RDOPARG(); \ - PUSH(PCH); \ - PUSH(PCL); \ + logerror("%04x: BRK\n",PCW); \ + RDOPARG(); \ + PUSH(PCH); \ + PUSH(PCL); \ PUSH(P | F_B); \ P = (P | F_I); \ - PCL = RDMEM(DECO16_IRQ_VEC+1); \ + PCL = RDMEM(DECO16_IRQ_VEC+1); \ PCH = RDMEM(DECO16_IRQ_VEC); @@ -88,7 +88,7 @@ OP(23) { RD_IMM; if (DECO16_VERBOSE) - logerror("%04x: OP23 %02x\n",cpu_get_pc(Machine->activecpu),tmp); + logerror("%04x: OP23 %02x\n",PCW,tmp); } OP(43) { RD_DUM; ILL; } /* 2 ILL */ OP(63) { @@ -98,7 +98,7 @@ OP(63) { RD_IMM; if (DECO16_VERBOSE) - logerror("%04x: OP63 %02x\n",cpu_get_pc(Machine->activecpu),tmp); + logerror("%04x: OP63 %02x\n",PCW,tmp); } OP(83) { RD_DUM; ILL; } /* 2 ILL */ OP(a3) { @@ -108,7 +108,7 @@ OP(a3) { RD_IMM; if (DECO16_VERBOSE) - logerror("%04x: OPA3 %02x\n",cpu_get_pc(Machine->activecpu),tmp); + logerror("%04x: OPA3 %02x\n",PCW,tmp); } OP(c3) { RD_DUM; ILL; } /* 2 ILL */ OP(e3) { RD_DUM; ILL; } /* 2 ILL */ @@ -116,7 +116,7 @@ OP(e3) { RD_DUM; ILL; } /* 2 ILL */ OP(13) { int tmp; cpustate->icount -= 1; RD_IMM; if (DECO16_VERBOSE) - logerror("%04x: OP13 %02x\n",cpu_get_pc(Machine->activecpu),tmp); + logerror("%04x: OP13 %02x\n",PCW,tmp); //bank select control? @@ -190,13 +190,13 @@ OP(67) { int tmp; RD_IMM; cpustate->a=memory_read_byte_8le(cpustate->io,0); -// logerror("%04x: VBL (0x67)\n",cpu_get_pc(Machine->activecpu)); +// logerror("%04x: VBL (0x67)\n",PCW); // really - wait for status? } /* */ OP(87) { int tmp; cpustate->icount -= 1; RD_IMM; - logerror("%04x: OP87 %02x\n",cpu_get_pc(Machine->activecpu),tmp); + logerror("%04x: OP87 %02x\n",PCW,tmp); } /* */ OP(a7) { RD_DUM; ILL; } /* 2 ILL / 5 SMB2 ZPG ?? */ @@ -267,12 +267,12 @@ OP(f7) { RD_DUM; ILL; } /* 2 ILL / 5 SMB7 ZPG ?? */ #define deco16_fa m65c02_fa /* 4 PLX */ OP(0b) { int tmp; cpustate->icount -= 1; RD_IMM; - logerror("%04x: OP0B %02x\n",cpu_get_pc(Machine->activecpu),tmp); + logerror("%04x: OP0B %02x\n",PCW,tmp); } OP(2b) { RD_DUM; ILL; } /* 2 ILL */ OP(4b) { int tmp; cpustate->icount -= 1; RD_IMM; - logerror("%04x: OP4B %02x\n",cpu_get_pc(Machine->activecpu),tmp); + logerror("%04x: OP4B %02x\n",PCW,tmp); // cpustate->a=memory_read_byte_8le(cpustate->io,0); @@ -300,7 +300,7 @@ OP(bb) { RD_IMM; if (DECO16_VERBOSE) - logerror("%04x: OPBB %02x\n",cpu_get_pc(Machine->activecpu),tmp); + logerror("%04x: OPBB %02x\n",PCW,tmp); } OP(db) { RD_DUM; ILL; } /* 2 ILL */ OP(fb) { RD_DUM; ILL; } /* 2 ILL */ @@ -364,7 +364,7 @@ OP(2f) { RD_DUM; ILL; } /* 2 ILL / 5 BBR2 ZPG ?? */ OP(4f) { RD_DUM; ILL; } /* 2 ILL / 5 BBR4 ZPG ?? */ OP(6f) { RD_DUM; ILL; } /* 2 ILL / 5 BBR6 ZPG ?? */ OP(8f) { int tmp; cpustate->icount -= 1; RD_IMM; - logerror("%04x: BANK (8F) %02x\n",cpu_get_pc(Machine->activecpu),tmp); + logerror("%04x: BANK (8F) %02x\n",PCW,tmp); memory_write_byte_8le(cpustate->io,0,tmp); @@ -383,7 +383,7 @@ OP(3f) { RD_IMM; if (DECO16_VERBOSE) - logerror("%04x: OP3F %02x\n",cpu_get_pc(Machine->activecpu),tmp); + logerror("%04x: OP3F %02x\n",PCW,tmp); } OP(5f) { RD_DUM; ILL; } /* 2 ILL / 5 BBR5 ZPG ?? */ OP(7f) { RD_DUM; ILL; } /* 2 ILL / 5 BBR7 ZPG ?? */ diff --git a/src/emu/cpu/mips/mips3.c b/src/emu/cpu/mips/mips3.c index 4d39f9b6944..c8cf3c238f6 100644 --- a/src/emu/cpu/mips/mips3.c +++ b/src/emu/cpu/mips/mips3.c @@ -475,7 +475,7 @@ INLINE UINT64 get_cop0_reg(int idx) mips3.core.icount -= MIPS3_COUNT_READ_CYCLES; else mips3.core.icount = 0; - return (UINT32)((cpu_get_total_cycles(machine->activecpu) - mips3.core.count_zero_time) / 2); + return (UINT32)((cpu_get_total_cycles(mips3.core.device) - mips3.core.count_zero_time) / 2); } else if (idx == COP0_Cause) { @@ -491,7 +491,7 @@ INLINE UINT64 get_cop0_reg(int idx) int wired = mips3.core.cpr[0][COP0_Wired] & 0x3f; int range = 48 - wired; if (range > 0) - return ((cpu_get_total_cycles(machine->activecpu) - mips3.core.count_zero_time) % range + wired) & 0x3f; + return ((cpu_get_total_cycles(mips3.core.device) - mips3.core.count_zero_time) % range + wired) & 0x3f; else return 47; } @@ -531,7 +531,7 @@ INLINE void set_cop0_reg(int idx, UINT64 val) case COP0_Count: mips3.core.cpr[0][idx] = val; - mips3.core.count_zero_time = cpu_get_total_cycles(machine->activecpu) - ((UINT64)(UINT32)val * 2); + mips3.core.count_zero_time = cpu_get_total_cycles(mips3.core.device) - ((UINT64)(UINT32)val * 2); mips3com_update_cycle_counting(&mips3.core); break; diff --git a/src/emu/cpu/mips/mips3drc.c b/src/emu/cpu/mips/mips3drc.c index cf4d7405955..a0a3365c877 100644 --- a/src/emu/cpu/mips/mips3drc.c +++ b/src/emu/cpu/mips/mips3drc.c @@ -768,7 +768,7 @@ static void code_compile_block(drcuml_state *drcuml, UINT8 mode, offs_t pc) } /* validate this code block if we're not pointing into ROM */ - if (memory_get_write_ptr(cpu_get_address_space(Machine->activecpu, ADDRESS_SPACE_PROGRAM), seqhead->physpc) != NULL) + if (memory_get_write_ptr(mips3->program, seqhead->physpc) != NULL) generate_checksum_block(block, &compiler, seqhead, seqlast); /* label this instruction, if it may be jumped to locally */ @@ -816,8 +816,8 @@ static void code_compile_block(drcuml_state *drcuml, UINT8 mode, offs_t pc) static void cfunc_get_cycles(void *param) { - UINT64 *dest = param; - *dest = cpu_get_total_cycles(Machine->activecpu); + mips3_state *mips3 = param; + mips3->impstate->numcycles = cpu_get_total_cycles(mips3->device); } @@ -2754,7 +2754,7 @@ static int generate_set_cop0_reg(drcuml_block *block, compiler_state *compiler, case COP0_Count: generate_update_cycles(block, compiler, IMM(desc->pc), !in_delay_slot); // <subtract cycles> UML_MOV(block, CPR032(COP0_Count), IREG(0)); // mov [Count],i0 - UML_CALLC(block, cfunc_get_cycles, &mips3->impstate->numcycles); // callc cfunc_get_cycles,&mips3->impstate->numcycles + UML_CALLC(block, cfunc_get_cycles, mips3); // callc cfunc_get_cycles,mips3 UML_DAND(block, IREG(0), IREG(0), IMM(0xffffffff)); // and i0,i0,0xffffffff UML_DADD(block, IREG(0), IREG(0), IREG(0)); // dadd i0,i0,i0 UML_DSUB(block, MEM(&mips3->count_zero_time), MEM(&mips3->impstate->numcycles), IREG(0)); @@ -2806,7 +2806,7 @@ static int generate_get_cop0_reg(drcuml_block *block, compiler_state *compiler, { case COP0_Count: generate_update_cycles(block, compiler, IMM(desc->pc), FALSE); // <subtract cycles> - UML_CALLC(block, cfunc_get_cycles, &mips3->impstate->numcycles); // callc cfunc_get_cycles,&mips3->impstate->numcycles + UML_CALLC(block, cfunc_get_cycles, mips3); // callc cfunc_get_cycles,mips3 UML_DSUB(block, IREG(0), MEM(&mips3->impstate->numcycles), MEM(&mips3->count_zero_time)); // dsub i0,[numcycles],[count_zero_time] UML_DSHR(block, IREG(0), IREG(0), IMM(1)); // dshr i0,i0,1 @@ -2815,7 +2815,7 @@ static int generate_get_cop0_reg(drcuml_block *block, compiler_state *compiler, case COP0_Random: generate_update_cycles(block, compiler, IMM(desc->pc), FALSE); // <subtract cycles> - UML_CALLC(block, cfunc_get_cycles, &mips3->impstate->numcycles); // callc cfunc_get_cycles,&mips3->impstate->numcycles + UML_CALLC(block, cfunc_get_cycles, mips3); // callc cfunc_get_cycles,mips3 UML_DSUB(block, IREG(0), MEM(&mips3->impstate->numcycles), MEM(&mips3->count_zero_time)); // dsub i0,[numcycles],[count_zero_time] UML_AND(block, IREG(1), CPR032(COP0_Wired), IMM(0x3f)); // and i1,[Wired],0x3f diff --git a/src/emu/cpu/nec/nec.c b/src/emu/cpu/nec/nec.c index e2c8e529cad..96d1020f589 100644 --- a/src/emu/cpu/nec/nec.c +++ b/src/emu/cpu/nec/nec.c @@ -114,6 +114,8 @@ typedef UINT32 DWORD; #include "nec.h" #include "necintrf.h" +#define PC(n) (((n)->sregs[PS]<<4)+(n)->ip) + /* default configuration */ static const nec_config default_config = { @@ -422,13 +424,13 @@ OP( 0x0f, i_pre_nec ) { UINT32 ModRM, tmp, tmp2; case 0x26 : CMP4S; CLKS(7,7,2); break; case 0x28 : ModRM = FETCH(); tmp = GetRMByte(ModRM); tmp <<= 4; tmp |= nec_state->regs.b[AL] & 0xf; nec_state->regs.b[AL] = (nec_state->regs.b[AL] & 0xf0) | ((tmp>>8)&0xf); tmp &= 0xff; PutbackRMByte(ModRM,tmp); CLKM(13,13,9,28,28,15); break; case 0x2a : ModRM = FETCH(); tmp = GetRMByte(ModRM); tmp2 = (nec_state->regs.b[AL] & 0xf)<<4; nec_state->regs.b[AL] = (nec_state->regs.b[AL] & 0xf0) | (tmp&0xf); tmp = tmp2 | (tmp>>4); PutbackRMByte(ModRM,tmp); CLKM(17,17,13,32,32,19); break; - case 0x31 : ModRM = FETCH(); ModRM=0; logerror("%06x: Unimplemented bitfield INS\n",cpu_get_pc(Machine->activecpu)); break; - case 0x33 : ModRM = FETCH(); ModRM=0; logerror("%06x: Unimplemented bitfield EXT\n",cpu_get_pc(Machine->activecpu)); break; + case 0x31 : ModRM = FETCH(); ModRM=0; logerror("%06x: Unimplemented bitfield INS\n",PC(nec_state)); break; + case 0x33 : ModRM = FETCH(); ModRM=0; logerror("%06x: Unimplemented bitfield EXT\n",PC(nec_state)); break; case 0x92 : CLK(2); break; /* V25/35 FINT */ - case 0xe0 : ModRM = FETCH(); ModRM=0; logerror("%06x: V33 unimplemented BRKXA (break to expansion address)\n",cpu_get_pc(Machine->activecpu)); break; - case 0xf0 : ModRM = FETCH(); ModRM=0; logerror("%06x: V33 unimplemented RETXA (return from expansion address)\n",cpu_get_pc(Machine->activecpu)); break; - case 0xff : ModRM = FETCH(); ModRM=0; logerror("%06x: unimplemented BRKEM (break to 8080 emulation mode)\n",cpu_get_pc(Machine->activecpu)); break; - default: logerror("%06x: Unknown V20 instruction\n",cpu_get_pc(Machine->activecpu)); break; + case 0xe0 : ModRM = FETCH(); ModRM=0; logerror("%06x: V33 unimplemented BRKXA (break to expansion address)\n",PC(nec_state)); break; + case 0xf0 : ModRM = FETCH(); ModRM=0; logerror("%06x: V33 unimplemented RETXA (return from expansion address)\n",PC(nec_state)); break; + case 0xff : ModRM = FETCH(); ModRM=0; logerror("%06x: unimplemented BRKEM (break to 8080 emulation mode)\n",PC(nec_state)); break; + default: logerror("%06x: Unknown V20 instruction\n",PC(nec_state)); break; } } @@ -556,7 +558,7 @@ OP( 0x62, i_chkind ) { nec_interrupt(nec_state, 5,0); } nec_state->icount-=20; - logerror("%06x: bound %04x high %04x low %04x tmp\n",cpu_get_pc(Machine->activecpu),high,low,tmp); + logerror("%06x: bound %04x high %04x low %04x tmp\n",PC(nec_state),high,low,tmp); } OP( 0x63, i_brkn ) { nec_interrupt(nec_state, FETCH(),1); CLKS(50,50,24); } // timing not verified, used by riskchal / gussun OP( 0x64, i_repnc ) { UINT32 next = fetchop(nec_state); UINT16 c = nec_state->regs.w[CW]; @@ -582,7 +584,7 @@ OP( 0x64, i_repnc ) { UINT32 next = fetchop(nec_state); UINT16 c = nec_state-> case 0xad: CLK(2); if (c) do { i_lodsw(nec_state); c--; } while (c>0 && !CF); nec_state->regs.w[CW]=c; break; case 0xae: CLK(2); if (c) do { i_scasb(nec_state); c--; } while (c>0 && !CF); nec_state->regs.w[CW]=c; break; case 0xaf: CLK(2); if (c) do { i_scasw(nec_state); c--; } while (c>0 && !CF); nec_state->regs.w[CW]=c; break; - default: logerror("%06x: REPNC invalid\n",cpu_get_pc(Machine->activecpu)); nec_instruction[next](nec_state); + default: logerror("%06x: REPNC invalid\n",PC(nec_state)); nec_instruction[next](nec_state); } nec_state->seg_prefix=FALSE; } @@ -610,7 +612,7 @@ OP( 0x65, i_repc ) { UINT32 next = fetchop(nec_state); UINT16 c = nec_state->r case 0xad: CLK(2); if (c) do { i_lodsw(nec_state); c--; } while (c>0 && CF); nec_state->regs.w[CW]=c; break; case 0xae: CLK(2); if (c) do { i_scasb(nec_state); c--; } while (c>0 && CF); nec_state->regs.w[CW]=c; break; case 0xaf: CLK(2); if (c) do { i_scasw(nec_state); c--; } while (c>0 && CF); nec_state->regs.w[CW]=c; break; - default: logerror("%06x: REPC invalid\n",cpu_get_pc(Machine->activecpu)); nec_instruction[next](nec_state); + default: logerror("%06x: REPC invalid\n",PC(nec_state)); nec_instruction[next](nec_state); } nec_state->seg_prefix=FALSE; } @@ -714,7 +716,7 @@ OP( 0x8e, i_mov_sregw ) { UINT16 src; GetModRM; src = GetRMWord(ModRM); CLKR(15, case 0x08: nec_state->sregs[PS] = src; break; /* mov cs,ew */ case 0x10: nec_state->sregs[SS] = src; break; /* mov ss,ew */ case 0x18: nec_state->sregs[DS0] = src; break; /* mov ds,ew */ - default: logerror("%06x: Mov Sreg - Invalid register\n",cpu_get_pc(Machine->activecpu)); + default: logerror("%06x: Mov Sreg - Invalid register\n",PC(nec_state)); } nec_state->no_interrupt=1; } @@ -785,7 +787,7 @@ OP( 0xc0, i_rotshft_bd8 ) { case 0x18: do { RORC_BYTE; c--; CLK(1); } while (c>0); PutbackRMByte(ModRM,(BYTE)dst); break; case 0x20: SHL_BYTE(c); break; case 0x28: SHR_BYTE(c); break; - case 0x30: logerror("%06x: Undefined opcode 0xc0 0x30 (SHLA)\n",cpu_get_pc(Machine->activecpu)); break; + case 0x30: logerror("%06x: Undefined opcode 0xc0 0x30 (SHLA)\n",PC(nec_state)); break; case 0x38: SHRA_BYTE(c); break; } } @@ -802,7 +804,7 @@ OP( 0xc1, i_rotshft_wd8 ) { case 0x18: do { RORC_WORD; c--; CLK(1); } while (c>0); PutbackRMWord(ModRM,(WORD)dst); break; case 0x20: SHL_WORD(c); break; case 0x28: SHR_WORD(c); break; - case 0x30: logerror("%06x: Undefined opcode 0xc1 0x30 (SHLA)\n",cpu_get_pc(Machine->activecpu)); break; + case 0x30: logerror("%06x: Undefined opcode 0xc1 0x30 (SHLA)\n",PC(nec_state)); break; case 0x38: SHRA_WORD(c); break; } } @@ -852,7 +854,7 @@ OP( 0xd0, i_rotshft_b ) { case 0x18: RORC_BYTE; PutbackRMByte(ModRM,(BYTE)dst); nec_state->OverVal = (src^dst)&0x80; break; case 0x20: SHL_BYTE(1); nec_state->OverVal = (src^dst)&0x80; break; case 0x28: SHR_BYTE(1); nec_state->OverVal = (src^dst)&0x80; break; - case 0x30: logerror("%06x: Undefined opcode 0xd0 0x30 (SHLA)\n",cpu_get_pc(Machine->activecpu)); break; + case 0x30: logerror("%06x: Undefined opcode 0xd0 0x30 (SHLA)\n",PC(nec_state)); break; case 0x38: SHRA_BYTE(1); nec_state->OverVal = 0; break; } } @@ -867,7 +869,7 @@ OP( 0xd1, i_rotshft_w ) { case 0x18: RORC_WORD; PutbackRMWord(ModRM,(WORD)dst); nec_state->OverVal = (src^dst)&0x8000; break; case 0x20: SHL_WORD(1); nec_state->OverVal = (src^dst)&0x8000; break; case 0x28: SHR_WORD(1); nec_state->OverVal = (src^dst)&0x8000; break; - case 0x30: logerror("%06x: Undefined opcode 0xd1 0x30 (SHLA)\n",cpu_get_pc(Machine->activecpu)); break; + case 0x30: logerror("%06x: Undefined opcode 0xd1 0x30 (SHLA)\n",PC(nec_state)); break; case 0x38: SHRA_WORD(1); nec_state->OverVal = 0; break; } } @@ -883,7 +885,7 @@ OP( 0xd2, i_rotshft_bcl ) { case 0x18: do { RORC_BYTE; c--; CLK(1); } while (c>0); PutbackRMByte(ModRM,(BYTE)dst); break; case 0x20: SHL_BYTE(c); break; case 0x28: SHR_BYTE(c); break; - case 0x30: logerror("%06x: Undefined opcode 0xd2 0x30 (SHLA)\n",cpu_get_pc(Machine->activecpu)); break; + case 0x30: logerror("%06x: Undefined opcode 0xd2 0x30 (SHLA)\n",PC(nec_state)); break; case 0x38: SHRA_BYTE(c); break; } } @@ -899,16 +901,16 @@ OP( 0xd3, i_rotshft_wcl ) { case 0x18: do { RORC_WORD; c--; CLK(1); } while (c>0); PutbackRMWord(ModRM,(WORD)dst); break; case 0x20: SHL_WORD(c); break; case 0x28: SHR_WORD(c); break; - case 0x30: logerror("%06x: Undefined opcode 0xd3 0x30 (SHLA)\n",cpu_get_pc(Machine->activecpu)); break; + case 0x30: logerror("%06x: Undefined opcode 0xd3 0x30 (SHLA)\n",PC(nec_state)); break; case 0x38: SHRA_WORD(c); break; } } OP( 0xd4, i_aam ) { UINT32 mult=FETCH(); mult=0; nec_state->regs.b[AH] = nec_state->regs.b[AL] / 10; nec_state->regs.b[AL] %= 10; SetSZPF_Word(nec_state->regs.w[AW]); CLKS(15,15,12); } OP( 0xd5, i_aad ) { UINT32 mult=FETCH(); mult=0; nec_state->regs.b[AL] = nec_state->regs.b[AH] * 10 + nec_state->regs.b[AL]; nec_state->regs.b[AH] = 0; SetSZPF_Byte(nec_state->regs.b[AL]); CLKS(7,7,8); } -OP( 0xd6, i_setalc ) { nec_state->regs.b[AL] = (CF)?0xff:0x00; nec_state->icount-=3; logerror("%06x: Undefined opcode (SETALC)\n",cpu_get_pc(Machine->activecpu)); } +OP( 0xd6, i_setalc ) { nec_state->regs.b[AL] = (CF)?0xff:0x00; nec_state->icount-=3; logerror("%06x: Undefined opcode (SETALC)\n",PC(nec_state)); } OP( 0xd7, i_trans ) { UINT32 dest = (nec_state->regs.w[BW]+nec_state->regs.b[AL])&0xffff; nec_state->regs.b[AL] = GetMemB(DS0, dest); CLKS(9,9,5); } -OP( 0xd8, i_fpo ) { GetModRM; nec_state->icount-=2; logerror("%06x: Unimplemented floating point control %04x\n",cpu_get_pc(Machine->activecpu),ModRM); } +OP( 0xd8, i_fpo ) { GetModRM; nec_state->icount-=2; logerror("%06x: Unimplemented floating point control %04x\n",PC(nec_state),ModRM); } OP( 0xe0, i_loopne ) { INT8 disp = (INT8)FETCH(); nec_state->regs.w[CW]--; if (!ZF && nec_state->regs.w[CW]) { nec_state->ip = (WORD)(nec_state->ip+disp); /*CHANGE_PC;*/ CLKS(14,14,6); } else CLKS(5,5,3); } OP( 0xe1, i_loope ) { INT8 disp = (INT8)FETCH(); nec_state->regs.w[CW]--; if ( ZF && nec_state->regs.w[CW]) { nec_state->ip = (WORD)(nec_state->ip+disp); /*CHANGE_PC;*/ CLKS(14,14,6); } else CLKS(5,5,3); } @@ -928,7 +930,7 @@ OP( 0xed, i_inaxdx ) { nec_state->regs.w[AW] = read_port_word(nec_state->regs. OP( 0xee, i_outdxal ) { write_port_byte(nec_state->regs.w[DW], nec_state->regs.b[AL]); CLKS(8,8,3); } OP( 0xef, i_outdxax ) { write_port_word(nec_state->regs.w[DW], nec_state->regs.w[AW]); CLKW(12,12,5,12,8,3,nec_state->regs.w[DW]); } -OP( 0xf0, i_lock ) { logerror("%06x: Warning - BUSLOCK\n",cpu_get_pc(Machine->activecpu)); nec_state->no_interrupt=1; CLK(2); } +OP( 0xf0, i_lock ) { logerror("%06x: Warning - BUSLOCK\n",PC(nec_state)); nec_state->no_interrupt=1; CLK(2); } OP( 0xf2, i_repne ) { UINT32 next = fetchop(nec_state); UINT16 c = nec_state->regs.w[CW]; switch(next) { /* Segments */ case 0x26: nec_state->seg_prefix=TRUE; nec_state->prefix_base=nec_state->sregs[DS1]<<4; next = fetchop(nec_state); CLK(2); break; @@ -952,7 +954,7 @@ OP( 0xf2, i_repne ) { UINT32 next = fetchop(nec_state); UINT16 c = nec_state- case 0xad: CLK(2); if (c) do { i_lodsw(nec_state); c--; } while (c>0); nec_state->regs.w[CW]=c; break; case 0xae: CLK(2); if (c) do { i_scasb(nec_state); c--; } while (c>0 && ZF==0); nec_state->regs.w[CW]=c; break; case 0xaf: CLK(2); if (c) do { i_scasw(nec_state); c--; } while (c>0 && ZF==0); nec_state->regs.w[CW]=c; break; - default: logerror("%06x: REPNE invalid\n",cpu_get_pc(Machine->activecpu)); nec_instruction[next](nec_state); + default: logerror("%06x: REPNE invalid\n",PC(nec_state)); nec_instruction[next](nec_state); } nec_state->seg_prefix=FALSE; } @@ -979,17 +981,17 @@ OP( 0xf3, i_repe ) { UINT32 next = fetchop(nec_state); UINT16 c = nec_state- case 0xad: CLK(2); if (c) do { i_lodsw(nec_state); c--; } while (c>0); nec_state->regs.w[CW]=c; break; case 0xae: CLK(2); if (c) do { i_scasb(nec_state); c--; } while (c>0 && ZF==1); nec_state->regs.w[CW]=c; break; case 0xaf: CLK(2); if (c) do { i_scasw(nec_state); c--; } while (c>0 && ZF==1); nec_state->regs.w[CW]=c; break; - default: logerror("%06x: REPE invalid\n",cpu_get_pc(Machine->activecpu)); nec_instruction[next](nec_state); + default: logerror("%06x: REPE invalid\n",PC(nec_state)); nec_instruction[next](nec_state); } nec_state->seg_prefix=FALSE; } -OP( 0xf4, i_hlt ) { logerror("%06x: HALT\n",cpu_get_pc(Machine->activecpu)); nec_state->icount=0; } +OP( 0xf4, i_hlt ) { logerror("%06x: HALT\n",PC(nec_state)); nec_state->icount=0; } OP( 0xf5, i_cmc ) { nec_state->CarryVal = !CF; CLK(2); } OP( 0xf6, i_f6pre ) { UINT32 tmp; UINT32 uresult,uresult2; INT32 result,result2; GetModRM; tmp = GetRMByte(ModRM); switch (ModRM & 0x38) { case 0x00: tmp &= FETCH(); nec_state->CarryVal = nec_state->OverVal = 0; SetSZPF_Byte(tmp); nec_state->icount-=(ModRM >=0xc0 )?4:11; break; /* TEST */ - case 0x08: logerror("%06x: Undefined opcode 0xf6 0x08\n",cpu_get_pc(Machine->activecpu)); break; + case 0x08: logerror("%06x: Undefined opcode 0xf6 0x08\n",PC(nec_state)); break; case 0x10: PutbackRMByte(ModRM,~tmp); nec_state->icount-=(ModRM >=0xc0 )?2:16; break; /* NOT */ case 0x18: nec_state->CarryVal=(tmp!=0); tmp=(~tmp)+1; SetSZPF_Byte(tmp); PutbackRMByte(ModRM,tmp&0xff); nec_state->icount-=(ModRM >=0xc0 )?2:16; break; /* NEG */ case 0x20: uresult = nec_state->regs.b[AL]*tmp; nec_state->regs.w[AW]=(WORD)uresult; nec_state->CarryVal=nec_state->OverVal=(nec_state->regs.b[AH]!=0); nec_state->icount-=(ModRM >=0xc0 )?30:36; break; /* MULU */ @@ -1003,7 +1005,7 @@ OP( 0xf7, i_f7pre ) { UINT32 tmp,tmp2; UINT32 uresult,uresult2; INT32 result,r GetModRM; tmp = GetRMWord(ModRM); switch (ModRM & 0x38) { case 0x00: tmp2 = FETCHWORD(); tmp &= tmp2; nec_state->CarryVal = nec_state->OverVal = 0; SetSZPF_Word(tmp); nec_state->icount-=(ModRM >=0xc0 )?4:11; break; /* TEST */ - case 0x08: logerror("%06x: Undefined opcode 0xf7 0x08\n",cpu_get_pc(Machine->activecpu)); break; + case 0x08: logerror("%06x: Undefined opcode 0xf7 0x08\n",PC(nec_state)); break; case 0x10: PutbackRMWord(ModRM,~tmp); nec_state->icount-=(ModRM >=0xc0 )?2:16; break; /* NOT */ case 0x18: nec_state->CarryVal=(tmp!=0); tmp=(~tmp)+1; SetSZPF_Word(tmp); PutbackRMWord(ModRM,tmp&0xffff); nec_state->icount-=(ModRM >=0xc0 )?2:16; break; /* NEG */ case 0x20: uresult = nec_state->regs.w[AW]*tmp; nec_state->regs.w[AW]=uresult&0xffff; nec_state->regs.w[DW]=((UINT32)uresult)>>16; nec_state->CarryVal=nec_state->OverVal=(nec_state->regs.w[DW]!=0); nec_state->icount-=(ModRM >=0xc0 )?30:36; break; /* MULU */ @@ -1023,7 +1025,7 @@ OP( 0xfe, i_fepre ) { UINT32 tmp, tmp1; GetModRM; tmp=GetRMByte(ModRM); switch(ModRM & 0x38) { case 0x00: tmp1 = tmp+1; nec_state->OverVal = (tmp==0x7f); SetAF(tmp1,tmp,1); SetSZPF_Byte(tmp1); PutbackRMByte(ModRM,(BYTE)tmp1); CLKM(2,2,2,16,16,7); break; /* INC */ case 0x08: tmp1 = tmp-1; nec_state->OverVal = (tmp==0x80); SetAF(tmp1,tmp,1); SetSZPF_Byte(tmp1); PutbackRMByte(ModRM,(BYTE)tmp1); CLKM(2,2,2,16,16,7); break; /* DEC */ - default: logerror("%06x: FE Pre with unimplemented mod\n",cpu_get_pc(Machine->activecpu)); + default: logerror("%06x: FE Pre with unimplemented mod\n",PC(nec_state)); } } OP( 0xff, i_ffpre ) { UINT32 tmp, tmp1; GetModRM; tmp=GetRMWord(ModRM); @@ -1035,14 +1037,14 @@ OP( 0xff, i_ffpre ) { UINT32 tmp, tmp1; GetModRM; tmp=GetRMWord(ModRM); case 0x20: nec_state->ip = tmp; CHANGE_PC; nec_state->icount-=13; break; /* JMP */ case 0x28: nec_state->ip = tmp; nec_state->sregs[PS] = GetnextRMWord; CHANGE_PC; nec_state->icount-=15; break; /* JMP FAR */ case 0x30: PUSH(tmp); nec_state->icount-=4; break; - default: logerror("%06x: FF Pre with unimplemented mod\n",cpu_get_pc(Machine->activecpu)); + default: logerror("%06x: FF Pre with unimplemented mod\n",PC(nec_state)); } } static void i_invalid(nec_state_t *nec_state) { nec_state->icount-=10; - logerror("%06x: Invalid Opcode\n",cpu_get_pc(Machine->activecpu)); + logerror("%06x: Invalid Opcode\n",PC(nec_state)); } /*****************************************************************************/ diff --git a/src/emu/cpu/nec/nec.h b/src/emu/cpu/nec/nec.h index 08d6ec03bb9..247593b4a92 100644 --- a/src/emu/cpu/nec/nec.h +++ b/src/emu/cpu/nec/nec.h @@ -303,7 +303,7 @@ typedef enum { AH,AL,CH,CL,DH,DL,BH,BL,SPH,SPL,BPH,BPL,IXH,IXL,IYH,IYL } BREGS; unsigned di = nec_state->regs.w[IY]; \ unsigned si = nec_state->regs.w[IX]; \ static const UINT8 table[3]={18,19,19}; \ - if (nec_state->seg_prefix) logerror("%06x: Warning: seg_prefix defined for add4s\n",cpu_get_pc(Machine->activecpu)); \ + if (nec_state->seg_prefix) logerror("%06x: Warning: seg_prefix defined for add4s\n",PC(nec_state)); \ nec_state->ZeroVal = nec_state->CarryVal = 0; \ for (i=0;i<count;i++) { \ nec_state->icount-=table[nec_state->chip_type/8]; \ @@ -328,7 +328,7 @@ typedef enum { AH,AL,CH,CL,DH,DL,BH,BL,SPH,SPL,BPH,BPL,IXH,IXL,IYH,IYL } BREGS; unsigned di = nec_state->regs.w[IY]; \ unsigned si = nec_state->regs.w[IX]; \ static const UINT8 table[3]={18,19,19}; \ - if (nec_state->seg_prefix) logerror("%06x: Warning: seg_prefix defined for sub4s\n",cpu_get_pc(Machine->activecpu)); \ + if (nec_state->seg_prefix) logerror("%06x: Warning: seg_prefix defined for sub4s\n",PC(nec_state)); \ nec_state->ZeroVal = nec_state->CarryVal = 0; \ for (i=0;i<count;i++) { \ nec_state->icount-=table[nec_state->chip_type/8]; \ @@ -358,7 +358,7 @@ typedef enum { AH,AL,CH,CL,DH,DL,BH,BL,SPH,SPL,BPH,BPL,IXH,IXL,IYH,IYL } BREGS; unsigned di = nec_state->regs.w[IY]; \ unsigned si = nec_state->regs.w[IX]; \ static const UINT8 table[3]={14,19,19}; \ - if (nec_state->seg_prefix) logerror("%06x: Warning: seg_prefix defined for cmp4s\n",cpu_get_pc(Machine->activecpu)); \ + if (nec_state->seg_prefix) logerror("%06x: Warning: seg_prefix defined for cmp4s\n",PC(nec_state)); \ nec_state->ZeroVal = nec_state->CarryVal = 0; \ for (i=0;i<count;i++) { \ nec_state->icount-=table[nec_state->chip_type/8]; \ diff --git a/src/emu/cpu/sh2/sh2drc.c b/src/emu/cpu/sh2/sh2drc.c index e67b6867087..d99cba557bf 100644 --- a/src/emu/cpu/sh2/sh2drc.c +++ b/src/emu/cpu/sh2/sh2drc.c @@ -962,7 +962,7 @@ static void code_compile_block(drcuml_state *drcuml, UINT8 mode, offs_t pc) } /* validate this code block if we're not pointing into ROM */ - if (memory_get_write_ptr(cpu_get_address_space(Machine->activecpu, ADDRESS_SPACE_PROGRAM), seqhead->physpc) != NULL) + if (memory_get_write_ptr(sh2->program, seqhead->physpc) != NULL) generate_checksum_block(block, &compiler, seqhead, seqlast); /* label this instruction, if it may be jumped to locally */ diff --git a/src/emu/cpu/tlcs90/tlcs90.c b/src/emu/cpu/tlcs90/tlcs90.c index 2520a1e5b69..75da1b4c1a9 100644 --- a/src/emu/cpu/tlcs90/tlcs90.c +++ b/src/emu/cpu/tlcs90/tlcs90.c @@ -986,7 +986,7 @@ static int sprint_arg(char *buffer, UINT32 pc, const char *pre, const e_mode mod case MODE_R16D8: return sprintf( buffer, "%s%s%c$%02X", pre, r16_names[r], (rb&0x80)?'-':'+', (rb&0x80)?((rb^0xff)+1):rb ); default: - fatalerror("%04x: unimplemented addr mode = %d\n",cpu_get_pc(Machine->activecpu),mode); + fatalerror("%04x: unimplemented addr mode = %d\n",pc,mode); } return 0; @@ -1023,7 +1023,7 @@ INLINE UINT16 r8( const e_r r ) case L: return T90.hl.b.l; default: - fatalerror("%04x: unimplemented r8 register index = %d\n",cpu_get_pc(Machine->activecpu),r); + fatalerror("%04x: unimplemented r8 register index = %d\n",T90.pc,r); } } @@ -1040,7 +1040,7 @@ INLINE void w8( const e_r r, UINT16 value ) case L: T90.hl.b.l = value; return; default: - fatalerror("%04x: unimplemented w8 register index = %d\n",cpu_get_pc(Machine->activecpu),r); + fatalerror("%04x: unimplemented w8 register index = %d\n",T90.pc,r); } } @@ -1061,7 +1061,7 @@ case AF2: return (T90.af2.w.l & (~IF)) | (T90.af.w.l & IF); case PC: return T90.pc.w.l; default: - fatalerror("%04x: unimplemented r16 register index = %d\n",cpu_get_pc(Machine->activecpu),r); + fatalerror("%04x: unimplemented r16 register index = %d\n",T90.pc,r); } } @@ -1080,7 +1080,7 @@ INLINE void w16( const e_r r, UINT16 value ) case PC: T90.pc.d = value; return; default: - fatalerror("%04x: unimplemented w16 register index = %d\n",cpu_get_pc(Machine->activecpu),r); + fatalerror("%04x: unimplemented w16 register index = %d\n",T90.pc,r); } } @@ -1108,7 +1108,7 @@ INLINE UINT8 Read##N##_8(void) { \ } \ return RM8((UINT16)(r16(r##N) + (INT8)r##N##b)); \ default: \ - fatalerror("%04x: unimplemented Read%d_8 mode = %d\n",cpu_get_pc(Machine->activecpu),N,mode##N); \ + fatalerror("%04x: unimplemented Read%d_8 mode = %d\n",T90.pc,N,mode##N); \ } \ return 0; \ } \ @@ -1133,7 +1133,7 @@ INLINE UINT16 Read##N##_16(void) { \ } \ return RM16((UINT16)(r16(r##N) + (INT8)r##N##b)); \ default: \ - fatalerror("%04x: unimplemented Read%d_16 modes = %d\n",cpu_get_pc(Machine->activecpu),N,mode##N); \ + fatalerror("%04x: unimplemented Read%d_16 modes = %d\n",T90.pc,N,mode##N); \ } \ return 0; \ } @@ -1159,7 +1159,7 @@ INLINE void Write##N##_8( UINT8 value ) { \ } \ WM8((UINT16)(r16(r##N) + (INT8)r##N##b), value); return; \ default: \ - fatalerror("%04x: unimplemented Write%d_8 mode = %d\n",cpu_get_pc(Machine->activecpu),N,mode##N); \ + fatalerror("%04x: unimplemented Write%d_8 mode = %d\n",T90.pc,N,mode##N); \ } \ } \ INLINE void Write##N##_16( UINT16 value ) \ @@ -1181,7 +1181,7 @@ INLINE void Write##N##_16( UINT16 value ) \ } \ WM16((UINT16)(r16(r##N) + (INT8)r##N##b), value); return; \ default: \ - fatalerror("%04x: unimplemented Write%d_16 mode = %d\n",cpu_get_pc(Machine->activecpu),N,mode##N); \ + fatalerror("%04x: unimplemented Write%d_16 mode = %d\n",T90.pc,N,mode##N); \ } \ } @@ -1212,7 +1212,7 @@ INLINE int Test( UINT8 cond ) case NZ: return !(F & ZF); case NC: return !(F & CF); default: - fatalerror("%04x: unimplemented condition = %d\n",cpu_get_pc(Machine->activecpu),cond); + fatalerror("%04x: unimplemented condition = %d\n",T90.pc,cond); } return 0; } @@ -2314,22 +2314,22 @@ static void t90_start_timer(int i) // 16-bit mode if (i & 1) { - logerror("%04X: CPU Timer %d clocked by Timer %d overflow signal\n", cpu_get_pc(Machine->activecpu), i,i-1); + logerror("%04X: CPU Timer %d clocked by Timer %d overflow signal\n", T90.pc, i,i-1); return; } break; case 2: - logerror("%04X: CPU Timer %d, unsupported PPG mode\n", cpu_get_pc(Machine->activecpu), i); + logerror("%04X: CPU Timer %d, unsupported PPG mode\n", T90.pc, i); return; case 3: - logerror("%04X: CPU Timer %d, unsupported PWM mode\n", cpu_get_pc(Machine->activecpu), i); + logerror("%04X: CPU Timer %d, unsupported PWM mode\n", T90.pc, i); return; } switch((T90.internal_registers[ T90_TCLK - T90_IOBASE ] >> (i * 2)) & 0x03) { - case 0: if (i & 1) logerror("%04X: CPU Timer %d clocked by Timer %d match signal\n", cpu_get_pc(Machine->activecpu), i,i-1); - else logerror("%04X: CPU Timer %d, unsupported TCLK = 0\n", cpu_get_pc(Machine->activecpu), i); + case 0: if (i & 1) logerror("%04X: CPU Timer %d clocked by Timer %d match signal\n", T90.pc, i,i-1); + else logerror("%04X: CPU Timer %d, unsupported TCLK = 0\n", T90.pc, i); return; case 2: prescaler = 16; break; case 3: prescaler = 256; break; @@ -2342,7 +2342,7 @@ static void t90_start_timer(int i) timer_adjust_periodic(T90.timer[i], period, i, period); - logerror("%04X: CPU Timer %d started at %lf Hz\n", cpu_get_pc(Machine->activecpu), i, 1.0 / attotime_to_double(period)); + logerror("%04X: CPU Timer %d started at %lf Hz\n", T90.pc, i, 1.0 / attotime_to_double(period)); } static void t90_start_timer4(void) @@ -2356,7 +2356,7 @@ static void t90_start_timer4(void) { case 1: prescaler = 1; break; case 2: prescaler = 16; break; - default: logerror("%04X: CPU Timer 4, unsupported T4MOD = %d\n", cpu_get_pc(Machine->activecpu),T90.internal_registers[ T90_T4MOD - T90_IOBASE ] & 0x03); + default: logerror("%04X: CPU Timer 4, unsupported T4MOD = %d\n", T90.pc,T90.internal_registers[ T90_T4MOD - T90_IOBASE ] & 0x03); return; } @@ -2364,14 +2364,14 @@ static void t90_start_timer4(void) timer_adjust_periodic(T90.timer[4], period, 4, period); - logerror("%04X: CPU Timer 4 started at %lf Hz\n", cpu_get_pc(Machine->activecpu), 1.0 / attotime_to_double(period)); + logerror("%04X: CPU Timer 4 started at %lf Hz\n", T90.pc, 1.0 / attotime_to_double(period)); } static void t90_stop_timer(int i) { timer_adjust_oneshot(T90.timer[i], attotime_never, i); - logerror("%04X: CPU Timer %d stopped\n", cpu_get_pc(Machine->activecpu), i); + logerror("%04X: CPU Timer %d stopped\n", T90.pc, i); } static void t90_stop_timer4(void) @@ -2651,7 +2651,7 @@ static CPU_INIT( t90 ) T90.program = memory_find_address_space(device, ADDRESS_SPACE_PROGRAM); T90.io = memory_find_address_space(device, ADDRESS_SPACE_IO); - T90.timer_period = attotime_mul(ATTOTIME_IN_HZ(cpu_get_clock(device->machine->activecpu)), 8); + T90.timer_period = attotime_mul(ATTOTIME_IN_HZ(cpu_get_clock(device)), 8); // Reset registers to their initial values diff --git a/src/emu/cpu/tms7000/tms7000.c b/src/emu/cpu/tms7000/tms7000.c index 36afb9ace24..ba538249c44 100644 --- a/src/emu/cpu/tms7000/tms7000.c +++ b/src/emu/cpu/tms7000/tms7000.c @@ -47,7 +47,7 @@ static void tms7000_check_IRQ_lines( void ); static void tms7000_do_interrupt( UINT16 address, UINT8 line ); static CPU_EXECUTE( tms7000 ); static CPU_EXECUTE( tms7000_exl ); -static void tms7000_service_timer1( void ); +static void tms7000_service_timer1( const device_config *device ); static UINT16 bcd_add( UINT16 a, UINT16 b ); static UINT16 bcd_tencomp( UINT16 a ); static UINT16 bcd_sub( UINT16 a, UINT16 b); @@ -489,7 +489,7 @@ static CPU_EXECUTE( tms7000 ) if( (tms7000.pf[0x03] & 0x80) == 0x80 ) /* Is timer system active? */ { if( (tms7000.pf[0x03] & 0x40) != 0x40) /* Is system clock (divided by 16) the timer source? */ - tms7000_service_timer1(); + tms7000_service_timer1(device); } } @@ -529,7 +529,7 @@ static CPU_EXECUTE( tms7000_exl ) if( (tms7000.pf[0x03] & 0x80) == 0x80 ) /* Is timer system active? */ { if( (tms7000.pf[0x03] & 0x40) != 0x40) /* Is system clock (divided by 16) the timer source? */ - tms7000_service_timer1(); + tms7000_service_timer1(device); } } @@ -542,16 +542,16 @@ static CPU_EXECUTE( tms7000_exl ) /**************************************************************************** * Trigger the event counter ****************************************************************************/ -void tms7000_A6EC1( void ) +void tms7000_A6EC1( const device_config *device ) { if( (tms7000.pf[0x03] & 0x80) == 0x80 ) /* Is timer system active? */ { if( (tms7000.pf[0x03] & 0x40) == 0x40) /* Is event counter the timer source? */ - tms7000_service_timer1(); + tms7000_service_timer1(device); } } -static void tms7000_service_timer1( void ) +static void tms7000_service_timer1( const device_config *device ) { if( --tms7000.t1_prescaler < 0 ) /* Decrement prescaler and check for underflow */ { @@ -560,14 +560,14 @@ static void tms7000_service_timer1( void ) if( --tms7000.t1_decrementer < 0 ) /* Decrement timer1 register and check for underflow */ { tms7000.t1_decrementer = tms7000.pf[2]; /* Reload decrementer (8 bit) */ - cpu_set_input_line(Machine->activecpu, TMS7000_IRQ2_LINE, HOLD_LINE); - //LOG( ("tms7000: trigger int2 (cycles: %d)\t%d\tdelta %d\n", cpu_get_total_cycles(machine->activecpu), cpu_get_total_cycles(machine->activecpu) - tick, tms7000_cycles_per_INT2-(cpu_get_total_cycles(machine->activecpu) - tick) ); - //tick = cpu_get_total_cycles(machine->activecpu) ); + cpu_set_input_line(device, TMS7000_IRQ2_LINE, HOLD_LINE); + //LOG( ("tms7000: trigger int2 (cycles: %d)\t%d\tdelta %d\n", cpu_get_total_cycles(device), cpu_get_total_cycles(device) - tick, tms7000_cycles_per_INT2-(cpu_get_total_cycles(device) - tick) ); + //tick = cpu_get_total_cycles(device) ); /* Also, cascade out to timer 2 - timer 2 unimplemented */ } } -// LOG( ( "tms7000: service timer1. 0x%2.2x 0x%2.2x (cycles %d)\t%d\t\n", tms7000.t1_prescaler, tms7000.t1_decrementer, cpu_get_total_cycles(machine->activecpu), cpu_get_total_cycles(machine->activecpu) - tick2 ) ); -// tick2 = cpu_get_total_cycles(machine->activecpu); +// LOG( ( "tms7000: service timer1. 0x%2.2x 0x%2.2x (cycles %d)\t%d\t\n", tms7000.t1_prescaler, tms7000.t1_decrementer, cpu_get_total_cycles(device), cpu_get_total_cycles(device) - tick2 ) ); +// tick2 = cpu_get_total_cycles(device); } static WRITE8_HANDLER( tms70x0_pf_w ) /* Perpherial file write */ diff --git a/src/emu/cpu/tms7000/tms7000.h b/src/emu/cpu/tms7000/tms7000.h index 5536f896773..0408888689a 100644 --- a/src/emu/cpu/tms7000/tms7000.h +++ b/src/emu/cpu/tms7000/tms7000.h @@ -47,7 +47,7 @@ enum }; /* PUBLIC FUNCTIONS */ -extern void tms7000_A6EC1( void ); /* External event counter */ +extern void tms7000_A6EC1( const device_config *device ); /* External event counter */ extern CPU_GET_INFO( tms7000 ); extern CPU_GET_INFO( tms7000_exl ); diff --git a/src/emu/cpu/v30mz/v30mz.c b/src/emu/cpu/v30mz/v30mz.c index 322f70e7cf9..d9a466a5150 100644 --- a/src/emu/cpu/v30mz/v30mz.c +++ b/src/emu/cpu/v30mz/v30mz.c @@ -43,6 +43,8 @@ #include "debugger.h" #include "deprecat.h" +#define PC(n) (((n)->sregs[CS]<<4)+(n)->ip) + typedef UINT8 BOOLEAN; typedef UINT8 BYTE; typedef UINT16 WORD; @@ -245,13 +247,13 @@ OP( 0x0f, i_pre_nec ) { UINT32 ModRM, tmp, tmp2; case 0x26 : CMP4S; break; case 0x28 : ModRM = FETCH; tmp = GetRMByte(ModRM); tmp <<= 4; tmp |= I.regs.b[AL] & 0xf; I.regs.b[AL] = (I.regs.b[AL] & 0xf0) | ((tmp>>8)&0xf); tmp &= 0xff; PutbackRMByte(ModRM,tmp); CLKM(9,15); break; case 0x2a : ModRM = FETCH; tmp = GetRMByte(ModRM); tmp2 = (I.regs.b[AL] & 0xf)<<4; I.regs.b[AL] = (I.regs.b[AL] & 0xf0) | (tmp&0xf); tmp = tmp2 | (tmp>>4); PutbackRMByte(ModRM,tmp); CLKM(13,19); break; - case 0x31 : ModRM = FETCH; ModRM=0; logerror("%06x: Unimplemented bitfield INS\n",cpu_get_pc(Machine->activecpu)); break; - case 0x33 : ModRM = FETCH; ModRM=0; logerror("%06x: Unimplemented bitfield EXT\n",cpu_get_pc(Machine->activecpu)); break; + case 0x31 : ModRM = FETCH; ModRM=0; logerror("%06x: Unimplemented bitfield INS\n",PC(&I)); break; + case 0x33 : ModRM = FETCH; ModRM=0; logerror("%06x: Unimplemented bitfield EXT\n",PC(&I)); break; case 0x92 : CLK(2); break; /* V25/35 FINT */ - case 0xe0 : ModRM = FETCH; ModRM=0; logerror("%06x: V33 unimplemented BRKXA (break to expansion address)\n",cpu_get_pc(Machine->activecpu)); break; - case 0xf0 : ModRM = FETCH; ModRM=0; logerror("%06x: V33 unimplemented RETXA (return from expansion address)\n",cpu_get_pc(Machine->activecpu)); break; - case 0xff : ModRM = FETCH; ModRM=0; logerror("%06x: unimplemented BRKEM (break to 8080 emulation mode)\n",cpu_get_pc(Machine->activecpu)); break; - default: logerror("%06x: Unknown V20 instruction\n",cpu_get_pc(Machine->activecpu)); break; + case 0xe0 : ModRM = FETCH; ModRM=0; logerror("%06x: V33 unimplemented BRKXA (break to expansion address)\n",PC(&I)); break; + case 0xf0 : ModRM = FETCH; ModRM=0; logerror("%06x: V33 unimplemented RETXA (return from expansion address)\n",PC(&I)); break; + case 0xff : ModRM = FETCH; ModRM=0; logerror("%06x: unimplemented BRKEM (break to 8080 emulation mode)\n",PC(&I)); break; + default: logerror("%06x: Unknown V20 instruction\n",PC(&I)); break; } } @@ -381,7 +383,7 @@ OP( 0x62, i_chkind ) { } else { CLK(13); } - logerror("%06x: bound %04x high %04x low %04x tmp\n",cpu_get_pc(Machine->activecpu),high,low,tmp); + logerror("%06x: bound %04x high %04x low %04x tmp\n",PC(&I),high,low,tmp); } OP( 0x64, i_repnc ) { UINT32 next = FETCHOP; UINT16 c = I.regs.w[CW]; switch(next) { /* Segments */ @@ -406,7 +408,7 @@ OP( 0x64, i_repnc ) { UINT32 next = FETCHOP; UINT16 c = I.regs.w[CW]; case 0xad: CLK(2); if (c) do { i_lodsw(); c--; } while (c>0 && !CF); I.regs.w[CW]=c; break; case 0xae: CLK(2); if (c) do { i_scasb(); c--; } while (c>0 && !CF); I.regs.w[CW]=c; break; case 0xaf: CLK(2); if (c) do { i_scasw(); c--; } while (c>0 && !CF); I.regs.w[CW]=c; break; - default: logerror("%06x: REPNC invalid\n",cpu_get_pc(Machine->activecpu)); nec_instruction[next](); + default: logerror("%06x: REPNC invalid\n",PC(&I)); nec_instruction[next](); } seg_prefix=FALSE; } @@ -434,7 +436,7 @@ OP( 0x65, i_repc ) { UINT32 next = FETCHOP; UINT16 c = I.regs.w[CW]; case 0xad: CLK(2); if (c) do { i_lodsw(); c--; } while (c>0 && CF); I.regs.w[CW]=c; break; case 0xae: CLK(2); if (c) do { i_scasb(); c--; } while (c>0 && CF); I.regs.w[CW]=c; break; case 0xaf: CLK(2); if (c) do { i_scasw(); c--; } while (c>0 && CF); I.regs.w[CW]=c; break; - default: logerror("%06x: REPC invalid\n",cpu_get_pc(Machine->activecpu)); nec_instruction[next](); + default: logerror("%06x: REPC invalid\n",PC(&I)); nec_instruction[next](); } seg_prefix=FALSE; } @@ -538,7 +540,7 @@ OP( 0x8e, i_mov_sregw ) { UINT16 src; GetModRM; src = GetRMWord(ModRM); CLKM(2,3 case 0x08: I.sregs[CS] = src; break; /* mov cs,ew */ case 0x10: I.sregs[SS] = src; break; /* mov ss,ew */ case 0x18: I.sregs[DS] = src; break; /* mov ds,ew */ - default: logerror("%06x: Mov Sreg - Invalid register\n",cpu_get_pc(Machine->activecpu)); + default: logerror("%06x: Mov Sreg - Invalid register\n",PC(&I)); } I.no_interrupt=1; } @@ -559,7 +561,7 @@ OP( 0x97, i_xchg_axdi ) { XchgAWReg(IY); CLK(3); } OP( 0x98, i_cbw ) { I.regs.b[AH] = (I.regs.b[AL] & 0x80) ? 0xff : 0; CLK(1); } OP( 0x99, i_cwd ) { I.regs.w[DW] = (I.regs.b[AH] & 0x80) ? 0xffff : 0; CLK(1); } OP( 0x9a, i_call_far ) { UINT32 tmp, tmp2; FETCHWORD(tmp); FETCHWORD(tmp2); PUSH(I.sregs[CS]); PUSH(I.ip); I.ip = (WORD)tmp; I.sregs[CS] = (WORD)tmp2; CLK(10); } -OP( 0x9b, i_wait ) { logerror("%06x: Hardware POLL\n",cpu_get_pc(Machine->activecpu)); } +OP( 0x9b, i_wait ) { logerror("%06x: Hardware POLL\n",PC(&I)); } OP( 0x9c, i_pushf ) { PUSH( CompressFlags() ); CLK(2); } OP( 0x9d, i_popf ) { UINT32 tmp; POP(tmp); ExpandFlags(tmp); CLK(3); if (I.TF) nec_trap(); } OP( 0x9e, i_sahf ) { UINT32 tmp = (CompressFlags() & 0xff00) | (I.regs.b[AH] & 0xd5); ExpandFlags(tmp); CLK(4); } @@ -613,7 +615,7 @@ OP( 0xc0, i_rotshft_bd8 ) { case 0x18: do { RORC_BYTE; c--; } while (c>0); PutbackRMByte(ModRM,(BYTE)dst); break; case 0x20: SHL_BYTE(c); break; case 0x28: SHR_BYTE(c); break; - case 0x30: logerror("%06x: Undefined opcode 0xc0 0x30 (SHLA)\n",cpu_get_pc(Machine->activecpu)); break; + case 0x30: logerror("%06x: Undefined opcode 0xc0 0x30 (SHLA)\n",PC(&I)); break; case 0x38: SHRA_BYTE(c); break; } } @@ -630,7 +632,7 @@ OP( 0xc1, i_rotshft_wd8 ) { case 0x18: do { RORC_WORD; c--; } while (c>0); PutbackRMWord(ModRM,(WORD)dst); break; case 0x20: SHL_WORD(c); break; case 0x28: SHR_WORD(c); break; - case 0x30: logerror("%06x: Undefined opcode 0xc1 0x30 (SHLA)\n",cpu_get_pc(Machine->activecpu)); break; + case 0x30: logerror("%06x: Undefined opcode 0xc1 0x30 (SHLA)\n",PC(&I)); break; case 0x38: SHRA_WORD(c); break; } } @@ -680,7 +682,7 @@ OP( 0xd0, i_rotshft_b ) { case 0x18: RORC_BYTE; PutbackRMByte(ModRM,(BYTE)dst); I.OverVal = (src^dst)&0x80; break; case 0x20: SHL_BYTE(1); I.OverVal = (src^dst)&0x80; break; case 0x28: SHR_BYTE(1); I.OverVal = (src^dst)&0x80; break; - case 0x30: logerror("%06x: Undefined opcode 0xd0 0x30 (SHLA)\n",cpu_get_pc(Machine->activecpu)); break; + case 0x30: logerror("%06x: Undefined opcode 0xd0 0x30 (SHLA)\n",PC(&I)); break; case 0x38: SHRA_BYTE(1); I.OverVal = 0; break; } } @@ -695,7 +697,7 @@ OP( 0xd1, i_rotshft_w ) { case 0x18: RORC_WORD; PutbackRMWord(ModRM,(WORD)dst); I.OverVal = (src^dst)&0x8000; break; case 0x20: SHL_WORD(1); I.OverVal = (src^dst)&0x8000; break; case 0x28: SHR_WORD(1); I.OverVal = (src^dst)&0x8000; break; - case 0x30: logerror("%06x: Undefined opcode 0xd1 0x30 (SHLA)\n",cpu_get_pc(Machine->activecpu)); break; + case 0x30: logerror("%06x: Undefined opcode 0xd1 0x30 (SHLA)\n",PC(&I)); break; case 0x38: SHRA_WORD(1); I.OverVal = 0; break; } } @@ -711,7 +713,7 @@ OP( 0xd2, i_rotshft_bcl ) { case 0x18: do { RORC_BYTE; c--; } while (c>0); PutbackRMByte(ModRM,(BYTE)dst); break; case 0x20: SHL_BYTE(c); break; case 0x28: SHR_BYTE(c); break; - case 0x30: logerror("%06x: Undefined opcode 0xd2 0x30 (SHLA)\n",cpu_get_pc(Machine->activecpu)); break; + case 0x30: logerror("%06x: Undefined opcode 0xd2 0x30 (SHLA)\n",PC(&I)); break; case 0x38: SHRA_BYTE(c); break; } } @@ -727,16 +729,16 @@ OP( 0xd3, i_rotshft_wcl ) { case 0x18: do { RORC_WORD; c--; } while (c>0); PutbackRMWord(ModRM,(WORD)dst); break; case 0x20: SHL_WORD(c); break; case 0x28: SHR_WORD(c); break; - case 0x30: logerror("%06x: Undefined opcode 0xd3 0x30 (SHLA)\n",cpu_get_pc(Machine->activecpu)); break; + case 0x30: logerror("%06x: Undefined opcode 0xd3 0x30 (SHLA)\n",PC(&I)); break; case 0x38: SHRA_WORD(c); break; } } OP( 0xd4, i_aam ) { UINT32 mult=FETCH; mult=0; I.regs.b[AH] = I.regs.b[AL] / 10; I.regs.b[AL] %= 10; SetSZPF_Word(I.regs.w[AW]); CLK(17); } OP( 0xd5, i_aad ) { UINT32 mult=FETCH; mult=0; I.regs.b[AL] = I.regs.b[AH] * 10 + I.regs.b[AL]; I.regs.b[AH] = 0; SetSZPF_Byte(I.regs.b[AL]); CLK(5); } -OP( 0xd6, i_setalc ) { I.regs.b[AL] = (CF)?0xff:0x00; CLK(3); logerror("%06x: Undefined opcode (SETALC)\n",cpu_get_pc(Machine->activecpu)); } +OP( 0xd6, i_setalc ) { I.regs.b[AL] = (CF)?0xff:0x00; CLK(3); logerror("%06x: Undefined opcode (SETALC)\n",PC(&I)); } OP( 0xd7, i_trans ) { UINT32 dest = (I.regs.w[BW]+I.regs.b[AL])&0xffff; I.regs.b[AL] = GetMemB(DS, dest); CLK(5); } -OP( 0xd8, i_fpo ) { GetModRM; CLK(1); logerror("%06x: Unimplemented floating point control %04x\n",cpu_get_pc(Machine->activecpu),ModRM); } +OP( 0xd8, i_fpo ) { GetModRM; CLK(1); logerror("%06x: Unimplemented floating point control %04x\n",PC(&I),ModRM); } OP( 0xe0, i_loopne ) { INT8 disp = (INT8)FETCH; I.regs.w[CW]--; if (!ZF && I.regs.w[CW]) { I.ip = (WORD)(I.ip+disp); CLK(6); } else CLK(3); } OP( 0xe1, i_loope ) { INT8 disp = (INT8)FETCH; I.regs.w[CW]--; if ( ZF && I.regs.w[CW]) { I.ip = (WORD)(I.ip+disp); CLK(6); } else CLK(3); } @@ -759,7 +761,7 @@ OP( 0xed, i_inaxdx ) { UINT32 port = I.regs.w[DW]; I.regs.b[AL] = read_port(po OP( 0xee, i_outdxal ) { write_port(I.regs.w[DW], I.regs.b[AL]); CLK(6); } OP( 0xef, i_outdxax ) { UINT32 port = I.regs.w[DW]; write_port(port, I.regs.b[AL]); write_port(port+1, I.regs.b[AH]); CLK(6); } -OP( 0xf0, i_lock ) { logerror("%06x: Warning - BUSLOCK\n",cpu_get_pc(Machine->activecpu)); I.no_interrupt=1; CLK(1); } +OP( 0xf0, i_lock ) { logerror("%06x: Warning - BUSLOCK\n",PC(&I)); I.no_interrupt=1; CLK(1); } OP( 0xf2, i_repne ) { UINT32 next = FETCHOP; UINT16 c = I.regs.w[CW]; switch(next) { /* Segments */ case 0x26: seg_prefix=TRUE; prefix_base=I.sregs[ES]<<4; next = FETCHOP; CLK(2); break; @@ -783,7 +785,7 @@ OP( 0xf2, i_repne ) { UINT32 next = FETCHOP; UINT16 c = I.regs.w[CW]; case 0xad: CLK(3); if (c) do { i_lodsw(); c--; } while (c>0); I.regs.w[CW]=c; break; case 0xae: CLK(3); if (c) do { i_scasb(); c--; } while (c>0 && ZF==0); I.regs.w[CW]=c; break; case 0xaf: CLK(3); if (c) do { i_scasw(); c--; } while (c>0 && ZF==0); I.regs.w[CW]=c; break; - default: logerror("%06x: REPNE invalid\n",cpu_get_pc(Machine->activecpu)); nec_instruction[next](); + default: logerror("%06x: REPNE invalid\n",PC(&I)); nec_instruction[next](); } seg_prefix=FALSE; } @@ -810,17 +812,17 @@ OP( 0xf3, i_repe ) { UINT32 next = FETCHOP; UINT16 c = I.regs.w[CW]; case 0xad: CLK(3); if (c) do { i_lodsw(); c--; } while (c>0); I.regs.w[CW]=c; break; case 0xae: CLK(3); if (c) do { i_scasb(); c--; } while (c>0 && ZF==1); I.regs.w[CW]=c; break; case 0xaf: CLK(3); if (c) do { i_scasw(); c--; } while (c>0 && ZF==1); I.regs.w[CW]=c; break; - default: logerror("%06x: REPE invalid\n",cpu_get_pc(Machine->activecpu)); nec_instruction[next](); + default: logerror("%06x: REPE invalid\n",PC(&I)); nec_instruction[next](); } seg_prefix=FALSE; } -OP( 0xf4, i_hlt ) { logerror("%06x: HALT\n",cpu_get_pc(Machine->activecpu)); nec_ICount=0; } +OP( 0xf4, i_hlt ) { logerror("%06x: HALT\n",PC(&I)); nec_ICount=0; } OP( 0xf5, i_cmc ) { I.CarryVal = !CF; CLK(4); } OP( 0xf6, i_f6pre ) { UINT32 tmp; UINT32 uresult,uresult2; INT32 result,result2; GetModRM; tmp = GetRMByte(ModRM); switch (ModRM & 0x38) { case 0x00: tmp &= FETCH; I.CarryVal = I.OverVal = 0; SetSZPF_Byte(tmp); CLKM(1,2); break; /* TEST */ - case 0x08: logerror("%06x: Undefined opcode 0xf6 0x08\n",cpu_get_pc(Machine->activecpu)); break; + case 0x08: logerror("%06x: Undefined opcode 0xf6 0x08\n",PC(&I)); break; case 0x10: PutbackRMByte(ModRM,~tmp); CLKM(1,3); break; /* NOT */ case 0x18: I.CarryVal=(tmp!=0); tmp=(~tmp)+1; SetSZPF_Byte(tmp); PutbackRMByte(ModRM,tmp&0xff); CLKM(1,3); break; /* NEG */ case 0x20: uresult = I.regs.b[AL]*tmp; I.regs.w[AW]=(WORD)uresult; I.CarryVal=I.OverVal=(I.regs.b[AH]!=0); CLKM(3,4); break; /* MULU */ @@ -834,7 +836,7 @@ OP( 0xf7, i_f7pre ) { UINT32 tmp,tmp2; UINT32 uresult,uresult2; INT32 result,r GetModRM; tmp = GetRMWord(ModRM); switch (ModRM & 0x38) { case 0x00: FETCHWORD(tmp2); tmp &= tmp2; I.CarryVal = I.OverVal = 0; SetSZPF_Word(tmp); CLKM(1,2); break; /* TEST */ - case 0x08: logerror("%06x: Undefined opcode 0xf7 0x08\n",cpu_get_pc(Machine->activecpu)); break; + case 0x08: logerror("%06x: Undefined opcode 0xf7 0x08\n",PC(&I)); break; case 0x10: PutbackRMWord(ModRM,~tmp); CLKM(1,3); break; /* NOT */ case 0x18: I.CarryVal=(tmp!=0); tmp=(~tmp)+1; SetSZPF_Word(tmp); PutbackRMWord(ModRM,tmp&0xffff); CLKM(1,3); break; /* NEG */ case 0x20: uresult = I.regs.w[AW]*tmp; I.regs.w[AW]=uresult&0xffff; I.regs.w[DW]=((UINT32)uresult)>>16; I.CarryVal=I.OverVal=(I.regs.w[DW]!=0); CLKM(3,4); break; /* MULU */ @@ -854,7 +856,7 @@ OP( 0xfe, i_fepre ) { UINT32 tmp, tmp1; GetModRM; tmp=GetRMByte(ModRM); switch(ModRM & 0x38) { case 0x00: tmp1 = tmp+1; I.OverVal = (tmp==0x7f); SetAF(tmp1,tmp,1); SetSZPF_Byte(tmp1); PutbackRMByte(ModRM,(BYTE)tmp1); CLKM(1,3); break; /* INC */ case 0x08: tmp1 = tmp-1; I.OverVal = (tmp==0x80); SetAF(tmp1,tmp,1); SetSZPF_Byte(tmp1); PutbackRMByte(ModRM,(BYTE)tmp1); CLKM(1,3); break; /* DEC */ - default: logerror("%06x: FE Pre with unimplemented mod\n",cpu_get_pc(Machine->activecpu)); + default: logerror("%06x: FE Pre with unimplemented mod\n",PC(&I)); } } OP( 0xff, i_ffpre ) { UINT32 tmp, tmp1; GetModRM; tmp=GetRMWord(ModRM); @@ -866,14 +868,14 @@ OP( 0xff, i_ffpre ) { UINT32 tmp, tmp1; GetModRM; tmp=GetRMWord(ModRM); case 0x20: I.ip = tmp; CLKM(4,5); break; /* JMP */ case 0x28: I.ip = tmp; I.sregs[CS] = GetnextRMWord; CLK(10); break; /* JMP FAR */ case 0x30: PUSH(tmp); CLK(1); break; - default: logerror("%06x: FF Pre with unimplemented mod\n",cpu_get_pc(Machine->activecpu)); + default: logerror("%06x: FF Pre with unimplemented mod\n",PC(&I)); } } static void i_invalid(void) { nec_ICount-=10; - logerror("%06x: Invalid Opcode\n",cpu_get_pc(Machine->activecpu)); + logerror("%06x: Invalid Opcode\n",PC(&I)); } /*****************************************************************************/ diff --git a/src/emu/cpu/v30mz/v30mz.h b/src/emu/cpu/v30mz/v30mz.h index c00c3250eb6..65ba7d735d1 100644 --- a/src/emu/cpu/v30mz/v30mz.h +++ b/src/emu/cpu/v30mz/v30mz.h @@ -277,7 +277,7 @@ typedef enum { AH,AL,CH,CL,DH,DL,BH,BL,SPH,SPL,BPH,BPL,IXH,IXL,IYH,IYL } BREGS; unsigned di = I.regs.w[IY]; \ unsigned si = I.regs.w[IX]; \ static const UINT8 table[3]={18,19,19}; \ - if (seg_prefix) logerror("%06x: Warning: seg_prefix defined for add4s\n",cpu_get_pc(Machine->activecpu)); \ + if (seg_prefix) logerror("%06x: Warning: seg_prefix defined for add4s\n",PC(&I)); \ I.ZeroVal = I.CarryVal = 0; \ for (i=0;i<count;i++) { \ nec_ICount-=table[chip_type/8]; \ @@ -302,7 +302,7 @@ typedef enum { AH,AL,CH,CL,DH,DL,BH,BL,SPH,SPL,BPH,BPL,IXH,IXL,IYH,IYL } BREGS; unsigned di = I.regs.w[IY]; \ unsigned si = I.regs.w[IX]; \ static const UINT8 table[3]={18,19,19}; \ - if (seg_prefix) logerror("%06x: Warning: seg_prefix defined for sub4s\n",cpu_get_pc(Machine->activecpu)); \ + if (seg_prefix) logerror("%06x: Warning: seg_prefix defined for sub4s\n",PC(&I)); \ I.ZeroVal = I.CarryVal = 0; \ for (i=0;i<count;i++) { \ nec_ICount-=table[chip_type/8]; \ @@ -332,7 +332,7 @@ typedef enum { AH,AL,CH,CL,DH,DL,BH,BL,SPH,SPL,BPH,BPL,IXH,IXL,IYH,IYL } BREGS; unsigned di = I.regs.w[IY]; \ unsigned si = I.regs.w[IX]; \ static const UINT8 table[3]={14,19,19}; \ - if (seg_prefix) logerror("%06x: Warning: seg_prefix defined for cmp4s\n",cpu_get_pc(Machine->activecpu)); \ + if (seg_prefix) logerror("%06x: Warning: seg_prefix defined for cmp4s\n",PC(&I)); \ I.ZeroVal = I.CarryVal = 0; \ for (i=0;i<count;i++) { \ nec_ICount-=table[chip_type/8]; \ diff --git a/src/emu/debug/debugcmd.c b/src/emu/debug/debugcmd.c index 353e7984a5f..42272d494c0 100644 --- a/src/emu/debug/debugcmd.c +++ b/src/emu/debug/debugcmd.c @@ -696,7 +696,7 @@ static void execute_logerror(running_machine *machine, int ref, int params, cons static void execute_tracelog(running_machine *machine, int ref, int params, const char *param[]) { - FILE *file = cpu_get_debug_data(machine->activecpu)->trace.file; + FILE *file = cpu_get_debug_data(debug_cpu_get_visible_cpu(machine))->trace.file; UINT64 values[MAX_COMMAND_PARAMS]; char buffer[1024]; int i; |