diff options
| author | 2025-07-25 19:49:37 +0200 | |
|---|---|---|
| committer | 2025-07-25 19:49:37 +0200 | |
| commit | 27aa1f8031bf1e055abe8f2d172ee71839967c3e (patch) | |
| tree | 0ab049e0cf321cf4b2028c723d36a1e182fc8766 | |
| parent | 36e85e149118b12216dada7822d63d1463efbe43 (diff) | |
minferno: fix crash at reset
| -rw-r--r-- | src/mame/atlus/cave.cpp | 14 | ||||
| -rw-r--r-- | src/mame/meadows/meadows.cpp | 4 | ||||
| -rw-r--r-- | src/mame/technos/ddragon3.cpp | 4 |
3 files changed, 11 insertions, 11 deletions
diff --git a/src/mame/atlus/cave.cpp b/src/mame/atlus/cave.cpp index 38d5aefca69..80949b270f4 100644 --- a/src/mame/atlus/cave.cpp +++ b/src/mame/atlus/cave.cpp @@ -135,7 +135,7 @@ void cave_state::update_irq_state() TIMER_CALLBACK_MEMBER(cave_state::vblank_end) { - if (m_kludge == 3) /* mazinger metmqstr */ + if (m_kludge == 3) // mazinger metmqstr { m_unknown_irq = 1; update_irq_state(); @@ -168,8 +168,8 @@ INTERRUPT_GEN_MEMBER(cave_state::interrupt) } INTERRUPT_GEN_MEMBER(ppsatan_state::interrupt_ppsatan) { - m_int_timer->adjust (attotime::from_usec(17376 - m_time_vblank_irq)); - m_int_timer_left->adjust (attotime::from_usec(17376 - m_time_vblank_irq)); + m_int_timer->adjust(attotime::from_usec(17376 - m_time_vblank_irq)); + m_int_timer_left->adjust(attotime::from_usec(17376 - m_time_vblank_irq)); m_int_timer_right->adjust(attotime::from_usec(17376 - m_time_vblank_irq)); } @@ -270,7 +270,7 @@ u8 cave_z80_state::soundflags_r() { // bit 2 is low: can read command (lo) // bit 3 is low: can read command (hi) - //return (m_sound_flag[0] ? 0 : 4) | (m_sound_flag[1] ? 0 : 8) ; + //return (m_sound_flag[0] ? 0 : 4) | (m_sound_flag[1] ? 0 : 8) ; return 0; } @@ -288,7 +288,7 @@ void cave_z80_state::sound_cmd_w(u16 data) //m_sound_flag[0] = 1; //m_sound_flag[1] = 1; m_soundlatch->write(data); - m_maincpu->spin_until_time(attotime::from_usec(50)); // Allow the other cpu to reply + m_maincpu->spin_until_time(attotime::from_usec(50)); // Allow the other cpu to reply } /* Sound CPU: read the low 8 bits of the 16 bit sound latch */ @@ -391,7 +391,7 @@ void ppsatan_state::ppsatan_eeprom_w(offs_t offset, u16 data, u16 mem_mask) if (data & ~0x000f) logerror("%s: Unknown EEPROM bit written %04X\n",machine().describe_context(),data); - if (ACCESSING_BITS_0_7) // odd address + if (ACCESSING_BITS_0_7) // odd address { // bit 11? @@ -529,7 +529,7 @@ u16 cave_state::donpachi_videoregs_r(offs_t offset) case 2: case 3: return irq_cause_r(offset); - default: return 0x0000; + default: return 0x0000; } } diff --git a/src/mame/meadows/meadows.cpp b/src/mame/meadows/meadows.cpp index 041c28e84cf..2d16b9e8f08 100644 --- a/src/mame/meadows/meadows.cpp +++ b/src/mame/meadows/meadows.cpp @@ -249,7 +249,7 @@ void meadows_state::sh_init() { // initialized after samples_device::device_reset for (int i = 0; i < 2; i++) - if (!m_samples->playing(i)) + if (m_samples && !m_samples->playing(i)) { m_freq[i] = machine().sample_rate(); @@ -376,7 +376,7 @@ void meadows_state::draw_sprites(bitmap_ind16 &bitmap, const rectangle &clip) int const x = m_spriteram[i + 0] - 18; int const y = m_spriteram[i + 4] - 14; int const code = m_spriteram[i + 8] & 0x0f; // bit #0 .. #3 select sprite -// int const bank = (m_spriteram[i + 8] >> 4) & 1; bit #4 selects PROM ??? +// int const bank = (m_spriteram[i + 8] >> 4) & 1; // bit #4 selects PROM ??? int const bank = i; // that fixes it for now :-/ int const flip = m_spriteram[i + 8] >> 5; // bit #5 flip vertical flag diff --git a/src/mame/technos/ddragon3.cpp b/src/mame/technos/ddragon3.cpp index 5008d4dfe84..74b0ebe7af9 100644 --- a/src/mame/technos/ddragon3.cpp +++ b/src/mame/technos/ddragon3.cpp @@ -218,14 +218,14 @@ void ddragon3_state::ddragon3_vreg_w(offs_t offset, uint16_t data, uint16_t mem_ void ddragon3_state::irq6_ack_w(uint16_t data) { - // this gets written to on startup and at the end of IRQ6 + // this gets written to on startup and at the end of IRQ6 m_maincpu->set_input_line(6, CLEAR_LINE); } void ddragon3_state::irq5_ack_w(uint16_t data) { - // this gets written to on startup and at the end of IRQ5 (input port read) + // this gets written to on startup and at the end of IRQ5 (input port read) m_maincpu->set_input_line(5, CLEAR_LINE); } |
