diff options
author | Patrick Mackinlay <pmackinlay@hotmail.com> | 2019-08-29 19:45:01 +0700 |
---|---|---|
committer | Patrick Mackinlay <pmackinlay@hotmail.com> | 2019-08-29 19:45:01 +0700 |
commit | 23a5e123030ddc65b970c2b23a1f77e1ee74675e (patch) | |
tree | 6ca8e23afd0407b093fb67fc4284a53e44382776 | |
parent | cbb3262e2a74ec38cfc9236e78b7d62d954229ec (diff) |
mips1: undocumented behaviour (nw)
-rw-r--r-- | src/devices/cpu/mips/mips1.cpp | 13 |
1 files changed, 12 insertions, 1 deletions
diff --git a/src/devices/cpu/mips/mips1.cpp b/src/devices/cpu/mips/mips1.cpp index 2288293c804..6c491cb04ca 100644 --- a/src/devices/cpu/mips/mips1.cpp +++ b/src/devices/cpu/mips/mips1.cpp @@ -383,7 +383,18 @@ void mips1core_device_base::execute_run() } break; case 0x01: // REGIMM - switch (RTREG) + /* + * Hardware testing has established that MIPS-1 processors do + * not decode bit 17 of REGIMM format instructions. This bit is + * used to add the "branch likely" instructions for MIPS-2 and + * later architectures. + * + * IRIX 5.3 inst(1M) uses this behaviour to distinguish MIPS-1 + * from MIPS-2 processors; the latter nullify the delay slot + * instruction if the branch is not taken, whereas the former + * execute the delay slot instruction regardless. + */ + switch (RTREG & 0x1d) { case 0x00: // BLTZ if (s32(m_r[RSREG]) < 0) |