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authorGravatarGravatar Aaron Giles <aaron@aarongiles.com>2008-05-15 08:56:29 +0000
committerGravatarGravatar Aaron Giles <aaron@aarongiles.com>2008-05-15 08:56:29 +0000
commit21a686cf7d30027c6e372b64bd4a7831fa37b0b7 (patch)
tree52596b3e6dcaa5c69ddf5e7fbc02ef1ed7733a16
parent934fbd9fc2f92ebc86424ad7741765e65b4981a4 (diff)
Cleanups and version bump.mame0125u1
-rw-r--r--src/emu/cpu/cpu.mak2
-rw-r--r--src/emu/cpu/drcbex64.c384
-rw-r--r--src/emu/cpu/drcbex86.c198
-rw-r--r--src/emu/cpu/drccache.c10
-rw-r--r--src/emu/cpu/drcuml.c60
-rw-r--r--src/emu/cpu/ds5002fp/ds5002fp.c180
-rw-r--r--src/emu/cpu/ds5002fp/ds5002fp.h6
-rw-r--r--src/emu/cpu/ds5002fp/ds5002fpdasm.c4
-rw-r--r--src/emu/cpu/mips/mips3drc.c244
-rw-r--r--src/emu/cpu/mips/mips3fe.c2
-rw-r--r--src/emu/fileio.c2
-rw-r--r--src/emu/machine/cdp1852.c4
-rw-r--r--src/emu/machine/cdp1852.h26
-rw-r--r--src/emu/sound/tms5220.c2
-rw-r--r--src/emu/video.c16
-rw-r--r--src/emu/video/cdp1869.c2
-rw-r--r--src/lib/util/aviio.c4
-rw-r--r--src/mame/drivers/djmain.c4
-rw-r--r--src/mame/drivers/funworld.c2
-rw-r--r--src/mame/drivers/gatron.c8
-rw-r--r--src/mame/drivers/namcona1.c2
-rw-r--r--src/mame/drivers/undrfire.c4
-rw-r--r--src/mame/drivers/wrally.c24
-rw-r--r--src/mame/machine/gaelcrpt.c4
-rw-r--r--src/mame/video/namcona1.c2
-rw-r--r--src/mame/video/wrally.c26
-rw-r--r--src/version.c2
27 files changed, 612 insertions, 612 deletions
diff --git a/src/emu/cpu/cpu.mak b/src/emu/cpu/cpu.mak
index 35e52c3e362..bdd9a3a9752 100644
--- a/src/emu/cpu/cpu.mak
+++ b/src/emu/cpu/cpu.mak
@@ -25,7 +25,7 @@ DRCOBJ = \
$(CPUOBJ)/drcfe.o \
$(CPUOBJ)/drcuml.o \
$(CPUOBJ)/drcumld.o \
-
+
DRCDEPS = \
$(CPUSRC)/drcbeut.h \
$(CPUSRC)/drccache.h \
diff --git a/src/emu/cpu/drcbex64.c b/src/emu/cpu/drcbex64.c
index 18203f41c94..0d471809b94 100644
--- a/src/emu/cpu/drcbex64.c
+++ b/src/emu/cpu/drcbex64.c
@@ -10,20 +10,20 @@
****************************************************************************
- Future improvements/changes:
+ Future improvements/changes:
- * Add support for FP registers
+ * Add support for FP registers
- * Optimize to avoid unnecessary reloads
-
- * Identify common pairs and optimize output
+ * Optimize to avoid unnecessary reloads
+
+ * Identify common pairs and optimize output
****************************************************************************
-------------------------
ABI/conventions (Windows)
-------------------------
-
+
Registers:
RAX - volatile, function return value
RBX - non-volatile
@@ -41,28 +41,28 @@
R14 - non-volatile
R15 - non-volatile
- XMM0 - volatile, FP function parameter 1
- XMM1 - volatile, FP function parameter 2
- XMM2 - volatile, FP function parameter 3
- XMM3 - volatile, FP function parameter 4
- XMM4 - volatile
- XMM5 - volatile
- XMM6 - non-volatile
- XMM7 - non-volatile
- XMM8 - non-volatile
- XMM9 - non-volatile
- XMM10 - non-volatile
- XMM11 - non-volatile
- XMM12 - non-volatile
- XMM13 - non-volatile
- XMM14 - non-volatile
- XMM15 - non-volatile
-
+ XMM0 - volatile, FP function parameter 1
+ XMM1 - volatile, FP function parameter 2
+ XMM2 - volatile, FP function parameter 3
+ XMM3 - volatile, FP function parameter 4
+ XMM4 - volatile
+ XMM5 - volatile
+ XMM6 - non-volatile
+ XMM7 - non-volatile
+ XMM8 - non-volatile
+ XMM9 - non-volatile
+ XMM10 - non-volatile
+ XMM11 - non-volatile
+ XMM12 - non-volatile
+ XMM13 - non-volatile
+ XMM14 - non-volatile
+ XMM15 - non-volatile
+
-----------------------------
ABI/conventions (Linux/MacOS)
-----------------------------
-
+
Registers:
RAX - volatile, function return value
RBX - non-volatile
@@ -80,23 +80,23 @@
R14 - non-volatile
R15 - non-volatile
- XMM0 - volatile, FP function parameter 1
- XMM1 - volatile, FP function parameter 2
- XMM2 - volatile, FP function parameter 3
- XMM3 - volatile, FP function parameter 4
- XMM4 - volatile
- XMM5 - volatile
- XMM6 - volatile
- XMM7 - volatile
- XMM8 - volatile
- XMM9 - volatile
- XMM10 - volatile
- XMM11 - volatile
- XMM12 - volatile
- XMM13 - volatile
- XMM14 - volatile
- XMM15 - volatile
-
+ XMM0 - volatile, FP function parameter 1
+ XMM1 - volatile, FP function parameter 2
+ XMM2 - volatile, FP function parameter 3
+ XMM3 - volatile, FP function parameter 4
+ XMM4 - volatile
+ XMM5 - volatile
+ XMM6 - volatile
+ XMM7 - volatile
+ XMM8 - volatile
+ XMM9 - volatile
+ XMM10 - volatile
+ XMM11 - volatile
+ XMM12 - volatile
+ XMM13 - volatile
+ XMM14 - volatile
+ XMM15 - volatile
+
---------------
Execution model
@@ -259,7 +259,7 @@ struct _drcbe_state
x86_entry_point_func entry; /* entry point */
x86code * exit; /* exit point */
x86code * nocode; /* nocode handler */
-
+
x86code * mame_debug_hook; /* debugger callback */
x86code * debug_log_hashjmp; /* hashjmp debugging */
x86code * drcmap_get_value; /* map lookup helper */
@@ -717,7 +717,7 @@ static drcbe_state *drcbex64_alloc(drcuml_state *drcuml, drccache *cache, UINT32
drcbe->drcuml = drcuml;
drcbe->cache = cache;
drcbe->rbpvalue = drccache_near(cache) + 0x80;
-
+
/* build up necessary arrays */
memcpy(drcbe->ssecontrol, sse_control, sizeof(drcbe->ssecontrol));
drcbe->absmask32 = drccache_memory_alloc_near(cache, 16*2 + 15);
@@ -725,7 +725,7 @@ static drcbe_state *drcbex64_alloc(drcuml_state *drcuml, drccache *cache, UINT32
drcbe->absmask32[0] = drcbe->absmask32[1] = drcbe->absmask32[2] = drcbe->absmask32[3] = 0x7fffffff;
drcbe->absmask64 = (UINT64 *)&drcbe->absmask32[4];
drcbe->absmask64[0] = drcbe->absmask64[1] = U64(0x7fffffffffffffff);
-
+
/* get pointers to C functions we need to call */
#ifdef ENABLE_DEBUGGER
drcbe->mame_debug_hook = (x86code *)mame_debug_hook;
@@ -901,7 +901,7 @@ static void drcbex64_generate(drcbe_state *drcbe, drcuml_block *block, const drc
drcuml_disasm(inst, dasm);
x86log_add_comment(drcbe->log, dst, "%s", dasm);
}
-
+
/* extract a blockname */
if (blockname == NULL)
{
@@ -1241,7 +1241,7 @@ static void emit_mov_m32_p32(drcbe_state *drcbe, x86code **dst, DECLARE_MEMPARAM
/*-------------------------------------------------
- emit_mov_p32_r32 - move a register into a
+ emit_mov_p32_r32 - move a register into a
32-bit parameter
-------------------------------------------------*/
@@ -1969,7 +1969,7 @@ static void emit_mov_r64_p64(drcbe_state *drcbe, x86code **dst, UINT8 reg, const
/*-------------------------------------------------
- emit_mov_p64_r64 - move a registers into a
+ emit_mov_p64_r64 - move a registers into a
64-bit parameter
-------------------------------------------------*/
@@ -2771,7 +2771,7 @@ static void emit_movss_r128_p32(drcbe_state *drcbe, x86code **dst, UINT8 reg, co
/*-------------------------------------------------
- emit_movss_p32_r128 - move a register into a
+ emit_movss_p32_r128 - move a register into a
32-bit parameter
-------------------------------------------------*/
@@ -2807,7 +2807,7 @@ static void emit_movsd_r128_p64(drcbe_state *drcbe, x86code **dst, UINT8 reg, co
/*-------------------------------------------------
- emit_movsd_p64_r128 - move a register into a
+ emit_movsd_p64_r128 - move a register into a
64-bit parameter
-------------------------------------------------*/
@@ -2967,7 +2967,7 @@ static x86code *op_handle(drcbe_state *drcbe, x86code *dst, const drcuml_instruc
/* register the current pointer for the handle */
drcuml_handle_set_codeptr((drcuml_codehandle *)(FPTR)inst->param[0].value, dst);
-
+
/* by default, the handle points to prolog code that moves the stack pointer */
emit_sub_r64_imm(&dst, REG_RSP, 40); // sub rsp,40
return dst;
@@ -3126,7 +3126,7 @@ static x86code *op_hashjmp(drcbe_state *drcbe, x86code *dst, const drcuml_instru
{
UINT32 l1val = (pcp.value >> drcbe->hash->l1shift) & drcbe->hash->l1mask;
UINT32 l2val = (pcp.value >> drcbe->hash->l2shift) & drcbe->hash->l2mask;
- emit_call_m64(&dst, MABS(drcbe, &drcbe->hash->base[modep.value][l1val][l2val]));
+ emit_call_m64(&dst, MABS(drcbe, &drcbe->hash->base[modep.value][l1val][l2val]));
// call hash[modep][l1val][l2val]
}
@@ -3494,10 +3494,10 @@ static x86code *op_load1u(drcbe_state *drcbe, x86code *dst, const drcuml_instruc
/* pick a target register for the general case */
dstreg = param_select_register(REG_EAX, &dstp, NULL);
-
+
/* determine the pointer base */
basereg = get_base_register_and_offset(drcbe, &dst, basep.value, REG_RDX, &baseoffs);
-
+
/* immediate index */
if (indp.type == DRCUML_PTYPE_IMMEDIATE)
emit_movzx_r32_m8(&dst, dstreg, MBD(basereg, baseoffs + 1*indp.value)); // movzx dstreg,[basep + 1*indp]
@@ -3509,13 +3509,13 @@ static x86code *op_load1u(drcbe_state *drcbe, x86code *dst, const drcuml_instruc
emit_mov_r32_p32(drcbe, &dst, indreg, &indp);
emit_movzx_r32_m8(&dst, dstreg, MBISD(basereg, indreg, 1, baseoffs)); // movzx dstreg,[basep + 1*indp]
}
-
+
/* store to appropriate target size */
if (inst->size == 4)
emit_mov_p32_r32(drcbe, &dst, &dstp, dstreg); // mov dstp,dstreg
else if (inst->size == 8)
emit_mov_p64_r64(drcbe, &dst, &dstp, dstreg); // mov dstp,dstreg
-
+
return dst;
}
@@ -3542,7 +3542,7 @@ static x86code *op_load1s(drcbe_state *drcbe, x86code *dst, const drcuml_instruc
/* determine the pointer base */
basereg = get_base_register_and_offset(drcbe, &dst, basep.value, REG_RDX, &baseoffs);
-
+
/* 32-bit form */
if (inst->size == 4)
{
@@ -3606,7 +3606,7 @@ static x86code *op_load2u(drcbe_state *drcbe, x86code *dst, const drcuml_instruc
/* determine the pointer base */
basereg = get_base_register_and_offset(drcbe, &dst, basep.value, REG_RDX, &baseoffs);
-
+
/* immediate index */
if (indp.type == DRCUML_PTYPE_IMMEDIATE)
emit_movzx_r32_m16(&dst, dstreg, MBD(basereg, baseoffs + 2*indp.value)); // movzx dstreg,[basep + 2*indp]
@@ -3618,7 +3618,7 @@ static x86code *op_load2u(drcbe_state *drcbe, x86code *dst, const drcuml_instruc
emit_mov_r32_p32(drcbe, &dst, indreg, &indp);
emit_movzx_r32_m16(&dst, dstreg, MBISD(basereg, indreg, 2, baseoffs)); // movzx dstreg,[basep + 2*indp]
}
-
+
/* store to appropriate target size */
if (inst->size == 4)
emit_mov_p32_r32(drcbe, &dst, &dstp, dstreg); // mov dstp,dstreg
@@ -3651,7 +3651,7 @@ static x86code *op_load2s(drcbe_state *drcbe, x86code *dst, const drcuml_instruc
/* determine the pointer base */
basereg = get_base_register_and_offset(drcbe, &dst, basep.value, REG_RDX, &baseoffs);
-
+
/* 32-bit form */
if (inst->size == 4)
{
@@ -3715,7 +3715,7 @@ static x86code *op_load4u(drcbe_state *drcbe, x86code *dst, const drcuml_instruc
/* determine the pointer base */
basereg = get_base_register_and_offset(drcbe, &dst, basep.value, REG_RDX, &baseoffs);
-
+
/* immediate index */
if (indp.type == DRCUML_PTYPE_IMMEDIATE)
emit_mov_r32_m32(&dst, dstreg, MBD(basereg, baseoffs + 4*indp.value)); // mov dstreg,[basep + 4*indp]
@@ -3727,7 +3727,7 @@ static x86code *op_load4u(drcbe_state *drcbe, x86code *dst, const drcuml_instruc
emit_mov_r32_p32(drcbe, &dst, indreg, &indp);
emit_mov_r32_m32(&dst, dstreg, MBISD(basereg, indreg, 4, baseoffs)); // mov dstreg,[basep + 4*indp]
}
-
+
/* store to appropriate target size */
if (inst->size == 4)
emit_mov_p32_r32(drcbe, &dst, &dstp, dstreg); // mov dstp,dstreg
@@ -3760,7 +3760,7 @@ static x86code *op_load4s(drcbe_state *drcbe, x86code *dst, const drcuml_instruc
/* determine the pointer base */
basereg = get_base_register_and_offset(drcbe, &dst, basep.value, REG_RDX, &baseoffs);
-
+
/* immediate index */
if (indp.type == DRCUML_PTYPE_IMMEDIATE)
emit_movsxd_r64_m32(&dst, dstreg, MBD(basereg, baseoffs + 4*indp.value)); // mov dstreg,[basep + 4*indp]
@@ -3802,7 +3802,7 @@ static x86code *op_load8u(drcbe_state *drcbe, x86code *dst, const drcuml_instruc
/* determine the pointer base */
basereg = get_base_register_and_offset(drcbe, &dst, basep.value, REG_RDX, &baseoffs);
-
+
/* immediate index */
if (indp.type == DRCUML_PTYPE_IMMEDIATE)
emit_mov_r64_m64(&dst, dstreg, MBD(basereg, baseoffs + 8*indp.value)); // mov dstreg,[basep + 8*indp]
@@ -3841,10 +3841,10 @@ static x86code *op_store1(drcbe_state *drcbe, x86code *dst, const drcuml_instruc
/* pick a source register for the general case */
srcreg = param_select_register(REG_EAX, &srcp, NULL);
-
+
/* determine the pointer base */
basereg = get_base_register_and_offset(drcbe, &dst, basep.value, REG_RDX, &baseoffs);
-
+
/* degenerate case: constant index */
if (indp.type == DRCUML_PTYPE_IMMEDIATE)
{
@@ -3893,7 +3893,7 @@ static x86code *op_store2(drcbe_state *drcbe, x86code *dst, const drcuml_instruc
/* pick a source register for the general case */
srcreg = param_select_register(REG_EAX, &srcp, NULL);
-
+
/* determine the pointer base */
basereg = get_base_register_and_offset(drcbe, &dst, basep.value, REG_RDX, &baseoffs);
@@ -3945,7 +3945,7 @@ static x86code *op_store4(drcbe_state *drcbe, x86code *dst, const drcuml_instruc
/* pick a source register for the general case */
srcreg = param_select_register(REG_EAX, &srcp, NULL);
-
+
/* determine the pointer base */
basereg = get_base_register_and_offset(drcbe, &dst, basep.value, REG_RDX, &baseoffs);
@@ -3997,7 +3997,7 @@ static x86code *op_store8(drcbe_state *drcbe, x86code *dst, const drcuml_instruc
/* pick a source register for the general case */
srcreg = param_select_register(REG_EAX, &srcp, NULL);
-
+
/* determine the pointer base */
basereg = get_base_register_and_offset(drcbe, &dst, basep.value, REG_RDX, &baseoffs);
@@ -4053,7 +4053,7 @@ static x86code *op_read1u(drcbe_state *drcbe, x86code *dst, const drcuml_instruc
emit_mov_r32_p32(drcbe, &dst, REG_PARAM1, &addrp); // mov param1,addrp
emit_smart_call_m64(drcbe, &dst, (x86code **)&drcbe->accessors[spacep.value].read_byte);// call read_byte
emit_movzx_r32_r8(&dst, dstreg, REG_AL); // movzx dstreg,al
-
+
/* store to appropriate target size */
if (inst->size == 4)
emit_mov_p32_r32(drcbe, &dst, &dstp, dstreg); // mov dstp,dstreg
@@ -4129,7 +4129,7 @@ static x86code *op_read2u(drcbe_state *drcbe, x86code *dst, const drcuml_instruc
emit_mov_r32_p32(drcbe, &dst, REG_PARAM1, &addrp); // mov param1,addrp
emit_smart_call_m64(drcbe, &dst, (x86code **)&drcbe->accessors[spacep.value].read_word);// call read_word
emit_movzx_r32_r16(&dst, dstreg, REG_AX); // movzx dstreg,ax
-
+
/* store to appropriate target size */
if (inst->size == 4)
emit_mov_p32_r32(drcbe, &dst, &dstp, dstreg); // mov dstp,dstreg
@@ -4206,7 +4206,7 @@ static x86code *op_read2m(drcbe_state *drcbe, x86code *dst, const drcuml_instruc
emit_mov_r32_p32(drcbe, &dst, REG_PARAM2, &maskp); // mov param1,maskp
emit_smart_call_m64(drcbe, &dst, (x86code **)&drcbe->accessors[spacep.value].read_word_masked);// call read_word_masked
emit_movzx_r32_r16(&dst, dstreg, REG_AX); // movzx dstreg,ax
-
+
/* store to appropriate target size */
if (inst->size == 4)
emit_mov_p32_r32(drcbe, &dst, &dstp, dstreg); // mov dstp,dstreg
@@ -4235,7 +4235,7 @@ static x86code *op_read4u(drcbe_state *drcbe, x86code *dst, const drcuml_instruc
/* set up a call to the read dword handler */
emit_mov_r32_p32(drcbe, &dst, REG_PARAM1, &addrp); // mov param1,addrp
emit_smart_call_m64(drcbe, &dst, (x86code **)&drcbe->accessors[spacep.value].read_dword);// call read_dword
-
+
/* store to appropriate target size */
if (inst->size == 4)
emit_mov_p32_r32(drcbe, &dst, &dstp, REG_EAX); // mov dstp,eax
@@ -4296,7 +4296,7 @@ static x86code *op_read4m(drcbe_state *drcbe, x86code *dst, const drcuml_instruc
emit_mov_r32_p32(drcbe, &dst, REG_PARAM1, &addrp); // mov param1,addrp
emit_mov_r32_p32(drcbe, &dst, REG_PARAM2, &maskp); // mov param2,maskp
emit_smart_call_m64(drcbe, &dst, (x86code **)&drcbe->accessors[spacep.value].read_dword_masked);// call read_dword_masked
-
+
/* store to appropriate target size */
if (inst->size == 4)
emit_mov_p32_r32(drcbe, &dst, &dstp, REG_EAX); // mov dstp,eax
@@ -4564,7 +4564,7 @@ static x86code *op_flags(drcbe_state *drcbe, x86code *dst, const drcuml_instruct
// mov dstreg,[eax*4+table]
emit_mov_p32_r32(drcbe, &dst, &dstp, dstreg); // mov dstp,dstreg
}
-
+
/* general case */
else
{
@@ -4577,7 +4577,7 @@ static x86code *op_flags(drcbe_state *drcbe, x86code *dst, const drcuml_instruct
emit_mov_p32_r32(drcbe, &dst, &dstp, dstreg); // mov dstp,dstreg
}
}
-
+
/* 64-bit form */
else
{
@@ -4588,7 +4588,7 @@ static x86code *op_flags(drcbe_state *drcbe, x86code *dst, const drcuml_instruct
// mov dstreg,[eax*8+table]
emit_mov_p64_r64(drcbe, &dst, &dstp, dstreg); // mov dstp,dstreg
}
-
+
/* general case */
else
{
@@ -4641,7 +4641,7 @@ static x86code *op_mov(drcbe_state *drcbe, x86code *dst, const drcuml_instructio
dstp = inst->param[0];
srcp = inst->param[1];
}
-
+
/* degenerate case: dest and source are equal */
if (dstp.type == srcp.type && dstp.value == srcp.value)
return dst;
@@ -4663,7 +4663,7 @@ static x86code *op_mov(drcbe_state *drcbe, x86code *dst, const drcuml_instructio
/* immediate to memory */
else if (dstp.type == DRCUML_PTYPE_MEMORY && srcp.type == DRCUML_PTYPE_IMMEDIATE)
emit_mov_m32_imm(&dst, MABS(drcbe, dstp.value), srcp.value); // mov [dstp],srcp
-
+
/* conditional memory to register */
else if (inst->condflags != 0 && dstp.type == DRCUML_PTYPE_INT_REGISTER && srcp.type == DRCUML_PTYPE_MEMORY)
{
@@ -4689,7 +4689,7 @@ static x86code *op_mov(drcbe_state *drcbe, x86code *dst, const drcuml_instructio
emit_mov_p32_r32(drcbe, &dst, &dstp, dstreg); // mov dstp,dstreg
}
}
-
+
/* 64-bit form */
else if (inst->size == 8)
{
@@ -4700,7 +4700,7 @@ static x86code *op_mov(drcbe_state *drcbe, x86code *dst, const drcuml_instructio
/* immediate to memory */
else if (dstp.type == DRCUML_PTYPE_MEMORY && srcp.type == DRCUML_PTYPE_IMMEDIATE && short_immediate(srcp.value))
emit_mov_m64_imm(&dst, MABS(drcbe, dstp.value), srcp.value); // mov [dstp],srcp
-
+
/* conditional memory to register */
else if (inst->condflags != 0 && dstp.type == DRCUML_PTYPE_INT_REGISTER && srcp.type == DRCUML_PTYPE_MEMORY)
{
@@ -4756,7 +4756,7 @@ static x86code *op_zext1(drcbe_state *drcbe, x86code *dst, const drcuml_instruct
/* pick a target register for the general case */
dstreg = param_select_register(REG_EAX, &dstp, NULL);
-
+
/* general case */
if (srcp.type == DRCUML_PTYPE_MEMORY)
emit_movzx_r32_m8(&dst, dstreg, MABS(drcbe, srcp.value)); // movzx dstreg,[srcp]
@@ -4797,7 +4797,7 @@ static x86code *op_zext2(drcbe_state *drcbe, x86code *dst, const drcuml_instruct
/* pick a target register for the general case */
dstreg = param_select_register(REG_EAX, &dstp, NULL);
-
+
/* general case */
if (srcp.type == DRCUML_PTYPE_MEMORY)
emit_movzx_r32_m16(&dst, dstreg, MABS(drcbe, srcp.value)); // movzx dstreg,[srcp]
@@ -4838,7 +4838,7 @@ static x86code *op_zext4(drcbe_state *drcbe, x86code *dst, const drcuml_instruct
/* pick a target register for the general case */
dstreg = param_select_register(REG_EAX, &dstp, NULL);
-
+
/* general case */
if (srcp.type == DRCUML_PTYPE_MEMORY)
emit_mov_r32_m32(&dst, dstreg, MABS(drcbe, srcp.value)); // mov dstreg,[srcp]
@@ -4872,14 +4872,14 @@ static x86code *op_sext1(drcbe_state *drcbe, x86code *dst, const drcuml_instruct
/* pick a target register for the general case */
dstreg = param_select_register(REG_EAX, &dstp, NULL);
-
+
/* convert 8-bit source registers */
if (srcp.type == DRCUML_PTYPE_INT_REGISTER && (srcp.value & 4))
{
emit_mov_r32_r32(&dst, REG_EAX, srcp.value); // mov eax,srcp
srcp.value = REG_EAX;
}
-
+
/* 32-bit form */
if (inst->size == 4)
{
@@ -4927,7 +4927,7 @@ static x86code *op_sext2(drcbe_state *drcbe, x86code *dst, const drcuml_instruct
/* pick a target register for the general case */
dstreg = param_select_register(REG_EAX, &dstp, NULL);
-
+
/* 32-bit form */
if (inst->size == 4)
{
@@ -4975,7 +4975,7 @@ static x86code *op_sext4(drcbe_state *drcbe, x86code *dst, const drcuml_instruct
/* pick a target register for the general case */
dstreg = param_select_register(REG_EAX, &dstp, NULL);
-
+
/* 64-bit form */
if (inst->size == 8)
{
@@ -5014,7 +5014,7 @@ static x86code *op_add(drcbe_state *drcbe, x86code *dst, const drcuml_instructio
/* pick a target register for the general case */
dstreg = param_select_register(REG_EAX, &dstp, &src2p);
-
+
/* 32-bit form */
if (inst->size == 4)
{
@@ -5038,7 +5038,7 @@ static x86code *op_add(drcbe_state *drcbe, x86code *dst, const drcuml_instructio
emit_mov_p32_r32(drcbe, &dst, &dstp, dstreg); // mov dstp,dstreg
}
}
-
+
/* 64-bit form */
else if (inst->size == 8)
{
@@ -5084,7 +5084,7 @@ static x86code *op_addc(drcbe_state *drcbe, x86code *dst, const drcuml_instructi
/* pick a target register for the general case */
dstreg = param_select_register(REG_EAX, &dstp, &src2p);
-
+
/* 32-bit form */
if (inst->size == 4)
{
@@ -5100,7 +5100,7 @@ static x86code *op_addc(drcbe_state *drcbe, x86code *dst, const drcuml_instructi
emit_mov_p32_r32(drcbe, &dst, &dstp, dstreg); // mov dstp,dstreg
}
}
-
+
/* 64-bit form */
else if (inst->size == 8)
{
@@ -5144,7 +5144,7 @@ static x86code *op_sub(drcbe_state *drcbe, x86code *dst, const drcuml_instructio
/* pick a target register for the general case */
dstreg = param_select_register(REG_EAX, &dstp, &src2p);
-
+
/* 32-bit form */
if (inst->size == 4)
{
@@ -5164,7 +5164,7 @@ static x86code *op_sub(drcbe_state *drcbe, x86code *dst, const drcuml_instructio
emit_mov_p32_r32(drcbe, &dst, &dstp, dstreg); // mov dstp,dstreg
}
}
-
+
/* 64-bit form */
else if (inst->size == 8)
{
@@ -5206,7 +5206,7 @@ static x86code *op_subc(drcbe_state *drcbe, x86code *dst, const drcuml_instructi
/* pick a target register for the general case */
dstreg = param_select_register(REG_EAX, &dstp, &src2p);
-
+
/* 32-bit form */
if (inst->size == 4)
{
@@ -5222,7 +5222,7 @@ static x86code *op_subc(drcbe_state *drcbe, x86code *dst, const drcuml_instructi
emit_mov_p32_r32(drcbe, &dst, &dstp, dstreg); // mov dstp,dstreg
}
}
-
+
/* 64-bit form */
else if (inst->size == 8)
{
@@ -5267,14 +5267,14 @@ static x86code *op_cmp(drcbe_state *drcbe, x86code *dst, const drcuml_instructio
/* pick a target register for the general case */
src1reg = param_select_register(REG_EAX, &src1p, NULL);
-
+
/* 32-bit form */
if (inst->size == 4)
{
/* memory versus anything */
if (src1p.type == DRCUML_PTYPE_MEMORY)
emit_cmp_m32_p32(drcbe, &dst, MABS(drcbe, src1p.value), &src2p, inst); // cmp [dstp],src2p
-
+
/* general case */
else
{
@@ -5283,14 +5283,14 @@ static x86code *op_cmp(drcbe_state *drcbe, x86code *dst, const drcuml_instructio
emit_cmp_r32_p32(drcbe, &dst, src1reg, &src2p, inst); // cmp src1reg,src2p
}
}
-
+
/* 64-bit form */
else
{
/* memory versus anything */
if (src1p.type == DRCUML_PTYPE_MEMORY)
emit_cmp_m64_p64(drcbe, &dst, MABS(drcbe, src1p.value), &src2p, inst); // cmp [dstp],src2p
-
+
/* general case */
else
{
@@ -5354,7 +5354,7 @@ static x86code *op_mulu(drcbe_state *drcbe, x86code *dst, const drcuml_instructi
if (compute_hi)
emit_mov_p32_r32(drcbe, &dst, &edstp, REG_EDX); // mov edstp,edx
}
-
+
/* 64-bit form */
else if (inst->size == 8)
{
@@ -5422,7 +5422,7 @@ static x86code *op_muls(drcbe_state *drcbe, x86code *dst, const drcuml_instructi
emit_imul_r32_r32_imm(&dst, REG_EAX, src1p.value, src2p.value); // imul eax,src1p,src2p
emit_mov_p32_r32(drcbe, &dst, &dstp, REG_EAX); // mov dstp,eax
}
-
+
/* 32-bit destination, general case */
else if (!compute_hi)
{
@@ -5433,7 +5433,7 @@ static x86code *op_muls(drcbe_state *drcbe, x86code *dst, const drcuml_instructi
emit_imul_r32_r32(&dst, REG_EAX, src2p.value); // imul eax,src2p
emit_mov_p32_r32(drcbe, &dst, &dstp, REG_EAX); // mov dstp,eax
}
-
+
/* 64-bit destination, general case */
else
{
@@ -5451,7 +5451,7 @@ static x86code *op_muls(drcbe_state *drcbe, x86code *dst, const drcuml_instructi
emit_mov_p32_r32(drcbe, &dst, &edstp, REG_EDX); // mov edstp,edx
}
}
-
+
/* 64-bit form */
else if (inst->size == 8)
{
@@ -5464,7 +5464,7 @@ static x86code *op_muls(drcbe_state *drcbe, x86code *dst, const drcuml_instructi
emit_imul_r64_r64_imm(&dst, REG_RAX, src1p.value, src2p.value); // imul rax,src1p,src2p
emit_mov_p64_r64(drcbe, &dst, &dstp, REG_RAX); // mov dstp,rax
}
-
+
/* 64-bit destination, general case */
else if (!compute_hi)
{
@@ -5475,7 +5475,7 @@ static x86code *op_muls(drcbe_state *drcbe, x86code *dst, const drcuml_instructi
emit_imul_r64_r64(&dst, REG_RAX, src2p.value); // imul rax,src2p
emit_mov_p64_r64(drcbe, &dst, &dstp, REG_RAX); // mov dstp,rax
}
-
+
/* 128-bit destination, general case */
else
{
@@ -5564,7 +5564,7 @@ static x86code *op_divu(drcbe_state *drcbe, x86code *dst, const drcuml_instructi
emit_mov_p32_r32(drcbe, &dst, &edstp, REG_EDX); // mov edstp,edx
resolve_link(&dst, &skip); // skip:
}
-
+
/* 64-bit form */
else if (inst->size == 8)
{
@@ -5650,7 +5650,7 @@ static x86code *op_divs(drcbe_state *drcbe, x86code *dst, const drcuml_instructi
emit_mov_p32_r32(drcbe, &dst, &edstp, REG_EDX); // mov edstp,edx
resolve_link(&dst, &skip); // skip:
}
-
+
/* 64-bit form */
else if (inst->size == 8)
{
@@ -5693,7 +5693,7 @@ static x86code *op_and(drcbe_state *drcbe, x86code *dst, const drcuml_instructio
/* pick a target register for the general case */
dstreg = param_select_register(REG_EAX, &dstp, &src2p);
-
+
/* 32-bit form */
if (inst->size == 4)
{
@@ -5709,7 +5709,7 @@ static x86code *op_and(drcbe_state *drcbe, x86code *dst, const drcuml_instructio
emit_mov_p32_r32(drcbe, &dst, &dstp, dstreg); // mov dstp,dstreg
}
}
-
+
/* 64-bit form */
else if (inst->size == 8)
{
@@ -5744,10 +5744,10 @@ static x86code *op_test(drcbe_state *drcbe, x86code *dst, const drcuml_instructi
/* normalize parameters */
param_normalize_2_commutative(drcbe, inst, &src1p, PTYPE_MRI, &src2p, PTYPE_MRI);
-
+
/* pick a target register for the general case */
src1reg = param_select_register(REG_EAX, &src1p, NULL);
-
+
/* 32-bit form */
if (inst->size == 4)
{
@@ -5762,7 +5762,7 @@ static x86code *op_test(drcbe_state *drcbe, x86code *dst, const drcuml_instructi
emit_test_r32_p32(drcbe, &dst, src1reg, &src2p, inst); // test src1reg,src2p
}
}
-
+
/* 64-bit form */
else if (inst->size == 8)
{
@@ -5805,7 +5805,7 @@ static x86code *op_or(drcbe_state *drcbe, x86code *dst, const drcuml_instruction
/* pick a target register for the general case */
dstreg = param_select_register(REG_EAX, &dstp, &src2p);
-
+
/* 32-bit form */
if (inst->size == 4)
{
@@ -5821,7 +5821,7 @@ static x86code *op_or(drcbe_state *drcbe, x86code *dst, const drcuml_instruction
emit_mov_p32_r32(drcbe, &dst, &dstp, dstreg); // mov dstp,dstreg
}
}
-
+
/* 64-bit form */
else if (inst->size == 8)
{
@@ -5865,7 +5865,7 @@ static x86code *op_xor(drcbe_state *drcbe, x86code *dst, const drcuml_instructio
/* pick a target register for the general case */
dstreg = param_select_register(REG_EAX, &dstp, &src2p);
-
+
/* 32-bit form */
if (inst->size == 4)
{
@@ -5881,7 +5881,7 @@ static x86code *op_xor(drcbe_state *drcbe, x86code *dst, const drcuml_instructio
emit_mov_p32_r32(drcbe, &dst, &dstp, dstreg); // mov dstp,dstreg
}
}
-
+
/* 64-bit form */
else if (inst->size == 8)
{
@@ -5925,7 +5925,7 @@ static x86code *op_shl(drcbe_state *drcbe, x86code *dst, const drcuml_instructio
/* pick a target register for the general case */
dstreg = param_select_register(REG_EAX, &dstp, &src2p);
-
+
/* 32-bit form */
if (inst->size == 4)
{
@@ -5941,7 +5941,7 @@ static x86code *op_shl(drcbe_state *drcbe, x86code *dst, const drcuml_instructio
emit_mov_p32_r32(drcbe, &dst, &dstp, dstreg); // mov dstp,dstreg
}
}
-
+
/* 64-bit form */
else if (inst->size == 8)
{
@@ -5985,7 +5985,7 @@ static x86code *op_shr(drcbe_state *drcbe, x86code *dst, const drcuml_instructio
/* pick a target register for the general case */
dstreg = param_select_register(REG_EAX, &dstp, &src2p);
-
+
/* 32-bit form */
if (inst->size == 4)
{
@@ -6001,7 +6001,7 @@ static x86code *op_shr(drcbe_state *drcbe, x86code *dst, const drcuml_instructio
emit_mov_p32_r32(drcbe, &dst, &dstp, dstreg); // mov dstp,dstreg
}
}
-
+
/* 64-bit form */
else if (inst->size == 8)
{
@@ -6050,7 +6050,7 @@ static x86code *op_sar(drcbe_state *drcbe, x86code *dst, const drcuml_instructio
/* pick a target register for the general case */
dstreg = param_select_register(REG_EAX, &dstp, &src2p);
-
+
/* 32-bit form */
if (inst->size == 4)
{
@@ -6066,7 +6066,7 @@ static x86code *op_sar(drcbe_state *drcbe, x86code *dst, const drcuml_instructio
emit_mov_p32_r32(drcbe, &dst, &dstp, dstreg); // mov dstp,dstreg
}
}
-
+
/* 64-bit form */
else if (inst->size == 8)
{
@@ -6110,7 +6110,7 @@ static x86code *op_rol(drcbe_state *drcbe, x86code *dst, const drcuml_instructio
/* pick a target register for the general case */
dstreg = param_select_register(REG_EAX, &dstp, &src2p);
-
+
/* 32-bit form */
if (inst->size == 4)
{
@@ -6126,7 +6126,7 @@ static x86code *op_rol(drcbe_state *drcbe, x86code *dst, const drcuml_instructio
emit_mov_p32_r32(drcbe, &dst, &dstp, dstreg); // mov dstp,dstreg
}
}
-
+
/* 64-bit form */
else if (inst->size == 8)
{
@@ -6167,10 +6167,10 @@ static x86code *op_ror(drcbe_state *drcbe, x86code *dst, const drcuml_instructio
return convert_to_mov_imm(drcbe, dst, inst, &dstp, (UINT64)src1p.value >> src2p.value);
if (src2p.type == DRCUML_PTYPE_IMMEDIATE && src2p.value == 0 && inst->condflags == 0)
return convert_to_mov_src1(drcbe, dst, inst, &dstp, &src1p);
-
+
/* pick a target register for the general case */
dstreg = param_select_register(REG_EAX, &dstp, &src2p);
-
+
/* 32-bit form */
if (inst->size == 4)
{
@@ -6186,7 +6186,7 @@ static x86code *op_ror(drcbe_state *drcbe, x86code *dst, const drcuml_instructio
emit_mov_p32_r32(drcbe, &dst, &dstp, dstreg); // mov dstp,dstreg
}
}
-
+
/* 64-bit form */
else if (inst->size == 8)
{
@@ -6230,7 +6230,7 @@ static x86code *op_rolc(drcbe_state *drcbe, x86code *dst, const drcuml_instructi
/* pick a target register for the general case */
dstreg = param_select_register(REG_EAX, &dstp, &src2p);
-
+
/* 32-bit form */
if (inst->size == 4)
{
@@ -6246,7 +6246,7 @@ static x86code *op_rolc(drcbe_state *drcbe, x86code *dst, const drcuml_instructi
emit_mov_p32_r32(drcbe, &dst, &dstp, dstreg); // mov dstp,dstreg
}
}
-
+
/* 64-bit form */
else if (inst->size == 8)
{
@@ -6287,10 +6287,10 @@ static x86code *op_rorc(drcbe_state *drcbe, x86code *dst, const drcuml_instructi
return convert_to_mov_imm(drcbe, dst, inst, &dstp, (UINT64)src1p.value >> src2p.value);
if (src2p.type == DRCUML_PTYPE_IMMEDIATE && src2p.value == 0 && inst->condflags == 0)
return convert_to_mov_src1(drcbe, dst, inst, &dstp, &src1p);
-
+
/* pick a target register for the general case */
dstreg = param_select_register(REG_EAX, &dstp, &src2p);
-
+
/* 32-bit form */
if (inst->size == 4)
{
@@ -6306,7 +6306,7 @@ static x86code *op_rorc(drcbe_state *drcbe, x86code *dst, const drcuml_instructi
emit_mov_p32_r32(drcbe, &dst, &dstp, dstreg); // mov dstp,dstreg
}
}
-
+
/* 64-bit form */
else if (inst->size == 8)
{
@@ -6347,13 +6347,13 @@ static x86code *op_fload(drcbe_state *drcbe, x86code *dst, const drcuml_instruct
/* normalize parameters */
param_normalize_3(drcbe, inst, &dstp, PTYPE_MF, &basep, PTYPE_M, &indp, PTYPE_MRI);
-
+
/* pick a target register for the general case */
dstreg = param_select_register(REG_XMM0, &dstp, NULL);
-
+
/* determine the pointer base */
basereg = get_base_register_and_offset(drcbe, &dst, basep.value, REG_RDX, &baseoffs);
-
+
/* 32-bit form */
if (inst->size == 4)
{
@@ -6367,7 +6367,7 @@ static x86code *op_fload(drcbe_state *drcbe, x86code *dst, const drcuml_instruct
}
emit_movss_p32_r128(drcbe, &dst, &dstp, dstreg); // movss dstp,dstreg
}
-
+
/* 64-bit form */
else if (inst->size == 8)
{
@@ -6401,13 +6401,13 @@ static x86code *op_fstore(drcbe_state *drcbe, x86code *dst, const drcuml_instruc
/* normalize parameters */
param_normalize_3(drcbe, inst, &basep, PTYPE_M, &indp, PTYPE_MRI, &srcp, PTYPE_MF);
-
+
/* pick a target register for the general case */
srcreg = param_select_register(REG_XMM0, &srcp, NULL);
-
+
/* determine the pointer base */
basereg = get_base_register_and_offset(drcbe, &dst, basep.value, REG_RDX, &baseoffs);
-
+
/* 32-bit form */
if (inst->size == 4)
{
@@ -6421,7 +6421,7 @@ static x86code *op_fstore(drcbe_state *drcbe, x86code *dst, const drcuml_instruc
emit_movss_m32_r128(&dst, MBISD(basereg, indreg, 4, baseoffs), srcreg); // movss [basep + 4*indp],srcreg
}
}
-
+
/* 64-bit form */
else if (inst->size == 8)
{
@@ -6453,7 +6453,7 @@ static x86code *op_fread(drcbe_state *drcbe, x86code *dst, const drcuml_instruct
/* normalize parameters */
param_normalize_3(drcbe, inst, &dstp, PTYPE_MF, &spacep, PTYPE_I, &addrp, PTYPE_MRI);
-
+
/* set up a call to the read dword/qword handler */
emit_mov_r32_p32(drcbe, &dst, REG_PARAM1, &addrp); // mov param1,addrp
if (inst->size == 4)
@@ -6497,7 +6497,7 @@ static x86code *op_fwrite(drcbe_state *drcbe, x86code *dst, const drcuml_instruc
/* general case */
emit_mov_r32_p32(drcbe, &dst, REG_PARAM1, &addrp); // mov param1,addrp
-
+
/* 32-bit form */
if (inst->size == 4)
{
@@ -6507,7 +6507,7 @@ static x86code *op_fwrite(drcbe_state *drcbe, x86code *dst, const drcuml_instruc
emit_movd_r32_r128(&dst, REG_PARAM2, srcp.value); // movd param2,srcp
emit_smart_call_m64(drcbe, &dst, (x86code **)&drcbe->accessors[spacep.value].write_dword);// call write_dword
}
-
+
/* 64-bit form */
else if (inst->size == 8)
{
@@ -6541,18 +6541,18 @@ static x86code *op_fmov(drcbe_state *drcbe, x86code *dst, const drcuml_instructi
/* pick a target register for the general case */
dstreg = param_select_register(REG_XMM0, &dstp, NULL);
-
+
/* always start with a jmp */
if (inst->condflags != DRCUML_COND_ALWAYS)
emit_jcc_short_link(&dst, X86_NOT_CONDITION(inst->condflags), &skip); // jcc skip
-
+
/* 32-bit form */
if (inst->size == 4)
{
emit_movss_r128_p32(drcbe, &dst, dstreg, &srcp); // movss dstreg,srcp
emit_movss_p32_r128(drcbe, &dst, &dstp, dstreg); // movss dstp,dstreg
}
-
+
/* 64-bit form */
else if (inst->size == 8)
{
@@ -6585,7 +6585,7 @@ static x86code *op_ftoi4(drcbe_state *drcbe, x86code *dst, const drcuml_instruct
/* pick a target register for the general case */
dstreg = param_select_register(REG_EAX, &dstp, NULL);
-
+
/* 32-bit form */
if (inst->size == 4)
{
@@ -6594,7 +6594,7 @@ static x86code *op_ftoi4(drcbe_state *drcbe, x86code *dst, const drcuml_instruct
else if (srcp.type == DRCUML_PTYPE_FLOAT_REGISTER)
emit_cvtss2si_r32_r128(&dst, dstreg, srcp.value); // cvtss2si dstreg,srcp
}
-
+
/* 64-bit form */
else if (inst->size == 8)
{
@@ -6603,7 +6603,7 @@ static x86code *op_ftoi4(drcbe_state *drcbe, x86code *dst, const drcuml_instruct
else if (srcp.type == DRCUML_PTYPE_FLOAT_REGISTER)
emit_cvtsd2si_r32_r128(&dst, dstreg, srcp.value); // cvtsd2si dstreg,srcp
}
-
+
/* general case */
emit_mov_p32_r32(drcbe, &dst, &dstp, dstreg); // mov dstp,dstreg
return dst;
@@ -6628,7 +6628,7 @@ static x86code *op_ftoi4t(drcbe_state *drcbe, x86code *dst, const drcuml_instruc
/* pick a target register for the general case */
dstreg = param_select_register(REG_EAX, &dstp, NULL);
-
+
/* 32-bit form */
if (inst->size == 4)
{
@@ -6637,7 +6637,7 @@ static x86code *op_ftoi4t(drcbe_state *drcbe, x86code *dst, const drcuml_instruc
else if (srcp.type == DRCUML_PTYPE_FLOAT_REGISTER)
emit_cvttss2si_r32_r128(&dst, dstreg, srcp.value); // cvttss2si dstreg,srcp
}
-
+
/* 64-bit form */
else if (inst->size == 8)
{
@@ -6646,7 +6646,7 @@ static x86code *op_ftoi4t(drcbe_state *drcbe, x86code *dst, const drcuml_instruc
else if (srcp.type == DRCUML_PTYPE_FLOAT_REGISTER)
emit_cvttsd2si_r32_r128(&dst, dstreg, srcp.value); // cvttsd2si dstreg,srcp
}
-
+
/* general case */
emit_mov_p32_r32(drcbe, &dst, &dstp, dstreg); // mov dstp,dstreg
return dst;
@@ -6671,7 +6671,7 @@ static x86code *op_ftoi4r(drcbe_state *drcbe, x86code *dst, const drcuml_instruc
/* pick a target register for the general case */
dstreg = param_select_register(REG_EAX, &dstp, NULL);
-
+
/* save and set the control word */
emit_stmxcsr_m32(&dst, MABS(drcbe, &drcbe->ssemodesave)); // stmxcsr [ssemodesave]
emit_ldmxcsr_m32(&dst, MABS(drcbe, &drcbe->ssecontrol[DRCUML_FMOD_ROUND])); // ldmxcsr fpcontrol[DRCUML_FMOD_ROUND]
@@ -6684,7 +6684,7 @@ static x86code *op_ftoi4r(drcbe_state *drcbe, x86code *dst, const drcuml_instruc
else if (srcp.type == DRCUML_PTYPE_FLOAT_REGISTER)
emit_cvtss2si_r32_r128(&dst, dstreg, srcp.value); // cvtss2si dstreg,srcp
}
-
+
/* 64-bit form */
else if (inst->size == 8)
{
@@ -6719,7 +6719,7 @@ static x86code *op_ftoi4f(drcbe_state *drcbe, x86code *dst, const drcuml_instruc
/* pick a target register for the general case */
dstreg = param_select_register(REG_EAX, &dstp, NULL);
-
+
/* save and set the control word */
emit_stmxcsr_m32(&dst, MABS(drcbe, &drcbe->ssemodesave)); // stmxcsr [ssemodesave]
emit_ldmxcsr_m32(&dst, MABS(drcbe, &drcbe->ssecontrol[DRCUML_FMOD_FLOOR])); // ldmxcsr fpcontrol[DRCUML_FMOD_FLOOR]
@@ -6732,7 +6732,7 @@ static x86code *op_ftoi4f(drcbe_state *drcbe, x86code *dst, const drcuml_instruc
else if (srcp.type == DRCUML_PTYPE_FLOAT_REGISTER)
emit_cvtss2si_r32_r128(&dst, dstreg, srcp.value); // cvtss2si dstreg,srcp
}
-
+
/* 64-bit form */
else if (inst->size == 8)
{
@@ -6767,7 +6767,7 @@ static x86code *op_ftoi4c(drcbe_state *drcbe, x86code *dst, const drcuml_instruc
/* pick a target register for the general case */
dstreg = param_select_register(REG_EAX, &dstp, NULL);
-
+
/* save and set the control word */
emit_stmxcsr_m32(&dst, MABS(drcbe, &drcbe->ssemodesave)); // stmxcsr [ssemodesave]
emit_ldmxcsr_m32(&dst, MABS(drcbe, &drcbe->ssecontrol[DRCUML_FMOD_CEIL])); // ldmxcsr fpcontrol[DRCUML_FMOD_CEIL]
@@ -6780,7 +6780,7 @@ static x86code *op_ftoi4c(drcbe_state *drcbe, x86code *dst, const drcuml_instruc
else if (srcp.type == DRCUML_PTYPE_FLOAT_REGISTER)
emit_cvtss2si_r32_r128(&dst, dstreg, srcp.value); // cvtss2si dstreg,srcp
}
-
+
/* 64-bit form */
else if (inst->size == 8)
{
@@ -6815,7 +6815,7 @@ static x86code *op_ftoi8(drcbe_state *drcbe, x86code *dst, const drcuml_instruct
/* pick a target register for the general case */
dstreg = param_select_register(REG_EAX, &dstp, NULL);
-
+
/* 32-bit form */
if (inst->size == 4)
{
@@ -6824,7 +6824,7 @@ static x86code *op_ftoi8(drcbe_state *drcbe, x86code *dst, const drcuml_instruct
else if (srcp.type == DRCUML_PTYPE_FLOAT_REGISTER)
emit_cvtss2si_r64_r128(&dst, dstreg, srcp.value); // cvtss2si dstreg,srcp
}
-
+
/* 64-bit form */
else if (inst->size == 8)
{
@@ -6833,7 +6833,7 @@ static x86code *op_ftoi8(drcbe_state *drcbe, x86code *dst, const drcuml_instruct
else if (srcp.type == DRCUML_PTYPE_FLOAT_REGISTER)
emit_cvtsd2si_r64_r128(&dst, dstreg, srcp.value); // cvtsd2si dstreg,srcp
}
-
+
/* general case */
emit_mov_p64_r64(drcbe, &dst, &dstp, dstreg); // mov dstp,dstreg
return dst;
@@ -6858,7 +6858,7 @@ static x86code *op_ftoi8t(drcbe_state *drcbe, x86code *dst, const drcuml_instruc
/* pick a target register for the general case */
dstreg = param_select_register(REG_EAX, &dstp, NULL);
-
+
/* 32-bit form */
if (inst->size == 4)
{
@@ -6867,7 +6867,7 @@ static x86code *op_ftoi8t(drcbe_state *drcbe, x86code *dst, const drcuml_instruc
else if (srcp.type == DRCUML_PTYPE_FLOAT_REGISTER)
emit_cvttss2si_r64_r128(&dst, dstreg, srcp.value); // cvttss2si dstreg,srcp
}
-
+
/* 64-bit form */
else if (inst->size == 8)
{
@@ -6876,7 +6876,7 @@ static x86code *op_ftoi8t(drcbe_state *drcbe, x86code *dst, const drcuml_instruc
else if (srcp.type == DRCUML_PTYPE_FLOAT_REGISTER)
emit_cvttsd2si_r64_r128(&dst, dstreg, srcp.value); // cvttsd2si dstreg,srcp
}
-
+
/* general case */
emit_mov_p64_r64(drcbe, &dst, &dstp, dstreg); // mov dstp,dstreg
return dst;
@@ -6901,7 +6901,7 @@ static x86code *op_ftoi8r(drcbe_state *drcbe, x86code *dst, const drcuml_instruc
/* pick a target register for the general case */
dstreg = param_select_register(REG_EAX, &dstp, NULL);
-
+
/* save and set the control word */
emit_stmxcsr_m32(&dst, MABS(drcbe, &drcbe->ssemodesave)); // stmxcsr [ssemodesave]
emit_ldmxcsr_m32(&dst, MABS(drcbe, &drcbe->ssecontrol[DRCUML_FMOD_ROUND])); // ldmxcsr fpcontrol[DRCUML_FMOD_ROUND]
@@ -6914,7 +6914,7 @@ static x86code *op_ftoi8r(drcbe_state *drcbe, x86code *dst, const drcuml_instruc
else if (srcp.type == DRCUML_PTYPE_FLOAT_REGISTER)
emit_cvtss2si_r64_r128(&dst, dstreg, srcp.value); // cvtss2si dstreg,srcp
}
-
+
/* 64-bit form */
else if (inst->size == 8)
{
@@ -6949,7 +6949,7 @@ static x86code *op_ftoi8f(drcbe_state *drcbe, x86code *dst, const drcuml_instruc
/* pick a target register for the general case */
dstreg = param_select_register(REG_EAX, &dstp, NULL);
-
+
/* save and set the control word */
emit_stmxcsr_m32(&dst, MABS(drcbe, &drcbe->ssemodesave)); // stmxcsr [ssemodesave]
emit_ldmxcsr_m32(&dst, MABS(drcbe, &drcbe->ssecontrol[DRCUML_FMOD_FLOOR])); // ldmxcsr fpcontrol[DRCUML_FMOD_FLOOR]
@@ -6962,7 +6962,7 @@ static x86code *op_ftoi8f(drcbe_state *drcbe, x86code *dst, const drcuml_instruc
else if (srcp.type == DRCUML_PTYPE_FLOAT_REGISTER)
emit_cvtss2si_r64_r128(&dst, dstreg, srcp.value); // cvtss2si dstreg,srcp
}
-
+
/* 64-bit form */
else if (inst->size == 8)
{
@@ -6997,7 +6997,7 @@ static x86code *op_ftoi8c(drcbe_state *drcbe, x86code *dst, const drcuml_instruc
/* pick a target register for the general case */
dstreg = param_select_register(REG_EAX, &dstp, NULL);
-
+
/* save and set the control word */
emit_stmxcsr_m32(&dst, MABS(drcbe, &drcbe->ssemodesave)); // stmxcsr [ssemodesave]
emit_ldmxcsr_m32(&dst, MABS(drcbe, &drcbe->ssecontrol[DRCUML_FMOD_CEIL])); // ldmxcsr fpcontrol[DRCUML_FMOD_CEIL]
@@ -7010,7 +7010,7 @@ static x86code *op_ftoi8c(drcbe_state *drcbe, x86code *dst, const drcuml_instruc
else if (srcp.type == DRCUML_PTYPE_FLOAT_REGISTER)
emit_cvtss2si_r64_r128(&dst, dstreg, srcp.value); // cvtss2si dstreg,srcp
}
-
+
/* 64-bit form */
else if (inst->size == 8)
{
@@ -7105,7 +7105,7 @@ static x86code *op_ffri4(drcbe_state *drcbe, x86code *dst, const drcuml_instruct
/* pick a target register for the general case */
dstreg = param_select_register(REG_XMM0, &dstp, NULL);
-
+
/* 32-bit form */
if (inst->size == 4)
{
@@ -7155,7 +7155,7 @@ static x86code *op_ffri8(drcbe_state *drcbe, x86code *dst, const drcuml_instruct
/* pick a target register for the general case */
dstreg = param_select_register(REG_XMM0, &dstp, NULL);
-
+
/* 32-bit form */
if (inst->size == 4)
{
@@ -7205,7 +7205,7 @@ static x86code *op_fadd(drcbe_state *drcbe, x86code *dst, const drcuml_instructi
/* pick a target register for the general case */
dstreg = param_select_register(REG_XMM0, &dstp, &src2p);
-
+
/* 32-bit form */
if (inst->size == 4)
{
@@ -7216,7 +7216,7 @@ static x86code *op_fadd(drcbe_state *drcbe, x86code *dst, const drcuml_instructi
emit_addss_r128_r128(&dst, dstreg, src2p.value); // addss dstreg,src2p
emit_movss_p32_r128(drcbe, &dst, &dstp, dstreg); // movss dstp,dstreg
}
-
+
/* 64-bit form */
else if (inst->size == 8)
{
@@ -7249,7 +7249,7 @@ static x86code *op_fsub(drcbe_state *drcbe, x86code *dst, const drcuml_instructi
/* pick a target register for the general case */
dstreg = param_select_register(REG_XMM0, &dstp, &src2p);
-
+
/* 32-bit form */
if (inst->size == 4)
{
@@ -7260,7 +7260,7 @@ static x86code *op_fsub(drcbe_state *drcbe, x86code *dst, const drcuml_instructi
emit_subss_r128_r128(&dst, dstreg, src2p.value); // subss dstreg,src2p
emit_movss_p32_r128(drcbe, &dst, &dstp, dstreg); // movss dstp,dstreg
}
-
+
/* 64-bit form */
else if (inst->size == 8)
{
@@ -7293,7 +7293,7 @@ static x86code *op_fcmp(drcbe_state *drcbe, x86code *dst, const drcuml_instructi
/* pick a target register for the general case */
src1reg = param_select_register(REG_XMM0, &src1p, NULL);
-
+
/* 32-bit form */
if (inst->size == 4)
{
@@ -7303,7 +7303,7 @@ static x86code *op_fcmp(drcbe_state *drcbe, x86code *dst, const drcuml_instructi
else if (src2p.type == DRCUML_PTYPE_FLOAT_REGISTER)
emit_comiss_r128_r128(&dst, src1reg, src2p.value); // comiss src1reg,src2p
}
-
+
/* 64-bit form */
else if (inst->size == 8)
{
@@ -7335,7 +7335,7 @@ static x86code *op_fmul(drcbe_state *drcbe, x86code *dst, const drcuml_instructi
/* pick a target register for the general case */
dstreg = param_select_register(REG_XMM0, &dstp, &src2p);
-
+
/* 32-bit form */
if (inst->size == 4)
{
@@ -7346,7 +7346,7 @@ static x86code *op_fmul(drcbe_state *drcbe, x86code *dst, const drcuml_instructi
emit_mulss_r128_r128(&dst, dstreg, src2p.value); // mulss dstreg,src2p
emit_movss_p32_r128(drcbe, &dst, &dstp, dstreg); // movss dstp,dstreg
}
-
+
/* 64-bit form */
else if (inst->size == 8)
{
@@ -7379,7 +7379,7 @@ static x86code *op_fdiv(drcbe_state *drcbe, x86code *dst, const drcuml_instructi
/* pick a target register for the general case */
dstreg = param_select_register(REG_XMM0, &dstp, &src2p);
-
+
/* 32-bit form */
if (inst->size == 4)
{
@@ -7390,7 +7390,7 @@ static x86code *op_fdiv(drcbe_state *drcbe, x86code *dst, const drcuml_instructi
emit_divss_r128_r128(&dst, dstreg, src2p.value); // divss dstreg,src2p
emit_movss_p32_r128(drcbe, &dst, &dstp, dstreg); // movss dstp,dstreg
}
-
+
/* 64-bit form */
else if (inst->size == 8)
{
@@ -7423,7 +7423,7 @@ static x86code *op_fneg(drcbe_state *drcbe, x86code *dst, const drcuml_instructi
/* pick a target register for the general case */
dstreg = param_select_register(REG_XMM0, &dstp, &srcp);
-
+
/* 32-bit form */
if (inst->size == 4)
{
@@ -7434,7 +7434,7 @@ static x86code *op_fneg(drcbe_state *drcbe, x86code *dst, const drcuml_instructi
emit_subss_r128_r128(&dst, dstreg, srcp.value); // subss dstreg,srcp
emit_movss_p32_r128(drcbe, &dst, &dstp, dstreg); // movss dstp,dstreg
}
-
+
/* 64-bit form */
else if (inst->size == 8)
{
@@ -7467,7 +7467,7 @@ static x86code *op_fabs(drcbe_state *drcbe, x86code *dst, const drcuml_instructi
/* pick a target register for the general case */
dstreg = param_select_register(REG_XMM0, &dstp, &srcp);
-
+
/* 32-bit form */
if (inst->size == 4)
{
@@ -7475,7 +7475,7 @@ static x86code *op_fabs(drcbe_state *drcbe, x86code *dst, const drcuml_instructi
emit_andps_r128_m128(&dst, dstreg, MABS(drcbe, drcbe->absmask32)); // andps dstreg,[absmask32]
emit_movss_p32_r128(drcbe, &dst, &dstp, dstreg); // movss dstp,dstreg
}
-
+
/* 64-bit form */
else if (inst->size == 8)
{
@@ -7505,7 +7505,7 @@ static x86code *op_fsqrt(drcbe_state *drcbe, x86code *dst, const drcuml_instruct
/* pick a target register for the general case */
dstreg = param_select_register(REG_XMM0, &dstp, NULL);
-
+
/* 32-bit form */
if (inst->size == 4)
{
@@ -7515,7 +7515,7 @@ static x86code *op_fsqrt(drcbe_state *drcbe, x86code *dst, const drcuml_instruct
emit_sqrtss_r128_r128(&dst, dstreg, srcp.value); // sqrtss dstreg,srcp
emit_movss_p32_r128(drcbe, &dst, &dstp, dstreg); // movss dstp,dstreg
}
-
+
/* 64-bit form */
else if (inst->size == 8)
{
@@ -7547,7 +7547,7 @@ static x86code *op_frecip(drcbe_state *drcbe, x86code *dst, const drcuml_instruc
/* pick a target register for the general case */
dstreg = param_select_register(REG_XMM0, &dstp, NULL);
-
+
/* 32-bit form */
if (inst->size == 4)
{
@@ -7557,7 +7557,7 @@ static x86code *op_frecip(drcbe_state *drcbe, x86code *dst, const drcuml_instruc
emit_rcpss_r128_r128(&dst, dstreg, srcp.value); // rcpss dstreg,srcp
emit_movss_p32_r128(drcbe, &dst, &dstp, dstreg); // movss dstp,dstreg
}
-
+
/* 64-bit form */
else if (inst->size == 8)
{
@@ -7591,7 +7591,7 @@ static x86code *op_frsqrt(drcbe_state *drcbe, x86code *dst, const drcuml_instruc
/* pick a target register for the general case */
dstreg = param_select_register(REG_XMM0, &dstp, NULL);
-
+
/* 32-bit form */
if (inst->size == 4)
{
@@ -7601,7 +7601,7 @@ static x86code *op_frsqrt(drcbe_state *drcbe, x86code *dst, const drcuml_instruc
emit_rsqrtss_r128_r128(&dst, dstreg, srcp.value); // rsqrtss dstreg,srcp
emit_movss_p32_r128(drcbe, &dst, &dstp, dstreg); // movss dstp,dstreg
}
-
+
/* 64-bit form */
else if (inst->size == 8)
{
diff --git a/src/emu/cpu/drcbex86.c b/src/emu/cpu/drcbex86.c
index ebff66c8a40..31a5b4d6034 100644
--- a/src/emu/cpu/drcbex86.c
+++ b/src/emu/cpu/drcbex86.c
@@ -10,20 +10,20 @@
****************************************************************************
- Future improvements/changes:
+ Future improvements/changes:
- * Optimize to avoid unnecessary reloads
- - especially EDX for 64-bit operations
- - also FCMP/FLAGS has unnecessary PUSHF/POP EAX
-
- * Identify common pairs and optimize output
+ * Optimize to avoid unnecessary reloads
+ - especially EDX for 64-bit operations
+ - also FCMP/FLAGS has unnecessary PUSHF/POP EAX
+
+ * Identify common pairs and optimize output
****************************************************************************
---------------
ABI/conventions
---------------
-
+
Registers:
EAX - volatile, function return value
EBX - non-volatile
@@ -34,7 +34,7 @@
EBP - non-volatile
FP stack - volatile
-
+
---------------
Execution model
@@ -717,7 +717,7 @@ static void drcbex86_generate(drcbe_state *drcbe, drcuml_block *block, const drc
drcuml_disasm(inst, dasm);
x86log_add_comment(drcbe->log, dst, "%s", dasm);
}
-
+
/* extract a blockname */
if (blockname == NULL)
{
@@ -1048,7 +1048,7 @@ static void emit_mov_m32_p32(drcbe_state *drcbe, x86code **dst, DECLARE_MEMPARAM
/*-------------------------------------------------
- emit_mov_p32_r32 - move a register into a
+ emit_mov_p32_r32 - move a register into a
32-bit parameter
-------------------------------------------------*/
@@ -1259,7 +1259,7 @@ static void emit_cmp_r32_p32(drcbe_state *drcbe, x86code **dst, UINT8 reg, const
/*-------------------------------------------------
emit_cmp_r32_p32hi - cmp operation to a 32-bit
- register from the upper 32 bits of a 64-bit
+ register from the upper 32 bits of a 64-bit
parameter
-------------------------------------------------*/
@@ -1294,7 +1294,7 @@ static void emit_cmp_m32_p32(drcbe_state *drcbe, x86code **dst, DECLARE_MEMPARAM
/*-------------------------------------------------
emit_cmp_m32_p32hi - cmp operation to a 32-bit
- memory location from the upper half of a
+ memory location from the upper half of a
64-bit parameter
-------------------------------------------------*/
@@ -1860,7 +1860,7 @@ static void emit_mov_p64_r64(drcbe_state *drcbe, x86code **dst, const drcuml_par
/*-------------------------------------------------
- emit_push_p64 - push a 64-bit parameter onto
+ emit_push_p64 - push a 64-bit parameter onto
the stack
-------------------------------------------------*/
@@ -2779,7 +2779,7 @@ static void emit_rcl_r64_p64(drcbe_state *drcbe, x86code **dst, UINT8 reglo, UIN
int saveflags = ((inst->condflags & DRCUML_FLAG_Z) != 0);
emit_link skipall, skiploop;
x86code *loop;
-
+
emit_mov_r32_p32(drcbe, dst, REG_ECX, param); // mov ecx,param
if (!saveflags)
{
@@ -2821,7 +2821,7 @@ static void emit_rcr_r64_p64(drcbe_state *drcbe, x86code **dst, UINT8 reglo, UIN
int saveflags = (inst->condflags != 0);
emit_link skipall, skiploop;
x86code *loop;
-
+
emit_mov_r32_p32(drcbe, dst, REG_ECX, param); // mov ecx,param
if (!saveflags)
{
@@ -3566,14 +3566,14 @@ static x86code *op_load1u(drcbe_state *drcbe, x86code *dst, const drcuml_instruc
emit_mov_r32_p32(drcbe, &dst, indreg, &indp);
emit_movzx_r32_m8(&dst, dstreg, MISD(indreg, 1, basep.value)); // movzx dstreg,[basep + 1*indp]
}
-
+
/* store low 32 bits */
emit_mov_p32_r32(drcbe, &dst, &dstp, dstreg); // mov dstp,dstreg
-
+
/* 64-bit form stores upper 32 bits */
if (inst->size == 8)
{
- /* general case */
+ /* general case */
if (dstp.type == DRCUML_PTYPE_MEMORY)
emit_mov_m32_imm(&dst, MABS(dstp.value + 4), 0); // mov [dstp+4],0
else if (dstp.type == DRCUML_PTYPE_INT_REGISTER)
@@ -3665,11 +3665,11 @@ static x86code *op_load2u(drcbe_state *drcbe, x86code *dst, const drcuml_instruc
/* store low 32 bits */
emit_mov_p32_r32(drcbe, &dst, &dstp, dstreg); // mov dstp,dstreg
-
+
/* 64-bit form stores upper 32 bits */
if (inst->size == 8)
{
- /* general case */
+ /* general case */
if (dstp.type == DRCUML_PTYPE_MEMORY)
emit_mov_m32_imm(&dst, MABS(dstp.value + 4), 0); // mov [dstp+4],0
else if (dstp.type == DRCUML_PTYPE_INT_REGISTER)
@@ -3761,11 +3761,11 @@ static x86code *op_load4u(drcbe_state *drcbe, x86code *dst, const drcuml_instruc
/* store low 32 bits */
emit_mov_p32_r32(drcbe, &dst, &dstp, dstreg); // mov dstp,dstreg
-
+
/* 64-bit form stores upper 32 bits */
if (inst->size == 8)
{
- /* general case */
+ /* general case */
if (dstp.type == DRCUML_PTYPE_MEMORY)
emit_mov_m32_imm(&dst, MABS(dstp.value + 4), 0); // mov [dstp+4],0
else if (dstp.type == DRCUML_PTYPE_INT_REGISTER)
@@ -3872,7 +3872,7 @@ static x86code *op_store1(drcbe_state *drcbe, x86code *dst, const drcuml_instruc
srcreg = param_select_register(REG_EAX, &srcp, NULL);
if (srcreg & 4)
srcreg = REG_EAX;
-
+
/* degenerate case: constant index */
if (indp.type == DRCUML_PTYPE_IMMEDIATE)
{
@@ -4082,11 +4082,11 @@ static x86code *op_read1u(drcbe_state *drcbe, x86code *dst, const drcuml_instruc
/* store low 32 bits */
emit_mov_p32_r32(drcbe, &dst, &dstp, dstreg); // mov dstp,dstreg
-
+
/* 64-bit form stores upper 32 bits */
if (inst->size == 8)
{
- /* general case */
+ /* general case */
if (dstp.type == DRCUML_PTYPE_MEMORY)
emit_mov_m32_imm(&dst, MABS(dstp.value + 4), 0); // mov [dstp+4],0
else if (dstp.type == DRCUML_PTYPE_INT_REGISTER)
@@ -4166,11 +4166,11 @@ static x86code *op_read2u(drcbe_state *drcbe, x86code *dst, const drcuml_instruc
/* store low 32 bits */
emit_mov_p32_r32(drcbe, &dst, &dstp, dstreg); // mov dstp,dstreg
-
+
/* 64-bit form stores upper 32 bits */
if (inst->size == 8)
{
- /* general case */
+ /* general case */
if (dstp.type == DRCUML_PTYPE_MEMORY)
emit_mov_m32_imm(&dst, MABS(dstp.value + 4), 0); // mov [dstp+4],0
else if (dstp.type == DRCUML_PTYPE_INT_REGISTER)
@@ -4252,11 +4252,11 @@ static x86code *op_read2m(drcbe_state *drcbe, x86code *dst, const drcuml_instruc
/* store low 32 bits */
emit_mov_p32_r32(drcbe, &dst, &dstp, dstreg); // mov dstp,dstreg
-
+
/* 64-bit form stores upper 32 bits */
if (inst->size == 8)
{
- /* general case */
+ /* general case */
if (dstp.type == DRCUML_PTYPE_MEMORY)
emit_mov_m32_imm(&dst, MABS(dstp.value + 4), 0); // mov [dstp+4],0
else if (dstp.type == DRCUML_PTYPE_INT_REGISTER)
@@ -4288,11 +4288,11 @@ static x86code *op_read4u(drcbe_state *drcbe, x86code *dst, const drcuml_instruc
/* store low 32 bits */
emit_mov_p32_r32(drcbe, &dst, &dstp, REG_EAX); // mov dstp,eax
-
+
/* 64-bit form stores upper 32 bits */
if (inst->size == 8)
{
- /* general case */
+ /* general case */
if (dstp.type == DRCUML_PTYPE_MEMORY)
emit_mov_m32_imm(&dst, MABS(dstp.value + 4), 0); // mov [dstp+4],0
else if (dstp.type == DRCUML_PTYPE_INT_REGISTER)
@@ -4354,11 +4354,11 @@ static x86code *op_read4m(drcbe_state *drcbe, x86code *dst, const drcuml_instruc
/* store low 32 bits */
emit_mov_p32_r32(drcbe, &dst, &dstp, REG_EAX); // mov dstp,eax
-
+
/* 64-bit form stores upper 32 bits */
if (inst->size == 8)
{
- /* general case */
+ /* general case */
if (dstp.type == DRCUML_PTYPE_MEMORY)
emit_mov_m32_imm(&dst, MABS(dstp.value + 4), 0); // mov [dstp+4],0
else if (dstp.type == DRCUML_PTYPE_INT_REGISTER)
@@ -4636,7 +4636,7 @@ static x86code *op_flags(drcbe_state *drcbe, x86code *dst, const drcuml_instruct
emit_mov_r32_m32(&dst, dstreg, MISD(REG_EAX, 4, tablep.value)); // mov dstreg,[eax*4+table]
emit_mov_p32_r32(drcbe, &dst, &dstp, dstreg); // mov dstp,dstreg
}
-
+
/* general case */
else
{
@@ -4648,7 +4648,7 @@ static x86code *op_flags(drcbe_state *drcbe, x86code *dst, const drcuml_instruct
emit_mov_p32_r32(drcbe, &dst, &dstp, dstreg); // mov dstp,dstreg
}
}
-
+
/* 64-bit form */
else
{
@@ -4659,7 +4659,7 @@ static x86code *op_flags(drcbe_state *drcbe, x86code *dst, const drcuml_instruct
emit_mov_r32_m32(&dst, REG_EDX, MISD(REG_EAX, 8, tablep.value + 4)); // mov edx,[eax*4+table+4]
emit_mov_p64_r64(drcbe, &dst, &dstp, dstreg, REG_EDX); // mov dst,edx:dstreg
}
-
+
/* general case */
else
{
@@ -4717,7 +4717,7 @@ static x86code *op_mov(drcbe_state *drcbe, x86code *dst, const drcuml_instructio
dstp = inst->param[0];
srcp = inst->param[1];
}
-
+
/* degenerate case: dest and source are equal */
if (dstp.type == srcp.type && dstp.value == srcp.value)
return dst;
@@ -4739,7 +4739,7 @@ static x86code *op_mov(drcbe_state *drcbe, x86code *dst, const drcuml_instructio
/* immediate to memory */
else if (dstp.type == DRCUML_PTYPE_MEMORY && srcp.type == DRCUML_PTYPE_IMMEDIATE)
emit_mov_m32_imm(&dst, MABS(dstp.value), srcp.value); // mov [dstp],srcp
-
+
/* conditional memory to register */
else if (inst->condflags != 0 && dstp.type == DRCUML_PTYPE_INT_REGISTER && srcp.type == DRCUML_PTYPE_MEMORY)
{
@@ -4765,7 +4765,7 @@ static x86code *op_mov(drcbe_state *drcbe, x86code *dst, const drcuml_instructio
emit_mov_p32_r32(drcbe, &dst, &dstp, dstreg); // mov dstp,dstreg
}
}
-
+
/* 64-bit form */
else if (inst->size == 8)
{
@@ -4783,7 +4783,7 @@ static x86code *op_mov(drcbe_state *drcbe, x86code *dst, const drcuml_instructio
emit_mov_m32_imm(&dst, MABS(dstp.value), srcp.value); // mov [dstp],srcp
emit_mov_m32_imm(&dst, MABS(dstp.value + 4), srcp.value >> 32); // mov [dstp+4],srcp >> 32
}
-
+
/* general case */
else
{
@@ -4821,14 +4821,14 @@ static x86code *op_zext1(drcbe_state *drcbe, x86code *dst, const drcuml_instruct
/* pick a target register for the general case */
dstreg = param_select_register(REG_EAX, &dstp, NULL);
-
+
/* convert 8-bit source registers */
if (srcp.type == DRCUML_PTYPE_INT_REGISTER && (srcp.value & 4))
{
emit_mov_r32_r32(&dst, REG_EAX, srcp.value); // mov eax,srcp
srcp.value = REG_EAX;
}
-
+
/* 32-bit form */
if (inst->size == 4)
{
@@ -4880,7 +4880,7 @@ static x86code *op_zext2(drcbe_state *drcbe, x86code *dst, const drcuml_instruct
/* pick a target register for the general case */
dstreg = param_select_register(REG_EAX, &dstp, NULL);
-
+
/* 32-bit form */
if (inst->size == 4)
{
@@ -4932,7 +4932,7 @@ static x86code *op_zext4(drcbe_state *drcbe, x86code *dst, const drcuml_instruct
/* pick a target register for the general case */
dstreg = param_select_register(REG_EAX, &dstp, NULL);
-
+
/* 64-bit form */
if (inst->size == 8)
{
@@ -4970,14 +4970,14 @@ static x86code *op_sext1(drcbe_state *drcbe, x86code *dst, const drcuml_instruct
/* pick a target register for the general case */
dstreg = param_select_register(REG_EAX, &dstp, NULL);
-
+
/* convert 8-bit source registers */
if (srcp.type == DRCUML_PTYPE_INT_REGISTER && (srcp.value & 4))
{
emit_mov_r32_r32(&dst, REG_EAX, srcp.value); // mov eax,srcp
srcp.value = REG_EAX;
}
-
+
/* 32-bit form */
if (inst->size == 4)
{
@@ -5026,7 +5026,7 @@ static x86code *op_sext2(drcbe_state *drcbe, x86code *dst, const drcuml_instruct
/* pick a target register for the general case */
dstreg = param_select_register(REG_EAX, &dstp, NULL);
-
+
/* 32-bit form */
if (inst->size == 4)
{
@@ -5108,7 +5108,7 @@ static x86code *op_add(drcbe_state *drcbe, x86code *dst, const drcuml_instructio
/* pick a target register for the general case */
dstreg = param_select_register(REG_EAX, &dstp, &src2p);
-
+
/* 32-bit form */
if (inst->size == 4)
{
@@ -5132,7 +5132,7 @@ static x86code *op_add(drcbe_state *drcbe, x86code *dst, const drcuml_instructio
emit_mov_p32_r32(drcbe, &dst, &dstp, dstreg); // mov dstp,dstreg
}
}
-
+
/* 64-bit form */
else if (inst->size == 8)
{
@@ -5170,7 +5170,7 @@ static x86code *op_addc(drcbe_state *drcbe, x86code *dst, const drcuml_instructi
/* pick a target register for the general case */
dstreg = param_select_register(REG_EAX, &dstp, &src2p);
-
+
/* 32-bit form */
if (inst->size == 4)
{
@@ -5186,7 +5186,7 @@ static x86code *op_addc(drcbe_state *drcbe, x86code *dst, const drcuml_instructi
emit_mov_p32_r32(drcbe, &dst, &dstp, dstreg); // mov dstp,dstreg
}
}
-
+
/* 64-bit form */
else if (inst->size == 8)
{
@@ -5230,7 +5230,7 @@ static x86code *op_sub(drcbe_state *drcbe, x86code *dst, const drcuml_instructio
/* pick a target register for the general case */
dstreg = param_select_register(REG_EAX, &dstp, &src2p);
-
+
/* 32-bit form */
if (inst->size == 4)
{
@@ -5250,7 +5250,7 @@ static x86code *op_sub(drcbe_state *drcbe, x86code *dst, const drcuml_instructio
emit_mov_p32_r32(drcbe, &dst, &dstp, dstreg); // mov dstp,dstreg
}
}
-
+
/* 64-bit form */
else if (inst->size == 8)
{
@@ -5288,7 +5288,7 @@ static x86code *op_subc(drcbe_state *drcbe, x86code *dst, const drcuml_instructi
/* pick a target register for the general case */
dstreg = param_select_register(REG_EAX, &dstp, &src2p);
-
+
/* 32-bit form */
if (inst->size == 4)
{
@@ -5304,7 +5304,7 @@ static x86code *op_subc(drcbe_state *drcbe, x86code *dst, const drcuml_instructi
emit_mov_p32_r32(drcbe, &dst, &dstp, dstreg); // mov dstp,dstreg
}
}
-
+
/* 64-bit form */
else if (inst->size == 8)
{
@@ -5350,14 +5350,14 @@ static x86code *op_cmp(drcbe_state *drcbe, x86code *dst, const drcuml_instructio
/* pick a target register for the general case */
src1reg = param_select_register(REG_EAX, &src1p, NULL);
-
+
/* 32-bit form */
if (inst->size == 4)
{
/* memory versus anything */
if (src1p.type == DRCUML_PTYPE_MEMORY)
emit_cmp_m32_p32(drcbe, &dst, MABS(src1p.value), &src2p, inst); // cmp [dstp],src2p
-
+
/* general case */
else
{
@@ -5366,7 +5366,7 @@ static x86code *op_cmp(drcbe_state *drcbe, x86code *dst, const drcuml_instructio
emit_cmp_r32_p32(drcbe, &dst, src1reg, &src2p, inst); // cmp src1reg,src2p
}
}
-
+
/* 64-bit form */
else
{
@@ -5378,7 +5378,7 @@ static x86code *op_cmp(drcbe_state *drcbe, x86code *dst, const drcuml_instructio
emit_cmp_m32_p32(drcbe, &dst, MABS(src1p.value), &src2p, inst); // cmp [dstp],src2p
resolve_link(&dst, &skip); // skip:
}
-
+
/* general case */
else
{
@@ -5464,7 +5464,7 @@ static x86code *op_mulu(drcbe_state *drcbe, x86code *dst, const drcuml_instructi
if (compute_hi)
emit_mov_p32_r32(drcbe, &dst, &edstp, REG_EDX); // mov edstp,edx
}
-
+
/* 64-bit form */
else if (inst->size == 8)
{
@@ -5554,7 +5554,7 @@ static x86code *op_muls(drcbe_state *drcbe, x86code *dst, const drcuml_instructi
emit_imul_r32_r32_imm(&dst, REG_EAX, src1p.value, src2p.value); // imul eax,src1p,src2p
emit_mov_p32_r32(drcbe, &dst, &dstp, REG_EAX); // mov dstp,eax
}
-
+
/* 32-bit destination, general case */
else if (!compute_hi)
{
@@ -5565,7 +5565,7 @@ static x86code *op_muls(drcbe_state *drcbe, x86code *dst, const drcuml_instructi
emit_imul_r32_r32(&dst, REG_EAX, src2p.value); // imul eax,src2p
emit_mov_p32_r32(drcbe, &dst, &dstp, REG_EAX); // mov dstp,eax
}
-
+
/* 64-bit destination, general case */
else
{
@@ -5583,7 +5583,7 @@ static x86code *op_muls(drcbe_state *drcbe, x86code *dst, const drcuml_instructi
emit_mov_p32_r32(drcbe, &dst, &edstp, REG_EDX); // mov edstp,edx
}
}
-
+
/* 64-bit form */
else if (inst->size == 8)
{
@@ -5679,7 +5679,7 @@ static x86code *op_divu(drcbe_state *drcbe, x86code *dst, const drcuml_instructi
emit_mov_p32_r32(drcbe, &dst, &edstp, REG_EDX); // mov edstp,edx
resolve_link(&dst, &skip); // skip:
}
-
+
/* 64-bit form */
else if (inst->size == 8)
{
@@ -5775,7 +5775,7 @@ static x86code *op_divs(drcbe_state *drcbe, x86code *dst, const drcuml_instructi
emit_mov_p32_r32(drcbe, &dst, &edstp, REG_EDX); // mov edstp,edx
resolve_link(&dst, &skip); // skip:
}
-
+
/* 64-bit form */
else if (inst->size == 8)
{
@@ -5829,7 +5829,7 @@ static x86code *op_and(drcbe_state *drcbe, x86code *dst, const drcuml_instructio
/* pick a target register for the general case */
dstreg = param_select_register(REG_EAX, &dstp, &src2p);
-
+
/* 32-bit form */
if (inst->size == 4)
{
@@ -5845,7 +5845,7 @@ static x86code *op_and(drcbe_state *drcbe, x86code *dst, const drcuml_instructio
emit_mov_p32_r32(drcbe, &dst, &dstp, dstreg); // mov dstp,dstreg
}
}
-
+
/* 64-bit form */
else if (inst->size == 8)
{
@@ -5880,10 +5880,10 @@ static x86code *op_test(drcbe_state *drcbe, x86code *dst, const drcuml_instructi
/* normalize parameters */
param_normalize_2_commutative(drcbe, inst, &src1p, PTYPE_MRI, &src2p, PTYPE_MRI);
-
+
/* pick a target register for the general case */
src1reg = param_select_register(REG_EAX, &src1p, NULL);
-
+
/* 32-bit form */
if (inst->size == 4)
{
@@ -5898,7 +5898,7 @@ static x86code *op_test(drcbe_state *drcbe, x86code *dst, const drcuml_instructi
emit_test_r32_p32(drcbe, &dst, src1reg, &src2p, inst); // test src1reg,src2p
}
}
-
+
/* 64-bit form */
else if (inst->size == 8)
{
@@ -5941,7 +5941,7 @@ static x86code *op_or(drcbe_state *drcbe, x86code *dst, const drcuml_instruction
/* pick a target register for the general case */
dstreg = param_select_register(REG_EAX, &dstp, &src2p);
-
+
/* 32-bit form */
if (inst->size == 4)
{
@@ -5957,7 +5957,7 @@ static x86code *op_or(drcbe_state *drcbe, x86code *dst, const drcuml_instruction
emit_mov_p32_r32(drcbe, &dst, &dstp, dstreg); // mov dstp,dstreg
}
}
-
+
/* 64-bit form */
else if (inst->size == 8)
{
@@ -6001,7 +6001,7 @@ static x86code *op_xor(drcbe_state *drcbe, x86code *dst, const drcuml_instructio
/* pick a target register for the general case */
dstreg = param_select_register(REG_EAX, &dstp, &src2p);
-
+
/* 32-bit form */
if (inst->size == 4)
{
@@ -6017,7 +6017,7 @@ static x86code *op_xor(drcbe_state *drcbe, x86code *dst, const drcuml_instructio
emit_mov_p32_r32(drcbe, &dst, &dstp, dstreg); // mov dstp,dstreg
}
}
-
+
/* 64-bit form */
else if (inst->size == 8)
{
@@ -6061,7 +6061,7 @@ static x86code *op_shl(drcbe_state *drcbe, x86code *dst, const drcuml_instructio
/* pick a target register for the general case */
dstreg = param_select_register(REG_EAX, &dstp, &src2p);
-
+
/* 32-bit form */
if (inst->size == 4)
{
@@ -6077,7 +6077,7 @@ static x86code *op_shl(drcbe_state *drcbe, x86code *dst, const drcuml_instructio
emit_mov_p32_r32(drcbe, &dst, &dstp, dstreg); // mov dstp,dstreg
}
}
-
+
/* 64-bit form */
else if (inst->size == 8)
{
@@ -6114,7 +6114,7 @@ static x86code *op_shr(drcbe_state *drcbe, x86code *dst, const drcuml_instructio
/* pick a target register for the general case */
dstreg = param_select_register(REG_EAX, &dstp, &src2p);
-
+
/* 32-bit form */
if (inst->size == 4)
{
@@ -6130,7 +6130,7 @@ static x86code *op_shr(drcbe_state *drcbe, x86code *dst, const drcuml_instructio
emit_mov_p32_r32(drcbe, &dst, &dstp, dstreg); // mov dstp,dstreg
}
}
-
+
/* 64-bit form */
else if (inst->size == 8)
{
@@ -6172,7 +6172,7 @@ static x86code *op_sar(drcbe_state *drcbe, x86code *dst, const drcuml_instructio
/* pick a target register for the general case */
dstreg = param_select_register(REG_EAX, &dstp, &src2p);
-
+
/* 32-bit form */
if (inst->size == 4)
{
@@ -6188,7 +6188,7 @@ static x86code *op_sar(drcbe_state *drcbe, x86code *dst, const drcuml_instructio
emit_mov_p32_r32(drcbe, &dst, &dstp, dstreg); // mov dstp,dstreg
}
}
-
+
/* 64-bit form */
else if (inst->size == 8)
{
@@ -6225,7 +6225,7 @@ static x86code *op_rol(drcbe_state *drcbe, x86code *dst, const drcuml_instructio
/* pick a target register for the general case */
dstreg = param_select_register(REG_EAX, &dstp, &src2p);
-
+
/* 32-bit form */
if (inst->size == 4)
{
@@ -6241,7 +6241,7 @@ static x86code *op_rol(drcbe_state *drcbe, x86code *dst, const drcuml_instructio
emit_mov_p32_r32(drcbe, &dst, &dstp, dstreg); // mov dstp,dstreg
}
}
-
+
/* 64-bit form */
else if (inst->size == 8)
{
@@ -6275,10 +6275,10 @@ static x86code *op_ror(drcbe_state *drcbe, x86code *dst, const drcuml_instructio
return convert_to_mov_imm(drcbe, dst, inst, &dstp, (UINT64)src1p.value >> src2p.value);
if (src2p.type == DRCUML_PTYPE_IMMEDIATE && src2p.value == 0 && inst->condflags == 0)
return convert_to_mov_src1(drcbe, dst, inst, &dstp, &src1p);
-
+
/* pick a target register for the general case */
dstreg = param_select_register(REG_EAX, &dstp, &src2p);
-
+
/* 32-bit form */
if (inst->size == 4)
{
@@ -6294,7 +6294,7 @@ static x86code *op_ror(drcbe_state *drcbe, x86code *dst, const drcuml_instructio
emit_mov_p32_r32(drcbe, &dst, &dstp, dstreg); // mov dstp,dstreg
}
}
-
+
/* 64-bit form */
else if (inst->size == 8)
{
@@ -6331,7 +6331,7 @@ static x86code *op_rolc(drcbe_state *drcbe, x86code *dst, const drcuml_instructi
/* pick a target register for the general case */
dstreg = param_select_register(REG_EAX, &dstp, &src2p);
-
+
/* 32-bit form */
if (inst->size == 4)
{
@@ -6347,7 +6347,7 @@ static x86code *op_rolc(drcbe_state *drcbe, x86code *dst, const drcuml_instructi
emit_mov_p32_r32(drcbe, &dst, &dstp, dstreg); // mov dstp,dstreg
}
}
-
+
/* 64-bit form */
else if (inst->size == 8)
{
@@ -6381,10 +6381,10 @@ static x86code *op_rorc(drcbe_state *drcbe, x86code *dst, const drcuml_instructi
return convert_to_mov_imm(drcbe, dst, inst, &dstp, (UINT64)src1p.value >> src2p.value);
if (src2p.type == DRCUML_PTYPE_IMMEDIATE && src2p.value == 0 && inst->condflags == 0)
return convert_to_mov_src1(drcbe, dst, inst, &dstp, &src1p);
-
+
/* pick a target register for the general case */
dstreg = param_select_register(REG_EAX, &dstp, &src2p);
-
+
/* 32-bit form */
if (inst->size == 4)
{
@@ -6400,7 +6400,7 @@ static x86code *op_rorc(drcbe_state *drcbe, x86code *dst, const drcuml_instructi
emit_mov_p32_r32(drcbe, &dst, &dstp, dstreg); // mov dstp,dstreg
}
}
-
+
/* 64-bit form */
else if (inst->size == 8)
{
@@ -6432,7 +6432,7 @@ static x86code *op_fload(drcbe_state *drcbe, x86code *dst, const drcuml_instruct
/* normalize parameters */
param_normalize_3(drcbe, inst, &dstp, PTYPE_MF, &basep, PTYPE_M, &indp, PTYPE_MRI);
-
+
/* immediate index */
if (indp.type == DRCUML_PTYPE_IMMEDIATE)
{
@@ -6441,7 +6441,7 @@ static x86code *op_fload(drcbe_state *drcbe, x86code *dst, const drcuml_instruct
else if (inst->size == 8)
emit_fld_m64(&dst, MABS(basep.value + 8*indp.value)); // fld [basep + 8*indp]
}
-
+
/* other index */
else
{
@@ -6474,10 +6474,10 @@ static x86code *op_fstore(drcbe_state *drcbe, x86code *dst, const drcuml_instruc
/* normalize parameters */
param_normalize_3(drcbe, inst, &basep, PTYPE_M, &indp, PTYPE_MRI, &srcp, PTYPE_MF);
-
+
/* general case */
emit_fld_p(&dst, inst->size, &srcp);
-
+
/* immediate index */
if (indp.type == DRCUML_PTYPE_IMMEDIATE)
{
@@ -6486,7 +6486,7 @@ static x86code *op_fstore(drcbe_state *drcbe, x86code *dst, const drcuml_instruc
else if (inst->size == 8)
emit_fstp_m64(&dst, MABS(basep.value + 8*indp.value)); // fstp [basep + 8*indp]
}
-
+
/* other index */
else
{
@@ -6584,7 +6584,7 @@ static x86code *op_fmov(drcbe_state *drcbe, x86code *dst, const drcuml_instructi
/* always start with a jmp */
if (inst->condflags != DRCUML_COND_ALWAYS)
emit_jcc_short_link(&dst, X86_NOT_CONDITION(inst->condflags), &skip); // jcc skip
-
+
/* general case */
emit_fld_p(&dst, inst->size, &srcp); // fld srcp
emit_fstp_p(&dst, inst->size, &dstp); // fstp dstp
@@ -6666,7 +6666,7 @@ static x86code *op_ftoi4r(drcbe_state *drcbe, x86code *dst, const drcuml_instruc
/* normalize parameters */
param_normalize_2(drcbe, inst, &dstp, PTYPE_MR, &srcp, PTYPE_MF);
-
+
/* save and set the control word */
emit_fstcw_m16(&dst, MABS(&drcbe->fmodesave)); // fstcw [fmodesave]
emit_fldcw_m16(&dst, MABS(&fp_control[DRCUML_FMOD_ROUND])); // fldcw fpcontrol[DRCUML_FMOD_ROUND]
@@ -6701,7 +6701,7 @@ static x86code *op_ftoi4f(drcbe_state *drcbe, x86code *dst, const drcuml_instruc
/* normalize parameters */
param_normalize_2(drcbe, inst, &dstp, PTYPE_MR, &srcp, PTYPE_MF);
-
+
/* save and set the control word */
emit_fstcw_m16(&dst, MABS(&drcbe->fmodesave)); // fstcw [fmodesave]
emit_fldcw_m16(&dst, MABS(&fp_control[DRCUML_FMOD_FLOOR])); // fldcw fpcontrol[DRCUML_FMOD_FLOOR]
@@ -6736,7 +6736,7 @@ static x86code *op_ftoi4c(drcbe_state *drcbe, x86code *dst, const drcuml_instruc
/* normalize parameters */
param_normalize_2(drcbe, inst, &dstp, PTYPE_MR, &srcp, PTYPE_MF);
-
+
/* save and set the control word */
emit_fstcw_m16(&dst, MABS(&drcbe->fmodesave)); // fstcw [fmodesave]
emit_fldcw_m16(&dst, MABS(&fp_control[DRCUML_FMOD_CEIL])); // fldcw fpcontrol[DRCUML_FMOD_CEIL]
diff --git a/src/emu/cpu/drccache.c b/src/emu/cpu/drccache.c
index 83b00da4907..15fdd25c693 100644
--- a/src/emu/cpu/drccache.c
+++ b/src/emu/cpu/drccache.c
@@ -140,7 +140,7 @@ void drccache_free(drccache *cache)
***************************************************************************/
/*-------------------------------------------------
- drccache_contains_pointer - return true if a
+ drccache_contains_pointer - return true if a
pointer is within the cache
-------------------------------------------------*/
@@ -151,7 +151,7 @@ int drccache_contains_pointer(drccache *cache, const void *ptr)
/*-------------------------------------------------
- drccache_contains_near_pointer - return true
+ drccache_contains_near_pointer - return true
if a pointer is within the cache
-------------------------------------------------*/
@@ -248,7 +248,7 @@ void *drccache_memory_alloc(drccache *cache, size_t bytes)
/*-------------------------------------------------
- drccache_memory_alloc_near - allocate
+ drccache_memory_alloc_near - allocate
permanent memory from the near part of the
cache
-------------------------------------------------*/
@@ -294,13 +294,13 @@ void drccache_memory_free(drccache *cache, void *memory, size_t bytes)
assert(bytes < MAX_PERMANENT_ALLOC);
assert(((drccodeptr)memory >= cache->near && (drccodeptr)memory < cache->base) || ((drccodeptr)memory >= cache->end && (drccodeptr)memory < cache->near + cache->size));
-
+
/* determine which free list to add to */
if ((drccodeptr)memory < cache->base)
linkptr = &cache->nearfree[(bytes + CACHE_ALIGNMENT - 1) / CACHE_ALIGNMENT];
else
linkptr = &cache->free[(bytes + CACHE_ALIGNMENT - 1) / CACHE_ALIGNMENT];
-
+
/* link is into the free list for our size */
link->next = *linkptr;
*linkptr = link;
diff --git a/src/emu/cpu/drcuml.c b/src/emu/cpu/drcuml.c
index ff89fc87aa8..df62b75d897 100644
--- a/src/emu/cpu/drcuml.c
+++ b/src/emu/cpu/drcuml.c
@@ -10,31 +10,31 @@
****************************************************************************
- Future improvements/changes:
-
- * Write a back-end validator:
- - checks all combinations of memory/register/immediate on all params
- - checks behavior of all opcodes
-
- * Extend registers to 16? Depends on if PPC can use them
-
- * New instructions?
- - EXTRACT dst,src,shift,mask
- dst = (src >> shift) & mask
-
- - INSERT dst,src,shift,mask
- dst = (dst & ~mask) | ((src << shift) & mask)
-
- - VALID opcode_desc,handle,param
- checksum/compare code referenced by opcode_desc; if not
- matching, generate exception with handle,param
-
- - RECALL handle
- change code at caller to call handle in the future
-
- * Add interface for getting hints from the backend:
- - number of direct-mapped integer registers
- - number of direct-mapped floating point registers
+ Future improvements/changes:
+
+ * Write a back-end validator:
+ - checks all combinations of memory/register/immediate on all params
+ - checks behavior of all opcodes
+
+ * Extend registers to 16? Depends on if PPC can use them
+
+ * New instructions?
+ - EXTRACT dst,src,shift,mask
+ dst = (src >> shift) & mask
+
+ - INSERT dst,src,shift,mask
+ dst = (dst & ~mask) | ((src << shift) & mask)
+
+ - VALID opcode_desc,handle,param
+ checksum/compare code referenced by opcode_desc; if not
+ matching, generate exception with handle,param
+
+ - RECALL handle
+ change code at caller to call handle in the future
+
+ * Add interface for getting hints from the backend:
+ - number of direct-mapped integer registers
+ - number of direct-mapped floating point registers
***************************************************************************/
@@ -350,7 +350,7 @@ void drcuml_reset(drcuml_state *drcuml)
/* if we error here, we are screwed */
if (setjmp(errorbuf) != 0)
fatalerror("Out of cache space in drcuml_reset");
-
+
/* reset all handle code pointers */
for (handle = drcuml->handlelist; handle != NULL; handle = handle->next)
handle->code = NULL;
@@ -688,7 +688,7 @@ drcuml_codehandle *drcuml_handle_alloc(drcuml_state *drcuml, const char *name)
if (string == NULL)
return NULL;
strcpy(string, name);
-
+
/* allocate a new handle info */
handle = drccache_memory_alloc_near(drcuml->cache, sizeof(*handle));
if (handle == NULL)
@@ -697,13 +697,13 @@ drcuml_codehandle *drcuml_handle_alloc(drcuml_state *drcuml, const char *name)
return NULL;
}
memset(handle, 0, sizeof(*handle));
-
+
/* fill in the rest of the info and add to the list of handles */
handle->drcuml = drcuml;
handle->string = string;
handle->next = drcuml->handlelist;
drcuml->handlelist = handle;
-
+
return handle;
}
@@ -722,7 +722,7 @@ void drcuml_handle_set_codeptr(drcuml_codehandle *handle, drccodeptr code)
/*-------------------------------------------------
- drcuml_handle_codeptr - get the pointer from
+ drcuml_handle_codeptr - get the pointer from
a handle
-------------------------------------------------*/
diff --git a/src/emu/cpu/ds5002fp/ds5002fp.c b/src/emu/cpu/ds5002fp/ds5002fp.c
index 06c216b6f16..9d0a5ac30fa 100644
--- a/src/emu/cpu/ds5002fp/ds5002fp.c
+++ b/src/emu/cpu/ds5002fp/ds5002fp.c
@@ -1,43 +1,43 @@
/*****************************************************************************
* DS5002FP emulator by Manuel Abadia
- *
+ *
* The emulator is just a modified version of the MCS-51 Family Emulator by Steve Ellenoff
- *
+ *
* What has been added?
- * - Extra SFRs
- * - Bytewide Bus Support
- * - Memory Partition and Memory Range
- * - Bootstrap Configuration
- * - Power Fail Interrupt
- * - Timed Access
- * - Stop Mode
- * - Idle Mode
- *
+ * - Extra SFRs
+ * - Bytewide Bus Support
+ * - Memory Partition and Memory Range
+ * - Bootstrap Configuration
+ * - Power Fail Interrupt
+ * - Timed Access
+ * - Stop Mode
+ * - Idle Mode
+ *
* What is not implemented?
- * - Peripherals and Reprogrammable Peripheral Controller
- * - CRC-16
- * - Watchdog timer
- *
+ * - Peripherals and Reprogrammable Peripheral Controller
+ * - CRC-16
+ * - Watchdog timer
+ *
* The main features of the DS5002FP are:
- * - 100% code-compatible with 8051
- * - Directly addresses 64kB program/64kB data memory
- * - Nonvolatile memory control circuitry
- * - 10-year data retention in the absence of power
- * - In-system reprogramming via serial port
- * - Dedicated memory bus, preserving four 8-bit ports for general purpose I/O
- * - Power-fail reset
- * - Early warning power-fail interrupt
- * - Watchdog timer
- * - Accesses up to 128kB on the bytewide bus
- * - Decodes memory for 32kB x 8 or 128kB x 8 SRAMs
- * - Four additional decoded peripheral-chip enables
- * - CRC hardware for checking memory validity
- * - Optionally emulates an 8042-style slave interface
- * - Memory encryption using an 80-bit encryption key
- * - Automatic random generation of encryption keys
- * - Self-destruct input for tamper protection
- * - Optional top-coating prevents microprobe
- *
+ * - 100% code-compatible with 8051
+ * - Directly addresses 64kB program/64kB data memory
+ * - Nonvolatile memory control circuitry
+ * - 10-year data retention in the absence of power
+ * - In-system reprogramming via serial port
+ * - Dedicated memory bus, preserving four 8-bit ports for general purpose I/O
+ * - Power-fail reset
+ * - Early warning power-fail interrupt
+ * - Watchdog timer
+ * - Accesses up to 128kB on the bytewide bus
+ * - Decodes memory for 32kB x 8 or 128kB x 8 SRAMs
+ * - Four additional decoded peripheral-chip enables
+ * - CRC hardware for checking memory validity
+ * - Optionally emulates an 8042-style slave interface
+ * - Memory encryption using an 80-bit encryption key
+ * - Automatic random generation of encryption keys
+ * - Self-destruct input for tamper protection
+ * - Optional top-coating prevents microprobe
+ *
*****************************************************************************/
/*****************************************************************************
@@ -411,7 +411,7 @@ static READ32_HANDLER((*hold_ebram_iaddr_callback));
#define GET_DMA ((R_RPCTL & 0x04)>>2)
#define GET_RPCON ((R_RPCTL & 0x02)>>1)
#define GET_RG0 ((R_RPCTL & 0x01)>>0)
-
+
/*Add and Subtract Flag settings*/
#define DO_ADD_FLAGS(a,d,c) do_add_flags(a,d,c);
#define DO_SUB_FLAGS(a,d,c) do_sub_flags(a,d,c);
@@ -505,9 +505,9 @@ static const ds5002fp_config default_config =
/* Memory Range (RG1 and RG0 @ MCON and RPCTL registers) */
static const UINT16 ds5002fp_ranges[4] = {
- 0x1fff,
- 0x3fff,
- 0x7fff,
+ 0x1fff,
+ 0x3fff,
+ 0x7fff,
0xffff
};
@@ -537,7 +537,7 @@ static const UINT32 ds5002fp_partitions[16] = {
void ds5002fp_init(int index, int clock, const void *_config, int (*irqcallback)(int))
{
const ds5002fp_config *config = _config ? _config : &default_config;
-
+
ds5002fp.config = config;
ds5002fp_set_irq_callback(irqcallback);
@@ -595,7 +595,7 @@ void ds5002fp_reset(void)
{
int (*save_irqcallback)(int);
const ds5002fp_config *save_config;
-
+
save_irqcallback = ds5002fp.irq_callback;
save_config = ds5002fp.config;
memset(&ds5002fp, 0, sizeof(DS5002FP));
@@ -657,7 +657,7 @@ void ds5002fp_reset(void)
/* Flag as NO IRQ in Progress */
CLEAR_CURRENT_IRQ
-
+
// set internal CPU state
ds5002fp.last_power_int = CLEAR_LINE;
ds5002fp.previous_ta = 0;
@@ -678,30 +678,30 @@ int ds5002fp_execute(int cycles)
if (R_PCON & 0x02) {
return cycles;
}
-
+
ds5002fp_icount = cycles;
-
+
//In idle mode, update timers and serial port (not sure if we need to do more things here)
if (R_PCON & 0x01) {
do {
//Update Timer (if any timers are running)
if((GET_TR0 && GET_ET0) || (GET_TR1 && GET_ET1))
update_timer(12);
-
+
//Update Serial (if serial port sending data)
if(uart.sending)
update_serial(12);
-
+
ds5002fp_icount -= 12;
} while( ds5002fp_icount > 0 );
-
+
return cycles - ds5002fp_icount;
- }
+ }
- do {
+ do {
//Read next opcode
UINT8 op = cpu_readop(PC);
-
+
//Store previous PC
PPC = PC;
@@ -1391,7 +1391,7 @@ int ds5002fp_execute(int cycles)
default:
illegal();
}
-
+
//If the chip entered in stop mode, end execution
if (R_PCON & 0x02) {
return cycles;
@@ -1399,7 +1399,7 @@ int ds5002fp_execute(int cycles)
//Store # of used cycles for this opcode (for timer & serial check at top of code)
ds5002fp.prev_used_cycles = ds5002fp_cycles[op];
-
+
// decrement the timed access window
if (ds5002fp.ta_window > 0) {
ds5002fp.ta_window -= ds5002fp_cycles[op];
@@ -1410,7 +1410,7 @@ int ds5002fp_execute(int cycles)
//Check for pending interrupts & handle - remove cycles used
ds5002fp_icount-=check_interrupts();
-
+
//If the chip entered in idle mode, end the loop
if (R_PCON & 0x01) {
return cycles - ds5002fp_icount;
@@ -1460,7 +1460,7 @@ unsigned ds5002fp_get_reg(int regnum)
case DS5002FP_DPH: return R_DPH;
case DS5002FP_DPL: return R_DPL;
case DS5002FP_IE: return R_IE;
-
+
case DS5002FP_PCON: return R_PCON;
case DS5002FP_MCON: return R_MCON;
case DS5002FP_RPCTL:return R_RPCTL;
@@ -1582,8 +1582,8 @@ void ds5002fp_set_irq_line(int irqline, int state)
}
break;
//Note: we won't call check interrupts, we'll let the main loop catch it
-
- //Power Fail Interrupt
+
+ //Power Fail Interrupt
case DS5002FP_PFI_LINE:
//Line Asserted?
if (state != CLEAR_LINE) {
@@ -1629,7 +1629,7 @@ INLINE UINT8 check_interrupts(void)
//Check which interrupt(s) requests have occurred..
//NOTE: The order of checking is based on the internal/default priority levels when levels are the same
-
+
// Power Fail Interrupt
if(GET_PFW) {
if (ds5002fp.last_power_int == CLEAR_LINE) {
@@ -1780,12 +1780,12 @@ static WRITE8_HANDLER(sfr_write)
case DPH: R_DPH = data; break;
case PCON:
reg_mask1 = 0xb9;
-
+
is_timed_access = (ds5002fp.ta_window > 0) && (R_TA == 0x55);
if (is_timed_access) {
reg_mask1 = 0xff;
}
- R_PCON = (R_PCON & (~reg_mask1)) | (data & reg_mask1);
+ R_PCON = (R_PCON & (~reg_mask1)) | (data & reg_mask1);
break;
case TCON: R_TCON = data; break;
case TMOD: R_TMOD = data; break;
@@ -1822,29 +1822,29 @@ static WRITE8_HANDLER(sfr_write)
OUT(3,data);
break;
- case IP:
+ case IP:
reg_mask1 = 0x7f;
-
+
is_timed_access = (ds5002fp.ta_window > 0) && (R_TA == 0x55);
if (is_timed_access) {
reg_mask1 = 0xff;
}
- R_IP = (R_IP & (~reg_mask1)) | (data & reg_mask1);
+ R_IP = (R_IP & (~reg_mask1)) | (data & reg_mask1);
break;
-
+
case CRCR: reg_mask2 = 0x0f;
R_CRC = (R_CRC & (~reg_mask2)) | (data & reg_mask2);
- LOG(("ds5002fp #%d: write to CRC register at 0x%04x, data=%x\n", cpu_getactivecpu(), PC, data));
+ LOG(("ds5002fp #%d: write to CRC register at 0x%04x, data=%x\n", cpu_getactivecpu(), PC, data));
break;
case CRCL: R_CRCL = data;
- LOG(("ds5002fp #%d: write to CRCL register at 0x%04x, data=%x\n", cpu_getactivecpu(), PC, data));
+ LOG(("ds5002fp #%d: write to CRCL register at 0x%04x, data=%x\n", cpu_getactivecpu(), PC, data));
break;
- case CRCH: R_CRCH = data;
+ case CRCH: R_CRCH = data;
LOG(("ds5002fp #%d: write to CRCH register at 0x%04x, data=%x\n", cpu_getactivecpu(), PC, data));
break;
case MCON: reg_mask1 = 0x0f;
reg_mask2 = 0xf7;
-
+
is_timed_access = (ds5002fp.ta_window > 0) && (R_TA == 0x55);
if (is_timed_access) {
reg_mask1 = 0xff;
@@ -1853,9 +1853,9 @@ static WRITE8_HANDLER(sfr_write)
R_MCON = (R_MCON & (~reg_mask2)) | (data & reg_mask2);
LOG(("ds5002fp #%d: write to MCON register at 0x%04x, data=%x\n", cpu_getactivecpu(), PC, data));
break;
- case TA: ds5002fp.previous_ta = R_TA;
+ case TA: ds5002fp.previous_ta = R_TA;
R_TA = data;
-
+
// init the time window after having wrote 0xaa
if ((data == 0xaa) && (ds5002fp.ta_window == 0)) {
ds5002fp.ta_window = 4*12 + 2*12;
@@ -1863,7 +1863,7 @@ static WRITE8_HANDLER(sfr_write)
}
//LOG(("ds5002fp #%d: write to TA register at 0x%04x, data=%x\n", cpu_getactivecpu(), PC, data));
break;
- case RNR: R_RNR = data;
+ case RNR: R_RNR = data;
LOG(("ds5002fp #%d: write to RNR register at 0x%04x, data=%x\n", cpu_getactivecpu(), PC, data));
break;
@@ -1871,19 +1871,19 @@ static WRITE8_HANDLER(sfr_write)
R_PSW = data;
SET_PARITY;
break;
-
+
case RPCTL: reg_mask1 = 0xef;
reg_mask2 = 0xfe;
-
+
is_timed_access = (ds5002fp.ta_window > 0) && (R_TA == 0x55);
if (is_timed_access) {
reg_mask1 = 0xff;
}
data = (R_RPCTL & (~reg_mask1)) | (data & reg_mask1);
- R_RPCTL = (R_RPCTL & (~reg_mask2)) | (data & reg_mask2);
- LOG(("ds5002fp #%d: write to RPCTL register at 0x%04x, data=%x\n", cpu_getactivecpu(), PC, data));
+ R_RPCTL = (R_RPCTL & (~reg_mask2)) | (data & reg_mask2);
+ LOG(("ds5002fp #%d: write to RPCTL register at 0x%04x, data=%x\n", cpu_getactivecpu(), PC, data));
break;
- case RPS: R_RPS = data;
+ case RPS: R_RPS = data;
LOG(("ds5002fp #%d: write to RPS register at 0x%04x, data=%x\n", cpu_getactivecpu(), PC, data));
break;
@@ -1939,7 +1939,7 @@ static READ8_HANDLER(sfr_read)
else
return IN(3); //Read from actual port
case IP: return R_IP;
-
+
case CRCR: LOG(("ds5002fp #%d: read CRC register at 0x%04x\n", cpu_getactivecpu(), PC));
return R_CRC;
case CRCL: LOG(("ds5002fp #%d: read CRCL register at 0x%04x\n", cpu_getactivecpu(), PC));
@@ -1952,14 +1952,14 @@ static READ8_HANDLER(sfr_read)
return R_TA;
case RNR: LOG(("ds5002fp #%d: read RNR register at 0x%04x\n", cpu_getactivecpu(), PC));
return R_RNR;
-
+
case PSW: return R_PSW;
-
+
case RPCTL: LOG(("ds5002fp #%d: read RPCTL register at 0x%04x\n", cpu_getactivecpu(), PC));
return R_RPCTL;
case RPS: LOG(("ds5002fp #%d: read RPS register at 0x%04x\n", cpu_getactivecpu(), PC));
return R_RPS;
-
+
case ACC: return R_ACC;
case B: return R_B;
@@ -2015,18 +2015,18 @@ static WRITE8_HANDLER(internal_ram_iwrite)
}
/* Generate an expanded bus/bytewide bus ram address for read/writing */
-/*
- The DS5002FP has 2 16 bits data address buses (the byte-wide bus and the expanded bus). The exact memory position accessed depends on the
- partition mode, the memory range and the expanded bus select. The partition mode and the expanded bus select can be changed at any time.
-
- In order to simplify memory mapping to the data address bus, the following address map is assumed for partitioned mode:
-
- 0x00000-0x0ffff -> data memory on the expanded bus
- 0x10000-0x1ffff -> data memory on the byte-wide bus
-
- For non-partitioned mode the following memory map is assumed:
-
- 0x0000-0xffff -> data memory (the bus used to access it does not matter)
+/*
+ The DS5002FP has 2 16 bits data address buses (the byte-wide bus and the expanded bus). The exact memory position accessed depends on the
+ partition mode, the memory range and the expanded bus select. The partition mode and the expanded bus select can be changed at any time.
+
+ In order to simplify memory mapping to the data address bus, the following address map is assumed for partitioned mode:
+
+ 0x00000-0x0ffff -> data memory on the expanded bus
+ 0x10000-0x1ffff -> data memory on the byte-wide bus
+
+ For non-partitioned mode the following memory map is assumed:
+
+ 0x0000-0xffff -> data memory (the bus used to access it does not matter)
*/
static READ32_HANDLER(external_ram_iaddr)
{
diff --git a/src/emu/cpu/ds5002fp/ds5002fp.h b/src/emu/cpu/ds5002fp/ds5002fp.h
index 7e2487ee43f..8559432efca 100644
--- a/src/emu/cpu/ds5002fp/ds5002fp.h
+++ b/src/emu/cpu/ds5002fp/ds5002fp.h
@@ -1,8 +1,8 @@
/*****************************************************************************
* DS5002FP emulator
- *
+ *
* The emulator is just a modified version of the MCS-51 Family Emulator by Steve Ellenoff
- *
+ *
*****************************************************************************/
/*****************************************************************************
@@ -44,7 +44,7 @@
enum {
DS5002FP_PC=1, DS5002FP_SP, DS5002FP_PSW, DS5002FP_ACC, DS5002FP_B, DS5002FP_DPH, DS5002FP_DPL, DS5002FP_IE,
- DS5002FP_PCON, DS5002FP_MCON, DS5002FP_RPCTL, DS5002FP_CRC,
+ DS5002FP_PCON, DS5002FP_MCON, DS5002FP_RPCTL, DS5002FP_CRC,
DS5002FP_R0, DS5002FP_R1, DS5002FP_R2, DS5002FP_R3, DS5002FP_R4, DS5002FP_R5, DS5002FP_R6, DS5002FP_R7, DS5002FP_RB
};
diff --git a/src/emu/cpu/ds5002fp/ds5002fpdasm.c b/src/emu/cpu/ds5002fp/ds5002fpdasm.c
index ca4684bc817..bd4a8c5a104 100644
--- a/src/emu/cpu/ds5002fp/ds5002fpdasm.c
+++ b/src/emu/cpu/ds5002fp/ds5002fpdasm.c
@@ -1,8 +1,8 @@
/*****************************************************************************
* DS5002FP emulator
- *
+ *
* The emulator is just a modified version of the MCS-51 Family Emulator by Steve Ellenoff
- *
+ *
*****************************************************************************/
/*****************************************************************************
diff --git a/src/emu/cpu/mips/mips3drc.c b/src/emu/cpu/mips/mips3drc.c
index 11666848934..023d47a9230 100644
--- a/src/emu/cpu/mips/mips3drc.c
+++ b/src/emu/cpu/mips/mips3drc.c
@@ -10,24 +10,24 @@
****************************************************************************
- Future improvements/changes:
-
- * Add DRC option to flush PC before calling memory handlers
-
- * Map MIPS registers to i5-i7 (or more)
- - should rely on backend hints to know how many to assign
- - add instrumentation to figure out which ones are most used
- - on entry, load registers; on exit, flush them
- - also flush before calling debugger
-
- * Constant tracking? (hasn't bought us much in the past)
-
- * Customized mapped/unmapped memory handlers
- - create 3 sets of handlers: cached, uncached, general
- - default to general
- - in general case, if cached use RECALL to point to cached code
- - (same for uncached)
- - in cached/uncached case, fall back to general case
+ Future improvements/changes:
+
+ * Add DRC option to flush PC before calling memory handlers
+
+ * Map MIPS registers to i5-i7 (or more)
+ - should rely on backend hints to know how many to assign
+ - add instrumentation to figure out which ones are most used
+ - on entry, load registers; on exit, flush them
+ - also flush before calling debugger
+
+ * Constant tracking? (hasn't bought us much in the past)
+
+ * Customized mapped/unmapped memory handlers
+ - create 3 sets of handlers: cached, uncached, general
+ - default to general
+ - in general case, if cached use RECALL to point to cached code
+ - (same for uncached)
+ - in cached/uncached case, fall back to general case
***************************************************************************/
@@ -189,7 +189,7 @@ struct _mips3_regs
/* internal stuff */
UINT8 cache_dirty; /* true if we need to flush the cache */
-
+
/* subroutines */
drcuml_codehandle * entry; /* entry point */
drcuml_codehandle * nocode; /* nocode exception handler */
@@ -209,7 +209,7 @@ struct _mips3_regs
drcuml_codehandle * write64mask; /* write double masked */
drcuml_codehandle * exception[EXCEPTION_COUNT]; /* array of exception handlers */
drcuml_codehandle * exception_norecover[EXCEPTION_COUNT]; /* array of no-recover exception handlers */
-
+
/* fast RAM */
UINT32 fastram_select;
fast_ram_info fastram[MIPS3_MAX_FASTRAM];
@@ -618,7 +618,7 @@ static const UINT32 c_ule_table_source[32] =
***************************************************************************/
/*-------------------------------------------------
- epc - compute the exception PC from a
+ epc - compute the exception PC from a
descriptor
-------------------------------------------------*/
@@ -661,15 +661,15 @@ static void mips3_init(mips3_flavor flavor, int bigendian, int index, int clock,
UINT32 flags = 0;
size_t extrasize;
void *extramem;
-
+
/* determine how much memory beyond the core size we need */
extrasize = mips3com_init(NULL, flavor, bigendian, index, clock, config, irqcallback, NULL);
-
+
/* allocate enough space for the cache and the core */
mips3.cache = drccache_alloc(CACHE_SIZE + sizeof(*mips3.core) + extrasize);
if (mips3.cache == NULL)
fatalerror("Unable to allocate cache of size %d", (UINT32)(CACHE_SIZE + sizeof(*mips3.core) + extrasize));
-
+
/* allocate the core and the extra memory */
mips3.core = drccache_memory_alloc_near(mips3.cache, sizeof(*mips3.core));
extramem = drccache_memory_alloc(mips3.cache, extrasize);
@@ -690,7 +690,7 @@ static void mips3_init(mips3_flavor flavor, int bigendian, int index, int clock,
memcpy(mips3.cstate->c_ult_table, c_ult_table_source, sizeof(c_ult_table_source));
memcpy(mips3.cstate->c_ole_table, c_ole_table_source, sizeof(c_ole_table_source));
memcpy(mips3.cstate->c_ule_table, c_ule_table_source, sizeof(c_ule_table_source));
-
+
/* initialize the UML generator */
if (FORCE_C_BACKEND)
flags |= DRCUML_OPTION_USE_C;
@@ -701,12 +701,12 @@ static void mips3_init(mips3_flavor flavor, int bigendian, int index, int clock,
mips3.drcuml = drcuml_alloc(mips3.cache, flags, 2, 32, 2);
if (mips3.drcuml == NULL)
fatalerror("Error initializing the UML");
-
+
/* initialize the front-end helper */
if (SINGLE_INSTRUCTION_MODE)
feconfig.max_sequence = 1;
mips3.drcfe = drcfe_init(&feconfig, mips3.core);
-
+
/* mark the cache dirty so it is updated on next execute */
mips3.cache_dirty = TRUE;
}
@@ -733,7 +733,7 @@ static int mips3_execute(int cycles)
{
drcuml_state *drcuml = mips3.drcuml;
int execute_result;
-
+
/* reset the cache if dirty */
if (mips3.cache_dirty)
code_flush_cache(drcuml);
@@ -745,11 +745,11 @@ static int mips3_execute(int cycles)
{
/* run as much as we can */
execute_result = drcuml_execute(drcuml, mips3.entry);
-
+
/* if we need to recompile, do it */
if (execute_result == EXECUTE_MISSING_CODE)
code_compile_block(drcuml, mips3.cstate->mode, mips3.core->pc);
-
+
} while (execute_result != EXECUTE_OUT_OF_CYCLES);
/* return the number of cycles executed */
@@ -837,7 +837,7 @@ static void code_flush_cache(drcuml_state *drcuml)
static_generate_entry_point(drcuml);
static_generate_nocode_handler(drcuml);
static_generate_out_of_cycles(drcuml);
-
+
/* append exception handlers for various types */
static_generate_exception(drcuml, EXCEPTION_INTERRUPT, TRUE, "exception_interrupt");
static_generate_exception(drcuml, EXCEPTION_INTERRUPT, FALSE, "exception_interrupt_norecover");
@@ -850,7 +850,7 @@ static void code_flush_cache(drcuml_state *drcuml)
static_generate_exception(drcuml, EXCEPTION_BADCOP, TRUE, "exception_badcop");
static_generate_exception(drcuml, EXCEPTION_OVERFLOW, TRUE, "exception_overflow");
static_generate_exception(drcuml, EXCEPTION_TRAP, TRUE, "exception_trap");
-
+
/* add subroutines for memory accesses */
static_generate_memory_accessor(drcuml, 1, FALSE, FALSE, "read8", &mips3.read8);
static_generate_memory_accessor(drcuml, 1, TRUE, FALSE, "write8", &mips3.write8);
@@ -880,7 +880,7 @@ static void code_compile_block(drcuml_state *drcuml, UINT8 mode, offs_t pc)
int override = FALSE;
drcuml_block *block;
jmp_buf errorbuf;
-
+
/* get a description of this sequence */
desclist = drcfe_describe_code(mips3.drcfe, pc);
if (LOG_UML)
@@ -889,7 +889,7 @@ static void code_compile_block(drcuml_state *drcuml, UINT8 mode, offs_t pc)
/* if we get an error back, flush the cache and try again */
if (setjmp(errorbuf) != 0)
code_flush_cache(drcuml);
-
+
/* start the block */
block = drcuml_block_begin(drcuml, 4096, &errorbuf);
@@ -920,7 +920,7 @@ static void code_compile_block(drcuml_state *drcuml, UINT8 mode, offs_t pc)
override = TRUE;
UML_HASH(block, mode, seqhead->pc); // hash mode,pc
}
-
+
/* otherwise, redispatch to that fixed PC and skip the rest of the processing */
else
{
@@ -929,7 +929,7 @@ static void code_compile_block(drcuml_state *drcuml, UINT8 mode, offs_t pc)
// hashjmp <mode>,seqhead->pc,nocode
continue;
}
-
+
/* validate this code block if we're not pointing into ROM */
if (memory_get_write_ptr(cpu_getactivecpu(), ADDRESS_SPACE_PROGRAM, seqhead->physpc) != NULL)
generate_checksum_block(block, &compiler, seqhead, seqlast);
@@ -941,7 +941,7 @@ static void code_compile_block(drcuml_state *drcuml, UINT8 mode, offs_t pc)
/* iterate over instructions in the sequence and compile them */
for (curdesc = seqhead; curdesc != seqlast->next; curdesc = curdesc->next)
generate_sequence_instruction(block, &compiler, curdesc);
-
+
/* if we need to return to the start, do it */
if (seqlast->flags & OPFLAG_RETURN_TO_START)
nextpc = pc;
@@ -949,10 +949,10 @@ static void code_compile_block(drcuml_state *drcuml, UINT8 mode, offs_t pc)
/* otherwise we just go to the next instruction */
else
nextpc = seqlast->pc + (seqlast->skipslots + 1) * 4;
-
+
/* count off cycles and go there */
generate_update_cycles(block, &compiler, nextpc, NULL, TRUE); // <subtract cycles>
-
+
/* if the last instruction can change modes, use a variable mode; otherwise, assume the same mode */
if (seqlast->flags & OPFLAG_CAN_CHANGE_MODES)
UML_HASHJMP(block, MEM(&mips3.cstate->mode), IMM(nextpc), mips3.nocode);// hashjmp <mode>,nextpc,nocode
@@ -995,7 +995,7 @@ static void cfunc_get_cycles(void *param)
/*-------------------------------------------------
- cfunc_printf_probe - print the current CPU
+ cfunc_printf_probe - print the current CPU
state and return
-------------------------------------------------*/
@@ -1055,7 +1055,7 @@ static void cfunc_printf_probe(void *param)
***************************************************************************/
/*-------------------------------------------------
- static_generate_entry_point - generate a
+ static_generate_entry_point - generate a
static entry point
-------------------------------------------------*/
@@ -1064,14 +1064,14 @@ static void static_generate_entry_point(drcuml_state *drcuml)
drcuml_codelabel skip = 1;
drcuml_block *block;
jmp_buf errorbuf;
-
+
/* if we get an error back, we're screwed */
if (setjmp(errorbuf) != 0)
fatalerror("Unrecoverable error in static_generate_entry_point");
/* begin generating */
block = drcuml_block_begin(drcuml, 20, &errorbuf);
-
+
/* forward references */
alloc_handle(drcuml, &mips3.exception_norecover[EXCEPTION_INTERRUPT], "interrupt_norecover");
alloc_handle(drcuml, &mips3.nocode, "nocode");
@@ -1099,13 +1099,13 @@ static void static_generate_entry_point(drcuml_state *drcuml)
/* generate a hash jump via the current mode and PC */
UML_HASHJMP(block, MEM(&mips3.cstate->mode), MEM(&mips3.core->pc), mips3.nocode);// hashjmp <mode>,<pc>,nocode
-
+
drcuml_block_end(block);
}
/*-------------------------------------------------
- static_generate_nocode_handler - generate an
+ static_generate_nocode_handler - generate an
exception handler for "out of code"
-------------------------------------------------*/
@@ -1113,21 +1113,21 @@ static void static_generate_nocode_handler(drcuml_state *drcuml)
{
drcuml_block *block;
jmp_buf errorbuf;
-
+
/* if we get an error back, we're screwed */
if (setjmp(errorbuf) != 0)
fatalerror("Unrecoverable error in static_generate_nocode_handler");
/* begin generating */
block = drcuml_block_begin(drcuml, 10, &errorbuf);
-
+
/* generate a hash jump via the current mode and PC */
alloc_handle(drcuml, &mips3.nocode, "nocode");
UML_HANDLE(block, mips3.nocode); // handle nocode
UML_GETEXP(block, IREG(0)); // getexp i0
UML_MOV(block, MEM(&mips3.core->pc), IREG(0)); // mov [pc],i0
UML_EXIT(block, IMM(EXECUTE_MISSING_CODE)); // exit EXECUTE_MISSING_CODE
-
+
drcuml_block_end(block);
}
@@ -1141,21 +1141,21 @@ static void static_generate_out_of_cycles(drcuml_state *drcuml)
{
drcuml_block *block;
jmp_buf errorbuf;
-
+
/* if we get an error back, we're screwed */
if (setjmp(errorbuf) != 0)
fatalerror("Unrecoverable error in static_generate_out_of_cycles");
/* begin generating */
block = drcuml_block_begin(drcuml, 10, &errorbuf);
-
+
/* generate a hash jump via the current mode and PC */
alloc_handle(drcuml, &mips3.out_of_cycles, "out_of_cycles");
UML_HANDLE(block, mips3.out_of_cycles); // handle out_of_cycles
UML_GETEXP(block, IREG(0)); // getexp i0
UML_MOV(block, MEM(&mips3.core->pc), IREG(0)); // mov <pc>,i0
UML_EXIT(block, IMM(EXECUTE_OUT_OF_CYCLES)); // exit EXECUTE_OUT_OF_CYCLES
-
+
drcuml_block_end(block);
}
@@ -1171,14 +1171,14 @@ static void static_generate_exception(drcuml_state *drcuml, UINT8 exception, int
drcuml_codelabel next = 1;
drcuml_block *block;
jmp_buf errorbuf;
-
+
/* if we get an error back, we're screwed */
if (setjmp(errorbuf) != 0)
fatalerror("Unrecoverable error in static_generate_exception");
/* begin generating */
block = drcuml_block_begin(drcuml, 1024, &errorbuf);
-
+
/* add a global entry for this */
if (recover)
{
@@ -1201,7 +1201,7 @@ static void static_generate_exception(drcuml_state *drcuml, UINT8 exception, int
UML_AND(block, IREG(0), IREG(0), IMM(0xffffe000)); // and i0,i0,0xffffe000
UML_AND(block, IREG(1), CPR032(COP0_EntryHi), IMM(0x000000ff)); // and i1,[EntryHi],0x000000ff
UML_OR(block, CPR032(COP0_EntryHi), IREG(0), IREG(1)); // or [EntryHi],i0,i1
-
+
/* set the lower bits of Context to the fault page */
UML_SHR(block, IREG(0), IREG(0), IMM(9)); // shr i0,i0,9
UML_AND(block, IREG(1), CPR032(COP0_Context), IMM(0xff800000)); // and i1,[Context],0xff800000
@@ -1223,25 +1223,25 @@ static void static_generate_exception(drcuml_state *drcuml, UINT8 exception, int
UML_LABEL(block, next); // <next>:
UML_MOV(block, CPR032(COP0_EPC), IREG(0)); // mov [EPC],i0
UML_OR(block, CPR032(COP0_Cause), IREG(2), IMM(exception << 2)); // or [Cause],i2,exception << 2
-
+
/* set EXL in the SR */
UML_OR(block, CPR032(COP0_Status), CPR032(COP0_Status), IMM(SR_EXL)); // or [Status],[Status],SR_EXL
-
+
/* optionally print exceptions */
if (PRINTF_EXCEPTIONS && exception != EXCEPTION_INTERRUPT && exception != EXCEPTION_SYSCALL)
UML_CALLC(block, cfunc_printf_exception, NULL); // callc cfunc_printf_exception,NULL
-
+
/* choose our target PC */
UML_MOV(block, IREG(0), IMM(0xbfc00200 + offset)); // mov i0,0xbfc00200 + offset
UML_TEST(block, CPR032(COP0_Status), IMM(SR_BEV)); // test [Status],SR_BEV
UML_MOVc(block, IF_Z, IREG(0), IMM(0x80000000 + offset)); // mov i0,0x80000000 + offset,z
-
+
/* adjust cycles */
UML_SUBf(block, MEM(&mips3.core->icount), MEM(&mips3.core->icount), IREG(1), FLAGS_S); // sub icount,icount,cycles,S
UML_EXHc(block, IF_S, mips3.out_of_cycles, IREG(0)); // exh out_of_cycles,i0
-
+
UML_HASHJMP(block, MEM(&mips3.cstate->mode), IREG(0), mips3.nocode); // hashjmp <mode>,i0,nocode
-
+
drcuml_block_end(block);
}
@@ -1260,7 +1260,7 @@ static void static_generate_memory_accessor(drcuml_state *drcuml, int size, int
jmp_buf errorbuf;
int label = 0;
int ramnum;
-
+
/* if we get an error back, we're screwed */
if (setjmp(errorbuf) != 0)
fatalerror("Unrecoverable error in static_generate_exception");
@@ -1321,7 +1321,7 @@ static void static_generate_memory_accessor(drcuml_state *drcuml, int size, int
{
UML_SHR(block, IREG(0), IREG(0), IMM(3)); // shr i0,i0,3
UML_DLOAD8(block, IREG(0), fastbase, IREG(0)); // dload8 i0,fastbase,i0
- UML_DROR(block, IREG(0), IREG(0), IMM(32 * (mips3.core->bigendian ? BYTE_XOR_BE(0) : BYTE_XOR_LE(0))));
+ UML_DROR(block, IREG(0), IREG(0), IMM(32 * (mips3.core->bigendian ? BYTE_XOR_BE(0) : BYTE_XOR_LE(0))));
// dror i0,i0,32*bytexor
}
UML_RET(block); // ret
@@ -1357,15 +1357,15 @@ static void static_generate_memory_accessor(drcuml_state *drcuml, int size, int
else if (size == 8)
{
UML_SHR(block, IREG(0), IREG(0), IMM(3)); // shr i0,i0,3
- UML_DROR(block, IREG(1), IREG(1), IMM(32 * (mips3.core->bigendian ? BYTE_XOR_BE(0) : BYTE_XOR_LE(0))));
+ UML_DROR(block, IREG(1), IREG(1), IMM(32 * (mips3.core->bigendian ? BYTE_XOR_BE(0) : BYTE_XOR_LE(0))));
// dror i1,i1,32*bytexor
if (ismasked)
{
- UML_DROR(block, IREG(2), IREG(2), IMM(32 * (mips3.core->bigendian ? BYTE_XOR_BE(0) : BYTE_XOR_LE(0))));
+ UML_DROR(block, IREG(2), IREG(2), IMM(32 * (mips3.core->bigendian ? BYTE_XOR_BE(0) : BYTE_XOR_LE(0))));
// dror i2,i2,32*bytexor
UML_DLOAD8(block, IREG(3), fastbase, IREG(0)); // dload8 i3,fastbase,i0
UML_DAND(block, IREG(1), IREG(1), IREG(2)); // dand i1,i1,i2
- UML_DXOR(block, IREG(2), IREG(2), IMM(U64(0xffffffffffffffff)));
+ UML_DXOR(block, IREG(2), IREG(2), IMM(U64(0xffffffffffffffff)));
// dxor i2,i2,0xfffffffffffffffff
UML_DAND(block, IREG(3), IREG(3), IREG(2)); // dand i3,i3,i2
UML_DOR(block, IREG(1), IREG(1), IREG(3)); // dor i1,i1,i3
@@ -1386,14 +1386,14 @@ static void static_generate_memory_accessor(drcuml_state *drcuml, int size, int
else
UML_READ1U(block, IREG(0), PROGRAM, IREG(0)); // read1u i0,i0
break;
-
+
case 2:
if (iswrite)
UML_WRITE2(block, PROGRAM, IREG(0), IREG(1)); // write2 i0,i1
else
UML_READ2U(block, IREG(0), PROGRAM, IREG(0)); // read2u i0,i0
break;
-
+
case 4:
if (iswrite)
{
@@ -1410,7 +1410,7 @@ static void static_generate_memory_accessor(drcuml_state *drcuml, int size, int
UML_READ4M(block, IREG(0), PROGRAM, IREG(0), IREG(2)); // read4m i0,PROGRAM,i0,i2
}
break;
-
+
case 8:
if (iswrite)
{
@@ -1429,7 +1429,7 @@ static void static_generate_memory_accessor(drcuml_state *drcuml, int size, int
break;
}
UML_RET(block); // ret
-
+
drcuml_block_end(block);
}
@@ -1515,7 +1515,7 @@ static void generate_checksum_block(drcuml_block *block, compiler_state *compile
const opcode_desc *curdesc;
if (LOG_UML)
UML_COMMENT(block, "[Validation for %08X]", seqhead->pc); // comment
-
+
/* loose verify or single instruction: just compare and fail */
if (!(mips3.drcoptions & MIPS3DRC_STRICT_VERIFY) || seqhead->next == NULL)
{
@@ -1523,7 +1523,7 @@ static void generate_checksum_block(drcuml_block *block, compiler_state *compile
UML_CMP(block, IREG(0), IMM(*seqhead->opptr.l)); // cmp i0,*opptr
UML_EXHc(block, IF_NE, mips3.nocode, IMM(epc(seqhead))); // exne nocode,seqhead->pc
}
-
+
/* full verification; sum up everything */
else
{
@@ -1570,7 +1570,7 @@ static void generate_sequence_instruction(drcuml_block *block, compiler_state *c
compiler->cycles += mips3.hotspot[hotnum].cycles;
break;
}
-
+
/* update the icount map variable */
UML_MAPVAR(block, MAPVAR_CYCLES, compiler->cycles); // mapvar CYCLES,compiler->cycles
@@ -1588,7 +1588,7 @@ static void generate_sequence_instruction(drcuml_block *block, compiler_state *c
/* validate our TLB entry at this PC; if we fail, we need to recompile */
if ((desc->flags & OPFLAG_VALIDATE_TLB) && (desc->pc < 0x80000000 || desc->pc >= 0xc0000000))
{
- UML_CMP(block, MEM(&mips3.core->tlb_table[desc->pc >> 12]),
+ UML_CMP(block, MEM(&mips3.core->tlb_table[desc->pc >> 12]),
IMM(mips3.core->tlb_table[desc->pc >> 12])); // cmp [tlbentry],*tlbentry
UML_EXHc(block, IF_NE, mips3.tlb_mismatch, IMM(0)); // exh tlb_mismatch,0,NE
}
@@ -1640,10 +1640,10 @@ static void generate_delay_slot_and_branch(drcuml_block *block, compiler_state *
// <subtract cycles>
UML_HASHJMP(block, IMM(mips3.cstate->mode), R32(RSREG), mips3.nocode); // hashjmp <mode>,<rsreg>,nocode
}
-
+
/* update the label */
compiler->labelnum = compiler_temp.labelnum;
-
+
/* reset the mapvar to the current cycles */
UML_MAPVAR(block, MAPVAR_CYCLES, compiler->cycles); // mapvar CYCLES,compiler->cycles
}
@@ -1692,7 +1692,7 @@ static int generate_opcode(drcuml_block *block, compiler_state *compiler, const
generate_delay_slot_and_branch(block, compiler, desc, 0); // <next instruction + hashjmp>
UML_LABEL(block, skip); // skip:
return TRUE;
-
+
case 0x05: /* BNE - MIPS I */
case 0x15: /* BNEL - MIPS II */
UML_DCMP(block, R64(RSREG), R64(RTREG)); // dcmp <rsreg>,<rtreg>
@@ -1700,7 +1700,7 @@ static int generate_opcode(drcuml_block *block, compiler_state *compiler, const
generate_delay_slot_and_branch(block, compiler, desc, 0); // <next instruction + hashjmp>
UML_LABEL(block, skip); // skip:
return TRUE;
-
+
case 0x06: /* BLEZ - MIPS I */
case 0x16: /* BLEZL - MIPS II */
if (RSREG != 0)
@@ -1713,7 +1713,7 @@ static int generate_opcode(drcuml_block *block, compiler_state *compiler, const
else
generate_delay_slot_and_branch(block, compiler, desc, 0); // <next instruction + hashjmp>
return TRUE;
-
+
case 0x07: /* BGTZ - MIPS I */
case 0x17: /* BGTZL - MIPS II */
UML_DCMP(block, R64(RSREG), IMM(0)); // dcmp <rsreg>,0
@@ -1721,7 +1721,7 @@ static int generate_opcode(drcuml_block *block, compiler_state *compiler, const
generate_delay_slot_and_branch(block, compiler, desc, 0); // <next instruction + hashjmp>
UML_LABEL(block, skip); // skip:
return TRUE;
-
+
/* ----- immediate arithmetic ----- */
@@ -1809,7 +1809,7 @@ static int generate_opcode(drcuml_block *block, compiler_state *compiler, const
if (!in_delay_slot)
generate_update_cycles(block, compiler, desc->pc + 4, 0, TRUE);
return TRUE;
-
+
case 0x21: /* LH - MIPS I */
UML_ADD(block, IREG(0), R32(RSREG), IMM(SIMMVAL)); // add i0,<rsreg>,SIMMVAL
UML_CALLH(block, mips3.read16); // callh read16
@@ -1818,7 +1818,7 @@ static int generate_opcode(drcuml_block *block, compiler_state *compiler, const
if (!in_delay_slot)
generate_update_cycles(block, compiler, desc->pc + 4, 0, TRUE);
return TRUE;
-
+
case 0x23: /* LW - MIPS I */
UML_ADD(block, IREG(0), R32(RSREG), IMM(SIMMVAL)); // add i0,<rsreg>,SIMMVAL
UML_CALLH(block, mips3.read32); // callh read32
@@ -1827,7 +1827,7 @@ static int generate_opcode(drcuml_block *block, compiler_state *compiler, const
if (!in_delay_slot)
generate_update_cycles(block, compiler, desc->pc + 4, 0, TRUE);
return TRUE;
-
+
case 0x24: /* LBU - MIPS I */
UML_ADD(block, IREG(0), R32(RSREG), IMM(SIMMVAL)); // add i0,<rsreg>,SIMMVAL
UML_CALLH(block, mips3.read8); // callh read8
@@ -1836,7 +1836,7 @@ static int generate_opcode(drcuml_block *block, compiler_state *compiler, const
if (!in_delay_slot)
generate_update_cycles(block, compiler, desc->pc + 4, 0, TRUE);
return TRUE;
-
+
case 0x25: /* LHU - MIPS I */
UML_ADD(block, IREG(0), R32(RSREG), IMM(SIMMVAL)); // add i0,<rsreg>,SIMMVAL
UML_CALLH(block, mips3.read16); // callh read16
@@ -1845,7 +1845,7 @@ static int generate_opcode(drcuml_block *block, compiler_state *compiler, const
if (!in_delay_slot)
generate_update_cycles(block, compiler, desc->pc + 4, 0, TRUE);
return TRUE;
-
+
case 0x27: /* LWU - MIPS III */
UML_ADD(block, IREG(0), R32(RSREG), IMM(SIMMVAL)); // add i0,<rsreg>,SIMMVAL
UML_CALLH(block, mips3.read32); // callh read32
@@ -1854,7 +1854,7 @@ static int generate_opcode(drcuml_block *block, compiler_state *compiler, const
if (!in_delay_slot)
generate_update_cycles(block, compiler, desc->pc + 4, 0, TRUE);
return TRUE;
-
+
case 0x37: /* LD - MIPS III */
UML_ADD(block, IREG(0), R32(RSREG), IMM(SIMMVAL)); // add i0,<rsreg>,SIMMVAL
UML_CALLH(block, mips3.read64); // callh read64
@@ -1941,7 +1941,7 @@ static int generate_opcode(drcuml_block *block, compiler_state *compiler, const
if (!in_delay_slot)
generate_update_cycles(block, compiler, desc->pc + 4, 0, TRUE);
return TRUE;
-
+
case 0x31: /* LWC1 - MIPS I */
UML_ADD(block, IREG(0), R32(RSREG), IMM(SIMMVAL)); // add i0,<rsreg>,SIMMVAL
UML_CALLH(block, mips3.read32); // callh read32
@@ -1984,7 +1984,7 @@ static int generate_opcode(drcuml_block *block, compiler_state *compiler, const
if (!in_delay_slot)
generate_update_cycles(block, compiler, desc->pc + 4, 0, TRUE);
return TRUE;
-
+
case 0x29: /* SH - MIPS I */
UML_ADD(block, IREG(0), R32(RSREG), IMM(SIMMVAL)); // add i0,<rsreg>,SIMMVAL
UML_MOV(block, IREG(1), R32(RTREG)); // mov i1,<rtreg>
@@ -1992,7 +1992,7 @@ static int generate_opcode(drcuml_block *block, compiler_state *compiler, const
if (!in_delay_slot)
generate_update_cycles(block, compiler, desc->pc + 4, 0, TRUE);
return TRUE;
-
+
case 0x2b: /* SW - MIPS I */
UML_ADD(block, IREG(0), R32(RSREG), IMM(SIMMVAL)); // add i0,<rsreg>,SIMMVAL
UML_MOV(block, IREG(1), R32(RTREG)); // mov i1,<rtreg>
@@ -2000,7 +2000,7 @@ static int generate_opcode(drcuml_block *block, compiler_state *compiler, const
if (!in_delay_slot)
generate_update_cycles(block, compiler, desc->pc + 4, 0, TRUE);
return TRUE;
-
+
case 0x3f: /* SD - MIPS III */
UML_ADD(block, IREG(0), R32(RSREG), IMM(SIMMVAL)); // add i0,<rsreg>,SIMMVAL
UML_DMOV(block, IREG(1), R64(RTREG)); // dmov i1,<rtreg>
@@ -2008,7 +2008,7 @@ static int generate_opcode(drcuml_block *block, compiler_state *compiler, const
if (!in_delay_slot)
generate_update_cycles(block, compiler, desc->pc + 4, 0, TRUE);
return TRUE;
-
+
case 0x2a: /* SWL - MIPS I */
UML_ADD(block, IREG(0), R32(RSREG), IMM(SIMMVAL)); // add i0,<rsreg>,SIMMVAL
UML_SHL(block, IREG(4), IREG(0), IMM(3)); // shl i4,i0,3
@@ -2060,7 +2060,7 @@ static int generate_opcode(drcuml_block *block, compiler_state *compiler, const
if (!in_delay_slot)
generate_update_cycles(block, compiler, desc->pc + 4, 0, TRUE);
return TRUE;
-
+
case 0x39: /* SWC1 - MIPS I */
UML_ADD(block, IREG(0), R32(RSREG), IMM(SIMMVAL)); // add i0,<rsreg>,SIMMVAL
UML_MOV(block, IREG(1), FPR32(RTREG)); // mov i1,<cpr1_rt>
@@ -2068,7 +2068,7 @@ static int generate_opcode(drcuml_block *block, compiler_state *compiler, const
if (!in_delay_slot)
generate_update_cycles(block, compiler, desc->pc + 4, 0, TRUE);
return TRUE;
-
+
case 0x3d: /* SDC1 - MIPS III */
UML_ADD(block, IREG(0), R32(RSREG), IMM(SIMMVAL)); // add i0,<rsreg>,SIMMVAL
UML_DMOV(block, IREG(1), FPR64(RTREG)); // dmov i1,<cpr1_rt>
@@ -2151,7 +2151,7 @@ static int generate_special(drcuml_block *block, compiler_state *compiler, const
UML_DSEXT4(block, R64(RDREG), IREG(0)); // dsext4 <rdreg>,i0
}
return TRUE;
-
+
case 0x02: /* SRL - MIPS I */
if (RDREG != 0)
{
@@ -2159,7 +2159,7 @@ static int generate_special(drcuml_block *block, compiler_state *compiler, const
UML_DSEXT4(block, R64(RDREG), IREG(0)); // dsext4 <rdreg>,i0
}
return TRUE;
-
+
case 0x03: /* SRA - MIPS I */
if (RDREG != 0)
{
@@ -2167,7 +2167,7 @@ static int generate_special(drcuml_block *block, compiler_state *compiler, const
UML_DSEXT4(block, R64(RDREG), IREG(0)); // dsext4 <rdreg>,i0
}
return TRUE;
-
+
case 0x04: /* SLLV - MIPS I */
if (RDREG != 0)
{
@@ -2196,32 +2196,32 @@ static int generate_special(drcuml_block *block, compiler_state *compiler, const
if (RDREG != 0)
UML_DSHL(block, R64(RDREG), R64(RTREG), IMM(SHIFT)); // dshl <rdreg>,<rtreg>,<shift>
return TRUE;
-
+
case 0x3a: /* DSRL - MIPS III */
if (RDREG != 0)
UML_DSHR(block, R64(RDREG), R64(RTREG), IMM(SHIFT)); // dshr <rdreg>,<rtreg>,<shift>
return TRUE;
-
+
case 0x3b: /* DSRA - MIPS III */
if (RDREG != 0)
UML_DSAR(block, R64(RDREG), R64(RTREG), IMM(SHIFT)); // dsar <rdreg>,<rtreg>,<shift>
return TRUE;
-
+
case 0x3c: /* DSLL32 - MIPS III */
if (RDREG != 0)
UML_DSHL(block, R64(RDREG), R64(RTREG), IMM(SHIFT + 32)); // dshl <rdreg>,<rtreg>,<shift>+32
return TRUE;
-
+
case 0x3e: /* DSRL32 - MIPS III */
if (RDREG != 0)
UML_DSHR(block, R64(RDREG), R64(RTREG), IMM(SHIFT + 32)); // dshr <rdreg>,<rtreg>,<shift>+32
return TRUE;
-
+
case 0x3f: /* DSRA32 - MIPS III */
if (RDREG != 0)
UML_DSAR(block, R64(RDREG), R64(RTREG), IMM(SHIFT + 32)); // dsar <rdreg>,<rtreg>,<shift>+32
return TRUE;
-
+
case 0x14: /* DSLLV - MIPS III */
if (RDREG != 0)
UML_DSHL(block, R64(RDREG), R64(RTREG), R64(RSREG)); // dshl <rdreg>,<rtreg>,<rsreg>
@@ -2367,7 +2367,7 @@ static int generate_special(drcuml_block *block, compiler_state *compiler, const
if (RDREG != 0)
UML_DAND(block, R64(RDREG), R64(RSREG), R64(RTREG)); // dand <rdreg>,<rsreg>,<rtreg>
return TRUE;
-
+
case 0x25: /* OR - MIPS I */
if (RDREG != 0)
UML_DOR(block, R64(RDREG), R64(RSREG), R64(RTREG)); // dor <rdreg>,<rsreg>,<rtreg>
@@ -2396,7 +2396,7 @@ static int generate_special(drcuml_block *block, compiler_state *compiler, const
UML_DFLAGS(block, R64(RDREG), (UINT64)~0, mips3.cstate->slt_table); // dflags <rdreg>,~0,slt_table
}
return TRUE;
-
+
case 0x2b: /* SLTU - MIPS I */
if (RDREG != 0)
{
@@ -2412,27 +2412,27 @@ static int generate_special(drcuml_block *block, compiler_state *compiler, const
UML_DCMP(block, R64(RSREG), R64(RTREG)); // dcmp <rsreg>,<rtreg>
UML_EXHc(block, IF_GE, mips3.exception[EXCEPTION_TRAP], IMM(0)); // exh trap,0,GE
return TRUE;
-
+
case 0x31: /* TGEU - MIPS II */
UML_DCMP(block, R64(RSREG), R64(RTREG)); // dcmp <rsreg>,<rtreg>
UML_EXHc(block, IF_AE, mips3.exception[EXCEPTION_TRAP], IMM(0)); // exh trap,0,AE
return TRUE;
-
+
case 0x32: /* TLT - MIPS II */
UML_DCMP(block, R64(RSREG), R64(RTREG)); // dcmp <rsreg>,<rtreg>
UML_EXHc(block, IF_L, mips3.exception[EXCEPTION_TRAP], IMM(0)); // exh trap,0,LT
return TRUE;
-
+
case 0x33: /* TLTU - MIPS II */
UML_DCMP(block, R64(RSREG), R64(RTREG)); // dcmp <rsreg>,<rtreg>
UML_EXHc(block, IF_B, mips3.exception[EXCEPTION_TRAP], IMM(0)); // exh trap,0,B
return TRUE;
-
+
case 0x34: /* TEQ - MIPS II */
UML_DCMP(block, R64(RSREG), R64(RTREG)); // dcmp <rsreg>,<rtreg>
UML_EXHc(block, IF_E, mips3.exception[EXCEPTION_TRAP], IMM(0)); // exh trap,0,E
return TRUE;
-
+
case 0x36: /* TNE - MIPS II */
UML_DCMP(block, R64(RSREG), R64(RTREG)); // dcmp <rsreg>,<rtreg>
UML_EXHc(block, IF_NE, mips3.exception[EXCEPTION_TRAP], IMM(0)); // exh trap,0,NE
@@ -2448,7 +2448,7 @@ static int generate_special(drcuml_block *block, compiler_state *compiler, const
UML_DMOVc(block, IF_Z, R64(RDREG), R64(RSREG)); // mov <rdreg>,<rsreg>,Z
}
return TRUE;
-
+
case 0x0b: /* MOVN - MIPS IV */
if (RDREG != 0)
{
@@ -2456,7 +2456,7 @@ static int generate_special(drcuml_block *block, compiler_state *compiler, const
UML_DMOVc(block, IF_NZ, R64(RDREG), R64(RSREG)); // mov <rdreg>,<rsreg>,NZ
}
return TRUE;
-
+
case 0x01: /* MOVF/MOVT - MIPS IV */
if (RDREG != 0)
{
@@ -2545,7 +2545,7 @@ static int generate_regimm(drcuml_block *block, compiler_state *compiler, const
UML_LABEL(block, skip); // skip:
}
return TRUE;
-
+
case 0x01: /* BGEZ */
case 0x03: /* BGEZL */
case 0x11: /* BGEZAL */
@@ -2567,27 +2567,27 @@ static int generate_regimm(drcuml_block *block, compiler_state *compiler, const
UML_DCMP(block, R64(RSREG), IMM(SIMMVAL)); // dcmp <rsreg>,SIMMVAL
UML_EXHc(block, IF_GE, mips3.exception[EXCEPTION_TRAP], IMM(0)); // exh trap,0,GE
return TRUE;
-
+
case 0x09: /* TGEIU */
UML_DCMP(block, R64(RSREG), IMM(SIMMVAL)); // dcmp <rsreg>,SIMMVAL
UML_EXHc(block, IF_AE, mips3.exception[EXCEPTION_TRAP], IMM(0)); // exh trap,0,AE
return TRUE;
-
+
case 0x0a: /* TLTI */
UML_DCMP(block, R64(RSREG), IMM(SIMMVAL)); // dcmp <rsreg>,SIMMVAL
UML_EXHc(block, IF_L, mips3.exception[EXCEPTION_TRAP], IMM(0)); // exh trap,0,L
return TRUE;
-
+
case 0x0b: /* TLTIU */
UML_DCMP(block, R64(RSREG), IMM(SIMMVAL)); // dcmp <rsreg>,SIMMVAL
UML_EXHc(block, IF_B, mips3.exception[EXCEPTION_TRAP], IMM(0)); // exh trap,0,B
return TRUE;
-
+
case 0x0c: /* TEQI */
UML_DCMP(block, R64(RSREG), IMM(SIMMVAL)); // dcmp <rsreg>,SIMMVAL
UML_EXHc(block, IF_E, mips3.exception[EXCEPTION_TRAP], IMM(0)); // exh trap,0,E
return TRUE;
-
+
case 0x0e: /* TNEI */
UML_DCMP(block, R64(RSREG), IMM(SIMMVAL)); // dcmp <rsreg>,SIMMVAL
UML_EXHc(block, IF_NE, mips3.exception[EXCEPTION_TRAP], IMM(0)); // exh trap,0,NE
@@ -2706,7 +2706,7 @@ static int generate_set_cop0_reg(drcuml_block *block, compiler_state *compiler,
UML_CALLC(block, cfunc_get_cycles, &mips3.cstate->numcycles); // callc cfunc_get_cycles,&mips3.numcycles
UML_DZEXT4(block, IREG(0), IREG(0)); // dzext4 i0,i0
UML_DADD(block, IREG(0), IREG(0), IREG(0)); // dadd i0,i0,i0
- UML_DSUB(block, MEM(&mips3.core->count_zero_time), MEM(&mips3.cstate->numcycles), IREG(0));
+ UML_DSUB(block, MEM(&mips3.core->count_zero_time), MEM(&mips3.cstate->numcycles), IREG(0));
// dsub [count_zero_time],[mips3.numcycles],i0
UML_CALLC(block, mips3com_update_cycle_counting, mips3.core); // callc mips3com_update_cycle_counting,mips.core
return TRUE;
@@ -2726,7 +2726,7 @@ static int generate_set_cop0_reg(drcuml_block *block, compiler_state *compiler,
UML_AND(block, IREG(1), CPR032(COP0_Config), IMM(~0x0007)); // and i1,[Config],~0x0007
UML_OR(block, CPR032(COP0_Config), IREG(0), IREG(1)); // or [Config],i0,i1
return TRUE;
-
+
case COP0_EntryHi:
UML_XOR(block, IREG(1), IREG(0), CPR032(reg)); // xor i1,i0,cpr0[reg]
UML_MOV(block, CPR032(reg), IREG(0)); // mov cpr0[reg],i0
@@ -2758,7 +2758,7 @@ static int generate_get_cop0_reg(drcuml_block *block, compiler_state *compiler,
case COP0_Count:
generate_update_cycles(block, compiler, desc->pc, NULL, FALSE); // <subtract cycles>
UML_CALLC(block, cfunc_get_cycles, &mips3.cstate->numcycles); // callc cfunc_get_cycles,&mips3.numcycles
- UML_DSUB(block, IREG(0), MEM(&mips3.cstate->numcycles), MEM(&mips3.core->count_zero_time));
+ UML_DSUB(block, IREG(0), MEM(&mips3.cstate->numcycles), MEM(&mips3.core->count_zero_time));
// dsub i0,[numcycles],[count_zero_time]
UML_DSHR(block, IREG(0), IREG(0), IMM(1)); // dshr i0,i0,1
UML_DSEXT4(block, IREG(0), IREG(0)); // dsext4 i0,i0
@@ -2767,7 +2767,7 @@ static int generate_get_cop0_reg(drcuml_block *block, compiler_state *compiler,
case COP0_Random:
generate_update_cycles(block, compiler, desc->pc, NULL, FALSE); // <subtract cycles>
UML_CALLC(block, cfunc_get_cycles, &mips3.cstate->numcycles); // callc cfunc_get_cycles,&mips3.numcycles
- UML_DSUB(block, IREG(0), MEM(&mips3.cstate->numcycles), MEM(&mips3.core->count_zero_time));
+ UML_DSUB(block, IREG(0), MEM(&mips3.cstate->numcycles), MEM(&mips3.core->count_zero_time));
// dsub i0,[numcycles],[count_zero_time]
UML_AND(block, IREG(1), CPR032(COP0_Wired), IMM(0x3f)); // and i1,[Wired],0x3f
UML_SUBf(block, IREG(2), IMM(48), IREG(1), FLAGS_BE); // sub i2,48,i1,ALL
@@ -2837,7 +2837,7 @@ static int generate_cop0(drcuml_block *block, compiler_state *compiler, const op
UML_DSEXT4(block, IREG(0), R32(RTREG)); // dsext4 i0,<rtreg>
generate_set_cop0_reg(block, compiler, desc, RDREG); // <set cop0 reg>
return TRUE;
-
+
case 0x05: /* DMTCz */
UML_DMOV(block, IREG(0), R64(RTREG)); // dmov i0,<rtreg>
generate_set_cop0_reg(block, compiler, desc, RDREG); // <set cop0 reg>
@@ -2882,7 +2882,7 @@ static int generate_cop0(drcuml_block *block, compiler_state *compiler, const op
return TRUE;
case 0x18: /* ERET */
- UML_AND(block, CPR032(COP0_Status), CPR032(COP0_Status), IMM(~SR_EXL));
+ UML_AND(block, CPR032(COP0_Status), CPR032(COP0_Status), IMM(~SR_EXL));
// and [Status],[Status],~SR_EXL
compiler->checkints = TRUE;
generate_update_cycles(block, compiler, 0, LOPTR(&mips3.core->cpr[0][COP0_EPC]), TRUE);
diff --git a/src/emu/cpu/mips/mips3fe.c b/src/emu/cpu/mips/mips3fe.c
index eadf1b1e5e4..78b1a6dbb9f 100644
--- a/src/emu/cpu/mips/mips3fe.c
+++ b/src/emu/cpu/mips/mips3fe.c
@@ -471,7 +471,7 @@ static int describe_instruction_cop0(mips3_state *mips, UINT32 op, opcode_desc *
desc->cycles += MIPS3_CAUSE_READ_CYCLES;
desc->gpr.modified |= REGFLAG_R(RTREG);
return TRUE;
-
+
case 0x02: /* CFCz */
desc->gpr.modified |= REGFLAG_R(RTREG);
return TRUE;
diff --git a/src/emu/fileio.c b/src/emu/fileio.c
index 3c07d7f867a..abfbdc5509e 100644
--- a/src/emu/fileio.c
+++ b/src/emu/fileio.c
@@ -703,7 +703,7 @@ core_file *mame_core_file(mame_file *file)
/*-------------------------------------------------
- mame_file_full_name - return the full filename
+ mame_file_full_name - return the full filename
for a given mame_file
-------------------------------------------------*/
diff --git a/src/emu/machine/cdp1852.c b/src/emu/machine/cdp1852.c
index 551e75c0858..3589604d197 100644
--- a/src/emu/machine/cdp1852.c
+++ b/src/emu/machine/cdp1852.c
@@ -164,7 +164,7 @@ static DEVICE_RESET( cdp1852 )
// reset data register
cdp1852->data = 0;
-
+
if (cdp1852->intf->mode == CDP1852_MODE_INPUT)
{
// reset service request flip-flop
@@ -174,7 +174,7 @@ static DEVICE_RESET( cdp1852 )
{
// output data
cdp1852->intf->data_w(device, 0);
-
+
// reset service request flip-flop
set_sr_line(device, 0);
}
diff --git a/src/emu/machine/cdp1852.h b/src/emu/machine/cdp1852.h
index 47d44167b9b..eb10dd0ff67 100644
--- a/src/emu/machine/cdp1852.h
+++ b/src/emu/machine/cdp1852.h
@@ -6,19 +6,19 @@
Visit http://mamedev.org for licensing and usage restrictions.
**********************************************************************
- _____ _____
- CSI/_CSI 1 |* \_/ | 24 Vdd
- MODE 2 | | 23 _SR/SR
- DI0 3 | | 22 DI7
- DO0 4 | | 21 DO7
- DI1 5 | | 20 DI6
- DO1 6 | CDP1852 | 19 DO6
- DI2 7 | | 18 DI5
- DO2 8 | | 17 DO5
- DI3 9 | | 16 DI4
- DO3 10 | | 15 DO4
- CLOCK 11 | | 14 _CLEAR
- Vss 12 |_____________| 13 CS2
+ _____ _____
+ CSI/_CSI 1 |* \_/ | 24 Vdd
+ MODE 2 | | 23 _SR/SR
+ DI0 3 | | 22 DI7
+ DO0 4 | | 21 DO7
+ DI1 5 | | 20 DI6
+ DO1 6 | CDP1852 | 19 DO6
+ DI2 7 | | 18 DI5
+ DO2 8 | | 17 DO5
+ DI3 9 | | 16 DI4
+ DO3 10 | | 15 DO4
+ CLOCK 11 | | 14 _CLEAR
+ Vss 12 |_____________| 13 CS2
**********************************************************************/
diff --git a/src/emu/sound/tms5220.c b/src/emu/sound/tms5220.c
index d6e50fc9db0..49e5da33ee5 100644
--- a/src/emu/sound/tms5220.c
+++ b/src/emu/sound/tms5220.c
@@ -10,7 +10,7 @@
Chirp/excitation table fixes by Lord Nightmare
Various fixes by Lord Nightmare
Modularization by Lord Nightmare
-
+
Much information regarding these lpc encoding comes from US patent 4,209,844
US patent 4,331,836 describes the complete 51xx chip
US patent 4,335,277 describes the complete 52xx chip
diff --git a/src/emu/video.c b/src/emu/video.c
index 09b0c83ffb0..6a5c362221e 100644
--- a/src/emu/video.c
+++ b/src/emu/video.c
@@ -2246,7 +2246,7 @@ static file_error mame_fopen_next(running_machine *machine, const char *pathopti
***************************************************************************/
/*-------------------------------------------------
- video_mng_is_movie_active - return true if a
+ video_mng_is_movie_active - return true if a
MNG movie is currently being recorded
-------------------------------------------------*/
@@ -2375,10 +2375,10 @@ void video_avi_begin_recording(const device_config *screen, const char *name)
/* close any existing movie file */
if (state->avi_file != NULL)
video_avi_end_recording(screen);
-
+
/* create a snapshot bitmap so we know what the target size is */
create_snapshot_bitmap(screen);
-
+
/* build up information about this new movie */
info.video_format = 0;
info.video_timescale = 1000 * ATTOSECONDS_TO_HZ(state->frame_period);
@@ -2387,7 +2387,7 @@ void video_avi_begin_recording(const device_config *screen, const char *name)
info.video_width = global.snap_bitmap->width;
info.video_height = global.snap_bitmap->height;
info.video_depth = 24;
-
+
info.audio_format = 0;
info.audio_timescale = 1;
info.audio_sampletime = screen->machine->sample_rate;
@@ -2395,20 +2395,20 @@ void video_avi_begin_recording(const device_config *screen, const char *name)
info.audio_channels = 2;
info.audio_samplebits = 16;
info.audio_samplerate = screen->machine->sample_rate;
-
+
/* create a new temporary movie file */
if (name != NULL)
filerr = mame_fopen(SEARCHPATH_MOVIE, name, OPEN_FLAG_WRITE | OPEN_FLAG_CREATE | OPEN_FLAG_CREATE_PATHS, &tempfile);
else
filerr = mame_fopen_next(screen->machine, SEARCHPATH_MOVIE, "avi", &tempfile);
state->movie_frame = 0;
-
+
/* if we succeeded, make a copy of the name and create the real file over top */
if (filerr == FILERR_NONE)
{
astring *fullname = astring_dupc(mame_file_full_name(tempfile));
mame_fclose(tempfile);
-
+
/* create the file and free the string */
avierr = avi_create(astring_c(fullname), &info, &state->avi_file);
astring_free(fullname);
@@ -2477,7 +2477,7 @@ void video_avi_add_sound(running_machine *machine, const INT16 *sound, int numsa
for (screen = video_screen_first(machine->config); screen != NULL; screen = video_screen_next(screen))
{
screen_state *state = get_safe_token(screen);
-
+
/* only record if we have a file */
if (state->avi_file != NULL)
{
diff --git a/src/emu/video/cdp1869.c b/src/emu/video/cdp1869.c
index cf4a9be63a5..7ffffc97c3a 100644
--- a/src/emu/video/cdp1869.c
+++ b/src/emu/video/cdp1869.c
@@ -12,7 +12,7 @@
- connect to sound system when possible
- white noise
- scanline based update
- - separate to CDP1869 and CDP1870/6
+ - separate to CDP1869 and CDP1870/6
*/
diff --git a/src/lib/util/aviio.c b/src/lib/util/aviio.c
index 80484524f5c..7d1aa11e8b4 100644
--- a/src/lib/util/aviio.c
+++ b/src/lib/util/aviio.c
@@ -2317,7 +2317,7 @@ static avi_error rgb32_compress_to_rgb(avi_stream *stream, const bitmap_t *bitma
*dest++ = RGB_GREEN(pix);
*dest++ = RGB_RED(pix);
}
-
+
/* fill in any blank space on the right */
for ( ; x < stream->width && dest < dataend; x++)
{
@@ -2326,7 +2326,7 @@ static avi_error rgb32_compress_to_rgb(avi_stream *stream, const bitmap_t *bitma
*dest++ = 0;
}
}
-
+
/* fill in any blank space on the bottom */
for ( ; y < stream->height; y++)
{
diff --git a/src/mame/drivers/djmain.c b/src/mame/drivers/djmain.c
index e781c2e957a..04c75cf7e98 100644
--- a/src/mame/drivers/djmain.c
+++ b/src/mame/drivers/djmain.c
@@ -1290,7 +1290,7 @@ ROM_START( bm1stmix )
DISK_REGION( REGION_DISKS ) /* IDE HARD DRIVE */
DISK_IMAGE( "753jaa11", 0, MD5(d56ec7b9877d1f26d7fc1cabed404947) SHA1(71d200d1bd3f1f3a01f4daa78dc9abcca8b8a1fb) ) /* ver 1.00 JA */
// There is an alternate image
- //DISK_IMAGE( "753jaa11", 0, MD5(260c9b72f4a03055e3abad61c6225324) SHA1(2cc3e149744516bf2353a2b47d33bc9d2072b6c4) ) /* ver 1.00 JA */
+ //DISK_IMAGE( "753jaa11", 0, MD5(260c9b72f4a03055e3abad61c6225324) SHA1(2cc3e149744516bf2353a2b47d33bc9d2072b6c4) ) /* ver 1.00 JA */
ROM_END
ROM_START( bm2ndmix )
@@ -1612,7 +1612,7 @@ ROM_START( bmfinal )
DISK_REGION( REGION_DISKS ) /* IDE HARD DRIVE */
DISK_IMAGE( "c01jaa11", 0, NO_DUMP )
// this image has not been verified
- //DISK_IMAGE( "c01jaa11", 0, MD5(8bb7e6b6bc63cac8a4f2997307c25748) ) /* ver 1.00 JA */
+ //DISK_IMAGE( "c01jaa11", 0, MD5(8bb7e6b6bc63cac8a4f2997307c25748) ) /* ver 1.00 JA */
ROM_END
#if 0
diff --git a/src/mame/drivers/funworld.c b/src/mame/drivers/funworld.c
index 766b626410e..fa76834f0fd 100644
--- a/src/mame/drivers/funworld.c
+++ b/src/mame/drivers/funworld.c
@@ -2320,7 +2320,7 @@ static DRIVER_INIT( tabblue )
the result to the left carring the less significant bit and losing the most significant one.
- Encrypted nibble: 0 1 2 3 4 5 6 7 8 9 A B C D E F
+ Encrypted nibble: 0 1 2 3 4 5 6 7 8 9 A B C D E F
Bits: 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111
-------------------------------------------------------------------------------------------------
Bits: 0000 0011 0110 0101 1100 1111 1010 1001 1000 1011 1110 1101 0100 0111 0010 0001
diff --git a/src/mame/drivers/gatron.c b/src/mame/drivers/gatron.c
index ddf105269a7..6769b7918f6 100644
--- a/src/mame/drivers/gatron.c
+++ b/src/mame/drivers/gatron.c
@@ -69,7 +69,7 @@
CPU at u13 still covered in black plastic.
U05 M5L8255AP-5
- U11 SCP RAM TC5516APL (2Kx8)
+ U11 SCP RAM TC5516APL (2Kx8)
U30 VRAM HM6116LP-3 (2Kx8)
1x 16MHz Crystal
@@ -85,7 +85,7 @@
All games:
- The first time the machine is turned on, will show the legend "DATA ERROR".
+ The first time the machine is turned on, will show the legend "DATA ERROR".
You must to RESET (F3) the machine to initialize the NVRAM properly.
@@ -119,7 +119,7 @@
The rest of buttons are self-explanatory.
-
+
* Slots Game:
Pressing SERVICE 1 (key 9) you enter the Test/Setting Mode. You can test
@@ -349,7 +349,7 @@ static const gfx_layout charlayout =
3,
{ 0, RGN_FRAC(1,3), RGN_FRAC(2,3) }, /* bitplanes are separated */
{ 0, 1, 2, 3, 4, 5, 6, 7 },
- { 0*8, 1*8, 2*8, 3*8, 4*8, 5*8, 6*8, 7*8,
+ { 0*8, 1*8, 2*8, 3*8, 4*8, 5*8, 6*8, 7*8,
8*8, 9*8, 10*8, 11*8, 12*8, 13*8, 14*8, 15*8 },
16*8 /* every char takes 16 consecutive bytes */
diff --git a/src/mame/drivers/namcona1.c b/src/mame/drivers/namcona1.c
index 95210ff1227..21b9219b1f2 100644
--- a/src/mame/drivers/namcona1.c
+++ b/src/mame/drivers/namcona1.c
@@ -947,7 +947,7 @@ static void namcona1_blit( running_machine *machine )
(void)src2;
(void)src0;
/*
- logerror( "0x%08x: blt(%08x,%08x,numBytes=%04x);src=%04x %04x %04x; dst=%04x %04x %04x; gfx=%04x\n",
+ logerror( "0x%08x: blt(%08x,%08x,numBytes=%04x);src=%04x %04x %04x; dst=%04x %04x %04x; gfx=%04x\n",
activecpu_get_pc(),
dst_baseaddr,src_baseaddr,num_bytes,
src0,src1,src2,
diff --git a/src/mame/drivers/undrfire.c b/src/mame/drivers/undrfire.c
index fd6f196b9cb..ecb994b2152 100644
--- a/src/mame/drivers/undrfire.c
+++ b/src/mame/drivers/undrfire.c
@@ -462,8 +462,8 @@ static WRITE32_HANDLER( motor_control_w )
static WRITE32_HANDLER( cbombers_cpua_ctrl_w )
{
/*
- ........ ..xxxxxx Lamp 1-6 enables
- ........ .x...... Vibration
+ ........ ..xxxxxx Lamp 1-6 enables
+ ........ .x...... Vibration
*/
cpunum_set_input_line(machine, 2, INPUT_LINE_RESET, (data & 0x1000) ? CLEAR_LINE : ASSERT_LINE);
diff --git a/src/mame/drivers/wrally.c b/src/mame/drivers/wrally.c
index 81dac2efeef..7f5ad260ee0 100644
--- a/src/mame/drivers/wrally.c
+++ b/src/mame/drivers/wrally.c
@@ -22,7 +22,7 @@ CPUs related:
* 1xOSC24MHz @ B20
* 2xM27C4001 @ C22 & C23 (M68000 program ROMs)
* 1xPAL20L8 @ B23 (handles 1st level M68000 memory map)
- 0 -> DTACK M68000 data ack
+ 0 -> DTACK M68000 data ack
1 -> SELACT
2 -> Input/sound (see below)
3 -> ACTEXT
@@ -52,14 +52,14 @@ CPUs related:
7 -> CKA/D?
* 1x16AS @ B15
- 0 -> OE
- 1 -> XSRL Shared RAM @ D14
- 2 -> XSRH Shared RAM @ D15
- 3 -> SAD Shared Access with DS5002FP
- 4 -> SRE Shared Access with M68000
- 5 -> TRANS
- 6 -> XLD
- 7 -> XHI
+ 0 -> OE
+ 1 -> XSRL Shared RAM @ D14
+ 2 -> XSRH Shared RAM @ D15
+ 3 -> SAD Shared Access with DS5002FP
+ 4 -> SRE Shared Access with M68000
+ 5 -> TRANS
+ 6 -> XLD
+ 7 -> XHI
Sound related:
==============
@@ -274,7 +274,7 @@ ROM_START( wrally )
ROM_REGION( 0x100000, REGION_CPU1, 0 ) /* 68000 code */
ROM_LOAD16_BYTE( "worldr17.c23", 0x000000, 0x080000, CRC(050f5629) SHA1(74fc2cd5114f3bc4b2429f1d8d7eeb1658f9f179) ) /* Only difference compared to set 2 is how the Dallas DS5002FP */
ROM_LOAD16_BYTE( "worldr16.c22", 0x000001, 0x080000, CRC(9e0d126c) SHA1(369360b7ec2c3497af3bf62b4eba24c3d9f94675) ) /* power failure shows on screen, IE: "Tension baja " */
-
+
ROM_REGION( 0x10000, REGION_CPU2, 0 ) /* DS5002FP code */
ROM_LOAD( "wrdallas.bin", 0x00000, 0x8000, CRC(547d1768) SHA1(c58d1edd072d796be0663fb265f4739ec006b688) )
@@ -302,7 +302,7 @@ ROM_START( wrallya )
ROM_REGION( 0x100000, REGION_CPU1, 0 ) /* 68000 code */
ROM_LOAD16_BYTE( "c23.bin", 0x000000, 0x080000, CRC(8b7d93c3) SHA1(ce4163eebc5d4a0c1266d650523b1ffc702d1b87) ) /* Only difference compared to set 1 is how the Dallas DS5002FP */
ROM_LOAD16_BYTE( "c22.bin", 0x000001, 0x080000, CRC(56da43b6) SHA1(02db8f969ed5e7f5e5356c45c0312faf5f000335) ) /* power failure shows on screen, IE: "Power Failure" */
-
+
ROM_REGION( 0x10000, REGION_CPU2, 0 ) /* DS5002FP code */
ROM_LOAD( "wrdallas.bin", 0x00000, 0x8000, CRC(547d1768) SHA1(c58d1edd072d796be0663fb265f4739ec006b688) )
@@ -330,7 +330,7 @@ ROM_START( wrallyb ) /* Board Marked 930217, Atari License */
ROM_REGION( 0x100000, REGION_CPU1, 0 ) /* 68000 code */
ROM_LOAD16_BYTE( "rally.c23", 0x000000, 0x080000, CRC(366595ad) SHA1(e16341ed9eacf9b729c28184268150ea9b62f185) ) /* North & South America only... */
ROM_LOAD16_BYTE( "rally.c22", 0x000001, 0x080000, CRC(0ad4ec6f) SHA1(991557cf25fe960b1c586e990e6019befe5a11d0) )
-
+
ROM_REGION( 0x10000, REGION_CPU2, 0 ) /* DS5002FP code */
ROM_LOAD( "wrdallas.bin", 0x00000, 0x8000, CRC(547d1768) SHA1(c58d1edd072d796be0663fb265f4739ec006b688) )
diff --git a/src/mame/machine/gaelcrpt.c b/src/mame/machine/gaelcrpt.c
index 639cf08224a..e60d2a51b3e 100644
--- a/src/mame/machine/gaelcrpt.c
+++ b/src/mame/machine/gaelcrpt.c
@@ -124,7 +124,7 @@ UINT16 gaelco_decrypt(int offset, int data, int param1, int param2)
static int lastpc, lastoffset, lastencword, lastdecword;
int thispc = activecpu_get_pc();
-// int savedata = data;
+// int savedata = data;
/* check if 2nd half of 32 bit */
if(lastpc == thispc && offset == lastoffset + 1)
@@ -145,7 +145,7 @@ UINT16 gaelco_decrypt(int offset, int data, int param1, int param2)
lastdecword = data;
-// logerror("%8x : data1 = %4x > %4x @ %8x\n",activecpu_get_pc(),savedata,data,lastoffset);
+// logerror("%8x : data1 = %4x > %4x @ %8x\n",activecpu_get_pc(),savedata,data,lastoffset);
}
return data;
}
diff --git a/src/mame/video/namcona1.c b/src/mame/video/namcona1.c
index 12ffd30a4cf..02cb89ecebc 100644
--- a/src/mame/video/namcona1.c
+++ b/src/mame/video/namcona1.c
@@ -758,7 +758,7 @@ $efff20: sprite control: 0x3a,0x3e,0x3f
$efff00: src0 src1 src2 dst0 dst1 dst2 BANK [src
$efff10: src] [dst dst] #BYT BLIT eINT 001f 0001
$efff20: 003f 003f IACK ---- ---- ---- ---- ----
-$efff80: 0050 0170 0020 0100 0000 POSI 0000 GFXE POSI: scanline for POSIRQ
+$efff80: 0050 0170 0020 0100 0000 POSI 0000 GFXE POSI: scanline for POSIRQ
$efff90: 0000 0001 0002 0003 FLIP ---- ---- ----
$efffa0: PRI PRI PRI PRI ---- PRI? --?? ---- priority (0..7)
$efffb0: CLR CLR CLR CLR 0001 CLR? BPP ---- color (0..f), bpp flag per layer
diff --git a/src/mame/video/wrally.c b/src/mame/video/wrally.c
index 7dba3724260..8b285cdbfaa 100644
--- a/src/mame/video/wrally.c
+++ b/src/mame/video/wrally.c
@@ -34,7 +34,7 @@ tilemap *wrally_pant[2];
1 | -------- --x----- | priority
1 | -------- -x------ | flip y
1 | -------- x------- | flip x
- 1 | ---xxxxx -------- | data used to handle collisions, speed, etc
+ 1 | ---xxxxx -------- | data used to handle collisions, speed, etc
1 | xxx----- -------- | not used?
*/
@@ -43,9 +43,9 @@ static TILE_GET_INFO( get_tile_info_wrally_screen0 )
int data = wrally_videoram[tile_index << 1];
int data2 = wrally_videoram[(tile_index << 1) + 1];
int code = data & 0x3fff;
-
+
tileinfo->category = (data2 >> 5) & 0x01;
-
+
SET_TILE_INFO(0, code, data2 & 0x1f, TILE_FLIPYX((data2 >> 6) & 0x03));
}
@@ -54,7 +54,7 @@ static TILE_GET_INFO( get_tile_info_wrally_screen1 )
int data = wrally_videoram[(0x2000/2) + (tile_index << 1)];
int data2 = wrally_videoram[(0x2000/2) + (tile_index << 1) + 1];
int code = data & 0x3fff;
-
+
tileinfo->category = (data2 >> 5) & 0x01;
SET_TILE_INFO(0, code, data2 & 0x1f, TILE_FLIPYX((data2 >> 6) & 0x03));
@@ -100,9 +100,9 @@ VIDEO_START( wrally )
3 | --xxxxxx xxxxxxxx | sprite code
3 | xx------ -------- | not used?
- For shadows/highlights, the tile color below the sprite will be set using a
- palette (from the 8 available) based on the gfx pen of the sprite. Only pens
- in the range 0x8-0xf are used.
+ For shadows/highlights, the tile color below the sprite will be set using a
+ palette (from the 8 available) based on the gfx pen of the sprite. Only pens
+ in the range 0x8-0xf are used.
*/
static void draw_sprites(running_machine *machine, bitmap_t *bitmap, const rectangle *cliprect, int priority)
@@ -122,13 +122,13 @@ static void draw_sprites(running_machine *machine, bitmap_t *bitmap, const recta
int color_effect = (color & 0x10) >> 4;
int high_priority = number >= 0x3700;
color = color & 0x0f;
-
+
if (high_priority != priority) continue;
-
+
if (flip_screen_get()) {
sy = sy + 248;
}
-
+
if (!color_effect) {
drawgfx(bitmap,gfx,number,
0x20 + color,xflip,yflip,
@@ -196,15 +196,15 @@ VIDEO_UPDATE( wrally )
tilemap_draw(bitmap,cliprect,wrally_pant[1],TILEMAP_DRAW_OPAQUE,0);
tilemap_draw(bitmap,cliprect,wrally_pant[0],TILEMAP_DRAW_CATEGORY(0) | TILEMAP_DRAW_LAYER0,0);
tilemap_draw(bitmap,cliprect,wrally_pant[0],TILEMAP_DRAW_CATEGORY(0) | TILEMAP_DRAW_LAYER1,0);
-
+
tilemap_draw(bitmap,cliprect,wrally_pant[1],TILEMAP_DRAW_CATEGORY(1),0);
tilemap_draw(bitmap,cliprect,wrally_pant[0],TILEMAP_DRAW_CATEGORY(1) | TILEMAP_DRAW_LAYER0,0);
draw_sprites(screen->machine,bitmap,cliprect,0);
tilemap_draw(bitmap,cliprect,wrally_pant[0],TILEMAP_DRAW_CATEGORY(1) | TILEMAP_DRAW_LAYER1,0);
-
+
draw_sprites(screen->machine,bitmap,cliprect,1);
-
+
return 0;
}
diff --git a/src/version.c b/src/version.c
index 37888b60ad1..a420ae0859a 100644
--- a/src/version.c
+++ b/src/version.c
@@ -9,4 +9,4 @@
***************************************************************************/
-const char build_version[] = "0.125 ("__DATE__")";
+const char build_version[] = "0.125u1 ("__DATE__")";