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authorGravatarGravatar Aaron Giles <aaron@aarongiles.com>2008-06-05 15:57:00 +0000
committerGravatarGravatar Aaron Giles <aaron@aarongiles.com>2008-06-05 15:57:00 +0000
commit1bc774b32b7bc31fa4e0536e2d882c2589819e59 (patch)
tree574c19db33596299806e078fce9ee26ce6a4c74f
parentcfb9caf08f06729c5e312bf7a40f1ca77c2fe72b (diff)
Cleanups/version bump.mame0125u4
-rw-r--r--src/emu/cheat.c142
-rw-r--r--src/emu/cpu/cop400/410ops.c58
-rw-r--r--src/emu/cpu/cop400/cop400.h8
-rw-r--r--src/emu/cpu/cop400/cop410.c2
-rw-r--r--src/emu/cpu/cop400/cop420.c6
-rw-r--r--src/emu/cpu/drcbec.c20
-rw-r--r--src/emu/cpu/drcbex64.c48
-rw-r--r--src/emu/cpu/drcbex86.c46
-rw-r--r--src/emu/cpu/drcuml.c10
-rw-r--r--src/emu/cpu/drcumld.c2
-rw-r--r--src/emu/cpu/minx/minxops.h2
-rw-r--r--src/emu/cpu/powerpc/ppc.h6
-rw-r--r--src/emu/cpu/powerpc/ppc_dasm.c12
-rw-r--r--src/emu/cpu/powerpc/ppccom.c160
-rw-r--r--src/emu/cpu/powerpc/ppccom.h6
-rw-r--r--src/emu/cpu/powerpc/ppcdrc.c276
-rw-r--r--src/emu/cpu/powerpc/ppcfe.c92
-rw-r--r--src/emu/inputseq.c2
-rw-r--r--src/emu/machine/53c810.c2
-rw-r--r--src/mame/drivers/angelkds.c4
-rw-r--r--src/mame/drivers/atarig1.c4
-rw-r--r--src/mame/drivers/atarig42.c2
-rw-r--r--src/mame/drivers/atarisy2.c4
-rw-r--r--src/mame/drivers/blackt96.c2
-rw-r--r--src/mame/drivers/brkthru.c6
-rw-r--r--src/mame/drivers/gticlub.c4
-rw-r--r--src/mame/drivers/hornet.c14
-rw-r--r--src/mame/drivers/imolagp.c16
-rw-r--r--src/mame/drivers/itgambl2.c4
-rw-r--r--src/mame/drivers/itgamble.c6
-rw-r--r--src/mame/drivers/model3.c2
-rw-r--r--src/mame/drivers/ms32.c2
-rw-r--r--src/mame/drivers/nmk16.c2
-rw-r--r--src/mame/drivers/nwk-tr.c4
-rw-r--r--src/mame/drivers/seibuspi.c2
-rw-r--r--src/mame/drivers/tecmosys.c38
-rw-r--r--src/mame/drivers/thayers.c90
-rw-r--r--src/mame/machine/tecmosys.c50
-rw-r--r--src/mame/video/aeroboto.c2
-rw-r--r--src/mame/video/snookr10.c2
-rw-r--r--src/version.c2
41 files changed, 581 insertions, 581 deletions
diff --git a/src/emu/cheat.c b/src/emu/cheat.c
index 1169cdb34e5..608c8a16911 100644
--- a/src/emu/cheat.c
+++ b/src/emu/cheat.c
@@ -116,15 +116,15 @@ enum
/* cpu/region field */
DEFINE_BITFIELD_ENUM(CPUIndex, 0, 3),
DEFINE_BITFIELD_ENUM(AddressSpace, 4, 6),
-// DEFINE_BITFIELD_ENUM(RegionIndex, 0, 6), /* unused ??? */
+// DEFINE_BITFIELD_ENUM(RegionIndex, 0, 6), /* unused ??? */
/* old code */
-// DEFINE_BITFIELD_ENUM(OneShot, 0, 0), /* = OneShot in new format */
+// DEFINE_BITFIELD_ENUM(OneShot, 0, 0), /* = OneShot in new format */
DEFINE_BITFIELD_ENUM(Type, 1, 2),
DEFINE_BITFIELD_ENUM(Operation, 3, 4),
DEFINE_BITFIELD_ENUM(TypeParameter, 5, 7),
- DEFINE_BITFIELD_ENUM(UserSelectEnable, 8, 8),
- DEFINE_BITFIELD_ENUM(UserSelectMinimumDisplay, 9, 9),
+ DEFINE_BITFIELD_ENUM(UserSelectEnable, 8, 8),
+ DEFINE_BITFIELD_ENUM(UserSelectMinimumDisplay, 9, 9),
DEFINE_BITFIELD_ENUM(UserSelectMinimum, 10, 10),
DEFINE_BITFIELD_ENUM(UserSelectBCD, 11, 11),
DEFINE_BITFIELD_ENUM(Prefill, 12, 13),
@@ -402,7 +402,7 @@ enum // entry flags
kCheatFlag_HasWrongCode = 1 << 13,
/* true if the cheat has been edited or is a new cheat
- checked at auto-save then save the code if true */
+ checked at auto-save then save the code if true */
kCheatFlag_Dirty = 1 << 14,
/* masks */
@@ -1062,16 +1062,16 @@ static const UINT32 kIncrementDecTable[] =
static const char *const kRegionNames[] = {
"INVALID",
- "CPU1", "CPU2", "CPU3", "CPU4", "CPU5", "CPU6", "CPU7", "CPU8", // 01-08 [01-08] : CPU
- "GFX1", "GFX2", "GFX3", "GFX4", "GFX5", "GFX6", "GFX7", "GFX8", // 09-16 [08-10] : GFX
- "PROMS", // 17 [11] : PROMS
- "SOUND1", "SOUND2", "SOUND3", "SOUND4", "SOUND5", "SOUND6", "SOUND7", "SOUND8", // 18-25 [12-19] : SOUND
- "USER1", "USER2", "USER3", "USER4", "USER5", "USER6", "USER7", "USER8", // 26-45 [1A-2D] : USER
+ "CPU1", "CPU2", "CPU3", "CPU4", "CPU5", "CPU6", "CPU7", "CPU8", // 01-08 [01-08] : CPU
+ "GFX1", "GFX2", "GFX3", "GFX4", "GFX5", "GFX6", "GFX7", "GFX8", // 09-16 [08-10] : GFX
+ "PROMS", // 17 [11] : PROMS
+ "SOUND1", "SOUND2", "SOUND3", "SOUND4", "SOUND5", "SOUND6", "SOUND7", "SOUND8", // 18-25 [12-19] : SOUND
+ "USER1", "USER2", "USER3", "USER4", "USER5", "USER6", "USER7", "USER8", // 26-45 [1A-2D] : USER
/* USER9 - PLDS are undefined in old format */
"USER9", "USER10", "USER11", "USER12", "USER13", "USER14", "USER15", "USER16",
"USER17", "USER18", "USER19", "USER20",
- "DISKS", // 46 [2E] : DISKS
- "PLDS" }; // 47 [2F] : PLDS
+ "DISKS", // 46 [2E] : DISKS
+ "PLDS" }; // 47 [2F] : PLDS
static const char *const kNumbersTable[] = {
"0", "1", "2", "3", "4", "5", "6", "7",
@@ -1458,12 +1458,12 @@ static int ShiftKeyPressed(void)
{
return (input_code_pressed(KEYCODE_LSHIFT) || input_code_pressed(KEYCODE_RSHIFT));
}
-
+
static int ControlKeyPressed(void)
{
return (input_code_pressed(KEYCODE_LCONTROL) || input_code_pressed(KEYCODE_RCONTROL));
}
-
+
static int AltKeyPressed(void)
{
return (input_code_pressed(KEYCODE_LALT) || input_code_pressed(KEYCODE_RALT));
@@ -4695,31 +4695,31 @@ static int edit_cheat_menu(running_machine *machine, cheat_menu_stack *menu)
switch(info->fieldType)
{
-/* case kType_ActivationKey1:
- case kType_ActivationKey2:
- if(info->fieldType == kType_ActivationKey1)
- {
- entry->activationKey1--;
-
- if(entry->activationKey1 < 0)
- entry->activationKey1 = __code_max - 1;
- if(entry->activationKey1 >= __code_max)
- entry->activationKey1 = 0;
-
- entry->flags |= kCheatFlag_HasActivationKey1;
- }
- else
- {
- entry->activationKey2--;
-
- if(entry->activationKey2 < 0)
- entry->activationKey2 = __code_max - 1;
- if(entry->activationKey2 >= __code_max)
- entry->activationKey2 = 0;
-
- entry->flags |= kCheatFlag_HasActivationKey2;
- }
- break;
+/* case kType_ActivationKey1:
+ case kType_ActivationKey2:
+ if(info->fieldType == kType_ActivationKey1)
+ {
+ entry->activationKey1--;
+
+ if(entry->activationKey1 < 0)
+ entry->activationKey1 = __code_max - 1;
+ if(entry->activationKey1 >= __code_max)
+ entry->activationKey1 = 0;
+
+ entry->flags |= kCheatFlag_HasActivationKey1;
+ }
+ else
+ {
+ entry->activationKey2--;
+
+ if(entry->activationKey2 < 0)
+ entry->activationKey2 = __code_max - 1;
+ if(entry->activationKey2 >= __code_max)
+ entry->activationKey2 = 0;
+
+ entry->flags |= kCheatFlag_HasActivationKey2;
+ }
+ break;
*/
case kType_Link:
TOGGLE_MASK_FIELD(action->type, LinkEnable);
@@ -4995,31 +4995,31 @@ static int edit_cheat_menu(running_machine *machine, cheat_menu_stack *menu)
switch(info->fieldType)
{
-/* case kType_ActivationKey1:
- case kType_ActivationKey2:
- if(info->fieldType == kType_ActivationKey1)
- {
- entry->activationKey1++;
-
- if(entry->activationKey1 < 0)
- entry->activationKey1 = __code_max - 1;
- if(entry->activationKey1 >= __code_max)
- entry->activationKey1 = 0;
-
- entry->flags |= kCheatFlag_HasActivationKey1;
- }
- else
- {
- entry->activationKey2++;
-
- if(entry->activationKey2 < 0)
- entry->activationKey2 = __code_max - 1;
- if(entry->activationKey2 >= __code_max)
- entry->activationKey2 = 0;
-
- entry->flags |= kCheatFlag_HasActivationKey2;
- }
- break;
+/* case kType_ActivationKey1:
+ case kType_ActivationKey2:
+ if(info->fieldType == kType_ActivationKey1)
+ {
+ entry->activationKey1++;
+
+ if(entry->activationKey1 < 0)
+ entry->activationKey1 = __code_max - 1;
+ if(entry->activationKey1 >= __code_max)
+ entry->activationKey1 = 0;
+
+ entry->flags |= kCheatFlag_HasActivationKey1;
+ }
+ else
+ {
+ entry->activationKey2++;
+
+ if(entry->activationKey2 < 0)
+ entry->activationKey2 = __code_max - 1;
+ if(entry->activationKey2 >= __code_max)
+ entry->activationKey2 = 0;
+
+ entry->flags |= kCheatFlag_HasActivationKey2;
+ }
+ break;
*/
case kType_Link:
TOGGLE_MASK_FIELD(action->type, LinkEnable);
@@ -6232,8 +6232,8 @@ static int search_minimum_menu(running_machine *machine, cheat_menu_stack *menu)
const char * menuSubItem[kMenu_Max + 1] = { 0 };
char flagBuf[kMenu_Max + 1] = { 0 };
char cpuBuf[4];
- char valueBuf[32]; // "FFFFFFF[F] (4294967295)" 23 chars
- char timerBuf[32]; // "-FFFFFFF[F] (4294967295)" 24 chars
+ char valueBuf[32]; // "FFFFFFF[F] (4294967295)" 23 chars
+ char timerBuf[32]; // "-FFFFFFF[F] (4294967295)" 24 chars
char numResultsBuf[16];
char * stringsBuf;
search_info *search = get_current_search();
@@ -7835,7 +7835,7 @@ static int select_search_region_menu(running_machine *machine, cheat_menu_stack
else
{
- /* in case of no search region */
+ /* in case of no search region */
menu_item[total] = "No Search Region";
menu_sub_item[total++] = NULL;
}
@@ -8356,7 +8356,7 @@ static int choose_watch_menu(running_machine *machine, cheat_menu_stack *menu)
UINT8 total = 0;
const char ** menuItem;
char ** buf;
- char * stringsBuf; // "USER20 FFFFFFFF (99:32 Bit)" 27 chars
+ char * stringsBuf; // "USER20 FFFFFFFF (99:32 Bit)" 27 chars
watch_info *watch;
/* first setting : NONE */
@@ -10455,7 +10455,7 @@ static void resize_cheat_action_list(cheat_entry *entry, UINT32 new_length, UINT
#if 0
/*----------------------------------------------------------------
AddActionBefore - Insert empty Action
- This function is only called in EditCheat()
+ This function is only called in EditCheat()
----------------------------------------------------------------*/
static void AddActionBefore(CheatEntry * entry, UINT32 idx)
@@ -10973,7 +10973,7 @@ static UINT32 read_region_data(search_region *region, UINT32 offset, UINT8 size,
UINT8 * buf = (UINT8 *)region->cached_pointer;
if(buf)
-/* return DoMemoryRead(region->cached_pointer, address, size, swap, &raw_cpu_info); */
+/* return DoMemoryRead(region->cached_pointer, address, size, swap, &raw_cpu_info); */
return DoMemoryRead(buf, address, size, cpu_needs_swap(region->target_idx) ^ swap, get_cpu_info(region->target_idx));
else
return 0;
@@ -14982,7 +14982,7 @@ static void BuildLabelIndexTable(cheat_entry *entry)
//logerror("Cheat - Finish building index table for %s (length = %x)\n", entry->name, entry->label_index_length);
//for(i = 0; i < entry->label_index_length; i++)
- // logerror("IndexTable[%x] = %x\n",i,entry->label_index[i]);
+ // logerror("IndexTable[%x] = %x\n",i,entry->label_index[i]);
}
diff --git a/src/emu/cpu/cop400/410ops.c b/src/emu/cpu/cop400/410ops.c
index 8c5ebf5a457..478890c904c 100644
--- a/src/emu/cpu/cop400/410ops.c
+++ b/src/emu/cpu/cop400/410ops.c
@@ -492,7 +492,7 @@ INSTRUCTION(retsk)
/*
- Processor: COP410C/COP411C
+ Processor: COP410C/COP411C
Mnemonic: HALT
@@ -528,34 +528,34 @@ INSTRUCTION(camq)
{
/*
- Excerpt from the COP410L data sheet:
-
- False states may be generated on L0-L7 during the execution of the CAMQ instruction.
- The L-ports should not be used as clocks for edge sensitive devices such as flip-flops,
- counters, shift registers, etc. the following short program that illustrates this situation.
-
- START:
- CLRA ;ENABLE THE Q
- LEI 4 ;REGISTER TO L LINES
- LBI TEST
- STII 3
- AISC 12
- LOOP:
- LBI TEST ;LOAD Q WITH X'C3
- CAMQ
- JP LOOP
-
- In this program the internal Q register is enabled onto the L lines and a steady bit
- pattern of logic highs is output on L0, L1, L6, L7, and logic lows on L2-L5 via the
- two-byte CAMQ instruction. Timing constraints on the device are such that the Q
- register may be temporarily loaded with the second byte of the CAMQ opcode (3C) prior
- to receiving the valid data pattern. If this occurs, the opcode will ripple onto the L
- lines and cause negative-going glitches on L0, L1, L6, L7, and positive glitches on
- L2-L5. Glitch durations are under 2 ms, although the exact value may vary due to data
- patterns, processing parameters, and L line loading. These false states are peculiar
- only to the CAMQ instruction and the L lines.
-
- */
+ Excerpt from the COP410L data sheet:
+
+ False states may be generated on L0-L7 during the execution of the CAMQ instruction.
+ The L-ports should not be used as clocks for edge sensitive devices such as flip-flops,
+ counters, shift registers, etc. the following short program that illustrates this situation.
+
+ START:
+ CLRA ;ENABLE THE Q
+ LEI 4 ;REGISTER TO L LINES
+ LBI TEST
+ STII 3
+ AISC 12
+ LOOP:
+ LBI TEST ;LOAD Q WITH X'C3
+ CAMQ
+ JP LOOP
+
+ In this program the internal Q register is enabled onto the L lines and a steady bit
+ pattern of logic highs is output on L0, L1, L6, L7, and logic lows on L2-L5 via the
+ two-byte CAMQ instruction. Timing constraints on the device are such that the Q
+ register may be temporarily loaded with the second byte of the CAMQ opcode (3C) prior
+ to receiving the valid data pattern. If this occurs, the opcode will ripple onto the L
+ lines and cause negative-going glitches on L0, L1, L6, L7, and positive glitches on
+ L2-L5. Glitch durations are under 2 ms, although the exact value may vary due to data
+ patterns, processing parameters, and L line loading. These false states are peculiar
+ only to the CAMQ instruction and the L lines.
+
+ */
UINT8 data = (A << 4) | RAM_R(B);
diff --git a/src/emu/cpu/cop400/cop400.h b/src/emu/cpu/cop400/cop400.h
index 7b4f2592dce..3427b040d30 100644
--- a/src/emu/cpu/cop400/cop400.h
+++ b/src/emu/cpu/cop400/cop400.h
@@ -67,11 +67,11 @@ struct _cop400_interface
/*
- Prefix Temperature Range
+ Prefix Temperature Range
- COP4xx 0C to 70C
- COP3xx -40C to +85C
- COP2xx -55C to +125C
+ COP4xx 0C to 70C
+ COP3xx -40C to +85C
+ COP2xx -55C to +125C
*/
diff --git a/src/emu/cpu/cop400/cop410.c b/src/emu/cpu/cop400/cop410.c
index b55f6fc5b7a..2722842f144 100644
--- a/src/emu/cpu/cop400/cop410.c
+++ b/src/emu/cpu/cop400/cop410.c
@@ -15,7 +15,7 @@
- run interrupt test suite
- run production test suite
- - run microbus test suite
+ - run microbus test suite
- remove LBIops
*/
diff --git a/src/emu/cpu/cop400/cop420.c b/src/emu/cpu/cop400/cop420.c
index ab94755a53a..23510320cd3 100644
--- a/src/emu/cpu/cop400/cop420.c
+++ b/src/emu/cpu/cop400/cop420.c
@@ -13,12 +13,12 @@
TODO:
- - when is the microbus int cleared?
+ - when is the microbus int cleared?
- run interrupt test suite
- run production test suite
- - run microbus test suite
+ - run microbus test suite
- remove LBIops
- - move cop440 stuff to cop440.c
+ - move cop440 stuff to cop440.c
*/
diff --git a/src/emu/cpu/drcbec.c b/src/emu/cpu/drcbec.c
index 4506d4f2651..925b42d2d98 100644
--- a/src/emu/cpu/drcbec.c
+++ b/src/emu/cpu/drcbec.c
@@ -465,7 +465,7 @@ static void drcbec_generate(drcbe_state *drcbe, drcuml_block *block, const drcum
psize[0] = 1 << inst->param[2].value;
if (opcode == DRCUML_OP_FFRINT || opcode == DRCUML_OP_FFRFLT)
psize[1] = 1 << inst->param[2].value;
-
+
/* pre-expand opcodes that encode size in them */
if (opcode == DRCUML_OP_LOAD)
opcode = DRCUML_OP_LOAD1 + (inst->param[3].value & 3);
@@ -732,11 +732,11 @@ static int drcbec_execute(drcbe_state *drcbe, drcuml_codehandle *entry)
case MAKE_OPCODE_SHORT(DRCUML_OP_LOADS1, 4, 0): /* LOADS dst,base,index,BYTE */
PARAM0 = inst[1].pint8[PARAM2];
break;
-
+
case MAKE_OPCODE_SHORT(DRCUML_OP_LOADS2, 4, 0): /* LOADS dst,base,index,WORD */
PARAM0 = inst[1].pint16[PARAM2];
break;
-
+
case MAKE_OPCODE_SHORT(DRCUML_OP_LOADS4, 4, 0): /* LOADS dst,base,index,DWORD */
PARAM0 = inst[1].pint32[PARAM2];
break;
@@ -744,33 +744,33 @@ static int drcbec_execute(drcbe_state *drcbe, drcuml_codehandle *entry)
case MAKE_OPCODE_SHORT(DRCUML_OP_STORE1, 4, 0): /* STORE dst,base,index,BYTE */
inst[0].puint8[PARAM1] = PARAM2;
break;
-
+
case MAKE_OPCODE_SHORT(DRCUML_OP_STORE2, 4, 0): /* STORE dst,base,index,WORD */
inst[0].puint16[PARAM1] = PARAM2;
break;
-
+
case MAKE_OPCODE_SHORT(DRCUML_OP_STORE4, 4, 0): /* STORE dst,base,index,DWORD */
inst[0].puint32[PARAM1] = PARAM2;
break;
case MAKE_OPCODE_SHORT(DRCUML_OP_READ1, 4, 0): /* READ dst,src1,space_BYTE */
- PARAM0 = (UINT8)(*active_address_space[PARAM2 / 16].accessors->read_byte)(PARAM1);
+ PARAM0 = (UINT8)(*active_address_space[PARAM2 / 16].accessors->read_byte)(PARAM1);
break;
case MAKE_OPCODE_SHORT(DRCUML_OP_READ2, 4, 0): /* READ dst,src1,space_WORD */
- PARAM0 = (UINT16)(*active_address_space[PARAM2 / 16].accessors->read_word)(PARAM1);
+ PARAM0 = (UINT16)(*active_address_space[PARAM2 / 16].accessors->read_word)(PARAM1);
break;
case MAKE_OPCODE_SHORT(DRCUML_OP_READ4, 4, 0): /* READ dst,src1,space_DWORD */
- PARAM0 = (UINT32)(*active_address_space[PARAM2 / 16].accessors->read_dword)(PARAM1);
+ PARAM0 = (UINT32)(*active_address_space[PARAM2 / 16].accessors->read_dword)(PARAM1);
break;
case MAKE_OPCODE_SHORT(DRCUML_OP_READM2, 4, 0): /* READM dst,src1,mask,space_WORD */
- PARAM0 = (UINT16)(*active_address_space[PARAM3 / 16].accessors->read_word_masked)(PARAM1, PARAM2);
+ PARAM0 = (UINT16)(*active_address_space[PARAM3 / 16].accessors->read_word_masked)(PARAM1, PARAM2);
break;
case MAKE_OPCODE_SHORT(DRCUML_OP_READM4, 4, 0): /* READM dst,src1,mask,space_DWORD */
- PARAM0 = (UINT32)(*active_address_space[PARAM3 / 16].accessors->read_dword_masked)(PARAM1, PARAM2);
+ PARAM0 = (UINT32)(*active_address_space[PARAM3 / 16].accessors->read_dword_masked)(PARAM1, PARAM2);
break;
case MAKE_OPCODE_SHORT(DRCUML_OP_WRITE1, 4, 0): /* WRITE dst,src1,space_BYTE */
diff --git a/src/emu/cpu/drcbex64.c b/src/emu/cpu/drcbex64.c
index 1e4dd02e44b..85ba1d12d45 100644
--- a/src/emu/cpu/drcbex64.c
+++ b/src/emu/cpu/drcbex64.c
@@ -3499,7 +3499,7 @@ static x86code *op_getflgs(drcbe_state *drcbe, x86code *dst, const drcuml_instru
/* normalize parameters */
param_normalize_1(drcbe, inst, &dstp, PTYPE_MR);
-
+
/* pick a target register for the general case */
dstreg = param_select_register(REG_EAX, &dstp, NULL);
@@ -3534,7 +3534,7 @@ static x86code *op_getflgs(drcbe_state *drcbe, x86code *dst, const drcuml_instru
emit_movzx_r32_r8(&dst, dstreg, REG_AL); // movzx dstreg,al
emit_shl_r32_imm(&dst, dstreg, 4); // shl dstreg,4
break;
-
+
/* carry plus another flag */
case DRCUML_FLAG_C | DRCUML_FLAG_V:
emit_setcc_r8(&dst, COND_C, REG_AL); // setc al
@@ -3543,7 +3543,7 @@ static x86code *op_getflgs(drcbe_state *drcbe, x86code *dst, const drcuml_instru
emit_movzx_r32_r8(&dst, REG_ECX, REG_CL); // movzx ecx,al
emit_lea_r32_m32(&dst, dstreg, MBISD(REG_EAX, REG_ECX, 2, 0)); // lea dstreg,[eax+ecx*2]
break;
-
+
case DRCUML_FLAG_C | DRCUML_FLAG_Z:
emit_setcc_r8(&dst, COND_C, REG_AL); // setc al
emit_setcc_r8(&dst, COND_Z, REG_CL); // setz cl
@@ -3551,7 +3551,7 @@ static x86code *op_getflgs(drcbe_state *drcbe, x86code *dst, const drcuml_instru
emit_movzx_r32_r8(&dst, REG_ECX, REG_CL); // movzx ecx,al
emit_lea_r32_m32(&dst, dstreg, MBISD(REG_EAX, REG_ECX, 4, 0)); // lea dstreg,[eax+ecx*4]
break;
-
+
case DRCUML_FLAG_C | DRCUML_FLAG_S:
emit_setcc_r8(&dst, COND_C, REG_AL); // setc al
emit_setcc_r8(&dst, COND_S, REG_CL); // sets cl
@@ -3559,7 +3559,7 @@ static x86code *op_getflgs(drcbe_state *drcbe, x86code *dst, const drcuml_instru
emit_movzx_r32_r8(&dst, REG_ECX, REG_CL); // movzx ecx,al
emit_lea_r32_m32(&dst, dstreg, MBISD(REG_EAX, REG_ECX, 8, 0)); // lea dstreg,[eax+ecx*8]
break;
-
+
/* overflow plus another flag */
case DRCUML_FLAG_V | DRCUML_FLAG_Z:
emit_setcc_r8(&dst, COND_O, REG_AL); // seto al
@@ -3569,7 +3569,7 @@ static x86code *op_getflgs(drcbe_state *drcbe, x86code *dst, const drcuml_instru
emit_lea_r32_m32(&dst, dstreg, MBISD(REG_EAX, REG_ECX, 2, 0)); // lea dstreg,[eax+ecx*2]
emit_shl_r32_imm(&dst, dstreg, 1); // shl dstreg,1
break;
-
+
case DRCUML_FLAG_V | DRCUML_FLAG_S:
emit_setcc_r8(&dst, COND_O, REG_AL); // seto al
emit_setcc_r8(&dst, COND_S, REG_CL); // sets cl
@@ -3578,7 +3578,7 @@ static x86code *op_getflgs(drcbe_state *drcbe, x86code *dst, const drcuml_instru
emit_lea_r32_m32(&dst, dstreg, MBISD(REG_EAX, REG_ECX, 4, 0)); // lea dstreg,[eax+ecx*4]
emit_shl_r32_imm(&dst, dstreg, 1); // shl dstreg,1
break;
-
+
/* zero plus another flag */
case DRCUML_FLAG_Z | DRCUML_FLAG_S:
emit_setcc_r8(&dst, COND_Z, REG_AL); // setz al
@@ -3588,7 +3588,7 @@ static x86code *op_getflgs(drcbe_state *drcbe, x86code *dst, const drcuml_instru
emit_lea_r32_m32(&dst, dstreg, MBISD(REG_EAX, REG_ECX, 2, 0)); // lea dstreg,[eax+ecx*2]
emit_shl_r32_imm(&dst, dstreg, 2); // shl dstreg,2
break;
-
+
/* default cases */
default:
emit_pushf(&dst); // pushf
@@ -3598,11 +3598,11 @@ static x86code *op_getflgs(drcbe_state *drcbe, x86code *dst, const drcuml_instru
// movzx dstreg,[flags_map]
break;
}
-
+
/* 32-bit form */
if (inst->size == 4)
emit_mov_p32_r32(drcbe, &dst, &dstp, dstreg); // mov dstp,dstreg
-
+
/* 64-bit form */
else if (inst->size == 8)
emit_mov_p64_r64(drcbe, &dst, &dstp, dstreg); // mov dstp,dstreg
@@ -3926,12 +3926,12 @@ static x86code *op_store(drcbe_state *drcbe, x86code *dst, const drcuml_instruct
else
{
emit_mov_m32_imm(&dst, MBD(basereg, baseoffs + 8*indp.value), srcp.value);// mov [basep + 8*indp],srcp
- emit_mov_m32_imm(&dst, MBD(basereg, baseoffs + 8*indp.value + 4), srcp.value >> 32);
+ emit_mov_m32_imm(&dst, MBD(basereg, baseoffs + 8*indp.value + 4), srcp.value >> 32);
// mov [basep + 8*indp + 4],srcp >> 32
}
}
}
-
+
/* variable source */
else
{
@@ -4281,15 +4281,15 @@ static x86code *op_set(drcbe_state *drcbe, x86code *dst, const drcuml_instructio
/* pick a target register for the general case */
dstreg = param_select_register(REG_EAX, &dstp, NULL);
-
+
/* set to AL */
emit_setcc_r8(&dst, X86_CONDITION(inst->condflags), REG_AL); // setcc al
emit_movzx_r32_r8(&dst, dstreg, REG_AL); // movzx dstreg,al
-
+
/* 32-bit form */
if (inst->size == 4)
emit_mov_p32_r32(drcbe, &dst, &dstp, dstreg); // mov dstp,dstreg
-
+
/* 64-bit form */
else if (inst->size == 8)
emit_mov_p64_r64(drcbe, &dst, &dstp, dstreg); // mov dstp,dstreg
@@ -4988,7 +4988,7 @@ static x86code *op_mulu(drcbe_state *drcbe, x86code *dst, const drcuml_instructi
emit_mov_p32_r32(drcbe, &dst, &dstp, REG_EAX); // mov dstp,eax
if (compute_hi)
emit_mov_p32_r32(drcbe, &dst, &edstp, REG_EDX); // mov edstp,edx
-
+
/* compute flags */
if (inst->condflags != 0)
{
@@ -5028,7 +5028,7 @@ static x86code *op_mulu(drcbe_state *drcbe, x86code *dst, const drcuml_instructi
emit_mov_p64_r64(drcbe, &dst, &dstp, REG_RAX); // mov dstp,rax
if (compute_hi)
emit_mov_p64_r64(drcbe, &dst, &edstp, REG_RDX); // mov edstp,rdx
-
+
/* compute flags */
if (inst->condflags != 0)
{
@@ -5190,7 +5190,7 @@ static x86code *op_muls(drcbe_state *drcbe, x86code *dst, const drcuml_instructi
emit_mov_p64_r64(drcbe, &dst, &dstp, REG_RAX); // mov dstp,rax
emit_mov_p64_r64(drcbe, &dst, &edstp, REG_RDX); // mov edstp,rdx
}
-
+
/* compute flags */
if (inst->condflags != 0)
{
@@ -6404,7 +6404,7 @@ static x86code *op_ftoint(drcbe_state *drcbe, x86code *dst, const drcuml_instruc
emit_stmxcsr_m32(&dst, MABS(drcbe, &drcbe->ssemodesave)); // stmxcsr [ssemodesave]
emit_ldmxcsr_m32(&dst, MABS(drcbe, &drcbe->ssecontrol[roundp.value])); // ldmxcsr fpcontrol[mode]
}
-
+
/* 32-bit form */
if (inst->size == 4)
{
@@ -6426,7 +6426,7 @@ static x86code *op_ftoint(drcbe_state *drcbe, x86code *dst, const drcuml_instruc
emit_cvttss2si_r32_r128(&dst, dstreg, srcp.value); // cvttss2si dstreg,srcp
}
}
-
+
/* 64-bit integer source */
else if (sizep.value == DRCUML_SIZE_QWORD)
{
@@ -6468,7 +6468,7 @@ static x86code *op_ftoint(drcbe_state *drcbe, x86code *dst, const drcuml_instruc
emit_cvttsd2si_r32_r128(&dst, dstreg, srcp.value); // cvttsd2si dstreg,srcp
}
}
-
+
/* 64-bit integer source */
else if (sizep.value == DRCUML_SIZE_QWORD)
{
@@ -6537,7 +6537,7 @@ static x86code *op_ffrint(drcbe_state *drcbe, x86code *dst, const drcuml_instruc
emit_cvtsi2ss_r128_r32(&dst, dstreg, srcreg); // cvtsi2ss dstreg,srcreg
}
}
-
+
/* 64-bit integer source */
else
{
@@ -6568,7 +6568,7 @@ static x86code *op_ffrint(drcbe_state *drcbe, x86code *dst, const drcuml_instruc
emit_cvtsi2sd_r128_r32(&dst, dstreg, srcreg); // cvtsi2sd dstreg,srcreg
}
}
-
+
/* 64-bit integer source */
else
{
@@ -6615,7 +6615,7 @@ static x86code *op_ffrflt(drcbe_state *drcbe, x86code *dst, const drcuml_instruc
emit_cvtss2sd_r128_r128(&dst, dstreg, srcp.value); // cvtss2sd dstreg,srcp
emit_movsd_p64_r128(drcbe, &dst, &dstp, dstreg); // movsd dstp,dstreg
}
-
+
/* double-to-single */
else if (inst->size == 4 && sizep.value == DRCUML_SIZE_QWORD)
{
diff --git a/src/emu/cpu/drcbex86.c b/src/emu/cpu/drcbex86.c
index f0bffc6829f..46a5a2489cf 100644
--- a/src/emu/cpu/drcbex86.c
+++ b/src/emu/cpu/drcbex86.c
@@ -17,7 +17,7 @@
- also FCMP/FLAGS has unnecessary PUSHF/POP EAX
* Identify common pairs and optimize output
-
+
* Convert AND 0xff/0xffff to movzx
****************************************************************************
@@ -3549,7 +3549,7 @@ static x86code *op_getflgs(drcbe_state *drcbe, x86code *dst, const drcuml_instru
/* normalize parameters */
param_normalize_1(drcbe, inst, &dstp, PTYPE_MR);
-
+
/* pick a target register for the general case */
dstreg = param_select_register(REG_EAX, &dstp, NULL);
@@ -3584,7 +3584,7 @@ static x86code *op_getflgs(drcbe_state *drcbe, x86code *dst, const drcuml_instru
emit_movzx_r32_r8(&dst, dstreg, REG_AL); // movzx dstreg,al
emit_shl_r32_imm(&dst, dstreg, 4); // shl dstreg,4
break;
-
+
/* carry plus another flag */
case DRCUML_FLAG_C | DRCUML_FLAG_V:
emit_setcc_r8(&dst, COND_C, REG_AL); // setc al
@@ -3593,7 +3593,7 @@ static x86code *op_getflgs(drcbe_state *drcbe, x86code *dst, const drcuml_instru
emit_movzx_r32_r8(&dst, REG_ECX, REG_CL); // movzx ecx,al
emit_lea_r32_m32(&dst, dstreg, MBISD(REG_EAX, REG_ECX, 2, 0)); // lea dstreg,[eax+ecx*2]
break;
-
+
case DRCUML_FLAG_C | DRCUML_FLAG_Z:
emit_setcc_r8(&dst, COND_C, REG_AL); // setc al
emit_setcc_r8(&dst, COND_Z, REG_CL); // setz cl
@@ -3601,7 +3601,7 @@ static x86code *op_getflgs(drcbe_state *drcbe, x86code *dst, const drcuml_instru
emit_movzx_r32_r8(&dst, REG_ECX, REG_CL); // movzx ecx,al
emit_lea_r32_m32(&dst, dstreg, MBISD(REG_EAX, REG_ECX, 4, 0)); // lea dstreg,[eax+ecx*4]
break;
-
+
case DRCUML_FLAG_C | DRCUML_FLAG_S:
emit_setcc_r8(&dst, COND_C, REG_AL); // setc al
emit_setcc_r8(&dst, COND_S, REG_CL); // sets cl
@@ -3609,7 +3609,7 @@ static x86code *op_getflgs(drcbe_state *drcbe, x86code *dst, const drcuml_instru
emit_movzx_r32_r8(&dst, REG_ECX, REG_CL); // movzx ecx,al
emit_lea_r32_m32(&dst, dstreg, MBISD(REG_EAX, REG_ECX, 8, 0)); // lea dstreg,[eax+ecx*8]
break;
-
+
/* overflow plus another flag */
case DRCUML_FLAG_V | DRCUML_FLAG_Z:
emit_setcc_r8(&dst, COND_O, REG_AL); // seto al
@@ -3619,7 +3619,7 @@ static x86code *op_getflgs(drcbe_state *drcbe, x86code *dst, const drcuml_instru
emit_lea_r32_m32(&dst, dstreg, MBISD(REG_EAX, REG_ECX, 2, 0)); // lea dstreg,[eax+ecx*2]
emit_shl_r32_imm(&dst, dstreg, 1); // shl dstreg,1
break;
-
+
case DRCUML_FLAG_V | DRCUML_FLAG_S:
emit_setcc_r8(&dst, COND_O, REG_AL); // seto al
emit_setcc_r8(&dst, COND_S, REG_CL); // sets cl
@@ -3628,7 +3628,7 @@ static x86code *op_getflgs(drcbe_state *drcbe, x86code *dst, const drcuml_instru
emit_lea_r32_m32(&dst, dstreg, MBISD(REG_EAX, REG_ECX, 4, 0)); // lea dstreg,[eax+ecx*4]
emit_shl_r32_imm(&dst, dstreg, 1); // shl dstreg,1
break;
-
+
/* zero plus another flag */
case DRCUML_FLAG_Z | DRCUML_FLAG_S:
emit_setcc_r8(&dst, COND_Z, REG_AL); // setz al
@@ -3638,7 +3638,7 @@ static x86code *op_getflgs(drcbe_state *drcbe, x86code *dst, const drcuml_instru
emit_lea_r32_m32(&dst, dstreg, MBISD(REG_EAX, REG_ECX, 2, 0)); // lea dstreg,[eax+ecx*2]
emit_shl_r32_imm(&dst, dstreg, 2); // shl dstreg,2
break;
-
+
/* default cases */
default:
emit_pushf(&dst); // pushf
@@ -3647,7 +3647,7 @@ static x86code *op_getflgs(drcbe_state *drcbe, x86code *dst, const drcuml_instru
emit_movzx_r32_m8(&dst, dstreg, MBD(REG_EAX, flags_map)); // movzx dstreg,[flags_map]
break;
}
-
+
/* store low 32 bits */
emit_mov_p32_r32(drcbe, &dst, &dstp, dstreg); // mov dstp,dstreg
@@ -3854,7 +3854,7 @@ static x86code *op_load(drcbe_state *drcbe, x86code *dst, const drcuml_instructi
else if (dstp.type == DRCUML_PTYPE_INT_REGISTER)
emit_mov_m32_imm(&dst, MABS(drcbe->reghi[dstp.value]), 0); // mov [reghi],0
}
-
+
/* 8-byte case */
else
{
@@ -3973,11 +3973,11 @@ static x86code *op_store(drcbe_state *drcbe, x86code *dst, const drcuml_instruct
else if (sizep.value == DRCUML_SIZE_QWORD)
{
emit_mov_m32_imm(&dst, MABS(basep.value + 8*indp.value), srcp.value); // mov [basep + 8*indp],srcp
- emit_mov_m32_imm(&dst, MABS(basep.value + 8*indp.value + 4), srcp.value >> 32);
+ emit_mov_m32_imm(&dst, MABS(basep.value + 8*indp.value + 4), srcp.value >> 32);
// mov [basep + 8*indp + 4],srcp >> 32
}
}
-
+
/* variable source */
else
{
@@ -4107,7 +4107,7 @@ static x86code *op_read(drcbe_state *drcbe, x86code *dst, const drcuml_instructi
else if (dstp.type == DRCUML_PTYPE_INT_REGISTER)
emit_mov_m32_imm(&dst, MABS(drcbe->reghi[dstp.value]), 0); // mov [reghi],0
}
-
+
/* 8-byte case */
else
{
@@ -4180,7 +4180,7 @@ static x86code *op_readm(drcbe_state *drcbe, x86code *dst, const drcuml_instruct
else if (dstp.type == DRCUML_PTYPE_INT_REGISTER)
emit_mov_m32_imm(&dst, MABS(drcbe->reghi[dstp.value]), 0); // mov [reghi],0
}
-
+
/* 8-byte case */
else
{
@@ -4371,7 +4371,7 @@ static x86code *op_set(drcbe_state *drcbe, x86code *dst, const drcuml_instructio
/* pick a target register for the general case */
dstreg = param_select_register(REG_EAX, &dstp, NULL);
-
+
/* set to AL */
emit_setcc_r8(&dst, X86_CONDITION(inst->condflags), REG_AL); // setcc al
emit_movzx_r32_r8(&dst, dstreg, REG_AL); // movzx dstreg,al
@@ -4554,7 +4554,7 @@ static x86code *op_sext(drcbe_state *drcbe, x86code *dst, const drcuml_instructi
else if (sizep.value == DRCUML_SIZE_DWORD && dstreg != srcp.value)
emit_mov_r32_r32(&dst, dstreg, srcp.value); // mov dstreg,srcp
}
-
+
/* 32-bit form: store the low 32 bits */
if (inst->size == 4)
emit_mov_p32_r32(drcbe, &dst, &dstp, dstreg); // mov dstp,dstreg
@@ -5107,7 +5107,7 @@ static x86code *op_mulu(drcbe_state *drcbe, x86code *dst, const drcuml_instructi
emit_mov_p32_r32(drcbe, &dst, &dstp, REG_EAX); // mov dstp,eax
if (compute_hi)
emit_mov_p32_r32(drcbe, &dst, &edstp, REG_EDX); // mov edstp,edx
-
+
/* compute flags */
if (inst->condflags != 0)
{
@@ -5279,7 +5279,7 @@ static x86code *op_muls(drcbe_state *drcbe, x86code *dst, const drcuml_instructi
emit_mov_p32_r32(drcbe, &dst, &dstp, REG_EAX); // mov dstp,eax
emit_mov_p32_r32(drcbe, &dst, &edstp, REG_EDX); // mov edstp,edx
}
-
+
/* compute flags */
if (inst->condflags != 0)
{
@@ -6469,10 +6469,10 @@ static x86code *op_ftoint(drcbe_state *drcbe, x86code *dst, const drcuml_instruc
emit_fstcw_m16(&dst, MABS(&drcbe->fmodesave)); // fstcw [fmodesave]
emit_fldcw_m16(&dst, MABS(&fp_control[roundp.value])); // fldcw fpcontrol[roundp]
}
-
+
/* general case */
emit_fld_p(&dst, inst->size, &srcp); // fld srcp
-
+
/* 4-byte integer case */
if (sizep.value == DRCUML_SIZE_DWORD)
{
@@ -6492,7 +6492,7 @@ static x86code *op_ftoint(drcbe_state *drcbe, x86code *dst, const drcuml_instruc
emit_mov_r32_m32(&dst, dstp.value, MABS(drcbe->reglo[dstp.value])); // mov dstp,reglo[dstp]
}
}
-
+
/* 8-byte integer case */
else if (sizep.value == DRCUML_SIZE_QWORD)
{
@@ -6552,7 +6552,7 @@ static x86code *op_ffrint(drcbe_state *drcbe, x86code *dst, const drcuml_instruc
emit_fild_m32(&dst, MABS(drcbe->reglo[srcp.value])); // fild reglo[srcp]
}
}
-
+
/* 8-bit integer case */
else if (sizep.value == DRCUML_SIZE_QWORD)
{
diff --git a/src/emu/cpu/drcuml.c b/src/emu/cpu/drcuml.c
index a6a3c0609af..d16d0cbaddd 100644
--- a/src/emu/cpu/drcuml.c
+++ b/src/emu/cpu/drcuml.c
@@ -12,11 +12,11 @@
Future improvements/changes:
- * UML optimizer:
- - detects constant operations, converts to MOV
- - eliminates no-ops (add i0,i0,0)
- - determines flags automatically
- - constant folding
+ * UML optimizer:
+ - detects constant operations, converts to MOV
+ - eliminates no-ops (add i0,i0,0)
+ - determines flags automatically
+ - constant folding
* Write a back-end validator:
- checks all combinations of memory/register/immediate on all params
diff --git a/src/emu/cpu/drcumld.c b/src/emu/cpu/drcumld.c
index d64d50be1e2..5f034b761a3 100644
--- a/src/emu/cpu/drcumld.c
+++ b/src/emu/cpu/drcumld.c
@@ -456,7 +456,7 @@ static char *output_param_space_size(char *dest, int size, const drcuml_paramete
dest += sprintf(dest, "%s_", address_space_names[param->value / 16]);
return output_param_size(dest, size, param);
}
-
+
return output_param(dest, size, param);
}
diff --git a/src/emu/cpu/minx/minxops.h b/src/emu/cpu/minx/minxops.h
index 063e16dd22c..39ccf201c1a 100644
--- a/src/emu/cpu/minx/minxops.h
+++ b/src/emu/cpu/minx/minxops.h
@@ -314,7 +314,7 @@ static const int insnminx_cycles[256] = {
8, 8, 8, 8, 12, 16, 8, 8, 8, 8, 8, 8, 12, 16, 8, 8,
8, 8, 8, 8, 12, 16, 8, 8, 8, 8, 8, 8, 12, 16, 8, 8,
8, 8, 8, 8, 12, 16, 8, 8, 8, 8, 8, 8, 12, 16, 8, 8,
-
+
4, 4, 4, 4, 12, 8, 8, 8, 4, 4, 4, 4, 12, 8, 8, 8,
4, 4, 4, 4, 12, 8, 8, 8, 4, 4, 4, 4, 12, 8, 8, 8,
8, 8, 8, 8, 16, 12, 12, 12, 8, 8, 8, 8, 16, 12, 12, 12,
diff --git a/src/emu/cpu/powerpc/ppc.h b/src/emu/cpu/powerpc/ppc.h
index 161ac2dbd92..0b712cd58b8 100644
--- a/src/emu/cpu/powerpc/ppc.h
+++ b/src/emu/cpu/powerpc/ppc.h
@@ -16,7 +16,7 @@
REGISTER ENUMERATION
***************************************************************************/
-enum
+enum
{
PPC_PC = 1,
PPC_R0,
@@ -87,14 +87,14 @@ enum
CPUINFO_INT_PPC_HOTSPOT_PC,
CPUINFO_INT_PPC_HOTSPOT_OPCODE,
CPUINFO_INT_PPC_HOTSPOT_CYCLES,
-
+
CPUINFO_INT_PPC_RX_DATA,
CPUINFO_PTR_PPC_FASTRAM_BASE = CPUINFO_PTR_CPU_SPECIFIC,
CPUINFO_PTR_SPU_RX_HANDLER,
CPUINFO_PTR_SPU_TX_HANDLER,
-
+
CPUINFO_PTR_CONTEXT /* temporary */
};
diff --git a/src/emu/cpu/powerpc/ppc_dasm.c b/src/emu/cpu/powerpc/ppc_dasm.c
index ae81392f268..d5ff1c4ebf5 100644
--- a/src/emu/cpu/powerpc/ppc_dasm.c
+++ b/src/emu/cpu/powerpc/ppc_dasm.c
@@ -425,9 +425,9 @@ static void SPR(char *dest, int spr_field)
case SPR4XX_PID: strcat(dest, "pid"); break;
case SPR4XX_TBHU: strcat(dest, "tbhu"); break;
case SPR4XX_TBLU: strcat(dest, "tblu"); break;
-// case SPR4XX_ICDBDR: strcat(dest, "icdbdr"); break; // same as SPR603E_HASH2
-// case SPR4XX_DEAR: strcat(dest, "dear"); break; // same as SPR603E_ICMP
-// case SPR4XX_EVPR: strcat(dest, "evpr"); break; // same as SPR603E_RPA
+// case SPR4XX_ICDBDR: strcat(dest, "icdbdr"); break; // same as SPR603E_HASH2
+// case SPR4XX_DEAR: strcat(dest, "dear"); break; // same as SPR603E_ICMP
+// case SPR4XX_EVPR: strcat(dest, "evpr"); break; // same as SPR603E_RPA
case SPR4XX_CDBCR: strcat(dest, "cdbcr"); break;
case SPR4XX_TSR: strcat(dest, "tsr"); break;
case SPR4XX_TCR: strcat(dest, "tcr"); break;
@@ -436,10 +436,10 @@ static void SPR(char *dest, int spr_field)
case SPR4XX_TBLO: strcat(dest, "tblo"); break;
case SPR4XX_SRR2: strcat(dest, "srr2"); break;
case SPR4XX_SRR3: strcat(dest, "srr3"); break;
-// case SPR4XX_DBSR: strcat(dest, "dbsr"); break; // same as SPR603E_HID0
-// case SPR4XX_DBCR: strcat(dest, "dbcr"); break; // same as SPR603E_IABR
+// case SPR4XX_DBSR: strcat(dest, "dbsr"); break; // same as SPR603E_HID0
+// case SPR4XX_DBCR: strcat(dest, "dbcr"); break; // same as SPR603E_IABR
case SPR4XX_IAC1: strcat(dest, "iac1"); break;
-// case SPR4XX_IAC2: strcat(dest, "iac2"); break; // same as SPROEA_DABR
+// case SPR4XX_IAC2: strcat(dest, "iac2"); break; // same as SPROEA_DABR
case SPR4XX_DAC1: strcat(dest, "dac1"); break;
case SPR4XX_DAC2: strcat(dest, "dac2"); break;
case SPR4XX_DCCR: strcat(dest, "dccr"); break;
diff --git a/src/emu/cpu/powerpc/ppccom.c b/src/emu/cpu/powerpc/ppccom.c
index 1eadcd33776..428c61260bf 100644
--- a/src/emu/cpu/powerpc/ppccom.c
+++ b/src/emu/cpu/powerpc/ppccom.c
@@ -68,7 +68,7 @@ INLINE int page_access_allowed(int transtype, UINT8 key, UINT8 protbits)
INLINE void tlb_entry_free(powerpc_state *ppc, int entrynum)
{
int oldentry = ppc->tlb_entries[entrynum];
-
+
/* if we're mapped to something, free the entry in the table */
if (oldentry != 0)
{
@@ -94,13 +94,13 @@ INLINE int tlb_entry_allocate(powerpc_state *ppc, int entrynum, offs_t address,
{
/* if there's already a TLB entry at the current index, zap it */
tlb_entry_free(ppc, entrynum);
-
+
/* allocate a new entry and advance to the next one */
ppc->tlb_entries[entrynum] = (address >> 12) + 1;
allocated = TRUE;
}
*entry = value;
-
+
return allocated;
}
@@ -127,7 +127,7 @@ INLINE void set_timebase(powerpc_state *ppc, UINT64 newtb)
/*-------------------------------------------------
- get_decremeter - return the current
+ get_decremeter - return the current
decrementer value
-------------------------------------------------*/
@@ -199,7 +199,7 @@ size_t ppccom_init(powerpc_state *ppc, powerpc_flavor flavor, UINT8 cap, int tb_
/* allocate a timer for the compare interrupt */
if (cap & PPCCAP_OEA)
ppc->decrementer_int_timer = timer_alloc(decrementer_int_callback, ppc);
-
+
/* and for the 4XX interrupts if needed */
if (cap & PPCCAP_4XX)
{
@@ -207,7 +207,7 @@ size_t ppccom_init(powerpc_state *ppc, powerpc_flavor flavor, UINT8 cap, int tb_
ppc->pit_timer = timer_alloc(ppc4xx_pit_callback, ppc);
ppc->spu.timer = timer_alloc(ppc4xx_spu_callback, ppc);
}
-
+
/* reset the state */
ppccom_reset(ppc);
return 0;
@@ -227,30 +227,30 @@ void ppccom_reset(powerpc_state *ppc)
/* PC to the reset vector; MSR has IP set to start */
ppc->pc = 0xfff00100;
ppc->msr = MSROEA_IP;
-
+
/* reset the decrementer */
ppc->dec_zero_cycles = cpunum_gettotalcycles(ppc->cpunum);
decrementer_int_callback(Machine, ppc, 0);
}
-
+
/* initialize the 4XX state */
if (ppc->cap & PPCCAP_4XX)
{
/* PC to the last word; MSR to 0 */
ppc->pc = 0xfffffffc;
ppc->msr = 0;
-
+
/* reset the SPU status */
ppc->spr[SPR4XX_TCR] &= ~PPC4XX_TCR_WRC_MASK;
ppc->spu.regs[SPU4XX_LINE_STATUS] = 0x06;
}
-
+
/* time base starts here */
ppc->tb_zero_cycles = cpunum_gettotalcycles(ppc->cpunum);
/* clear interrupts */
ppc->irq_pending = 0;
-
+
/* flush the TLB */
ppc->tlb_index = 0;
memset(ppc->tlb_entries, 0, sizeof(ppc->tlb_entries[0]) * (POWERPC_TLB_ENTRIES + PPC603_FIXED_TLB_ENTRIES));
@@ -280,7 +280,7 @@ offs_t ppccom_dasm(powerpc_state *ppc, char *buffer, offs_t pc, const UINT8 *opr
***************************************************************************/
/*-------------------------------------------------
- ppccom_translate_address_internal - translate
+ ppccom_translate_address_internal - translate
an address from logical to physical; shared
between external requests and internal TLB
filling
@@ -297,22 +297,22 @@ static UINT32 ppccom_translate_address_internal(powerpc_state *ppc, int intentio
/* only applies if we support the OEA */
if (!(ppc->cap & PPCCAP_OEA))
return 0x001;
-
+
/* also no translation necessary if translation is disabled */
if ((transtype == TRANSLATE_FETCH && (ppc->msr & MSROEA_IR) == 0) || (transtype != TRANSLATE_FETCH && (ppc->msr & MSROEA_DR) == 0))
return 0x001;
-
+
/* first scan the appropriate BAT */
batbase = (transtype == TRANSLATE_FETCH) ? SPROEA_IBAT0U : SPROEA_DBAT0U;
for (batnum = 0; batnum < 4; batnum++)
{
UINT32 upper = ppc->spr[batbase + 2*batnum + 0];
-
+
/* check user/supervisor valid bit */
if ((upper >> transpriv) & 0x01)
{
UINT32 mask = (~upper << 15) & 0xfffe0000;
-
+
/* check for a hit against this bucket */
if ((*address & mask) == (upper & mask))
{
@@ -321,24 +321,24 @@ static UINT32 ppccom_translate_address_internal(powerpc_state *ppc, int intentio
/* verify protection; if we fail, return false and indicate a protection violation */
if (!page_access_allowed(transtype, 1, lower & 3))
return DSISR_PROTECTED | ((transtype == TRANSLATE_WRITE) ? DSISR_STORE : 0);
-
+
/* otherwise we're good */
*address = (lower & mask) | (*address & ~mask);
return 0x001;
}
}
}
-
+
/* look up the segment register */
segreg = ppc->sr[*address >> 28];
if (transtype == TRANSLATE_FETCH && (segreg & 0x10000000))
return DSISR_PROTECTED | ((transtype == TRANSLATE_WRITE) ? DSISR_STORE : 0);
-
+
/* get hash table information from SD1 */
hashbase = ppc->spr[SPROEA_SDR1] & 0xffff0000;
hashmask = ((ppc->spr[SPROEA_SDR1] & 0x1ff) << 16) | 0xffff;
hash = (segreg & 0x7ffff) ^ ((*address >> 12) & 0xffff);
-
+
/* if we're simulating the 603 MMU, fill in the data and stop here */
if (ppc->cap & PPCCAP_603_MMU)
{
@@ -353,23 +353,23 @@ static UINT32 ppccom_translate_address_internal(powerpc_state *ppc, int intentio
{
offs_t ptegaddr = hashbase | ((hash << 6) & hashmask);
UINT32 *ptegptr = memory_get_read_ptr(cpu_getactivecpu(), ADDRESS_SPACE_PROGRAM, ptegaddr);
-
+
/* should only have valid memory here, but make sure */
if (ptegptr != NULL)
{
UINT32 targetupper = 0x80000000 | ((segreg & 0xffffff) << 7) | (hashnum << 6) | ((*address >> 22) & 0x3f);
int ptenum;
-
+
/* scan PTEs */
for (ptenum = 0; ptenum < 8; ptenum++)
if (ptegptr[BYTE_XOR_BE(ptenum * 2)] == targetupper)
{
UINT32 pteglower = ptegptr[BYTE_XOR_BE(ptenum * 2 + 1)];
-
+
/* verify protection; if we fail, return false and indicate a protection violation */
if (!page_access_allowed(transtype, (segreg >> (29 + transpriv)) & 1, pteglower & 3))
return DSISR_PROTECTED | ((transtype == TRANSLATE_WRITE) ? DSISR_STORE : 0);
-
+
/* update page table bits */
if (!(intention & TRANSLATE_DEBUG_MASK))
{
@@ -378,21 +378,21 @@ static UINT32 ppccom_translate_address_internal(powerpc_state *ppc, int intentio
pteglower |= 0x080;
ptegptr[BYTE_XOR_BE(ptenum * 2 + 1)] = pteglower;
}
-
+
/* otherwise we're good */
*address = (pteglower & 0xfffff000) | (*address & 0x00000fff);
return (pteglower >> 7) & 1;
}
}
-
+
/* invert the hash after the first round */
hash = ~hash;
}
-
+
/* we failed to find any match: not found */
return DSISR_NOT_FOUND | ((transtype == TRANSLATE_WRITE) ? DSISR_STORE : 0);
-}
-
+}
+
/*-------------------------------------------------
ppccom_translate_address - translate an address
@@ -421,11 +421,11 @@ void ppccom_tlb_fill(powerpc_state *ppc)
int transtype = ppc->param1;
offs_t transaddr = address;
UINT32 entryval;
-
+
/* allow for an implementation-specific override */
if (ppc->tlb_fill != NULL && (*ppc->tlb_fill)(ppc))
return;
-
+
/* if we can't translate the address, just return (and fail) */
ppc->param0 = ppccom_translate_address_internal(ppc, transtype | transuser, &transaddr);
if (PRINTF_TLB_FILL)
@@ -454,7 +454,7 @@ void ppccom_tlb_fill(powerpc_state *ppc)
void ppccom_tlb_flush(powerpc_state *ppc)
{
int entnum;
-
+
/* iterate over entries and invalidate them */
for (entnum = 0; entnum < POWERPC_TLB_ENTRIES; entnum++)
tlb_entry_free(ppc, entnum);
@@ -474,7 +474,7 @@ void ppccom_tlb_flush(powerpc_state *ppc)
void ppccom_execute_tlbie(powerpc_state *ppc)
{
offs_t address = ppc->param0;
-
+
/* just nuke it in the table; we may have spare entries referencing it, but no harm */
ppc->tlb_table[address >> 12] = 0;
}
@@ -501,7 +501,7 @@ void ppccom_execute_tlbl(powerpc_state *ppc)
UINT32 address = ppc->param0;
int isitlb = ppc->param1;
UINT32 entrynum, entryval;
-
+
/* determine entry number; we use rand() for associativity */
entrynum = ((address >> 12) & 0x1f) | (mame_rand(Machine) & 0x20) | (isitlb ? 0x40 : 0);
@@ -574,14 +574,14 @@ void ppccom_execute_mfspr(powerpc_state *ppc)
case SPROEA_DABR:
ppc->param1 = ppc->spr[ppc->param0];
return;
-
+
/* decrementer */
case SPROEA_DEC:
ppc->param1 = get_decrementer(ppc);
return;
}
}
-
+
/* handle 603 SPRs */
if (ppc->cap & PPCCAP_603_MMU)
{
@@ -611,7 +611,7 @@ void ppccom_execute_mfspr(powerpc_state *ppc)
return;
}
}
-
+
/* handle 4XX SPRs */
if (ppc->cap & PPCCAP_4XX)
{
@@ -692,14 +692,14 @@ void ppccom_execute_mtspr(powerpc_state *ppc)
ppc->spr[ppc->param0] = ppc->param1;
ppccom_tlb_flush(ppc);
return;
-
+
/* decrementer */
case SPROEA_DEC:
set_decrementer(ppc, ppc->param1);
return;
}
}
-
+
/* handle 603 SPRs */
if (ppc->cap & PPCCAP_603_MMU)
{
@@ -722,7 +722,7 @@ void ppccom_execute_mtspr(powerpc_state *ppc)
case SPR603_HID2:
ppc->spr[ppc->param0] = ppc->param1;
return;
-
+
/* timebase */
case SPR603_TBL_W:
set_timebase(ppc, (get_timebase(ppc) & ~U64(0xffffffff00000000)) | ppc->param1);
@@ -732,7 +732,7 @@ void ppccom_execute_mtspr(powerpc_state *ppc)
return;
}
}
-
+
/* handle 4XX SPRs */
if (ppc->cap & PPCCAP_4XX)
{
@@ -750,7 +750,7 @@ void ppccom_execute_mtspr(powerpc_state *ppc)
case SPR4XX_SRR3:
ppc->spr[ppc->param0] = ppc->param1;
return;
-
+
/* timer control register */
case SPR4XX_TCR:
ppc->spr[SPR4XX_TCR] = ppc->param1 | (oldval & PPC4XX_TCR_WRC_MASK);
@@ -759,20 +759,20 @@ void ppccom_execute_mtspr(powerpc_state *ppc)
if ((oldval ^ ppc->spr[SPR4XX_TCR]) & PPC4XX_TCR_PIE)
ppc4xx_pit_callback(Machine, ppc, FALSE);
return;
-
+
/* timer status register */
case SPR4XX_TSR:
ppc->spr[SPR4XX_TSR] &= ~ppc->param1;
ppc4xx_set_irq_line(ppc, 0, 0);
return;
-
+
/* PIT */
case SPR4XX_PIT:
ppc->spr[SPR4XX_PIT] = ppc->param1;
ppc->pit_reload = ppc->param1;
ppc4xx_pit_callback(Machine, ppc, FALSE);
return;
-
+
/* timebase */
case SPR4XX_TBLO:
set_timebase(ppc, (get_timebase(ppc) & ~U64(0x00ffffff00000000)) | ppc->param1);
@@ -850,7 +850,7 @@ void ppccom_execute_mfdcr(powerpc_state *ppc)
void ppccom_execute_mtdcr(powerpc_state *ppc)
{
UINT8 oldval;
-
+
/* handle various DCRs */
switch (ppc->param0)
{
@@ -882,25 +882,25 @@ void ppccom_execute_mtdcr(powerpc_state *ppc)
case DCR4XX_DMACC3:
ppc->dcr[ppc->param0] = ppc->param1;
return;
-
+
/* DMA status */
case DCR4XX_DMASR:
ppc->dcr[DCR4XX_DMASR] &= ~(ppc->param1 & 0xfff80070);
ppc4xx_dma_update_irq_states(ppc);
return;
-
+
/* interrupt enables */
case DCR4XX_EXIER:
ppc->dcr[DCR4XX_EXIER] = ppc->param1;
ppc4xx_set_irq_line(ppc, 0, 0);
return;
-
+
/* interrupt clear */
case DCR4XX_EXISR:
ppc->dcr[ppc->param0] &= ~ppc->param1;
ppc4xx_set_irq_line(ppc, 0, 0);
return;
-
+
/* DMA controls */
case DCR4XX_DMACR0:
case DCR4XX_DMACR1:
@@ -1207,11 +1207,11 @@ static void ppc4xx_set_irq_line(powerpc_state *ppc, UINT32 bitmask, int state)
ppc->irqstate |= bitmask;
else
ppc->irqstate &= ~bitmask;
-
+
/* if the state changed to on, edge trigger the interrupt */
if (((ppc->irqstate ^ oldstate) & bitmask) && (ppc->irqstate & bitmask))
ppc->dcr[DCR4XX_EXISR] |= bitmask;
-
+
/* pass through all level-triggered interrupts */
levelmask = PPC4XX_IRQ_BIT_CRITICAL | PPC4XX_IRQ_BIT_SPUR | PPC4XX_IRQ_BIT_SPUT;
levelmask |= PPC4XX_IRQ_BIT_JTAGR | PPC4XX_IRQ_BIT_JTAGT;
@@ -1222,7 +1222,7 @@ static void ppc4xx_set_irq_line(powerpc_state *ppc, UINT32 bitmask, int state)
if (!(ppc->dcr[DCR4XX_IOCR] & 0x02000000)) levelmask |= PPC4XX_IRQ_BIT_EXT3;
if (!(ppc->dcr[DCR4XX_IOCR] & 0x00800000)) levelmask |= PPC4XX_IRQ_BIT_EXT4;
ppc->dcr[DCR4XX_EXISR] = (ppc->dcr[DCR4XX_EXISR] & ~levelmask) | (ppc->irqstate & levelmask);
-
+
/* update the IRQ status */
ppc->irq_pending = ((ppc->dcr[DCR4XX_EXISR] & ppc->dcr[DCR4XX_EXIER]) != 0);
if ((ppc->spr[SPR4XX_TCR] & PPC4XX_TCR_FIE) && (ppc->spr[SPR4XX_TSR] & PPC4XX_TSR_FIS))
@@ -1251,7 +1251,7 @@ static int ppc4xx_get_irq_line(powerpc_state *ppc, UINT32 bitmask)
static void ppc4xx_dma_update_irq_states(powerpc_state *ppc)
{
int dmachan;
-
+
/* update the IRQ state for each DMA channel */
for (dmachan = 0; dmachan < 4; dmachan++)
if ((ppc->dcr[DCR4XX_DMACR0 + 8 * dmachan] & PPC4XX_DMACR_CIE) && (ppc->dcr[DCR4XX_DMASR] & (1 << (27 - dmachan))))
@@ -1273,11 +1273,11 @@ static int ppc4xx_dma_decrement_count(powerpc_state *ppc, int dmachan)
/* decrement the counter */
dmaregs[DCR4XX_DMACT0]--;
-
+
/* if non-zero, we keep going */
if ((dmaregs[DCR4XX_DMACT0] & 0xffff) != 0)
return FALSE;
-
+
/* set the complete bit and handle interrupts */
ppc->dcr[DCR4XX_DMASR] |= 1 << (27 - dmachan);
ppc4xx_dma_update_irq_states(ppc);
@@ -1297,11 +1297,11 @@ static int ppc4xx_dma_fetch_transmit_byte(powerpc_state *ppc, int dmachan, UINT8
/* if the channel is not enabled, fail */
if (!(dmaregs[DCR4XX_DMACR0] & PPC4XX_DMACR_CE))
return FALSE;
-
+
/* if no transfers remaining, fail */
if ((dmaregs[DCR4XX_DMACT0] & 0xffff) == 0)
return FALSE;
-
+
/* fetch the data */
cpuintrf_push_context(ppc->cpunum);
*byte = program_read_byte(dmaregs[DCR4XX_DMADA0]++);
@@ -1323,11 +1323,11 @@ static int ppc4xx_dma_handle_receive_byte(powerpc_state *ppc, int dmachan, UINT8
/* if the channel is not enabled, fail */
if (!(dmaregs[DCR4XX_DMACR0] & PPC4XX_DMACR_CE))
return FALSE;
-
+
/* if no transfers remaining, fail */
if ((dmaregs[DCR4XX_DMACT0] & 0xffff) == 0)
return FALSE;
-
+
/* store the data */
cpuintrf_push_context(ppc->cpunum);
program_write_byte(dmaregs[DCR4XX_DMADA0]++, byte);
@@ -1348,7 +1348,7 @@ static void ppc4xx_dma_exec(powerpc_state *ppc, int dmachan)
UINT32 *dmaregs = &ppc->dcr[8 * dmachan];
INT32 destinc, srcinc;
UINT8 width;
-
+
/* skip if not enabled */
if (!(dmaregs[DCR4XX_DMACR0] & PPC4XX_DMACR_CE))
return;
@@ -1438,14 +1438,14 @@ static void ppc4xx_dma_exec(powerpc_state *ppc, int dmachan)
static TIMER_CALLBACK( ppc4xx_fit_callback )
{
powerpc_state *ppc = ptr;
-
+
/* if this is a real callback and we are enabled, signal an interrupt */
if (param)
{
ppc->spr[SPR4XX_TSR] |= PPC4XX_TSR_FIS;
ppc4xx_set_irq_line(ppc, 0, 0);
}
-
+
/* update ourself for the next interval if we are enabled */
if (ppc->spr[SPR4XX_TCR] & PPC4XX_TCR_FIE)
{
@@ -1454,7 +1454,7 @@ static TIMER_CALLBACK( ppc4xx_fit_callback )
UINT32 target = (timebase + interval) & ~(interval - 1);
timer_adjust_oneshot(ppc->fit_timer, ATTOTIME_IN_CYCLES((target + 1 - timebase) / ppc->tb_divisor, ppc->cpunum), TRUE);
}
-
+
/* otherwise, turn ourself off */
else
timer_adjust_oneshot(ppc->fit_timer, attotime_never, FALSE);
@@ -1468,16 +1468,16 @@ static TIMER_CALLBACK( ppc4xx_fit_callback )
static TIMER_CALLBACK( ppc4xx_pit_callback )
{
powerpc_state *ppc = ptr;
-
+
/* if this is a real callback and we are enabled, signal an interrupt */
if (param)
{
ppc->spr[SPR4XX_TSR] |= PPC4XX_TSR_PIS;
ppc4xx_set_irq_line(ppc, 0, 0);
}
-
+
/* update ourself for the next interval if we are enabled and we are either being
- forced to update, or we are in auto-reload mode */
+ forced to update, or we are in auto-reload mode */
if ((ppc->spr[SPR4XX_TCR] & PPC4XX_TCR_PIE) && ppc->pit_reload != 0 && (!param || (ppc->spr[SPR4XX_TCR] & PPC4XX_TCR_ARE)))
{
UINT32 timebase = get_timebase(ppc);
@@ -1485,7 +1485,7 @@ static TIMER_CALLBACK( ppc4xx_pit_callback )
UINT32 target = timebase + interval;
timer_adjust_oneshot(ppc->pit_timer, ATTOTIME_IN_CYCLES((target + 1 - timebase) / ppc->tb_divisor, ppc->cpunum), TRUE);
}
-
+
/* otherwise, turn ourself off */
else
timer_adjust_oneshot(ppc->pit_timer, attotime_never, FALSE);
@@ -1543,7 +1543,7 @@ static void ppc4xx_spu_rx_data(powerpc_state *ppc, UINT8 data)
static void ppc4xx_spu_timer_reset(powerpc_state *ppc)
{
UINT8 enabled = (ppc->spu.regs[SPU4XX_RX_COMMAND] | ppc->spu.regs[SPU4XX_TX_COMMAND]) & 0x80;
-
+
/* if we're enabled, reset at the current baud rate */
if (enabled)
{
@@ -1555,7 +1555,7 @@ static void ppc4xx_spu_timer_reset(powerpc_state *ppc)
if (PRINTF_SPU)
mame_printf_debug("ppc4xx_spu_timer_reset: baud rate = %.0f\n", ATTOSECONDS_TO_HZ(charperiod.attoseconds) * bpc);
}
-
+
/* otherwise, disable the timer */
else
timer_adjust_oneshot(ppc->spu.timer, attotime_never, 0);
@@ -1571,7 +1571,7 @@ static TIMER_CALLBACK( ppc4xx_spu_callback )
{
powerpc_state *ppc = ptr;
UINT8 rxbyte;
-
+
/* transmit enabled? */
if (ppc->spu.regs[SPU4XX_TX_COMMAND] & 0x80)
{
@@ -1583,12 +1583,12 @@ static TIMER_CALLBACK( ppc4xx_spu_callback )
/* if we have a transmit handler, send it that way */
if (ppc->spu.tx_handler != NULL)
(*ppc->spu.tx_handler)(ppc->spu.txbuf);
-
+
/* indicate that we have moved it to the shift register */
ppc->spu.regs[SPU4XX_LINE_STATUS] |= 0x04;
ppc->spu.regs[SPU4XX_LINE_STATUS] &= ~0x02;
}
-
+
/* otherwise, clear the shift register */
else if (!(ppc->spu.regs[SPU4XX_LINE_STATUS] & 0x02))
ppc->spu.regs[SPU4XX_LINE_STATUS] |= 0x02;
@@ -1610,7 +1610,7 @@ static TIMER_CALLBACK( ppc4xx_spu_callback )
ppc->spu.rxbuf = rxbyte;
ppc->spu.regs[SPU4XX_LINE_STATUS] |= 0x80;
}
-
+
/* otherwise signal an overrun */
else
{
@@ -1637,14 +1637,14 @@ static READ8_HANDLER( ppc4xx_spu_r )
{
powerpc_state *ppc = activecpu_get_info_ptr(CPUINFO_PTR_CONTEXT);
UINT8 result = 0xff;
-
+
switch (offset)
{
case SPU4XX_BUFFER:
result = ppc->spu.rxbuf;
ppc->spu.regs[SPU4XX_LINE_STATUS] &= ~0x80;
break;
-
+
default:
if (offset < ARRAY_LENGTH(ppc->spu.regs))
result = ppc->spu.regs[offset];
@@ -1664,7 +1664,7 @@ static WRITE8_HANDLER( ppc4xx_spu_w )
{
powerpc_state *ppc = activecpu_get_info_ptr(CPUINFO_PTR_CONTEXT);
UINT8 oldstate, newstate;
-
+
if (PRINTF_SPU)
mame_printf_debug("spu_w(%d) = %02X\n", offset, data);
switch (offset)
@@ -1685,7 +1685,7 @@ static WRITE8_HANDLER( ppc4xx_spu_w )
ppc4xx_spu_timer_reset(ppc);
ppc4xx_spu_update_irq_states(ppc);
break;
-
+
/* if the divisor changes, we need to update the timer */
case SPU4XX_BAUD_DIVISOR_H:
case SPU4XX_BAUD_DIVISOR_L:
@@ -1695,7 +1695,7 @@ static WRITE8_HANDLER( ppc4xx_spu_w )
ppc4xx_spu_timer_reset(ppc);
}
break;
-
+
/* if the number of data bits or stop bits changes, we need to update the timer */
case SPU4XX_CONTROL:
oldstate = ppc->spu.regs[offset];
@@ -1711,7 +1711,7 @@ static WRITE8_HANDLER( ppc4xx_spu_w )
ppc->spu.txbuf = data;
ppc->spu.regs[SPU4XX_LINE_STATUS] &= ~0x04;
break;
-
+
default:
if (offset < ARRAY_LENGTH(ppc->spu.regs))
ppc->spu.regs[offset] = data;
diff --git a/src/emu/cpu/powerpc/ppccom.h b/src/emu/cpu/powerpc/ppccom.h
index 9f78534c559..4a5c51b55ba 100644
--- a/src/emu/cpu/powerpc/ppccom.h
+++ b/src/emu/cpu/powerpc/ppccom.h
@@ -529,7 +529,7 @@ struct _powerpc_state
UINT32 sr[16];
UINT32 spr[1024];
UINT32 dcr[256];
-
+
/* parameters for calls */
UINT32 param0;
UINT32 param1;
@@ -555,7 +555,7 @@ struct _powerpc_state
emu_timer * wdog_timer;
UINT32 pit_reload;
UINT32 irqstate;
-
+
/* PowerPC 603-specific state */
UINT32 mmu603_cmp;
UINT32 mmu603_hash[2];
@@ -570,7 +570,7 @@ struct _powerpc_state
UINT64 tb_zero_cycles;
UINT64 dec_zero_cycles;
emu_timer * decrementer_int_timer;
-
+
/* for use by specific implementations */
ppcimp_state * impstate;
};
diff --git a/src/emu/cpu/powerpc/ppcdrc.c b/src/emu/cpu/powerpc/ppcdrc.c
index 45afbbd3e67..19e404b1b5f 100644
--- a/src/emu/cpu/powerpc/ppcdrc.c
+++ b/src/emu/cpu/powerpc/ppcdrc.c
@@ -12,10 +12,10 @@
Future improvements/changes:
- * Timing for long instructions (stmw/lmw/mul/div/stswi)
+ * Timing for long instructions (stmw/lmw/mul/div/stswi)
- * Eliminate unnecessary flag calculations using information from the
- frontend
+ * Eliminate unnecessary flag calculations using information from the
+ frontend
***************************************************************************/
@@ -114,7 +114,7 @@ extern offs_t ppc_dasm_one(char *buffer, UINT32 pc, UINT32 op);
((((op) >> (31- 4)) & 0x0f) << (31-21)) | /* bits 18-21: opcode bits 1-4 */ \
((((op) >> (31-10)) & 0x1f) << (31-26)) | /* bits 22-26: opcode bits 6-10 */ \
((((op) >> (31-15)) & 0x1f) << (31-31))) /* bits 27-31: opcode bits 11-15 */
-
+
#define DSISR_IDX(op) (((((op) >> (31-30)) & 0x03) << (31-16)) | /* bits 15-16: opcode bits 29-30 */ \
((((op) >> (31-25)) & 0x01) << (31-17)) | /* bit 17: opcode bit 25 */ \
((((op) >> (31-24)) & 0x0f) << (31-21)) | /* bits 18-21: opcode bits 21-24 */ \
@@ -195,7 +195,7 @@ struct _ppcimp_state
/* internal stuff */
UINT8 cache_dirty; /* true if we need to flush the cache */
-
+
/* register mappings */
drcuml_parameter regmap[32]; /* parameter to register mappings for all 32 integer registers */
drcuml_parameter fsregmap[32]; /* parameter to register mappings for all 32 floating point registers */
@@ -462,7 +462,7 @@ INLINE void alloc_handle(drcuml_state *drcuml, drcuml_codehandle **handleptr, co
INLINE void load_fast_iregs(drcuml_block *block)
{
int regnum;
-
+
for (regnum = 0; regnum < ARRAY_LENGTH(ppc->impstate->regmap); regnum++)
if (ppc->impstate->regmap[regnum].type == DRCUML_PTYPE_INT_REGISTER)
UML_MOV(block, IREG(ppc->impstate->regmap[regnum].value - DRCUML_REG_I0), MEM(&ppc->r[regnum]));
@@ -477,7 +477,7 @@ INLINE void load_fast_iregs(drcuml_block *block)
INLINE void save_fast_iregs(drcuml_block *block)
{
int regnum;
-
+
for (regnum = 0; regnum < ARRAY_LENGTH(ppc->impstate->regmap); regnum++)
if (ppc->impstate->regmap[regnum].type == DRCUML_PTYPE_INT_REGISTER)
UML_MOV(block, MEM(&ppc->r[regnum]), IREG(ppc->impstate->regmap[regnum].value - DRCUML_REG_I0));
@@ -826,7 +826,7 @@ static void ppcdrc_get_info(UINT32 state, cpuinfo *info)
static void code_flush_cache(drcuml_state *drcuml)
{
int mode;
-
+
/* empty the transient cache contents */
drcuml_reset(drcuml);
@@ -1039,7 +1039,7 @@ static void cfunc_printf_probe(void *param)
/*-------------------------------------------------
- cfunc_unimplemented - handler for
+ cfunc_unimplemented - handler for
unimplemented opcdes
-------------------------------------------------*/
@@ -1084,7 +1084,7 @@ static void static_generate_entry_point(drcuml_state *drcuml)
UML_AND(block, IREG(0), FPSCR32, IMM(3)); // and i0,fpscr,3
UML_LOAD(block, IREG(0), &ppc->impstate->fpmode[0], IREG(0), BYTE); // load i0,fpmode,i0,byte
UML_SETFMOD(block, IREG(0)); // setfmod i0
-
+
/* load fast integer registers */
load_fast_iregs(block); // <load fastregs>
@@ -1253,19 +1253,19 @@ static void static_generate_exception(drcuml_state *drcuml, UINT8 exception, int
UML_RECOVER(block, IREG(0), MAPVAR_PC); // recover i0,PC
UML_RECOVER(block, IREG(1), MAPVAR_CYCLES); // recover i1,CYCLES
}
-
+
/* OEA handling of SRR exceptions */
if (ppc->cap & PPCCAP_OEA)
{
UINT32 msrandmask = MSROEA_POW | MSR_EE | MSR_PR | MSROEA_FP | MSROEA_FE0 | MSROEA_SE | MSROEA_BE | MSROEA_FE1 | MSROEA_IR | MSROEA_DR | MSROEA_RI | MSR_LE;
UINT32 msrormask = 0;
-
+
/* check registers to see the real source of our exception (EI exceptions only) */
UML_MOV(block, IREG(3), IMM(vector)); // mov i3,vector
if (exception == EXCEPTION_EI)
{
drcuml_codelabel not_decrementer;
-
+
UML_TEST(block, MEM(&ppc->irq_pending), IMM(0x01)); // test [irq_pending],0x01
UML_JMPc(block, IF_NZ, not_decrementer = label++); // jmp not_decrementer,nz
UML_MOV(block, IREG(3), IMM(EXCEPTION_DECREMENT << 8)); // mov i3,EXCEPTION_DECREMENT << 8
@@ -1320,7 +1320,7 @@ static void static_generate_exception(drcuml_state *drcuml, UINT8 exception, int
UML_MOVc(block, IF_NZ, IREG(0), IMM(0xfff00000)); // mov i0,0xfff00000,nz
UML_OR(block, IREG(0), IREG(0), IREG(3)); // or i0,i0,i3
}
-
+
/* 4XX handling of exceptions */
if (ppc->cap & PPCCAP_4XX)
{
@@ -1329,7 +1329,7 @@ static void static_generate_exception(drcuml_state *drcuml, UINT8 exception, int
if (exception == EXCEPTION_EI)
{
drcuml_codelabel notwdog, common;
-
+
UML_TEST(block, SPR32(SPR4XX_TSR), IMM(PPC4XX_TSR_PIS)); // test [tsr],PIS
UML_MOVc(block, IF_NZ, IREG(3), IMM(0x1000)); // mov i3,0x1000,NZ
UML_TEST(block, SPR32(SPR4XX_TSR), IMM(PPC4XX_TSR_FIS)); // test [tsr],FIS
@@ -1345,7 +1345,7 @@ static void static_generate_exception(drcuml_state *drcuml, UINT8 exception, int
UML_MOV(block, SPR32(SPR4XX_SRR3), MSR32); // mov [srr3],[msr]
UML_AND(block, IREG(2), MSR32, IMM(~(MSR4XX_WE | MSR_PR | MSR4XX_CE | MSR_EE | MSR4XX_DE | MSR4XX_PE)));
UML_JMP(block, common = label++); // jmp common
-
+
/* exception PC goes into SRR0, MSR goes to SRR1 */
UML_LABEL(block, notwdog); // notwdog:
UML_MOV(block, SPR32(SPR4XX_SRR0), IREG(0)); // mov [srr0],i0
@@ -1360,7 +1360,7 @@ static void static_generate_exception(drcuml_state *drcuml, UINT8 exception, int
UML_MOV(block, SPR32(SPR4XX_SRR1), MSR32); // mov [srr1],[msr]
UML_AND(block, IREG(2), MSR32, IMM(~(MSR4XX_WE | MSR_PR | MSR_EE | MSR4XX_PE)));// and i2,[msr],~(bunch-o-flags)
}
-
+
/* finish updating MSR */
UML_ROLINS(block, IREG(2), IREG(2), IMM(16), IMM(MSR_LE)); // rolins i2,u2,16,MSR_LE
UML_MOV(block, MSR32, IREG(2)); // mov [msr],i2
@@ -1372,7 +1372,7 @@ static void static_generate_exception(drcuml_state *drcuml, UINT8 exception, int
UML_GETEXP(block, IREG(1)); // getexp i1
UML_SHL(block, SPR32(SPR4XX_ESR), IREG(1), IMM(8)); // shl [esr],i1,8
}
-
+
/* determine our target PC */
UML_ROLINS(block, IREG(3), SPR32(SPR4XX_EVPR), IMM(0), IMM(0xffff0000)); // rolins i3,[evpr],0,0xffff0000
UML_MOV(block, IREG(0), IREG(3)); // mov i0,i3
@@ -1424,7 +1424,7 @@ static void static_generate_memory_accessor(drcuml_state *drcuml, int mode, int
/* add a global entry for this */
alloc_handle(drcuml, handleptr, name);
UML_HANDLE(block, *handleptr); // handle *handleptr
-
+
/* check for unaligned accesses and break into two */
if (!ismasked && size != 1)
{
@@ -1434,7 +1434,7 @@ static void static_generate_memory_accessor(drcuml_state *drcuml, int mode, int
UML_TEST(block, IREG(0), IMM(size - 1)); // test i0,size-1
UML_JMPc(block, IF_NZ, alignex = label++); // jmp alignex,nz
}
-
+
/* in big-endian mode, it's more complicated */
else
{
@@ -1444,7 +1444,7 @@ static void static_generate_memory_accessor(drcuml_state *drcuml, int mode, int
UML_TEST(block, IREG(0), IMM(3)); // test i0,3
UML_JMPc(block, IF_NZ, alignex = label++); // jmp alignex,nz
}
-
+
/* unaligned 2 and 4 byte accesses need to be broken up */
else
{
@@ -1453,7 +1453,7 @@ static void static_generate_memory_accessor(drcuml_state *drcuml, int mode, int
}
}
}
-
+
/* general case: assume paging and perform a translation */
if ((ppc->cap & PPCCAP_OEA) && (mode & MODE_DATA_TRANSLATION))
{
@@ -1471,7 +1471,7 @@ static void static_generate_memory_accessor(drcuml_state *drcuml, int mode, int
{
void *fastbase = (UINT8 *)ppc->impstate->fastram[ramnum].base - ppc->impstate->fastram[ramnum].start;
UINT32 skip = label++;
-
+
if (ppc->impstate->fastram[ramnum].end != 0xffffffff)
{
UML_CMP(block, IREG(0), IMM(ppc->impstate->fastram[ramnum].end)); // cmp i0,end
@@ -1732,7 +1732,7 @@ static void static_generate_memory_accessor(drcuml_state *drcuml, int mode, int
}
UML_RET(block); // ret
}
-
+
/* handle an alignment exception */
if (alignex != 0)
{
@@ -1740,12 +1740,12 @@ static void static_generate_memory_accessor(drcuml_state *drcuml, int mode, int
UML_RECOVER(block, SPR32(SPROEA_DSISR), MAPVAR_DSISR); // recover [dsisr],DSISR
UML_EXH(block, ppc->impstate->exception[EXCEPTION_ALIGN], IREG(0)); // exh align,i0
}
-
+
/* handle a TLB miss */
if (tlbmiss != 0)
{
int dsi;
-
+
UML_LABEL(block, tlbmiss); // tlbmiss:
UML_MOV(block, MEM(&ppc->param0), IREG(0)); // mov [param0],i0
UML_MOV(block, MEM(&ppc->param1), IMM(iswrite ? TRANSLATE_WRITE : TRANSLATE_READ)); // mov [param1],TRANSLATE_READ/WRITE
@@ -1962,7 +1962,7 @@ static void generate_sequence_instruction(drcuml_block *block, compiler_state *c
save_fast_iregs(block); // <save fastregs>
UML_DEBUG(block, IMM(desc->pc)); // debug desc->pc
}
-
+
/* if we hit an unmapped address, fatal error */
if (desc->flags & OPFLAG_COMPILER_UNMAPPED)
{
@@ -1981,7 +1981,7 @@ static void generate_sequence_instruction(drcuml_block *block, compiler_state *c
}
UML_EXH(block, ppc->impstate->tlb_mismatch, IMM(0)); // exh tlb_mismatch,0
}
-
+
/* validate our TLB entry at this PC; if we fail, we need to handle it */
if ((desc->flags & OPFLAG_VALIDATE_TLB) && (ppc->impstate->mode & MODE_DATA_TRANSLATION))
{
@@ -1997,7 +1997,7 @@ static void generate_sequence_instruction(drcuml_block *block, compiler_state *c
UML_CMP(block, IREG(0), IMM(ppc->tlb_table[desc->pc >> 12])); // cmp i0,*tlbentry
UML_EXHc(block, IF_NE, ppc->impstate->tlb_mismatch, IMM(0)); // exh tlb_mismatch,0,NE
}
-
+
/* otherwise, we generate an unconditional exception */
else
{
@@ -2013,7 +2013,7 @@ static void generate_sequence_instruction(drcuml_block *block, compiler_state *c
/* if this is an invalid opcode, generate the exception now */
if (desc->flags & OPFLAG_INVALID_OPCODE)
UML_EXH(block, ppc->impstate->exception[EXCEPTION_PROGRAM], IMM(0x80000)); // exh exception_program,0x80000
-
+
/* if this is a privileged opcode in user mode, generate the exception */
else if ((desc->flags & OPFLAG_PRIVILEGED) && (ppc->impstate->mode & MODE_USER))
UML_EXH(block, ppc->impstate->exception[EXCEPTION_PROGRAM], IMM(0x40000)); // exh exception_program,0x40000
@@ -2043,7 +2043,7 @@ static void generate_compute_flags(drcuml_block *block, int updatecr, UINT32 xer
/* easy case: nothing to do */
if (!updatecr && xermask == 0)
return;
-
+
/* semi-easy case: crfield only */
if (xermask == 0)
{
@@ -2056,7 +2056,7 @@ static void generate_compute_flags(drcuml_block *block, int updatecr, UINT32 xer
UML_OR(block, CR32, IREG(0), IREG(1)); // or [cr],i0,i1
return;
}
-
+
/* semi-easy case: xer only */
if (!updatecr)
{
@@ -2078,7 +2078,7 @@ static void generate_compute_flags(drcuml_block *block, int updatecr, UINT32 xer
}
return;
}
-
+
/* tricky case: both */
UML_GETFLGS(block, IREG(0), DRCUML_FLAG_S | DRCUML_FLAG_Z | xerflags); // getflgs i0,sz|xerflags
if (invertcarry)
@@ -2146,7 +2146,7 @@ UML_CALLCc(block, IF_E, cfunc_printf_debug, "b032 @ PC=%08X\n");
static void generate_branch_bo(drcuml_block *block, compiler_state *compiler, const opcode_desc *desc, UINT32 bo, UINT32 bi, int source, int link)
{
int skip = compiler->labelnum++;
-
+
if (!(bo & 0x04))
{
UML_SUBf(block, SPR32(SPR_CTR), SPR32(SPR_CTR), IMM(1), FLAGS_Z); // sub [ctr],[ctr],1,z
@@ -2160,7 +2160,7 @@ static void generate_branch_bo(drcuml_block *block, compiler_state *compiler, co
generate_branch(block, compiler, desc, source, link); // <branch>
UML_LABEL(block, skip); // skip:
}
-
+
/*-------------------------------------------------
generate_opcode - generate code for a specific
@@ -2180,7 +2180,7 @@ static int generate_opcode(drcuml_block *block, compiler_state *compiler, const
case 0x3a: /* 0x3a group - 64-bit only */
case 0x3e: /* 0x3e group - 64-bit only */
return FALSE;
-
+
case 0x03: /* TWI */
UML_CMP(block, R32(G_RA(op)), IMM((INT16)G_SIMM(op))); // cmp ra,simm
if (G_TO(op) & 0x10)
@@ -2194,7 +2194,7 @@ static int generate_opcode(drcuml_block *block, compiler_state *compiler, const
if (G_TO(op) & 0x01)
UML_EXHc(block, IF_A, ppc->impstate->exception[EXCEPTION_PROGRAM], IMM(0x20000));// exh program,0x20000,a
return TRUE;
-
+
case 0x07: /* MULLI */
UML_MULS(block, R32(G_RD(op)), R32(G_RD(op)), R32(G_RA(op)), IMM((INT16)G_SIMM(op)));
// muls rd,rd,ra,simm
@@ -2203,55 +2203,55 @@ static int generate_opcode(drcuml_block *block, compiler_state *compiler, const
case 0x0e: /* ADDI */
UML_ADD(block, R32(G_RD(op)), R32Z(G_RA(op)), IMM((INT16)G_SIMM(op))); // add rd,ra,simm
return TRUE;
-
+
case 0x0f: /* ADDIS */
UML_ADD(block, R32(G_RD(op)), R32Z(G_RA(op)), IMM(G_SIMM(op) << 16)); // add rd,ra,simm << 16
return TRUE;
-
+
case 0x0a: /* CMPLI */
UML_CMP(block, R32(G_RA(op)), IMM(G_UIMM(op))); // cmp ra,uimm
UML_GETFLGS(block, IREG(0), DRCUML_FLAG_Z | DRCUML_FLAG_C); // getflgs i0,zc
UML_LOAD(block, IREG(0), ppc->impstate->cmpl_cr_table, IREG(0), DWORD); // load i0,cmpl_cr_table,i0,dword
UML_ROLINS(block, CR32, IREG(0), IMM(0), IMM(CRMASK(G_CRFD(op)))); // rolins cr,i0,0,crmask[cr]
return TRUE;
-
+
case 0x0b: /* CMPI */
UML_CMP(block, R32(G_RA(op)), IMM((INT16)G_SIMM(op))); // cmp ra,uimm
UML_GETFLGS(block, IREG(0), DRCUML_FLAG_Z | DRCUML_FLAG_C | DRCUML_FLAG_S); // getflgs i0,zcs
UML_LOAD(block, IREG(0), ppc->impstate->cmp_cr_table, IREG(0), DWORD); // load i0,cmp_cr_table,i0,dword
UML_ROLINS(block, CR32, IREG(0), IMM(0), IMM(CRMASK(G_CRFD(op)))); // rolins cr,i0,0,crmask[cr]
return TRUE;
-
+
case 0x08: /* SUBFIC */
UML_SUBf(block, R32(G_RD(op)), IMM((INT16)G_SIMM(op)), R32(G_RA(op)), FLAGS_C); // sub rd,simm,ra,c
generate_compute_flags(block, FALSE, XER_CA, TRUE); // <update flags>
return TRUE;
-
+
case 0x0c: /* ADDIC */
UML_ADDf(block, R32(G_RD(op)), R32(G_RA(op)), IMM((INT16)G_SIMM(op)), FLAGS_C); // add rd,ra,simm,c
generate_compute_flags(block, FALSE, XER_CA, FALSE); // <update flags>
return TRUE;
-
+
case 0x0d: /* ADDIC. */
UML_ADDf(block, R32(G_RD(op)), R32(G_RA(op)), IMM((INT16)G_SIMM(op)), FLAGS_C); // add rd,ra,simm,c
generate_compute_flags(block, TRUE, XER_CA, FALSE); // <update flags>
return TRUE;
-
+
case 0x10: /* BCx */
generate_branch_bo(block, compiler, desc, G_BO(op), G_BI(op), 0, op & M_LK); // <branch conditional>
return TRUE;
-
+
case 0x11: /* SC */
UML_EXH(block, ppc->impstate->exception[EXCEPTION_SYSCALL], IMM(0)); // exh syscall,0
return TRUE;
-
+
case 0x12: /* Bx */
generate_branch(block, compiler, desc, 0, op & M_LK); // <branch>
return TRUE;
-
+
case 0x13: /* 0x13 group */
return generate_instruction_13(block, compiler, desc); // <group13>
-
+
case 0x14: /* RLWIMIx */
UML_ROLINS(block, R32(G_RA(op)), R32(G_RS(op)), IMM(G_SH(op)), IMM(compute_rlw_mask(G_MB(op), G_ME(op))));
// rolins ra,rs,sh,mask
@@ -2261,7 +2261,7 @@ static int generate_opcode(drcuml_block *block, compiler_state *compiler, const
generate_compute_flags(block, TRUE, 0, FALSE); // <update flags>
}
return TRUE;
-
+
case 0x15: /* RLWINMx */
UML_ROLAND(block, R32(G_RA(op)), R32(G_RS(op)), IMM(G_SH(op)), IMM(compute_rlw_mask(G_MB(op), G_ME(op))));
// roland ra,rs,sh,mask
@@ -2271,7 +2271,7 @@ static int generate_opcode(drcuml_block *block, compiler_state *compiler, const
generate_compute_flags(block, TRUE, 0, FALSE); // <update flags>
}
return TRUE;
-
+
case 0x17: /* RLWNMx */
UML_ROLAND(block, R32(G_RA(op)), R32(G_RS(op)), R32(G_RB(op)), IMM(compute_rlw_mask(G_MB(op), G_ME(op))));
// roland ra,rs,rb,mask
@@ -2281,23 +2281,23 @@ static int generate_opcode(drcuml_block *block, compiler_state *compiler, const
generate_compute_flags(block, TRUE, 0, FALSE); // <update flags>
}
return TRUE;
-
+
case 0x18: /* ORI */
UML_OR(block, R32(G_RA(op)), R32(G_RS(op)), IMM(G_UIMM(op))); // or ra,rs,uimm
return TRUE;
-
+
case 0x19: /* ORIS */
UML_OR(block, R32(G_RA(op)), R32(G_RS(op)), IMM(G_UIMM(op) << 16)); // or ra,rs,uimm << 16
return TRUE;
-
+
case 0x1a: /* XORI */
UML_XOR(block, R32(G_RA(op)), R32(G_RS(op)), IMM(G_UIMM(op))); // xor ra,rs,uimm
return TRUE;
-
+
case 0x1b: /* XORIS */
UML_XOR(block, R32(G_RA(op)), R32(G_RS(op)), IMM(G_UIMM(op) << 16)); // xor ra,rs,uimm << 16
return TRUE;
-
+
case 0x1c: /* ANDI. */
UML_ANDf(block, R32(G_RA(op)), R32(G_RS(op)), IMM(G_UIMM(op)), FLAGS_RC(op)); // and ra,rs,uimm,FLAGS_RC
generate_compute_flags(block, TRUE, 0, FALSE); // <update flags>
@@ -2307,10 +2307,10 @@ static int generate_opcode(drcuml_block *block, compiler_state *compiler, const
UML_ANDf(block, R32(G_RA(op)), R32(G_RS(op)), IMM(G_UIMM(op) << 16), FLAGS_RC(op));// and ra,rs,uimm << 16,FLAGS_RC
generate_compute_flags(block, TRUE, 0, FALSE); // <update flags>
return TRUE;
-
+
case 0x1f: /* 0x1f group */
return generate_instruction_1f(block, compiler, desc); // <group1f>
-
+
case 0x22: /* LBZ */
UML_ADD(block, IREG(0), R32Z(G_RA(op)), IMM((INT16)G_SIMM(op))); // add i0,ra,simm
UML_MAPVAR(block, MAPVAR_DSISR, DSISR_IMM(op)); // mapvar dsisr,DSISR_IMM(op)
@@ -2318,7 +2318,7 @@ static int generate_opcode(drcuml_block *block, compiler_state *compiler, const
UML_AND(block, R32(G_RD(op)), IREG(0), IMM(0xff)); // and rd,i0,0xff
generate_update_cycles(block, compiler, IMM(desc->pc + 4), TRUE); // <update cycles>
return TRUE;
-
+
case 0x28: /* LHZ */
UML_ADD(block, IREG(0), R32Z(G_RA(op)), IMM((INT16)G_SIMM(op))); // add i0,ra,simm
UML_MAPVAR(block, MAPVAR_DSISR, DSISR_IMM(op)); // mapvar dsisr,DSISR_IMM(op)
@@ -2326,7 +2326,7 @@ static int generate_opcode(drcuml_block *block, compiler_state *compiler, const
UML_AND(block, R32(G_RD(op)), IREG(0), IMM(0xffff)); // and rd,i0,0xffff
generate_update_cycles(block, compiler, IMM(desc->pc + 4), TRUE); // <update cycles>
return TRUE;
-
+
case 0x2a: /* LHA */
UML_ADD(block, IREG(0), R32Z(G_RA(op)), IMM((INT16)G_SIMM(op))); // add i0,ra,simm
UML_MAPVAR(block, MAPVAR_DSISR, DSISR_IMM(op)); // mapvar dsisr,DSISR_IMM(op)
@@ -2334,7 +2334,7 @@ static int generate_opcode(drcuml_block *block, compiler_state *compiler, const
UML_SEXT(block, R32(G_RD(op)), IREG(0), WORD); // sext rd,i0,word
generate_update_cycles(block, compiler, IMM(desc->pc + 4), TRUE); // <update cycles>
return TRUE;
-
+
case 0x20: /* LWZ */
UML_ADD(block, IREG(0), R32Z(G_RA(op)), IMM((INT16)G_SIMM(op))); // add i0,ra,simm
UML_MAPVAR(block, MAPVAR_DSISR, DSISR_IMM(op)); // mapvar dsisr,DSISR_IMM(op)
@@ -2342,7 +2342,7 @@ static int generate_opcode(drcuml_block *block, compiler_state *compiler, const
UML_MOV(block, R32(G_RD(op)), IREG(0)); // mov rd,i0
generate_update_cycles(block, compiler, IMM(desc->pc + 4), TRUE); // <update cycles>
return TRUE;
-
+
case 0x23: /* LBZU */
UML_ADD(block, IREG(0), R32(G_RA(op)), IMM((INT16)G_SIMM(op))); // add i0,ra,simm
UML_MOV(block, MEM(&ppc->impstate->updateaddr), IREG(0)); // mov [updateaddr],i0
@@ -2352,7 +2352,7 @@ static int generate_opcode(drcuml_block *block, compiler_state *compiler, const
UML_MOV(block, R32(G_RA(op)), MEM(&ppc->impstate->updateaddr)); // mov ra,[updateaddr]
generate_update_cycles(block, compiler, IMM(desc->pc + 4), TRUE); // <update cycles>
return TRUE;
-
+
case 0x29: /* LHZU */
UML_ADD(block, IREG(0), R32(G_RA(op)), IMM((INT16)G_SIMM(op))); // add i0,ra,simm
UML_MOV(block, MEM(&ppc->impstate->updateaddr), IREG(0)); // mov [updateaddr],i0
@@ -2362,7 +2362,7 @@ static int generate_opcode(drcuml_block *block, compiler_state *compiler, const
UML_MOV(block, R32(G_RA(op)), MEM(&ppc->impstate->updateaddr)); // mov ra,[updateaddr]
generate_update_cycles(block, compiler, IMM(desc->pc + 4), TRUE); // <update cycles>
return TRUE;
-
+
case 0x2b: /* LHAU */
UML_ADD(block, IREG(0), R32(G_RA(op)), IMM((INT16)G_SIMM(op))); // add i0,ra,simm
UML_MOV(block, MEM(&ppc->impstate->updateaddr), IREG(0)); // mov [updateaddr],i0
@@ -2372,7 +2372,7 @@ static int generate_opcode(drcuml_block *block, compiler_state *compiler, const
UML_MOV(block, R32(G_RA(op)), MEM(&ppc->impstate->updateaddr)); // mov ra,[updateaddr]
generate_update_cycles(block, compiler, IMM(desc->pc + 4), TRUE); // <update cycles>
return TRUE;
-
+
case 0x21: /* LWZU */
UML_ADD(block, IREG(0), R32(G_RA(op)), IMM((INT16)G_SIMM(op))); // add i0,ra,simm
UML_MOV(block, MEM(&ppc->impstate->updateaddr), IREG(0)); // mov [updateaddr],i0
@@ -2448,7 +2448,7 @@ static int generate_opcode(drcuml_block *block, compiler_state *compiler, const
}
generate_update_cycles(block, compiler, IMM(desc->pc + 4), TRUE); // <update cycles>
return TRUE;
-
+
case 0x2f: /* STMW */
UML_MAPVAR(block, MAPVAR_DSISR, DSISR_IMMU(op)); // mapvar dsisr,DSISR_IMMU(op)
for (regnum = G_RS(op); regnum < 32; regnum++)
@@ -2460,7 +2460,7 @@ static int generate_opcode(drcuml_block *block, compiler_state *compiler, const
}
generate_update_cycles(block, compiler, IMM(desc->pc + 4), TRUE); // <update cycles>
return TRUE;
-
+
case 0x30: /* LFS */
UML_ADD(block, IREG(0), R32Z(G_RA(op)), IMM((INT16)G_SIMM(op))); // add i0,ra,simm
UML_MAPVAR(block, MAPVAR_DSISR, DSISR_IMM(op)); // mapvar dsisr,DSISR_IMM(op)
@@ -2469,7 +2469,7 @@ static int generate_opcode(drcuml_block *block, compiler_state *compiler, const
UML_FDFRFLT(block, F64(G_RD(op)), MEM(&ppc->impstate->tempdata), DWORD); // fdfrflt fd,[tempdata],dword
generate_update_cycles(block, compiler, IMM(desc->pc + 4), TRUE); // <update cycles>
return TRUE;
-
+
case 0x32: /* LFD */
UML_ADD(block, IREG(0), R32Z(G_RA(op)), IMM((INT16)G_SIMM(op))); // add i0,ra,simm
UML_MAPVAR(block, MAPVAR_DSISR, DSISR_IMM(op)); // mapvar dsisr,DSISR_IMM(op)
@@ -2478,7 +2478,7 @@ static int generate_opcode(drcuml_block *block, compiler_state *compiler, const
UML_FDMOV(block, F64(G_RD(op)), MEM(&ppc->impstate->tempdata)); // fdmov fd,[tempdata]
generate_update_cycles(block, compiler, IMM(desc->pc + 4), TRUE); // <update cycles>
return TRUE;
-
+
case 0x31: /* LFSU */
UML_ADD(block, IREG(0), R32(G_RA(op)), IMM((INT16)G_SIMM(op))); // add i0,ra,simm
UML_MOV(block, MEM(&ppc->impstate->updateaddr), IREG(0)); // mov [updateaddr],i0
@@ -2489,7 +2489,7 @@ static int generate_opcode(drcuml_block *block, compiler_state *compiler, const
UML_MOV(block, R32(G_RA(op)), MEM(&ppc->impstate->updateaddr)); // mov ra,[updateaddr]
generate_update_cycles(block, compiler, IMM(desc->pc + 4), TRUE); // <update cycles>
return TRUE;
-
+
case 0x33: /* LFDU */
UML_ADD(block, IREG(0), R32(G_RA(op)), IMM((INT16)G_SIMM(op))); // add i0,ra,simm
UML_MOV(block, MEM(&ppc->impstate->updateaddr), IREG(0)); // mov [updateaddr],i0
@@ -2500,7 +2500,7 @@ static int generate_opcode(drcuml_block *block, compiler_state *compiler, const
UML_MOV(block, R32(G_RA(op)), MEM(&ppc->impstate->updateaddr)); // mov ra,[updateaddr]
generate_update_cycles(block, compiler, IMM(desc->pc + 4), TRUE); // <update cycles>
return TRUE;
-
+
case 0x34: /* STFS */
UML_ADD(block, IREG(0), R32Z(G_RA(op)), IMM((INT16)G_SIMM(op))); // add i0,ra,simm
UML_FSFRFLT(block, MEM(&ppc->impstate->tempdata), F64(G_RS(op)), QWORD); // fsfrflt [tempdata],rs,qword
@@ -2518,7 +2518,7 @@ static int generate_opcode(drcuml_block *block, compiler_state *compiler, const
UML_CALLH(block, ppc->impstate->write64[ppc->impstate->mode & 3]); // callh write64
generate_update_cycles(block, compiler, IMM(desc->pc + 4), TRUE); // <update cycles>
return TRUE;
-
+
case 0x35: /* STFSU */
UML_ADD(block, IREG(0), R32(G_RA(op)), IMM((INT16)G_SIMM(op))); // add i0,ra,simm
UML_FSFRFLT(block, MEM(&ppc->impstate->tempdata), F64(G_RS(op)), QWORD); // fsfrflt [tempdata],rs,qword
@@ -2543,7 +2543,7 @@ static int generate_opcode(drcuml_block *block, compiler_state *compiler, const
case 0x3b: /* 0x3b group */
return generate_instruction_3b(block, compiler, desc); // <group3b>
-
+
case 0x3f: /* 0x3f group */
return generate_instruction_3f(block, compiler, desc); // <group3f>
}
@@ -2553,7 +2553,7 @@ static int generate_opcode(drcuml_block *block, compiler_state *compiler, const
/*-------------------------------------------------
- generate_instruction_13 - compile opcodes in
+ generate_instruction_13 - compile opcodes in
the 0x13 group
-------------------------------------------------*/
@@ -2561,13 +2561,13 @@ static int generate_instruction_13(drcuml_block *block, compiler_state *compiler
{
UINT32 op = *desc->opptr.l;
UINT32 opswitch = (op >> 1) & 0x3ff;
-
+
switch (opswitch)
{
case 0x010: /* BCLRx */
generate_branch_bo(block, compiler, desc, G_BO(op), G_BI(op), SPR_LR, op & M_LK);// <branch conditional>
return TRUE;
-
+
case 0x210: /* BCCTRx */
generate_branch_bo(block, compiler, desc, G_BO(op), G_BI(op), SPR_CTR, op & M_LK);
// <branch conditional>
@@ -2577,7 +2577,7 @@ static int generate_instruction_13(drcuml_block *block, compiler_state *compiler
UML_ROLINS(block, CR32, CR32, IMM(((G_CRFS(op) - G_CRFD(op)) & 7) * 4), IMM(CRMASK(G_CRFD(op))));
// rolins cr,cr,4*(crfs-crfd),crmask[crfd]
return TRUE;
-
+
case 0x101: /* CRAND */
UML_SHL(block, IREG(0), CR32, IMM(G_CRBA(op))); // shl i0,cr,crba(op)
UML_SHL(block, IREG(1), CR32, IMM(G_CRBB(op))); // shl i1,cr,crbb(op)
@@ -2603,7 +2603,7 @@ static int generate_instruction_13(drcuml_block *block, compiler_state *compiler
UML_ROLINS(block, CR32, IREG(0), IMM(32 - G_CRBD(op)), IMM(0x80000000 >> G_CRBD(op)));
// rolins cr,i0,32-crbd,1<<crbd
return TRUE;
-
+
case 0x1c1: /* CROR */
UML_SHL(block, IREG(0), CR32, IMM(G_CRBA(op))); // shl i0,cr,crba(op)
UML_SHL(block, IREG(1), CR32, IMM(G_CRBB(op))); // shl i1,cr,crbb(op)
@@ -2629,7 +2629,7 @@ static int generate_instruction_13(drcuml_block *block, compiler_state *compiler
UML_ROLINS(block, CR32, IREG(0), IMM(32 - G_CRBD(op)), IMM(0x80000000 >> G_CRBD(op)));
// rolins cr,i0,32-crbd,1<<crbd
return TRUE;
-
+
case 0x0c1: /* CRXOR */
UML_SHL(block, IREG(0), CR32, IMM(G_CRBA(op))); // shl i0,cr,crba(op)
UML_SHL(block, IREG(1), CR32, IMM(G_CRBB(op))); // shl i1,cr,crbb(op)
@@ -2670,7 +2670,7 @@ static int generate_instruction_13(drcuml_block *block, compiler_state *compiler
UML_HASHJMP(block, MEM(&ppc->impstate->mode), SPR32(SPROEA_SRR0), ppc->impstate->nocode);
// hashjmp mode,[srr0],nocode
return TRUE;
-
+
case 0x033: /* RFCI */
assert(ppc->cap & PPCCAP_4XX);
UML_MOV(block, MSR32, SPR32(SPR4XX_SRR3)); // mov [msr],[srr3]
@@ -2680,7 +2680,7 @@ static int generate_instruction_13(drcuml_block *block, compiler_state *compiler
UML_HASHJMP(block, MEM(&ppc->impstate->mode), SPR32(SPR4XX_SRR2), ppc->impstate->nocode);
// hashjmp mode,[srr2],nocode
return TRUE;
-
+
case 0x096: /* ISYNC */
/* effective no-op */
return TRUE;
@@ -2691,7 +2691,7 @@ static int generate_instruction_13(drcuml_block *block, compiler_state *compiler
/*-------------------------------------------------
- generate_instruction_1f - compile opcodes in
+ generate_instruction_1f - compile opcodes in
the 0x1f group
-------------------------------------------------*/
@@ -2701,7 +2701,7 @@ static int generate_instruction_1f(drcuml_block *block, compiler_state *compiler
UINT32 opswitch = (op >> 1) & 0x3ff;
drcuml_codelabel swloop, swloopend;
int item;
-
+
switch (opswitch)
{
case 0x009: /* MULHDUx - 64-bit only */
@@ -2751,46 +2751,46 @@ static int generate_instruction_1f(drcuml_block *block, compiler_state *compiler
UML_ADDf(block, R32(G_RD(op)), R32(G_RA(op)), R32(G_RB(op)), FLAGS_RCOE(op)); // add rd,ra,rb,FLAGS_RCOE(op)
generate_compute_flags(block, op & M_RC, ((op & M_OE) ? XER_OV : 0), FALSE); // <update flags>
return TRUE;
-
+
case 0x00a: /* ADDCx */
case 0x20a: /* ADDCOx */
UML_ADDf(block, R32(G_RD(op)), R32(G_RA(op)), R32(G_RB(op)), FLAGS_RCOECA(op)); // add rd,ra,rb,FLAGS_RCOECA(op)
generate_compute_flags(block, op & M_RC, XER_CA | ((op & M_OE) ? XER_OV : 0), FALSE);// <update flags>
return TRUE;
-
+
case 0x08a: /* ADDEx */
case 0x28a: /* ADDEOx */
UML_CARRY(block, SPR32(SPR_XER), IMM(29)); // carry [xer],XER_CA
UML_ADDCf(block, R32(G_RD(op)), R32(G_RA(op)), R32(G_RB(op)), FLAGS_RCOECA(op));// addc rd,ra,rb,FLAGS_RCOECA(op)
generate_compute_flags(block, op & M_RC, XER_CA | ((op & M_OE) ? XER_OV : 0), FALSE);// <update flags>
return TRUE;
-
+
case 0x0ca: /* ADDZEx */
case 0x2ca: /* ADDZEOx */
UML_CARRY(block, SPR32(SPR_XER), IMM(29)); // carry [xer],XER_CA
UML_ADDCf(block, R32(G_RD(op)), R32(G_RA(op)), IMM(0), FLAGS_RCOECA(op)); // addc rd,ra,0,FLAGS_RCOECA(op)
generate_compute_flags(block, op & M_RC, XER_CA | ((op & M_OE) ? XER_OV : 0), FALSE);// <update flags>
return TRUE;
-
+
case 0x0ea: /* ADDMEx */
case 0x2ea: /* ADDMEOx */
UML_CARRY(block, SPR32(SPR_XER), IMM(29)); // carry [xer],XER_CA
UML_ADDCf(block, R32(G_RD(op)), R32(G_RA(op)), IMM(-1), FLAGS_RCOE(op)); // addc rd,ra,-1,FLAGS_RCOECA(op)
generate_compute_flags(block, op & M_RC, XER_CA | ((op & M_OE) ? XER_OV : 0), FALSE);// <update flags>
return TRUE;
-
+
case 0x028: /* SUBFx */
case 0x228: /* SUBFOx */
UML_SUBf(block, R32(G_RD(op)), R32(G_RB(op)), R32(G_RA(op)), FLAGS_RCOE(op)); // sub rd,rb,ra,FLAGS_RCOE(op)
generate_compute_flags(block, op & M_RC, (op & M_OE) ? XER_OV : 0, TRUE); // <update flags>
return TRUE;
-
+
case 0x008: /* SUBFCx */
case 0x208: /* SUBFCOx */
UML_SUBf(block, R32(G_RD(op)), R32(G_RB(op)), R32(G_RA(op)), FLAGS_RCOECA(op)); // sub rd,rb,ra,FLAGS_RCOECA(op)
generate_compute_flags(block, op & M_RC, XER_CA | ((op & M_OE) ? XER_OV : 0), TRUE);// <update flags>
return TRUE;
-
+
case 0x088: /* SUBFEx */
case 0x288: /* SUBFEOx */
UML_XOR(block, IREG(0), SPR32(SPR_XER), IMM(XER_CA)); // xor i0,[xer],XER_CA
@@ -2798,7 +2798,7 @@ static int generate_instruction_1f(drcuml_block *block, compiler_state *compiler
UML_SUBBf(block, R32(G_RD(op)), R32(G_RB(op)), R32(G_RA(op)), FLAGS_RCOECA(op));// subc rd,rb,ra,FLAGS_RCOECA(op)
generate_compute_flags(block, op & M_RC, XER_CA | ((op & M_OE) ? XER_OV : 0), TRUE);// <update flags>
return TRUE;
-
+
case 0x0c8: /* SUBFZEx */
case 0x2c8: /* SUBFZEOx */
UML_XOR(block, IREG(0), SPR32(SPR_XER), IMM(XER_CA)); // xor i0,[xer],XER_CA
@@ -2806,7 +2806,7 @@ static int generate_instruction_1f(drcuml_block *block, compiler_state *compiler
UML_SUBBf(block, R32(G_RD(op)), IMM(0), R32(G_RA(op)), FLAGS_RCOECA(op)); // subc rd,0,ra,FLAGS_RCOECA(op)
generate_compute_flags(block, op & M_RC, XER_CA | ((op & M_OE) ? XER_OV : 0), TRUE);// <update flags>
return TRUE;
-
+
case 0x0e8: /* SUBFMEx */
case 0x2e8: /* SUBFMEOx */
UML_XOR(block, IREG(0), SPR32(SPR_XER), IMM(XER_CA)); // xor i0,[xer],XER_CA
@@ -2814,7 +2814,7 @@ static int generate_instruction_1f(drcuml_block *block, compiler_state *compiler
UML_SUBBf(block, R32(G_RD(op)), IMM(-1), R32(G_RA(op)), FLAGS_RCOECA(op)); // subc rd,-1,ra,,FLAGS_RCOECA(op)
generate_compute_flags(block, op & M_RC, XER_CA | ((op & M_OE) ? XER_OV : 0), TRUE);// <update flags>
return TRUE;
-
+
case 0x068: /* NEGx */
case 0x268: /* NEGOx */
UML_SUBf(block, R32(G_RD(op)), IMM(0), R32(G_RA(op)), FLAGS_RCOE(op)); // sub rd,0,ra,FLAGS_RCOE(op)
@@ -2827,26 +2827,26 @@ static int generate_instruction_1f(drcuml_block *block, compiler_state *compiler
UML_LOAD(block, IREG(0), ppc->impstate->cmp_cr_table, IREG(0), DWORD); // load i0,cmp_cr_table,i0,dword
UML_ROLINS(block, CR32, IREG(0), IMM(0), IMM(CRMASK(G_CRFD(op)))); // rolins cr,i0,0,crmask[cr]
return TRUE;
-
+
case 0x020: /* CMPL */
UML_CMP(block, R32(G_RA(op)), R32(G_RB(op))); // cmp ra,rb
UML_GETFLGS(block, IREG(0), DRCUML_FLAG_Z | DRCUML_FLAG_C); // getflgs i0,zc
UML_LOAD(block, IREG(0), ppc->impstate->cmpl_cr_table, IREG(0), DWORD); // load i0,cmpl_cr_table,i0,dword
UML_ROLINS(block, CR32, IREG(0), IMM(0), IMM(CRMASK(G_CRFD(op)))); // rolins cr,i0,0,crmask[cr]
return TRUE;
-
+
case 0x00b: /* MULHWUx */
UML_MULUf(block, IREG(0), R32(G_RD(op)), R32(G_RA(op)), R32(G_RB(op)), FLAGS_RC(op));
// mulu i0,rd,ra,rb,FLAGS_RC(op)
generate_compute_flags(block, op & M_RC, 0, FALSE); // <update flags>
return TRUE;
-
+
case 0x04b: /* MULHWx */
UML_MULSf(block, IREG(0), R32(G_RD(op)), R32(G_RA(op)), R32(G_RB(op)), FLAGS_RC(op));
// muls i0,rd,ra,rb,,FLAGS_RC(op)
generate_compute_flags(block, op & M_RC, 0, FALSE); // <update flags>
return TRUE;
-
+
case 0x0eb: /* MULLWx */
case 0x2eb: /* MULLWOx */
if (!(op & M_OE))
@@ -2868,32 +2868,32 @@ static int generate_instruction_1f(drcuml_block *block, compiler_state *compiler
UML_OR(block, SPR32(SPR_XER), SPR32(SPR_XER), IREG(0)); // or [xer],[xer],i0
}
return TRUE;
-
+
case 0x1cb: /* DIVWUx */
case 0x3cb: /* DIVWUOx */
UML_DIVUf(block, R32(G_RD(op)), R32(G_RD(op)), R32(G_RA(op)), R32(G_RB(op)), FLAGS_RCOE(op));
// divu rd,rd,ra,rb,FLAGS_RCOE(op)
generate_compute_flags(block, op & M_RC, ((op & M_OE) ? XER_OV : 0), FALSE); // <update flags>
return TRUE;
-
+
case 0x1eb: /* DIVWx */
case 0x3eb: /* DIVWOx */
UML_DIVSf(block, R32(G_RD(op)), R32(G_RD(op)), R32(G_RA(op)), R32(G_RB(op)), FLAGS_RCOE(op));
// divs rd,rd,ra,rb,FLAGS_RCOE(op)
generate_compute_flags(block, op & M_RC, ((op & M_OE) ? XER_OV : 0), FALSE); // <update flags>
return TRUE;
-
+
case 0x01c: /* ANDx */
UML_ANDf(block, R32(G_RA(op)), R32(G_RS(op)), R32(G_RB(op)), FLAGS_RC(op)); // and ra,rs,rb,FLAGS_RC(op)
generate_compute_flags(block, op & M_RC, 0, FALSE); // <update flags>
return TRUE;
-
+
case 0x03c: /* ANDCx */
UML_XOR(block, IREG(0), R32(G_RB(op)), IMM(~0)); // xor i0,rb,~0
UML_ANDf(block, R32(G_RA(op)), R32(G_RS(op)), IREG(0), FLAGS_RC(op)); // and ra,rs,i0,FLAGS_RC(op)
generate_compute_flags(block, op & M_RC, 0, FALSE); // <update flags>
return TRUE;
-
+
case 0x1dc: /* NANDx */
UML_AND(block, IREG(0), R32(G_RS(op)), R32(G_RB(op))); // and i0,rs,rb
UML_XORf(block, R32(G_RA(op)), IREG(0), IMM(~0), FLAGS_RC(op)); // xor ra,i0,~0,FLAGS_RC(op)
@@ -2904,13 +2904,13 @@ static int generate_instruction_1f(drcuml_block *block, compiler_state *compiler
UML_ORf(block, R32(G_RA(op)), R32(G_RS(op)), R32(G_RB(op)), FLAGS_RC(op)); // or ra,rs,rb,FLAGS_RC(op)
generate_compute_flags(block, op & M_RC, 0, FALSE); // <update flags>
return TRUE;
-
+
case 0x19c: /* ORCx */
UML_XORf(block, IREG(0), R32(G_RB(op)), IMM(~0), FLAGS_RC(op)); // xor i0,rb,~0,FLAGS_RC(op)
UML_OR(block, R32(G_RA(op)), R32(G_RS(op)), IREG(0)); // or ra,rs,i0
generate_compute_flags(block, op & M_RC, 0, FALSE); // <update flags>
return TRUE;
-
+
case 0x07c: /* NORx */
UML_OR(block, IREG(0), R32(G_RS(op)), R32(G_RB(op))); // or i0,rs,rb
UML_XORf(block, R32(G_RA(op)), IREG(0), IMM(~0), FLAGS_RC(op)); // xor ra,i0,~0,FLAGS_RC(op)
@@ -2921,7 +2921,7 @@ static int generate_instruction_1f(drcuml_block *block, compiler_state *compiler
UML_XORf(block, R32(G_RA(op)), R32(G_RS(op)), R32(G_RB(op)), FLAGS_RC(op)); // xor ra,rs,rb,FLAGS_RC(op)
generate_compute_flags(block, op & M_RC, 0, FALSE); // <update flags>
return TRUE;
-
+
case 0x11c: /* EQVx */
UML_XOR(block, IREG(0), R32(G_RS(op)), R32(G_RB(op))); // xor i0,rs,rb
UML_XORf(block, R32(G_RA(op)), IREG(0), IMM(~0), FLAGS_RC(op)); // xor ra,i0,~0,FLAGS_RC(op)
@@ -2932,12 +2932,12 @@ static int generate_instruction_1f(drcuml_block *block, compiler_state *compiler
UML_SHL(block, R32(G_RA(op)), R32(G_RS(op)), R32(G_RB(op))); // shl ra,rs,rb
generate_compute_flags(block, op & M_RC, 0, FALSE); // <update flags>
return TRUE;
-
+
case 0x218: /* SRWx */
UML_SHRf(block, R32(G_RA(op)), R32(G_RS(op)), R32(G_RB(op)), FLAGS_RC(op)); // shr ra,rs,rb,FLAGS_RC(op)
generate_compute_flags(block, op & M_RC, 0, FALSE); // <update flags>
return TRUE;
-
+
case 0x318: /* SRAWx */
UML_SHL(block, IREG(1), IMM(0xffffffff), R32(G_RB(op))); // shl i1,0xffffffff,rb
UML_XOR(block, IREG(1), IREG(1), IMM(~0)); // xor i1,i1,~0
@@ -2959,7 +2959,7 @@ static int generate_instruction_1f(drcuml_block *block, compiler_state *compiler
UML_SARf(block, R32(G_RA(op)), R32(G_RS(op)), IMM(G_SH(op)), FLAGS_RC(op)); // sar ra,rs,sh,FLAGS_RC(op)
generate_compute_flags(block, op & M_RC, 0, FALSE); // <update flags>
return TRUE;
-
+
case 0x01a: /* CNTLZWx */
UML_LZCNT(block, R32(G_RA(op)), R32(G_RS(op))); // lzcnt ra,rs,rb
if (op & M_RC)
@@ -2968,7 +2968,7 @@ static int generate_instruction_1f(drcuml_block *block, compiler_state *compiler
generate_compute_flags(block, op & M_RC, 0, FALSE); // <update flags>
}
return TRUE;
-
+
case 0x3ba: /* EXTSBx */
UML_SEXT(block, R32(G_RA(op)), R32(G_RS(op)), BYTE); // sext ra,rs,byte
if (op & M_RC)
@@ -2977,7 +2977,7 @@ static int generate_instruction_1f(drcuml_block *block, compiler_state *compiler
generate_compute_flags(block, op & M_RC, 0, FALSE); // <update flags>
}
return TRUE;
-
+
case 0x39a: /* EXTSHx */
UML_SEXT(block, R32(G_RA(op)), R32(G_RS(op)), WORD); // sext ra,rs,word
if (op & M_RC)
@@ -2986,7 +2986,7 @@ static int generate_instruction_1f(drcuml_block *block, compiler_state *compiler
generate_compute_flags(block, op & M_RC, 0, FALSE); // <update flags>
}
return TRUE;
-
+
case 0x057: /* LBZX */
UML_ADD(block, IREG(0), R32Z(G_RA(op)), R32(G_RB(op))); // add i0,ra,rb
UML_MAPVAR(block, MAPVAR_DSISR, DSISR_IDX(op)); // mapvar dsisr,DSISR_IDX(op)
@@ -3282,7 +3282,7 @@ static int generate_instruction_1f(drcuml_block *block, compiler_state *compiler
UML_MOV(block, R32(G_RA(op)), MEM(&ppc->impstate->updateaddr)); // mov ra,[updateaddr]
generate_update_cycles(block, compiler, IMM(desc->pc + 4), TRUE); // <update cycles>
return TRUE;
-
+
case 0x2f7: /* STFDUX */
UML_ADD(block, IREG(0), R32(G_RA(op)), R32(G_RB(op))); // add i0,ra,rb
UML_FDMOV(block, MEM(&ppc->impstate->tempdata), F64(G_RS(op))); // fdmov [tempdata],rs
@@ -3324,7 +3324,7 @@ static int generate_instruction_1f(drcuml_block *block, compiler_state *compiler
UML_JMPc(block, IF_NZ, swloop); // jmp swloop,NZ
generate_update_cycles(block, compiler, IMM(desc->pc + 4), TRUE); // <update cycles>
return TRUE;
-
+
case 0x295: /* STSWX */
UML_ANDf(block, FLAGS_Z, MEM(&ppc->impstate->swcount), SPR32(SPR_XER), IMM(0x7f));// and [swcount],[xer],0x7f,Z
UML_JMPc(block, IF_Z, swloopend = compiler->labelnum++); // jmp swloopend,Z
@@ -3347,11 +3347,11 @@ static int generate_instruction_1f(drcuml_block *block, compiler_state *compiler
UML_LABEL(block, swloopend); // swloopend:
generate_update_cycles(block, compiler, IMM(desc->pc + 4), TRUE); // <update cycles>
return TRUE;
-
+
case 0x1b6: /* ECOWX */
/* not implemented */
return FALSE;
-
+
case 0x036: /* DCBST */
case 0x056: /* DCBF */
case 0x0f6: /* DCBTST */
@@ -3366,7 +3366,7 @@ static int generate_instruction_1f(drcuml_block *block, compiler_state *compiler
case 0x3f6: /* DCBZ */
UML_ADD(block, IREG(0), R32Z(G_RA(op)), R32(G_RB(op))); // add i0,ra,rb
- UML_AND(block, MEM(&ppc->impstate->tempaddr), IREG(0), IMM(~(ppc->cache_line_size - 1)));
+ UML_AND(block, MEM(&ppc->impstate->tempaddr), IREG(0), IMM(~(ppc->cache_line_size - 1)));
// and [tempaddr],i0,~(cache_line_size - 1)
for (item = 0; item < ppc->cache_line_size / 8; item++)
{
@@ -3384,7 +3384,7 @@ static int generate_instruction_1f(drcuml_block *block, compiler_state *compiler
case 0x172: /* TLBIA */
UML_CALLC(block, ppccom_execute_tlbia, ppc); // callc ppccom_execute_tlbia,ppc
return TRUE;
-
+
case 0x3d2: /* TLBLD */
assert(ppc->cap & PPCCAP_603_MMU);
UML_MOV(block, MEM(&ppc->param0), R32(G_RB(op))); // mov [param0],rb
@@ -3402,7 +3402,7 @@ static int generate_instruction_1f(drcuml_block *block, compiler_state *compiler
case 0x013: /* MFCR */
UML_MOV(block, R32(G_RD(op)), CR32); // mov rd,cr
return TRUE;
-
+
case 0x053: /* MFMSR */
UML_MOV(block, R32(G_RD(op)), MSR32); // mov rd,msr
return TRUE;
@@ -3444,11 +3444,11 @@ static int generate_instruction_1f(drcuml_block *block, compiler_state *compiler
UML_MOV(block, R32(G_RD(op)), MEM(&ppc->param1)); // mov rd,[param1]
return TRUE;
}
-
+
case 0x090: /* MTCRF */
UML_ROLINS(block, CR32, R32(G_RS(op)), IMM(0), IMM(compute_crf_mask(G_CRM(op))));// rolins cr,rs,0,G_CRM
return TRUE;
-
+
case 0x092: /* MTMSR */
if (ppc->cap & PPCCAP_603_MMU)
UML_XOR(block, IREG(0), MSR32, R32(G_RS(op))); // xor i0,msr32,rs
@@ -3496,7 +3496,7 @@ static int generate_instruction_1f(drcuml_block *block, compiler_state *compiler
// rolins cr,[xer],32-4*crfd,crmask(crfd)
UML_AND(block, SPR32(SPR_XER), SPR32(SPR_XER), IMM(~0xf0000000)); // and [xer],[xer],~0xf0000000
return TRUE;
-
+
case 0x106: /* ICBT */
case 0x1c6: /* DCCCI */
case 0x3c6: /* ICCCI */
@@ -3533,14 +3533,14 @@ static int generate_instruction_1f(drcuml_block *block, compiler_state *compiler
generate_update_cycles(block, compiler, IMM(desc->pc + 4), TRUE); // <update cycles>
return TRUE;
}
-
+
case 0x083: /* WRTEE */
assert(ppc->cap & PPCCAP_4XX);
UML_ROLINS(block, MSR32, R32(G_RS(op)), IMM(0), IMM(MSR_EE)); // rolins msr,rs,0,MSR_EE
compiler->checkints = TRUE;
generate_update_cycles(block, compiler, IMM(desc->pc + 4), TRUE); // <update cycles>
return TRUE;
-
+
case 0x0a3: /* WRTEEI */
assert(ppc->cap & PPCCAP_4XX);
if (op & MSR_EE)
@@ -3559,7 +3559,7 @@ static int generate_instruction_1f(drcuml_block *block, compiler_state *compiler
/*-------------------------------------------------
- generate_instruction_3b - compile opcodes in
+ generate_instruction_3b - compile opcodes in
the 0x3b group
-------------------------------------------------*/
@@ -3574,27 +3574,27 @@ static int generate_instruction_3b(drcuml_block *block, compiler_state *compiler
UML_FDADD(block, FREG(0), F64(G_RA(op)), F64(G_RB(op))); // fdadd f0,ra,rb
UML_FDRNDS(block, F64(G_RD(op)), FREG(0)); // fdrnds rd,f0
return TRUE;
-
+
case 0x14: /* FSUBSx */
UML_FDSUB(block, FREG(0), F64(G_RA(op)), F64(G_RB(op))); // fdsub f0,ra,rb
UML_FDRNDS(block, F64(G_RD(op)), FREG(0)); // fdrnds rd,f0
return TRUE;
-
+
case 0x19: /* FMULSx */
UML_FDMUL(block, FREG(0), F64(G_RA(op)), F64(G_RB(op))); // fdmul f0,ra,rb
UML_FDRNDS(block, F64(G_RD(op)), FREG(0)); // fdrnds rd,f0
return TRUE;
-
+
case 0x12: /* FDIVSx */
UML_FDDIV(block, FREG(0), F64(G_RA(op)), F64(G_RB(op))); // fddiv f0,ra,rb
UML_FDRNDS(block, F64(G_RD(op)), FREG(0)); // fdrnds rd,f0
return TRUE;
-
+
case 0x16: /* FSQRTSx */
UML_FDSQRT(block, FREG(0), F64(G_RB(op))); // fdsqrt f0,rb
UML_FDRNDS(block, F64(G_RD(op)), FREG(0)); // fdrnds rd,f0
return TRUE;
-
+
case 0x18: /* FRESx */
UML_FSFRFLT(block, FREG(0), F64(G_RB(op)), QWORD); // fsfrlt f0,rb,qword
UML_FSRECIP(block, FREG(0), FREG(0)); // fsrecip f0,f0
@@ -3606,20 +3606,20 @@ static int generate_instruction_3b(drcuml_block *block, compiler_state *compiler
UML_FDADD(block, FREG(0), FREG(0), F64(G_RB(op))); // fdadd f0,f0,rb
UML_FDRNDS(block, F64(G_RD(op)), FREG(0)); // fdrnds rd,f0
return TRUE;
-
+
case 0x1c: /* FMSUBSx */
UML_FDMUL(block, FREG(0), F64(G_RA(op)), F64(G_REGC(op))); // fdmul f0,ra,rc
UML_FDSUB(block, FREG(0), FREG(0), F64(G_RB(op))); // fdsub f0,f0,rb
UML_FDRNDS(block, F64(G_RD(op)), FREG(0)); // fdrnds rd,f0
return TRUE;
-
+
case 0x1f: /* FNMADDSx */
UML_FDMUL(block, FREG(0), F64(G_RA(op)), F64(G_REGC(op))); // fdmul f0,ra,rc
UML_FDADD(block, FREG(0), FREG(0), F64(G_RB(op))); // fdadd f0,f0,rb
UML_FDNEG(block, FREG(0), FREG(0)); // fdneg f0,f0
UML_FDRNDS(block, F64(G_RD(op)), FREG(0)); // fdrnds rd,f0
return TRUE;
-
+
case 0x1e: /* FNMSUBSx */
UML_FDMUL(block, FREG(0), F64(G_RA(op)), F64(G_REGC(op))); // fdmul f0,ra,rc
UML_FDSUB(block, FREG(0), F64(G_RB(op)), FREG(0)); // fdsub f0,rb,f0
@@ -3633,7 +3633,7 @@ static int generate_instruction_3b(drcuml_block *block, compiler_state *compiler
/*-------------------------------------------------
- generate_instruction_3f - compile opcodes in
+ generate_instruction_3f - compile opcodes in
the 0x3f group
-------------------------------------------------*/
@@ -3641,7 +3641,7 @@ static int generate_instruction_3f(drcuml_block *block, compiler_state *compiler
{
UINT32 op = *desc->opptr.l;
UINT32 opswitch = (op >> 1) & 0x3ff;
-
+
if (opswitch & 0x10)
{
opswitch &= 0x1f;
@@ -3662,11 +3662,11 @@ static int generate_instruction_3f(drcuml_block *block, compiler_state *compiler
case 0x12: /* FDIVx */
UML_FDDIV(block, F64(G_RD(op)), F64(G_RA(op)), F64(G_RB(op))); // fddiv rd,ra,rb
return TRUE;
-
+
case 0x16: /* FSQRTx */
UML_FDSQRT(block, F64(G_RD(op)), F64(G_RB(op))); // fdsqrt rd,rb
return TRUE;
-
+
case 0x1a: /* FRSQRTEx */
UML_FDRSQRT(block, F64(G_RD(op)), F64(G_RB(op))); // fdrsqrt rd,rb
return TRUE;
@@ -3676,7 +3676,7 @@ static int generate_instruction_3f(drcuml_block *block, compiler_state *compiler
UML_FDMOVc(block, IF_AE, F64(G_RD(op)), F64(G_REGC(op))); // fdmov rd,rc,AE
UML_FDMOVc(block, IF_B, F64(G_RD(op)), F64(G_RB(op))); // fdmov rd,rb,B
return TRUE;
-
+
case 0x1d: /* FMADDx */
UML_FDMUL(block, FREG(0), F64(G_RA(op)), F64(G_REGC(op))); // fdmul f0,ra,rc
UML_FDADD(block, F64(G_RD(op)), FREG(0), F64(G_RB(op))); // fdadd rd,f0,rb
@@ -3752,11 +3752,11 @@ static int generate_instruction_3f(drcuml_block *block, compiler_state *compiler
case 0x046: /* MTFSB0x */
UML_AND(block, FPSCR32, FPSCR32, IMM(~(0x80000000 >> G_CRBD(op)))); // and fpscr32,fpscr32,~(0x80000000 >> G_CRBD)
return TRUE;
-
+
case 0x026: /* MTFSB1x */
UML_OR(block, FPSCR32, FPSCR32, IMM(0x80000000 >> G_CRBD(op))); // or fpscr32,fpscr32,(0x80000000 >> G_CRBD)
return TRUE;
-
+
case 0x040: /* MCRFS */
UML_ROLINS(block, CR32, FPSCR32, IMM(((G_CRFS(op) - G_CRFD(op)) & 7) * 4), IMM(CRMASK(G_CRFD(op))));
// rolins cr,fpscr,shift,crmask[crfd]
diff --git a/src/emu/cpu/powerpc/ppcfe.c b/src/emu/cpu/powerpc/ppcfe.c
index f232793e0d1..1a9209f4f7a 100644
--- a/src/emu/cpu/powerpc/ppcfe.c
+++ b/src/emu/cpu/powerpc/ppcfe.c
@@ -54,12 +54,12 @@ int ppcfe_describe(void *param, opcode_desc *desc)
case 0x3a: /* 0x3a group - 64-bit only */
case 0x3e: /* 0x3e group - 64-bit only */
return FALSE;
-
+
case 0x03: /* TWI */
desc->gpr.used |= REGFLAG_R(G_RA(op));
desc->flags |= OPFLAG_CAN_CAUSE_EXCEPTION;
return TRUE;
-
+
case 0x07: /* MULLI */
desc->gpr.used |= REGFLAG_R(G_RA(op));
desc->gpr.modified |= REGFLAG_R(G_RD(op));
@@ -70,24 +70,24 @@ int ppcfe_describe(void *param, opcode_desc *desc)
desc->gpr.used |= REGFLAG_RZ(G_RA(op));
desc->gpr.modified |= REGFLAG_R(G_RD(op));
return TRUE;
-
+
case 0x0a: /* CMPLI */
case 0x0b: /* CMPI */
desc->gpr.used |= REGFLAG_R(G_RA(op)) | REGFLAG_XER;
desc->gpr.modified |= REGFLAG_CR(G_CRFD(op));
return TRUE;
-
+
case 0x08: /* SUBFIC */
case 0x0c: /* ADDIC */
desc->gpr.used |= REGFLAG_R(G_RA(op));
desc->gpr.modified |= REGFLAG_R(G_RD(op)) | REGFLAG_XER;
return TRUE;
-
+
case 0x0d: /* ADDIC. */
desc->gpr.used |= REGFLAG_R(G_RA(op)) | REGFLAG_XER;
desc->gpr.modified |= REGFLAG_R(G_RT(op)) | REGFLAG_CR(0) | REGFLAG_XER;
return TRUE;
-
+
case 0x10: /* BCx */
desc->gpr.used |= REGFLAG_CR(G_BI(op) / 4);
if (op & M_LK) desc->gpr.modified |= REGFLAG_LR;
@@ -102,22 +102,22 @@ int ppcfe_describe(void *param, opcode_desc *desc)
desc->flags |= OPFLAG_IS_CONDITIONAL_BRANCH;
desc->targetpc = (INT16)(G_BD(op) << 2) + ((op & M_AA) ? 0 : desc->pc);
return TRUE;
-
+
case 0x11: /* SC */
if (!(ppc->cap & (PPCCAP_OEA | PPCCAP_4XX)))
return FALSE;
desc->flags |= OPFLAG_WILL_CAUSE_EXCEPTION;
return TRUE;
-
+
case 0x12: /* Bx */
if (op & M_LK) desc->gpr.modified |= REGFLAG_LR;
desc->flags |= OPFLAG_IS_UNCONDITIONAL_BRANCH | OPFLAG_END_SEQUENCE;
desc->targetpc = ((INT32)(G_LI(op) << 8) >> 6) + ((op & M_AA) ? 0 : desc->pc);
return TRUE;
-
+
case 0x13: /* 0x13 group */
return describe_instruction_13(ppc, op, desc);
-
+
case 0x14: /* RLWIMIx */
desc->gpr.used |= REGFLAG_R(G_RS(op)) | REGFLAG_R(G_RA(op));
desc->gpr.modified |= REGFLAG_R(G_RA(op));
@@ -127,7 +127,7 @@ int ppcfe_describe(void *param, opcode_desc *desc)
desc->gpr.modified |= REGFLAG_CR(0);
}
return TRUE;
-
+
case 0x15: /* RLWINMx */
desc->gpr.used |= REGFLAG_R(G_RS(op));
desc->gpr.modified |= REGFLAG_R(G_RA(op));
@@ -137,7 +137,7 @@ int ppcfe_describe(void *param, opcode_desc *desc)
desc->gpr.modified |= REGFLAG_CR(0);
}
return TRUE;
-
+
case 0x17: /* RLWNMx */
desc->gpr.used |= REGFLAG_R(G_RS(op)) | REGFLAG_R(G_RB(op));
desc->gpr.modified |= REGFLAG_R(G_RA(op));
@@ -147,7 +147,7 @@ int ppcfe_describe(void *param, opcode_desc *desc)
desc->gpr.modified |= REGFLAG_CR(0);
}
return TRUE;
-
+
case 0x18: /* ORI */
case 0x19: /* ORIS */
case 0x1a: /* XORI */
@@ -155,16 +155,16 @@ int ppcfe_describe(void *param, opcode_desc *desc)
desc->gpr.used |= REGFLAG_R(G_RS(op));
desc->gpr.modified |= REGFLAG_R(G_RA(op));
return TRUE;
-
+
case 0x1c: /* ANDI. */
case 0x1d: /* ANDIS. */
desc->gpr.used |= REGFLAG_R(G_RS(op)) | REGFLAG_XER;
desc->gpr.modified |= REGFLAG_R(G_RA(op)) | REGFLAG_CR(0);
return TRUE;
-
+
case 0x1f: /* 0x1f group */
return describe_instruction_1f(ppc, op, desc);
-
+
case 0x20: /* LWZ */
case 0x22: /* LBZ */
case 0x28: /* LHZ */
@@ -173,7 +173,7 @@ int ppcfe_describe(void *param, opcode_desc *desc)
desc->gpr.modified |= REGFLAG_R(G_RD(op));
desc->flags |= OPFLAG_READS_MEMORY;
return TRUE;
-
+
case 0x21: /* LWZU */
case 0x23: /* LBZU */
case 0x29: /* LHZU */
@@ -184,14 +184,14 @@ int ppcfe_describe(void *param, opcode_desc *desc)
desc->gpr.modified |= REGFLAG_R(G_RD(op)) | REGFLAG_R(G_RA(op));
desc->flags |= OPFLAG_READS_MEMORY;
return TRUE;
-
+
case 0x24: /* STW */
case 0x26: /* STB */
case 0x2c: /* STH */
desc->gpr.used |= REGFLAG_RZ(G_RA(op)) | REGFLAG_R(G_RS(op));
desc->flags |= OPFLAG_WRITES_MEMORY;
return TRUE;
-
+
case 0x25: /* STWU */
case 0x27: /* STBU */
case 0x2d: /* STHU */
@@ -201,18 +201,18 @@ int ppcfe_describe(void *param, opcode_desc *desc)
desc->gpr.modified |= REGFLAG_R(G_RA(op));
desc->flags |= OPFLAG_WRITES_MEMORY;
return TRUE;
-
+
case 0x2e: /* LMW */
desc->gpr.used |= REGFLAG_RZ(G_RA(op));
desc->gpr.modified |= ((REGFLAG_R(31) << 1) - 1) & ~(REGFLAG_R(G_RD(op)) - 1);
desc->flags |= OPFLAG_READS_MEMORY;
return TRUE;
-
+
case 0x2f: /* STMW */
desc->gpr.used |= REGFLAG_RZ(G_RA(op)) | (((REGFLAG_R(31) << 1) - 1) & ~(REGFLAG_R(G_RS(op)) - 1));
desc->flags |= OPFLAG_WRITES_MEMORY;
return TRUE;
-
+
case 0x30: /* LFS */
case 0x32: /* LFD */
if (!(ppc->cap & PPCCAP_FPU))
@@ -221,7 +221,7 @@ int ppcfe_describe(void *param, opcode_desc *desc)
desc->fpr.modified |= REGFLAG_R(G_RD(op));
desc->flags |= OPFLAG_READS_MEMORY;
return TRUE;
-
+
case 0x31: /* LFSU */
case 0x33: /* LFDU */
if (!(ppc->cap & PPCCAP_FPU))
@@ -231,7 +231,7 @@ int ppcfe_describe(void *param, opcode_desc *desc)
desc->fpr.modified |= REGFLAG_R(G_RD(op));
desc->flags |= OPFLAG_READS_MEMORY;
return TRUE;
-
+
case 0x34: /* STFS */
case 0x36: /* STFD */
if (!(ppc->cap & PPCCAP_FPU))
@@ -240,7 +240,7 @@ int ppcfe_describe(void *param, opcode_desc *desc)
desc->fpr.used |= REGFLAG_R(G_RS(op));
desc->flags |= OPFLAG_WRITES_MEMORY;
return TRUE;
-
+
case 0x35: /* STFSU */
case 0x37: /* STFDU */
if (!(ppc->cap & PPCCAP_FPU))
@@ -250,10 +250,10 @@ int ppcfe_describe(void *param, opcode_desc *desc)
desc->fpr.used |= REGFLAG_R(G_RS(op));
desc->flags |= OPFLAG_WRITES_MEMORY;
return TRUE;
-
+
case 0x3b: /* 0x3b group */
return describe_instruction_3b(ppc, op, desc);
-
+
case 0x3f: /* 0x3f group */
return describe_instruction_3f(ppc, op, desc);
}
@@ -271,14 +271,14 @@ int ppcfe_describe(void *param, opcode_desc *desc)
static int describe_instruction_13(powerpc_state *ppc, UINT32 op, opcode_desc *desc)
{
UINT32 opswitch = (op >> 1) & 0x3ff;
-
+
switch (opswitch)
{
case 0x000: /* MTCRF */
desc->gpr.used |= REGFLAG_CR(G_CRFS(op));
desc->gpr.modified |= REGFLAG_CR(G_CRFD(op));
return TRUE;
-
+
case 0x010: /* BCLRx */
desc->gpr.used |= REGFLAG_CR(G_BI(op) / 4) | REGFLAG_LR;
if (op & M_LK) desc->gpr.modified |= REGFLAG_LR;
@@ -305,26 +305,26 @@ static int describe_instruction_13(powerpc_state *ppc, UINT32 op, opcode_desc *d
desc->gpr.used |= REGFLAG_CR(G_CRBA(op) / 4) | REGFLAG_CR(G_CRBB(op) / 4);
desc->gpr.modified |= REGFLAG_CR(G_CRBD(op) / 4);
return TRUE;
-
+
case 0x032: /* RFI */
if (!(ppc->cap & (PPCCAP_OEA | PPCCAP_4XX)))
return FALSE;
desc->flags |= OPFLAG_PRIVILEGED | OPFLAG_CAN_CHANGE_MODES | OPFLAG_IS_UNCONDITIONAL_BRANCH | OPFLAG_END_SEQUENCE | OPFLAG_CAN_CAUSE_EXCEPTION;
desc->targetpc = BRANCH_TARGET_DYNAMIC;
return TRUE;
-
+
case 0x033: /* RFCI */
if (!(ppc->cap & PPCCAP_4XX))
return FALSE;
desc->flags |= OPFLAG_PRIVILEGED | OPFLAG_CAN_CHANGE_MODES | OPFLAG_IS_UNCONDITIONAL_BRANCH | OPFLAG_END_SEQUENCE | OPFLAG_CAN_CAUSE_EXCEPTION;
desc->targetpc = BRANCH_TARGET_DYNAMIC;
return TRUE;
-
+
case 0x096: /* ISYNC */
if (!(ppc->cap & (PPCCAP_VEA | PPCCAP_4XX)))
return FALSE;
return TRUE;
-
+
case 0x210: /* BCCTRx */
desc->gpr.used |= REGFLAG_CR(G_BI(op) / 4) | REGFLAG_CTR;
if (op & M_LK) desc->gpr.modified |= REGFLAG_LR;
@@ -349,7 +349,7 @@ static int describe_instruction_13(powerpc_state *ppc, UINT32 op, opcode_desc *d
static int describe_instruction_1f(powerpc_state *ppc, UINT32 op, opcode_desc *desc)
{
UINT32 opswitch = (op >> 1) & 0x3ff;
-
+
switch (opswitch)
{
case 0x009: /* MULHDUx - 64-bit only */
@@ -441,7 +441,7 @@ static int describe_instruction_1f(powerpc_state *ppc, UINT32 op, opcode_desc *d
desc->gpr.used |= ((REGFLAG_CR(7) << 1) - 1) & ~(REGFLAG_CR(0) - 1);
desc->gpr.modified |= REGFLAG_R(G_RD(op));
return TRUE;
-
+
case 0x136: /* ECIWX */
if (!(ppc->cap & PPCCAP_VEA))
return FALSE;
@@ -528,7 +528,7 @@ static int describe_instruction_1f(powerpc_state *ppc, UINT32 op, opcode_desc *d
return FALSE;
desc->gpr.modified |= REGFLAG_R(G_RD(op));
return TRUE;
-
+
case 0x068: /* NEGx */
desc->gpr.used |= REGFLAG_R(G_RA(op));
desc->gpr.modified |= REGFLAG_R(G_RD(op));
@@ -560,7 +560,7 @@ static int describe_instruction_1f(powerpc_state *ppc, UINT32 op, opcode_desc *d
if (G_CRM(op) & 0x40) desc->gpr.modified |= REGFLAG_CR(6);
if (G_CRM(op) & 0x80) desc->gpr.modified |= REGFLAG_CR(7);
return TRUE;
-
+
case 0x092: /* MTMSR */
desc->gpr.used |= REGFLAG_R(G_RS(op));
desc->flags |= OPFLAG_PRIVILEGED | OPFLAG_CAN_CAUSE_EXCEPTION | OPFLAG_CAN_CHANGE_MODES | OPFLAG_END_SEQUENCE;
@@ -619,7 +619,7 @@ static int describe_instruction_1f(powerpc_state *ppc, UINT32 op, opcode_desc *d
return FALSE;
desc->flags |= OPFLAG_PRIVILEGED | OPFLAG_CAN_CAUSE_EXCEPTION;
return TRUE;
-
+
case 0x3d2: /* TLBLD */
case 0x3f2: /* TLBLI */
if (!(ppc->cap & PPCCAP_603_MMU))
@@ -652,7 +652,7 @@ static int describe_instruction_1f(powerpc_state *ppc, UINT32 op, opcode_desc *d
return FALSE;
desc->flags |= OPFLAG_PRIVILEGED | OPFLAG_CAN_CAUSE_EXCEPTION;
return TRUE;
-
+
case 0x256: /* SYNC */
return TRUE;
@@ -660,7 +660,7 @@ static int describe_instruction_1f(powerpc_state *ppc, UINT32 op, opcode_desc *d
if (!(ppc->cap & PPCCAP_VEA))
return FALSE;
return TRUE;
-
+
case 0x237: /* LFSUX */
case 0x277: /* LFDUX */
if (!(ppc->cap & PPCCAP_FPU))
@@ -714,7 +714,7 @@ static int describe_instruction_1f(powerpc_state *ppc, UINT32 op, opcode_desc *d
desc->gpr.used |= REGFLAG_RZ(G_RA(op)) | REGFLAG_R(G_RB(op));
desc->flags |= OPFLAG_WRITES_MEMORY;
return TRUE;
-
+
case 0x106: /* ICBT */
case 0x1c6: /* DCCCI */
case 0x3c6: /* ICCCI */
@@ -746,14 +746,14 @@ static int describe_instruction_1f(powerpc_state *ppc, UINT32 op, opcode_desc *d
desc->gpr.used |= REGFLAG_R(G_RS(op));
desc->flags |= OPFLAG_PRIVILEGED | OPFLAG_CAN_CAUSE_EXCEPTION | OPFLAG_CAN_EXPOSE_EXTERNAL_INT;
return TRUE;
-
+
case 0x083: /* WRTEE */
if (!(ppc->cap & PPCCAP_4XX))
return FALSE;
desc->gpr.used |= REGFLAG_R(G_RS(op));
desc->flags |= OPFLAG_CAN_EXPOSE_EXTERNAL_INT;
return TRUE;
-
+
case 0x0a3: /* WRTEEI */
if (!(ppc->cap & PPCCAP_4XX))
return FALSE;
@@ -778,7 +778,7 @@ static int describe_instruction_3b(powerpc_state *ppc, UINT32 op, opcode_desc *d
if (!(ppc->cap & PPCCAP_FPU))
return FALSE;
-
+
switch (opswitch)
{
case 0x12: /* FDIVSx */
@@ -832,7 +832,7 @@ static int describe_instruction_3b(powerpc_state *ppc, UINT32 op, opcode_desc *d
static int describe_instruction_3f(powerpc_state *ppc, UINT32 op, opcode_desc *desc)
{
UINT32 opswitch = (op >> 1) & 0x3ff;
-
+
if (!(ppc->cap & PPCCAP_FPU))
return FALSE;
@@ -916,7 +916,7 @@ static int describe_instruction_3f(powerpc_state *ppc, UINT32 op, opcode_desc *d
case 0x046: /* MTFSB0x */
desc->fpr.modified |= REGFLAG_FPSCR;
return TRUE;
-
+
case 0x040: /* MCRFS */
desc->fpr.used |= REGFLAG_FPSCR;
desc->gpr.modified |= REGFLAG_CR(G_CRFD(op));
diff --git a/src/emu/inputseq.c b/src/emu/inputseq.c
index b434f640b2c..30e1f869bee 100644
--- a/src/emu/inputseq.c
+++ b/src/emu/inputseq.c
@@ -97,7 +97,7 @@ INLINE input_code input_seq_get_last(const input_seq *seq)
}
/*-------------------------------------------------
- input_seq_get_last_but_one - return the
+ input_seq_get_last_but_one - return the
last_but_one code in a sequence
-------------------------------------------------*/
diff --git a/src/emu/machine/53c810.c b/src/emu/machine/53c810.c
index 93e079e6bb4..3fa9db4e2c5 100644
--- a/src/emu/machine/53c810.c
+++ b/src/emu/machine/53c810.c
@@ -479,7 +479,7 @@ UINT8 lsi53c810_reg_r(int reg)
return (lsi810.dsa >> 24) & 0xff;
case 0x14: /* ISTAT */
// clear the interrupt on service
- if(intf->irq_callback != NULL)
+ if(intf->irq_callback != NULL)
{
intf->irq_callback(Machine, 0);
}
diff --git a/src/mame/drivers/angelkds.c b/src/mame/drivers/angelkds.c
index f71b370af73..1addbef2a27 100644
--- a/src/mame/drivers/angelkds.c
+++ b/src/mame/drivers/angelkds.c
@@ -180,9 +180,9 @@ these make the game a bit easier for testing purposes
static READ8_HANDLER( angelkds_input_r )
{
- int fake;
+ int fake;
char port1[4], port2[6];
-
+
sprintf(port1, "I8%d", 1 + offset);
sprintf(port2, "FAKE%d", 1 + offset);
fake = input_port_read(machine, port2);
diff --git a/src/mame/drivers/atarig1.c b/src/mame/drivers/atarig1.c
index 940a6b47606..1b0f74df766 100644
--- a/src/mame/drivers/atarig1.c
+++ b/src/mame/drivers/atarig1.c
@@ -126,7 +126,7 @@ static WRITE16_HANDLER( a2d_select_w )
static READ16_HANDLER( a2d_data_r )
{
char port[5];
-
+
/* Pit Fighter has no A2D, just another input port */
if (atarig1_pitfight)
return input_port_read(machine, "ADC0");
@@ -137,7 +137,7 @@ static READ16_HANDLER( a2d_data_r )
sprintf(port, "ADC%d", which_input);
return input_port_read(machine, port) << 8;
}
-
+
return 0;
}
diff --git a/src/mame/drivers/atarig42.c b/src/mame/drivers/atarig42.c
index 54f1c85f580..20b891f4ff4 100644
--- a/src/mame/drivers/atarig42.c
+++ b/src/mame/drivers/atarig42.c
@@ -94,7 +94,7 @@ static READ16_HANDLER( special_port2_r )
static WRITE16_HANDLER( a2d_select_w )
{
char port[5];
-
+
sprintf(port, "A2D%d", (offset != 0));
analog_data = input_port_read(machine, port);
}
diff --git a/src/mame/drivers/atarisy2.c b/src/mame/drivers/atarisy2.c
index b5a8f181206..feeeb0977bf 100644
--- a/src/mame/drivers/atarisy2.c
+++ b/src/mame/drivers/atarisy2.c
@@ -424,7 +424,7 @@ static WRITE16_HANDLER( adc_strobe_w )
static READ16_HANDLER( adc_r )
{
char port[5];
-
+
sprintf(port, "ADC%d", which_adc);
if (which_adc < pedal_count)
return ~input_port_read(machine, port);
@@ -436,7 +436,7 @@ static READ16_HANDLER( adc_r )
static READ8_HANDLER( leta_r )
{
char port[6];
-
+
if (pedal_count == -1) /* 720 */
{
/* special thanks to MAME Analog+ for the mapping code */
diff --git a/src/mame/drivers/blackt96.c b/src/mame/drivers/blackt96.c
index ae6cb13976a..8c40598eb0d 100644
--- a/src/mame/drivers/blackt96.c
+++ b/src/mame/drivers/blackt96.c
@@ -1,6 +1,6 @@
/*
- Black Touch '96
+ Black Touch '96
Black Touch 96
diff --git a/src/mame/drivers/brkthru.c b/src/mame/drivers/brkthru.c
index 89295150af6..74d5a0df4d0 100644
--- a/src/mame/drivers/brkthru.c
+++ b/src/mame/drivers/brkthru.c
@@ -276,9 +276,9 @@ static INPUT_PORTS_START( darwin )
PORT_DIPSETTING( 0x08, DEF_STR( Medium ) )
PORT_DIPSETTING( 0x04, DEF_STR( Hard ) )
PORT_DIPSETTING( 0x00, DEF_STR( Hardest ) )
-// PORT_DIPNAME( 0x20, 0x20, DEF_STR( Flip_Screen ) )
-// PORT_DIPSETTING( 0x20, DEF_STR( Off ) )
-// PORT_DIPSETTING( 0x00, DEF_STR( On ) )
+// PORT_DIPNAME( 0x20, 0x20, DEF_STR( Flip_Screen ) )
+// PORT_DIPSETTING( 0x20, DEF_STR( Off ) )
+// PORT_DIPSETTING( 0x00, DEF_STR( On ) )
PORT_BIT( 0x20, IP_ACTIVE_LOW, IPT_COIN1 ) PORT_CHANGED(coin_inserted, 0)
PORT_BIT( 0x40, IP_ACTIVE_LOW, IPT_COIN2 ) PORT_CHANGED(coin_inserted, 0)
PORT_BIT( 0x80, IP_ACTIVE_LOW, IPT_SERVICE1 ) PORT_CHANGED(coin_inserted, 0)
diff --git a/src/mame/drivers/gticlub.c b/src/mame/drivers/gticlub.c
index 7203af4b0ce..c176dce0600 100644
--- a/src/mame/drivers/gticlub.c
+++ b/src/mame/drivers/gticlub.c
@@ -401,8 +401,8 @@ WRITE8_HANDLER( K056230_w )
// Thunder Hurricane breaks otherwise...
if (mame_stricmp(Machine->gamedrv->name, "thunderh") != 0)
{
-// timer_set(ATTOTIME_IN_MSEC(1), NULL, 0, network_irq_gen);
-// cpunum_set_input_line(Machine, 0, INPUT_LINE_IRQ2, ASSERT_LINE);
+// timer_set(ATTOTIME_IN_MSEC(1), NULL, 0, network_irq_gen);
+// cpunum_set_input_line(Machine, 0, INPUT_LINE_IRQ2, ASSERT_LINE);
}
}
else
diff --git a/src/mame/drivers/hornet.c b/src/mame/drivers/hornet.c
index b97f07e4209..9ce76ad5562 100644
--- a/src/mame/drivers/hornet.c
+++ b/src/mame/drivers/hornet.c
@@ -688,7 +688,7 @@ static UINT32 *workram;
static READ8_HANDLER( sysreg_r )
{
UINT8 r = 0;
-
+
switch (offset)
{
case 0:
@@ -696,11 +696,11 @@ static READ8_HANDLER( sysreg_r )
case 2:
r = input_port_read_indexed(machine, offset);
break;
-
+
case 3:
r = 0xf7;
break;
-
+
case 4:
r = input_port_read_indexed(machine, 3);
break;
@@ -715,11 +715,11 @@ static WRITE8_HANDLER( sysreg_w )
case 0:
led_reg0 = data;
break;
-
+
case 1:
led_reg1 = data;
break;
-
+
case 7:
if (data & 0x80) /* CG Board 1 IRQ Ack */
cpunum_set_input_line(machine, 0, INPUT_LINE_IRQ1, CLEAR_LINE);
@@ -1099,7 +1099,7 @@ static void jamma_jvs_w(UINT8 data)
return;
jvs_sdata[jvs_sdata_ptr] = data;
jvs_sdata_ptr++;
-
+
if (jvs_sdata_ptr >= 3 && jvs_sdata_ptr >= 3 + jvs_sdata[2])
jamma_jvs_cmd_exec();
}
@@ -1164,7 +1164,7 @@ static void jamma_jvs_cmd_exec(void)
sync = jvs_sdata[0];
node = jvs_sdata[1];
byte_num = jvs_sdata[2];
-
+
length = jvs_decode_data(&jvs_sdata[3], data, byte_num-1);
/*
diff --git a/src/mame/drivers/imolagp.c b/src/mame/drivers/imolagp.c
index 79dfe3a193c..ed78ef4fa0b 100644
--- a/src/mame/drivers/imolagp.c
+++ b/src/mame/drivers/imolagp.c
@@ -487,16 +487,16 @@ static INPUT_PORTS_START( imolagp )
PORT_DIPSETTING( 0x80, DEF_STR( On ) )
PORT_START /* 2800 */ /* speed: 08 00 0F 1C 0F 00 1E 3D */
-// PORT_DIPNAME( 0x03, 0x03, "Pedal" )
-// PORT_DIPSETTING( 0x01, "STOPPED" )
-// PORT_DIPSETTING( 0x00, "SLOW" )
-// PORT_DIPSETTING( 0x02, "MEDIUM" )
-// PORT_DIPSETTING( 0x03, "FAST" )
+// PORT_DIPNAME( 0x03, 0x03, "Pedal" )
+// PORT_DIPSETTING( 0x01, "STOPPED" )
+// PORT_DIPSETTING( 0x00, "SLOW" )
+// PORT_DIPSETTING( 0x02, "MEDIUM" )
+// PORT_DIPSETTING( 0x03, "FAST" )
PORT_BIT( 0x01, IP_ACTIVE_LOW, IPT_BUTTON1 )
PORT_BIT( 0x02, IP_ACTIVE_LOW, IPT_BUTTON2 )
-// PORT_DIPNAME( 0x04, 0x04, "Stick Shift" )
-// PORT_DIPSETTING( 0x0, DEF_STR(Low) )
-// PORT_DIPSETTING( 0x4, DEF_STR(High) )
+// PORT_DIPNAME( 0x04, 0x04, "Stick Shift" )
+// PORT_DIPSETTING( 0x0, DEF_STR(Low) )
+// PORT_DIPSETTING( 0x4, DEF_STR(High) )
PORT_BIT( 0x04, IP_ACTIVE_LOW, IPT_BUTTON3 )
PORT_BIT( 0x08, IP_ACTIVE_LOW, IPT_COIN1 )
PORT_BIT( 0x10, IP_ACTIVE_LOW, IPT_COIN2 )
diff --git a/src/mame/drivers/itgambl2.c b/src/mame/drivers/itgambl2.c
index 5f8f257c9bf..7983093cb62 100644
--- a/src/mame/drivers/itgambl2.c
+++ b/src/mame/drivers/itgambl2.c
@@ -34,7 +34,7 @@
ROMs: 1x (up to) 27C2000 or similar (sound).
3x or 4x 27C4001 or similar (graphics).
-
+
Connectors: 1x 28x2 edge connector.
1x RS232 connector.
1x 14 legs connector.
@@ -280,7 +280,7 @@ ROMs:
1x 27C2000 (s)
3x M27C4001 (1, 2, 3)
-
+
Note:
1x 28x2 edge connector
diff --git a/src/mame/drivers/itgamble.c b/src/mame/drivers/itgamble.c
index 19e20af4e37..6b0672ee13d 100644
--- a/src/mame/drivers/itgamble.c
+++ b/src/mame/drivers/itgamble.c
@@ -30,7 +30,7 @@
ROMs: 1x (up to) 27C2001 or similar (sound).
2x or more 27C4001 or similar (graphics).
-
+
Timekeeping: 1x Dallas DS1302 Trickle Charge Timekeeping Chip (optional).
Connectors: 1x 28x2 edge connector.
@@ -446,8 +446,8 @@ Note:
1x 12 legs connector
1x 50 legs flat cable connector
1x 12x2 switches dip
-1x trimmer (volume)
-1x trimmer (spark)
+1x trimmer (volume)
+1x trimmer (spark)
---------------------------------------
diff --git a/src/mame/drivers/model3.c b/src/mame/drivers/model3.c
index 7f98ec4434b..61818b7c141 100644
--- a/src/mame/drivers/model3.c
+++ b/src/mame/drivers/model3.c
@@ -811,7 +811,7 @@ static UINT32 scsi_fetch(UINT32 dsp)
static void scsi_irq_callback(running_machine *machine, int state)
{
scsi_irq_state = state;
-// model3_irq_state |= irq_enable & ~0x60; /* FIXME: enable only SCSI interrupt */
+// model3_irq_state |= irq_enable & ~0x60; /* FIXME: enable only SCSI interrupt */
update_irq_state(machine);
}
diff --git a/src/mame/drivers/ms32.c b/src/mame/drivers/ms32.c
index 30f20d25e5a..ae571962b63 100644
--- a/src/mame/drivers/ms32.c
+++ b/src/mame/drivers/ms32.c
@@ -1133,7 +1133,7 @@ static INPUT_PORTS_START( wpksocv2 )
PORT_DIPNAME( 0xc0, 0x00, DEF_STR( Region ) ) PORT_DIPLOCATION("SW3:2,1")
PORT_DIPSETTING( 0x40, DEF_STR( USA ) )
PORT_DIPSETTING( 0x00, DEF_STR( World ) )
-// PORT_DIPSETTING( 0x80, "?" )
+// PORT_DIPSETTING( 0x80, "?" )
PORT_DIPSETTING( 0xc0, DEF_STR( Japan ) )
PORT_DIPNAME( 0x20, 0x00, "Tickets" ) PORT_DIPLOCATION("SW3:3")
PORT_DIPSETTING( 0x00, DEF_STR( Off ) )
diff --git a/src/mame/drivers/nmk16.c b/src/mame/drivers/nmk16.c
index c576f1e91bc..4843036ba35 100644
--- a/src/mame/drivers/nmk16.c
+++ b/src/mame/drivers/nmk16.c
@@ -4351,7 +4351,7 @@ static MACHINE_DRIVER_START( gunnail )
/* video hardware */
MDRV_SCREEN_ADD("main", RASTER)
MDRV_SCREEN_REFRESH_RATE(56)
-// MDRV_SCREEN_VBLANK_TIME(ATTOSECONDS_IN_USEC(2500) /* not accurate */)
+// MDRV_SCREEN_VBLANK_TIME(ATTOSECONDS_IN_USEC(2500) /* not accurate */)
MDRV_SCREEN_FORMAT(BITMAP_FORMAT_INDEXED16)
MDRV_SCREEN_SIZE(512, 256)
MDRV_SCREEN_VISIBLE_AREA(0*8, 48*8-1, 2*8, 30*8-1)
diff --git a/src/mame/drivers/nwk-tr.c b/src/mame/drivers/nwk-tr.c
index ea45b373d18..c51026070a7 100644
--- a/src/mame/drivers/nwk-tr.c
+++ b/src/mame/drivers/nwk-tr.c
@@ -951,8 +951,8 @@ static DRIVER_INIT( nwktr )
K056800_init(sound_irq_callback);
K033906_init();
-// cpunum_set_info_fct(0, CPUINFO_PTR_SPU_TX_HANDLER, (genf *)jamma_jvs_w);
-// cpunum_set_info_fct(0, CPUINFO_PTR_SPU_RX_HANDLER, (genf *)jamma_jvs_r);
+// cpunum_set_info_fct(0, CPUINFO_PTR_SPU_TX_HANDLER, (genf *)jamma_jvs_w);
+// cpunum_set_info_fct(0, CPUINFO_PTR_SPU_RX_HANDLER, (genf *)jamma_jvs_r);
adc1213x_init(0, adc12138_input_callback);
}
diff --git a/src/mame/drivers/seibuspi.c b/src/mame/drivers/seibuspi.c
index 5ffde99962f..e9f4f5c6c97 100644
--- a/src/mame/drivers/seibuspi.c
+++ b/src/mame/drivers/seibuspi.c
@@ -1293,7 +1293,7 @@ static CUSTOM_INPUT( ejanhs_encode )
static const UINT8 encoding[] = { 0x02, 0x10, 0x03, 0x18, 0x04, 0x20, 0x05, 0x28, 0x06, 0x30, 0x07 };
input_port_value state = input_port_read(field->port->machine, param);
int bit;
-
+
for (bit = 0; bit < ARRAY_LENGTH(encoding); bit++)
if (state & (1 << bit))
return encoding[bit];
diff --git a/src/mame/drivers/tecmosys.c b/src/mame/drivers/tecmosys.c
index 97b00fe8a22..d9e2496da65 100644
--- a/src/mame/drivers/tecmosys.c
+++ b/src/mame/drivers/tecmosys.c
@@ -305,12 +305,12 @@ static WRITE16_HANDLER( sound_w )
}
/*
- 880000 and 880002 might be video related,
- see sub @ 68k:002e5e where they are written if the screen is set to inverted.
- Also, irq code at 22c4 :
- - 880000 & 00, execute irq code
- - 880000 & 01, scroll?
- - 880000 & 03, crash
+ 880000 and 880002 might be video related,
+ see sub @ 68k:002e5e where they are written if the screen is set to inverted.
+ Also, irq code at 22c4 :
+ - 880000 & 00, execute irq code
+ - 880000 & 01, scroll?
+ - 880000 & 03, crash
*/
@@ -840,22 +840,22 @@ static VIDEO_UPDATE(deroon)
tecmosys_do_final_mix(bitmap);
/*
- popmessage("%04x %04x %04x %04x | %04x %04x %04x %04x | %04x %04x %04x %04x | %04x %04x %04x %04x | %04x %04x %04x %04x | %04x %04x %04x %04x",
- tecmosys_880000regs[0x0], tecmosys_880000regs[0x1], tecmosys_880000regs[0x2], tecmosys_880000regs[0x3],
- tecmosys_880000regs[0x4], tecmosys_880000regs[0x5], tecmosys_880000regs[0x6], tecmosys_880000regs[0x7],
- tecmosys_880000regs[0x8], tecmosys_880000regs[0x9], tecmosys_880000regs[0xa], tecmosys_880000regs[0xb],
- tecmosys_880000regs[0xc], tecmosys_880000regs[0xd], tecmosys_880000regs[0xe], tecmosys_880000regs[0xf],
- tecmosys_880000regs[0x10], tecmosys_880000regs[0x11], tecmosys_880000regs[0x12], tecmosys_880000regs[0x13],
- tecmosys_880000regs[0x14], tecmosys_880000regs[0x15], tecmosys_880000regs[0x16], tecmosys_880000regs[0x17]);
+ popmessage("%04x %04x %04x %04x | %04x %04x %04x %04x | %04x %04x %04x %04x | %04x %04x %04x %04x | %04x %04x %04x %04x | %04x %04x %04x %04x",
+ tecmosys_880000regs[0x0], tecmosys_880000regs[0x1], tecmosys_880000regs[0x2], tecmosys_880000regs[0x3],
+ tecmosys_880000regs[0x4], tecmosys_880000regs[0x5], tecmosys_880000regs[0x6], tecmosys_880000regs[0x7],
+ tecmosys_880000regs[0x8], tecmosys_880000regs[0x9], tecmosys_880000regs[0xa], tecmosys_880000regs[0xb],
+ tecmosys_880000regs[0xc], tecmosys_880000regs[0xd], tecmosys_880000regs[0xe], tecmosys_880000regs[0xf],
+ tecmosys_880000regs[0x10], tecmosys_880000regs[0x11], tecmosys_880000regs[0x12], tecmosys_880000regs[0x13],
+ tecmosys_880000regs[0x14], tecmosys_880000regs[0x15], tecmosys_880000regs[0x16], tecmosys_880000regs[0x17]);
*/
-// popmessage("%04x %04x %04x | %04x %04x %04x",
-// tecmosys_c00000regs[0], tecmosys_c00000regs[1], tecmosys_c00000regs[2],
-// tecmosys_c80000regs[0], tecmosys_c80000regs[1], tecmosys_c80000regs[2]);
+// popmessage("%04x %04x %04x | %04x %04x %04x",
+// tecmosys_c00000regs[0], tecmosys_c00000regs[1], tecmosys_c00000regs[2],
+// tecmosys_c80000regs[0], tecmosys_c80000regs[1], tecmosys_c80000regs[2]);
-// popmessage("%04x %04x %04x | %04x %04x %04x",
-// tecmosys_b00000regs[0], tecmosys_b00000regs[1], tecmosys_b00000regs[2],
-// tecmosys_a80000regs[0], tecmosys_a80000regs[1], tecmosys_a80000regs[2]);
+// popmessage("%04x %04x %04x | %04x %04x %04x",
+// tecmosys_b00000regs[0], tecmosys_b00000regs[1], tecmosys_b00000regs[2],
+// tecmosys_a80000regs[0], tecmosys_a80000regs[1], tecmosys_a80000regs[2]);
// prepare sprites for NEXT frame - causes 1 frame palette errors, but prevents sprite lag in tkdensho, which is correct?
tecmosys_render_sprites_to_bitmap(bitmap, tecmosys_880000regs[0x0], tecmosys_880000regs[0x1]);
diff --git a/src/mame/drivers/thayers.c b/src/mame/drivers/thayers.c
index f592642d307..002f8efb984 100644
--- a/src/mame/drivers/thayers.c
+++ b/src/mame/drivers/thayers.c
@@ -416,51 +416,51 @@ static INPUT_PORTS_START( thayers )
/* "Scan codes" heisted from Daphne - need to be tested! */
/*
- PORT_START_TAG("THAYERS_ACTIONS")
- PORT_BIT( 0x30, IP_ACTIVE_HIGH, IPT_OTHER ) PORT_NAME( DEF_STR( No ) ) PORT_CODE( KEYCODE_DEL_PAD )
- PORT_BIT( 0x31, IP_ACTIVE_HIGH, IPT_OTHER ) PORT_NAME( DEF_STR( Yes ) ) PORT_CODE( KEYCODE_0_PAD )
- PORT_BIT( 0x32, IP_ACTIVE_HIGH, IPT_OTHER ) PORT_NAME( "Items" ) PORT_CODE( KEYCODE_1_PAD )
- PORT_BIT( 0x33, IP_ACTIVE_HIGH, IPT_OTHER ) PORT_NAME( "Drop Item" ) PORT_CODE( KEYCODE_2_PAD )
- PORT_BIT( 0x34, IP_ACTIVE_HIGH, IPT_OTHER ) PORT_NAME( "Give Score" ) PORT_CODE( KEYCODE_3_PAD )
- PORT_BIT( 0x35, IP_ACTIVE_HIGH, IPT_OTHER ) PORT_NAME( "Replay" ) PORT_CODE( KEYCODE_4_PAD )
- PORT_BIT( 0x36, IP_ACTIVE_HIGH, IPT_OTHER ) PORT_NAME( "Combine Action" ) PORT_CODE( KEYCODE_6_PAD )
- PORT_BIT( 0x37, IP_ACTIVE_HIGH, IPT_OTHER ) PORT_NAME( "Save Game" ) PORT_CODE( KEYCODE_7_PAD )
- PORT_BIT( 0x38, IP_ACTIVE_HIGH, IPT_OTHER ) PORT_NAME( "Update" ) PORT_CODE( KEYCODE_8_PAD )
- PORT_BIT( 0x39, IP_ACTIVE_HIGH, IPT_OTHER ) PORT_NAME( "Hint" ) PORT_CODE( KEYCODE_9_PAD )
-
- PORT_START_TAG("THAYERS_LETTERS")
- PORT_BIT( 0x41, IP_ACTIVE_HIGH, IPT_OTHER ) PORT_NAME( "A" ) PORT_CODE( KEYCODE_A )
- PORT_BIT( 0x42, IP_ACTIVE_HIGH, IPT_OTHER ) PORT_NAME( "B - Silver Wheat" ) PORT_CODE( KEYCODE_B )
- PORT_BIT( 0x43, IP_ACTIVE_HIGH, IPT_OTHER ) PORT_NAME( "C - Spell of Seeing" ) PORT_CODE( KEYCODE_C )
- PORT_BIT( 0x44, IP_ACTIVE_HIGH, IPT_OTHER ) PORT_NAME( "D - Great Circlet" ) PORT_CODE( KEYCODE_D )
- PORT_BIT( 0x45, IP_ACTIVE_HIGH, IPT_OTHER ) PORT_NAME( "E - Black Mace" ) PORT_CODE( KEYCODE_E )
- PORT_BIT( 0x46, IP_ACTIVE_HIGH, IPT_OTHER ) PORT_NAME( "F - Hunting Horn" ) PORT_CODE( KEYCODE_F )
- PORT_BIT( 0x47, IP_ACTIVE_HIGH, IPT_OTHER ) PORT_NAME( "G - Long Bow" ) PORT_CODE( KEYCODE_G )
- PORT_BIT( 0x48, IP_ACTIVE_HIGH, IPT_OTHER ) PORT_NAME( "H - Medallion" ) PORT_CODE( KEYCODE_H )
- PORT_BIT( 0x49, IP_ACTIVE_HIGH, IPT_OTHER ) PORT_NAME( "I - Crown" ) PORT_CODE( KEYCODE_I )
- PORT_BIT( 0x4a, IP_ACTIVE_HIGH, IPT_OTHER ) PORT_NAME( "J - Onyx Seal" ) PORT_CODE( KEYCODE_J )
- PORT_BIT( 0x4b, IP_ACTIVE_HIGH, IPT_OTHER ) PORT_NAME( "K - Orb of Quoid" ) PORT_CODE( KEYCODE_K )
- PORT_BIT( 0x4c, IP_ACTIVE_HIGH, IPT_OTHER ) PORT_NAME( "L" ) PORT_CODE( KEYCODE_L )
- PORT_BIT( 0x4d, IP_ACTIVE_HIGH, IPT_OTHER ) PORT_NAME( "M - Spell of Understanding" ) PORT_CODE( KEYCODE_M )
- PORT_BIT( 0x4e, IP_ACTIVE_HIGH, IPT_OTHER ) PORT_NAME( "N - Staff" ) PORT_CODE( KEYCODE_N )
- PORT_BIT( 0x4f, IP_ACTIVE_HIGH, IPT_OTHER ) PORT_NAME( "O - Crystal" ) PORT_CODE( KEYCODE_O )
- PORT_BIT( 0x50, IP_ACTIVE_HIGH, IPT_OTHER ) PORT_NAME( "P" ) PORT_CODE( KEYCODE_P )
- PORT_BIT( 0x51, IP_ACTIVE_HIGH, IPT_OTHER ) PORT_NAME( "Q" ) PORT_CODE( KEYCODE_Q )
- PORT_BIT( 0x52, IP_ACTIVE_HIGH, IPT_OTHER ) PORT_NAME( "R - Blood Sword" ) PORT_CODE( KEYCODE_R )
- PORT_BIT( 0x53, IP_ACTIVE_HIGH, IPT_OTHER ) PORT_NAME( "S - Dagger" ) PORT_CODE( KEYCODE_S )
- PORT_BIT( 0x54, IP_ACTIVE_HIGH, IPT_OTHER ) PORT_NAME( "T - Chalice" ) PORT_CODE( KEYCODE_T )
- PORT_BIT( 0x55, IP_ACTIVE_HIGH, IPT_OTHER ) PORT_NAME( "U - Cold Fire" ) PORT_CODE( KEYCODE_U )
- PORT_BIT( 0x56, IP_ACTIVE_HIGH, IPT_OTHER ) PORT_NAME( "V - Shield" ) PORT_CODE( KEYCODE_V )
- PORT_BIT( 0x57, IP_ACTIVE_HIGH, IPT_OTHER ) PORT_NAME( "W - Amulet" ) PORT_CODE( KEYCODE_W )
- PORT_BIT( 0x58, IP_ACTIVE_HIGH, IPT_OTHER ) PORT_NAME( "X - Scepter" ) PORT_CODE( KEYCODE_X )
- PORT_BIT( 0x59, IP_ACTIVE_HIGH, IPT_OTHER ) PORT_NAME( "Y - Coins" ) PORT_CODE( KEYCODE_Y )
- PORT_BIT( 0x5a, IP_ACTIVE_HIGH, IPT_OTHER ) PORT_NAME( "Z - Spell of Release" ) PORT_CODE( KEYCODE_Z )
-
- PORT_START_TAG("THAYERS_NUMBERS")
- PORT_BIT( 0x80, IP_ACTIVE_HIGH, IPT_OTHER ) PORT_NAME( "1 - Clear" ) PORT_CODE( KEYCODE_LCONTROL )
- PORT_BIT( 0x81, IP_ACTIVE_HIGH, IPT_OTHER ) PORT_NAME( "2" ) PORT_CODE( KEYCODE_RCONTROL )
- PORT_BIT( 0x82, IP_ACTIVE_HIGH, IPT_OTHER ) PORT_NAME( "3 - Enter" ) PORT_CODE( KEYCODE_ENTER )
- PORT_BIT( 0x83, IP_ACTIVE_HIGH, IPT_OTHER ) PORT_NAME( "4 - Space" ) PORT_CODE( KEYCODE_SPACE )
+ PORT_START_TAG("THAYERS_ACTIONS")
+ PORT_BIT( 0x30, IP_ACTIVE_HIGH, IPT_OTHER ) PORT_NAME( DEF_STR( No ) ) PORT_CODE( KEYCODE_DEL_PAD )
+ PORT_BIT( 0x31, IP_ACTIVE_HIGH, IPT_OTHER ) PORT_NAME( DEF_STR( Yes ) ) PORT_CODE( KEYCODE_0_PAD )
+ PORT_BIT( 0x32, IP_ACTIVE_HIGH, IPT_OTHER ) PORT_NAME( "Items" ) PORT_CODE( KEYCODE_1_PAD )
+ PORT_BIT( 0x33, IP_ACTIVE_HIGH, IPT_OTHER ) PORT_NAME( "Drop Item" ) PORT_CODE( KEYCODE_2_PAD )
+ PORT_BIT( 0x34, IP_ACTIVE_HIGH, IPT_OTHER ) PORT_NAME( "Give Score" ) PORT_CODE( KEYCODE_3_PAD )
+ PORT_BIT( 0x35, IP_ACTIVE_HIGH, IPT_OTHER ) PORT_NAME( "Replay" ) PORT_CODE( KEYCODE_4_PAD )
+ PORT_BIT( 0x36, IP_ACTIVE_HIGH, IPT_OTHER ) PORT_NAME( "Combine Action" ) PORT_CODE( KEYCODE_6_PAD )
+ PORT_BIT( 0x37, IP_ACTIVE_HIGH, IPT_OTHER ) PORT_NAME( "Save Game" ) PORT_CODE( KEYCODE_7_PAD )
+ PORT_BIT( 0x38, IP_ACTIVE_HIGH, IPT_OTHER ) PORT_NAME( "Update" ) PORT_CODE( KEYCODE_8_PAD )
+ PORT_BIT( 0x39, IP_ACTIVE_HIGH, IPT_OTHER ) PORT_NAME( "Hint" ) PORT_CODE( KEYCODE_9_PAD )
+
+ PORT_START_TAG("THAYERS_LETTERS")
+ PORT_BIT( 0x41, IP_ACTIVE_HIGH, IPT_OTHER ) PORT_NAME( "A" ) PORT_CODE( KEYCODE_A )
+ PORT_BIT( 0x42, IP_ACTIVE_HIGH, IPT_OTHER ) PORT_NAME( "B - Silver Wheat" ) PORT_CODE( KEYCODE_B )
+ PORT_BIT( 0x43, IP_ACTIVE_HIGH, IPT_OTHER ) PORT_NAME( "C - Spell of Seeing" ) PORT_CODE( KEYCODE_C )
+ PORT_BIT( 0x44, IP_ACTIVE_HIGH, IPT_OTHER ) PORT_NAME( "D - Great Circlet" ) PORT_CODE( KEYCODE_D )
+ PORT_BIT( 0x45, IP_ACTIVE_HIGH, IPT_OTHER ) PORT_NAME( "E - Black Mace" ) PORT_CODE( KEYCODE_E )
+ PORT_BIT( 0x46, IP_ACTIVE_HIGH, IPT_OTHER ) PORT_NAME( "F - Hunting Horn" ) PORT_CODE( KEYCODE_F )
+ PORT_BIT( 0x47, IP_ACTIVE_HIGH, IPT_OTHER ) PORT_NAME( "G - Long Bow" ) PORT_CODE( KEYCODE_G )
+ PORT_BIT( 0x48, IP_ACTIVE_HIGH, IPT_OTHER ) PORT_NAME( "H - Medallion" ) PORT_CODE( KEYCODE_H )
+ PORT_BIT( 0x49, IP_ACTIVE_HIGH, IPT_OTHER ) PORT_NAME( "I - Crown" ) PORT_CODE( KEYCODE_I )
+ PORT_BIT( 0x4a, IP_ACTIVE_HIGH, IPT_OTHER ) PORT_NAME( "J - Onyx Seal" ) PORT_CODE( KEYCODE_J )
+ PORT_BIT( 0x4b, IP_ACTIVE_HIGH, IPT_OTHER ) PORT_NAME( "K - Orb of Quoid" ) PORT_CODE( KEYCODE_K )
+ PORT_BIT( 0x4c, IP_ACTIVE_HIGH, IPT_OTHER ) PORT_NAME( "L" ) PORT_CODE( KEYCODE_L )
+ PORT_BIT( 0x4d, IP_ACTIVE_HIGH, IPT_OTHER ) PORT_NAME( "M - Spell of Understanding" ) PORT_CODE( KEYCODE_M )
+ PORT_BIT( 0x4e, IP_ACTIVE_HIGH, IPT_OTHER ) PORT_NAME( "N - Staff" ) PORT_CODE( KEYCODE_N )
+ PORT_BIT( 0x4f, IP_ACTIVE_HIGH, IPT_OTHER ) PORT_NAME( "O - Crystal" ) PORT_CODE( KEYCODE_O )
+ PORT_BIT( 0x50, IP_ACTIVE_HIGH, IPT_OTHER ) PORT_NAME( "P" ) PORT_CODE( KEYCODE_P )
+ PORT_BIT( 0x51, IP_ACTIVE_HIGH, IPT_OTHER ) PORT_NAME( "Q" ) PORT_CODE( KEYCODE_Q )
+ PORT_BIT( 0x52, IP_ACTIVE_HIGH, IPT_OTHER ) PORT_NAME( "R - Blood Sword" ) PORT_CODE( KEYCODE_R )
+ PORT_BIT( 0x53, IP_ACTIVE_HIGH, IPT_OTHER ) PORT_NAME( "S - Dagger" ) PORT_CODE( KEYCODE_S )
+ PORT_BIT( 0x54, IP_ACTIVE_HIGH, IPT_OTHER ) PORT_NAME( "T - Chalice" ) PORT_CODE( KEYCODE_T )
+ PORT_BIT( 0x55, IP_ACTIVE_HIGH, IPT_OTHER ) PORT_NAME( "U - Cold Fire" ) PORT_CODE( KEYCODE_U )
+ PORT_BIT( 0x56, IP_ACTIVE_HIGH, IPT_OTHER ) PORT_NAME( "V - Shield" ) PORT_CODE( KEYCODE_V )
+ PORT_BIT( 0x57, IP_ACTIVE_HIGH, IPT_OTHER ) PORT_NAME( "W - Amulet" ) PORT_CODE( KEYCODE_W )
+ PORT_BIT( 0x58, IP_ACTIVE_HIGH, IPT_OTHER ) PORT_NAME( "X - Scepter" ) PORT_CODE( KEYCODE_X )
+ PORT_BIT( 0x59, IP_ACTIVE_HIGH, IPT_OTHER ) PORT_NAME( "Y - Coins" ) PORT_CODE( KEYCODE_Y )
+ PORT_BIT( 0x5a, IP_ACTIVE_HIGH, IPT_OTHER ) PORT_NAME( "Z - Spell of Release" ) PORT_CODE( KEYCODE_Z )
+
+ PORT_START_TAG("THAYERS_NUMBERS")
+ PORT_BIT( 0x80, IP_ACTIVE_HIGH, IPT_OTHER ) PORT_NAME( "1 - Clear" ) PORT_CODE( KEYCODE_LCONTROL )
+ PORT_BIT( 0x81, IP_ACTIVE_HIGH, IPT_OTHER ) PORT_NAME( "2" ) PORT_CODE( KEYCODE_RCONTROL )
+ PORT_BIT( 0x82, IP_ACTIVE_HIGH, IPT_OTHER ) PORT_NAME( "3 - Enter" ) PORT_CODE( KEYCODE_ENTER )
+ PORT_BIT( 0x83, IP_ACTIVE_HIGH, IPT_OTHER ) PORT_NAME( "4 - Space" ) PORT_CODE( KEYCODE_SPACE )
*/
PORT_START_TAG("R0")
PORT_BIT( 0x01, IP_ACTIVE_LOW, IPT_OTHER )
diff --git a/src/mame/machine/tecmosys.c b/src/mame/machine/tecmosys.c
index a22c25633e8..370aa23bb2d 100644
--- a/src/mame/machine/tecmosys.c
+++ b/src/mame/machine/tecmosys.c
@@ -1,31 +1,31 @@
/* tecmosys protection related functions */
/*
- The device validates a password,
- then uploads the size of a code upload followed by the code upload itself.
- After that, it uploads 4 ranges of code to checksum, followed by the 4 checksums.
- The 68K does the checksumming, and returns the results to the protection device.
-
- Apart from inital protection calls and code upload, the vblank in both games writes
- info to the protection but they seem to ignore the returned data.
- Maybe the protection is tied to something else, or maybe it was preliminary work on
- further security.
- This is what happens in the vblank:
- - prot_w( 0xff )
- - val = prot_r()
- - prot_w( checksum1[val] )
- (The area following checksum1 is the code upload in deroon, and active RAM in tkdensho,
- so the value sent may be meaningless.)
-
- There is provision for calling the protection read/write functions from two of the trap 0xf switch
- statements in the 68K, but I don't see it being used anywhere.
-
- It looks like the code upload is very plain, it can only be 0xff bytes long, and not contain the byte 0xff.
- The checksum ranges can't contain 0xff either, although the checksum values can.
- I'd be very interested in putting some trojan ROMs together if anyone has a board to run them on.
- It might be possible to use one set of ROMs to get the checksum ranges,
- and another set with dump code places outside those ranges.
- You can get me at nuapete@hotmail.com
+ The device validates a password,
+ then uploads the size of a code upload followed by the code upload itself.
+ After that, it uploads 4 ranges of code to checksum, followed by the 4 checksums.
+ The 68K does the checksumming, and returns the results to the protection device.
+
+ Apart from inital protection calls and code upload, the vblank in both games writes
+ info to the protection but they seem to ignore the returned data.
+ Maybe the protection is tied to something else, or maybe it was preliminary work on
+ further security.
+ This is what happens in the vblank:
+ - prot_w( 0xff )
+ - val = prot_r()
+ - prot_w( checksum1[val] )
+ (The area following checksum1 is the code upload in deroon, and active RAM in tkdensho,
+ so the value sent may be meaningless.)
+
+ There is provision for calling the protection read/write functions from two of the trap 0xf switch
+ statements in the 68K, but I don't see it being used anywhere.
+
+ It looks like the code upload is very plain, it can only be 0xff bytes long, and not contain the byte 0xff.
+ The checksum ranges can't contain 0xff either, although the checksum values can.
+ I'd be very interested in putting some trojan ROMs together if anyone has a board to run them on.
+ It might be possible to use one set of ROMs to get the checksum ranges,
+ and another set with dump code places outside those ranges.
+ You can get me at nuapete@hotmail.com
*/
#include "driver.h"
diff --git a/src/mame/video/aeroboto.c b/src/mame/video/aeroboto.c
index 02c0a52c537..c7c9c6a4383 100644
--- a/src/mame/video/aeroboto.c
+++ b/src/mame/video/aeroboto.c
@@ -76,7 +76,7 @@ VIDEO_START( aeroboto )
READ8_HANDLER( aeroboto_in0_r )
{
char port[4];
-
+
sprintf(port, "IN%d", flip_screen_get() ? 1 : 0);
return input_port_read(machine, port);
}
diff --git a/src/mame/video/snookr10.c b/src/mame/video/snookr10.c
index ade43524583..6063cf6810a 100644
--- a/src/mame/video/snookr10.c
+++ b/src/mame/video/snookr10.c
@@ -18,7 +18,7 @@
Resistor Network for all PCBs:
-
+
74LS373
+-------+
| 02|--> 1 KOhms resistor --> \
diff --git a/src/version.c b/src/version.c
index 3d5e9a0e9b7..749efddf233 100644
--- a/src/version.c
+++ b/src/version.c
@@ -9,4 +9,4 @@
***************************************************************************/
-const char build_version[] = "0.125u3 ("__DATE__")";
+const char build_version[] = "0.125u4 ("__DATE__")";