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author | arbee <rb6502@users.noreply.github.com> | 2018-02-08 15:55:06 -0500 |
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committer | arbee <rb6502@users.noreply.github.com> | 2018-02-08 15:55:06 -0500 |
commit | 15556478e7f2796688bd654b9ea7806d5b07b889 (patch) | |
tree | a9280349f995c747c0f875d19b7804ba431c9400 | |
parent | cde11d74f7d440bf7213e15800083808890af432 (diff) |
Add CPU notes (nw)
-rw-r--r-- | src/mame/drivers/inteladv.cpp | 11 |
1 files changed, 11 insertions, 0 deletions
diff --git a/src/mame/drivers/inteladv.cpp b/src/mame/drivers/inteladv.cpp index f6d0f050a55..84a9de22adc 100644 --- a/src/mame/drivers/inteladv.cpp +++ b/src/mame/drivers/inteladv.cpp @@ -4,6 +4,17 @@ inteladv.cpp: VTech Intelligence Advance E/R Lerncomputer + CPU is a Rockwell R65C02 (the dead-end bit-twiddling 65C02, as opposed to + the WDC version that the 65816 is back-compatible with) with some customizations: + + JMP (ZP) accepts a 3rd ZP location after the 16-bit address to jump to which + contains a bank value for the ROM window at 0x4000. I believe it's in 0x4000 + byte segments, as the first long jump uses a value of 4 and that leads to + the correct start of a subroutine at 0x10000 + the offset. + + JSR / RTS may also push and pop an additional byte for the bank offset but + this is not proven yet. + ***************************************************************************/ #include "emu.h" |