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author David Haywood <davidhaywood@users.noreply.github.com>2017-10-17 22:05:49 +0100
committer David Haywood <davidhaywood@users.noreply.github.com>2017-10-17 22:05:49 +0100
commit154aee25d1025f0d88a23acdaaf819a6dcef3055 (patch)
tree44de5d90212e7c52b899558c35d6d351d16dff45
parente37cf6f65978d230bfdaacf21e216d73949a56e1 (diff)
fix an error that was preventing dc from booting (my own mistake, was testing something at the time) and document what were a few more differences between the cores (nw)
-rw-r--r--src/devices/cpu/sh/sh.cpp5
-rw-r--r--src/devices/cpu/sh/sh4.cpp9
2 files changed, 8 insertions, 6 deletions
diff --git a/src/devices/cpu/sh/sh.cpp b/src/devices/cpu/sh/sh.cpp
index dcc9ebbf7b9..bdc0977e3fc 100644
--- a/src/devices/cpu/sh/sh.cpp
+++ b/src/devices/cpu/sh/sh.cpp
@@ -758,7 +758,7 @@ void sh_common_execution::EXTUW(uint32_t m, uint32_t n)
void sh_common_execution::JMP(uint32_t m)
{
m_sh2_state->m_delay = m_sh2_state->ea = m_sh2_state->r[m];
- m_sh2_state->icount--; // not in SH4 implementation?
+ //m_sh2_state->icount--; // not in SH4 implementation?
}
/* JSR @Rm */
@@ -1303,6 +1303,7 @@ void sh_common_execution::OR(uint32_t m, uint32_t n)
void sh_common_execution::ORI(uint32_t i)
{
m_sh2_state->r[0] |= i;
+ m_sh2_state->icount -= 2; // not in SH2 implementation?
}
/* OR.B #imm,@(R0,GBR) */
@@ -1314,7 +1315,7 @@ void sh_common_execution::ORM(uint32_t i)
temp = RB( m_sh2_state->ea );
temp |= i;
WB( m_sh2_state->ea, temp );
- m_sh2_state->icount -= 2;
+ //m_sh2_state->icount -= 2; // not in SH4 implementation?
}
/* ROTCL Rn */
diff --git a/src/devices/cpu/sh/sh4.cpp b/src/devices/cpu/sh/sh4.cpp
index a2e90e1fd5a..f8f38fe4522 100644
--- a/src/devices/cpu/sh/sh4.cpp
+++ b/src/devices/cpu/sh/sh4.cpp
@@ -463,15 +463,16 @@ inline void sh34_base_device::SETS(const uint16_t opcode)
/* LDC Rm,SR */
inline void sh34_base_device::LDCSR(const uint16_t opcode)
{
- // copy current registers to banked version of current register set
+ // important to store the value now so that it doesn't get affected by the bank change
+ uint32_t reg = m_sh2_state->r[Rn];
+
if ((machine().debug_flags & DEBUG_FLAG_ENABLED) != 0)
sh4_syncronize_register_bank((m_sh2_state->sr & sRB) >> 29);
- // if the register bank in the new differs from the one already in SR
if ((m_sh2_state->r[Rn] & sRB) != (m_sh2_state->sr & sRB))
sh4_change_register_bank(m_sh2_state->r[Rn] & sRB ? 1 : 0);
-
- m_sh2_state->sr = m_sh2_state->r[Rn] & SH34_FLAGS;
+
+ m_sh2_state->sr = reg & SH34_FLAGS;
sh4_exception_recompute();
}