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author MetalliC <0vetal0@gmail.com>2017-11-09 22:12:05 +0200
committer MetalliC <0vetal0@gmail.com>2017-11-09 22:12:05 +0200
commit098687350d7e7411aef46d3b40ee0aa006145586 (patch)
treeb1d620ef0e9a6e2b0f1d247198174002c5748895
parent77d60e5e3d90e14d59f95bdc0cb9b020f7a7961f (diff)
arm7: LDR/LDRM switch to Thumb mode on ARMv5T [David Haywood, MetalliC]
note - why we don't have archflags for cpu architecture versions ? this feature present not on all CPUs with Thumb IA.
-rw-r--r--src/devices/cpu/arm7/arm7ops.cpp20
1 files changed, 20 insertions, 0 deletions
diff --git a/src/devices/cpu/arm7/arm7ops.cpp b/src/devices/cpu/arm7/arm7ops.cpp
index 9f6c998abed..d3784cfc2f8 100644
--- a/src/devices/cpu/arm7/arm7ops.cpp
+++ b/src/devices/cpu/arm7/arm7ops.cpp
@@ -492,6 +492,12 @@ void arm7_cpu_device::HandleMemSingle(uint32_t insn)
R15 = (R15 & ~0x03FFFFFC) /* N Z C V I F M1 M0 */ | ((data - 4) & 0x03FFFFFC);
// LDR, PC takes 2S + 2N + 1I (5 total cycles)
ARM7_ICOUNT -= 2;
+ // TODO only ARMv5T and above
+ if (data & 1)
+ {
+ set_cpsr(GET_CPSR | T_MASK);
+ R15--;
+ }
}
else
{
@@ -1371,6 +1377,13 @@ void arm7_cpu_device::HandleMemBlock(uint32_t insn)
SwitchMode(temp & 3);
}
}
+ // TODO only ARMv5T and above
+ else
+ if (R15 & 1)
+ {
+ set_cpsr(GET_CPSR | T_MASK);
+ R15--;
+ }
// LDM PC - takes 2 extra cycles
ARM7_ICOUNT -= 2;
}
@@ -1428,6 +1441,13 @@ void arm7_cpu_device::HandleMemBlock(uint32_t insn)
SwitchMode(temp & 3);
}
}
+ // TODO only ARMv5T and above
+ else
+ if (R15 & 1)
+ {
+ set_cpsr(GET_CPSR | T_MASK);
+ R15--;
+ }
// LDM PC - takes 2 extra cycles
ARM7_ICOUNT -= 2;
}