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author couriersud <couriersud@users.noreply.github.com>2020-09-18 18:44:58 +0200
committer GitHub <noreply@github.com>2020-09-18 18:44:58 +0200
commit0348faf9ae44990e5b21deae61c46cb8f0585435 (patch)
tree19be7a401e44a7cc35b7ccc028a20295a0d80685
parent37e3cd01c2650877911cd376449c6d0b9c715a1a (diff)
parenta5879b9750c680e4c92881c6a6f6446c30d6f001 (diff)
Merge pull request #7214 from Lord-Nightmare/master
netlist: devices for MCM14524, CD4029, CD4030, CD4042, CD4049, CD4076 [Lord Nightmare]
-rw-r--r--scripts/src/netlist.lua3
-rw-r--r--src/lib/netlist/devices/nld_4029.cpp272
-rw-r--r--src/lib/netlist/devices/nld_4042.cpp120
-rw-r--r--src/lib/netlist/devices/nld_4076.cpp132
-rw-r--r--src/lib/netlist/devices/nld_roms.cpp68
-rwxr-xr-xsrc/lib/netlist/generated/lib_entries.hxx4
-rwxr-xr-xsrc/lib/netlist/generated/nld_devinc.h64
-rw-r--r--src/lib/netlist/macro/nlm_cd4xxx_lib.cpp318
-rw-r--r--src/lib/netlist/macro/nlm_roms_lib.cpp34
9 files changed, 1015 insertions, 0 deletions
diff --git a/scripts/src/netlist.lua b/scripts/src/netlist.lua
index 442074f0215..c5dec60b6b4 100644
--- a/scripts/src/netlist.lua
+++ b/scripts/src/netlist.lua
@@ -137,8 +137,11 @@ project "netlist"
MAME_DIR .. "src/lib/netlist/devices/nld_4013.cpp",
MAME_DIR .. "src/lib/netlist/devices/nld_4017.cpp",
MAME_DIR .. "src/lib/netlist/devices/nld_4020.cpp",
+ MAME_DIR .. "src/lib/netlist/devices/nld_4029.cpp",
+ MAME_DIR .. "src/lib/netlist/devices/nld_4042.cpp",
MAME_DIR .. "src/lib/netlist/devices/nld_4053.cpp",
MAME_DIR .. "src/lib/netlist/devices/nld_4066.cpp",
+ MAME_DIR .. "src/lib/netlist/devices/nld_4076.cpp",
MAME_DIR .. "src/lib/netlist/devices/nld_4316.cpp",
MAME_DIR .. "src/lib/netlist/devices/nld_7448.cpp",
MAME_DIR .. "src/lib/netlist/devices/nld_7450.cpp",
diff --git a/src/lib/netlist/devices/nld_4029.cpp b/src/lib/netlist/devices/nld_4029.cpp
new file mode 100644
index 00000000000..2e18ba9f4e1
--- /dev/null
+++ b/src/lib/netlist/devices/nld_4029.cpp
@@ -0,0 +1,272 @@
+// license:GPL-2.0+
+// copyright-holders:Couriersud, Jonathan Gevaryahu
+/*
+ * nld_4029.cpp
+ *
+ * CD4029BM/CD4029BC Presettable Binary/Decade Up/Down Counter
+ *
+ * +--------------+
+ * PE |1 ++ 16| VDD
+ * Q4 |2 15| CLK
+ * J4 |3 14| Q3
+ * J1 |4 4029 13| J3
+ * CI |5 12| J2
+ * Q1 |6 11| Q2
+ * CO |7 10| U/D
+ * VSS |8 9| B/D
+ * +--------------+
+ *
+ * Counter Sequences:
+ *
+ * B/D high (Binary), U/D high (Up)
+ * +-------++----+----+----+----+----++-------+
+ * | COUNT || Q4 | Q3 | Q2 | Q1 | CO || NEXT |
+ * +=======++====+====+====+====+====++=======+
+ * | 0 || 0 | 0 | 0 | 0 | 1 || 1 |
+ * | 1 || 0 | 0 | 0 | 1 | 1 || 2 |
+ * | 2 || 0 | 0 | 1 | 0 | 1 || 3 |
+ * | 3 || 0 | 0 | 1 | 1 | 1 || 4 |
+ * | 4 || 0 | 1 | 0 | 0 | 1 || 5 |
+ * | 5 || 0 | 1 | 0 | 1 | 1 || 6 |
+ * | 6 || 0 | 1 | 1 | 0 | 1 || 7 |
+ * | 7 || 0 | 1 | 1 | 1 | 1 || 8 |
+ * | 8 || 1 | 0 | 0 | 0 | 1 || 9 |
+ * | 9 || 1 | 0 | 0 | 1 | 1 || A |
+ * | A || 1 | 0 | 1 | 0 | 1 || B |
+ * | B || 1 | 0 | 1 | 1 | 1 || C |
+ * | C || 1 | 1 | 0 | 0 | 1 || D |
+ * | D || 1 | 1 | 0 | 1 | 1 || E |
+ * | E || 1 | 1 | 1 | 0 | 1 || F |
+ * | F || 1 | 1 | 1 | 1 |0|CI|| 0 |
+ * | 0 || 0 | 0 | 0 | 0 | 1 || 1 |
+ * +-------++----+----+----+----+----++-------+
+ *
+ * B/D high (Binary), U/D low (Down)
+ * +-------++----+----+----+----+----++-------+
+ * | COUNT || Q4 | Q3 | Q2 | Q1 | CO || NEXT |
+ * +=======++====+====+====+====+====++=======+
+ * | F || 1 | 1 | 1 | 1 | 1 || E |
+ * | E || 1 | 1 | 1 | 0 | 1 || D |
+ * | D || 1 | 1 | 0 | 1 | 1 || C |
+ * | C || 1 | 1 | 0 | 0 | 1 || B |
+ * | B || 1 | 0 | 1 | 1 | 1 || A |
+ * | A || 1 | 0 | 1 | 0 | 1 || 9 |
+ * | 9 || 1 | 0 | 0 | 1 | 1 || 8 |
+ * | 8 || 1 | 0 | 0 | 0 | 1 || 7 |
+ * | 7 || 0 | 1 | 1 | 1 | 1 || 6 |
+ * | 6 || 0 | 1 | 1 | 0 | 1 || 5 |
+ * | 5 || 0 | 1 | 0 | 1 | 1 || 4 |
+ * | 4 || 0 | 1 | 0 | 0 | 1 || 3 |
+ * | 3 || 0 | 0 | 1 | 1 | 1 || 2 |
+ * | 2 || 0 | 0 | 1 | 0 | 1 || 1 |
+ * | 1 || 0 | 0 | 0 | 1 | 1 || 0 |
+ * | 0 || 0 | 0 | 0 | 0 |0|CI|| F |
+ * | F || 1 | 1 | 1 | 1 | 1 || E |
+ * +-------++----+----+----+----+----++-------+
+ *
+ * B/D low (Decimal), U/D high (Up)
+ * +-------++----+----+----+----+----++-------+
+ * | COUNT || Q4 | Q3 | Q2 | Q1 | CO || NEXT |
+ * +=======++====+====+====+====+====++=======+
+ * | 0 || 0 | 0 | 0 | 0 | 1 || 1 |
+ * | 1 || 0 | 0 | 0 | 1 | 1 || 2 |
+ * | 2 || 0 | 0 | 1 | 0 | 1 || 3 |
+ * | 3 || 0 | 0 | 1 | 1 | 1 || 4 |
+ * | 4 || 0 | 1 | 0 | 0 | 1 || 5 |
+ * | 5 || 0 | 1 | 0 | 1 | 1 || 6 |
+ * | 6 || 0 | 1 | 1 | 0 | 1 || 7 |
+ * | 7 || 0 | 1 | 1 | 1 | 1 || 8 |
+ * | 8 || 1 | 0 | 0 | 0 | 1 || 9 |
+ * | 9 || 1 | 0 | 0 | 1 |0|CI|| 0 |
+ * | A || 1 | 0 | 1 | 0 | 1 || B |
+ * | B || 1 | 0 | 1 | 1 |0|CI|| 6 |
+ * | C || 1 | 1 | 0 | 0 | 1 || D |
+ * | D || 1 | 1 | 0 | 1 |0|CI|| 4 |
+ * | E || 1 | 1 | 1 | 0 | 1 || F |
+ * | F || 1 | 1 | 1 | 1 |0|CI|| 2 |
+ * | 0 || 0 | 0 | 0 | 0 | 1 || 1 |
+ * +-------++----+----+----+----+----++-------+
+ *
+ * B/D low (Decimal), U/D low (Down)
+ * +-------++----+----+----+----+----++-------+
+ * | COUNT || Q4 | Q3 | Q2 | Q1 | CO || NEXT |
+ * +=======++====+====+====+====+====++=======+
+ * | F || 1 | 1 | 1 | 1 | 1 || E |
+ * | E || 1 | 1 | 1 | 0 | 1 || D |
+ * | D || 1 | 1 | 0 | 1 | 1 || C |
+ * | C || 1 | 1 | 0 | 0 | 1 || B |
+ * | B || 1 | 0 | 1 | 1 | 1 || A |
+ * | A || 1 | 0 | 1 | 0 | 1 || 9 |
+ * | 9 || 1 | 0 | 0 | 1 | 1 || 8 |
+ * | 8 || 1 | 0 | 0 | 0 | 1 || 7 |
+ * | 7 || 0 | 1 | 1 | 1 | 1 || 6 |
+ * | 6 || 0 | 1 | 1 | 0 | 1 || 5 |
+ * | 5 || 0 | 1 | 0 | 1 | 1 || 4 |
+ * | 4 || 0 | 1 | 0 | 0 | 1 || 3 |
+ * | 3 || 0 | 0 | 1 | 1 | 1 || 2 |
+ * | 2 || 0 | 0 | 1 | 0 | 1 || 1 |
+ * | 1 || 0 | 0 | 0 | 1 | 1 || 0 |
+ * | 0 || 0 | 0 | 0 | 0 |0|CI|| 9 |
+ * | 9 || 1 | 0 | 0 | 1 | 1 || 8 |
+ * +-------++----+----+----+----+----++-------+
+ *
+ * Note that in all cases where Carry-out is generating a non-1 signal (0 | Carry-in),
+ * this signal is asynchronous, so if carry-in changes the carry-out value will
+ * change immediately.
+ *
+ *
+ * Preset/Carry in function table
+ * +-----+-----+-----++----+----+----+----+
+ * | PE | CLK | CI || Q1 | Q2 | Q3 | Q4 |
+ * +=====+=====+=====++====+====+====+====+
+ * | 1 | X | X || J1 | J2 | J3 | J4 |
+ * | 0 | X | 1 || Q1 | Q2 | Q3 | Q4 |
+ * | 0 | ./` | 0 || COUNT |
+ * +-----+-----+-----++----+----+----+----+
+ *
+ * Naming conventions follow National Semiconductor datasheet
+ *
+ */
+
+#include "nl_base.h"
+
+namespace netlist
+{
+namespace devices
+{
+
+ NETLIB_OBJECT(CD4029)
+ {
+ NETLIB_CONSTRUCTOR_MODEL(CD4029, "CD4XXX")
+ , m_PE(*this, "PE", NETLIB_DELEGATE(inputs))
+ , m_J(*this, {"J1", "J2", "J3", "J4"}, NETLIB_DELEGATE(inputs))
+ , m_CI(*this, "CI", NETLIB_DELEGATE(inputs))
+ , m_UD(*this, "UD", NETLIB_DELEGATE(inputs))
+ , m_BD(*this, "BD", NETLIB_DELEGATE(inputs))
+ , m_CLK(*this, "CLK", NETLIB_DELEGATE(clk))
+ , m_clk_old(*this, "m_clk_old", false)
+ , m_Q(*this, {"Q1", "Q2", "Q3", "Q4"})
+ , m_CO(*this, "CO", 0)
+ , m_cnt(*this, "m_cnt", 0)
+ , m_power_pins(*this)
+ {
+ }
+
+ private:
+ inline NETLIB_HANDLERI(inputs) // pe causes an asynchronous counter load on level so has to be handled separately; if pe is high, then J changing will asynchronously change the Q state. changing J in this state does affect CO as well; CI will affect CO asynchronously if there is currently a carry
+ {
+ if (m_PE())
+ {
+ m_cnt = m_J()&0xf;
+ }
+ m_Q.push(m_cnt, NLTIME_FROM_NS(200));
+ // figure out CO
+ if (!m_UD()) // downward is the same for binary and decimal
+ {
+ m_CO.push(m_cnt||m_CI(),NLTIME_FROM_NS(320));
+ }
+ else // upward mode differs
+ {
+ if (!m_BD()) // decimal mode
+ {
+ m_CO.push((m_cnt<8)||(~m_cnt&1)||m_CI(),NLTIME_FROM_NS(320));
+ }
+ else // binary mode
+ {
+ m_CO.push((m_cnt!=0xf)||m_CI(),NLTIME_FROM_NS(320));
+ }
+ }
+ }
+
+ inline NETLIB_HANDLERI(clk)
+ {
+ // clocking only happens if m_clk_old was low, m_CLK is high, m_PE is NOT high, and m_CI is NOT high.
+ if (!m_PE() && !m_CI() && !m_clk_old && m_CLK())
+ {
+ if (m_BD()) // binary
+ {
+ m_cnt += (m_UD() ? 1 : -1);
+ m_cnt &= 0xf;
+ }
+ else // decimal
+ {
+ if (m_UD()) // upward
+ {
+ switch(m_cnt)
+ {
+ case 0: case 1: case 2: case 3:
+ case 4: case 5: case 6: case 7:
+ case 8: case 0xa: case 0xc: case 0xe:
+ m_cnt++;
+ break;
+ case 9:
+ m_cnt = 0;
+ break;
+ case 0xb:
+ m_cnt = 6;
+ break;
+ case 0xd:
+ m_cnt = 4;
+ break;
+ case 0xf:
+ m_cnt = 2;
+ break;
+ }
+ }
+ else // downward
+ {
+ if (m_cnt>0)
+ {
+ m_cnt--;
+ }
+ else // m_cnt == 0
+ {
+ m_cnt = 9;
+ }
+ }
+ }
+ }
+ m_clk_old = m_CLK();
+ m_Q.push(m_cnt, NLTIME_FROM_NS(200));
+ // figure out CO
+ if (!m_UD()) // downward is the same for binary and decimal
+ {
+ m_CO.push(m_cnt||m_CI(),NLTIME_FROM_NS(320));
+ }
+ else // upward mode differs
+ {
+ if (!m_BD()) // decimal mode
+ {
+ m_CO.push((m_cnt<8)||(~m_cnt&1)||m_CI(),NLTIME_FROM_NS(320));
+ }
+ else // binary mode
+ {
+ m_CO.push((m_cnt!=0xf)||m_CI(),NLTIME_FROM_NS(320));
+ }
+ }
+ }
+
+ NETLIB_RESETI()
+ {
+ m_cnt = 0;
+ m_clk_old = false;
+ }
+
+ logic_input_t m_PE;
+ object_array_t<logic_input_t, 4> m_J;
+ logic_input_t m_CI;
+ logic_input_t m_UD;
+ logic_input_t m_BD;
+ logic_input_t m_CLK;
+
+ state_var<netlist_sig_t> m_clk_old;
+ object_array_t<logic_output_t, 4> m_Q;
+ logic_output_t m_CO;
+ state_var_u8 m_cnt;
+ nld_power_pins m_power_pins;
+ };
+
+ NETLIB_DEVICE_IMPL(CD4029, "CD4029", "+PE,+J1,+J2,+J3,+J4,+CI,+UD,+BD,+CLK,@VCC,@GND")
+
+} // namespace devices
+} // namespace netlist
diff --git a/src/lib/netlist/devices/nld_4042.cpp b/src/lib/netlist/devices/nld_4042.cpp
new file mode 100644
index 00000000000..f79a3bdb7a5
--- /dev/null
+++ b/src/lib/netlist/devices/nld_4042.cpp
@@ -0,0 +1,120 @@
+// license:GPL-2.0+
+// copyright-holders:Couriersud, Jonathan Gevaryahu
+/*
+ * nld_4042.cpp
+ *
+ * CD4042BM/CD4042BC Quad Clocked D Latch
+ *
+ * +--------------+
+ * Q4 |1 ++ 16| VDD
+ * Q1 |2 15| Q4Q
+ * Q1Q |3 14| D4
+ * D1 |4 4042 13| D3
+ * CLK |5 12| Q3Q
+ * POL |6 11| Q3
+ * D2 |7 10| Q2
+ * VSS |8 9| Q2Q
+ * +--------------+
+ *
+ *
+ * Function table
+ * +-----+-----+----++----+-----+
+ * | POL | CLK | Dx || Qx | QQx |
+ * +=====+=====+====++====+=====+
+ * | 0 | 0 | X || Qx | /Qx |
+ * | 0 | 1 | D || D | /D |
+ * | 1 | 1 | X || Qx | /Qx |
+ * | 1 | 0 | D || D | /D |
+ * +-----+-----+----++----+-----+
+ * Note that since this is a level triggered transparent latch,
+ * as long as POL ^ CLK == true, the latch is transparent, and
+ * if D changes Q and QQ(/Q) will instantly change.
+ *
+ * Naming conventions follow National Semiconductor datasheet
+ *
+ * National Semiconductor Datasheet: http://pdf.datasheetcatalog.com/datasheet/nationalsemiconductor/DS005966.PDF
+ * TI Datasheet: https://www.ti.com/lit/ds/symlink/cd4042b.pdf
+ */
+
+#include "nl_base.h"
+
+namespace netlist
+{
+namespace devices
+{
+
+
+ NETLIB_OBJECT(CD4042)
+ {
+ NETLIB_CONSTRUCTOR_MODEL(CD4042, "CD4XXX")
+ , m_D(*this, {"D1", "D2", "D3", "D4"}, NETLIB_DELEGATE(inputs))
+ , m_POL(*this, "POL", NETLIB_DELEGATE(clk))
+ , m_CLK(*this, "CLK", NETLIB_DELEGATE(clk))
+ , m_Q(*this, {"Q1", "Q2", "Q3", "Q4"})
+ , m_QQ(*this, {"Q1Q", "Q2Q", "Q3Q", "Q4Q"})
+ , m_latch(*this, "m_latch", 0)
+ , m_tpdq(*this, "m_tpd", netlist_time::from_nsec(175))
+ , m_tpdqq(*this, "m_tpd", netlist_time::from_nsec(150))
+ , m_tpcq(*this, "m_tpc", netlist_time::from_nsec(250))
+ , m_tpcqq(*this, "m_tpc", netlist_time::from_nsec(250))
+ , m_power_pins(*this, NETLIB_DELEGATE(vdd_vss))
+ {
+ }
+
+ private:
+ inline NETLIB_HANDLERI(clk)
+ {
+ if (m_POL() ^ m_CLK()) // are we in transparent mode? if so latch the data and push it.
+ {
+ m_latch = m_D()&0xf;
+ m_Q.push(m_latch&0xf, m_tpcq);
+ m_QQ.push((~m_latch)&0xf, m_tpcqq);
+ }
+ // if not, the data inputs are ignored and just do nothing
+ }
+
+ inline NETLIB_HANDLERI(inputs)
+ {
+ if ((m_POL() ^ m_CLK())&&(m_latch != (m_D()&0xf))) // are we in transparent mode? if so latch the data and push it. only do this if the data actually changed
+ {
+ m_latch = m_D()&0xf;
+ m_Q.push(m_latch&0xf, m_tpdq);
+ m_QQ.push((~m_latch)&0xf, m_tpdqq);
+ }
+ }
+
+ inline NETLIB_HANDLERI(vdd_vss)
+ {
+ auto d = m_power_pins.VCC()() - m_power_pins.GND()();
+ if (d > 0.1) // avoid unrealistic values
+ {
+ m_tpdq = netlist_time::from_nsec(gsl::narrow_cast<unsigned>(894.0 / d - 6.0));
+ m_tpdqq = netlist_time::from_nsec(gsl::narrow_cast<unsigned>(750.0 / d + 0.0));
+ m_tpcq = netlist_time::from_nsec(gsl::narrow_cast<unsigned>(1327.0 / d - 18.8));
+ m_tpcqq = netlist_time::from_nsec(gsl::narrow_cast<unsigned>(1234.5 / d + 0.8));
+ }
+ }
+
+ NETLIB_RESETI()
+ {
+ m_latch = 0;
+ }
+
+ object_array_t<logic_input_t, 4> m_D;
+ logic_input_t m_POL;
+ logic_input_t m_CLK;
+
+ object_array_t<logic_output_t, 4> m_Q;
+ object_array_t<logic_output_t, 4> m_QQ;
+ state_var_u8 m_latch;
+ state_var<netlist_time> m_tpdq; // propagation time for data alone when in transparent mode, Q
+ state_var<netlist_time> m_tpdqq; // propagation time for data alone when in transparent mode, /Q
+ state_var<netlist_time> m_tpcq; // propagation time for data vs CLK, Q
+ state_var<netlist_time> m_tpcqq; // propagation time for data vs CLK, /Q
+ nld_power_pins m_power_pins;
+ };
+
+ NETLIB_DEVICE_IMPL(CD4042, "CD4042", "+D1,+D2,+D3,+D4,+POL,+CLK,@VCC,@GND")
+
+} // namespace devices
+} // namespace netlist
diff --git a/src/lib/netlist/devices/nld_4076.cpp b/src/lib/netlist/devices/nld_4076.cpp
new file mode 100644
index 00000000000..b4430390b31
--- /dev/null
+++ b/src/lib/netlist/devices/nld_4076.cpp
@@ -0,0 +1,132 @@
+// license:GPL-2.0+
+// copyright-holders:Couriersud, Jonathan Gevaryahu
+/*
+ * nld_4076.cpp
+ *
+ * CD4076BM/CD4076BC TRI-STATE(R) Quad D Flip-Flop
+ *
+ * +--------------+
+ * OD1 |1 ++ 16| VDD
+ * OD2 |2 15| CLR
+ * OA |3 14| IA
+ * OB |4 4076 13| IB
+ * OC |5 12| IC
+ * OD |6 11| ID
+ * CLK |7 10| ID2
+ * VSS |8 9| ID1
+ * +--------------+
+ *
+ *
+ * Function table for ID1/2 pins
+ * +-----+-----+-----+----+-----++-----+
+ * | ID1 | ID2 | CLR | Ix | CLK || iOx |
+ * +=====+=====+=====+====+=====++=====+
+ * | X | X | 0 | X | 0 || iOx |
+ * | X | X | 0 | X | 1 || iOx |
+ * | 1 | X | 0 | X | 0>1 || iOx |
+ * | X | 1 | 0 | X | 0>1 || iOx |
+ * | 0 | 0 | 0 | 0 | 0>1 || 0 |
+ * | 0 | 0 | 0 | 1 | 0>1 || 1 |
+ * | X | X | 1 | X | X || 0 |
+ * +-----+-----+-----+----+-----++-----+
+ * Note: iOX is an internal signal, the output of each D-latch
+ *
+ * Function table for OD1/2 pins vs output of the internal D-latches
+ * +-----+-----+-----++-----+
+ * | OD1 | OD2 | iOx || Ox |
+ * +=====+=====+=====++=====+
+ * | 1 | X | X || Z |
+ * | X | 1 | X || Z |
+ * | 0 | 0 | 0 || 0 |
+ * | 0 | 0 | 1 || 1 |
+ * +-----+-----+-----++-----+
+ *
+ * Naming conventions follow National Semiconductor datasheet
+ * http://www.bitsavers.org/components/national/_dataBooks/1981_Natonal_CMOS_Databook.pdf 5-186 (pdf page 567)
+ *
+ * TODO: the 74C173 is 100% identical to this CMOS part.
+ */
+
+#include "nl_base.h"
+
+namespace netlist
+{
+namespace devices
+{
+
+
+ NETLIB_OBJECT(CD4076)
+ {
+ NETLIB_CONSTRUCTOR_MODEL(CD4076, "CD4XXX")
+ , m_I(*this, {"IA", "IB", "IC", "ID"}, NETLIB_DELEGATE(id)) // if the d-pins change absolutely nothing happens, as they are clock-latched.
+ , m_ID1(*this, "ID1", NETLIB_DELEGATE(id))
+ , m_ID2(*this, "ID2", NETLIB_DELEGATE(id))
+ , m_enable_in(*this, "m_enable_in", true)
+ , m_CLK(*this, "CLK", NETLIB_DELEGATE(clk))
+ , m_clk_old(*this, "m_clk_old", 0)
+ , m_OD1(*this, "OD1", NETLIB_DELEGATE(od)) // if the OD pins change nothing about the internal state changes directly, but the outputs can change from driven to tri-state or vice-versa
+ , m_OD2(*this, "OD2", NETLIB_DELEGATE(od)) // ""
+ , m_enable_out(*this, "m_enable_out", true)
+ , m_O(*this, {"OA", "OB", "OC", "OD"})
+ , m_latch(*this, "m_latch", 0)
+ , m_power_pins(*this)
+ {
+ }
+
+ private:
+ inline NETLIB_HANDLERI(id)
+ {
+ m_enable_in = (!(m_ID1() || m_ID2()));
+ }
+
+ inline NETLIB_HANDLERI(clk)
+ {
+ if ((!m_clk_old) && m_CLK() && m_enable_in) // clock rising edge and input is enabled; otherwise the latch just re-latches its own value
+ {
+ m_latch = m_I()&0xf;
+ }
+ m_clk_old = m_CLK();
+ // update the pin output state
+ for (std::size_t i=0; i<4; i++)
+ {
+ m_O.set_tristate(m_enable_out, NLTIME_FROM_NS(170), NLTIME_FROM_NS(170));
+ m_O[i].push((m_latch >> i) & 1, NLTIME_FROM_NS(220));
+ }
+ }
+
+ inline NETLIB_HANDLERI(od)
+ {
+ m_enable_out = (!(m_OD1() || m_OD2()));
+ // update the pin output state
+ for (std::size_t i=0; i<4; i++)
+ {
+ m_O.set_tristate(m_enable_out, NLTIME_FROM_NS(170), NLTIME_FROM_NS(170));
+ m_O[i].push((m_latch >> i) & 1, NLTIME_FROM_NS(220));
+ }
+ }
+
+ NETLIB_RESETI()
+ {
+ m_latch = 0;
+ m_enable_in = true;
+ m_enable_out = true;
+ }
+
+ object_array_t<logic_input_t, 4> m_I;
+ logic_input_t m_ID1;
+ logic_input_t m_ID2;
+ state_var<bool> m_enable_in;
+ logic_input_t m_CLK;
+ state_var<netlist_sig_t> m_clk_old;
+ logic_input_t m_OD1;
+ logic_input_t m_OD2;
+ state_var<bool> m_enable_out;
+ object_array_t<logic_output_t, 4> m_O;
+ state_var_u8 m_latch;
+ nld_power_pins m_power_pins;
+ };
+
+ NETLIB_DEVICE_IMPL(CD4076, "CD4076", "+I1,+I2,+I3,+I4,+ID1,+ID2,+OD1,+OD2,@VCC,@GND")
+
+} // namespace devices
+} // namespace netlist
diff --git a/src/lib/netlist/devices/nld_roms.cpp b/src/lib/netlist/devices/nld_roms.cpp
index de440b4a8d2..a0bee0b60cd 100644
--- a/src/lib/netlist/devices/nld_roms.cpp
+++ b/src/lib/netlist/devices/nld_roms.cpp
@@ -96,6 +96,72 @@ namespace netlist
nld_power_pins m_power_pins;
};
+ NETLIB_OBJECT(mcm14524_rom)
+ {
+ NETLIB_CONSTRUCTOR_MODEL(mcm14524_rom, "CD4XXX")
+ , m_enabled(*this, "m_enabled", true)
+ , m_latched_rom(*this, "m_latched_rom", 0)
+ , m_A(*this, 1, "A{}", NETLIB_DELEGATE(addr))
+ , m_CLK(*this, "CLK", NETLIB_DELEGATE(addr))
+ , m_clk_old(*this, "m_clk_old", true)
+ , m_EN(*this, "EN", NETLIB_DELEGATE(en))
+ , m_B(*this, 1, "B{}", 0)
+ , m_ROM(*this, "ROM")
+ , m_taccc(*this, "m_taccc", netlist_time::from_nsec(1350))
+ , m_taccen(*this, "m_taccen", netlist_time::from_nsec(245))
+ , m_power_pins(*this, NETLIB_DELEGATE(vdd_vss))
+ {
+ }
+
+ private:
+ inline NETLIB_HANDLERI(en)
+ {
+ m_enabled = m_EN();
+ uint8_t o = m_enabled ? m_latched_rom : 0; // outputs are forced to 0 by enable going low; this chip does not have tri-state outputs!
+ for (std::size_t i=0; i<4; i++)
+ {
+ m_B[i].push((o >> i) & 1, m_taccen);
+ }
+ }
+
+ inline NETLIB_HANDLERI(addr)
+ {
+ if (!m_CLK() && m_clk_old) // latch on falling edge
+ {
+ const auto addr = m_A();
+ m_latched_rom = m_ROM[addr];
+ }
+ m_clk_old = m_CLK();
+ uint8_t o = m_enabled ? m_latched_rom : 0; // outputs are forced to 0 by enable going low; this chip does not have tri-state outputs!
+ for (std::size_t i=0; i<4; i++)
+ {
+ m_B[i].push((o >> i) & 1, m_taccc);
+ }
+ }
+
+ inline NETLIB_HANDLERI(vdd_vss)
+ {
+ auto d = m_power_pins.VCC()() - m_power_pins.GND()();
+ if (d > 0.1) // avoid unrealistic values
+ {
+ m_taccc = netlist_time::from_nsec(gsl::narrow_cast<unsigned>(7615.5 / d - 181));
+ m_taccen = netlist_time::from_nsec(gsl::narrow_cast<unsigned>(1292.5 / d - 14.6));
+ }
+ }
+
+ state_var<bool> m_enabled;
+ state_var<uint8_t> m_latched_rom;
+ object_array_t<logic_input_t, 8> m_A;
+ logic_input_t m_CLK;
+ state_var<bool> m_clk_old;
+ logic_input_t m_EN;
+ object_array_t<tristate_output_t, 4> m_B;
+ param_rom_t<uint8_t, 8, 4> m_ROM;
+ state_var<netlist_time> m_taccc; // propagation time for data vs CLK
+ state_var<netlist_time> m_taccen; // propagation time for data vs /EN
+ nld_power_pins m_power_pins;
+ };
+
template <typename D>
NETLIB_OBJECT(generic_prom)
{
@@ -230,12 +296,14 @@ namespace netlist
using NETLIB_NAME(74S287) = NETLIB_NAME(generic_prom)<desc_74S287>; // 1024 bits, 32x32, used as 256x4
using NETLIB_NAME(2716) = NETLIB_NAME(generic_prom)<desc_2716>; // CE2Q = OE, CE1Q = CE
using NETLIB_NAME(MK28000) = NETLIB_NAME(mk28000_prom); // 16384 bits, either 2048x8 or 4096x4, determined by OE1/OE2 use
+ using NETLIB_NAME(MCM14524) = NETLIB_NAME(mcm14524_rom); // 1024 bits, 256x4, latched address
NETLIB_DEVICE_IMPL(82S126, "PROM_82S126", "+CE1Q,+CE2Q,+A0,+A1,+A2,+A3,+A4,+A5,+A6,+A7,@VCC,@GND")
NETLIB_DEVICE_IMPL(74S287, "PROM_74S287", "+CE1Q,+CE2Q,+A0,+A1,+A2,+A3,+A4,+A5,+A6,+A7,@VCC,@GND")
NETLIB_DEVICE_IMPL(82S123, "PROM_82S123", "+CEQ,+A0,+A1,+A2,+A3,+A4,@VCC,@GND")
NETLIB_DEVICE_IMPL(2716, "EPROM_2716", "+CE2Q,+CE1Q,+A0,+A1,+A2,+A3,+A4,+A5,+A6,+A7,+A8,+A9,+A10,@VCC,@GND")
NETLIB_DEVICE_IMPL(MK28000, "PROM_MK28000", "+OE1,+OE2,+ARQ,+A1,+A2,+A3,+A4,+A5,+A6,+A7,+A8,+A9,+A10,+A11,@VCC,@GND")
+ NETLIB_DEVICE_IMPL(MCM14524, "ROM_MCM14524", "+EN,+CLK,+A0,+A1,+A2,+A3,+A4,+A5,+A6,+A7,@VCC,@GND")
} //namespace devices
} // namespace netlist
diff --git a/src/lib/netlist/generated/lib_entries.hxx b/src/lib/netlist/generated/lib_entries.hxx
index da6ad55a0a3..debc626fd47 100755
--- a/src/lib/netlist/generated/lib_entries.hxx
+++ b/src/lib/netlist/generated/lib_entries.hxx
@@ -60,14 +60,18 @@ LIB_ENTRY(CD4017)
LIB_ENTRY(CD4020)
LIB_ENTRY(CD4022)
LIB_ENTRY(CD4024)
+LIB_ENTRY(CD4029)
+LIB_ENTRY(CD4042)
LIB_ENTRY(CD4053_GATE)
LIB_ENTRY(CD4066_GATE)
+LIB_ENTRY(CD4076)
LIB_ENTRY(CD4316_GATE)
LIB_ENTRY(CS)
LIB_ENTRY(D)
LIB_ENTRY(L)
LIB_ENTRY(LVCCS)
LIB_ENTRY(MC1455P)
+LIB_ENTRY(MCM14524)
LIB_ENTRY(MK28000)
LIB_ENTRY(MM5837)
LIB_ENTRY(MOSFET)
diff --git a/src/lib/netlist/generated/nld_devinc.h b/src/lib/netlist/generated/nld_devinc.h
index f5b14563db8..1a2fa7eeca3 100755
--- a/src/lib/netlist/generated/nld_devinc.h
+++ b/src/lib/netlist/generated/nld_devinc.h
@@ -154,6 +154,24 @@
NET_REGISTER_DEVEXT(CD4024, __VA_ARGS__)
// ---------------------------------------------------------------------
+// Source: ../devices/nld_4029.cpp
+// ---------------------------------------------------------------------
+
+// usage : CD4029(name, PE, J1, J2, J3, J4, CI, UD, BD, CLK)
+// auto connect: VCC, GND
+#define CD4029(...) \
+ NET_REGISTER_DEVEXT(CD4029, __VA_ARGS__)
+
+// ---------------------------------------------------------------------
+// Source: ../devices/nld_4042.cpp
+// ---------------------------------------------------------------------
+
+// usage : CD4042(name, D1, D2, D3, D4, POL, CLK)
+// auto connect: VCC, GND
+#define CD4042(...) \
+ NET_REGISTER_DEVEXT(CD4042, __VA_ARGS__)
+
+// ---------------------------------------------------------------------
// Source: ../devices/nld_4053.cpp
// ---------------------------------------------------------------------
@@ -170,6 +188,15 @@
NET_REGISTER_DEVEXT(CD4066_GATE, __VA_ARGS__)
// ---------------------------------------------------------------------
+// Source: ../devices/nld_4076.cpp
+// ---------------------------------------------------------------------
+
+// usage : CD4076(name, I1, I2, I3, I4, ID1, ID2, OD1, OD2)
+// auto connect: VCC, GND
+#define CD4076(...) \
+ NET_REGISTER_DEVEXT(CD4076, __VA_ARGS__)
+
+// ---------------------------------------------------------------------
// Source: ../devices/nld_4316.cpp
// ---------------------------------------------------------------------
@@ -652,6 +679,11 @@
#define PROM_MK28000(...) \
NET_REGISTER_DEVEXT(PROM_MK28000, __VA_ARGS__)
+// usage : ROM_MCM14524(name, EN, CLK, A0, A1, A2, A3, A4, A5, A6, A7)
+// auto connect: VCC, GND
+#define ROM_MCM14524(...) \
+ NET_REGISTER_DEVEXT(ROM_MCM14524, __VA_ARGS__)
+
// ---------------------------------------------------------------------
// Source: ../devices/nld_schmitt.cpp
// ---------------------------------------------------------------------
@@ -769,6 +801,14 @@
#define CD4011_GATE(...) \
NET_REGISTER_DEVEXT(CD4011_GATE, __VA_ARGS__)
+// usage : CD4030_GATE(name, )
+#define CD4030_GATE(...) \
+ NET_REGISTER_DEVEXT(CD4030_GATE, __VA_ARGS__)
+
+// usage : CD4049_GATE(name, )
+#define CD4049_GATE(...) \
+ NET_REGISTER_DEVEXT(CD4049_GATE, __VA_ARGS__)
+
// usage : CD4069_GATE(name, )
#define CD4069_GATE(...) \
NET_REGISTER_DEVEXT(CD4069_GATE, __VA_ARGS__)
@@ -785,6 +825,14 @@
#define CD4011_DIP(...) \
NET_REGISTER_DEVEXT(CD4011_DIP, __VA_ARGS__)
+// usage : CD4030_DIP(name, )
+#define CD4030_DIP(...) \
+ NET_REGISTER_DEVEXT(CD4030_DIP, __VA_ARGS__)
+
+// usage : CD4049_DIP(name, )
+#define CD4049_DIP(...) \
+ NET_REGISTER_DEVEXT(CD4049_DIP, __VA_ARGS__)
+
// usage : CD4069_DIP(name, )
#define CD4069_DIP(...) \
NET_REGISTER_DEVEXT(CD4069_DIP, __VA_ARGS__)
@@ -817,6 +865,14 @@
#define CD4024_DIP(...) \
NET_REGISTER_DEVEXT(CD4024_DIP, __VA_ARGS__)
+// usage : CD4029_DIP(name, )
+#define CD4029_DIP(...) \
+ NET_REGISTER_DEVEXT(CD4029_DIP, __VA_ARGS__)
+
+// usage : CD4042_DIP(name, )
+#define CD4042_DIP(...) \
+ NET_REGISTER_DEVEXT(CD4042_DIP, __VA_ARGS__)
+
// usage : CD4053_DIP(name, )
#define CD4053_DIP(...) \
NET_REGISTER_DEVEXT(CD4053_DIP, __VA_ARGS__)
@@ -829,6 +885,10 @@
#define CD4016_DIP(...) \
NET_REGISTER_DEVEXT(CD4016_DIP, __VA_ARGS__)
+// usage : CD4076_DIP(name, )
+#define CD4076_DIP(...) \
+ NET_REGISTER_DEVEXT(CD4076_DIP, __VA_ARGS__)
+
// usage : CD4316_DIP(name, )
#define CD4316_DIP(...) \
NET_REGISTER_DEVEXT(CD4316_DIP, __VA_ARGS__)
@@ -989,6 +1049,10 @@
#define PROM_MK28000_DIP(...) \
NET_REGISTER_DEVEXT(PROM_MK28000_DIP, __VA_ARGS__)
+// usage : ROM_MCM14524_DIP(name, )
+#define ROM_MCM14524_DIP(...) \
+ NET_REGISTER_DEVEXT(ROM_MCM14524_DIP, __VA_ARGS__)
+
// usage : RAM_2102A_DIP(name, )
#define RAM_2102A_DIP(...) \
NET_REGISTER_DEVEXT(RAM_2102A_DIP, __VA_ARGS__)
diff --git a/src/lib/netlist/macro/nlm_cd4xxx_lib.cpp b/src/lib/netlist/macro/nlm_cd4xxx_lib.cpp
index 13c80aa391b..51034eb3498 100644
--- a/src/lib/netlist/macro/nlm_cd4xxx_lib.cpp
+++ b/src/lib/netlist/macro/nlm_cd4xxx_lib.cpp
@@ -268,6 +268,251 @@ static NETLIST_START(CD4024_DIP)
/* +--------------+ */)
NETLIST_END()
+//- Identifier: CD4029_DIP
+//- Title: CD4029BM/CD4029BC Presettable Binary/Decade Up/Down Counter
+//- Pinalias: PE,Q4,J4,J1,CI,Q1,CO,VSS,BD,UD,Q2,J2,J3,Q3,CLK,VDD
+//- Package: DIP
+//- NamingConvention: Naming conventions follow National Semiconductor datasheet
+//- Limitations:
+//- Voltage-dependent timing is not implemented.
+//- FunctionTable:
+//- http://pdf.datasheetcatalog.com/datasheets/166/108968_DS.pdf
+//- See nld_4029.cpp for tables explaining the counting order for all states
+//-
+//- Counter Sequences:
+//-
+//- B/D high (Binary), U/D high (Up)
+//- +-------++----+----+----+----+----++-------+
+//- | COUNT || Q4 | Q3 | Q2 | Q1 | CO || NEXT |
+//- +=======++====+====+====+====+====++=======+
+//- | 0 || 0 | 0 | 0 | 0 | 1 || 1 |
+//- | 1 || 0 | 0 | 0 | 1 | 1 || 2 |
+//- | 2 || 0 | 0 | 1 | 0 | 1 || 3 |
+//- | 3 || 0 | 0 | 1 | 1 | 1 || 4 |
+//- | 4 || 0 | 1 | 0 | 0 | 1 || 5 |
+//- | 5 || 0 | 1 | 0 | 1 | 1 || 6 |
+//- | 6 || 0 | 1 | 1 | 0 | 1 || 7 |
+//- | 7 || 0 | 1 | 1 | 1 | 1 || 8 |
+//- | 8 || 1 | 0 | 0 | 0 | 1 || 9 |
+//- | 9 || 1 | 0 | 0 | 1 | 1 || A |
+//- | A || 1 | 0 | 1 | 0 | 1 || B |
+//- | B || 1 | 0 | 1 | 1 | 1 || C |
+//- | C || 1 | 1 | 0 | 0 | 1 || D |
+//- | D || 1 | 1 | 0 | 1 | 1 || E |
+//- | E || 1 | 1 | 1 | 0 | 1 || F |
+//- | F || 1 | 1 | 1 | 1 |0|CI|| 0 |
+//- | 0 || 0 | 0 | 0 | 0 | 1 || 1 |
+//- +-------++----+----+----+----+----++-------+
+//-
+//- B/D high (Binary), U/D low (Down)
+//- +-------++----+----+----+----+----++-------+
+//- | COUNT || Q4 | Q3 | Q2 | Q1 | CO || NEXT |
+//- +=======++====+====+====+====+====++=======+
+//- | F || 1 | 1 | 1 | 1 | 1 || E |
+//- | E || 1 | 1 | 1 | 0 | 1 || D |
+//- | D || 1 | 1 | 0 | 1 | 1 || C |
+//- | C || 1 | 1 | 0 | 0 | 1 || B |
+//- | B || 1 | 0 | 1 | 1 | 1 || A |
+//- | A || 1 | 0 | 1 | 0 | 1 || 9 |
+//- | 9 || 1 | 0 | 0 | 1 | 1 || 8 |
+//- | 8 || 1 | 0 | 0 | 0 | 1 || 7 |
+//- | 7 || 0 | 1 | 1 | 1 | 1 || 6 |
+//- | 6 || 0 | 1 | 1 | 0 | 1 || 5 |
+//- | 5 || 0 | 1 | 0 | 1 | 1 || 4 |
+//- | 4 || 0 | 1 | 0 | 0 | 1 || 3 |
+//- | 3 || 0 | 0 | 1 | 1 | 1 || 2 |
+//- | 2 || 0 | 0 | 1 | 0 | 1 || 1 |
+//- | 1 || 0 | 0 | 0 | 1 | 1 || 0 |
+//- | 0 || 0 | 0 | 0 | 0 |0|CI|| F |
+//- | F || 1 | 1 | 1 | 1 | 1 || E |
+//- +-------++----+----+----+----+----++-------+
+//-
+//- B/D low (Decimal), U/D high (Up)
+//- +-------++----+----+----+----+----++-------+
+//- | COUNT || Q4 | Q3 | Q2 | Q1 | CO || NEXT |
+//- +=======++====+====+====+====+====++=======+
+//- | 0 || 0 | 0 | 0 | 0 | 1 || 1 |
+//- | 1 || 0 | 0 | 0 | 1 | 1 || 2 |
+//- | 2 || 0 | 0 | 1 | 0 | 1 || 3 |
+//- | 3 || 0 | 0 | 1 | 1 | 1 || 4 |
+//- | 4 || 0 | 1 | 0 | 0 | 1 || 5 |
+//- | 5 || 0 | 1 | 0 | 1 | 1 || 6 |
+//- | 6 || 0 | 1 | 1 | 0 | 1 || 7 |
+//- | 7 || 0 | 1 | 1 | 1 | 1 || 8 |
+//- | 8 || 1 | 0 | 0 | 0 | 1 || 9 |
+//- | 9 || 1 | 0 | 0 | 1 |0|CI|| 0 |
+//- | A || 1 | 0 | 1 | 0 | 1 || B |
+//- | B || 1 | 0 | 1 | 1 |0|CI|| 6 |
+//- | C || 1 | 1 | 0 | 0 | 1 || D |
+//- | D || 1 | 1 | 0 | 1 |0|CI|| 4 |
+//- | E || 1 | 1 | 1 | 0 | 1 || F |
+//- | F || 1 | 1 | 1 | 1 |0|CI|| 2 |
+//- | 0 || 0 | 0 | 0 | 0 | 1 || 1 |
+//- +-------++----+----+----+----+----++-------+
+//-
+//- B/D low (Decimal), U/D low (Down)
+//- +-------++----+----+----+----+----++-------+
+//- | COUNT || Q4 | Q3 | Q2 | Q1 | CO || NEXT |
+//- +=======++====+====+====+====+====++=======+
+//- | F || 1 | 1 | 1 | 1 | 1 || E |
+//- | E || 1 | 1 | 1 | 0 | 1 || D |
+//- | D || 1 | 1 | 0 | 1 | 1 || C |
+//- | C || 1 | 1 | 0 | 0 | 1 || B |
+//- | B || 1 | 0 | 1 | 1 | 1 || A |
+//- | A || 1 | 0 | 1 | 0 | 1 || 9 |
+//- | 9 || 1 | 0 | 0 | 1 | 1 || 8 |
+//- | 8 || 1 | 0 | 0 | 0 | 1 || 7 |
+//- | 7 || 0 | 1 | 1 | 1 | 1 || 6 |
+//- | 6 || 0 | 1 | 1 | 0 | 1 || 5 |
+//- | 5 || 0 | 1 | 0 | 1 | 1 || 4 |
+//- | 4 || 0 | 1 | 0 | 0 | 1 || 3 |
+//- | 3 || 0 | 0 | 1 | 1 | 1 || 2 |
+//- | 2 || 0 | 0 | 1 | 0 | 1 || 1 |
+//- | 1 || 0 | 0 | 0 | 1 | 1 || 0 |
+//- | 0 || 0 | 0 | 0 | 0 |0|CI|| 9 |
+//- | 9 || 1 | 0 | 0 | 1 | 1 || 8 |
+//- +-------++----+----+----+----+----++-------+
+//-
+//- Note that in all cases where Carry-out is generating a non-1 signal (0 | Carry-in),
+//- this signal is asynchronous, so if carry-in changes the carry-out value will
+//- change immediately.
+//-
+//- Preset/Carry in function table
+//- +-----+-----+-----++----+----+----+----+
+//- | PE | CLK | CI || Q1 | Q2 | Q3 | Q4 |
+//- +=====+=====+=====++====+====+====+====+
+//- | 1 | X | X || J1 | J2 | J3 | J4 |
+//- | 0 | X | 1 || Q1 | Q2 | Q3 | Q4 |
+//- | 0 | ./` | 0 || COUNT |
+//- +-----+-----+-----++----+----+----+----+
+//-
+static NETLIST_START(CD4029_DIP)
+ CD4029(A)
+
+ DIPPINS( /* +--------------+ */
+ A.PE, /* PE |1 ++ 16| VDD */ A.VDD,
+ A.Q4, /* Q4 |2 15| CLK */ A.CLK,
+ A.J4, /* J4 |3 14| Q3 */ A.Q3,
+ A.J1, /* J1 |4 4029 13| J3 */ A.J3,
+ A.CI, /* CI |5 12| J2 */ A.J2,
+ A.Q1, /* Q1 |6 11| Q2 */ A.Q2,
+ A.CO, /* CO |7 10| U/D */ A.UD,
+ A.VSS, /* VSS |8 9| B/D */ A.BD
+ /* +--------------+ */)
+NETLIST_END()
+
+//- Identifier: CD4030_DIP
+//- Title: CD4030M/CD4030C Quad EXCLUSIVE-OR Gate
+//- Pinalias: A1,B1,Y1,Y2,A2,B2,VSS,A3,B3,Y3,Y4,A4,B4,VDD
+//- Package: DIP
+//- NamingConvention: Naming conventions follow National Semiconductor datasheet
+//- Limitations:
+//- Voltage-dependent timing is not implemented.
+//- FunctionTable:
+//- https://www.uni-kl.de/elektronik-lager/418055
+//-
+static NETLIST_START(CD4030_DIP)
+ CD4030_GATE(A)
+ CD4030_GATE(B)
+ CD4030_GATE(C)
+ CD4030_GATE(D)
+
+ DIPPINS( /* +--------------+ */
+ A.A, /* A1 |1 ++ 14| VDD */ A.VDD,
+ A.B, /* B1 |2 13| B4 */ D.B,
+ A.Q, /* Y1 |3 12| A4 */ D.A,
+ B.Q, /* Y2 |4 4030 11| Y4 */ D.Q,
+ B.A, /* A2 |5 10| Y3 */ C.Q,
+ B.B, /* B2 |6 9| B3 */ C.B,
+ A.VSS, /* VSS |7 8| A3 */ C.A
+ /* +--------------+ */
+ )
+NETLIST_END()
+
+//- Identifier: CD4042_DIP
+//- Title: CD4042BM/CD4042BC Quad Clocked D Latch
+//- Pinalias: Q4,Q1,QQ1,D1,CLK,POL,D2,VSS,QQ2,Q2,Q3,QQ3,D3,D4,QQ4,VDD
+//- Package: DIP
+//- NamingConvention: Naming conventions follow National Semiconductor datasheet
+//- Limitations:
+//- Voltage-dependent timing is partially implemented.
+//- FunctionTable:
+//- http://pdf.datasheetcatalog.com/datasheet/nationalsemiconductor/DS005966.PDF
+//-
+//- +-----+-----+----++----+-----+
+//- | POL | CLK | Dx || Qx | QQx |
+//- +=====+=====+====++====+=====+
+//- | 0 | 0 | X || Qx | /Qx |
+//- | 0 | 1 | D || D | /D |
+//- | 1 | 1 | X || Qx | /Qx |
+//- | 1 | 0 | D || D | /D |
+//- +-----+-----+----++----+-----+
+//- Note that since this is a level triggered transparent latch,
+//- as long as POL ^ CLK == true, the latch is transparent, and
+//- if D changes Q and QQ(/Q) will instantly change.
+//-
+static NETLIST_START(CD4042_DIP)
+ CD4042(A)
+
+ DIPPINS( /* +--------------+ */
+ A.Q4, /* Q4 |1 ++ 16| VDD */ A.VDD,
+ A.Q1, /* Q1 |2 15| Q4Q */ A.Q4Q,
+ A.Q1Q, /* Q1Q |3 14| D4 */ A.D4,
+ A.D1, /* D1 |4 4042 13| D3 */ A.D3,
+ A.CLK, /* CLK |5 12| Q3Q */ A.Q3Q,
+ A.POL, /* POL |6 11| Q3 */ A.Q3,
+ A.D2, /* D2 |7 10| Q2 */ A.Q2,
+ A.VSS, /* VSS |8 9| Q2Q */ A.Q2Q
+ /* +--------------+ */
+ )
+NETLIST_END()
+
+//- Identifier: CD4049_DIP
+//- Title: CD4049UBM/CD4049UBC Hex Inverting Buffer
+//- Pinalias: VDD,G,A,H,B,I,C,VSS,D,J,E,K,NC,F,L,NC
+//- Package: DIP
+//- NamingConvention: Naming conventions follow National Semiconductor datasheet
+//- Limitations:
+//- Voltage-dependent timing is not implemented.
+//- FunctionTable:
+//- http://pdf.datasheetcatalog.com/datasheets/134/109125_DS.pdf
+//-
+static NETLIST_START(CD4049_DIP)
+ CD4049_GATE(A)
+ CD4049_GATE(B)
+ CD4049_GATE(C)
+ CD4049_GATE(D)
+ CD4049_GATE(E)
+ CD4049_GATE(F)
+ NC_PIN(NC)
+
+ NET_C(A.VDD, B.VDD, C.VDD, D.VDD, E.VDD, F.VDD)
+ NET_C(A.VSS, B.VSS, C.VSS, D.VSS, E.VSS, F.VSS)
+
+ //DIPPINS( /* +--------------+ */
+ // A.VDD, /* VCC |1 ++ 16| NC */ NC.I,
+ // A.G, /*G=/A |2 15| L=/F*/ F.L,
+ // A.A, /* A |3 14| F */ F.F,
+ // B.H, /*H=/B |4 13| NC */ NC.I,
+ // B.B, /* B |5 4049 12| K=/E*/ E.K,
+ // C.I, /*I=/C |6 11| E */ E.E,
+ // C.C, /* C |7 10| J=/D*/ D.J,
+ // A.VSS, /* VSS |8 9| D */ D.D
+ // /* +--------------+ */
+ //)
+ DIPPINS( /* +--------------+ */
+ A.VDD, /* VCC |1 ++ 16| NC */ NC.I,
+ A.Q, /*G=/A |2 15| L=/F*/ F.Q,
+ A.A, /* A |3 14| F */ F.A,
+ B.Q, /*H=/B |4 13| NC */ NC.I,
+ B.A, /* B |5 4049 12| K=/E*/ E.Q,
+ C.Q, /*I=/C |6 11| E */ E.A,
+ C.A, /* C |7 10| J=/D*/ D.Q,
+ A.VSS, /* VSS |8 9| D */ D.A
+ /* +--------------+ */
+ )
+NETLIST_END()
+
//- Identifier: CD4053_DIP
//- Title: CD4053BM/CD4053BC Triple 2-Channel AnalogMultiplexer/Demultiplexer
//- Pinalias: INOUTBY,INOUTBX,INOUTCY,OUTINC,INOUTCX,INH,VEE,VSS,C,B,A,INOUTAX,INOUTAY,OUTINA,OUTINB,VDD
@@ -397,6 +642,56 @@ static NETLIST_START(CD4070_DIP)
)
NETLIST_END()
+//- Identifier: CD4076_DIP
+//- Title: CD4076BM/CD4076BC TRI-STATE(R) Quad D Flip-Flop
+//- Pinalias: OD1,OD2,OA,OB,OC,OD,CLK,VSS,ID1,ID2,ID,IC,IB,IA,CLR,VDD
+//- Package: DIP
+//- NamingConvention: Naming conventions follow National Semiconductor datasheet
+//- Limitations:
+//- Voltage-dependent timing is not implemented.
+//- FunctionTable:
+//- http://www.bitsavers.org/components/national/_dataBooks/1981_Natonal_CMOS_Databook.pdf 5-186 (pdf page 567)
+//-
+//- Function table for ID1/2 pins
+//- +-----+-----+-----+----+-----++-----+
+//- | ID1 | ID2 | CLR | Ix | CLK || iOx |
+//- +=====+=====+=====+====+=====++=====+
+//- | X | X | 0 | X | 0 || iOx |
+//- | X | X | 0 | X | 1 || iOx |
+//- | 1 | X | 0 | X | 0>1 || iOx |
+//- | X | 1 | 0 | X | 0>1 || iOx |
+//- | 0 | 0 | 0 | 0 | 0>1 || 0 |
+//- | 0 | 0 | 0 | 1 | 0>1 || 1 |
+//- | X | X | 1 | X | X || 0 |
+//- +-----+-----+-----+----+-----++-----+
+//- Note: iOX is an internal signal, the output of each D-latch
+//-
+//- Function table for OD1/2 pins vs output of the internal D-latches
+//- +-----+-----+-----++-----+
+//- | OD1 | OD2 | iOx || Ox |
+//- +=====+=====+=====++=====+
+//- | 1 | X | X || Z |
+//- | X | 1 | X || Z |
+//- | 0 | 0 | 0 || 0 |
+//- | 0 | 0 | 1 || 1 |
+//- +-----+-----+-----++-----+
+//-
+static NETLIST_START(CD4076_DIP)
+ CD4076(A)
+
+ DIPPINS( /* +--------------+ */
+ A.OD1, /* OD1 |1 ++ 16| VDD */ A.VDD,
+ A.OD2, /* OD2 |2 15| CLR */ A.CLR,
+ A.OA, /* OA |3 14| IA */ A.IA,
+ A.OB, /* OB |4 4076 13| IB */ A.IB,
+ A.OC, /* OC |5 12| IC */ A.IC,
+ A.OD, /* OD |6 11| ID */ A.ID,
+ A.CLK, /* CLK |7 10| ID2 */ A.ID2,
+ A.VSS, /* VSS |8 9| ID1 */ A.ID1
+ /* +--------------+ */
+ )
+NETLIST_END()
+
//- Identifier: CD4316_DIP
//- Title: 74HC/HCT4316 Quad bilateral switches
//- Pinalias: 1Z,1Y,2Y,2Z,2S,3S,EQ,GND,VEE,3Z,3Y,4Y,4Z,4S,1S,VCC
@@ -501,6 +796,22 @@ static TRUTHTABLE_START(CD4011_GATE, 2, 1, "")
TT_FAMILY("CD4XXX")
TRUTHTABLE_END()
+static TRUTHTABLE_START(CD4030_GATE, 2, 1, "")
+ TT_HEAD("A , B | Q ")
+ TT_LINE("0,0|0|100")
+ TT_LINE("0,1|1|100")
+ TT_LINE("1,0|1|100")
+ TT_LINE("1,1|0|100")
+ TT_FAMILY("CD4XXX")
+TRUTHTABLE_END()
+
+static TRUTHTABLE_START(CD4049_GATE, 1, 1, "")
+ TT_HEAD("A|Q ")
+ TT_LINE("0|1|45")
+ TT_LINE("1|0|45")
+ TT_FAMILY("CD4XXX")
+TRUTHTABLE_END()
+
static TRUTHTABLE_START(CD4069_GATE, 1, 1, "")
TT_HEAD("A|Q ")
TT_LINE("0|1|55")
@@ -521,11 +832,15 @@ NETLIST_START(cd4xxx_lib)
TRUTHTABLE_ENTRY(CD4001_GATE)
TRUTHTABLE_ENTRY(CD4011_GATE)
+ TRUTHTABLE_ENTRY(CD4030_GATE)
+ TRUTHTABLE_ENTRY(CD4049_GATE)
TRUTHTABLE_ENTRY(CD4069_GATE)
TRUTHTABLE_ENTRY(CD4070_GATE)
LOCAL_LIB_ENTRY(CD4001_DIP)
LOCAL_LIB_ENTRY(CD4011_DIP)
+ LOCAL_LIB_ENTRY(CD4030_DIP)
+ LOCAL_LIB_ENTRY(CD4049_DIP)
LOCAL_LIB_ENTRY(CD4069_DIP)
LOCAL_LIB_ENTRY(CD4070_DIP)
@@ -536,9 +851,12 @@ NETLIST_START(cd4xxx_lib)
LOCAL_LIB_ENTRY(CD4022_DIP)
LOCAL_LIB_ENTRY(CD4020_DIP)
LOCAL_LIB_ENTRY(CD4024_DIP)
+ LOCAL_LIB_ENTRY(CD4029_DIP)
+ LOCAL_LIB_ENTRY(CD4042_DIP)
LOCAL_LIB_ENTRY(CD4053_DIP)
LOCAL_LIB_ENTRY(CD4066_DIP)
LOCAL_LIB_ENTRY(CD4016_DIP)
+ LOCAL_LIB_ENTRY(CD4076_DIP)
LOCAL_LIB_ENTRY(CD4316_DIP)
LOCAL_LIB_ENTRY(CD4538_DIP)
diff --git a/src/lib/netlist/macro/nlm_roms_lib.cpp b/src/lib/netlist/macro/nlm_roms_lib.cpp
index 4e8ab22a910..d728078c87f 100644
--- a/src/lib/netlist/macro/nlm_roms_lib.cpp
+++ b/src/lib/netlist/macro/nlm_roms_lib.cpp
@@ -342,6 +342,39 @@ static NETLIST_START(PROM_MK28000_DIP)
ALIAS(24, A.OE1)
NETLIST_END()
+//- Identifier: ROM_MCM14524_DIP
+//- Title: MCM14524 1024-BIT READ ONLY MEMORY
+//- Pinalias: CLK,EN,B0,B1,B2,B3,A2,GND,A3,A4,A5,A6,A7,A1,A0,VCC
+//- Package: DIP
+//- Param: ROM
+//- The name of the source to load the rom content from
+//- NamingConvention: Naming conventions follow Motorola datasheet
+//- Limitations:
+//- Voltage-dependent timing is partially implemented.
+//- FunctionTable:
+//- http://www.bitsavers.org/components/motorola/_dataBooks/1978_Motorola_CMOS_Data_Book.pdf 7-439 (pdf page 488)
+
+static NETLIST_START(ROM_MCM14524_DIP)
+
+ ROM_MCM14524(A)
+
+ DEFPARAM(ROM, "unknown")
+ PARAM(A.ROM, "$(@.ROM)")
+
+ /* Motorola MCM14524: */
+ DIPPINS( /* +-----..-----+ */
+ A.CLK, /* /CLK |1 16| VDD */ A.VCC,
+ A.EN, /* CE |2 15| A0 */ A.A0,
+ A.B0, /* B0 |3 MCM 14| A1 */ A.A1,
+ A.B1, /* B1 |4 14524 13| A7 */ A.A7,
+ A.B2, /* B2 |5 12| A6 */ A.A6,
+ A.B3, /* B3 |6 11| A5 */ A.A5,
+ A.A2, /* A2 |7 10| A4 */ A.A4,
+ A.GND, /* VSS |8 9| A3 */ A.A3
+ /* +------------+ */
+ )
+NETLIST_END()
+
/* 2102: 1024 x 1-bit Static RAM
*
* +--------------+
@@ -402,6 +435,7 @@ NETLIST_START(roms_lib)
LOCAL_LIB_ENTRY(TTL_82S16_DIP)
LOCAL_LIB_ENTRY(PROM_82S115_DIP)
LOCAL_LIB_ENTRY(PROM_MK28000_DIP)
+ LOCAL_LIB_ENTRY(ROM_MCM14524_DIP)
LOCAL_LIB_ENTRY(RAM_2102A_DIP)
LOCAL_LIB_ENTRY(ROM_TMS4800_DIP)
NETLIST_END()