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author couriersud <couriersud@gmx.org>2020-08-02 13:43:32 +0200
committer couriersud <couriersud@gmx.org>2020-08-02 13:43:32 +0200
commit759ee2932991c9bb89d09c1f4ccfb6918883a51e (patch)
treed39941c74e99901eb2528910501a49f4aabf7350
parentcfcae647d548fca2f823812e8ac7ef288672e350 (diff)
netlist: Move documentation from header to cpp file. Batch 1.
-rw-r--r--src/lib/netlist/devices/nld_2102A.cpp16
-rw-r--r--src/lib/netlist/devices/nld_2102A.h20
-rw-r--r--src/lib/netlist/devices/nld_4006.cpp36
-rw-r--r--src/lib/netlist/devices/nld_4006.h38
-rw-r--r--src/lib/netlist/devices/nld_4013.cpp34
-rw-r--r--src/lib/netlist/devices/nld_4013.h38
-rw-r--r--src/lib/netlist/devices/nld_4017.cpp34
-rw-r--r--src/lib/netlist/devices/nld_4017.h36
-rw-r--r--src/lib/netlist/devices/nld_4020.cpp34
-rw-r--r--src/lib/netlist/devices/nld_4020.h36
-rw-r--r--src/lib/netlist/devices/nld_4053.cpp20
-rw-r--r--src/lib/netlist/devices/nld_4053.h22
-rw-r--r--src/lib/netlist/devices/nld_4066.cpp18
-rw-r--r--src/lib/netlist/devices/nld_4066.h20
-rw-r--r--src/lib/netlist/devices/nld_4316.cpp19
-rw-r--r--src/lib/netlist/devices/nld_4316.h21
-rw-r--r--src/lib/netlist/devices/nld_74107.cpp58
-rw-r--r--src/lib/netlist/devices/nld_74107.h60
-rw-r--r--src/lib/netlist/devices/nld_74113.cpp54
-rw-r--r--src/lib/netlist/devices/nld_74113.h56
-rw-r--r--src/lib/netlist/devices/nld_74123.cpp43
-rw-r--r--src/lib/netlist/devices/nld_74123.h45
-rw-r--r--src/lib/netlist/devices/nld_74153.cpp39
-rw-r--r--src/lib/netlist/devices/nld_74153.h41
-rw-r--r--src/lib/netlist/devices/nld_74164.cpp38
-rw-r--r--src/lib/netlist/devices/nld_74164.h38
-rw-r--r--src/lib/netlist/devices/nld_74165.cpp19
-rw-r--r--src/lib/netlist/devices/nld_74165.h23
-rw-r--r--src/lib/netlist/devices/nld_74166.cpp19
-rw-r--r--src/lib/netlist/devices/nld_74166.h23
-rw-r--r--src/lib/netlist/devices/nld_74174.cpp28
-rw-r--r--src/lib/netlist/devices/nld_74174.h32
-rw-r--r--src/lib/netlist/devices/nld_74175.cpp30
-rw-r--r--src/lib/netlist/devices/nld_74175.h32
-rw-r--r--src/lib/netlist/devices/nld_74192.cpp23
-rw-r--r--src/lib/netlist/devices/nld_74192.h25
-rw-r--r--src/lib/netlist/devices/nld_74193.cpp20
-rw-r--r--src/lib/netlist/devices/nld_74193.h22
-rw-r--r--src/lib/netlist/devices/nld_74194.cpp19
-rw-r--r--src/lib/netlist/devices/nld_74194.h23
-rw-r--r--src/lib/netlist/devices/nld_74365.cpp17
-rw-r--r--src/lib/netlist/devices/nld_74365.h22
-rw-r--r--src/lib/netlist/devices/nld_74377.cpp45
-rw-r--r--src/lib/netlist/devices/nld_74377.h47
-rw-r--r--src/lib/netlist/devices/nld_74393.cpp16
-rw-r--r--src/lib/netlist/devices/nld_74393.h18
46 files changed, 664 insertions, 753 deletions
diff --git a/src/lib/netlist/devices/nld_2102A.cpp b/src/lib/netlist/devices/nld_2102A.cpp
index 134e2aae945..e2fcd7ef9e1 100644
--- a/src/lib/netlist/devices/nld_2102A.cpp
+++ b/src/lib/netlist/devices/nld_2102A.cpp
@@ -3,6 +3,22 @@
/*
* nld_2102A.cpp
*
+ * 2102: 1024 x 1-bit Static RAM
+ *
+ * +--------------+
+ * A6 |1 ++ 16| A7
+ * A5 |2 15| A8
+ * RWQ |3 14| A9
+ * A1 |4 82S16 13| CEQ
+ * A2 |5 12| DO
+ * A3 |6 11| DI
+ * A4 |7 10| VCC
+ * A0 |8 9| GND
+ * +--------------+
+ *
+ *
+ * Naming conventions follow Intel datasheet
+ *
*/
#include "nld_2102A.h"
diff --git a/src/lib/netlist/devices/nld_2102A.h b/src/lib/netlist/devices/nld_2102A.h
index b617a209fdc..30e693f0e00 100644
--- a/src/lib/netlist/devices/nld_2102A.h
+++ b/src/lib/netlist/devices/nld_2102A.h
@@ -1,25 +1,5 @@
// license:BSD-3-Clause
// copyright-holders:Ryan Holtz
-/*
- * nld_2102A.h
- *
- * 2102: 1024 x 1-bit Static RAM
- *
- * +--------------+
- * A6 |1 ++ 16| A7
- * A5 |2 15| A8
- * RWQ |3 14| A9
- * A1 |4 82S16 13| CEQ
- * A2 |5 12| DO
- * A3 |6 11| DI
- * A4 |7 10| VCC
- * A0 |8 9| GND
- * +--------------+
- *
- *
- * Naming conventions follow Intel datasheet
- *
- */
#ifndef NLD_2102A_H_
#define NLD_2102A_H_
diff --git a/src/lib/netlist/devices/nld_4006.cpp b/src/lib/netlist/devices/nld_4006.cpp
index d616c7c7258..1e49a46b724 100644
--- a/src/lib/netlist/devices/nld_4006.cpp
+++ b/src/lib/netlist/devices/nld_4006.cpp
@@ -1,7 +1,41 @@
// license:GPL-2.0+
// copyright-holders:Couriersud
/*
- * nld_4006.c
+ * nld_4006.cpp
+ *
+ * CD4006: CMOS 18-Stage Static Register
+ *
+ * Description
+ *
+ * CD4006BMS types are composed of 4 separate shift register sections: two
+ * sections of four stages and two sections of five stages with an output tap
+ * at the fourth stage. Each section has an independent single-rail data path.
+ *
+ * A common clock signal is used for all stages. Data are shifted to the next
+ * stages on negative-going transitions of the clock. Through appropriate
+ * connections of inputs and outputs, multiple register sections of 4, 5, 8,
+ * and 9 stages or single register sections of 10, 12, 13, 14, 16, 17 and 18
+ * stages can be implemented using one CD4006BMS package. Longer shift register
+ * sections can be assembled by using more than one CD4006BMS.
+ *
+ * To facilitate cascading stages when clock rise and fall times are slow,
+ * an optional output (D1 + 4’) that is delayed one-half clockcycle, is
+ * provided.
+ *
+ * +--------------+
+ * D1 |1 ++ 14| VDD
+ * D1+4' |2 13| D1+4
+ * CLOCK |3 12| D2+5
+ * D2 |4 4006 11| D2+4
+ * D3 |5 10| D3+4
+ * D4 |6 9| D4+5
+ * VSS |7 8| D4+4
+ * +--------------+
+ *
+ *
+ * Naming conventions follow SYC datasheet
+ *
+ * FIXME: Timing depends on VDD-VSS
*
*/
diff --git a/src/lib/netlist/devices/nld_4006.h b/src/lib/netlist/devices/nld_4006.h
index 77ff7528fc8..86092c254dc 100644
--- a/src/lib/netlist/devices/nld_4006.h
+++ b/src/lib/netlist/devices/nld_4006.h
@@ -1,43 +1,5 @@
// license:GPL-2.0+
// copyright-holders:Couriersud
-/*
- * nld_4006.h
- *
- * CD4006: CMOS 18-Stage Static Register
- *
- * Description
- *
- * CD4006BMS types are composed of 4 separate shift register sections: two
- * sections of four stages and two sections of five stages with an output tap
- * at the fourth stage. Each section has an independent single-rail data path.
- *
- * A common clock signal is used for all stages. Data are shifted to the next
- * stages on negative-going transitions of the clock. Through appropriate
- * connections of inputs and outputs, multiple register sections of 4, 5, 8,
- * and 9 stages or single register sections of 10, 12, 13, 14, 16, 17 and 18
- * stages can be implemented using one CD4006BMS package. Longer shift register
- * sections can be assembled by using more than one CD4006BMS.
- *
- * To facilitate cascading stages when clock rise and fall times are slow,
- * an optional output (D1 + 4’) that is delayed one-half clockcycle, is
- * provided.
- *
- * +--------------+
- * D1 |1 ++ 14| VDD
- * D1+4' |2 13| D1+4
- * CLOCK |3 12| D2+5
- * D2 |4 4006 11| D2+4
- * D3 |5 10| D3+4
- * D4 |6 9| D4+5
- * VSS |7 8| D4+4
- * +--------------+
- *
- *
- * Naming conventions follow SYC datasheet
- *
- * FIXME: Timing depends on VDD-VSS
- *
- */
#ifndef NLD_4006_H_
#define NLD_4006_H_
diff --git a/src/lib/netlist/devices/nld_4013.cpp b/src/lib/netlist/devices/nld_4013.cpp
index 455a4926d1f..66d03e09fbd 100644
--- a/src/lib/netlist/devices/nld_4013.cpp
+++ b/src/lib/netlist/devices/nld_4013.cpp
@@ -3,6 +3,40 @@
/*
* nld_4013.cpp
*
+ * CD4013: Dual Positive-Edge-Triggered D Flip-Flops
+ * with Set, Reset and Complementary Outputs
+ *
+ * +--------------+
+ * Q1 |1 ++ 14| VDD
+ * Q1Q |2 13| Q2
+ * CLOCK1 |3 12| Q2Q
+ * RESET1 |4 4013 11| CLOCK2
+ * DATA1 |5 10| RESET2
+ * SET1 |6 9| DATA2
+ * VSS |7 8| SET2
+ * +--------------+
+ *
+ * +-----+-----+-----+---++---+-----+
+ * | SET | RES | CLK | D || Q | QQ |
+ * +=====+=====+=====+===++===+=====+
+ * | 1 | 0 | X | X || 1 | 0 |
+ * | 0 | 1 | X | X || 0 | 1 |
+ * | 1 | 1 | X | X || 1 | 1 | (*)
+ * | 0 | 0 | R | 1 || 1 | 0 |
+ * | 0 | 0 | R | 0 || 0 | 1 |
+ * | 0 | 0 | 0 | X || Q0| Q0Q |
+ * +-----+-----+-----+---++---+-----+
+ *
+ * (*) This configuration is not stable, i.e. it will not persist
+ * when either the preset and or clear inputs return to their inactive (high) level
+ *
+ * Q0 The output logic level of Q before the indicated input conditions were established
+ *
+ * R: 0 -. 1
+ *
+ * Naming conventions follow National Semiconductor datasheet
+ *
+ * FIXME: Check that (*) is emulated properly
*/
#include "netlist/nl_base.h"
diff --git a/src/lib/netlist/devices/nld_4013.h b/src/lib/netlist/devices/nld_4013.h
index bb47796a553..7a2623bb8df 100644
--- a/src/lib/netlist/devices/nld_4013.h
+++ b/src/lib/netlist/devices/nld_4013.h
@@ -1,43 +1,5 @@
// license:GPL-2.0+
// copyright-holders:Couriersud
-/*
- * nld_4013.h
- *
- * CD4013: Dual Positive-Edge-Triggered D Flip-Flops
- * with Set, Reset and Complementary Outputs
- *
- * +--------------+
- * Q1 |1 ++ 14| VDD
- * Q1Q |2 13| Q2
- * CLOCK1 |3 12| Q2Q
- * RESET1 |4 4013 11| CLOCK2
- * DATA1 |5 10| RESET2
- * SET1 |6 9| DATA2
- * VSS |7 8| SET2
- * +--------------+
- *
- * +-----+-----+-----+---++---+-----+
- * | SET | RES | CLK | D || Q | QQ |
- * +=====+=====+=====+===++===+=====+
- * | 1 | 0 | X | X || 1 | 0 |
- * | 0 | 1 | X | X || 0 | 1 |
- * | 1 | 1 | X | X || 1 | 1 | (*)
- * | 0 | 0 | R | 1 || 1 | 0 |
- * | 0 | 0 | R | 0 || 0 | 1 |
- * | 0 | 0 | 0 | X || Q0| Q0Q |
- * +-----+-----+-----+---++---+-----+
- *
- * (*) This configuration is not stable, i.e. it will not persist
- * when either the preset and or clear inputs return to their inactive (high) level
- *
- * Q0 The output logic level of Q before the indicated input conditions were established
- *
- * R: 0 -. 1
- *
- * Naming conventions follow National Semiconductor datasheet
- *
- * FIXME: Check that (*) is emulated properly
- */
#ifndef NLD_4013_H_
#define NLD_4013_H_
diff --git a/src/lib/netlist/devices/nld_4017.cpp b/src/lib/netlist/devices/nld_4017.cpp
index c396ff73cd2..d680eaa4829 100644
--- a/src/lib/netlist/devices/nld_4017.cpp
+++ b/src/lib/netlist/devices/nld_4017.cpp
@@ -1,7 +1,39 @@
// license:GPL-2.0+
// copyright-holders:Couriersud
/*
- * nld_4017.c
+ * nld_4017.cpp
+ *
+ * CD4017: Decade Counter/Divider with 10 Decoded Outputs
+ *
+ * +--------------+
+ * Q5 |1 ++ 16| VDD
+ * Q1 |2 15| RESET
+ * Q0 |3 14| CLOCK
+ * Q2 |4 4017 13| CLOCK ENABLE
+ * Q6 |5 12| CARRY OUT
+ * Q7 |6 11| Q9
+ * Q3 |7 10| Q4
+ * VSS |8 9| Q8
+ * +--------------+
+ *
+ *
+ * CD4022: Divide-by-8 Counter/Divider with 8 Decoded Outputs
+ *
+ * +--------------+
+ * Q1 |1 ++ 16| VDD
+ * Q0 |2 15| RESET
+ * Q2 |3 14| CLOCK
+ * Q5 |4 4022 13| CLOCK ENABLE
+ * Q6 |5 12| CARRY OUT
+ * NC |6 11| Q4
+ * Q3 |7 10| Q7
+ * VSS |8 9| NC
+ * +--------------+
+ *
+ * Naming conventions follow Fairchild datasheet
+ *
+ * FIXME: Timing depends on VDD-VSS
+ * This needs a cmos d-a/a-d proxy implementation.
*
*/
diff --git a/src/lib/netlist/devices/nld_4017.h b/src/lib/netlist/devices/nld_4017.h
index 58ff0dabcb9..e97c45586ca 100644
--- a/src/lib/netlist/devices/nld_4017.h
+++ b/src/lib/netlist/devices/nld_4017.h
@@ -1,41 +1,5 @@
// license:GPL-2.0+
// copyright-holders:Couriersud
-/*
- * nld_4017.h
- *
- * CD4017: Decade Counter/Divider with 10 Decoded Outputs
- *
- * +--------------+
- * Q5 |1 ++ 16| VDD
- * Q1 |2 15| RESET
- * Q0 |3 14| CLOCK
- * Q2 |4 4017 13| CLOCK ENABLE
- * Q6 |5 12| CARRY OUT
- * Q7 |6 11| Q9
- * Q3 |7 10| Q4
- * VSS |8 9| Q8
- * +--------------+
- *
- *
- * CD4022: Divide-by-8 Counter/Divider with 8 Decoded Outputs
- *
- * +--------------+
- * Q1 |1 ++ 16| VDD
- * Q0 |2 15| RESET
- * Q2 |3 14| CLOCK
- * Q5 |4 4022 13| CLOCK ENABLE
- * Q6 |5 12| CARRY OUT
- * NC |6 11| Q4
- * Q3 |7 10| Q7
- * VSS |8 9| NC
- * +--------------+
- *
- * Naming conventions follow Fairchild datasheet
- *
- * FIXME: Timing depends on VDD-VSS
- * This needs a cmos d-a/a-d proxy implementation.
- *
- */
#ifndef NLD_4017_H_
#define NLD_4017_H_
diff --git a/src/lib/netlist/devices/nld_4020.cpp b/src/lib/netlist/devices/nld_4020.cpp
index b6ae2b45bd1..4143f66da8d 100644
--- a/src/lib/netlist/devices/nld_4020.cpp
+++ b/src/lib/netlist/devices/nld_4020.cpp
@@ -1,7 +1,39 @@
// license:GPL-2.0+
// copyright-holders:Couriersud
/*
- * nld_4020.c
+ * nld_4020.cpp
+ *
+ * CD4020: 14-Stage Ripple Carry Binary Counters
+ *
+ * +--------------+
+ * Q12 |1 ++ 16| VDD
+ * Q13 |2 15| Q11
+ * Q14 |3 14| Q10
+ * Q6 |4 4020 13| Q8
+ * Q5 |5 12| Q9
+ * Q7 |6 11| RESET
+ * Q4 |7 10| IP (Input pulses)
+ * VSS |8 9| Q1
+ * +--------------+
+ *
+ *
+ * CD4024: 7-Stage Ripple Carry Binary Counters
+ *
+ * +--------------+
+ * IP |1 ++ 14| VDD
+ * RESET |2 13| NC
+ * Q7 |3 12| Q1
+ * Q6 |4 4024 11| Q2
+ * Q5 |5 10| NC
+ * Q4 |6 9| Q3
+ * VSS |7 8| NC
+ * +--------------+
+ *
+ *
+ * Naming conventions follow Texas Instruments datasheet
+ *
+ * FIXME: Timing depends on VDD-VSS
+ * This needs a cmos d-a/a-d proxy implementation.
*
*/
diff --git a/src/lib/netlist/devices/nld_4020.h b/src/lib/netlist/devices/nld_4020.h
index d3c9a60acd6..942b2f2d457 100644
--- a/src/lib/netlist/devices/nld_4020.h
+++ b/src/lib/netlist/devices/nld_4020.h
@@ -1,41 +1,5 @@
// license:GPL-2.0+
// copyright-holders:Couriersud
-/*
- * nld_4020.h
- *
- * CD4020: 14-Stage Ripple Carry Binary Counters
- *
- * +--------------+
- * Q12 |1 ++ 16| VDD
- * Q13 |2 15| Q11
- * Q14 |3 14| Q10
- * Q6 |4 4020 13| Q8
- * Q5 |5 12| Q9
- * Q7 |6 11| RESET
- * Q4 |7 10| IP (Input pulses)
- * VSS |8 9| Q1
- * +--------------+
- *
- *
- * CD4024: 7-Stage Ripple Carry Binary Counters
- *
- * +--------------+
- * IP |1 ++ 14| VDD
- * RESET |2 13| NC
- * Q7 |3 12| Q1
- * Q6 |4 4024 11| Q2
- * Q5 |5 10| NC
- * Q4 |6 9| Q3
- * VSS |7 8| NC
- * +--------------+
- *
- *
- * Naming conventions follow Texas Instruments datasheet
- *
- * FIXME: Timing depends on VDD-VSS
- * This needs a cmos d-a/a-d proxy implementation.
- *
- */
#ifndef NLD_4020_H_
#define NLD_4020_H_
diff --git a/src/lib/netlist/devices/nld_4053.cpp b/src/lib/netlist/devices/nld_4053.cpp
index 37099e2d9d1..62db781fbfa 100644
--- a/src/lib/netlist/devices/nld_4053.cpp
+++ b/src/lib/netlist/devices/nld_4053.cpp
@@ -1,10 +1,28 @@
// license:GPL-2.0+
// copyright-holders:Couriersud
/*
- * nld_4053.c
+ * nld_4053.cpp
+ *
+ * CD4053: Triple 2-Channel Analog Multiplexer/Demultiplexer
+ *
+ * +--------------+
+ * INOUTBY |1 ++ 16| VDD
+ * INOUTBX |2 15| OUTINB
+ * INOUTCY |3 14| OUTINA
+ * OUTINC |4 4053 13| INOUTAY
+ * INOUTCX |5 12| INOUTAX
+ * INH |6 11| A
+ * VEE |7 10| B
+ * VSS |8 9| C
+ * +--------------+
+ *
+ * FIXME: These devices are slow (~125 ns). This is currently not reflected
+ *
+ * Naming conventions follow National semiconductor datasheet
*
*/
+
#include "nld_4053.h"
#include "netlist/analog/nlid_twoterm.h"
diff --git a/src/lib/netlist/devices/nld_4053.h b/src/lib/netlist/devices/nld_4053.h
index 27c2257cc65..83636ef636c 100644
--- a/src/lib/netlist/devices/nld_4053.h
+++ b/src/lib/netlist/devices/nld_4053.h
@@ -1,27 +1,5 @@
// license:GPL-2.0+
// copyright-holders:Couriersud
-/*
- * nld_4053.h
- *
- * CD4053: Triple 2-Channel Analog Multiplexer/Demultiplexer
- *
- * +--------------+
- * INOUTBY |1 ++ 16| VDD
- * INOUTBX |2 15| OUTINB
- * INOUTCY |3 14| OUTINA
- * OUTINC |4 4053 13| INOUTAY
- * INOUTCX |5 12| INOUTAX
- * INH |6 11| A
- * VEE |7 10| B
- * VSS |8 9| C
- * +--------------+
- *
- * FIXME: These devices are slow (~125 ns). This is currently not reflected
- *
- * Naming conventions follow National semiconductor datasheet
- *
- */
-
#ifndef NLD_4053_H_
#define NLD_4053_H_
diff --git a/src/lib/netlist/devices/nld_4066.cpp b/src/lib/netlist/devices/nld_4066.cpp
index fd66d982ac5..1c6723dcb1e 100644
--- a/src/lib/netlist/devices/nld_4066.cpp
+++ b/src/lib/netlist/devices/nld_4066.cpp
@@ -1,7 +1,23 @@
// license:GPL-2.0+
// copyright-holders:Couriersud
/*
- * nld_4066.c
+ * nld_4066.cpp
+ *
+ * CD4066: Quad Bilateral Switch
+ *
+ * +--------------+
+ * INOUTA |1 ++ 14| VDD
+ * OUTINA |2 13| CONTROLA
+ * OUTINB |3 12| CONTROLD
+ * INOUTB |4 4066 11| INOUTD
+ * CONTROLB |5 10| OUTIND
+ * CONTROLC |6 9| OUTINC
+ * VSS |7 8| INOUTC
+ * +--------------+
+ *
+ * FIXME: These devices are slow (~125 ns). This is currently not reflected
+ *
+ * Naming conventions follow National semiconductor datasheet
*
*/
diff --git a/src/lib/netlist/devices/nld_4066.h b/src/lib/netlist/devices/nld_4066.h
index 0a43911d3ce..f30369f28d3 100644
--- a/src/lib/netlist/devices/nld_4066.h
+++ b/src/lib/netlist/devices/nld_4066.h
@@ -1,25 +1,5 @@
// license:GPL-2.0+
// copyright-holders:Couriersud
-/*
- * nld_4066.h
- *
- * CD4066: Quad Bilateral Switch
- *
- * +--------------+
- * INOUTA |1 ++ 14| VDD
- * OUTINA |2 13| CONTROLA
- * OUTINB |3 12| CONTROLD
- * INOUTB |4 4066 11| INOUTD
- * CONTROLB |5 10| OUTIND
- * CONTROLC |6 9| OUTINC
- * VSS |7 8| INOUTC
- * +--------------+
- *
- * FIXME: These devices are slow (~125 ns). This is currently not reflected
- *
- * Naming conventions follow National semiconductor datasheet
- *
- */
#ifndef NLD_4066_H_
#define NLD_4066_H_
diff --git a/src/lib/netlist/devices/nld_4316.cpp b/src/lib/netlist/devices/nld_4316.cpp
index 7c0159dbe91..9bd042e1bcd 100644
--- a/src/lib/netlist/devices/nld_4316.cpp
+++ b/src/lib/netlist/devices/nld_4316.cpp
@@ -1,7 +1,24 @@
// license:BSD-3-Clause
// copyright-holders:Vas Crabb
/*
- * nld_4316.c
+ * nld_4316.cpp
+ *
+ * CD4066: Quad Analog Switch with Level Translation
+ *
+ * +--------------+
+ * 1Z |1 ++ 16| VCC
+ * 1Y |2 15| 1S
+ * 2Y |3 14| 4S
+ * 2Z |4 4316 13| 4Z
+ * 2S |5 12| 4Y
+ * 3S |6 11| 3Y
+ * /E |7 10| 3Z
+ * GND |8 9| VEE
+ * +--------------+
+ *
+ * FIXME: These devices are slow (can be over 200 ns in HC types). This is currently not reflected
+ *
+ * Naming conventions follow Texas Instruments datasheet
*
*/
diff --git a/src/lib/netlist/devices/nld_4316.h b/src/lib/netlist/devices/nld_4316.h
index d19e16d171c..35c94bd30a0 100644
--- a/src/lib/netlist/devices/nld_4316.h
+++ b/src/lib/netlist/devices/nld_4316.h
@@ -1,26 +1,5 @@
// license:BSD-3-Clause
// copyright-holders:Vas Crabb
-/*
- * nld_4316.h
- *
- * CD4066: Quad Analog Switch with Level Translation
- *
- * +--------------+
- * 1Z |1 ++ 16| VCC
- * 1Y |2 15| 1S
- * 2Y |3 14| 4S
- * 2Z |4 4316 13| 4Z
- * 2S |5 12| 4Y
- * 3S |6 11| 3Y
- * /E |7 10| 3Z
- * GND |8 9| VEE
- * +--------------+
- *
- * FIXME: These devices are slow (can be over 200 ns in HC types). This is currently not reflected
- *
- * Naming conventions follow Texas Instruments datasheet
- *
- */
#ifndef NLD_4316_H_
#define NLD_4316_H_
diff --git a/src/lib/netlist/devices/nld_74107.cpp b/src/lib/netlist/devices/nld_74107.cpp
index 4c24bd760f4..26df3f65bee 100644
--- a/src/lib/netlist/devices/nld_74107.cpp
+++ b/src/lib/netlist/devices/nld_74107.cpp
@@ -1,7 +1,63 @@
// license:GPL-2.0+
// copyright-holders:Couriersud
/*
- * nld_74107.c
+ * nld_74107.cpp
+ *
+ * DM74107: DUAL J-K FLIP-FLOPS WITH CLEAR
+ *
+ * +--------------+
+ * 1J |1 ++ 14| VCC
+ * 1QQ |2 13| 1CLRQ
+ * 1Q |3 12| 1CLK
+ * 1K |4 74107 11| 2K
+ * 2Q |5 10| 2CLRQ
+ * 2QQ |6 9| 2CLK
+ * GND |7 8| 2J
+ * +--------------+
+ *
+ *
+ * Function table 107
+ *
+ * +-----+-----+-----+---++---+-----+
+ * | CLRQ| CLK | J | K || Q | QQ |
+ * +=====+=====+=====+===++===+=====+
+ * | 0 | X | X | X || 0 | 1 |
+ * | 1 | * | 0 | 0 || Q0| Q0Q |
+ * | 1 | * | 1 | 0 || 1 | 0 |
+ * | 1 | * | 0 | 1 || 0 | 1 |
+ * | 1 | * | 1 | 1 || TOGGLE |
+ * +-----+-----+-----+---++---+-----+
+ * _
+ * * = _| |_
+ *
+ * This is positive triggered, J and K
+ * are latched during clock high and
+ * transferred when CLK falls. The
+ * datasheet requires J and K to be
+ * stable during clock high.
+ *
+ * Function table 107A
+ *
+ * +-----+-----+-----+---++---+-----+
+ * | CLRQ| CLK | J | K || Q | QQ |
+ * +=====+=====+=====+===++===+=====+
+ * | 0 | X | X | X || 0 | 1 |
+ * | 1 | F | 0 | 0 || Q0| Q0Q |
+ * | 1 | F | 1 | 0 || 1 | 0 |
+ * | 1 | F | 0 | 1 || 0 | 1 |
+ * | 1 | F | 1 | 1 || TOGGLE |
+ * | 1 | 1 | X | X || Q0| Q0Q |
+ * +-----+-----+-----+---++---+-----+
+ *
+ * THe 107A is negative triggered.
+ *
+ * Naming conventions follow Texas instruments datasheet
+ *
+ * TODO: Currently, only the 107A is implemented.
+ * The 107 uses the same model, but different timings.
+ * The requirement that J and K must be stable during
+ * clock high indicates that the chip may exhibit undefined
+ * behaviour.
*
*/
diff --git a/src/lib/netlist/devices/nld_74107.h b/src/lib/netlist/devices/nld_74107.h
index 6ca1316b0bf..3a954dbe09a 100644
--- a/src/lib/netlist/devices/nld_74107.h
+++ b/src/lib/netlist/devices/nld_74107.h
@@ -1,65 +1,5 @@
// license:GPL-2.0+
// copyright-holders:Couriersud
-/*
- * nld_74107.h
- *
- * DM74107: DUAL J-K FLIP-FLOPS WITH CLEAR
- *
- * +--------------+
- * 1J |1 ++ 14| VCC
- * 1QQ |2 13| 1CLRQ
- * 1Q |3 12| 1CLK
- * 1K |4 74107 11| 2K
- * 2Q |5 10| 2CLRQ
- * 2QQ |6 9| 2CLK
- * GND |7 8| 2J
- * +--------------+
- *
- *
- * Function table 107
- *
- * +-----+-----+-----+---++---+-----+
- * | CLRQ| CLK | J | K || Q | QQ |
- * +=====+=====+=====+===++===+=====+
- * | 0 | X | X | X || 0 | 1 |
- * | 1 | * | 0 | 0 || Q0| Q0Q |
- * | 1 | * | 1 | 0 || 1 | 0 |
- * | 1 | * | 0 | 1 || 0 | 1 |
- * | 1 | * | 1 | 1 || TOGGLE |
- * +-----+-----+-----+---++---+-----+
- * _
- * * = _| |_
- *
- * This is positive triggered, J and K
- * are latched during clock high and
- * transferred when CLK falls. The
- * datasheet requires J and K to be
- * stable during clock high.
- *
- * Function table 107A
- *
- * +-----+-----+-----+---++---+-----+
- * | CLRQ| CLK | J | K || Q | QQ |
- * +=====+=====+=====+===++===+=====+
- * | 0 | X | X | X || 0 | 1 |
- * | 1 | F | 0 | 0 || Q0| Q0Q |
- * | 1 | F | 1 | 0 || 1 | 0 |
- * | 1 | F | 0 | 1 || 0 | 1 |
- * | 1 | F | 1 | 1 || TOGGLE |
- * | 1 | 1 | X | X || Q0| Q0Q |
- * +-----+-----+-----+---++---+-----+
- *
- * THe 107A is negative triggered.
- *
- * Naming conventions follow Texas instruments datasheet
- *
- * TODO: Currently, only the 107A is implemented.
- * The 107 uses the same model, but different timings.
- * The requirement that J and K must be stable during
- * clock high indicates that the chip may exhibit undefined
- * behaviour.
- *
- */
#ifndef NLD_74107_H_
#define NLD_74107_H_
diff --git a/src/lib/netlist/devices/nld_74113.cpp b/src/lib/netlist/devices/nld_74113.cpp
index 37b81c01499..1198771695e 100644
--- a/src/lib/netlist/devices/nld_74113.cpp
+++ b/src/lib/netlist/devices/nld_74113.cpp
@@ -1,7 +1,59 @@
// license:GPL-2.0+
// copyright-holders:Couriersud
/*
- * nld_74113.c
+ * nld_74113.cpp
+ *
+ * 74113: Dual Master-Slave J-K Flip-Flops with Set and Complementary Outputs
+ * 74113A: Dual Negative-Edge-Triggered Master-Slave J-K Flip-Flops with Set and Complementary Outputs
+ *
+ * +----------+
+ * 1CLK |1 ++ 14| VCC
+ * 1K |2 13| 2CLK
+ * 1J |3 12| 2K
+ * 1SETQ |4 74113 11| 2J
+ * 1Q |5 10| 2SETQ
+ * 1QQ |6 9| 2Q
+ * GND |7 8| 2QQ
+ * +----------+
+ *
+ *
+ * Function table 113
+ *
+ * +-----+-----+-----+---++---+-----+
+ * | SETQ| CLK | J | K || Q | QQ |
+ * +=====+=====+=====+===++===+=====+
+ * | 0 | X | X | X || 1 | 0 |
+ * | 1 | * | 0 | 0 || Q0| Q0Q |
+ * | 1 | * | 1 | 0 || 1 | 0 |
+ * | 1 | * | 0 | 1 || 0 | 1 |
+ * | 1 | * | 1 | 1 || TOGGLE |
+ * +-----+-----+-----+---++---+-----+
+ * _
+ * * = _| |_
+ *
+ * This is positive triggered, J and K
+ * are latched during clock high and
+ * transferred when CLK falls.
+ *
+ * Function table 113A
+ *
+ * +-----+-----+-----+---++---+-----+
+ * | CLRQ| CLK | J | K || Q | QQ |
+ * +=====+=====+=====+===++===+=====+
+ * | 0 | X | X | X || 0 | 1 |
+ * | 1 | F | 0 | 0 || Q0| Q0Q |
+ * | 1 | F | 1 | 0 || 1 | 0 |
+ * | 1 | F | 0 | 1 || 0 | 1 |
+ * | 1 | F | 1 | 1 || TOGGLE |
+ * | 1 | 1 | X | X || Q0| Q0Q |
+ * +-----+-----+-----+---++---+-----+
+ *
+ * THe 113A is negative triggered.
+ *
+ * Naming conventions follow Texas instruments datasheet
+ *
+ * FIXME: Currently, only the 113 is implemented.
+ * The 113A uses the same model.
*
*/
diff --git a/src/lib/netlist/devices/nld_74113.h b/src/lib/netlist/devices/nld_74113.h
index e43915d8e9d..0a33de8cac6 100644
--- a/src/lib/netlist/devices/nld_74113.h
+++ b/src/lib/netlist/devices/nld_74113.h
@@ -1,61 +1,5 @@
// license:GPL-2.0+
// copyright-holders:Couriersud
-/*
- * nld_74113.h
- *
- * 74113: Dual Master-Slave J-K Flip-Flops with Set and Complementary Outputs
- * 74113A: Dual Negative-Edge-Triggered Master-Slave J-K Flip-Flops with Set and Complementary Outputs
- *
- * +----------+
- * 1CLK |1 ++ 14| VCC
- * 1K |2 13| 2CLK
- * 1J |3 12| 2K
- * 1SETQ |4 74113 11| 2J
- * 1Q |5 10| 2SETQ
- * 1QQ |6 9| 2Q
- * GND |7 8| 2QQ
- * +----------+
- *
- *
- * Function table 113
- *
- * +-----+-----+-----+---++---+-----+
- * | SETQ| CLK | J | K || Q | QQ |
- * +=====+=====+=====+===++===+=====+
- * | 0 | X | X | X || 1 | 0 |
- * | 1 | * | 0 | 0 || Q0| Q0Q |
- * | 1 | * | 1 | 0 || 1 | 0 |
- * | 1 | * | 0 | 1 || 0 | 1 |
- * | 1 | * | 1 | 1 || TOGGLE |
- * +-----+-----+-----+---++---+-----+
- * _
- * * = _| |_
- *
- * This is positive triggered, J and K
- * are latched during clock high and
- * transferred when CLK falls.
- *
- * Function table 113A
- *
- * +-----+-----+-----+---++---+-----+
- * | CLRQ| CLK | J | K || Q | QQ |
- * +=====+=====+=====+===++===+=====+
- * | 0 | X | X | X || 0 | 1 |
- * | 1 | F | 0 | 0 || Q0| Q0Q |
- * | 1 | F | 1 | 0 || 1 | 0 |
- * | 1 | F | 0 | 1 || 0 | 1 |
- * | 1 | F | 1 | 1 || TOGGLE |
- * | 1 | 1 | X | X || Q0| Q0Q |
- * +-----+-----+-----+---++---+-----+
- *
- * THe 113A is negative triggered.
- *
- * Naming conventions follow Texas instruments datasheet
- *
- * FIXME: Currently, only the 113 is implemented.
- * The 113A uses the same model.
- *
- */
#ifndef NLD_74113_H_
#define NLD_74113_H_
diff --git a/src/lib/netlist/devices/nld_74123.cpp b/src/lib/netlist/devices/nld_74123.cpp
index 31f59dbbc22..f19f0042be1 100644
--- a/src/lib/netlist/devices/nld_74123.cpp
+++ b/src/lib/netlist/devices/nld_74123.cpp
@@ -1,7 +1,48 @@
// license:GPL-2.0+
// copyright-holders:Couriersud
/*
- * nld_74123.c
+ * nld_74123.cpp
+ *
+ * 74123: Dual Retriggerable One-Shot with Clear and Complementary Outputs
+ *
+ * +--------------+
+ * A1 |1 ++ 16| VCC
+ * B1 |2 15| RC1
+ * CLR1 |3 14| C1
+ * Q1Q |4 74123 13| Q1
+ * Q2 |5 12| Q2Q
+ * C2 |6 11| CLR2
+ * RC2 |7 10| B2
+ * GND |8 9| A2
+ * +--------------+
+ *
+ * Naming conventions follow Fairchild Semiconductor datasheet
+ *
+ * DM9602: Dual Retriggerable, Resettable One Shots
+ *
+ * +--------------+
+ * C1 |1 ++ 16| VCC
+ * RC1 |2 15| C2
+ * CLR1 |3 14| RC2
+ * B1 |4 9602 13| CLR2
+ * A1 |5 12| B2
+ * Q1 |6 11| A2
+ * Q1Q |7 10| Q2
+ * GND |8 9| Q2Q
+ * +--------------+
+ *
+ * CD4538: Dual Retriggerable, Resettable One Shots
+ *
+ * +--------------+
+ * C1 |1 ++ 16| VCC
+ * RC1 |2 15| C2
+ * CLR1 |3 14| RC2
+ * A1 |4 4538 13| CLR2
+ * B1 |5 12| A2
+ * Q1 |6 11| B2
+ * Q1Q |7 10| Q2
+ * GND |8 9| Q2Q
+ * +--------------+
*
*/
diff --git a/src/lib/netlist/devices/nld_74123.h b/src/lib/netlist/devices/nld_74123.h
index 9557b0382b6..be07c60f6d4 100644
--- a/src/lib/netlist/devices/nld_74123.h
+++ b/src/lib/netlist/devices/nld_74123.h
@@ -1,50 +1,5 @@
// license:GPL-2.0+
// copyright-holders:Couriersud
-/*
- * nld_74123.h
- *
- * 74123: Dual Retriggerable One-Shot with Clear and Complementary Outputs
- *
- * +--------------+
- * A1 |1 ++ 16| VCC
- * B1 |2 15| RC1
- * CLR1 |3 14| C1
- * Q1Q |4 74123 13| Q1
- * Q2 |5 12| Q2Q
- * C2 |6 11| CLR2
- * RC2 |7 10| B2
- * GND |8 9| A2
- * +--------------+
- *
- * Naming conventions follow Fairchild Semiconductor datasheet
- *
- * DM9602: Dual Retriggerable, Resettable One Shots
- *
- * +--------------+
- * C1 |1 ++ 16| VCC
- * RC1 |2 15| C2
- * CLR1 |3 14| RC2
- * B1 |4 9602 13| CLR2
- * A1 |5 12| B2
- * Q1 |6 11| A2
- * Q1Q |7 10| Q2
- * GND |8 9| Q2Q
- * +--------------+
- *
- * CD4538: Dual Retriggerable, Resettable One Shots
- *
- * +--------------+
- * C1 |1 ++ 16| VCC
- * RC1 |2 15| C2
- * CLR1 |3 14| RC2
- * A1 |4 4538 13| CLR2
- * B1 |5 12| A2
- * Q1 |6 11| B2
- * Q1Q |7 10| Q2
- * GND |8 9| Q2Q
- * +--------------+
- *
- */
#ifndef NLD_74123_H_
#define NLD_74123_H_
diff --git a/src/lib/netlist/devices/nld_74153.cpp b/src/lib/netlist/devices/nld_74153.cpp
index 09602abd2f8..6fea1a711d3 100644
--- a/src/lib/netlist/devices/nld_74153.cpp
+++ b/src/lib/netlist/devices/nld_74153.cpp
@@ -1,7 +1,44 @@
// license:GPL-2.0+
// copyright-holders:Couriersud
/*
- * nld_74153.c
+ * nld_74153.cpp
+ *
+ * DM74153: Dual 4-Line to 1-Line Data Selectors Multiplexers
+ *
+ * +--------------+
+ * G1 |1 ++ 16| VCC
+ * B |2 15| G2
+ * 1C3 |3 14| A
+ * 1C2 |4 74153 13| 2C3
+ * 1C1 |5 12| 2C2
+ * 1C0 |6 11| 2C1
+ * Y1 |7 10| 2C0
+ * GND |8 9| Y2
+ * +--------------+
+ *
+ *
+ * Function table
+ *
+ * +-----+-----++----+----+----+----++----+----+
+ * | B | A || C0 | C1 | C2 | C3 || G | Y |
+ * +=====+=====++====+====+====+====++====+====+
+ * | X | X || X | X | X | X || H | L |
+ * | L | L || L | X | X | X || L | L |
+ * | L | L || H | X | X | X || L | H |
+ * | L | H || X | L | X | X || L | L |
+ * | L | H || X | H | X | X || L | H |
+ * | H | L || X | X | L | X || L | L |
+ * | H | L || X | X | H | X || L | H |
+ * | H | H || X | X | X | L || L | L |
+ * | H | H || X | X | X | H || L | H |
+ * +-----+-----++----+----+----+----++----+----+
+ *
+ * A, B : Select Inputs
+ * C* : Data inputs
+ * G : Strobe
+ * Y : Output
+ *
+ * Naming conventions follow National Semiconductor datasheet
*
*/
diff --git a/src/lib/netlist/devices/nld_74153.h b/src/lib/netlist/devices/nld_74153.h
index 4a0e24d1aa3..b291e1dd231 100644
--- a/src/lib/netlist/devices/nld_74153.h
+++ b/src/lib/netlist/devices/nld_74153.h
@@ -1,46 +1,5 @@
// license:GPL-2.0+
// copyright-holders:Couriersud
-/*
- * nld_74153.h
- *
- * DM74153: Dual 4-Line to 1-Line Data Selectors Multiplexers
- *
- * +--------------+
- * G1 |1 ++ 16| VCC
- * B |2 15| G2
- * 1C3 |3 14| A
- * 1C2 |4 74153 13| 2C3
- * 1C1 |5 12| 2C2
- * 1C0 |6 11| 2C1
- * Y1 |7 10| 2C0
- * GND |8 9| Y2
- * +--------------+
- *
- *
- * Function table
- *
- * +-----+-----++----+----+----+----++----+----+
- * | B | A || C0 | C1 | C2 | C3 || G | Y |
- * +=====+=====++====+====+====+====++====+====+
- * | X | X || X | X | X | X || H | L |
- * | L | L || L | X | X | X || L | L |
- * | L | L || H | X | X | X || L | H |
- * | L | H || X | L | X | X || L | L |
- * | L | H || X | H | X | X || L | H |
- * | H | L || X | X | L | X || L | L |
- * | H | L || X | X | H | X || L | H |
- * | H | H || X | X | X | L || L | L |
- * | H | H || X | X | X | H || L | H |
- * +-----+-----++----+----+----+----++----+----+
- *
- * A, B : Select Inputs
- * C* : Data inputs
- * G : Strobe
- * Y : Output
- *
- * Naming conventions follow National Semiconductor datasheet
- *
- */
#ifndef NLD_74153_H_
#define NLD_74153_H_
diff --git a/src/lib/netlist/devices/nld_74164.cpp b/src/lib/netlist/devices/nld_74164.cpp
index 05aab8b5ccd..9626232a309 100644
--- a/src/lib/netlist/devices/nld_74164.cpp
+++ b/src/lib/netlist/devices/nld_74164.cpp
@@ -7,6 +7,44 @@
* implementing this was simple.
*
*/
+/*****************************************************************************
+
+ 5/74164 8-bit parallel-out serial shift registers
+
+***********************************************************************
+
+ Connection Diagram:
+ ___ ___
+ A 1 |* u | 14 Vcc
+ B 2 | | 13 QH
+ QA 3 | | 12 QG
+ QB 4 | | 11 QF
+ QC 5 | | 10 QE
+ QD 6 | | 9 *Clear
+ GND 7 |_______| 8 Clock
+
+***********************************************************************
+ Function Table:
+ +-------------------------+----------------+
+ | Inputs | Qutputs* |
+ +-------+-------+---------+----------------+
+ | Clear | Clock | A B | QA QB ... QH |
+ +-------+-------+---------+----------------+
+ | L | X | X X | L L L |
+ | H | L | X X | QA0 QB0 QH0 |
+ | H | ^ | H H | H QAn QGn |
+ | H | ^ | L X | L QAn QGn |
+ | H | ^ | X L | L QAn QGn |
+ +-------+-------+---------+----------------+
+
+ H = High Level (steady state)
+ L = Low Level (steady state)
+ X = Don't Care
+ ^ = Transition from low to high level
+ QA0, QB0 ... QH0 = The level of QA, QB ... QH before the indicated steady-state input conditions were established.
+ QAn, QGn = The level of QA or QG before the most recent ^ transition of the clock; indicates a 1 bit shift.
+
+**********************************************************************/
#include "nld_74164.h"
#include "netlist/nl_base.h"
diff --git a/src/lib/netlist/devices/nld_74164.h b/src/lib/netlist/devices/nld_74164.h
index f4da1568a85..f732301e1f9 100644
--- a/src/lib/netlist/devices/nld_74164.h
+++ b/src/lib/netlist/devices/nld_74164.h
@@ -1,43 +1,5 @@
// license:BSD-3-Clause
// copyright-holders:Joakim Larsson Edstrom
-/*****************************************************************************
-
- 5/74164 8-bit parallel-out serial shift registers
-
-***********************************************************************
-
- Connection Diagram:
- ___ ___
- A 1 |* u | 14 Vcc
- B 2 | | 13 QH
- QA 3 | | 12 QG
- QB 4 | | 11 QF
- QC 5 | | 10 QE
- QD 6 | | 9 *Clear
- GND 7 |_______| 8 Clock
-
-***********************************************************************
- Function Table:
- +-------------------------+----------------+
- | Inputs | Qutputs* |
- +-------+-------+---------+----------------+
- | Clear | Clock | A B | QA QB ... QH |
- +-------+-------+---------+----------------+
- | L | X | X X | L L L |
- | H | L | X X | QA0 QB0 QH0 |
- | H | ^ | H H | H QAn QGn |
- | H | ^ | L X | L QAn QGn |
- | H | ^ | X L | L QAn QGn |
- +-------+-------+---------+----------------+
-
- H = High Level (steady state)
- L = Low Level (steady state)
- X = Don't Care
- ^ = Transition from low to high level
- QA0, QB0 ... QH0 = The level of QA, QB ... QH before the indicated steady-state input conditions were established.
- QAn, QGn = The level of QA or QG before the most recent ^ transition of the clock; indicates a 1 bit shift.
-
-**********************************************************************/
#ifndef NLD_74164_H_
#define NLD_74164_H_
diff --git a/src/lib/netlist/devices/nld_74165.cpp b/src/lib/netlist/devices/nld_74165.cpp
index d27c14953ea..3db58672418 100644
--- a/src/lib/netlist/devices/nld_74165.cpp
+++ b/src/lib/netlist/devices/nld_74165.cpp
@@ -3,6 +3,25 @@
/*
* nld_74165.cpp
*
+ * 74165: Parallel-Load 8-Bit Shift Register
+ *
+ * +--------------+
+ * SH/LDQ |1 ++ 16| VCC
+ * CLK |2 15| CLKINH
+ * E |3 14| D
+ * F |4 74165 13| C
+ * G |5 12| B
+ * H |6 11| A
+ * QHQ |7 10| SER
+ * GND |8 9| QH
+ * +--------------+
+ *
+ * SH/LDQ: Shift / !Load
+ * CLKINH: Clock Inhibit
+ * SER: Serial In
+ *
+ * Naming convention attempts to follow NTE Electronics datasheet
+ *
*/
#include "nld_74165.h"
diff --git a/src/lib/netlist/devices/nld_74165.h b/src/lib/netlist/devices/nld_74165.h
index b4918276779..72e1a415342 100644
--- a/src/lib/netlist/devices/nld_74165.h
+++ b/src/lib/netlist/devices/nld_74165.h
@@ -1,28 +1,5 @@
// license:BSD-3-Clause
// copyright-holders:Ryan Holtz
-/*
- * nld_74165.h
- *
- * 74165: Parallel-Load 8-Bit Shift Register
- *
- * +--------------+
- * SH/LDQ |1 ++ 16| VCC
- * CLK |2 15| CLKINH
- * E |3 14| D
- * F |4 74165 13| C
- * G |5 12| B
- * H |6 11| A
- * QHQ |7 10| SER
- * GND |8 9| QH
- * +--------------+
- *
- * SH/LDQ: Shift / !Load
- * CLKINH: Clock Inhibit
- * SER: Serial In
- *
- * Naming convention attempts to follow NTE Electronics datasheet
- *
- */
#ifndef NLD_74165_H_
#define NLD_74165_H_
diff --git a/src/lib/netlist/devices/nld_74166.cpp b/src/lib/netlist/devices/nld_74166.cpp
index ebe911662bc..467132c9451 100644
--- a/src/lib/netlist/devices/nld_74166.cpp
+++ b/src/lib/netlist/devices/nld_74166.cpp
@@ -3,6 +3,25 @@
/*
* nld_74166.cpp
*
+ * 74166: Parallel-Load 8-Bit Shift Register
+ *
+ * +--------------+
+ * SER |1 ++ 16| VCC
+ * A |2 15| SH/LDQ
+ * B |3 14| H
+ * C |4 74166 13| QH
+ * D |5 12| G
+ * CLKINH |6 11| F
+ * CLK |7 10| E
+ * GND |8 9| CLRQ
+ * +--------------+
+ *
+ * SH/LDQ: Shift / !Load
+ * CLKINH: Clock Inhibit
+ * SER: Serial In
+ *
+ * Naming convention attempts to follow Texas Instruments datasheet
+ *
*/
#include "nld_74166.h"
diff --git a/src/lib/netlist/devices/nld_74166.h b/src/lib/netlist/devices/nld_74166.h
index fa001e4c6a2..8184c2610d3 100644
--- a/src/lib/netlist/devices/nld_74166.h
+++ b/src/lib/netlist/devices/nld_74166.h
@@ -1,28 +1,5 @@
// license:BSD-3-Clause
// copyright-holders:Ryan Holtz
-/*
- * nld_74166.h
- *
- * 74166: Parallel-Load 8-Bit Shift Register
- *
- * +--------------+
- * SER |1 ++ 16| VCC
- * A |2 15| SH/LDQ
- * B |3 14| H
- * C |4 74166 13| QH
- * D |5 12| G
- * CLKINH |6 11| F
- * CLK |7 10| E
- * GND |8 9| CLRQ
- * +--------------+
- *
- * SH/LDQ: Shift / !Load
- * CLKINH: Clock Inhibit
- * SER: Serial In
- *
- * Naming convention attempts to follow Texas Instruments datasheet
- *
- */
#ifndef NLD_74166_H_
#define NLD_74166_H_
diff --git a/src/lib/netlist/devices/nld_74174.cpp b/src/lib/netlist/devices/nld_74174.cpp
index 5f0e3c99ea9..cdc08aa8d8e 100644
--- a/src/lib/netlist/devices/nld_74174.cpp
+++ b/src/lib/netlist/devices/nld_74174.cpp
@@ -3,6 +3,34 @@
/*
* nld_74174.cpp
*
+ * DM74174: Hex D Flip-Flops with Clear
+ *
+ * +--------------+
+ * CLR |1 ++ 16| VCC
+ * Q1 |2 15| Q6
+ * D1 |3 14| D6
+ * D2 |4 74174 13| D5
+ * Q2 |5 12| Q5
+ * D3 |6 11| D4
+ * Q3 |7 10| Q4
+ * GND |8 9| CLK
+ * +--------------+
+ *
+ * +-----+-----+---++---+-----+
+ * | CLR | CLK | D || Q | QQ |
+ * +=====+=====+===++===+=====+
+ * | 0 | X | X || 0 | 1 |
+ * | 1 | R | 1 || 1 | 0 |
+ * | 1 | R | 0 || 0 | 1 |
+ * | 1 | 0 | X || Q0| Q0Q |
+ * +-----+-----+---++---+-----+
+ *
+ * Q0 The output logic level of Q before the indicated input conditions were established
+ *
+ * R: 0 -> 1
+ *
+ * Naming conventions follow National Semiconductor datasheet
+ *
*/
#include "nld_74174.h"
diff --git a/src/lib/netlist/devices/nld_74174.h b/src/lib/netlist/devices/nld_74174.h
index f5708fd2e90..7b41f818787 100644
--- a/src/lib/netlist/devices/nld_74174.h
+++ b/src/lib/netlist/devices/nld_74174.h
@@ -1,37 +1,5 @@
// license:GPL-2.0+
// copyright-holders:Couriersud
-/*
- * nld_74174.h
- *
- * DM74174: Hex D Flip-Flops with Clear
- *
- * +--------------+
- * CLR |1 ++ 16| VCC
- * Q1 |2 15| Q6
- * D1 |3 14| D6
- * D2 |4 74174 13| D5
- * Q2 |5 12| Q5
- * D3 |6 11| D4
- * Q3 |7 10| Q4
- * GND |8 9| CLK
- * +--------------+
- *
- * +-----+-----+---++---+-----+
- * | CLR | CLK | D || Q | QQ |
- * +=====+=====+===++===+=====+
- * | 0 | X | X || 0 | 1 |
- * | 1 | R | 1 || 1 | 0 |
- * | 1 | R | 0 || 0 | 1 |
- * | 1 | 0 | X || Q0| Q0Q |
- * +-----+-----+---++---+-----+
- *
- * Q0 The output logic level of Q before the indicated input conditions were established
- *
- * R: 0 -> 1
- *
- * Naming conventions follow National Semiconductor datasheet
- *
- */
#ifndef NLD_74174_H_
#define NLD_74174_H_
diff --git a/src/lib/netlist/devices/nld_74175.cpp b/src/lib/netlist/devices/nld_74175.cpp
index 5f1b483e5c3..4e30785de08 100644
--- a/src/lib/netlist/devices/nld_74175.cpp
+++ b/src/lib/netlist/devices/nld_74175.cpp
@@ -1,7 +1,35 @@
// license:GPL-2.0+
// copyright-holders:Couriersud
/*
- * nld_74175.c
+ * nld_74175.cpp
+ *
+ * DM74175: Quad D Flip-Flops with Clear
+ *
+ * +--------------+
+ * CLR |1 ++ 16| VCC
+ * Q1 |2 15| Q4
+ * Q1Q |3 14| Q4Q
+ * D1 |4 74175 13| D4
+ * D2 |5 12| D3
+ * Q2Q |6 11| Q3Q
+ * Q2 |7 10| Q3
+ * GND |8 9| CLK
+ * +--------------+
+ *
+ * +-----+-----+---++---+-----+
+ * | CLR | CLK | D || Q | QQ |
+ * +=====+=====+===++===+=====+
+ * | 0 | X | X || 0 | 1 |
+ * | 1 | R | 1 || 1 | 0 |
+ * | 1 | R | 0 || 0 | 1 |
+ * | 1 | 0 | X || Q0| Q0Q |
+ * +-----+-----+---++---+-----+
+ *
+ * Q0 The output logic level of Q before the indicated input conditions were established
+ *
+ * R: 0 -> 1
+ *
+ * Naming conventions follow National Semiconductor datasheet
*
*/
diff --git a/src/lib/netlist/devices/nld_74175.h b/src/lib/netlist/devices/nld_74175.h
index b29d4680813..0687df96947 100644
--- a/src/lib/netlist/devices/nld_74175.h
+++ b/src/lib/netlist/devices/nld_74175.h
@@ -1,37 +1,5 @@
// license:GPL-2.0+
// copyright-holders:Couriersud
-/*
- * nld_74175.h
- *
- * DM74175: Quad D Flip-Flops with Clear
- *
- * +--------------+
- * CLR |1 ++ 16| VCC
- * Q1 |2 15| Q4
- * Q1Q |3 14| Q4Q
- * D1 |4 74175 13| D4
- * D2 |5 12| D3
- * Q2Q |6 11| Q3Q
- * Q2 |7 10| Q3
- * GND |8 9| CLK
- * +--------------+
- *
- * +-----+-----+---++---+-----+
- * | CLR | CLK | D || Q | QQ |
- * +=====+=====+===++===+=====+
- * | 0 | X | X || 0 | 1 |
- * | 1 | R | 1 || 1 | 0 |
- * | 1 | R | 0 || 0 | 1 |
- * | 1 | 0 | X || Q0| Q0Q |
- * +-----+-----+---++---+-----+
- *
- * Q0 The output logic level of Q before the indicated input conditions were established
- *
- * R: 0 -> 1
- *
- * Naming conventions follow National Semiconductor datasheet
- *
- */
#ifndef NLD_74175_H_
#define NLD_74175_H_
diff --git a/src/lib/netlist/devices/nld_74192.cpp b/src/lib/netlist/devices/nld_74192.cpp
index f395e8e3df4..5e77e245f97 100644
--- a/src/lib/netlist/devices/nld_74192.cpp
+++ b/src/lib/netlist/devices/nld_74192.cpp
@@ -1,7 +1,28 @@
// license:GPL-2.0+
// copyright-holders:Couriersud
/*
- * nld_74192.c
+ * nld_74192.cpp
+ *
+ * DM74192: Synchronous 4-Bit Binary Counter with Dual Clock
+ * Decade counter
+ *
+ * FIXME: This should be merged with the 74193 which counts to 16
+ *
+ * +--------------+
+ * B |1 ++ 16| VCC
+ * QB |2 15| A
+ * QA |3 14| CLEAR
+ * CD |4 74192 13| BORROWQ
+ * CU |5 12| CARRYQ
+ * QC |6 11| LOADQ
+ * QD |7 10| C
+ * GND |8 9| D
+ * +--------------+
+ *
+ * CD: Count up
+ * CU: Count down
+ *
+ * Naming conventions follow National Semiconductor datasheet
*
*/
diff --git a/src/lib/netlist/devices/nld_74192.h b/src/lib/netlist/devices/nld_74192.h
index 81397f355ae..30e80ad28fa 100644
--- a/src/lib/netlist/devices/nld_74192.h
+++ b/src/lib/netlist/devices/nld_74192.h
@@ -1,30 +1,5 @@
// license:GPL-2.0+
// copyright-holders:Couriersud
-/*
- * nld_74192.h
- *
- * DM74192: Synchronous 4-Bit Binary Counter with Dual Clock
- * Decade counter
- *
- * FIXME: This should be merged with the 74193 which counts to 16
- *
- * +--------------+
- * B |1 ++ 16| VCC
- * QB |2 15| A
- * QA |3 14| CLEAR
- * CD |4 74192 13| BORROWQ
- * CU |5 12| CARRYQ
- * QC |6 11| LOADQ
- * QD |7 10| C
- * GND |8 9| D
- * +--------------+
- *
- * CD: Count up
- * CU: Count down
- *
- * Naming conventions follow National Semiconductor datasheet
- *
- */
#ifndef NLD_74192_H_
#define NLD_74192_H_
diff --git a/src/lib/netlist/devices/nld_74193.cpp b/src/lib/netlist/devices/nld_74193.cpp
index 38933a89a62..40ea170087b 100644
--- a/src/lib/netlist/devices/nld_74193.cpp
+++ b/src/lib/netlist/devices/nld_74193.cpp
@@ -1,7 +1,25 @@
// license:GPL-2.0+
// copyright-holders:Couriersud
/*
- * nld_74193.c
+ * nld_74193.cpp
+ *
+ * DM74193: Synchronous 4-Bit Binary Counter with Dual Clock
+ *
+ * +--------------+
+ * B |1 ++ 16| VCC
+ * QB |2 15| A
+ * QA |3 14| CLEAR
+ * CD |4 74193 13| BORROWQ
+ * CU |5 12| CARRYQ
+ * QC |6 11| LOADQ
+ * QD |7 10| C
+ * GND |8 9| D
+ * +--------------+
+ *
+ * CD: Count up
+ * CU: Count down
+ *
+ * Naming conventions follow National Semiconductor datasheet
*
*/
diff --git a/src/lib/netlist/devices/nld_74193.h b/src/lib/netlist/devices/nld_74193.h
index 493e6854266..5049f783016 100644
--- a/src/lib/netlist/devices/nld_74193.h
+++ b/src/lib/netlist/devices/nld_74193.h
@@ -1,27 +1,5 @@
// license:GPL-2.0+
// copyright-holders:Couriersud
-/*
- * nld_74193.h
- *
- * DM74193: Synchronous 4-Bit Binary Counter with Dual Clock
- *
- * +--------------+
- * B |1 ++ 16| VCC
- * QB |2 15| A
- * QA |3 14| CLEAR
- * CD |4 74193 13| BORROWQ
- * CU |5 12| CARRYQ
- * QC |6 11| LOADQ
- * QD |7 10| C
- * GND |8 9| D
- * +--------------+
- *
- * CD: Count up
- * CU: Count down
- *
- * Naming conventions follow National Semiconductor datasheet
- *
- */
#ifndef NLD_74193_H_
#define NLD_74193_H_
diff --git a/src/lib/netlist/devices/nld_74194.cpp b/src/lib/netlist/devices/nld_74194.cpp
index 6cd30ff648a..5eba4549a5e 100644
--- a/src/lib/netlist/devices/nld_74194.cpp
+++ b/src/lib/netlist/devices/nld_74194.cpp
@@ -3,8 +3,27 @@
/*
* nld_74194.cpp
*
+ * 74194: Parallel-Load 8-Bit Shift Register
+ *
+ * +--------------+
+ * CLRQ |1 ++ 16| VCC
+ * SRIN |2 15| QA
+ * A |3 14| QB
+ * B |4 74194 13| QC
+ * C |5 12| QD
+ * D |6 11| CLK
+ * SLIN |7 10| S1
+ * GND |8 9| S0
+ * +--------------+
+ *
+ * CLR: Clear
+ * SRIN: Shift Right Serial Input
+ * SLIN: Shift Left Serial Input
+ * CLK: Clock
+ *
*/
+
#include "nld_74194.h"
#include "netlist/nl_base.h"
diff --git a/src/lib/netlist/devices/nld_74194.h b/src/lib/netlist/devices/nld_74194.h
index 2432a6ece97..838c3c96406 100644
--- a/src/lib/netlist/devices/nld_74194.h
+++ b/src/lib/netlist/devices/nld_74194.h
@@ -1,28 +1,5 @@
// license:BSD-3-Clause
// copyright-holders:Ryan Holtz
-/*
- * nld_74194.h
- *
- * 74194: Parallel-Load 8-Bit Shift Register
- *
- * +--------------+
- * CLRQ |1 ++ 16| VCC
- * SRIN |2 15| QA
- * A |3 14| QB
- * B |4 74194 13| QC
- * C |5 12| QD
- * D |6 11| CLK
- * SLIN |7 10| S1
- * GND |8 9| S0
- * +--------------+
- *
- * CLR: Clear
- * SRIN: Shift Right Serial Input
- * SLIN: Shift Left Serial Input
- * CLK: Clock
- *
- */
-
#ifndef NLD_74194_H_
#define NLD_74194_H_
diff --git a/src/lib/netlist/devices/nld_74365.cpp b/src/lib/netlist/devices/nld_74365.cpp
index 46a13a4d086..4b9f7be9afa 100644
--- a/src/lib/netlist/devices/nld_74365.cpp
+++ b/src/lib/netlist/devices/nld_74365.cpp
@@ -3,6 +3,23 @@
/*
* nld_74365.cpp
*
+ * SN74365: Hex Bus Driver with 3-State Outputs
+ *
+ * +--------------+
+ * G1Q |1 ++ 16| VCC
+ * A1 |2 15| G2Q
+ * Y1 |3 14| A6
+ * A2 |4 74365 13| Y6
+ * Y2 |5 12| A5
+ * A3 |6 11| Y5
+ * Y3 |7 10| A4
+ * GND |8 9| Y4
+ * +--------------+
+ *
+ * Naming conventions follow Texas Instruments datasheet
+ *
+ * Note: Currently the netlist system does not support proper tristate output, so this
+ * is not a "real" bus driver, it simply outputs 0 if the chip is not enabled.
*/
#include "nld_74365.h"
diff --git a/src/lib/netlist/devices/nld_74365.h b/src/lib/netlist/devices/nld_74365.h
index 1aeeddaff8d..9fc55f52243 100644
--- a/src/lib/netlist/devices/nld_74365.h
+++ b/src/lib/netlist/devices/nld_74365.h
@@ -1,27 +1,5 @@
// license:BSD-3-Clause
// copyright-holders:Ryan Holtz
-/*
- * nld_74365.h
- *
- * SN74365: Hex Bus Driver with 3-State Outputs
- *
- * +--------------+
- * G1Q |1 ++ 16| VCC
- * A1 |2 15| G2Q
- * Y1 |3 14| A6
- * A2 |4 74365 13| Y6
- * Y2 |5 12| A5
- * A3 |6 11| Y5
- * Y3 |7 10| A4
- * GND |8 9| Y4
- * +--------------+
- *
- * Naming conventions follow Texas Instruments datasheet
- *
- * Note: Currently the netlist system does not support proper tristate output, so this
- * is not a "real" bus driver, it simply outputs 0 if the chip is not enabled.
- */
-
#ifndef NLD_74365_H_
#define NLD_74365_H_
diff --git a/src/lib/netlist/devices/nld_74377.cpp b/src/lib/netlist/devices/nld_74377.cpp
index 4f2e00f229a..8d5381ce92a 100644
--- a/src/lib/netlist/devices/nld_74377.cpp
+++ b/src/lib/netlist/devices/nld_74377.cpp
@@ -1,7 +1,50 @@
// license:GPL-2.0+
// copyright-holders:Couriersud
/*
- * nld_74377.c
+ * nld_74377.cpp
+ *
+ * DM74377: Octal D Flip-Flop With Enable
+ *
+ * +--------------+
+ * /E |1 ++ 20| VCC
+ * Q0 |2 19| Q7
+ * D0 |3 18| D7
+ * D1 |4 74377 17| D6
+ * Q1 |5 16| Q6
+ * Q2 |6 15| Q5
+ * D2 |7 14| D5
+ * D3 |8 13| D4
+ * Q3 |9 12| Q4
+ * GND |10 11| CP
+ * +--------------+
+ *
+ * DM74378: Hex D Flip-Flop With Enable
+ *
+ * +--------------+
+ * /E |1 ++ 16| VCC
+ * Q0 |2 15| Q5
+ * D0 |3 14| D5
+ * D1 |4 74378 13| D4
+ * Q1 |5 12| Q4
+ * D2 |6 11| D3
+ * Q2 |7 10| Q3
+ * GND |8 9| CP
+ * +--------------+
+ *
+ * DM74379: 4-bit D Flip-Flop With Enable
+ *
+ * +--------------+
+ * /E |1 ++ 16| VCC
+ * Q0 |2 15| Q3
+ * /Q0 |3 14| /Q3
+ * D0 |4 74379 13| D3
+ * D1 |5 12| D2
+ * /Q1 |6 11| /Q2
+ * Q1 |7 10| Q2
+ * GND |8 9| CP
+ * +--------------+
+ *
+ * Naming conventions follow Motorola datasheet
*
*/
diff --git a/src/lib/netlist/devices/nld_74377.h b/src/lib/netlist/devices/nld_74377.h
index 6f5a3aed14e..9b3d2b87210 100644
--- a/src/lib/netlist/devices/nld_74377.h
+++ b/src/lib/netlist/devices/nld_74377.h
@@ -1,52 +1,5 @@
// license:GPL-2.0+
// copyright-holders:Couriersud,Aaron Giles
-/*
- * nld_74377.h
- *
- * DM74377: Octal D Flip-Flop With Enable
- *
- * +--------------+
- * /E |1 ++ 20| VCC
- * Q0 |2 19| Q7
- * D0 |3 18| D7
- * D1 |4 74377 17| D6
- * Q1 |5 16| Q6
- * Q2 |6 15| Q5
- * D2 |7 14| D5
- * D3 |8 13| D4
- * Q3 |9 12| Q4
- * GND |10 11| CP
- * +--------------+
- *
- * DM74378: Hex D Flip-Flop With Enable
- *
- * +--------------+
- * /E |1 ++ 16| VCC
- * Q0 |2 15| Q5
- * D0 |3 14| D5
- * D1 |4 74378 13| D4
- * Q1 |5 12| Q4
- * D2 |6 11| D3
- * Q2 |7 10| Q3
- * GND |8 9| CP
- * +--------------+
- *
- * DM74379: 4-bit D Flip-Flop With Enable
- *
- * +--------------+
- * /E |1 ++ 16| VCC
- * Q0 |2 15| Q3
- * /Q0 |3 14| /Q3
- * D0 |4 74379 13| D3
- * D1 |5 12| D2
- * /Q1 |6 11| /Q2
- * Q1 |7 10| Q2
- * GND |8 9| CP
- * +--------------+
- *
- * Naming conventions follow Motorola datasheet
- *
- */
#ifndef NLD_74377_H_
#define NLD_74377_H_
diff --git a/src/lib/netlist/devices/nld_74393.cpp b/src/lib/netlist/devices/nld_74393.cpp
index 377f7298ebe..38e42475eda 100644
--- a/src/lib/netlist/devices/nld_74393.cpp
+++ b/src/lib/netlist/devices/nld_74393.cpp
@@ -1,7 +1,21 @@
// license:GPL-2.0+
// copyright-holders:Couriersud
/*
- * nld_74393.c
+ * nld_74393.cpp
+ *
+ * DM74393: Dual 4-Stage Binary Counter
+ *
+ * +--------------+
+ * /CP |1 ++ 14| VCC
+ * MR |2 13| /CP
+ * Q0 |3 12| MR
+ * Q1 |4 74393 11| Q0
+ * Q2 |5 10| Q1
+ * Q3 |6 9| Q2
+ * GND |7 8| Q3
+ * +--------------+
+ *
+ * Naming conventions follow Motorola datasheet
*
*/
diff --git a/src/lib/netlist/devices/nld_74393.h b/src/lib/netlist/devices/nld_74393.h
index a49b78ab1b2..cf4d3b82932 100644
--- a/src/lib/netlist/devices/nld_74393.h
+++ b/src/lib/netlist/devices/nld_74393.h
@@ -1,23 +1,5 @@
// license:GPL-2.0+
// copyright-holders:Couriersud
-/*
- * nld_74393.h
- *
- * DM74393: Dual 4-Stage Binary Counter
- *
- * +--------------+
- * /CP |1 ++ 14| VCC
- * MR |2 13| /CP
- * Q0 |3 12| MR
- * Q1 |4 74393 11| Q0
- * Q2 |5 10| Q1
- * Q3 |6 9| Q2
- * GND |7 8| Q3
- * +--------------+
- *
- * Naming conventions follow Motorola datasheet
- *
- */
#ifndef NLD_74393_H_
#define NLD_74393_H_