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author Nathan Woods <npwoods@mess.org>2014-04-12 16:06:35 +0000
committer Nathan Woods <npwoods@mess.org>2014-04-12 16:06:35 +0000
commite0aa3725a580ca2aff883224c10d9f95bbad0800 (patch)
treee98fc85e4124a98d4dfd2e5370613c17a7d78703
parent0be111068bea5b647dfbe807ec55187bf5c28db7 (diff)
parent5e378738aafb738373edf6014996482aa7ee6a3c (diff)
Merge branch 'master' of ssh://mess.org/mame into new_menus
-rw-r--r--.gitattributes9
-rw-r--r--src/emu/bus/bus.mak11
-rw-r--r--src/emu/bus/oricext/jasmin.c173
-rw-r--r--src/emu/bus/oricext/jasmin.h41
-rw-r--r--src/emu/bus/oricext/microdisc.c151
-rw-r--r--src/emu/bus/oricext/microdisc.h52
-rw-r--r--src/emu/bus/oricext/oricext.c76
-rw-r--r--src/emu/bus/oricext/oricext.h63
-rw-r--r--src/emu/cpu/cpu.mak12
-rw-r--r--src/emu/cpu/sh2/sh2.c2522
-rw-r--r--src/emu/cpu/sh2/sh2.h449
-rw-r--r--src/emu/cpu/sh2/sh2comn.c820
-rw-r--r--src/emu/cpu/sh2/sh2comn.h182
-rw-r--r--src/emu/cpu/sh2/sh2drc.c1730
-rw-r--r--src/emu/cpu/sh2/sh2fe.c9
-rw-r--r--src/emu/imagedev/floppy.c3
-rw-r--r--src/emu/machine/6522via.c10
-rw-r--r--src/emu/machine/6522via.h2
-rw-r--r--src/emu/machine/saturn.c8
-rw-r--r--src/emu/machine/wd_fdc.c13
-rw-r--r--src/lib/formats/mfi_dsk.c2
-rw-r--r--src/lib/formats/oric_dsk.c348
-rw-r--r--src/lib/formats/oric_dsk.h18
-rw-r--r--src/mame/drivers/coolridr.c8
-rw-r--r--src/mame/drivers/cps3.c2
-rw-r--r--src/mame/drivers/deco_mlc.c6
-rw-r--r--src/mame/drivers/psikyosh.c20
-rw-r--r--src/mame/drivers/stv.c178
-rw-r--r--src/mame/drivers/suprnova.c4
-rw-r--r--src/mame/includes/cps3.h3
-rw-r--r--src/mame/includes/deco_mlc.h4
-rw-r--r--src/mame/includes/psikyosh.h4
-rw-r--r--src/mame/includes/stv.h5
-rw-r--r--src/mame/includes/suprnova.h6
-rw-r--r--src/mess/drivers/oric.c1129
-rw-r--r--src/mess/drivers/saturn.c4
-rw-r--r--src/mess/includes/oric.h204
-rw-r--r--src/mess/machine/mega32x.c12
-rw-r--r--src/mess/machine/mega32x.h4
-rw-r--r--src/mess/machine/oric.c1357
-rw-r--r--src/mess/mess.mak5
-rw-r--r--src/mess/tools/floptool/main.c8
-rw-r--r--src/mess/video/oric.c304
43 files changed, 4384 insertions, 5587 deletions
diff --git a/.gitattributes b/.gitattributes
index 13ad0856f58..d24e70ec249 100644
--- a/.gitattributes
+++ b/.gitattributes
@@ -1088,6 +1088,12 @@ src/emu/bus/nubus/pds30_procolor816.c svneol=native#text/plain
src/emu/bus/nubus/pds30_procolor816.h svneol=native#text/plain
src/emu/bus/nubus/pds30_sigmalview.c svneol=native#text/plain
src/emu/bus/nubus/pds30_sigmalview.h svneol=native#text/plain
+src/emu/bus/oricext/jasmin.c svneol=native#text/plain
+src/emu/bus/oricext/jasmin.h svneol=native#text/plain
+src/emu/bus/oricext/microdisc.c svneol=native#text/plain
+src/emu/bus/oricext/microdisc.h svneol=native#text/plain
+src/emu/bus/oricext/oricext.c svneol=native#text/plain
+src/emu/bus/oricext/oricext.h svneol=native#text/plain
src/emu/bus/pc_joy/pc_joy.c svneol=native#text/plain
src/emu/bus/pc_joy/pc_joy.h svneol=native#text/plain
src/emu/bus/pc_joy/pc_joy_sw.c svneol=native#text/plain
@@ -8202,7 +8208,6 @@ src/mess/includes/next.h svneol=native#text/plain
src/mess/includes/ob68k1a.h svneol=native#text/plain
src/mess/includes/ondra.h svneol=native#text/plain
src/mess/includes/orao.h svneol=native#text/plain
-src/mess/includes/oric.h svneol=native#text/plain
src/mess/includes/orion.h svneol=native#text/plain
src/mess/includes/osborne1.h svneol=native#text/plain
src/mess/includes/osi.h svneol=native#text/plain
@@ -8557,7 +8562,6 @@ src/mess/machine/nextmo.c svneol=native#text/plain
src/mess/machine/nextmo.h svneol=native#text/plain
src/mess/machine/ondra.c svneol=native#text/plain
src/mess/machine/orao.c svneol=native#text/plain
-src/mess/machine/oric.c svneol=native#text/plain
src/mess/machine/orion.c svneol=native#text/plain
src/mess/machine/osborne1.c svneol=native#text/plain
src/mess/machine/p2000t.c svneol=native#text/plain
@@ -8829,7 +8833,6 @@ src/mess/video/nick.c svneol=native#text/plain
src/mess/video/nick.h svneol=native#text/plain
src/mess/video/ondra.c svneol=native#text/plain
src/mess/video/orao.c svneol=native#text/plain
-src/mess/video/oric.c svneol=native#text/plain
src/mess/video/orion.c svneol=native#text/plain
src/mess/video/osi.c svneol=native#text/plain
src/mess/video/p2000m.c svneol=native#text/plain
diff --git a/src/emu/bus/bus.mak b/src/emu/bus/bus.mak
index 70cefb05ddb..5fb3201e51a 100644
--- a/src/emu/bus/bus.mak
+++ b/src/emu/bus/bus.mak
@@ -1047,3 +1047,14 @@ OBJDIRS += $(BUSOBJ)/macpds
BUSOBJS += $(BUSOBJ)/macpds/macpds.o
BUSOBJS += $(BUSOBJ)/macpds/pds_tpdfpd.o
endif
+
+#-------------------------------------------------
+#
+#@src/emu/bus/oricext/oricext.h,BUSES += ORICEXT
+#-------------------------------------------------
+ifneq ($(filter ORICEXT,$(BUSES)),)
+OBJDIRS += $(BUSOBJ)/oricext
+BUSOBJS += $(BUSOBJ)/oricext/oricext.o
+BUSOBJS += $(BUSOBJ)/oricext/jasmin.o
+BUSOBJS += $(BUSOBJ)/oricext/microdisc.o
+endif
diff --git a/src/emu/bus/oricext/jasmin.c b/src/emu/bus/oricext/jasmin.c
new file mode 100644
index 00000000000..0435d30ffcb
--- /dev/null
+++ b/src/emu/bus/oricext/jasmin.c
@@ -0,0 +1,173 @@
+#include "jasmin.h"
+#include "formats/oric_dsk.h"
+
+const device_type JASMIN = &device_creator<jasmin_device>;
+
+ROM_START( jasmin )
+ ROM_REGION( 0x800, "jasmin", 0 )
+ ROM_LOAD("jasmin.rom", 0, 0x800, CRC(37220e89) SHA1(70e59b8abd67092f050462abc6cb5271e4c15f01) )
+ROM_END
+
+FLOPPY_FORMATS_MEMBER( jasmin_device::floppy_formats )
+ FLOPPY_ORIC_DSK_FORMAT
+FLOPPY_FORMATS_END
+
+static SLOT_INTERFACE_START( jasmin_floppies )
+ SLOT_INTERFACE( "3dsdd", FLOPPY_3_DSDD )
+SLOT_INTERFACE_END
+
+static MACHINE_CONFIG_FRAGMENT( jasmin )
+ MCFG_WD1770x_ADD("fdc", XTAL_8MHz)
+ MCFG_WD_FDC_DRQ_CALLBACK(WRITELINE(oricext_device, irq_w))
+
+ MCFG_FLOPPY_DRIVE_ADD("fdc:0", jasmin_floppies, "3dsdd", jasmin_device::floppy_formats)
+ MCFG_FLOPPY_DRIVE_ADD("fdc:1", jasmin_floppies, NULL, jasmin_device::floppy_formats)
+ MCFG_FLOPPY_DRIVE_ADD("fdc:2", jasmin_floppies, NULL, jasmin_device::floppy_formats)
+ MCFG_FLOPPY_DRIVE_ADD("fdc:3", jasmin_floppies, NULL, jasmin_device::floppy_formats)
+MACHINE_CONFIG_END
+
+INPUT_PORTS_START( jasmin )
+ PORT_START("JASMIN")
+ PORT_BIT( 0x01, IP_ACTIVE_HIGH, IPT_KEYBOARD ) PORT_NAME("Boot") PORT_CODE(KEYCODE_F1) PORT_CHAR(UCHAR_MAMEKEY(F1)) PORT_CHANGED_MEMBER(DEVICE_SELF, jasmin_device, boot_pressed, 0)
+INPUT_PORTS_END
+
+DEVICE_ADDRESS_MAP_START(map, 8, jasmin_device)
+ AM_RANGE(0x3f4, 0x3f7) AM_DEVREADWRITE("fdc", wd1770_t, read, write)
+ AM_RANGE(0x3f8, 0x3f8) AM_WRITE(side_sel_w)
+ AM_RANGE(0x3f9, 0x3f9) AM_WRITE(fdc_reset_w)
+ AM_RANGE(0x3fa, 0x3fa) AM_WRITE(ram_access_w)
+ AM_RANGE(0x3fb, 0x3fb) AM_WRITE(rom_access_w)
+ AM_RANGE(0x3fc, 0x3ff) AM_WRITE(select_w)
+ADDRESS_MAP_END
+
+jasmin_device::jasmin_device(const machine_config &mconfig, const char *tag, device_t *owner, UINT32 clock) :
+ oricext_device(mconfig, JASMIN, "Jasmin floppy drive interface", tag, owner, clock, "jasmin", __FILE__),
+ fdc(*this, "fdc")
+{
+}
+
+jasmin_device::~jasmin_device()
+{
+}
+
+void jasmin_device::device_start()
+{
+ oricext_device::device_start();
+ astring tempstring;
+ jasmin_rom = device().machine().root_device().memregion(this->subtag(tempstring, "jasmin"))->base();
+ cpu->space(AS_PROGRAM).install_device(0x0000, 0xffff, *this, &jasmin_device::map);
+
+ for(int i=0; i<4; i++) {
+ char name[32];
+ sprintf(name, "fdc:%d", i);
+ floppies[i] = subdevice<floppy_connector>(name)->get_device();
+ }
+}
+
+void jasmin_device::device_reset()
+{
+ side_sel = fdc_reset = ram_access = rom_access = false;
+ select[0] = select[1] = select[2] = select[3] = false;
+ remap();
+ cur_floppy = NULL;
+ fdc->set_floppy(NULL);
+}
+
+const rom_entry *jasmin_device::device_rom_region() const
+{
+ return ROM_NAME( jasmin );
+}
+
+machine_config_constructor jasmin_device::device_mconfig_additions() const
+{
+ return MACHINE_CONFIG_NAME( jasmin );
+}
+
+ioport_constructor jasmin_device::device_input_ports() const
+{
+ return INPUT_PORTS_NAME( jasmin );
+}
+
+void jasmin_device::remap()
+{
+ if(rom_access) {
+ if(ram_access) {
+ bank_c000_r->set_base(ram+0xc000);
+ bank_e000_r->set_base(ram+0xe000);
+ bank_f800_r->set_base(jasmin_rom);
+ bank_c000_w->set_base(ram+0xc000);
+ bank_e000_w->set_base(ram+0xe000);
+ bank_f800_w->set_base(junk_write);
+ } else {
+ bank_c000_r->set_base(junk_read);
+ bank_e000_r->set_base(junk_read);
+ bank_f800_r->set_base(jasmin_rom);
+ bank_c000_w->set_base(junk_write);
+ bank_e000_w->set_base(junk_write);
+ bank_f800_w->set_base(junk_write);
+ }
+ } else {
+ if(ram_access) {
+ bank_c000_r->set_base(ram+0xc000);
+ bank_e000_r->set_base(ram+0xe000);
+ bank_f800_r->set_base(ram+0xf800);
+ bank_c000_w->set_base(ram+0xc000);
+ bank_e000_w->set_base(ram+0xe000);
+ bank_f800_w->set_base(ram+0xf800);
+ } else {
+ bank_c000_r->set_base(rom+0x0000);
+ bank_e000_r->set_base(rom+0x2000);
+ bank_f800_r->set_base(rom+0x3800);
+ bank_c000_w->set_base(junk_write);
+ bank_e000_w->set_base(junk_write);
+ bank_f800_w->set_base(junk_write);
+ }
+ }
+}
+
+INPUT_CHANGED_MEMBER(jasmin_device::boot_pressed)
+{
+ if(newval) {
+ rom_access = true;
+ remap();
+ cpu->reset();
+ }
+}
+
+WRITE8_MEMBER(jasmin_device::side_sel_w)
+{
+ side_sel = data & 1;
+ if(cur_floppy)
+ cur_floppy->ss_w(side_sel);
+}
+
+WRITE8_MEMBER(jasmin_device::fdc_reset_w)
+{
+ if((data & 1) != fdc_reset)
+ fdc->soft_reset();
+ fdc_reset = data & 1;
+}
+
+WRITE8_MEMBER(jasmin_device::ram_access_w)
+{
+ ram_access = data & 1;
+ remap();
+}
+
+WRITE8_MEMBER(jasmin_device::rom_access_w)
+{
+ rom_access = data & 1;
+ remap();
+}
+
+WRITE8_MEMBER(jasmin_device::select_w)
+{
+ select[offset] = data & 1;
+ cur_floppy = NULL;
+ for(int i=0; i != 4; i++)
+ if(select[i]) {
+ cur_floppy = floppies[i];
+ break;
+ }
+ fdc->set_floppy(cur_floppy);
+}
diff --git a/src/emu/bus/oricext/jasmin.h b/src/emu/bus/oricext/jasmin.h
new file mode 100644
index 00000000000..6815d652daf
--- /dev/null
+++ b/src/emu/bus/oricext/jasmin.h
@@ -0,0 +1,41 @@
+#ifndef __JASMIN_H__
+#define __JASMIN_H__
+
+#include "oricext.h"
+#include "imagedev/floppy.h"
+#include "machine/wd_fdc.h"
+
+extern const device_type JASMIN;
+
+class jasmin_device : public oricext_device
+{
+public:
+ jasmin_device(const machine_config &mconfig, const char *tag, device_t *owner, UINT32 clock);
+ virtual ~jasmin_device();
+
+ DECLARE_FLOPPY_FORMATS(floppy_formats);
+ DECLARE_ADDRESS_MAP(map, 8);
+ DECLARE_INPUT_CHANGED_MEMBER(boot_pressed);
+ DECLARE_WRITE8_MEMBER(side_sel_w);
+ DECLARE_WRITE8_MEMBER(fdc_reset_w);
+ DECLARE_WRITE8_MEMBER(ram_access_w);
+ DECLARE_WRITE8_MEMBER(rom_access_w);
+ DECLARE_WRITE8_MEMBER(select_w);
+
+protected:
+ required_device<wd1770_t> fdc;
+
+ bool side_sel, fdc_reset, ram_access, rom_access, select[4];
+ UINT8 *jasmin_rom;
+ floppy_image_device *cur_floppy, *floppies[4];
+
+ virtual void device_start();
+ virtual void device_reset();
+ const rom_entry *device_rom_region() const;
+ machine_config_constructor device_mconfig_additions() const;
+ virtual ioport_constructor device_input_ports() const;
+
+ void remap();
+};
+
+#endif
diff --git a/src/emu/bus/oricext/microdisc.c b/src/emu/bus/oricext/microdisc.c
new file mode 100644
index 00000000000..0351c1be0e0
--- /dev/null
+++ b/src/emu/bus/oricext/microdisc.c
@@ -0,0 +1,151 @@
+#include "microdisc.h"
+#include "formats/oric_dsk.h"
+
+const device_type MICRODISC = &device_creator<microdisc_device>;
+
+ROM_START( microdisc )
+ ROM_REGION( 0x2000, "microdisc", 0 )
+ ROM_LOAD ("microdis.rom", 0, 0x02000, CRC(a9664a9c) SHA1(0d2ef6e67322f48f4b7e08d8bbe68827e2074561) )
+ROM_END
+
+FLOPPY_FORMATS_MEMBER( microdisc_device::floppy_formats )
+ FLOPPY_ORIC_DSK_FORMAT
+FLOPPY_FORMATS_END
+
+static SLOT_INTERFACE_START( microdisc_floppies )
+ SLOT_INTERFACE( "3dsdd", FLOPPY_3_DSDD )
+SLOT_INTERFACE_END
+
+static MACHINE_CONFIG_FRAGMENT( microdisc )
+ MCFG_FD1793x_ADD("fdc", XTAL_8MHz/8)
+ MCFG_WD_FDC_INTRQ_CALLBACK(WRITELINE(microdisc_device, fdc_irq_w))
+ MCFG_WD_FDC_DRQ_CALLBACK(WRITELINE(microdisc_device, fdc_drq_w))
+ MCFG_WD_FDC_HLD_CALLBACK(WRITELINE(microdisc_device, fdc_hld_w))
+ MCFG_WD_FDC_FORCE_READY
+
+ MCFG_FLOPPY_DRIVE_ADD("fdc:0", microdisc_floppies, "3dsdd", microdisc_device::floppy_formats)
+ MCFG_FLOPPY_DRIVE_ADD("fdc:1", microdisc_floppies, NULL, microdisc_device::floppy_formats)
+ MCFG_FLOPPY_DRIVE_ADD("fdc:2", microdisc_floppies, NULL, microdisc_device::floppy_formats)
+ MCFG_FLOPPY_DRIVE_ADD("fdc:3", microdisc_floppies, NULL, microdisc_device::floppy_formats)
+MACHINE_CONFIG_END
+
+DEVICE_ADDRESS_MAP_START(map, 8, microdisc_device)
+ AM_RANGE(0x310, 0x313) AM_DEVREADWRITE("fdc", fd1793_t, read, write)
+ AM_RANGE(0x314, 0x314) AM_READWRITE(port_314_r, port_314_w)
+ AM_RANGE(0x318, 0x318) AM_READ(port_318_r)
+ADDRESS_MAP_END
+
+microdisc_device::microdisc_device(const machine_config &mconfig, const char *tag, device_t *owner, UINT32 clock) :
+ oricext_device(mconfig, MICRODISC, "Microdisc floppy drive interface", tag, owner, clock, "microdisc", __FILE__),
+ fdc(*this, "fdc")
+{
+}
+
+microdisc_device::~microdisc_device()
+{
+}
+
+void microdisc_device::device_start()
+{
+ oricext_device::device_start();
+ astring tempstring;
+ microdisc_rom = device().machine().root_device().memregion(this->subtag(tempstring, "microdisc"))->base();
+ cpu->space(AS_PROGRAM).install_device(0x0000, 0xffff, *this, &microdisc_device::map);
+
+ for(int i=0; i<4; i++) {
+ char name[32];
+ sprintf(name, "fdc:%d", i);
+ floppies[i] = subdevice<floppy_connector>(name)->get_device();
+ }
+ intrq_state = drq_state = hld_state = false;
+}
+
+void microdisc_device::device_reset()
+{
+ port_314 = 0x00;
+ irq_w(false);
+ remap();
+ fdc->set_floppy(floppies[0]);
+
+ // The bootstrap checksums part of the high ram and if the sum is
+ // 0 it goes wrong.
+ ram[0xe000] = 0x42;
+}
+
+const rom_entry *microdisc_device::device_rom_region() const
+{
+ return ROM_NAME( microdisc );
+}
+
+machine_config_constructor microdisc_device::device_mconfig_additions() const
+{
+ return MACHINE_CONFIG_NAME( microdisc );
+}
+
+void microdisc_device::remap()
+{
+ if(port_314 & P_ROMDIS) {
+ bank_c000_r->set_base(rom+0x0000);
+ bank_e000_r->set_base(rom+0x2000);
+ bank_f800_r->set_base(rom+0x3800);
+ bank_c000_w->set_base(junk_write);
+ bank_e000_w->set_base(junk_write);
+ bank_f800_w->set_base(junk_write);
+ } else {
+ bank_c000_r->set_base(ram+0xc000);
+ bank_c000_w->set_base(ram+0xc000);
+ if(port_314 & P_EPROM) {
+ bank_e000_r->set_base(ram+0xe000);
+ bank_f800_r->set_base(ram+0xf800);
+ bank_e000_w->set_base(ram+0xe000);
+ bank_f800_w->set_base(ram+0xf800);
+ } else {
+ bank_e000_r->set_base(microdisc_rom+0x0000);
+ bank_f800_r->set_base(microdisc_rom+0x1800);
+ bank_e000_w->set_base(junk_write);
+ bank_f800_w->set_base(junk_write);
+ }
+ }
+}
+
+WRITE8_MEMBER(microdisc_device::port_314_w)
+{
+ port_314 = data;
+ remap();
+ floppy_image_device *floppy = floppies[(port_314 >> 5) & 3];
+ fdc->set_floppy(floppy);
+ fdc->dden_w(port_314 & P_DDEN);
+ if(floppy) {
+ floppy->ss_w(port_314 & P_SS ? 1 : 0);
+ floppy->mon_w(0);
+ }
+ irq_w(intrq_state && (port_314 & P_IRQEN));
+}
+
+READ8_MEMBER(microdisc_device::port_314_r)
+{
+ return (intrq_state && (port_314 & P_IRQEN)) ? 0x7f : 0xff;
+}
+
+READ8_MEMBER(microdisc_device::port_318_r)
+{
+ return drq_state ? 0x7f : 0xff;
+}
+
+WRITE_LINE_MEMBER(microdisc_device::fdc_irq_w)
+{
+ intrq_state = state;
+ irq_w(intrq_state && (port_314 & P_IRQEN));
+}
+
+WRITE_LINE_MEMBER(microdisc_device::fdc_drq_w)
+{
+ drq_state = state;
+}
+
+WRITE_LINE_MEMBER(microdisc_device::fdc_hld_w)
+{
+ logerror("hld %d\n", state);
+ hld_state = state;
+ floppies[(port_314 >> 5) & 3]->mon_w(!hld_state);
+}
diff --git a/src/emu/bus/oricext/microdisc.h b/src/emu/bus/oricext/microdisc.h
new file mode 100644
index 00000000000..fb7a6fd68b5
--- /dev/null
+++ b/src/emu/bus/oricext/microdisc.h
@@ -0,0 +1,52 @@
+#ifndef __MICRODISC_H__
+#define __MICRODISC_H__
+
+#include "oricext.h"
+#include "imagedev/floppy.h"
+#include "machine/wd_fdc.h"
+
+extern const device_type MICRODISC;
+
+class microdisc_device : public oricext_device
+{
+public:
+ microdisc_device(const machine_config &mconfig, const char *tag, device_t *owner, UINT32 clock);
+ virtual ~microdisc_device();
+
+ DECLARE_FLOPPY_FORMATS(floppy_formats);
+ DECLARE_ADDRESS_MAP(map, 8);
+ DECLARE_WRITE8_MEMBER(port_314_w);
+ DECLARE_READ8_MEMBER(port_314_r);
+ DECLARE_READ8_MEMBER(port_318_r);
+
+ DECLARE_WRITE_LINE_MEMBER(fdc_irq_w);
+ DECLARE_WRITE_LINE_MEMBER(fdc_drq_w);
+ DECLARE_WRITE_LINE_MEMBER(fdc_hld_w);
+
+protected:
+ enum {
+ P_IRQEN = 0x01,
+ P_ROMDIS = 0x02,
+ P_DDS = 0x04,
+ P_DDEN = 0x08,
+ P_SS = 0x10,
+ P_DRIVE = 0x60,
+ P_EPROM = 0x80
+ };
+
+ required_device<fd1793_t> fdc;
+
+ UINT8 *microdisc_rom;
+ floppy_image_device *floppies[4];
+ UINT8 port_314;
+ bool intrq_state, drq_state, hld_state;
+
+ virtual void device_start();
+ virtual void device_reset();
+ const rom_entry *device_rom_region() const;
+ machine_config_constructor device_mconfig_additions() const;
+
+ void remap();
+};
+
+#endif
diff --git a/src/emu/bus/oricext/oricext.c b/src/emu/bus/oricext/oricext.c
new file mode 100644
index 00000000000..fa6471d59f2
--- /dev/null
+++ b/src/emu/bus/oricext/oricext.c
@@ -0,0 +1,76 @@
+#include "oricext.h"
+#include "jasmin.h"
+#include "microdisc.h"
+
+const device_type ORICEXT_CONNECTOR = &device_creator<oricext_connector>;
+
+oricext_connector::oricext_connector(const machine_config &mconfig, const char *tag, device_t *owner, UINT32 clock) :
+ device_t(mconfig, ORICEXT_CONNECTOR, "ORIC extension connector", tag, owner, clock, "oricext_connector", __FILE__),
+ device_slot_interface(mconfig, *this),
+ irq_handler(*this)
+{
+}
+
+oricext_connector::~oricext_connector()
+{
+}
+
+void oricext_connector::set_cputag(const char *tag)
+{
+ cputag = tag;
+}
+
+void oricext_connector::device_start()
+{
+ irq_handler.resolve_safe();
+}
+
+void oricext_connector::irq_w(int state)
+{
+ irq_handler(state);
+}
+
+void oricext_connector::device_config_complete()
+{
+ oricext_device *dev = dynamic_cast<oricext_device *>(get_card_device());
+ if(dev)
+ dev->set_cputag(cputag);
+}
+
+oricext_device::oricext_device(const machine_config &mconfig, device_type type, const char *name, const char *tag, device_t *owner, UINT32 clock, const char *shortname, const char *source) :
+ device_t(mconfig, type, name, tag, owner, clock, shortname, source),
+ device_slot_card_interface(mconfig, *this)
+{
+}
+
+void oricext_device::set_cputag(const char *tag)
+{
+ cputag = tag;
+}
+
+void oricext_device::device_start()
+{
+ cpu = machine().device<m6502_device>(cputag);
+ connector = downcast<oricext_connector *>(owner());
+ bank_c000_r = membank(":bank_c000_r");
+ bank_e000_r = membank(":bank_e000_r");
+ bank_f800_r = membank(":bank_f800_r");
+ bank_c000_w = membank(":bank_c000_w");
+ bank_e000_w = membank(":bank_e000_w");
+ bank_f800_w = membank(":bank_f800_w");
+ rom = (UINT8 *)machine().root_device().memregion(cputag)->base();
+ ram = (UINT8 *)memshare(":ram")->ptr();
+
+ memset(junk_read, 0xff, sizeof(junk_read));
+ memset(junk_write, 0x00, sizeof(junk_write));
+}
+
+WRITE_LINE_MEMBER(oricext_device::irq_w)
+{
+ connector->irq_w(state);
+}
+
+SLOT_INTERFACE_START(oricext_intf)
+ SLOT_INTERFACE("jasmin", JASMIN)
+ SLOT_INTERFACE("microdisc", MICRODISC)
+SLOT_INTERFACE_END
diff --git a/src/emu/bus/oricext/oricext.h b/src/emu/bus/oricext/oricext.h
new file mode 100644
index 00000000000..2a5f2134a60
--- /dev/null
+++ b/src/emu/bus/oricext/oricext.h
@@ -0,0 +1,63 @@
+/***************************************************************************
+
+ oric.h - Oric 1/Atmos extension port
+
+***************************************************************************/
+
+#ifndef __ORICEXT_H__
+#define __ORICEXT_H__
+
+#include "emu.h"
+#include "cpu/m6502/m6502.h"
+
+#define MCFG_ORICEXT_ADD(_tag, _slot_intf, _def_slot, _cputag, _irq) \
+ MCFG_DEVICE_ADD(_tag, ORICEXT_CONNECTOR, 0) \
+ MCFG_DEVICE_SLOT_INTERFACE(_slot_intf, _def_slot, false) \
+ downcast<oricext_connector *>(device)->set_cputag(_cputag); \
+ devcb = &oricext_connector::set_irq_handler(*device, DEVCB2_##_irq);
+
+
+class oricext_device;
+
+class oricext_connector: public device_t,
+ public device_slot_interface
+{
+public:
+ oricext_connector(const machine_config &mconfig, const char *tag, device_t *owner, UINT32 clock);
+ virtual ~oricext_connector();
+
+ void set_cputag(const char *tag);
+ template<class _Object> static devcb2_base &set_irq_handler(device_t &device, _Object object) { return downcast<oricext_connector &>(device).irq_handler.set_callback(object); }
+ void irq_w(int state);
+
+protected:
+ devcb2_write_line irq_handler;
+ const char *cputag;
+ virtual void device_start();
+ virtual void device_config_complete();
+};
+
+class oricext_device : public device_t,
+ public device_slot_card_interface
+{
+public:
+ oricext_device(const machine_config &mconfig, device_type type, const char *name, const char *tag, device_t *owner, UINT32 clock, const char *shortname, const char *source);
+
+ void set_cputag(const char *tag);
+ DECLARE_WRITE_LINE_MEMBER(irq_w);
+
+protected:
+ const char *cputag;
+ m6502_device *cpu;
+ oricext_connector *connector;
+ memory_bank *bank_c000_r, *bank_e000_r, *bank_f800_r, *bank_c000_w, *bank_e000_w, *bank_f800_w;
+ UINT8 *rom, *ram;
+ UINT8 junk_read[8192], junk_write[8192];
+
+ virtual void device_start();
+};
+
+extern const device_type ORICEXT_CONNECTOR;
+SLOT_INTERFACE_EXTERN( oricext_intf );
+
+#endif /* __ORICEXT_H__ */
diff --git a/src/emu/cpu/cpu.mak b/src/emu/cpu/cpu.mak
index 227682e1d84..52ec3e78b24 100644
--- a/src/emu/cpu/cpu.mak
+++ b/src/emu/cpu/cpu.mak
@@ -685,20 +685,14 @@ $(CPUOBJ)/hcd62121/hcd62121.o: $(CPUSRC)/hcd62121/hcd62121.c \
ifneq ($(filter SH2,$(CPUS)),)
OBJDIRS += $(CPUOBJ)/sh2
-CPUOBJS += $(CPUOBJ)/sh2/sh2.o $(CPUOBJ)/sh2/sh2comn.o $(CPUOBJ)/sh2/sh2drc.o $(CPUOBJ)/sh2/sh2fe.o $(DRCOBJ)
+CPUOBJS += $(CPUOBJ)/sh2/sh2.o $(CPUOBJ)/sh2/sh2fe.o $(DRCOBJ)
DASMOBJS += $(CPUOBJ)/sh2/sh2dasm.o
endif
$(CPUOBJ)/sh2/sh2.o: $(CPUSRC)/sh2/sh2.c \
$(CPUSRC)/sh2/sh2.h \
- $(CPUSRC)/sh2/sh2comn.h
-
-$(CPUOBJ)/sh2/sh2comn.o: $(CPUSRC)/sh2/sh2comn.c \
- $(CPUSRC)/sh2/sh2comn.h \
- $(CPUSRC)/sh2/sh2.h
-
-$(CPUOBJ)/sh2/sh2drc.o: $(CPUSRC)/sh2/sh2drc.c \
- $(CPUSRC)/sh2/sh2.h \
+ $(CPUSRC)/sh2/sh2comn.c \
+ $(CPUSRC)/sh2/sh2drc.c \
$(CPUSRC)/sh2/sh2comn.h \
$(DRCDEPS)
diff --git a/src/emu/cpu/sh2/sh2.c b/src/emu/cpu/sh2/sh2.c
index c1b61d22c09..e168ef3daf6 100644
--- a/src/emu/cpu/sh2/sh2.c
+++ b/src/emu/cpu/sh2/sh2.c
@@ -82,7 +82,7 @@
20010207 Sylvain Glaize (mokona@puupuu.org)
- - Bug fix in INLINE void MOVBM(UINT32 m, UINT32 n) (see comment)
+ - Bug fix in void MOVBM(UINT32 m, UINT32 n) (see comment)
- Support of full 32 bit addressing (RB, RW, RL and WB, WW, WL functions)
reason : when the two high bits of the address are set, access is
done directly in the cache data array. The SUPER KANEKO NOVA SYSTEM
@@ -110,7 +110,146 @@
#include "sh2.h"
#include "sh2comn.h"
-CPU_DISASSEMBLE( sh2 );
+
+/***************************************************************************
+ DEBUGGING
+***************************************************************************/
+
+#define LOG_UML (0) // log UML assembly
+#define LOG_NATIVE (0) // log native assembly
+
+#define DISABLE_FAST_REGISTERS (0) // set to 1 to turn off usage of register caching
+#define SINGLE_INSTRUCTION_MODE (0)
+
+#define VERBOSE 0
+#define LOG(x) do { if (VERBOSE) logerror x; } while (0)
+
+/***************************************************************************
+ CONSTANTS
+***************************************************************************/
+
+/* size of the execution code cache */
+#define CACHE_SIZE (32 * 1024 * 1024)
+
+/* compilation boundaries -- how far back/forward does the analysis extend? */
+#define COMPILE_BACKWARDS_BYTES 64
+#define COMPILE_FORWARDS_BYTES 256
+#define COMPILE_MAX_INSTRUCTIONS ((COMPILE_BACKWARDS_BYTES/2) + (COMPILE_FORWARDS_BYTES/2))
+#define COMPILE_MAX_SEQUENCE 64
+
+
+const device_type SH1 = &device_creator<sh1_device>;
+const device_type SH2 = &device_creator<sh2_device>;
+
+
+/*-------------------------------------------------
+ sh2_internal_a5 - read handler for
+ SH2 internal map
+-------------------------------------------------*/
+
+READ32_MEMBER(sh2_device::sh2_internal_a5)
+{
+ return 0xa5a5a5a5;
+}
+
+
+/*-------------------------------------------------
+ sh2_internal_map - maps SH2 built-ins
+-------------------------------------------------*/
+
+static ADDRESS_MAP_START( sh2_internal_map, AS_PROGRAM, 32, sh2_device )
+ AM_RANGE(0x40000000, 0xbfffffff) AM_READ(sh2_internal_a5)
+ AM_RANGE(0xe0000000, 0xffffffff) AM_READWRITE(sh2_internal_r, sh2_internal_w)
+ADDRESS_MAP_END
+
+
+sh2_device::sh2_device(const machine_config &mconfig, const char *tag, device_t *owner, UINT32 clock)
+ : cpu_device(mconfig, SH2, "SH-2", tag, owner, clock, "sh2", __FILE__)
+ , m_program_config("program", ENDIANNESS_BIG, 32, 32, 0, ADDRESS_MAP_NAME(sh2_internal_map))
+ , m_cpu_type(CPU_TYPE_SH2)
+ , m_cache(CACHE_SIZE + sizeof(internal_sh2_state))
+ , m_drcuml(NULL)
+// , m_drcuml(*this, m_cache, ( LOG_UML ? DRCUML_OPTION_LOG_UML : 0 ) | ( LOG_NATIVE ? DRCUML_OPTION_LOG_NATIVE : 0 ), 1, 32, 1)
+ , m_drcfe(NULL)
+ , m_drcoptions(0)
+ , m_sh2_state(NULL)
+ , m_entry(NULL)
+ , m_read8(NULL)
+ , m_write8(NULL)
+ , m_read16(NULL)
+ , m_write16(NULL)
+ , m_read32(NULL)
+ , m_write32(NULL)
+ , m_interrupt(NULL)
+ , m_nocode(NULL)
+ , m_out_of_cycles(NULL)
+{
+ m_isdrc = mconfig.options().drc() ? true : false;
+}
+
+
+void sh2_device::device_stop()
+{
+ /* clean up the DRC */
+ if ( m_drcuml )
+ {
+ auto_free(machine(), m_drcuml);
+ }
+}
+
+
+sh2_device::sh2_device(const machine_config &mconfig, device_type type, const char *name, const char *tag, device_t *owner, UINT32 clock, const char *shortname, const char *source, int cpu_type)
+ : cpu_device(mconfig, type, name, tag, owner, clock, shortname, source)
+ , m_program_config("program", ENDIANNESS_BIG, 32, 32, 0, ADDRESS_MAP_NAME(sh2_internal_map))
+ , m_cpu_type(cpu_type)
+ , m_cache(CACHE_SIZE + sizeof(internal_sh2_state))
+ , m_drcuml(NULL)
+// , m_drcuml(*this, m_cache, ( LOG_UML ? DRCUML_OPTION_LOG_UML : 0 ) | ( LOG_NATIVE ? DRCUML_OPTION_LOG_NATIVE : 0 ), 1, 32, 1)
+ , m_drcfe(NULL)
+ , m_drcoptions(0)
+ , m_sh2_state(NULL)
+ , m_entry(NULL)
+ , m_read8(NULL)
+ , m_write8(NULL)
+ , m_read16(NULL)
+ , m_write16(NULL)
+ , m_read32(NULL)
+ , m_write32(NULL)
+ , m_interrupt(NULL)
+ , m_nocode(NULL)
+ , m_out_of_cycles(NULL)
+{
+ m_isdrc = mconfig.options().drc() ? true : false;
+}
+
+sh1_device::sh1_device(const machine_config &mconfig, const char *tag, device_t *owner, UINT32 clock)
+ : sh2_device(mconfig, SH1, "SH-1", tag, owner, clock, "sh1", __FILE__, CPU_TYPE_SH1 )
+{
+}
+
+
+offs_t sh2_device::disasm_disassemble(char *buffer, offs_t pc, const UINT8 *oprom, const UINT8 *opram, UINT32 options)
+{
+ extern CPU_DISASSEMBLE( sh2 );
+ return CPU_DISASSEMBLE_NAME( sh2 )(this, buffer, pc, oprom, opram, options);
+}
+
+
+void sh2_device::device_config_complete()
+{
+ // inherit a copy of the static data
+ const sh2_cpu_core *intf = reinterpret_cast<const sh2_cpu_core *>(static_config());
+ if (intf != NULL)
+ *static_cast<sh2_cpu_core *>(this) = *intf;
+
+ // or initialize to defaults if none provided
+ else
+ {
+ memset(&dma_callback_kludge, 0, sizeof(dma_callback_kludge));
+ memset(&dma_callback_fifo_data_available, 0, sizeof(dma_callback_fifo_data_available));
+ is_slave = 0;
+ }
+}
/* speed up delay loops, bail out of tight loops */
@@ -120,172 +259,171 @@ CPU_DISASSEMBLE( sh2 );
#define LOG(x) do { if (VERBOSE) logerror x; } while (0)
-INLINE sh2_state *get_safe_token(device_t *device)
-{
- assert(device != NULL);
- assert(device->type() == SH1_INT ||
- device->type() == SH2_INT);
- return (sh2_state *)downcast<legacy_cpu_device *>(device)->token();
-}
-INLINE UINT8 RB(sh2_state *sh2, offs_t A)
+UINT8 sh2_device::RB(offs_t A)
{
if (A >= 0xe0000000)
- return sh2_internal_r(*sh2->internal, (A & 0x1fc)>>2, 0xff << (((~A) & 3)*8)) >> (((~A) & 3)*8);
+ return sh2_internal_r(*m_internal, (A & 0x1fc)>>2, 0xff << (((~A) & 3)*8)) >> (((~A) & 3)*8);
if (A >= 0xc0000000)
- return sh2->program->read_byte(A);
+ return m_program->read_byte(A);
if (A >= 0x40000000)
return 0xa5;
- return sh2->program->read_byte(A & AM);
+ return m_program->read_byte(A & AM);
}
-INLINE UINT16 RW(sh2_state *sh2, offs_t A)
+UINT16 sh2_device::RW(offs_t A)
{
if (A >= 0xe0000000)
- return sh2_internal_r(*sh2->internal, (A & 0x1fc)>>2, 0xffff << (((~A) & 2)*8)) >> (((~A) & 2)*8);
+ return sh2_internal_r(*m_internal, (A & 0x1fc)>>2, 0xffff << (((~A) & 2)*8)) >> (((~A) & 2)*8);
if (A >= 0xc0000000)
- return sh2->program->read_word(A);
+ return m_program->read_word(A);
if (A >= 0x40000000)
return 0xa5a5;
- return sh2->program->read_word(A & AM);
+ return m_program->read_word(A & AM);
}
-INLINE UINT32 RL(sh2_state *sh2, offs_t A)
+UINT32 sh2_device::RL(offs_t A)
{
- if (A >= 0xe0000000)
- return sh2_internal_r(*sh2->internal, (A & 0x1fc)>>2, 0xffffffff);
+ if (A >= 0xe0000000) /* I/O */
+ return sh2_internal_r(*m_internal, (A & 0x1fc)>>2, 0xffffffff);
- if (A >= 0xc0000000)
- return sh2->program->read_dword(A);
+ if (A >= 0xc0000000) /* Cache Data Array */
+ return m_program->read_dword(A);
- if (A >= 0x40000000)
+ if (A >= 0x40000000) /* Cache Associative Purge Area */
return 0xa5a5a5a5;
- return sh2->program->read_dword(A & AM);
+ /* 0x20000000 no Cache */
+ /* 0x00000000 read thru Cache if CE bit is 1 */
+ return m_program->read_dword(A & AM);
}
-INLINE void WB(sh2_state *sh2, offs_t A, UINT8 V)
+void sh2_device::WB(offs_t A, UINT8 V)
{
if (A >= 0xe0000000)
{
- sh2_internal_w(*sh2->internal, (A & 0x1fc)>>2, V << (((~A) & 3)*8), 0xff << (((~A) & 3)*8));
+ sh2_internal_w(*m_internal, (A & 0x1fc)>>2, V << (((~A) & 3)*8), 0xff << (((~A) & 3)*8));
return;
}
if (A >= 0xc0000000)
{
- sh2->program->write_byte(A,V);
+ m_program->write_byte(A,V);
return;
}
if (A >= 0x40000000)
return;
- sh2->program->write_byte(A & AM,V);
+ m_program->write_byte(A & AM,V);
}
-INLINE void WW(sh2_state *sh2, offs_t A, UINT16 V)
+void sh2_device::WW(offs_t A, UINT16 V)
{
if (A >= 0xe0000000)
{
- sh2_internal_w(*sh2->internal, (A & 0x1fc)>>2, V << (((~A) & 2)*8), 0xffff << (((~A) & 2)*8));
+ sh2_internal_w(*m_internal, (A & 0x1fc)>>2, V << (((~A) & 2)*8), 0xffff << (((~A) & 2)*8));
return;
}
if (A >= 0xc0000000)
{
- sh2->program->write_word(A,V);
+ m_program->write_word(A,V);
return;
}
if (A >= 0x40000000)
return;
- sh2->program->write_word(A & AM,V);
+ m_program->write_word(A & AM,V);
}
-INLINE void WL(sh2_state *sh2, offs_t A, UINT32 V)
+void sh2_device::WL(offs_t A, UINT32 V)
{
- if (A >= 0xe0000000)
+ if (A >= 0xe0000000) /* I/O */
{
- sh2_internal_w(*sh2->internal, (A & 0x1fc)>>2, V, 0xffffffff);
+ sh2_internal_w(*m_internal, (A & 0x1fc)>>2, V, 0xffffffff);
return;
}
- if (A >= 0xc0000000)
+ if (A >= 0xc0000000) /* Cache Data Array */
{
- sh2->program->write_dword(A,V);
+ m_program->write_dword(A,V);
return;
}
- if (A >= 0x40000000)
+ /* 0x60000000 Cache Address Data Array */
+
+ if (A >= 0x40000000) /* Cache Associative Purge Area */
return;
- sh2->program->write_dword(A & AM,V);
+ /* 0x20000000 no Cache */
+ /* 0x00000000 read thru Cache if CE bit is 1 */
+ m_program->write_dword(A & AM,V);
}
/* code cycles t-bit
* 0011 nnnn mmmm 1100 1 -
* ADD Rm,Rn
*/
-INLINE void ADD(sh2_state *sh2, UINT32 m, UINT32 n)
+void sh2_device::ADD(UINT32 m, UINT32 n)
{
- sh2->r[n] += sh2->r[m];
+ m_sh2_state->r[n] += m_sh2_state->r[m];
}
/* code cycles t-bit
* 0111 nnnn iiii iiii 1 -
* ADD #imm,Rn
*/
-INLINE void ADDI(sh2_state *sh2, UINT32 i, UINT32 n)
+void sh2_device::ADDI(UINT32 i, UINT32 n)
{
- sh2->r[n] += (INT32)(INT16)(INT8)i;
+ m_sh2_state->r[n] += (INT32)(INT16)(INT8)i;
}
/* code cycles t-bit
* 0011 nnnn mmmm 1110 1 carry
* ADDC Rm,Rn
*/
-INLINE void ADDC(sh2_state *sh2, UINT32 m, UINT32 n)
+void sh2_device::ADDC(UINT32 m, UINT32 n)
{
UINT32 tmp0, tmp1;
- tmp1 = sh2->r[n] + sh2->r[m];
- tmp0 = sh2->r[n];
- sh2->r[n] = tmp1 + (sh2->sr & T);
+ tmp1 = m_sh2_state->r[n] + m_sh2_state->r[m];
+ tmp0 = m_sh2_state->r[n];
+ m_sh2_state->r[n] = tmp1 + (m_sh2_state->sr & T);
if (tmp0 > tmp1)
- sh2->sr |= T;
+ m_sh2_state->sr |= T;
else
- sh2->sr &= ~T;
- if (tmp1 > sh2->r[n])
- sh2->sr |= T;
+ m_sh2_state->sr &= ~T;
+ if (tmp1 > m_sh2_state->r[n])
+ m_sh2_state->sr |= T;
}
/* code cycles t-bit
* 0011 nnnn mmmm 1111 1 overflow
* ADDV Rm,Rn
*/
-INLINE void ADDV(sh2_state *sh2, UINT32 m, UINT32 n)
+void sh2_device::ADDV(UINT32 m, UINT32 n)
{
INT32 dest, src, ans;
- if ((INT32) sh2->r[n] >= 0)
+ if ((INT32) m_sh2_state->r[n] >= 0)
dest = 0;
else
dest = 1;
- if ((INT32) sh2->r[m] >= 0)
+ if ((INT32) m_sh2_state->r[m] >= 0)
src = 0;
else
src = 1;
src += dest;
- sh2->r[n] += sh2->r[m];
- if ((INT32) sh2->r[n] >= 0)
+ m_sh2_state->r[n] += m_sh2_state->r[m];
+ if ((INT32) m_sh2_state->r[n] >= 0)
ans = 0;
else
ans = 1;
@@ -293,21 +431,21 @@ INLINE void ADDV(sh2_state *sh2, UINT32 m, UINT32 n)
if (src == 0 || src == 2)
{
if (ans == 1)
- sh2->sr |= T;
+ m_sh2_state->sr |= T;
else
- sh2->sr &= ~T;
+ m_sh2_state->sr &= ~T;
}
else
- sh2->sr &= ~T;
+ m_sh2_state->sr &= ~T;
}
/* code cycles t-bit
* 0010 nnnn mmmm 1001 1 -
* AND Rm,Rn
*/
-INLINE void AND(sh2_state *sh2, UINT32 m, UINT32 n)
+void sh2_device::AND(UINT32 m, UINT32 n)
{
- sh2->r[n] &= sh2->r[m];
+ m_sh2_state->r[n] &= m_sh2_state->r[m];
}
@@ -315,36 +453,36 @@ INLINE void AND(sh2_state *sh2, UINT32 m, UINT32 n)
* 1100 1001 iiii iiii 1 -
* AND #imm,R0
*/
-INLINE void ANDI(sh2_state *sh2, UINT32 i)
+void sh2_device::ANDI(UINT32 i)
{
- sh2->r[0] &= i;
+ m_sh2_state->r[0] &= i;
}
/* code cycles t-bit
* 1100 1101 iiii iiii 1 -
* AND.B #imm,@(R0,GBR)
*/
-INLINE void ANDM(sh2_state *sh2, UINT32 i)
+void sh2_device::ANDM(UINT32 i)
{
UINT32 temp;
- sh2->ea = sh2->gbr + sh2->r[0];
- temp = i & RB( sh2, sh2->ea );
- WB( sh2, sh2->ea, temp );
- sh2->icount -= 2;
+ m_sh2_state->ea = m_sh2_state->gbr + m_sh2_state->r[0];
+ temp = i & RB( m_sh2_state->ea );
+ WB( m_sh2_state->ea, temp );
+ m_sh2_state->icount -= 2;
}
/* code cycles t-bit
* 1000 1011 dddd dddd 3/1 -
* BF disp8
*/
-INLINE void BF(sh2_state *sh2, UINT32 d)
+void sh2_device::BF(UINT32 d)
{
- if ((sh2->sr & T) == 0)
+ if ((m_sh2_state->sr & T) == 0)
{
INT32 disp = ((INT32)d << 24) >> 24;
- sh2->pc = sh2->ea = sh2->pc + disp * 2 + 2;
- sh2->icount -= 2;
+ m_sh2_state->pc = m_sh2_state->ea = m_sh2_state->pc + disp * 2 + 2;
+ m_sh2_state->icount -= 2;
}
}
@@ -352,14 +490,14 @@ INLINE void BF(sh2_state *sh2, UINT32 d)
* 1000 1111 dddd dddd 3/1 -
* BFS disp8
*/
-INLINE void BFS(sh2_state *sh2, UINT32 d)
+void sh2_device::BFS(UINT32 d)
{
- if ((sh2->sr & T) == 0)
+ if ((m_sh2_state->sr & T) == 0)
{
INT32 disp = ((INT32)d << 24) >> 24;
- sh2->delay = sh2->pc;
- sh2->pc = sh2->ea = sh2->pc + disp * 2 + 2;
- sh2->icount--;
+ m_delay = m_sh2_state->pc;
+ m_sh2_state->pc = m_sh2_state->ea = m_sh2_state->pc + disp * 2 + 2;
+ m_sh2_state->icount--;
}
}
@@ -367,74 +505,74 @@ INLINE void BFS(sh2_state *sh2, UINT32 d)
* 1010 dddd dddd dddd 2 -
* BRA disp12
*/
-INLINE void BRA(sh2_state *sh2, UINT32 d)
+void sh2_device::BRA(UINT32 d)
{
INT32 disp = ((INT32)d << 20) >> 20;
#if BUSY_LOOP_HACKS
if (disp == -2)
{
- UINT32 next_opcode = RW( sh2, sh2->ppc & AM );
+ UINT32 next_opcode = RW( m_sh2_state->ppc & AM );
/* BRA $
* NOP
*/
if (next_opcode == 0x0009)
- sh2->icount %= 3; /* cycles for BRA $ and NOP taken (3) */
+ m_sh2_state->icount %= 3; /* cycles for BRA $ and NOP taken (3) */
}
#endif
- sh2->delay = sh2->pc;
- sh2->pc = sh2->ea = sh2->pc + disp * 2 + 2;
- sh2->icount--;
+ m_delay = m_sh2_state->pc;
+ m_sh2_state->pc = m_sh2_state->ea = m_sh2_state->pc + disp * 2 + 2;
+ m_sh2_state->icount--;
}
/* code cycles t-bit
* 0000 mmmm 0010 0011 2 -
* BRAF Rm
*/
-INLINE void BRAF(sh2_state *sh2, UINT32 m)
+void sh2_device::BRAF(UINT32 m)
{
- sh2->delay = sh2->pc;
- sh2->pc += sh2->r[m] + 2;
- sh2->icount--;
+ m_delay = m_sh2_state->pc;
+ m_sh2_state->pc += m_sh2_state->r[m] + 2;
+ m_sh2_state->icount--;
}
/* code cycles t-bit
* 1011 dddd dddd dddd 2 -
* BSR disp12
*/
-INLINE void BSR(sh2_state *sh2, UINT32 d)
+void sh2_device::BSR(UINT32 d)
{
INT32 disp = ((INT32)d << 20) >> 20;
- sh2->pr = sh2->pc + 2;
- sh2->delay = sh2->pc;
- sh2->pc = sh2->ea = sh2->pc + disp * 2 + 2;
- sh2->icount--;
+ m_sh2_state->pr = m_sh2_state->pc + 2;
+ m_delay = m_sh2_state->pc;
+ m_sh2_state->pc = m_sh2_state->ea = m_sh2_state->pc + disp * 2 + 2;
+ m_sh2_state->icount--;
}
/* code cycles t-bit
* 0000 mmmm 0000 0011 2 -
* BSRF Rm
*/
-INLINE void BSRF(sh2_state *sh2, UINT32 m)
+void sh2_device::BSRF(UINT32 m)
{
- sh2->pr = sh2->pc + 2;
- sh2->delay = sh2->pc;
- sh2->pc += sh2->r[m] + 2;
- sh2->icount--;
+ m_sh2_state->pr = m_sh2_state->pc + 2;
+ m_delay = m_sh2_state->pc;
+ m_sh2_state->pc += m_sh2_state->r[m] + 2;
+ m_sh2_state->icount--;
}
/* code cycles t-bit
* 1000 1001 dddd dddd 3/1 -
* BT disp8
*/
-INLINE void BT(sh2_state *sh2, UINT32 d)
+void sh2_device::BT(UINT32 d)
{
- if ((sh2->sr & T) != 0)
+ if ((m_sh2_state->sr & T) != 0)
{
INT32 disp = ((INT32)d << 24) >> 24;
- sh2->pc = sh2->ea = sh2->pc + disp * 2 + 2;
- sh2->icount -= 2;
+ m_sh2_state->pc = m_sh2_state->ea = m_sh2_state->pc + disp * 2 + 2;
+ m_sh2_state->icount -= 2;
}
}
@@ -442,14 +580,14 @@ INLINE void BT(sh2_state *sh2, UINT32 d)
* 1000 1101 dddd dddd 2/1 -
* BTS disp8
*/
-INLINE void BTS(sh2_state *sh2, UINT32 d)
+void sh2_device::BTS(UINT32 d)
{
- if ((sh2->sr & T) != 0)
+ if ((m_sh2_state->sr & T) != 0)
{
INT32 disp = ((INT32)d << 24) >> 24;
- sh2->delay = sh2->pc;
- sh2->pc = sh2->ea = sh2->pc + disp * 2 + 2;
- sh2->icount--;
+ m_delay = m_sh2_state->pc;
+ m_sh2_state->pc = m_sh2_state->ea = m_sh2_state->pc + disp * 2 + 2;
+ m_sh2_state->icount--;
}
}
@@ -457,79 +595,79 @@ INLINE void BTS(sh2_state *sh2, UINT32 d)
* 0000 0000 0010 1000 1 -
* CLRMAC
*/
-INLINE void CLRMAC(sh2_state *sh2)
+void sh2_device::CLRMAC()
{
- sh2->mach = 0;
- sh2->macl = 0;
+ m_sh2_state->mach = 0;
+ m_sh2_state->macl = 0;
}
/* code cycles t-bit
* 0000 0000 0000 1000 1 -
* CLRT
*/
-INLINE void CLRT(sh2_state *sh2)
+void sh2_device::CLRT()
{
- sh2->sr &= ~T;
+ m_sh2_state->sr &= ~T;
}
/* code cycles t-bit
* 0011 nnnn mmmm 0000 1 comparison result
* CMP_EQ Rm,Rn
*/
-INLINE void CMPEQ(sh2_state *sh2, UINT32 m, UINT32 n)
+void sh2_device::CMPEQ(UINT32 m, UINT32 n)
{
- if (sh2->r[n] == sh2->r[m])
- sh2->sr |= T;
+ if (m_sh2_state->r[n] == m_sh2_state->r[m])
+ m_sh2_state->sr |= T;
else
- sh2->sr &= ~T;
+ m_sh2_state->sr &= ~T;
}
/* code cycles t-bit
* 0011 nnnn mmmm 0011 1 comparison result
* CMP_GE Rm,Rn
*/
-INLINE void CMPGE(sh2_state *sh2, UINT32 m, UINT32 n)
+void sh2_device::CMPGE(UINT32 m, UINT32 n)
{
- if ((INT32) sh2->r[n] >= (INT32) sh2->r[m])
- sh2->sr |= T;
+ if ((INT32) m_sh2_state->r[n] >= (INT32) m_sh2_state->r[m])
+ m_sh2_state->sr |= T;
else
- sh2->sr &= ~T;
+ m_sh2_state->sr &= ~T;
}
/* code cycles t-bit
* 0011 nnnn mmmm 0111 1 comparison result
* CMP_GT Rm,Rn
*/
-INLINE void CMPGT(sh2_state *sh2, UINT32 m, UINT32 n)
+void sh2_device::CMPGT(UINT32 m, UINT32 n)
{
- if ((INT32) sh2->r[n] > (INT32) sh2->r[m])
- sh2->sr |= T;
+ if ((INT32) m_sh2_state->r[n] > (INT32) m_sh2_state->r[m])
+ m_sh2_state->sr |= T;
else
- sh2->sr &= ~T;
+ m_sh2_state->sr &= ~T;
}
/* code cycles t-bit
* 0011 nnnn mmmm 0110 1 comparison result
* CMP_HI Rm,Rn
*/
-INLINE void CMPHI(sh2_state *sh2, UINT32 m, UINT32 n)
+void sh2_device::CMPHI(UINT32 m, UINT32 n)
{
- if ((UINT32) sh2->r[n] > (UINT32) sh2->r[m])
- sh2->sr |= T;
+ if ((UINT32) m_sh2_state->r[n] > (UINT32) m_sh2_state->r[m])
+ m_sh2_state->sr |= T;
else
- sh2->sr &= ~T;
+ m_sh2_state->sr &= ~T;
}
/* code cycles t-bit
* 0011 nnnn mmmm 0010 1 comparison result
* CMP_HS Rm,Rn
*/
-INLINE void CMPHS(sh2_state *sh2, UINT32 m, UINT32 n)
+void sh2_device::CMPHS(UINT32 m, UINT32 n)
{
- if ((UINT32) sh2->r[n] >= (UINT32) sh2->r[m])
- sh2->sr |= T;
+ if ((UINT32) m_sh2_state->r[n] >= (UINT32) m_sh2_state->r[m])
+ m_sh2_state->sr |= T;
else
- sh2->sr &= ~T;
+ m_sh2_state->sr &= ~T;
}
@@ -537,43 +675,43 @@ INLINE void CMPHS(sh2_state *sh2, UINT32 m, UINT32 n)
* 0100 nnnn 0001 0101 1 comparison result
* CMP_PL Rn
*/
-INLINE void CMPPL(sh2_state *sh2, UINT32 n)
+void sh2_device::CMPPL(UINT32 n)
{
- if ((INT32) sh2->r[n] > 0)
- sh2->sr |= T;
+ if ((INT32) m_sh2_state->r[n] > 0)
+ m_sh2_state->sr |= T;
else
- sh2->sr &= ~T;
+ m_sh2_state->sr &= ~T;
}
/* code cycles t-bit
* 0100 nnnn 0001 0001 1 comparison result
* CMP_PZ Rn
*/
-INLINE void CMPPZ(sh2_state *sh2, UINT32 n)
+void sh2_device::CMPPZ(UINT32 n)
{
- if ((INT32) sh2->r[n] >= 0)
- sh2->sr |= T;
+ if ((INT32) m_sh2_state->r[n] >= 0)
+ m_sh2_state->sr |= T;
else
- sh2->sr &= ~T;
+ m_sh2_state->sr &= ~T;
}
/* code cycles t-bit
* 0010 nnnn mmmm 1100 1 comparison result
* CMP_STR Rm,Rn
*/
-INLINE void CMPSTR(sh2_state *sh2, UINT32 m, UINT32 n)
+void sh2_device::CMPSTR(UINT32 m, UINT32 n)
{
UINT32 temp;
INT32 HH, HL, LH, LL;
- temp = sh2->r[n] ^ sh2->r[m];
+ temp = m_sh2_state->r[n] ^ m_sh2_state->r[m];
HH = (temp >> 24) & 0xff;
HL = (temp >> 16) & 0xff;
LH = (temp >> 8) & 0xff;
LL = temp & 0xff;
if (HH && HL && LH && LL)
- sh2->sr &= ~T;
+ m_sh2_state->sr &= ~T;
else
- sh2->sr |= T;
+ m_sh2_state->sr |= T;
}
@@ -581,154 +719,154 @@ INLINE void CMPSTR(sh2_state *sh2, UINT32 m, UINT32 n)
* 1000 1000 iiii iiii 1 comparison result
* CMP/EQ #imm,R0
*/
-INLINE void CMPIM(sh2_state *sh2, UINT32 i)
+void sh2_device::CMPIM(UINT32 i)
{
UINT32 imm = (UINT32)(INT32)(INT16)(INT8)i;
- if (sh2->r[0] == imm)
- sh2->sr |= T;
+ if (m_sh2_state->r[0] == imm)
+ m_sh2_state->sr |= T;
else
- sh2->sr &= ~T;
+ m_sh2_state->sr &= ~T;
}
/* code cycles t-bit
* 0010 nnnn mmmm 0111 1 calculation result
* DIV0S Rm,Rn
*/
-INLINE void DIV0S(sh2_state *sh2, UINT32 m, UINT32 n)
+void sh2_device::DIV0S(UINT32 m, UINT32 n)
{
- if ((sh2->r[n] & 0x80000000) == 0)
- sh2->sr &= ~Q;
+ if ((m_sh2_state->r[n] & 0x80000000) == 0)
+ m_sh2_state->sr &= ~Q;
else
- sh2->sr |= Q;
- if ((sh2->r[m] & 0x80000000) == 0)
- sh2->sr &= ~M;
+ m_sh2_state->sr |= Q;
+ if ((m_sh2_state->r[m] & 0x80000000) == 0)
+ m_sh2_state->sr &= ~M;
else
- sh2->sr |= M;
- if ((sh2->r[m] ^ sh2->r[n]) & 0x80000000)
- sh2->sr |= T;
+ m_sh2_state->sr |= M;
+ if ((m_sh2_state->r[m] ^ m_sh2_state->r[n]) & 0x80000000)
+ m_sh2_state->sr |= T;
else
- sh2->sr &= ~T;
+ m_sh2_state->sr &= ~T;
}
/* code cycles t-bit
* 0000 0000 0001 1001 1 0
* DIV0U
*/
-INLINE void DIV0U(sh2_state *sh2)
+void sh2_device::DIV0U()
{
- sh2->sr &= ~(M | Q | T);
+ m_sh2_state->sr &= ~(M | Q | T);
}
/* code cycles t-bit
* 0011 nnnn mmmm 0100 1 calculation result
* DIV1 Rm,Rn
*/
-INLINE void DIV1(sh2_state *sh2, UINT32 m, UINT32 n)
+void sh2_device::DIV1(UINT32 m, UINT32 n)
{
UINT32 tmp0;
UINT32 old_q;
- old_q = sh2->sr & Q;
- if (0x80000000 & sh2->r[n])
- sh2->sr |= Q;
+ old_q = m_sh2_state->sr & Q;
+ if (0x80000000 & m_sh2_state->r[n])
+ m_sh2_state->sr |= Q;
else
- sh2->sr &= ~Q;
+ m_sh2_state->sr &= ~Q;
- sh2->r[n] = (sh2->r[n] << 1) | (sh2->sr & T);
+ m_sh2_state->r[n] = (m_sh2_state->r[n] << 1) | (m_sh2_state->sr & T);
if (!old_q)
{
- if (!(sh2->sr & M))
+ if (!(m_sh2_state->sr & M))
{
- tmp0 = sh2->r[n];
- sh2->r[n] -= sh2->r[m];
- if(!(sh2->sr & Q))
- if(sh2->r[n] > tmp0)
- sh2->sr |= Q;
+ tmp0 = m_sh2_state->r[n];
+ m_sh2_state->r[n] -= m_sh2_state->r[m];
+ if(!(m_sh2_state->sr & Q))
+ if(m_sh2_state->r[n] > tmp0)
+ m_sh2_state->sr |= Q;
else
- sh2->sr &= ~Q;
+ m_sh2_state->sr &= ~Q;
else
- if(sh2->r[n] > tmp0)
- sh2->sr &= ~Q;
+ if(m_sh2_state->r[n] > tmp0)
+ m_sh2_state->sr &= ~Q;
else
- sh2->sr |= Q;
+ m_sh2_state->sr |= Q;
}
else
{
- tmp0 = sh2->r[n];
- sh2->r[n] += sh2->r[m];
- if(!(sh2->sr & Q))
+ tmp0 = m_sh2_state->r[n];
+ m_sh2_state->r[n] += m_sh2_state->r[m];
+ if(!(m_sh2_state->sr & Q))
{
- if(sh2->r[n] < tmp0)
- sh2->sr &= ~Q;
+ if(m_sh2_state->r[n] < tmp0)
+ m_sh2_state->sr &= ~Q;
else
- sh2->sr |= Q;
+ m_sh2_state->sr |= Q;
}
else
{
- if(sh2->r[n] < tmp0)
- sh2->sr |= Q;
+ if(m_sh2_state->r[n] < tmp0)
+ m_sh2_state->sr |= Q;
else
- sh2->sr &= ~Q;
+ m_sh2_state->sr &= ~Q;
}
}
}
else
{
- if (!(sh2->sr & M))
+ if (!(m_sh2_state->sr & M))
{
- tmp0 = sh2->r[n];
- sh2->r[n] += sh2->r[m];
- if(!(sh2->sr & Q))
- if(sh2->r[n] < tmp0)
- sh2->sr |= Q;
+ tmp0 = m_sh2_state->r[n];
+ m_sh2_state->r[n] += m_sh2_state->r[m];
+ if(!(m_sh2_state->sr & Q))
+ if(m_sh2_state->r[n] < tmp0)
+ m_sh2_state->sr |= Q;
else
- sh2->sr &= ~Q;
+ m_sh2_state->sr &= ~Q;
else
- if(sh2->r[n] < tmp0)
- sh2->sr &= ~Q;
+ if(m_sh2_state->r[n] < tmp0)
+ m_sh2_state->sr &= ~Q;
else
- sh2->sr |= Q;
+ m_sh2_state->sr |= Q;
}
else
{
- tmp0 = sh2->r[n];
- sh2->r[n] -= sh2->r[m];
- if(!(sh2->sr & Q))
- if(sh2->r[n] > tmp0)
- sh2->sr &= ~Q;
+ tmp0 = m_sh2_state->r[n];
+ m_sh2_state->r[n] -= m_sh2_state->r[m];
+ if(!(m_sh2_state->sr & Q))
+ if(m_sh2_state->r[n] > tmp0)
+ m_sh2_state->sr &= ~Q;
else
- sh2->sr |= Q;
+ m_sh2_state->sr |= Q;
else
- if(sh2->r[n] > tmp0)
- sh2->sr |= Q;
+ if(m_sh2_state->r[n] > tmp0)
+ m_sh2_state->sr |= Q;
else
- sh2->sr &= ~Q;
+ m_sh2_state->sr &= ~Q;
}
}
- tmp0 = (sh2->sr & (Q | M));
+ tmp0 = (m_sh2_state->sr & (Q | M));
if((!tmp0) || (tmp0 == 0x300)) /* if Q == M set T else clear T */
- sh2->sr |= T;
+ m_sh2_state->sr |= T;
else
- sh2->sr &= ~T;
+ m_sh2_state->sr &= ~T;
}
/* DMULS.L Rm,Rn */
-INLINE void DMULS(sh2_state *sh2, UINT32 m, UINT32 n)
+void sh2_device::DMULS(UINT32 m, UINT32 n)
{
UINT32 RnL, RnH, RmL, RmH, Res0, Res1, Res2;
UINT32 temp0, temp1, temp2, temp3;
INT32 tempm, tempn, fnLmL;
- tempn = (INT32) sh2->r[n];
- tempm = (INT32) sh2->r[m];
+ tempn = (INT32) m_sh2_state->r[n];
+ tempm = (INT32) m_sh2_state->r[m];
if (tempn < 0)
tempn = 0 - tempn;
if (tempm < 0)
tempm = 0 - tempm;
- if ((INT32) (sh2->r[n] ^ sh2->r[m]) < 0)
+ if ((INT32) (m_sh2_state->r[n] ^ m_sh2_state->r[m]) < 0)
fnLmL = -1;
else
fnLmL = 0;
@@ -759,21 +897,21 @@ INLINE void DMULS(sh2_state *sh2, UINT32 m, UINT32 n)
else
Res0 = (~Res0) + 1;
}
- sh2->mach = Res2;
- sh2->macl = Res0;
- sh2->icount--;
+ m_sh2_state->mach = Res2;
+ m_sh2_state->macl = Res0;
+ m_sh2_state->icount--;
}
/* DMULU.L Rm,Rn */
-INLINE void DMULU(sh2_state *sh2, UINT32 m, UINT32 n)
+void sh2_device::DMULU(UINT32 m, UINT32 n)
{
UINT32 RnL, RnH, RmL, RmH, Res0, Res1, Res2;
UINT32 temp0, temp1, temp2, temp3;
- RnL = sh2->r[n] & 0x0000ffff;
- RnH = (sh2->r[n] >> 16) & 0x0000ffff;
- RmL = sh2->r[m] & 0x0000ffff;
- RmH = (sh2->r[m] >> 16) & 0x0000ffff;
+ RnL = m_sh2_state->r[n] & 0x0000ffff;
+ RnH = (m_sh2_state->r[n] >> 16) & 0x0000ffff;
+ RmL = m_sh2_state->r[m] & 0x0000ffff;
+ RmH = (m_sh2_state->r[m] >> 16) & 0x0000ffff;
temp0 = RmL * RnL;
temp1 = RmH * RnL;
temp2 = RmL * RnH;
@@ -787,31 +925,31 @@ INLINE void DMULU(sh2_state *sh2, UINT32 m, UINT32 n)
if (Res0 < temp0)
Res2++;
Res2 = Res2 + ((Res1 >> 16) & 0x0000ffff) + temp3;
- sh2->mach = Res2;
- sh2->macl = Res0;
- sh2->icount--;
+ m_sh2_state->mach = Res2;
+ m_sh2_state->macl = Res0;
+ m_sh2_state->icount--;
}
/* DT Rn */
-INLINE void DT(sh2_state *sh2, UINT32 n)
+void sh2_device::DT(UINT32 n)
{
- sh2->r[n]--;
- if (sh2->r[n] == 0)
- sh2->sr |= T;
+ m_sh2_state->r[n]--;
+ if (m_sh2_state->r[n] == 0)
+ m_sh2_state->sr |= T;
else
- sh2->sr &= ~T;
+ m_sh2_state->sr &= ~T;
#if BUSY_LOOP_HACKS
{
- UINT32 next_opcode = RW( sh2, sh2->ppc & AM );
+ UINT32 next_opcode = RW( m_sh2_state->ppc & AM );
/* DT Rn
* BF $-2
*/
if (next_opcode == 0x8bfd)
{
- while (sh2->r[n] > 1 && sh2->icount > 4)
+ while (m_sh2_state->r[n] > 1 && m_sh2_state->icount > 4)
{
- sh2->r[n]--;
- sh2->icount -= 4; /* cycles for DT (1) and BF taken (3) */
+ m_sh2_state->r[n]--;
+ m_sh2_state->icount -= 4; /* cycles for DT (1) and BF taken (3) */
}
}
}
@@ -819,164 +957,164 @@ INLINE void DT(sh2_state *sh2, UINT32 n)
}
/* EXTS.B Rm,Rn */
-INLINE void EXTSB(sh2_state *sh2, UINT32 m, UINT32 n)
+void sh2_device::EXTSB(UINT32 m, UINT32 n)
{
- sh2->r[n] = ((INT32)sh2->r[m] << 24) >> 24;
+ m_sh2_state->r[n] = ((INT32)m_sh2_state->r[m] << 24) >> 24;
}
/* EXTS.W Rm,Rn */
-INLINE void EXTSW(sh2_state *sh2, UINT32 m, UINT32 n)
+void sh2_device::EXTSW(UINT32 m, UINT32 n)
{
- sh2->r[n] = ((INT32)sh2->r[m] << 16) >> 16;
+ m_sh2_state->r[n] = ((INT32)m_sh2_state->r[m] << 16) >> 16;
}
/* EXTU.B Rm,Rn */
-INLINE void EXTUB(sh2_state *sh2, UINT32 m, UINT32 n)
+void sh2_device::EXTUB(UINT32 m, UINT32 n)
{
- sh2->r[n] = sh2->r[m] & 0x000000ff;
+ m_sh2_state->r[n] = m_sh2_state->r[m] & 0x000000ff;
}
/* EXTU.W Rm,Rn */
-INLINE void EXTUW(sh2_state *sh2, UINT32 m, UINT32 n)
+void sh2_device::EXTUW(UINT32 m, UINT32 n)
{
- sh2->r[n] = sh2->r[m] & 0x0000ffff;
+ m_sh2_state->r[n] = m_sh2_state->r[m] & 0x0000ffff;
}
/* ILLEGAL */
-INLINE void ILLEGAL(sh2_state *sh2)
+void sh2_device::ILLEGAL()
{
- logerror("SH2.%s: Illegal opcode at %08x\n", sh2->device->tag(), sh2->pc - 2);
- sh2->r[15] -= 4;
- WL( sh2, sh2->r[15], sh2->sr ); /* push SR onto stack */
- sh2->r[15] -= 4;
- WL( sh2, sh2->r[15], sh2->pc - 2 ); /* push PC onto stack */
+ logerror("SH2.%s: Illegal opcode at %08x\n", tag(), m_sh2_state->pc - 2);
+ m_sh2_state->r[15] -= 4;
+ WL( m_sh2_state->r[15], m_sh2_state->sr ); /* push SR onto stack */
+ m_sh2_state->r[15] -= 4;
+ WL( m_sh2_state->r[15], m_sh2_state->pc - 2 ); /* push PC onto stack */
/* fetch PC */
- sh2->pc = RL( sh2, sh2->vbr + 4 * 4 );
+ m_sh2_state->pc = RL( m_sh2_state->vbr + 4 * 4 );
/* TODO: timing is a guess */
- sh2->icount -= 5;
+ m_sh2_state->icount -= 5;
}
/* JMP @Rm */
-INLINE void JMP(sh2_state *sh2, UINT32 m)
+void sh2_device::JMP(UINT32 m)
{
- sh2->delay = sh2->pc;
- sh2->pc = sh2->ea = sh2->r[m];
- sh2->icount--;
+ m_delay = m_sh2_state->pc;
+ m_sh2_state->pc = m_sh2_state->ea = m_sh2_state->r[m];
+ m_sh2_state->icount--;
}
/* JSR @Rm */
-INLINE void JSR(sh2_state *sh2, UINT32 m)
+void sh2_device::JSR(UINT32 m)
{
- sh2->delay = sh2->pc;
- sh2->pr = sh2->pc + 2;
- sh2->pc = sh2->ea = sh2->r[m];
- sh2->icount--;
+ m_delay = m_sh2_state->pc;
+ m_sh2_state->pr = m_sh2_state->pc + 2;
+ m_sh2_state->pc = m_sh2_state->ea = m_sh2_state->r[m];
+ m_sh2_state->icount--;
}
/* LDC Rm,SR */
-INLINE void LDCSR(sh2_state *sh2, UINT32 m)
+void sh2_device::LDCSR(UINT32 m)
{
- sh2->sr = sh2->r[m] & FLAGS;
- sh2->test_irq = 1;
+ m_sh2_state->sr = m_sh2_state->r[m] & FLAGS;
+ m_test_irq = 1;
}
/* LDC Rm,GBR */
-INLINE void LDCGBR(sh2_state *sh2, UINT32 m)
+void sh2_device::LDCGBR(UINT32 m)
{
- sh2->gbr = sh2->r[m];
+ m_sh2_state->gbr = m_sh2_state->r[m];
}
/* LDC Rm,VBR */
-INLINE void LDCVBR(sh2_state *sh2, UINT32 m)
+void sh2_device::LDCVBR(UINT32 m)
{
- sh2->vbr = sh2->r[m];
+ m_sh2_state->vbr = m_sh2_state->r[m];
}
/* LDC.L @Rm+,SR */
-INLINE void LDCMSR(sh2_state *sh2, UINT32 m)
+void sh2_device::LDCMSR(UINT32 m)
{
- sh2->ea = sh2->r[m];
- sh2->sr = RL( sh2, sh2->ea ) & FLAGS;
- sh2->r[m] += 4;
- sh2->icount -= 2;
- sh2->test_irq = 1;
+ m_sh2_state->ea = m_sh2_state->r[m];
+ m_sh2_state->sr = RL( m_sh2_state->ea ) & FLAGS;
+ m_sh2_state->r[m] += 4;
+ m_sh2_state->icount -= 2;
+ m_test_irq = 1;
}
/* LDC.L @Rm+,GBR */
-INLINE void LDCMGBR(sh2_state *sh2, UINT32 m)
+void sh2_device::LDCMGBR(UINT32 m)
{
- sh2->ea = sh2->r[m];
- sh2->gbr = RL( sh2, sh2->ea );
- sh2->r[m] += 4;
- sh2->icount -= 2;
+ m_sh2_state->ea = m_sh2_state->r[m];
+ m_sh2_state->gbr = RL( m_sh2_state->ea );
+ m_sh2_state->r[m] += 4;
+ m_sh2_state->icount -= 2;
}
/* LDC.L @Rm+,VBR */
-INLINE void LDCMVBR(sh2_state *sh2, UINT32 m)
+void sh2_device::LDCMVBR(UINT32 m)
{
- sh2->ea = sh2->r[m];
- sh2->vbr = RL( sh2, sh2->ea );
- sh2->r[m] += 4;
- sh2->icount -= 2;
+ m_sh2_state->ea = m_sh2_state->r[m];
+ m_sh2_state->vbr = RL( m_sh2_state->ea );
+ m_sh2_state->r[m] += 4;
+ m_sh2_state->icount -= 2;
}
/* LDS Rm,MACH */
-INLINE void LDSMACH(sh2_state *sh2, UINT32 m)
+void sh2_device::LDSMACH(UINT32 m)
{
- sh2->mach = sh2->r[m];
+ m_sh2_state->mach = m_sh2_state->r[m];
}
/* LDS Rm,MACL */
-INLINE void LDSMACL(sh2_state *sh2, UINT32 m)
+void sh2_device::LDSMACL(UINT32 m)
{
- sh2->macl = sh2->r[m];
+ m_sh2_state->macl = m_sh2_state->r[m];
}
/* LDS Rm,PR */
-INLINE void LDSPR(sh2_state *sh2, UINT32 m)
+void sh2_device::LDSPR(UINT32 m)
{
- sh2->pr = sh2->r[m];
+ m_sh2_state->pr = m_sh2_state->r[m];
}
/* LDS.L @Rm+,MACH */
-INLINE void LDSMMACH(sh2_state *sh2, UINT32 m)
+void sh2_device::LDSMMACH(UINT32 m)
{
- sh2->ea = sh2->r[m];
- sh2->mach = RL( sh2, sh2->ea );
- sh2->r[m] += 4;
+ m_sh2_state->ea = m_sh2_state->r[m];
+ m_sh2_state->mach = RL( m_sh2_state->ea );
+ m_sh2_state->r[m] += 4;
}
/* LDS.L @Rm+,MACL */
-INLINE void LDSMMACL(sh2_state *sh2, UINT32 m)
+void sh2_device::LDSMMACL(UINT32 m)
{
- sh2->ea = sh2->r[m];
- sh2->macl = RL( sh2, sh2->ea );
- sh2->r[m] += 4;
+ m_sh2_state->ea = m_sh2_state->r[m];
+ m_sh2_state->macl = RL( m_sh2_state->ea );
+ m_sh2_state->r[m] += 4;
}
/* LDS.L @Rm+,PR */
-INLINE void LDSMPR(sh2_state *sh2, UINT32 m)
+void sh2_device::LDSMPR(UINT32 m)
{
- sh2->ea = sh2->r[m];
- sh2->pr = RL( sh2, sh2->ea );
- sh2->r[m] += 4;
+ m_sh2_state->ea = m_sh2_state->r[m];
+ m_sh2_state->pr = RL( m_sh2_state->ea );
+ m_sh2_state->r[m] += 4;
}
/* MAC.L @Rm+,@Rn+ */
-INLINE void MAC_L(sh2_state *sh2, UINT32 m, UINT32 n)
+void sh2_device::MAC_L(UINT32 m, UINT32 n)
{
UINT32 RnL, RnH, RmL, RmH, Res0, Res1, Res2;
UINT32 temp0, temp1, temp2, temp3;
INT32 tempm, tempn, fnLmL;
- tempn = (INT32) RL( sh2, sh2->r[n] );
- sh2->r[n] += 4;
- tempm = (INT32) RL( sh2, sh2->r[m] );
- sh2->r[m] += 4;
+ tempn = (INT32) RL( m_sh2_state->r[n] );
+ m_sh2_state->r[n] += 4;
+ tempm = (INT32) RL( m_sh2_state->r[m] );
+ m_sh2_state->r[m] += 4;
if ((INT32) (tempn ^ tempm) < 0)
fnLmL = -1;
else
@@ -1012,12 +1150,12 @@ INLINE void MAC_L(sh2_state *sh2, UINT32 m, UINT32 n)
else
Res0 = (~Res0) + 1;
}
- if (sh2->sr & S)
+ if (m_sh2_state->sr & S)
{
- Res0 = sh2->macl + Res0;
- if (sh2->macl > Res0)
+ Res0 = m_sh2_state->macl + Res0;
+ if (m_sh2_state->macl > Res0)
Res2++;
- Res2 += (sh2->mach & 0x0000ffff);
+ Res2 += (m_sh2_state->mach & 0x0000ffff);
if (((INT32) Res2 < 0) && (Res2 < 0xffff8000))
{
Res2 = 0x00008000;
@@ -1028,34 +1166,34 @@ INLINE void MAC_L(sh2_state *sh2, UINT32 m, UINT32 n)
Res2 = 0x00007fff;
Res0 = 0xffffffff;
}
- sh2->mach = Res2;
- sh2->macl = Res0;
+ m_sh2_state->mach = Res2;
+ m_sh2_state->macl = Res0;
}
else
{
- Res0 = sh2->macl + Res0;
- if (sh2->macl > Res0)
+ Res0 = m_sh2_state->macl + Res0;
+ if (m_sh2_state->macl > Res0)
Res2++;
- Res2 += sh2->mach;
- sh2->mach = Res2;
- sh2->macl = Res0;
+ Res2 += m_sh2_state->mach;
+ m_sh2_state->mach = Res2;
+ m_sh2_state->macl = Res0;
}
- sh2->icount -= 2;
+ m_sh2_state->icount -= 2;
}
/* MAC.W @Rm+,@Rn+ */
-INLINE void MAC_W(sh2_state *sh2, UINT32 m, UINT32 n)
+void sh2_device::MAC_W(UINT32 m, UINT32 n)
{
INT32 tempm, tempn, dest, src, ans;
UINT32 templ;
- tempn = (INT32) RW( sh2, sh2->r[n] );
- sh2->r[n] += 2;
- tempm = (INT32) RW( sh2, sh2->r[m] );
- sh2->r[m] += 2;
- templ = sh2->macl;
+ tempn = (INT32) RW( m_sh2_state->r[n] );
+ m_sh2_state->r[n] += 2;
+ tempm = (INT32) RW( m_sh2_state->r[m] );
+ m_sh2_state->r[m] += 2;
+ templ = m_sh2_state->macl;
tempm = ((INT32) (short) tempn * (INT32) (short) tempm);
- if ((INT32) sh2->macl >= 0)
+ if ((INT32) m_sh2_state->macl >= 0)
dest = 0;
else
dest = 1;
@@ -1070,644 +1208,644 @@ INLINE void MAC_W(sh2_state *sh2, UINT32 m, UINT32 n)
tempn = 0xffffffff;
}
src += dest;
- sh2->macl += tempm;
- if ((INT32) sh2->macl >= 0)
+ m_sh2_state->macl += tempm;
+ if ((INT32) m_sh2_state->macl >= 0)
ans = 0;
else
ans = 1;
ans += dest;
- if (sh2->sr & S)
+ if (m_sh2_state->sr & S)
{
if (ans == 1)
{
if (src == 0)
- sh2->macl = 0x7fffffff;
+ m_sh2_state->macl = 0x7fffffff;
if (src == 2)
- sh2->macl = 0x80000000;
+ m_sh2_state->macl = 0x80000000;
}
}
else
{
- sh2->mach += tempn;
- if (templ > sh2->macl)
- sh2->mach += 1;
+ m_sh2_state->mach += tempn;
+ if (templ > m_sh2_state->macl)
+ m_sh2_state->mach += 1;
}
- sh2->icount -= 2;
+ m_sh2_state->icount -= 2;
}
/* MOV Rm,Rn */
-INLINE void MOV(sh2_state *sh2, UINT32 m, UINT32 n)
+void sh2_device::MOV(UINT32 m, UINT32 n)
{
- sh2->r[n] = sh2->r[m];
+ m_sh2_state->r[n] = m_sh2_state->r[m];
}
/* MOV.B Rm,@Rn */
-INLINE void MOVBS(sh2_state *sh2, UINT32 m, UINT32 n)
+void sh2_device::MOVBS(UINT32 m, UINT32 n)
{
- sh2->ea = sh2->r[n];
- WB( sh2, sh2->ea, sh2->r[m] & 0x000000ff);
+ m_sh2_state->ea = m_sh2_state->r[n];
+ WB( m_sh2_state->ea, m_sh2_state->r[m] & 0x000000ff);
}
/* MOV.W Rm,@Rn */
-INLINE void MOVWS(sh2_state *sh2, UINT32 m, UINT32 n)
+void sh2_device::MOVWS(UINT32 m, UINT32 n)
{
- sh2->ea = sh2->r[n];
- WW( sh2, sh2->ea, sh2->r[m] & 0x0000ffff);
+ m_sh2_state->ea = m_sh2_state->r[n];
+ WW( m_sh2_state->ea, m_sh2_state->r[m] & 0x0000ffff);
}
/* MOV.L Rm,@Rn */
-INLINE void MOVLS(sh2_state *sh2, UINT32 m, UINT32 n)
+void sh2_device::MOVLS(UINT32 m, UINT32 n)
{
- sh2->ea = sh2->r[n];
- WL( sh2, sh2->ea, sh2->r[m] );
+ m_sh2_state->ea = m_sh2_state->r[n];
+ WL( m_sh2_state->ea, m_sh2_state->r[m] );
}
/* MOV.B @Rm,Rn */
-INLINE void MOVBL(sh2_state *sh2, UINT32 m, UINT32 n)
+void sh2_device::MOVBL(UINT32 m, UINT32 n)
{
- sh2->ea = sh2->r[m];
- sh2->r[n] = (UINT32)(INT32)(INT16)(INT8) RB( sh2, sh2->ea );
+ m_sh2_state->ea = m_sh2_state->r[m];
+ m_sh2_state->r[n] = (UINT32)(INT32)(INT16)(INT8) RB( m_sh2_state->ea );
}
/* MOV.W @Rm,Rn */
-INLINE void MOVWL(sh2_state *sh2, UINT32 m, UINT32 n)
+void sh2_device::MOVWL(UINT32 m, UINT32 n)
{
- sh2->ea = sh2->r[m];
- sh2->r[n] = (UINT32)(INT32)(INT16) RW( sh2, sh2->ea );
+ m_sh2_state->ea = m_sh2_state->r[m];
+ m_sh2_state->r[n] = (UINT32)(INT32)(INT16) RW( m_sh2_state->ea );
}
/* MOV.L @Rm,Rn */
-INLINE void MOVLL(sh2_state *sh2, UINT32 m, UINT32 n)
+void sh2_device::MOVLL(UINT32 m, UINT32 n)
{
- sh2->ea = sh2->r[m];
- sh2->r[n] = RL( sh2, sh2->ea );
+ m_sh2_state->ea = m_sh2_state->r[m];
+ m_sh2_state->r[n] = RL( m_sh2_state->ea );
}
/* MOV.B Rm,@-Rn */
-INLINE void MOVBM(sh2_state *sh2, UINT32 m, UINT32 n)
+void sh2_device::MOVBM(UINT32 m, UINT32 n)
{
- /* SMG : bug fix, was reading sh2->r[n] */
- UINT32 data = sh2->r[m] & 0x000000ff;
+ /* SMG : bug fix, was reading m_sh2_state->r[n] */
+ UINT32 data = m_sh2_state->r[m] & 0x000000ff;
- sh2->r[n] -= 1;
- WB( sh2, sh2->r[n], data );
+ m_sh2_state->r[n] -= 1;
+ WB( m_sh2_state->r[n], data );
}
/* MOV.W Rm,@-Rn */
-INLINE void MOVWM(sh2_state *sh2, UINT32 m, UINT32 n)
+void sh2_device::MOVWM(UINT32 m, UINT32 n)
{
- UINT32 data = sh2->r[m] & 0x0000ffff;
+ UINT32 data = m_sh2_state->r[m] & 0x0000ffff;
- sh2->r[n] -= 2;
- WW( sh2, sh2->r[n], data );
+ m_sh2_state->r[n] -= 2;
+ WW( m_sh2_state->r[n], data );
}
/* MOV.L Rm,@-Rn */
-INLINE void MOVLM(sh2_state *sh2, UINT32 m, UINT32 n)
+void sh2_device::MOVLM(UINT32 m, UINT32 n)
{
- UINT32 data = sh2->r[m];
+ UINT32 data = m_sh2_state->r[m];
- sh2->r[n] -= 4;
- WL( sh2, sh2->r[n], data );
+ m_sh2_state->r[n] -= 4;
+ WL( m_sh2_state->r[n], data );
}
/* MOV.B @Rm+,Rn */
-INLINE void MOVBP(sh2_state *sh2, UINT32 m, UINT32 n)
+void sh2_device::MOVBP(UINT32 m, UINT32 n)
{
- sh2->r[n] = (UINT32)(INT32)(INT16)(INT8) RB( sh2, sh2->r[m] );
+ m_sh2_state->r[n] = (UINT32)(INT32)(INT16)(INT8) RB( m_sh2_state->r[m] );
if (n != m)
- sh2->r[m] += 1;
+ m_sh2_state->r[m] += 1;
}
/* MOV.W @Rm+,Rn */
-INLINE void MOVWP(sh2_state *sh2, UINT32 m, UINT32 n)
+void sh2_device::MOVWP(UINT32 m, UINT32 n)
{
- sh2->r[n] = (UINT32)(INT32)(INT16) RW( sh2, sh2->r[m] );
+ m_sh2_state->r[n] = (UINT32)(INT32)(INT16) RW( m_sh2_state->r[m] );
if (n != m)
- sh2->r[m] += 2;
+ m_sh2_state->r[m] += 2;
}
/* MOV.L @Rm+,Rn */
-INLINE void MOVLP(sh2_state *sh2, UINT32 m, UINT32 n)
+void sh2_device::MOVLP(UINT32 m, UINT32 n)
{
- sh2->r[n] = RL( sh2, sh2->r[m] );
+ m_sh2_state->r[n] = RL( m_sh2_state->r[m] );
if (n != m)
- sh2->r[m] += 4;
+ m_sh2_state->r[m] += 4;
}
/* MOV.B Rm,@(R0,Rn) */
-INLINE void MOVBS0(sh2_state *sh2, UINT32 m, UINT32 n)
+void sh2_device::MOVBS0(UINT32 m, UINT32 n)
{
- sh2->ea = sh2->r[n] + sh2->r[0];
- WB( sh2, sh2->ea, sh2->r[m] & 0x000000ff );
+ m_sh2_state->ea = m_sh2_state->r[n] + m_sh2_state->r[0];
+ WB( m_sh2_state->ea, m_sh2_state->r[m] & 0x000000ff );
}
/* MOV.W Rm,@(R0,Rn) */
-INLINE void MOVWS0(sh2_state *sh2, UINT32 m, UINT32 n)
+void sh2_device::MOVWS0(UINT32 m, UINT32 n)
{
- sh2->ea = sh2->r[n] + sh2->r[0];
- WW( sh2, sh2->ea, sh2->r[m] & 0x0000ffff );
+ m_sh2_state->ea = m_sh2_state->r[n] + m_sh2_state->r[0];
+ WW( m_sh2_state->ea, m_sh2_state->r[m] & 0x0000ffff );
}
/* MOV.L Rm,@(R0,Rn) */
-INLINE void MOVLS0(sh2_state *sh2, UINT32 m, UINT32 n)
+void sh2_device::MOVLS0(UINT32 m, UINT32 n)
{
- sh2->ea = sh2->r[n] + sh2->r[0];
- WL( sh2, sh2->ea, sh2->r[m] );
+ m_sh2_state->ea = m_sh2_state->r[n] + m_sh2_state->r[0];
+ WL( m_sh2_state->ea, m_sh2_state->r[m] );
}
/* MOV.B @(R0,Rm),Rn */
-INLINE void MOVBL0(sh2_state *sh2, UINT32 m, UINT32 n)
+void sh2_device::MOVBL0(UINT32 m, UINT32 n)
{
- sh2->ea = sh2->r[m] + sh2->r[0];
- sh2->r[n] = (UINT32)(INT32)(INT16)(INT8) RB( sh2, sh2->ea );
+ m_sh2_state->ea = m_sh2_state->r[m] + m_sh2_state->r[0];
+ m_sh2_state->r[n] = (UINT32)(INT32)(INT16)(INT8) RB( m_sh2_state->ea );
}
/* MOV.W @(R0,Rm),Rn */
-INLINE void MOVWL0(sh2_state *sh2, UINT32 m, UINT32 n)
+void sh2_device::MOVWL0(UINT32 m, UINT32 n)
{
- sh2->ea = sh2->r[m] + sh2->r[0];
- sh2->r[n] = (UINT32)(INT32)(INT16) RW( sh2, sh2->ea );
+ m_sh2_state->ea = m_sh2_state->r[m] + m_sh2_state->r[0];
+ m_sh2_state->r[n] = (UINT32)(INT32)(INT16) RW( m_sh2_state->ea );
}
/* MOV.L @(R0,Rm),Rn */
-INLINE void MOVLL0(sh2_state *sh2, UINT32 m, UINT32 n)
+void sh2_device::MOVLL0(UINT32 m, UINT32 n)
{
- sh2->ea = sh2->r[m] + sh2->r[0];
- sh2->r[n] = RL( sh2, sh2->ea );
+ m_sh2_state->ea = m_sh2_state->r[m] + m_sh2_state->r[0];
+ m_sh2_state->r[n] = RL( m_sh2_state->ea );
}
/* MOV #imm,Rn */
-INLINE void MOVI(sh2_state *sh2, UINT32 i, UINT32 n)
+void sh2_device::MOVI(UINT32 i, UINT32 n)
{
- sh2->r[n] = (UINT32)(INT32)(INT16)(INT8) i;
+ m_sh2_state->r[n] = (UINT32)(INT32)(INT16)(INT8) i;
}
/* MOV.W @(disp8,PC),Rn */
-INLINE void MOVWI(sh2_state *sh2, UINT32 d, UINT32 n)
+void sh2_device::MOVWI(UINT32 d, UINT32 n)
{
UINT32 disp = d & 0xff;
- sh2->ea = sh2->pc + disp * 2 + 2;
- sh2->r[n] = (UINT32)(INT32)(INT16) RW( sh2, sh2->ea );
+ m_sh2_state->ea = m_sh2_state->pc + disp * 2 + 2;
+ m_sh2_state->r[n] = (UINT32)(INT32)(INT16) RW( m_sh2_state->ea );
}
/* MOV.L @(disp8,PC),Rn */
-INLINE void MOVLI(sh2_state *sh2, UINT32 d, UINT32 n)
+void sh2_device::MOVLI(UINT32 d, UINT32 n)
{
UINT32 disp = d & 0xff;
- sh2->ea = ((sh2->pc + 2) & ~3) + disp * 4;
- sh2->r[n] = RL( sh2, sh2->ea );
+ m_sh2_state->ea = ((m_sh2_state->pc + 2) & ~3) + disp * 4;
+ m_sh2_state->r[n] = RL( m_sh2_state->ea );
}
/* MOV.B @(disp8,GBR),R0 */
-INLINE void MOVBLG(sh2_state *sh2, UINT32 d)
+void sh2_device::MOVBLG(UINT32 d)
{
UINT32 disp = d & 0xff;
- sh2->ea = sh2->gbr + disp;
- sh2->r[0] = (UINT32)(INT32)(INT16)(INT8) RB( sh2, sh2->ea );
+ m_sh2_state->ea = m_sh2_state->gbr + disp;
+ m_sh2_state->r[0] = (UINT32)(INT32)(INT16)(INT8) RB( m_sh2_state->ea );
}
/* MOV.W @(disp8,GBR),R0 */
-INLINE void MOVWLG(sh2_state *sh2, UINT32 d)
+void sh2_device::MOVWLG(UINT32 d)
{
UINT32 disp = d & 0xff;
- sh2->ea = sh2->gbr + disp * 2;
- sh2->r[0] = (INT32)(INT16) RW( sh2, sh2->ea );
+ m_sh2_state->ea = m_sh2_state->gbr + disp * 2;
+ m_sh2_state->r[0] = (INT32)(INT16) RW( m_sh2_state->ea );
}
/* MOV.L @(disp8,GBR),R0 */
-INLINE void MOVLLG(sh2_state *sh2, UINT32 d)
+void sh2_device::MOVLLG(UINT32 d)
{
UINT32 disp = d & 0xff;
- sh2->ea = sh2->gbr + disp * 4;
- sh2->r[0] = RL( sh2, sh2->ea );
+ m_sh2_state->ea = m_sh2_state->gbr + disp * 4;
+ m_sh2_state->r[0] = RL( m_sh2_state->ea );
}
/* MOV.B R0,@(disp8,GBR) */
-INLINE void MOVBSG(sh2_state *sh2, UINT32 d)
+void sh2_device::MOVBSG(UINT32 d)
{
UINT32 disp = d & 0xff;
- sh2->ea = sh2->gbr + disp;
- WB( sh2, sh2->ea, sh2->r[0] & 0x000000ff );
+ m_sh2_state->ea = m_sh2_state->gbr + disp;
+ WB( m_sh2_state->ea, m_sh2_state->r[0] & 0x000000ff );
}
/* MOV.W R0,@(disp8,GBR) */
-INLINE void MOVWSG(sh2_state *sh2, UINT32 d)
+void sh2_device::MOVWSG(UINT32 d)
{
UINT32 disp = d & 0xff;
- sh2->ea = sh2->gbr + disp * 2;
- WW( sh2, sh2->ea, sh2->r[0] & 0x0000ffff );
+ m_sh2_state->ea = m_sh2_state->gbr + disp * 2;
+ WW( m_sh2_state->ea, m_sh2_state->r[0] & 0x0000ffff );
}
/* MOV.L R0,@(disp8,GBR) */
-INLINE void MOVLSG(sh2_state *sh2, UINT32 d)
+void sh2_device::MOVLSG(UINT32 d)
{
UINT32 disp = d & 0xff;
- sh2->ea = sh2->gbr + disp * 4;
- WL( sh2, sh2->ea, sh2->r[0] );
+ m_sh2_state->ea = m_sh2_state->gbr + disp * 4;
+ WL( m_sh2_state->ea, m_sh2_state->r[0] );
}
/* MOV.B R0,@(disp4,Rn) */
-INLINE void MOVBS4(sh2_state *sh2, UINT32 d, UINT32 n)
+void sh2_device::MOVBS4(UINT32 d, UINT32 n)
{
UINT32 disp = d & 0x0f;
- sh2->ea = sh2->r[n] + disp;
- WB( sh2, sh2->ea, sh2->r[0] & 0x000000ff );
+ m_sh2_state->ea = m_sh2_state->r[n] + disp;
+ WB( m_sh2_state->ea, m_sh2_state->r[0] & 0x000000ff );
}
/* MOV.W R0,@(disp4,Rn) */
-INLINE void MOVWS4(sh2_state *sh2, UINT32 d, UINT32 n)
+void sh2_device::MOVWS4(UINT32 d, UINT32 n)
{
UINT32 disp = d & 0x0f;
- sh2->ea = sh2->r[n] + disp * 2;
- WW( sh2, sh2->ea, sh2->r[0] & 0x0000ffff );
+ m_sh2_state->ea = m_sh2_state->r[n] + disp * 2;
+ WW( m_sh2_state->ea, m_sh2_state->r[0] & 0x0000ffff );
}
/* MOV.L Rm,@(disp4,Rn) */
-INLINE void MOVLS4(sh2_state *sh2, UINT32 m, UINT32 d, UINT32 n)
+void sh2_device::MOVLS4(UINT32 m, UINT32 d, UINT32 n)
{
UINT32 disp = d & 0x0f;
- sh2->ea = sh2->r[n] + disp * 4;
- WL( sh2, sh2->ea, sh2->r[m] );
+ m_sh2_state->ea = m_sh2_state->r[n] + disp * 4;
+ WL( m_sh2_state->ea, m_sh2_state->r[m] );
}
/* MOV.B @(disp4,Rm),R0 */
-INLINE void MOVBL4(sh2_state *sh2, UINT32 m, UINT32 d)
+void sh2_device::MOVBL4(UINT32 m, UINT32 d)
{
UINT32 disp = d & 0x0f;
- sh2->ea = sh2->r[m] + disp;
- sh2->r[0] = (UINT32)(INT32)(INT16)(INT8) RB( sh2, sh2->ea );
+ m_sh2_state->ea = m_sh2_state->r[m] + disp;
+ m_sh2_state->r[0] = (UINT32)(INT32)(INT16)(INT8) RB( m_sh2_state->ea );
}
/* MOV.W @(disp4,Rm),R0 */
-INLINE void MOVWL4(sh2_state *sh2, UINT32 m, UINT32 d)
+void sh2_device::MOVWL4(UINT32 m, UINT32 d)
{
UINT32 disp = d & 0x0f;
- sh2->ea = sh2->r[m] + disp * 2;
- sh2->r[0] = (UINT32)(INT32)(INT16) RW( sh2, sh2->ea );
+ m_sh2_state->ea = m_sh2_state->r[m] + disp * 2;
+ m_sh2_state->r[0] = (UINT32)(INT32)(INT16) RW( m_sh2_state->ea );
}
/* MOV.L @(disp4,Rm),Rn */
-INLINE void MOVLL4(sh2_state *sh2, UINT32 m, UINT32 d, UINT32 n)
+void sh2_device::MOVLL4(UINT32 m, UINT32 d, UINT32 n)
{
UINT32 disp = d & 0x0f;
- sh2->ea = sh2->r[m] + disp * 4;
- sh2->r[n] = RL( sh2, sh2->ea );
+ m_sh2_state->ea = m_sh2_state->r[m] + disp * 4;
+ m_sh2_state->r[n] = RL( m_sh2_state->ea );
}
/* MOVA @(disp8,PC),R0 */
-INLINE void MOVA(sh2_state *sh2, UINT32 d)
+void sh2_device::MOVA(UINT32 d)
{
UINT32 disp = d & 0xff;
- sh2->ea = ((sh2->pc + 2) & ~3) + disp * 4;
- sh2->r[0] = sh2->ea;
+ m_sh2_state->ea = ((m_sh2_state->pc + 2) & ~3) + disp * 4;
+ m_sh2_state->r[0] = m_sh2_state->ea;
}
/* MOVT Rn */
-INLINE void MOVT(sh2_state *sh2, UINT32 n)
+void sh2_device::MOVT(UINT32 n)
{
- sh2->r[n] = sh2->sr & T;
+ m_sh2_state->r[n] = m_sh2_state->sr & T;
}
/* MUL.L Rm,Rn */
-INLINE void MULL(sh2_state *sh2, UINT32 m, UINT32 n)
+void sh2_device::MULL(UINT32 m, UINT32 n)
{
- sh2->macl = sh2->r[n] * sh2->r[m];
- sh2->icount--;
+ m_sh2_state->macl = m_sh2_state->r[n] * m_sh2_state->r[m];
+ m_sh2_state->icount--;
}
/* MULS Rm,Rn */
-INLINE void MULS(sh2_state *sh2, UINT32 m, UINT32 n)
+void sh2_device::MULS(UINT32 m, UINT32 n)
{
- sh2->macl = (INT16) sh2->r[n] * (INT16) sh2->r[m];
+ m_sh2_state->macl = (INT16) m_sh2_state->r[n] * (INT16) m_sh2_state->r[m];
}
/* MULU Rm,Rn */
-INLINE void MULU(sh2_state *sh2, UINT32 m, UINT32 n)
+void sh2_device::MULU(UINT32 m, UINT32 n)
{
- sh2->macl = (UINT16) sh2->r[n] * (UINT16) sh2->r[m];
+ m_sh2_state->macl = (UINT16) m_sh2_state->r[n] * (UINT16) m_sh2_state->r[m];
}
/* NEG Rm,Rn */
-INLINE void NEG(sh2_state *sh2, UINT32 m, UINT32 n)
+void sh2_device::NEG(UINT32 m, UINT32 n)
{
- sh2->r[n] = 0 - sh2->r[m];
+ m_sh2_state->r[n] = 0 - m_sh2_state->r[m];
}
/* NEGC Rm,Rn */
-INLINE void NEGC(sh2_state *sh2, UINT32 m, UINT32 n)
+void sh2_device::NEGC(UINT32 m, UINT32 n)
{
UINT32 temp;
- temp = sh2->r[m];
- sh2->r[n] = -temp - (sh2->sr & T);
- if (temp || (sh2->sr & T))
- sh2->sr |= T;
+ temp = m_sh2_state->r[m];
+ m_sh2_state->r[n] = -temp - (m_sh2_state->sr & T);
+ if (temp || (m_sh2_state->sr & T))
+ m_sh2_state->sr |= T;
else
- sh2->sr &= ~T;
+ m_sh2_state->sr &= ~T;
}
/* NOP */
-INLINE void NOP(void)
+void sh2_device::NOP(void)
{
}
/* NOT Rm,Rn */
-INLINE void NOT(sh2_state *sh2, UINT32 m, UINT32 n)
+void sh2_device::NOT(UINT32 m, UINT32 n)
{
- sh2->r[n] = ~sh2->r[m];
+ m_sh2_state->r[n] = ~m_sh2_state->r[m];
}
/* OR Rm,Rn */
-INLINE void OR(sh2_state *sh2, UINT32 m, UINT32 n)
+void sh2_device::OR(UINT32 m, UINT32 n)
{
- sh2->r[n] |= sh2->r[m];
+ m_sh2_state->r[n] |= m_sh2_state->r[m];
}
/* OR #imm,R0 */
-INLINE void ORI(sh2_state *sh2, UINT32 i)
+void sh2_device::ORI(UINT32 i)
{
- sh2->r[0] |= i;
+ m_sh2_state->r[0] |= i;
}
/* OR.B #imm,@(R0,GBR) */
-INLINE void ORM(sh2_state *sh2, UINT32 i)
+void sh2_device::ORM(UINT32 i)
{
UINT32 temp;
- sh2->ea = sh2->gbr + sh2->r[0];
- temp = RB( sh2, sh2->ea );
+ m_sh2_state->ea = m_sh2_state->gbr + m_sh2_state->r[0];
+ temp = RB( m_sh2_state->ea );
temp |= i;
- WB( sh2, sh2->ea, temp );
- sh2->icount -= 2;
+ WB( m_sh2_state->ea, temp );
+ m_sh2_state->icount -= 2;
}
/* ROTCL Rn */
-INLINE void ROTCL(sh2_state *sh2, UINT32 n)
+void sh2_device::ROTCL(UINT32 n)
{
UINT32 temp;
- temp = (sh2->r[n] >> 31) & T;
- sh2->r[n] = (sh2->r[n] << 1) | (sh2->sr & T);
- sh2->sr = (sh2->sr & ~T) | temp;
+ temp = (m_sh2_state->r[n] >> 31) & T;
+ m_sh2_state->r[n] = (m_sh2_state->r[n] << 1) | (m_sh2_state->sr & T);
+ m_sh2_state->sr = (m_sh2_state->sr & ~T) | temp;
}
/* ROTCR Rn */
-INLINE void ROTCR(sh2_state *sh2, UINT32 n)
+void sh2_device::ROTCR(UINT32 n)
{
UINT32 temp;
- temp = (sh2->sr & T) << 31;
- if (sh2->r[n] & T)
- sh2->sr |= T;
+ temp = (m_sh2_state->sr & T) << 31;
+ if (m_sh2_state->r[n] & T)
+ m_sh2_state->sr |= T;
else
- sh2->sr &= ~T;
- sh2->r[n] = (sh2->r[n] >> 1) | temp;
+ m_sh2_state->sr &= ~T;
+ m_sh2_state->r[n] = (m_sh2_state->r[n] >> 1) | temp;
}
/* ROTL Rn */
-INLINE void ROTL(sh2_state *sh2, UINT32 n)
+void sh2_device::ROTL(UINT32 n)
{
- sh2->sr = (sh2->sr & ~T) | ((sh2->r[n] >> 31) & T);
- sh2->r[n] = (sh2->r[n] << 1) | (sh2->r[n] >> 31);
+ m_sh2_state->sr = (m_sh2_state->sr & ~T) | ((m_sh2_state->r[n] >> 31) & T);
+ m_sh2_state->r[n] = (m_sh2_state->r[n] << 1) | (m_sh2_state->r[n] >> 31);
}
/* ROTR Rn */
-INLINE void ROTR(sh2_state *sh2, UINT32 n)
+void sh2_device::ROTR(UINT32 n)
{
- sh2->sr = (sh2->sr & ~T) | (sh2->r[n] & T);
- sh2->r[n] = (sh2->r[n] >> 1) | (sh2->r[n] << 31);
+ m_sh2_state->sr = (m_sh2_state->sr & ~T) | (m_sh2_state->r[n] & T);
+ m_sh2_state->r[n] = (m_sh2_state->r[n] >> 1) | (m_sh2_state->r[n] << 31);
}
/* RTE */
-INLINE void RTE(sh2_state *sh2)
+void sh2_device::RTE()
{
- sh2->ea = sh2->r[15];
- sh2->delay = sh2->pc;
- sh2->pc = RL( sh2, sh2->ea );
- sh2->r[15] += 4;
- sh2->ea = sh2->r[15];
- sh2->sr = RL( sh2, sh2->ea ) & FLAGS;
- sh2->r[15] += 4;
- sh2->icount -= 3;
- sh2->test_irq = 1;
+ m_sh2_state->ea = m_sh2_state->r[15];
+ m_delay = m_sh2_state->pc;
+ m_sh2_state->pc = RL( m_sh2_state->ea );
+ m_sh2_state->r[15] += 4;
+ m_sh2_state->ea = m_sh2_state->r[15];
+ m_sh2_state->sr = RL( m_sh2_state->ea ) & FLAGS;
+ m_sh2_state->r[15] += 4;
+ m_sh2_state->icount -= 3;
+ m_test_irq = 1;
}
/* RTS */
-INLINE void RTS(sh2_state *sh2)
+void sh2_device::RTS()
{
- sh2->delay = sh2->pc;
- sh2->pc = sh2->ea = sh2->pr;
- sh2->icount--;
+ m_delay = m_sh2_state->pc;
+ m_sh2_state->pc = m_sh2_state->ea = m_sh2_state->pr;
+ m_sh2_state->icount--;
}
/* SETT */
-INLINE void SETT(sh2_state *sh2)
+void sh2_device::SETT()
{
- sh2->sr |= T;
+ m_sh2_state->sr |= T;
}
/* SHAL Rn (same as SHLL) */
-INLINE void SHAL(sh2_state *sh2, UINT32 n)
+void sh2_device::SHAL(UINT32 n)
{
- sh2->sr = (sh2->sr & ~T) | ((sh2->r[n] >> 31) & T);
- sh2->r[n] <<= 1;
+ m_sh2_state->sr = (m_sh2_state->sr & ~T) | ((m_sh2_state->r[n] >> 31) & T);
+ m_sh2_state->r[n] <<= 1;
}
/* SHAR Rn */
-INLINE void SHAR(sh2_state *sh2, UINT32 n)
+void sh2_device::SHAR(UINT32 n)
{
- sh2->sr = (sh2->sr & ~T) | (sh2->r[n] & T);
- sh2->r[n] = (UINT32)((INT32)sh2->r[n] >> 1);
+ m_sh2_state->sr = (m_sh2_state->sr & ~T) | (m_sh2_state->r[n] & T);
+ m_sh2_state->r[n] = (UINT32)((INT32)m_sh2_state->r[n] >> 1);
}
/* SHLL Rn (same as SHAL) */
-INLINE void SHLL(sh2_state *sh2, UINT32 n)
+void sh2_device::SHLL(UINT32 n)
{
- sh2->sr = (sh2->sr & ~T) | ((sh2->r[n] >> 31) & T);
- sh2->r[n] <<= 1;
+ m_sh2_state->sr = (m_sh2_state->sr & ~T) | ((m_sh2_state->r[n] >> 31) & T);
+ m_sh2_state->r[n] <<= 1;
}
/* SHLL2 Rn */
-INLINE void SHLL2(sh2_state *sh2, UINT32 n)
+void sh2_device::SHLL2(UINT32 n)
{
- sh2->r[n] <<= 2;
+ m_sh2_state->r[n] <<= 2;
}
/* SHLL8 Rn */
-INLINE void SHLL8(sh2_state *sh2, UINT32 n)
+void sh2_device::SHLL8(UINT32 n)
{
- sh2->r[n] <<= 8;
+ m_sh2_state->r[n] <<= 8;
}
/* SHLL16 Rn */
-INLINE void SHLL16(sh2_state *sh2, UINT32 n)
+void sh2_device::SHLL16(UINT32 n)
{
- sh2->r[n] <<= 16;
+ m_sh2_state->r[n] <<= 16;
}
/* SHLR Rn */
-INLINE void SHLR(sh2_state *sh2, UINT32 n)
+void sh2_device::SHLR(UINT32 n)
{
- sh2->sr = (sh2->sr & ~T) | (sh2->r[n] & T);
- sh2->r[n] >>= 1;
+ m_sh2_state->sr = (m_sh2_state->sr & ~T) | (m_sh2_state->r[n] & T);
+ m_sh2_state->r[n] >>= 1;
}
/* SHLR2 Rn */
-INLINE void SHLR2(sh2_state *sh2, UINT32 n)
+void sh2_device::SHLR2(UINT32 n)
{
- sh2->r[n] >>= 2;
+ m_sh2_state->r[n] >>= 2;
}
/* SHLR8 Rn */
-INLINE void SHLR8(sh2_state *sh2, UINT32 n)
+void sh2_device::SHLR8(UINT32 n)
{
- sh2->r[n] >>= 8;
+ m_sh2_state->r[n] >>= 8;
}
/* SHLR16 Rn */
-INLINE void SHLR16(sh2_state *sh2, UINT32 n)
+void sh2_device::SHLR16(UINT32 n)
{
- sh2->r[n] >>= 16;
+ m_sh2_state->r[n] >>= 16;
}
/* SLEEP */
-INLINE void SLEEP(sh2_state *sh2)
+void sh2_device::SLEEP()
{
- if(sh2->sleep_mode != 2)
- sh2->pc -= 2;
- sh2->icount -= 2;
+ if(m_sh2_state->sleep_mode != 2)
+ m_sh2_state->pc -= 2;
+ m_sh2_state->icount -= 2;
/* Wait_for_exception; */
- if(sh2->sleep_mode == 0)
- sh2->sleep_mode = 1;
- else if(sh2->sleep_mode == 2)
- sh2->sleep_mode = 0;
+ if(m_sh2_state->sleep_mode == 0)
+ m_sh2_state->sleep_mode = 1;
+ else if(m_sh2_state->sleep_mode == 2)
+ m_sh2_state->sleep_mode = 0;
}
/* STC SR,Rn */
-INLINE void STCSR(sh2_state *sh2, UINT32 n)
+void sh2_device::STCSR(UINT32 n)
{
- sh2->r[n] = sh2->sr;
+ m_sh2_state->r[n] = m_sh2_state->sr;
}
/* STC GBR,Rn */
-INLINE void STCGBR(sh2_state *sh2, UINT32 n)
+void sh2_device::STCGBR(UINT32 n)
{
- sh2->r[n] = sh2->gbr;
+ m_sh2_state->r[n] = m_sh2_state->gbr;
}
/* STC VBR,Rn */
-INLINE void STCVBR(sh2_state *sh2, UINT32 n)
+void sh2_device::STCVBR(UINT32 n)
{
- sh2->r[n] = sh2->vbr;
+ m_sh2_state->r[n] = m_sh2_state->vbr;
}
/* STC.L SR,@-Rn */
-INLINE void STCMSR(sh2_state *sh2, UINT32 n)
+void sh2_device::STCMSR(UINT32 n)
{
- sh2->r[n] -= 4;
- sh2->ea = sh2->r[n];
- WL( sh2, sh2->ea, sh2->sr );
- sh2->icount--;
+ m_sh2_state->r[n] -= 4;
+ m_sh2_state->ea = m_sh2_state->r[n];
+ WL( m_sh2_state->ea, m_sh2_state->sr );
+ m_sh2_state->icount--;
}
/* STC.L GBR,@-Rn */
-INLINE void STCMGBR(sh2_state *sh2, UINT32 n)
+void sh2_device::STCMGBR(UINT32 n)
{
- sh2->r[n] -= 4;
- sh2->ea = sh2->r[n];
- WL( sh2, sh2->ea, sh2->gbr );
- sh2->icount--;
+ m_sh2_state->r[n] -= 4;
+ m_sh2_state->ea = m_sh2_state->r[n];
+ WL( m_sh2_state->ea, m_sh2_state->gbr );
+ m_sh2_state->icount--;
}
/* STC.L VBR,@-Rn */
-INLINE void STCMVBR(sh2_state *sh2, UINT32 n)
+void sh2_device::STCMVBR(UINT32 n)
{
- sh2->r[n] -= 4;
- sh2->ea = sh2->r[n];
- WL( sh2, sh2->ea, sh2->vbr );
- sh2->icount--;
+ m_sh2_state->r[n] -= 4;
+ m_sh2_state->ea = m_sh2_state->r[n];
+ WL( m_sh2_state->ea, m_sh2_state->vbr );
+ m_sh2_state->icount--;
}
/* STS MACH,Rn */
-INLINE void STSMACH(sh2_state *sh2, UINT32 n)
+void sh2_device::STSMACH(UINT32 n)
{
- sh2->r[n] = sh2->mach;
+ m_sh2_state->r[n] = m_sh2_state->mach;
}
/* STS MACL,Rn */
-INLINE void STSMACL(sh2_state *sh2, UINT32 n)
+void sh2_device::STSMACL(UINT32 n)
{
- sh2->r[n] = sh2->macl;
+ m_sh2_state->r[n] = m_sh2_state->macl;
}
/* STS PR,Rn */
-INLINE void STSPR(sh2_state *sh2, UINT32 n)
+void sh2_device::STSPR(UINT32 n)
{
- sh2->r[n] = sh2->pr;
+ m_sh2_state->r[n] = m_sh2_state->pr;
}
/* STS.L MACH,@-Rn */
-INLINE void STSMMACH(sh2_state *sh2, UINT32 n)
+void sh2_device::STSMMACH(UINT32 n)
{
- sh2->r[n] -= 4;
- sh2->ea = sh2->r[n];
- WL( sh2, sh2->ea, sh2->mach );
+ m_sh2_state->r[n] -= 4;
+ m_sh2_state->ea = m_sh2_state->r[n];
+ WL( m_sh2_state->ea, m_sh2_state->mach );
}
/* STS.L MACL,@-Rn */
-INLINE void STSMMACL(sh2_state *sh2, UINT32 n)
+void sh2_device::STSMMACL(UINT32 n)
{
- sh2->r[n] -= 4;
- sh2->ea = sh2->r[n];
- WL( sh2, sh2->ea, sh2->macl );
+ m_sh2_state->r[n] -= 4;
+ m_sh2_state->ea = m_sh2_state->r[n];
+ WL( m_sh2_state->ea, m_sh2_state->macl );
}
/* STS.L PR,@-Rn */
-INLINE void STSMPR(sh2_state *sh2, UINT32 n)
+void sh2_device::STSMPR(UINT32 n)
{
- sh2->r[n] -= 4;
- sh2->ea = sh2->r[n];
- WL( sh2, sh2->ea, sh2->pr );
+ m_sh2_state->r[n] -= 4;
+ m_sh2_state->ea = m_sh2_state->r[n];
+ WL( m_sh2_state->ea, m_sh2_state->pr );
}
/* SUB Rm,Rn */
-INLINE void SUB(sh2_state *sh2, UINT32 m, UINT32 n)
+void sh2_device::SUB(UINT32 m, UINT32 n)
{
- sh2->r[n] -= sh2->r[m];
+ m_sh2_state->r[n] -= m_sh2_state->r[m];
}
/* SUBC Rm,Rn */
-INLINE void SUBC(sh2_state *sh2, UINT32 m, UINT32 n)
+void sh2_device::SUBC(UINT32 m, UINT32 n)
{
UINT32 tmp0, tmp1;
- tmp1 = sh2->r[n] - sh2->r[m];
- tmp0 = sh2->r[n];
- sh2->r[n] = tmp1 - (sh2->sr & T);
+ tmp1 = m_sh2_state->r[n] - m_sh2_state->r[m];
+ tmp0 = m_sh2_state->r[n];
+ m_sh2_state->r[n] = tmp1 - (m_sh2_state->sr & T);
if (tmp0 < tmp1)
- sh2->sr |= T;
+ m_sh2_state->sr |= T;
else
- sh2->sr &= ~T;
- if (tmp1 < sh2->r[n])
- sh2->sr |= T;
+ m_sh2_state->sr &= ~T;
+ if (tmp1 < m_sh2_state->r[n])
+ m_sh2_state->sr |= T;
}
/* SUBV Rm,Rn */
-INLINE void SUBV(sh2_state *sh2, UINT32 m, UINT32 n)
+void sh2_device::SUBV(UINT32 m, UINT32 n)
{
INT32 dest, src, ans;
- if ((INT32) sh2->r[n] >= 0)
+ if ((INT32) m_sh2_state->r[n] >= 0)
dest = 0;
else
dest = 1;
- if ((INT32) sh2->r[m] >= 0)
+ if ((INT32) m_sh2_state->r[m] >= 0)
src = 0;
else
src = 1;
src += dest;
- sh2->r[n] -= sh2->r[m];
- if ((INT32) sh2->r[n] >= 0)
+ m_sh2_state->r[n] -= m_sh2_state->r[m];
+ if ((INT32) m_sh2_state->r[n] >= 0)
ans = 0;
else
ans = 1;
@@ -1715,534 +1853,509 @@ INLINE void SUBV(sh2_state *sh2, UINT32 m, UINT32 n)
if (src == 1)
{
if (ans == 1)
- sh2->sr |= T;
+ m_sh2_state->sr |= T;
else
- sh2->sr &= ~T;
+ m_sh2_state->sr &= ~T;
}
else
- sh2->sr &= ~T;
+ m_sh2_state->sr &= ~T;
}
/* SWAP.B Rm,Rn */
-INLINE void SWAPB(sh2_state *sh2, UINT32 m, UINT32 n)
+void sh2_device::SWAPB(UINT32 m, UINT32 n)
{
UINT32 temp0, temp1;
- temp0 = sh2->r[m] & 0xffff0000;
- temp1 = (sh2->r[m] & 0x000000ff) << 8;
- sh2->r[n] = (sh2->r[m] >> 8) & 0x000000ff;
- sh2->r[n] = sh2->r[n] | temp1 | temp0;
+ temp0 = m_sh2_state->r[m] & 0xffff0000;
+ temp1 = (m_sh2_state->r[m] & 0x000000ff) << 8;
+ m_sh2_state->r[n] = (m_sh2_state->r[m] >> 8) & 0x000000ff;
+ m_sh2_state->r[n] = m_sh2_state->r[n] | temp1 | temp0;
}
/* SWAP.W Rm,Rn */
-INLINE void SWAPW(sh2_state *sh2, UINT32 m, UINT32 n)
+void sh2_device::SWAPW(UINT32 m, UINT32 n)
{
UINT32 temp;
- temp = (sh2->r[m] >> 16) & 0x0000ffff;
- sh2->r[n] = (sh2->r[m] << 16) | temp;
+ temp = (m_sh2_state->r[m] >> 16) & 0x0000ffff;
+ m_sh2_state->r[n] = (m_sh2_state->r[m] << 16) | temp;
}
/* TAS.B @Rn */
-INLINE void TAS(sh2_state *sh2, UINT32 n)
+void sh2_device::TAS(UINT32 n)
{
UINT32 temp;
- sh2->ea = sh2->r[n];
+ m_sh2_state->ea = m_sh2_state->r[n];
/* Bus Lock enable */
- temp = RB( sh2, sh2->ea );
+ temp = RB( m_sh2_state->ea );
if (temp == 0)
- sh2->sr |= T;
+ m_sh2_state->sr |= T;
else
- sh2->sr &= ~T;
+ m_sh2_state->sr &= ~T;
temp |= 0x80;
/* Bus Lock disable */
- WB( sh2, sh2->ea, temp );
- sh2->icount -= 3;
+ WB( m_sh2_state->ea, temp );
+ m_sh2_state->icount -= 3;
}
/* TRAPA #imm */
-INLINE void TRAPA(sh2_state *sh2, UINT32 i)
+void sh2_device::TRAPA(UINT32 i)
{
UINT32 imm = i & 0xff;
- sh2->ea = sh2->vbr + imm * 4;
+ m_sh2_state->ea = m_sh2_state->vbr + imm * 4;
- sh2->r[15] -= 4;
- WL( sh2, sh2->r[15], sh2->sr );
- sh2->r[15] -= 4;
- WL( sh2, sh2->r[15], sh2->pc );
+ m_sh2_state->r[15] -= 4;
+ WL( m_sh2_state->r[15], m_sh2_state->sr );
+ m_sh2_state->r[15] -= 4;
+ WL( m_sh2_state->r[15], m_sh2_state->pc );
- sh2->pc = RL( sh2, sh2->ea );
+ m_sh2_state->pc = RL( m_sh2_state->ea );
- sh2->icount -= 7;
+ m_sh2_state->icount -= 7;
}
/* TST Rm,Rn */
-INLINE void TST(sh2_state *sh2, UINT32 m, UINT32 n)
+void sh2_device::TST(UINT32 m, UINT32 n)
{
- if ((sh2->r[n] & sh2->r[m]) == 0)
- sh2->sr |= T;
+ if ((m_sh2_state->r[n] & m_sh2_state->r[m]) == 0)
+ m_sh2_state->sr |= T;
else
- sh2->sr &= ~T;
+ m_sh2_state->sr &= ~T;
}
/* TST #imm,R0 */
-INLINE void TSTI(sh2_state *sh2, UINT32 i)
+void sh2_device::TSTI(UINT32 i)
{
UINT32 imm = i & 0xff;
- if ((imm & sh2->r[0]) == 0)
- sh2->sr |= T;
+ if ((imm & m_sh2_state->r[0]) == 0)
+ m_sh2_state->sr |= T;
else
- sh2->sr &= ~T;
+ m_sh2_state->sr &= ~T;
}
/* TST.B #imm,@(R0,GBR) */
-INLINE void TSTM(sh2_state *sh2, UINT32 i)
+void sh2_device::TSTM(UINT32 i)
{
UINT32 imm = i & 0xff;
- sh2->ea = sh2->gbr + sh2->r[0];
- if ((imm & RB( sh2, sh2->ea )) == 0)
- sh2->sr |= T;
+ m_sh2_state->ea = m_sh2_state->gbr + m_sh2_state->r[0];
+ if ((imm & RB( m_sh2_state->ea )) == 0)
+ m_sh2_state->sr |= T;
else
- sh2->sr &= ~T;
- sh2->icount -= 2;
+ m_sh2_state->sr &= ~T;
+ m_sh2_state->icount -= 2;
}
/* XOR Rm,Rn */
-INLINE void XOR(sh2_state *sh2, UINT32 m, UINT32 n)
+void sh2_device::XOR(UINT32 m, UINT32 n)
{
- sh2->r[n] ^= sh2->r[m];
+ m_sh2_state->r[n] ^= m_sh2_state->r[m];
}
/* XOR #imm,R0 */
-INLINE void XORI(sh2_state *sh2, UINT32 i)
+void sh2_device::XORI(UINT32 i)
{
UINT32 imm = i & 0xff;
- sh2->r[0] ^= imm;
+ m_sh2_state->r[0] ^= imm;
}
/* XOR.B #imm,@(R0,GBR) */
-INLINE void XORM(sh2_state *sh2, UINT32 i)
+void sh2_device::XORM(UINT32 i)
{
UINT32 imm = i & 0xff;
UINT32 temp;
- sh2->ea = sh2->gbr + sh2->r[0];
- temp = RB( sh2, sh2->ea );
+ m_sh2_state->ea = m_sh2_state->gbr + m_sh2_state->r[0];
+ temp = RB( m_sh2_state->ea );
temp ^= imm;
- WB( sh2, sh2->ea, temp );
- sh2->icount -= 2;
+ WB( m_sh2_state->ea, temp );
+ m_sh2_state->icount -= 2;
}
/* XTRCT Rm,Rn */
-INLINE void XTRCT(sh2_state *sh2, UINT32 m, UINT32 n)
+void sh2_device::XTRCT(UINT32 m, UINT32 n)
{
UINT32 temp;
- temp = (sh2->r[m] << 16) & 0xffff0000;
- sh2->r[n] = (sh2->r[n] >> 16) & 0x0000ffff;
- sh2->r[n] |= temp;
+ temp = (m_sh2_state->r[m] << 16) & 0xffff0000;
+ m_sh2_state->r[n] = (m_sh2_state->r[n] >> 16) & 0x0000ffff;
+ m_sh2_state->r[n] |= temp;
}
/*****************************************************************************
* OPCODE DISPATCHERS
*****************************************************************************/
-INLINE void op0000(sh2_state *sh2, UINT16 opcode)
+void sh2_device::op0000(UINT16 opcode)
{
switch (opcode & 0x3F)
{
- case 0x00: ILLEGAL(sh2); break;
- case 0x01: ILLEGAL(sh2); break;
- case 0x02: STCSR(sh2, Rn); break;
- case 0x03: BSRF(sh2, Rn); break;
- case 0x04: MOVBS0(sh2, Rm, Rn); break;
- case 0x05: MOVWS0(sh2, Rm, Rn); break;
- case 0x06: MOVLS0(sh2, Rm, Rn); break;
- case 0x07: MULL(sh2, Rm, Rn); break;
- case 0x08: CLRT(sh2); break;
+ case 0x00: ILLEGAL(); break;
+ case 0x01: ILLEGAL(); break;
+ case 0x02: STCSR(Rn); break;
+ case 0x03: BSRF(Rn); break;
+ case 0x04: MOVBS0(Rm, Rn); break;
+ case 0x05: MOVWS0(Rm, Rn); break;
+ case 0x06: MOVLS0(Rm, Rn); break;
+ case 0x07: MULL(Rm, Rn); break;
+ case 0x08: CLRT(); break;
case 0x09: NOP(); break;
- case 0x0a: STSMACH(sh2, Rn); break;
- case 0x0b: RTS(sh2); break;
- case 0x0c: MOVBL0(sh2, Rm, Rn); break;
- case 0x0d: MOVWL0(sh2, Rm, Rn); break;
- case 0x0e: MOVLL0(sh2, Rm, Rn); break;
- case 0x0f: MAC_L(sh2, Rm, Rn); break;
-
- case 0x10: ILLEGAL(sh2); break;
- case 0x11: ILLEGAL(sh2); break;
- case 0x12: STCGBR(sh2, Rn); break;
- case 0x13: ILLEGAL(sh2); break;
- case 0x14: MOVBS0(sh2, Rm, Rn); break;
- case 0x15: MOVWS0(sh2, Rm, Rn); break;
- case 0x16: MOVLS0(sh2, Rm, Rn); break;
- case 0x17: MULL(sh2, Rm, Rn); break;
- case 0x18: SETT(sh2); break;
- case 0x19: DIV0U(sh2); break;
- case 0x1a: STSMACL(sh2, Rn); break;
- case 0x1b: SLEEP(sh2); break;
- case 0x1c: MOVBL0(sh2, Rm, Rn); break;
- case 0x1d: MOVWL0(sh2, Rm, Rn); break;
- case 0x1e: MOVLL0(sh2, Rm, Rn); break;
- case 0x1f: MAC_L(sh2, Rm, Rn); break;
-
- case 0x20: ILLEGAL(sh2); break;
- case 0x21: ILLEGAL(sh2); break;
- case 0x22: STCVBR(sh2, Rn); break;
- case 0x23: BRAF(sh2, Rn); break;
- case 0x24: MOVBS0(sh2, Rm, Rn); break;
- case 0x25: MOVWS0(sh2, Rm, Rn); break;
- case 0x26: MOVLS0(sh2, Rm, Rn); break;
- case 0x27: MULL(sh2, Rm, Rn); break;
- case 0x28: CLRMAC(sh2); break;
- case 0x29: MOVT(sh2, Rn); break;
- case 0x2a: STSPR(sh2, Rn); break;
- case 0x2b: RTE(sh2); break;
- case 0x2c: MOVBL0(sh2, Rm, Rn); break;
- case 0x2d: MOVWL0(sh2, Rm, Rn); break;
- case 0x2e: MOVLL0(sh2, Rm, Rn); break;
- case 0x2f: MAC_L(sh2, Rm, Rn); break;
-
- case 0x30: ILLEGAL(sh2); break;
- case 0x31: ILLEGAL(sh2); break;
- case 0x32: ILLEGAL(sh2); break;
- case 0x33: ILLEGAL(sh2); break;
- case 0x34: MOVBS0(sh2, Rm, Rn); break;
- case 0x35: MOVWS0(sh2, Rm, Rn); break;
- case 0x36: MOVLS0(sh2, Rm, Rn); break;
- case 0x37: MULL(sh2, Rm, Rn); break;
- case 0x38: ILLEGAL(sh2); break;
- case 0x39: ILLEGAL(sh2); break;
- case 0x3c: MOVBL0(sh2, Rm, Rn); break;
- case 0x3d: MOVWL0(sh2, Rm, Rn); break;
- case 0x3e: MOVLL0(sh2, Rm, Rn); break;
- case 0x3f: MAC_L(sh2, Rm, Rn); break;
- case 0x3a: ILLEGAL(sh2); break;
- case 0x3b: ILLEGAL(sh2); break;
+ case 0x0a: STSMACH(Rn); break;
+ case 0x0b: RTS(); break;
+ case 0x0c: MOVBL0(Rm, Rn); break;
+ case 0x0d: MOVWL0(Rm, Rn); break;
+ case 0x0e: MOVLL0(Rm, Rn); break;
+ case 0x0f: MAC_L(Rm, Rn); break;
+
+ case 0x10: ILLEGAL(); break;
+ case 0x11: ILLEGAL(); break;
+ case 0x12: STCGBR(Rn); break;
+ case 0x13: ILLEGAL(); break;
+ case 0x14: MOVBS0(Rm, Rn); break;
+ case 0x15: MOVWS0(Rm, Rn); break;
+ case 0x16: MOVLS0(Rm, Rn); break;
+ case 0x17: MULL(Rm, Rn); break;
+ case 0x18: SETT(); break;
+ case 0x19: DIV0U(); break;
+ case 0x1a: STSMACL(Rn); break;
+ case 0x1b: SLEEP(); break;
+ case 0x1c: MOVBL0(Rm, Rn); break;
+ case 0x1d: MOVWL0(Rm, Rn); break;
+ case 0x1e: MOVLL0(Rm, Rn); break;
+ case 0x1f: MAC_L(Rm, Rn); break;
+
+ case 0x20: ILLEGAL(); break;
+ case 0x21: ILLEGAL(); break;
+ case 0x22: STCVBR(Rn); break;
+ case 0x23: BRAF(Rn); break;
+ case 0x24: MOVBS0(Rm, Rn); break;
+ case 0x25: MOVWS0(Rm, Rn); break;
+ case 0x26: MOVLS0(Rm, Rn); break;
+ case 0x27: MULL(Rm, Rn); break;
+ case 0x28: CLRMAC(); break;
+ case 0x29: MOVT(Rn); break;
+ case 0x2a: STSPR(Rn); break;
+ case 0x2b: RTE(); break;
+ case 0x2c: MOVBL0(Rm, Rn); break;
+ case 0x2d: MOVWL0(Rm, Rn); break;
+ case 0x2e: MOVLL0(Rm, Rn); break;
+ case 0x2f: MAC_L(Rm, Rn); break;
+
+ case 0x30: ILLEGAL(); break;
+ case 0x31: ILLEGAL(); break;
+ case 0x32: ILLEGAL(); break;
+ case 0x33: ILLEGAL(); break;
+ case 0x34: MOVBS0(Rm, Rn); break;
+ case 0x35: MOVWS0(Rm, Rn); break;
+ case 0x36: MOVLS0(Rm, Rn); break;
+ case 0x37: MULL(Rm, Rn); break;
+ case 0x38: ILLEGAL(); break;
+ case 0x39: ILLEGAL(); break;
+ case 0x3c: MOVBL0(Rm, Rn); break;
+ case 0x3d: MOVWL0(Rm, Rn); break;
+ case 0x3e: MOVLL0(Rm, Rn); break;
+ case 0x3f: MAC_L(Rm, Rn); break;
+ case 0x3a: ILLEGAL(); break;
+ case 0x3b: ILLEGAL(); break;
}
}
-INLINE void op0001(sh2_state *sh2, UINT16 opcode)
+void sh2_device::op0001(UINT16 opcode)
{
- MOVLS4(sh2, Rm, opcode & 0x0f, Rn);
+ MOVLS4(Rm, opcode & 0x0f, Rn);
}
-INLINE void op0010(sh2_state *sh2, UINT16 opcode)
+void sh2_device::op0010(UINT16 opcode)
{
switch (opcode & 15)
{
- case 0: MOVBS(sh2, Rm, Rn); break;
- case 1: MOVWS(sh2, Rm, Rn); break;
- case 2: MOVLS(sh2, Rm, Rn); break;
- case 3: ILLEGAL(sh2); break;
- case 4: MOVBM(sh2, Rm, Rn); break;
- case 5: MOVWM(sh2, Rm, Rn); break;
- case 6: MOVLM(sh2, Rm, Rn); break;
- case 7: DIV0S(sh2, Rm, Rn); break;
- case 8: TST(sh2, Rm, Rn); break;
- case 9: AND(sh2, Rm, Rn); break;
- case 10: XOR(sh2, Rm, Rn); break;
- case 11: OR(sh2, Rm, Rn); break;
- case 12: CMPSTR(sh2, Rm, Rn); break;
- case 13: XTRCT(sh2, Rm, Rn); break;
- case 14: MULU(sh2, Rm, Rn); break;
- case 15: MULS(sh2, Rm, Rn); break;
+ case 0: MOVBS(Rm, Rn); break;
+ case 1: MOVWS(Rm, Rn); break;
+ case 2: MOVLS(Rm, Rn); break;
+ case 3: ILLEGAL(); break;
+ case 4: MOVBM(Rm, Rn); break;
+ case 5: MOVWM(Rm, Rn); break;
+ case 6: MOVLM(Rm, Rn); break;
+ case 7: DIV0S(Rm, Rn); break;
+ case 8: TST(Rm, Rn); break;
+ case 9: AND(Rm, Rn); break;
+ case 10: XOR(Rm, Rn); break;
+ case 11: OR(Rm, Rn); break;
+ case 12: CMPSTR(Rm, Rn); break;
+ case 13: XTRCT(Rm, Rn); break;
+ case 14: MULU(Rm, Rn); break;
+ case 15: MULS(Rm, Rn); break;
}
}
-INLINE void op0011(sh2_state *sh2, UINT16 opcode)
+void sh2_device::op0011(UINT16 opcode)
{
switch (opcode & 15)
{
- case 0: CMPEQ(sh2, Rm, Rn); break;
- case 1: ILLEGAL(sh2); break;
- case 2: CMPHS(sh2, Rm, Rn); break;
- case 3: CMPGE(sh2, Rm, Rn); break;
- case 4: DIV1(sh2, Rm, Rn); break;
- case 5: DMULU(sh2, Rm, Rn); break;
- case 6: CMPHI(sh2, Rm, Rn); break;
- case 7: CMPGT(sh2, Rm, Rn); break;
- case 8: SUB(sh2, Rm, Rn); break;
- case 9: ILLEGAL(sh2); break;
- case 10: SUBC(sh2, Rm, Rn); break;
- case 11: SUBV(sh2, Rm, Rn); break;
- case 12: ADD(sh2, Rm, Rn); break;
- case 13: DMULS(sh2, Rm, Rn); break;
- case 14: ADDC(sh2, Rm, Rn); break;
- case 15: ADDV(sh2, Rm, Rn); break;
+ case 0: CMPEQ(Rm, Rn); break;
+ case 1: ILLEGAL(); break;
+ case 2: CMPHS(Rm, Rn); break;
+ case 3: CMPGE(Rm, Rn); break;
+ case 4: DIV1(Rm, Rn); break;
+ case 5: DMULU(Rm, Rn); break;
+ case 6: CMPHI(Rm, Rn); break;
+ case 7: CMPGT(Rm, Rn); break;
+ case 8: SUB(Rm, Rn); break;
+ case 9: ILLEGAL(); break;
+ case 10: SUBC(Rm, Rn); break;
+ case 11: SUBV(Rm, Rn); break;
+ case 12: ADD(Rm, Rn); break;
+ case 13: DMULS(Rm, Rn); break;
+ case 14: ADDC(Rm, Rn); break;
+ case 15: ADDV(Rm, Rn); break;
}
}
-INLINE void op0100(sh2_state *sh2, UINT16 opcode)
+void sh2_device::op0100(UINT16 opcode)
{
switch (opcode & 0x3F)
{
- case 0x00: SHLL(sh2, Rn); break;
- case 0x01: SHLR(sh2, Rn); break;
- case 0x02: STSMMACH(sh2, Rn); break;
- case 0x03: STCMSR(sh2, Rn); break;
- case 0x04: ROTL(sh2, Rn); break;
- case 0x05: ROTR(sh2, Rn); break;
- case 0x06: LDSMMACH(sh2, Rn); break;
- case 0x07: LDCMSR(sh2, Rn); break;
- case 0x08: SHLL2(sh2, Rn); break;
- case 0x09: SHLR2(sh2, Rn); break;
- case 0x0a: LDSMACH(sh2, Rn); break;
- case 0x0b: JSR(sh2, Rn); break;
- case 0x0c: ILLEGAL(sh2); break;
- case 0x0d: ILLEGAL(sh2); break;
- case 0x0e: LDCSR(sh2, Rn); break;
- case 0x0f: MAC_W(sh2, Rm, Rn); break;
-
- case 0x10: DT(sh2, Rn); break;
- case 0x11: CMPPZ(sh2, Rn); break;
- case 0x12: STSMMACL(sh2, Rn); break;
- case 0x13: STCMGBR(sh2, Rn); break;
- case 0x14: ILLEGAL(sh2); break;
- case 0x15: CMPPL(sh2, Rn); break;
- case 0x16: LDSMMACL(sh2, Rn); break;
- case 0x17: LDCMGBR(sh2, Rn); break;
- case 0x18: SHLL8(sh2, Rn); break;
- case 0x19: SHLR8(sh2, Rn); break;
- case 0x1a: LDSMACL(sh2, Rn); break;
- case 0x1b: TAS(sh2, Rn); break;
- case 0x1c: ILLEGAL(sh2); break;
- case 0x1d: ILLEGAL(sh2); break;
- case 0x1e: LDCGBR(sh2, Rn); break;
- case 0x1f: MAC_W(sh2, Rm, Rn); break;
-
- case 0x20: SHAL(sh2, Rn); break;
- case 0x21: SHAR(sh2, Rn); break;
- case 0x22: STSMPR(sh2, Rn); break;
- case 0x23: STCMVBR(sh2, Rn); break;
- case 0x24: ROTCL(sh2, Rn); break;
- case 0x25: ROTCR(sh2, Rn); break;
- case 0x26: LDSMPR(sh2, Rn); break;
- case 0x27: LDCMVBR(sh2, Rn); break;
- case 0x28: SHLL16(sh2, Rn); break;
- case 0x29: SHLR16(sh2, Rn); break;
- case 0x2a: LDSPR(sh2, Rn); break;
- case 0x2b: JMP(sh2, Rn); break;
- case 0x2c: ILLEGAL(sh2); break;
- case 0x2d: ILLEGAL(sh2); break;
- case 0x2e: LDCVBR(sh2, Rn); break;
- case 0x2f: MAC_W(sh2, Rm, Rn); break;
-
- case 0x30: ILLEGAL(sh2); break;
- case 0x31: ILLEGAL(sh2); break;
- case 0x32: ILLEGAL(sh2); break;
- case 0x33: ILLEGAL(sh2); break;
- case 0x34: ILLEGAL(sh2); break;
- case 0x35: ILLEGAL(sh2); break;
- case 0x36: ILLEGAL(sh2); break;
- case 0x37: ILLEGAL(sh2); break;
- case 0x38: ILLEGAL(sh2); break;
- case 0x39: ILLEGAL(sh2); break;
- case 0x3a: ILLEGAL(sh2); break;
- case 0x3b: ILLEGAL(sh2); break;
- case 0x3c: ILLEGAL(sh2); break;
- case 0x3d: ILLEGAL(sh2); break;
- case 0x3e: ILLEGAL(sh2); break;
- case 0x3f: MAC_W(sh2, Rm, Rn); break;
+ case 0x00: SHLL(Rn); break;
+ case 0x01: SHLR(Rn); break;
+ case 0x02: STSMMACH(Rn); break;
+ case 0x03: STCMSR(Rn); break;
+ case 0x04: ROTL(Rn); break;
+ case 0x05: ROTR(Rn); break;
+ case 0x06: LDSMMACH(Rn); break;
+ case 0x07: LDCMSR(Rn); break;
+ case 0x08: SHLL2(Rn); break;
+ case 0x09: SHLR2(Rn); break;
+ case 0x0a: LDSMACH(Rn); break;
+ case 0x0b: JSR(Rn); break;
+ case 0x0c: ILLEGAL(); break;
+ case 0x0d: ILLEGAL(); break;
+ case 0x0e: LDCSR(Rn); break;
+ case 0x0f: MAC_W(Rm, Rn); break;
+
+ case 0x10: DT(Rn); break;
+ case 0x11: CMPPZ(Rn); break;
+ case 0x12: STSMMACL(Rn); break;
+ case 0x13: STCMGBR(Rn); break;
+ case 0x14: ILLEGAL(); break;
+ case 0x15: CMPPL(Rn); break;
+ case 0x16: LDSMMACL(Rn); break;
+ case 0x17: LDCMGBR(Rn); break;
+ case 0x18: SHLL8(Rn); break;
+ case 0x19: SHLR8(Rn); break;
+ case 0x1a: LDSMACL(Rn); break;
+ case 0x1b: TAS(Rn); break;
+ case 0x1c: ILLEGAL(); break;
+ case 0x1d: ILLEGAL(); break;
+ case 0x1e: LDCGBR(Rn); break;
+ case 0x1f: MAC_W(Rm, Rn); break;
+
+ case 0x20: SHAL(Rn); break;
+ case 0x21: SHAR(Rn); break;
+ case 0x22: STSMPR(Rn); break;
+ case 0x23: STCMVBR(Rn); break;
+ case 0x24: ROTCL(Rn); break;
+ case 0x25: ROTCR(Rn); break;
+ case 0x26: LDSMPR(Rn); break;
+ case 0x27: LDCMVBR(Rn); break;
+ case 0x28: SHLL16(Rn); break;
+ case 0x29: SHLR16(Rn); break;
+ case 0x2a: LDSPR(Rn); break;
+ case 0x2b: JMP(Rn); break;
+ case 0x2c: ILLEGAL(); break;
+ case 0x2d: ILLEGAL(); break;
+ case 0x2e: LDCVBR(Rn); break;
+ case 0x2f: MAC_W(Rm, Rn); break;
+
+ case 0x30: ILLEGAL(); break;
+ case 0x31: ILLEGAL(); break;
+ case 0x32: ILLEGAL(); break;
+ case 0x33: ILLEGAL(); break;
+ case 0x34: ILLEGAL(); break;
+ case 0x35: ILLEGAL(); break;
+ case 0x36: ILLEGAL(); break;
+ case 0x37: ILLEGAL(); break;
+ case 0x38: ILLEGAL(); break;
+ case 0x39: ILLEGAL(); break;
+ case 0x3a: ILLEGAL(); break;
+ case 0x3b: ILLEGAL(); break;
+ case 0x3c: ILLEGAL(); break;
+ case 0x3d: ILLEGAL(); break;
+ case 0x3e: ILLEGAL(); break;
+ case 0x3f: MAC_W(Rm, Rn); break;
}
}
-INLINE void op0101(sh2_state *sh2, UINT16 opcode)
+void sh2_device::op0101(UINT16 opcode)
{
- MOVLL4(sh2, Rm, opcode & 0x0f, Rn);
+ MOVLL4(Rm, opcode & 0x0f, Rn);
}
-INLINE void op0110(sh2_state *sh2, UINT16 opcode)
+void sh2_device::op0110(UINT16 opcode)
{
switch (opcode & 15)
{
- case 0: MOVBL(sh2, Rm, Rn); break;
- case 1: MOVWL(sh2, Rm, Rn); break;
- case 2: MOVLL(sh2, Rm, Rn); break;
- case 3: MOV(sh2, Rm, Rn); break;
- case 4: MOVBP(sh2, Rm, Rn); break;
- case 5: MOVWP(sh2, Rm, Rn); break;
- case 6: MOVLP(sh2, Rm, Rn); break;
- case 7: NOT(sh2, Rm, Rn); break;
- case 8: SWAPB(sh2, Rm, Rn); break;
- case 9: SWAPW(sh2, Rm, Rn); break;
- case 10: NEGC(sh2, Rm, Rn); break;
- case 11: NEG(sh2, Rm, Rn); break;
- case 12: EXTUB(sh2, Rm, Rn); break;
- case 13: EXTUW(sh2, Rm, Rn); break;
- case 14: EXTSB(sh2, Rm, Rn); break;
- case 15: EXTSW(sh2, Rm, Rn); break;
+ case 0: MOVBL(Rm, Rn); break;
+ case 1: MOVWL(Rm, Rn); break;
+ case 2: MOVLL(Rm, Rn); break;
+ case 3: MOV(Rm, Rn); break;
+ case 4: MOVBP(Rm, Rn); break;
+ case 5: MOVWP(Rm, Rn); break;
+ case 6: MOVLP(Rm, Rn); break;
+ case 7: NOT(Rm, Rn); break;
+ case 8: SWAPB(Rm, Rn); break;
+ case 9: SWAPW(Rm, Rn); break;
+ case 10: NEGC(Rm, Rn); break;
+ case 11: NEG(Rm, Rn); break;
+ case 12: EXTUB(Rm, Rn); break;
+ case 13: EXTUW(Rm, Rn); break;
+ case 14: EXTSB(Rm, Rn); break;
+ case 15: EXTSW(Rm, Rn); break;
}
}
-INLINE void op0111(sh2_state *sh2, UINT16 opcode)
+void sh2_device::op0111(UINT16 opcode)
{
- ADDI(sh2, opcode & 0xff, Rn);
+ ADDI(opcode & 0xff, Rn);
}
-INLINE void op1000(sh2_state *sh2, UINT16 opcode)
+void sh2_device::op1000(UINT16 opcode)
{
switch ( opcode & (15<<8) )
{
- case 0 << 8: MOVBS4(sh2, opcode & 0x0f, Rm); break;
- case 1 << 8: MOVWS4(sh2, opcode & 0x0f, Rm); break;
- case 2<< 8: ILLEGAL(sh2); break;
- case 3<< 8: ILLEGAL(sh2); break;
- case 4<< 8: MOVBL4(sh2, Rm, opcode & 0x0f); break;
- case 5<< 8: MOVWL4(sh2, Rm, opcode & 0x0f); break;
- case 6<< 8: ILLEGAL(sh2); break;
- case 7<< 8: ILLEGAL(sh2); break;
- case 8<< 8: CMPIM(sh2, opcode & 0xff); break;
- case 9<< 8: BT(sh2, opcode & 0xff); break;
- case 10<< 8: ILLEGAL(sh2); break;
- case 11<< 8: BF(sh2, opcode & 0xff); break;
- case 12<< 8: ILLEGAL(sh2); break;
- case 13<< 8: BTS(sh2, opcode & 0xff); break;
- case 14<< 8: ILLEGAL(sh2); break;
- case 15<< 8: BFS(sh2, opcode & 0xff); break;
+ case 0 << 8: MOVBS4(opcode & 0x0f, Rm); break;
+ case 1 << 8: MOVWS4(opcode & 0x0f, Rm); break;
+ case 2<< 8: ILLEGAL(); break;
+ case 3<< 8: ILLEGAL(); break;
+ case 4<< 8: MOVBL4(Rm, opcode & 0x0f); break;
+ case 5<< 8: MOVWL4(Rm, opcode & 0x0f); break;
+ case 6<< 8: ILLEGAL(); break;
+ case 7<< 8: ILLEGAL(); break;
+ case 8<< 8: CMPIM(opcode & 0xff); break;
+ case 9<< 8: BT(opcode & 0xff); break;
+ case 10<< 8: ILLEGAL(); break;
+ case 11<< 8: BF(opcode & 0xff); break;
+ case 12<< 8: ILLEGAL(); break;
+ case 13<< 8: BTS(opcode & 0xff); break;
+ case 14<< 8: ILLEGAL(); break;
+ case 15<< 8: BFS(opcode & 0xff); break;
}
}
-INLINE void op1001(sh2_state *sh2, UINT16 opcode)
+void sh2_device::op1001(UINT16 opcode)
{
- MOVWI(sh2, opcode & 0xff, Rn);
+ MOVWI(opcode & 0xff, Rn);
}
-INLINE void op1010(sh2_state *sh2, UINT16 opcode)
+void sh2_device::op1010(UINT16 opcode)
{
- BRA(sh2, opcode & 0xfff);
+ BRA(opcode & 0xfff);
}
-INLINE void op1011(sh2_state *sh2, UINT16 opcode)
+void sh2_device::op1011(UINT16 opcode)
{
- BSR(sh2, opcode & 0xfff);
+ BSR(opcode & 0xfff);
}
-INLINE void op1100(sh2_state *sh2, UINT16 opcode)
+void sh2_device::op1100(UINT16 opcode)
{
switch (opcode & (15<<8))
{
- case 0<<8: MOVBSG(sh2, opcode & 0xff); break;
- case 1<<8: MOVWSG(sh2, opcode & 0xff); break;
- case 2<<8: MOVLSG(sh2, opcode & 0xff); break;
- case 3<<8: TRAPA(sh2, opcode & 0xff); break;
- case 4<<8: MOVBLG(sh2, opcode & 0xff); break;
- case 5<<8: MOVWLG(sh2, opcode & 0xff); break;
- case 6<<8: MOVLLG(sh2, opcode & 0xff); break;
- case 7<<8: MOVA(sh2, opcode & 0xff); break;
- case 8<<8: TSTI(sh2, opcode & 0xff); break;
- case 9<<8: ANDI(sh2, opcode & 0xff); break;
- case 10<<8: XORI(sh2, opcode & 0xff); break;
- case 11<<8: ORI(sh2, opcode & 0xff); break;
- case 12<<8: TSTM(sh2, opcode & 0xff); break;
- case 13<<8: ANDM(sh2, opcode & 0xff); break;
- case 14<<8: XORM(sh2, opcode & 0xff); break;
- case 15<<8: ORM(sh2, opcode & 0xff); break;
+ case 0<<8: MOVBSG(opcode & 0xff); break;
+ case 1<<8: MOVWSG(opcode & 0xff); break;
+ case 2<<8: MOVLSG(opcode & 0xff); break;
+ case 3<<8: TRAPA(opcode & 0xff); break;
+ case 4<<8: MOVBLG(opcode & 0xff); break;
+ case 5<<8: MOVWLG(opcode & 0xff); break;
+ case 6<<8: MOVLLG(opcode & 0xff); break;
+ case 7<<8: MOVA(opcode & 0xff); break;
+ case 8<<8: TSTI(opcode & 0xff); break;
+ case 9<<8: ANDI(opcode & 0xff); break;
+ case 10<<8: XORI(opcode & 0xff); break;
+ case 11<<8: ORI(opcode & 0xff); break;
+ case 12<<8: TSTM(opcode & 0xff); break;
+ case 13<<8: ANDM(opcode & 0xff); break;
+ case 14<<8: XORM(opcode & 0xff); break;
+ case 15<<8: ORM(opcode & 0xff); break;
}
}
-INLINE void op1101(sh2_state *sh2, UINT16 opcode)
+void sh2_device::op1101(UINT16 opcode)
{
- MOVLI(sh2, opcode & 0xff, Rn);
+ MOVLI(opcode & 0xff, Rn);
}
-INLINE void op1110(sh2_state *sh2, UINT16 opcode)
+void sh2_device::op1110(UINT16 opcode)
{
- MOVI(sh2, opcode & 0xff, Rn);
+ MOVI(opcode & 0xff, Rn);
}
-INLINE void op1111(sh2_state *sh2, UINT16 opcode)
+void sh2_device::op1111(UINT16 opcode)
{
- ILLEGAL(sh2);
+ ILLEGAL();
}
/*****************************************************************************
* MAME CPU INTERFACE
*****************************************************************************/
-static CPU_RESET( sh2 )
+void sh2_device::device_reset()
{
- sh2_state *sh2 = get_safe_token(device);
- int (*dma_callback_kludge)(device_t *device, UINT32 src, UINT32 dst, UINT32 data, int size);
- int (*dma_callback_fifo_data_available)(device_t *device, UINT32 src, UINT32 dst, UINT32 data, int size);
- int save_is_slave;
-
- void (*f)(UINT32 data);
- device_irq_acknowledge_callback save_irqcallback;
-
- f = sh2->ftcsr_read_callback;
- save_irqcallback = sh2->irq_callback;
- save_is_slave = sh2->is_slave;
- dma_callback_kludge = sh2->dma_callback_kludge;
- dma_callback_fifo_data_available = sh2->dma_callback_fifo_data_available;
+ m_sh2_state->ppc = m_sh2_state->pc = m_sh2_state->pr = m_sh2_state->sr = m_sh2_state->gbr = m_sh2_state->vbr = m_sh2_state->mach = m_sh2_state->macl = 0;
+ m_sh2_state->evec = m_sh2_state->irqsr = 0;
+ memset(&m_sh2_state->r[0], 0, sizeof(m_sh2_state->r[0])*16);
+ m_sh2_state->ea = m_delay = m_cpu_off = m_dvsr = m_dvdnth = m_dvdntl = m_dvcr = 0;
+ m_sh2_state->pending_irq = m_test_irq = 0;
+ memset(&m_irq_queue[0], 0, sizeof(m_irq_queue[0])*16);
+ memset(&m_irq_line_state[0], 0, sizeof(m_irq_line_state[0])*17);
+ m_frc = m_ocra = m_ocrb = m_icr = 0;
+ m_frc_base = 0;
+ m_frt_input = m_sh2_state->internal_irq_level = m_internal_irq_vector = 0;
+ m_dma_timer_active[0] = m_dma_timer_active[1] = 0;
+ m_dma_irq[0] = m_dma_irq[1] = 0;
- sh2->ppc = sh2->pc = sh2->pr = sh2->sr = sh2->gbr = sh2->vbr = sh2->mach = sh2->macl = 0;
- sh2->evec = sh2->irqsr = 0;
- memset(&sh2->r[0], 0, sizeof(sh2->r[0])*16);
- sh2->ea = sh2->delay = sh2->cpu_off = sh2->dvsr = sh2->dvdnth = sh2->dvdntl = sh2->dvcr = 0;
- sh2->pending_irq = sh2->test_irq = 0;
- memset(&sh2->irq_queue[0], 0, sizeof(sh2->irq_queue[0])*16);
- memset(&sh2->irq_line_state[0], 0, sizeof(sh2->irq_line_state[0])*17);
- sh2->frc = sh2->ocra = sh2->ocrb = sh2->icr = 0;
- sh2->frc_base = 0;
- sh2->frt_input = sh2->internal_irq_level = sh2->internal_irq_vector = 0;
- sh2->dma_timer_active[0] = sh2->dma_timer_active[1] = 0;
- sh2->dma_irq[0] = sh2->dma_irq[1] = 0;
+ memset(m_m, 0, 0x200);
- sh2->dma_callback_kludge = dma_callback_kludge;
- sh2->dma_callback_fifo_data_available = dma_callback_fifo_data_available;
- sh2->is_slave = save_is_slave;
- sh2->ftcsr_read_callback = f;
- sh2->irq_callback = save_irqcallback;
- sh2->device = device;
+ m_sh2_state->pc = RL(0);
+ m_sh2_state->r[15] = RL(4);
+ m_sh2_state->sr = I;
+ m_sh2_state->sleep_mode = 0;
- memset(sh2->m, 0, 0x200);
+ m_sh2_state->internal_irq_level = -1;
- sh2->pc = RL(sh2, 0);
- sh2->r[15] = RL(sh2, 4);
- sh2->sr = I;
- sh2->sleep_mode = 0;
-
- sh2->internal_irq_level = -1;
+ m_cache_dirty = TRUE;
}
-/*-------------------------------------------------
- sh1_reset - reset the processor
--------------------------------------------------*/
-
-static CPU_RESET( sh1 )
-{
- sh2_state *sh2 = get_safe_token(device);
- CPU_RESET_CALL( sh2 );
- sh2->cpu_type = CPU_TYPE_SH1;
-}
/* Execute cycles - returns number of cycles actually run */
-static CPU_EXECUTE( sh2 )
+void sh2_device::execute_run()
{
- sh2_state *sh2 = get_safe_token(device);
+ if ( m_isdrc )
+ {
+ execute_run_drc();
+ return;
+ }
- if (sh2->cpu_off)
+ if (m_cpu_off)
{
- sh2->icount = 0;
+ m_sh2_state->icount = 0;
return;
}
// run any active DMAs now
#ifndef USE_TIMER_FOR_DMA
- for ( int i = 0; i < sh2->icount ; i++)
+ for ( int i = 0; i < m_sh2_state->icount ; i++)
{
for( int dma=0;dma<1;dma++)
{
- if (sh2->dma_timer_active[dma])
- sh2_do_dma(sh2, dma);
+ if (m_dma_timer_active[dma])
+ sh2_do_dma(dma);
}
}
#endif
@@ -2251,268 +2364,365 @@ static CPU_EXECUTE( sh2 )
{
UINT32 opcode;
- if (sh2->delay)
+ if (m_delay)
{
- opcode = sh2->program->read_word(((UINT32)(sh2->delay & AM)));
- sh2->pc -= 2;
+ opcode = m_program->read_word(((UINT32)(m_delay & AM)));
+ m_sh2_state->pc -= 2;
}
else
- opcode = sh2->program->read_word(((UINT32)(sh2->pc & AM)));
+ opcode = m_program->read_word(((UINT32)(m_sh2_state->pc & AM)));
- debugger_instruction_hook(device, sh2->pc);
+ debugger_instruction_hook(this, m_sh2_state->pc);
- sh2->delay = 0;
- sh2->pc += 2;
- sh2->ppc = sh2->pc;
+ m_delay = 0;
+ m_sh2_state->pc += 2;
+ m_sh2_state->ppc = m_sh2_state->pc;
switch (opcode & ( 15 << 12))
{
- case 0<<12: op0000(sh2, opcode); break;
- case 1<<12: op0001(sh2, opcode); break;
- case 2<<12: op0010(sh2, opcode); break;
- case 3<<12: op0011(sh2, opcode); break;
- case 4<<12: op0100(sh2, opcode); break;
- case 5<<12: op0101(sh2, opcode); break;
- case 6<<12: op0110(sh2, opcode); break;
- case 7<<12: op0111(sh2, opcode); break;
- case 8<<12: op1000(sh2, opcode); break;
- case 9<<12: op1001(sh2, opcode); break;
- case 10<<12: op1010(sh2, opcode); break;
- case 11<<12: op1011(sh2, opcode); break;
- case 12<<12: op1100(sh2, opcode); break;
- case 13<<12: op1101(sh2, opcode); break;
- case 14<<12: op1110(sh2, opcode); break;
- default: op1111(sh2, opcode); break;
+ case 0<<12: op0000(opcode); break;
+ case 1<<12: op0001(opcode); break;
+ case 2<<12: op0010(opcode); break;
+ case 3<<12: op0011(opcode); break;
+ case 4<<12: op0100(opcode); break;
+ case 5<<12: op0101(opcode); break;
+ case 6<<12: op0110(opcode); break;
+ case 7<<12: op0111(opcode); break;
+ case 8<<12: op1000(opcode); break;
+ case 9<<12: op1001(opcode); break;
+ case 10<<12: op1010(opcode); break;
+ case 11<<12: op1011(opcode); break;
+ case 12<<12: op1100(opcode); break;
+ case 13<<12: op1101(opcode); break;
+ case 14<<12: op1110(opcode); break;
+ default: op1111(opcode); break;
}
- if(sh2->test_irq && !sh2->delay)
+ if(m_test_irq && !m_delay)
{
CHECK_PENDING_IRQ("mame_sh2_execute");
- sh2->test_irq = 0;
+ m_test_irq = 0;
}
- sh2->icount--;
- } while( sh2->icount > 0 );
-}
-
-static CPU_INIT( sh2 )
-{
- sh2_state *sh2 = get_safe_token(device);
+ m_sh2_state->icount--;
+ } while( m_sh2_state->icount > 0 );
+}
+
+void sh2_device::device_start()
+{
+ /* allocate the implementation-specific state from the full cache */
+ m_sh2_state = (internal_sh2_state *)m_cache.alloc_near(sizeof(internal_sh2_state));
+
+ m_timer = machine().scheduler().timer_alloc(timer_expired_delegate(FUNC(sh2_device::sh2_timer_callback), this));
+ m_timer->adjust(attotime::never);
+
+ m_dma_current_active_timer[0] = machine().scheduler().timer_alloc(timer_expired_delegate(FUNC(sh2_device::sh2_dma_current_active_callback), this));
+ m_dma_current_active_timer[0]->adjust(attotime::never);
+
+ m_dma_current_active_timer[1] = machine().scheduler().timer_alloc(timer_expired_delegate(FUNC(sh2_device::sh2_dma_current_active_callback), this));
+ m_dma_current_active_timer[1]->adjust(attotime::never);
+
+ m_is_slave = is_slave;
+ m_dma_callback_kludge = dma_callback_kludge;
+ m_dma_callback_fifo_data_available = dma_callback_fifo_data_available;
+
+ m_program = &space(AS_PROGRAM);
+ m_direct = &m_program->direct();
+ m_internal = &space(AS_PROGRAM);
+
+ save_item(NAME(m_sh2_state->pc));
+ save_item(NAME(m_sh2_state->sr));
+ save_item(NAME(m_sh2_state->pr));
+ save_item(NAME(m_sh2_state->gbr));
+ save_item(NAME(m_sh2_state->vbr));
+ save_item(NAME(m_sh2_state->mach));
+ save_item(NAME(m_sh2_state->macl));
+ save_item(NAME(m_sh2_state->r));
+ save_item(NAME(m_sh2_state->ea));
+ save_item(NAME(m_delay));
+ save_item(NAME(m_cpu_off));
+ save_item(NAME(m_dvsr));
+ save_item(NAME(m_dvdnth));
+ save_item(NAME(m_dvdntl));
+ save_item(NAME(m_dvcr));
+ save_item(NAME(m_sh2_state->pending_irq));
+ save_item(NAME(m_test_irq));
+ save_item(NAME(m_sh2_state->pending_nmi));
+ save_item(NAME(m_sh2_state->irqline));
+ save_item(NAME(m_sh2_state->evec));
+ save_item(NAME(m_sh2_state->irqsr));
+ save_item(NAME(m_sh2_state->target));
+ for (int i = 0; i < 16; ++i)
+ {
+ save_item(NAME(m_irq_queue[i].irq_vector), i);
+ save_item(NAME(m_irq_queue[i].irq_priority), i);
+ }
+ save_item(NAME(m_pcfsel));
+ save_item(NAME(m_maxpcfsel));
+ save_item(NAME(m_pcflushes));
+ save_item(NAME(m_irq_line_state));
+ save_item(NAME(m_m));
+ save_item(NAME(m_nmi_line_state));
+ save_item(NAME(m_frc));
+ save_item(NAME(m_ocra));
+ save_item(NAME(m_ocrb));
+ save_item(NAME(m_icr));
+ save_item(NAME(m_frc_base));
+ save_item(NAME(m_frt_input));
+ save_item(NAME(m_sh2_state->internal_irq_level));
+ save_item(NAME(m_internal_irq_vector));
+ save_item(NAME(m_dma_timer_active));
+ save_item(NAME(m_dma_irq));
+ save_item(NAME(m_wtcnt));
+ save_item(NAME(m_wtcsr));
+ save_item(NAME(m_sh2_state->sleep_mode));
+
+ state_add( SH2_PC, "PC", m_debugger_temp).callimport().callexport().formatstr("%08X");
+ state_add( SH2_SR, "SR", m_sh2_state->sr).callimport().formatstr("%08X");
+ state_add( SH2_PR, "PR", m_sh2_state->pr).formatstr("%08X");
+ state_add( SH2_GBR, "GBR", m_sh2_state->gbr).formatstr("%08X");
+ state_add( SH2_VBR, "VBR", m_sh2_state->vbr).formatstr("%08X");
+ state_add( SH2_MACH, "MACH", m_sh2_state->mach).formatstr("%08X");
+ state_add( SH2_MACL, "MACL", m_sh2_state->macl).formatstr("%08X");
+ state_add( SH2_R0, "R0", m_sh2_state->r[ 0]).formatstr("%08X");
+ state_add( SH2_R1, "R1", m_sh2_state->r[ 1]).formatstr("%08X");
+ state_add( SH2_R2, "R2", m_sh2_state->r[ 2]).formatstr("%08X");
+ state_add( SH2_R3, "R3", m_sh2_state->r[ 3]).formatstr("%08X");
+ state_add( SH2_R4, "R4", m_sh2_state->r[ 4]).formatstr("%08X");
+ state_add( SH2_R5, "R5", m_sh2_state->r[ 5]).formatstr("%08X");
+ state_add( SH2_R6, "R6", m_sh2_state->r[ 6]).formatstr("%08X");
+ state_add( SH2_R7, "R7", m_sh2_state->r[ 7]).formatstr("%08X");
+ state_add( SH2_R8, "R8", m_sh2_state->r[ 8]).formatstr("%08X");
+ state_add( SH2_R9, "R9", m_sh2_state->r[ 9]).formatstr("%08X");
+ state_add( SH2_R10, "R10", m_sh2_state->r[10]).formatstr("%08X");
+ state_add( SH2_R11, "R11", m_sh2_state->r[11]).formatstr("%08X");
+ state_add( SH2_R12, "R12", m_sh2_state->r[12]).formatstr("%08X");
+ state_add( SH2_R13, "R13", m_sh2_state->r[13]).formatstr("%08X");
+ state_add( SH2_R14, "R14", m_sh2_state->r[14]).formatstr("%08X");
+ state_add( SH2_R15, "R15", m_sh2_state->r[15]).formatstr("%08X");
+ state_add( SH2_EA, "EA", m_sh2_state->ea).formatstr("%08X");
+
+ state_add( STATE_GENPC, "GENPC", m_sh2_state->pc ).noshow();
+ state_add( STATE_GENSP, "GENSP", m_sh2_state->r[15] ).noshow();
+ state_add( STATE_GENPCBASE, "GENPCBASE", m_sh2_state->ppc ).noshow();
+ state_add( STATE_GENFLAGS, "GENFLAGS", m_sh2_state->sr ).formatstr("%6s").noshow();
+
+ m_icountptr = &m_sh2_state->icount;
+
+ // Clear state
+ m_sh2_state->ppc = 0;
+ m_sh2_state->pc = 0;
+ m_sh2_state->pr = 0;
+ m_sh2_state->sr = 0;
+ m_sh2_state->gbr = 0;
+ m_sh2_state->vbr = 0;
+ m_sh2_state->mach = 0;
+ m_sh2_state->macl = 0;
+ memset(m_sh2_state->r, 0, sizeof(m_sh2_state->r));
+ m_sh2_state->ea = 0;
+ m_delay = 0;
+ m_cpu_off = 0;
+ m_dvsr = 0;
+ m_dvdnth = 0;
+ m_dvdntl = 0;
+ m_dvcr = 0;
+ m_sh2_state->pending_irq = 0;
+ m_test_irq = 0;
+ m_sh2_state->pending_nmi = 0;
+ m_sh2_state->irqline = 0;
+ m_sh2_state->evec = 0;
+ m_sh2_state->irqsr = 0;
+ m_sh2_state->target = 0;
+ memset(m_irq_queue, 0, sizeof(m_irq_queue));
+ m_maxpcfsel = 0;
+ memset(m_pcflushes, 0, sizeof(m_pcflushes));
+ memset(m_irq_line_state, 0, sizeof(m_irq_line_state));
+ memset(m_m, 0, sizeof(m_m));
+ m_nmi_line_state = 0;
+ m_frc = 0;
+ m_ocra = 0;
+ m_ocrb = 0;
+ m_icr = 0;
+ m_frc_base = 0;
+ m_frt_input = 0;
+ m_sh2_state->internal_irq_level = 0;
+ m_internal_irq_vector = 0;
+ m_sh2_state->icount = 0;
+ for ( int i = 0; i < 2; i++ )
+ {
+ m_dma_timer_active[i] = 0;
+ m_dma_irq[i] = 0;
+ m_active_dma_incs[i] = 0;
+ m_active_dma_incd[i] = 0;
+ m_active_dma_size[i] = 0;
+ m_active_dma_steal[i] = 0;
+ m_active_dma_src[i] = 0;
+ m_active_dma_dst[i] = 0;
+ m_active_dma_count[i] = 0;
+ }
+ m_wtcnt = 0;
+ m_wtcsr = 0;
+ m_sh2_state->sleep_mode = 0;
+ m_numcycles = 0;
+ m_sh2_state->arg0 = 0;
+ m_arg1 = 0;
+ m_irq = 0;
+ m_fastram_select = 0;
+ memset(m_fastram, 0, sizeof(m_fastram));
+
+ /* reset per-driver pcflushes */
+ m_pcfsel = 0;
+
+ /* initialize the UML generator */
+ UINT32 flags = 0;
+ if (LOG_UML)
+ flags |= DRCUML_OPTION_LOG_UML;
+ if (LOG_NATIVE)
+ flags |= DRCUML_OPTION_LOG_NATIVE;
+ m_drcuml = auto_alloc(machine(), drcuml_state(*this, m_cache, flags, 1, 32, 1));
+
+ /* add symbols for our stuff */
+ m_drcuml->symbol_add(&m_sh2_state->pc, sizeof(m_sh2_state->pc), "pc");
+ m_drcuml->symbol_add(&m_sh2_state->icount, sizeof(m_sh2_state->icount), "icount");
+ for (int regnum = 0; regnum < 16; regnum++)
+ {
+ char buf[10];
+ sprintf(buf, "r%d", regnum);
+ m_drcuml->symbol_add(&m_sh2_state->r[regnum], sizeof(m_sh2_state->r[regnum]), buf);
+ }
+ m_drcuml->symbol_add(&m_sh2_state->pr, sizeof(m_sh2_state->pr), "pr");
+ m_drcuml->symbol_add(&m_sh2_state->sr, sizeof(m_sh2_state->sr), "sr");
+ m_drcuml->symbol_add(&m_sh2_state->gbr, sizeof(m_sh2_state->gbr), "gbr");
+ m_drcuml->symbol_add(&m_sh2_state->vbr, sizeof(m_sh2_state->vbr), "vbr");
+ m_drcuml->symbol_add(&m_sh2_state->macl, sizeof(m_sh2_state->macl), "macl");
+ m_drcuml->symbol_add(&m_sh2_state->mach, sizeof(m_sh2_state->macl), "mach");
+
+ /* initialize the front-end helper */
+ m_drcfe = auto_alloc(machine(), sh2_frontend(this, COMPILE_BACKWARDS_BYTES, COMPILE_FORWARDS_BYTES, SINGLE_INSTRUCTION_MODE ? 1 : COMPILE_MAX_SEQUENCE));
+
+ /* compute the register parameters */
+ for (int regnum = 0; regnum < 16; regnum++)
+ {
+ m_regmap[regnum] = uml::mem(&m_sh2_state->r[regnum]);
+ }
+
+ /* if we have registers to spare, assign r0, r1, r2 to leftovers */
+ /* WARNING: do not use synthetic registers that are mapped here! */
+ if (!DISABLE_FAST_REGISTERS)
+ {
+ drcbe_info beinfo;
+ m_drcuml->get_backend_info(beinfo);
+ if (beinfo.direct_iregs > 4)
+ {
+ m_regmap[0] = uml::I4;
+ }
+ if (beinfo.direct_iregs > 5)
+ {
+ m_regmap[1] = uml::I5;
+ }
+ if (beinfo.direct_iregs > 6)
+ {
+ m_regmap[2] = uml::I6;
+ }
+ }
- /* initialize the common core parts */
- sh2_common_init(sh2, device, irqcallback,false);
+ /* mark the cache dirty so it is updated on next execute */
+ m_cache_dirty = TRUE;
}
-/**************************************************************************
- * Generic set_info
- **************************************************************************/
-static CPU_SET_INFO( sh2 )
+void sh2_device::state_string_export(const device_state_entry &entry, astring &string)
{
- sh2_state *sh2 = get_safe_token(device);
- switch (state)
+ switch (entry.index())
{
- /* --- the following bits of info are set as 64-bit signed integers --- */
- case CPUINFO_INT_INPUT_STATE + SH2_INT_VBLIN: sh2_set_irq_line(sh2, SH2_INT_VBLIN, info->i); break;
- case CPUINFO_INT_INPUT_STATE + SH2_INT_VBLOUT: sh2_set_irq_line(sh2, SH2_INT_VBLOUT, info->i); break;
- case CPUINFO_INT_INPUT_STATE + SH2_INT_HBLIN: sh2_set_irq_line(sh2, SH2_INT_HBLIN, info->i); break;
- case CPUINFO_INT_INPUT_STATE + SH2_INT_TIMER0: sh2_set_irq_line(sh2, SH2_INT_TIMER0, info->i); break;
- case CPUINFO_INT_INPUT_STATE + SH2_INT_TIMER1: sh2_set_irq_line(sh2, SH2_INT_TIMER1, info->i); break;
- case CPUINFO_INT_INPUT_STATE + SH2_INT_DSP: sh2_set_irq_line(sh2, SH2_INT_DSP, info->i); break;
- case CPUINFO_INT_INPUT_STATE + SH2_INT_SOUND: sh2_set_irq_line(sh2, SH2_INT_SOUND, info->i); break;
- case CPUINFO_INT_INPUT_STATE + SH2_INT_SMPC: sh2_set_irq_line(sh2, SH2_INT_SMPC, info->i); break;
- case CPUINFO_INT_INPUT_STATE + SH2_INT_PAD: sh2_set_irq_line(sh2, SH2_INT_PAD, info->i); break;
- case CPUINFO_INT_INPUT_STATE + SH2_INT_DMA2: sh2_set_irq_line(sh2, SH2_INT_DMA2, info->i); break;
- case CPUINFO_INT_INPUT_STATE + SH2_INT_DMA1: sh2_set_irq_line(sh2, SH2_INT_DMA1, info->i); break;
- case CPUINFO_INT_INPUT_STATE + SH2_INT_DMA0: sh2_set_irq_line(sh2, SH2_INT_DMA0, info->i); break;
- case CPUINFO_INT_INPUT_STATE + SH2_INT_DMAILL: sh2_set_irq_line(sh2, SH2_INT_DMAILL, info->i); break;
- case CPUINFO_INT_INPUT_STATE + SH2_INT_SPRITE: sh2_set_irq_line(sh2, SH2_INT_SPRITE, info->i); break;
- case CPUINFO_INT_INPUT_STATE + SH2_INT_14: sh2_set_irq_line(sh2, SH2_INT_14, info->i); break;
- case CPUINFO_INT_INPUT_STATE + SH2_INT_15: sh2_set_irq_line(sh2, SH2_INT_15, info->i); break;
- case CPUINFO_INT_INPUT_STATE + SH2_INT_ABUS: sh2_set_irq_line(sh2, SH2_INT_ABUS, info->i); break;
- case CPUINFO_INT_INPUT_STATE + INPUT_LINE_NMI: sh2_set_irq_line(sh2, INPUT_LINE_NMI, info->i); break;
-
- case CPUINFO_INT_REGISTER + SH2_PC:
- case CPUINFO_INT_PC: sh2->pc = info->i; sh2->delay = 0; break;
- case CPUINFO_INT_SP: sh2->r[15] = info->i; break;
- case CPUINFO_INT_REGISTER + SH2_PR: sh2->pr = info->i; break;
- case CPUINFO_INT_REGISTER + SH2_SR: sh2->sr = info->i; CHECK_PENDING_IRQ("sh2_set_reg"); break;
- case CPUINFO_INT_REGISTER + SH2_GBR: sh2->gbr = info->i; break;
- case CPUINFO_INT_REGISTER + SH2_VBR: sh2->vbr = info->i; break;
- case CPUINFO_INT_REGISTER + SH2_MACH: sh2->mach = info->i; break;
- case CPUINFO_INT_REGISTER + SH2_MACL: sh2->macl = info->i; break;
- case CPUINFO_INT_REGISTER + SH2_R0: sh2->r[ 0] = info->i; break;
- case CPUINFO_INT_REGISTER + SH2_R1: sh2->r[ 1] = info->i; break;
- case CPUINFO_INT_REGISTER + SH2_R2: sh2->r[ 2] = info->i; break;
- case CPUINFO_INT_REGISTER + SH2_R3: sh2->r[ 3] = info->i; break;
- case CPUINFO_INT_REGISTER + SH2_R4: sh2->r[ 4] = info->i; break;
- case CPUINFO_INT_REGISTER + SH2_R5: sh2->r[ 5] = info->i; break;
- case CPUINFO_INT_REGISTER + SH2_R6: sh2->r[ 6] = info->i; break;
- case CPUINFO_INT_REGISTER + SH2_R7: sh2->r[ 7] = info->i; break;
- case CPUINFO_INT_REGISTER + SH2_R8: sh2->r[ 8] = info->i; break;
- case CPUINFO_INT_REGISTER + SH2_R9: sh2->r[ 9] = info->i; break;
- case CPUINFO_INT_REGISTER + SH2_R10: sh2->r[10] = info->i; break;
- case CPUINFO_INT_REGISTER + SH2_R11: sh2->r[11] = info->i; break;
- case CPUINFO_INT_REGISTER + SH2_R12: sh2->r[12] = info->i; break;
- case CPUINFO_INT_REGISTER + SH2_R13: sh2->r[13] = info->i; break;
- case CPUINFO_INT_REGISTER + SH2_R14: sh2->r[14] = info->i; break;
- case CPUINFO_INT_REGISTER + SH2_R15: sh2->r[15] = info->i; break;
- case CPUINFO_INT_REGISTER + SH2_EA: sh2->ea = info->i; break;
+ case STATE_GENFLAGS:
+ string.printf("%c%c%d%c%c",
+ m_sh2_state->sr & M ? 'M':'.',
+ m_sh2_state->sr & Q ? 'Q':'.',
+ (m_sh2_state->sr & I) >> 4,
+ m_sh2_state->sr & S ? 'S':'.',
+ m_sh2_state->sr & T ? 'T':'.');
+ break;
}
}
-
-/**************************************************************************
- * Generic get_info
- **************************************************************************/
-
-CPU_GET_INFO( sh2_int )
+void sh2_device::state_import(const device_state_entry &entry)
{
- sh2_state *sh2 = (device != NULL && device->token() != NULL) ? get_safe_token(device) : NULL;
- switch (state)
+ switch (entry.index())
{
- /* --- the following bits of info are returned as 64-bit signed integers --- */
- case CPUINFO_INT_CONTEXT_SIZE: info->i = sizeof(sh2_state); break;
- case CPUINFO_INT_INPUT_LINES: info->i = 16; break;
- case CPUINFO_INT_DEFAULT_IRQ_VECTOR: info->i = 0; break;
- case CPUINFO_INT_ENDIANNESS: info->i = ENDIANNESS_BIG; break;
- case CPUINFO_INT_CLOCK_MULTIPLIER: info->i = 1; break;
- case CPUINFO_INT_CLOCK_DIVIDER: info->i = 1; break;
- case CPUINFO_INT_MIN_INSTRUCTION_BYTES: info->i = 2; break;
- case CPUINFO_INT_MAX_INSTRUCTION_BYTES: info->i = 2; break;
- case CPUINFO_INT_MIN_CYCLES: info->i = 1; break;
- case CPUINFO_INT_MAX_CYCLES: info->i = 4; break;
-
- case CPUINFO_INT_DATABUS_WIDTH + AS_PROGRAM: info->i = 32; break;
- case CPUINFO_INT_ADDRBUS_WIDTH + AS_PROGRAM: info->i = 32; break;
- case CPUINFO_INT_ADDRBUS_SHIFT + AS_PROGRAM: info->i = 0; break;
- case CPUINFO_INT_DATABUS_WIDTH + AS_DATA: info->i = 0; break;
- case CPUINFO_INT_ADDRBUS_WIDTH + AS_DATA: info->i = 0; break;
- case CPUINFO_INT_ADDRBUS_SHIFT + AS_DATA: info->i = 0; break;
- case CPUINFO_INT_DATABUS_WIDTH + AS_IO: info->i = 0; break;
- case CPUINFO_INT_ADDRBUS_WIDTH + AS_IO: info->i = 0; break;
- case CPUINFO_INT_ADDRBUS_SHIFT + AS_IO: info->i = 0; break;
-
- case CPUINFO_INT_INPUT_STATE + SH2_INT_VBLIN: info->i = sh2->irq_line_state[SH2_INT_VBLIN]; break;
- case CPUINFO_INT_INPUT_STATE + SH2_INT_VBLOUT: info->i = sh2->irq_line_state[SH2_INT_VBLOUT]; break;
- case CPUINFO_INT_INPUT_STATE + SH2_INT_HBLIN: info->i = sh2->irq_line_state[SH2_INT_HBLIN]; break;
- case CPUINFO_INT_INPUT_STATE + SH2_INT_TIMER0: info->i = sh2->irq_line_state[SH2_INT_TIMER0]; break;
- case CPUINFO_INT_INPUT_STATE + SH2_INT_TIMER1: info->i = sh2->irq_line_state[SH2_INT_TIMER1]; break;
- case CPUINFO_INT_INPUT_STATE + SH2_INT_DSP: info->i = sh2->irq_line_state[SH2_INT_DSP]; break;
- case CPUINFO_INT_INPUT_STATE + SH2_INT_SOUND: info->i = sh2->irq_line_state[SH2_INT_SOUND]; break;
- case CPUINFO_INT_INPUT_STATE + SH2_INT_SMPC: info->i = sh2->irq_line_state[SH2_INT_SMPC]; break;
- case CPUINFO_INT_INPUT_STATE + SH2_INT_PAD: info->i = sh2->irq_line_state[SH2_INT_PAD]; break;
- case CPUINFO_INT_INPUT_STATE + SH2_INT_DMA2: info->i = sh2->irq_line_state[SH2_INT_DMA2]; break;
- case CPUINFO_INT_INPUT_STATE + SH2_INT_DMA1: info->i = sh2->irq_line_state[SH2_INT_DMA1]; break;
- case CPUINFO_INT_INPUT_STATE + SH2_INT_DMA0: info->i = sh2->irq_line_state[SH2_INT_DMA0]; break;
- case CPUINFO_INT_INPUT_STATE + SH2_INT_DMAILL: info->i = sh2->irq_line_state[SH2_INT_DMAILL]; break;
- case CPUINFO_INT_INPUT_STATE + SH2_INT_SPRITE: info->i = sh2->irq_line_state[SH2_INT_SPRITE]; break;
- case CPUINFO_INT_INPUT_STATE + SH2_INT_14: info->i = sh2->irq_line_state[SH2_INT_14]; break;
- case CPUINFO_INT_INPUT_STATE + SH2_INT_15: info->i = sh2->irq_line_state[SH2_INT_15]; break;
- case CPUINFO_INT_INPUT_STATE + SH2_INT_ABUS: info->i = sh2->irq_line_state[SH2_INT_ABUS]; break;
- case CPUINFO_INT_INPUT_STATE + INPUT_LINE_NMI: info->i = sh2->nmi_line_state; break;
-
- case CPUINFO_INT_PREVIOUSPC: info->i = sh2->ppc; break;
-
- case CPUINFO_INT_PC:
- case CPUINFO_INT_REGISTER + SH2_PC: info->i = (sh2->delay) ? (sh2->delay & AM) : (sh2->pc & AM); break;
- case CPUINFO_INT_SP: info->i = sh2->r[15]; break;
- case CPUINFO_INT_REGISTER + SH2_PR: info->i = sh2->pr; break;
- case CPUINFO_INT_REGISTER + SH2_SR: info->i = sh2->sr; break;
- case CPUINFO_INT_REGISTER + SH2_GBR: info->i = sh2->gbr; break;
- case CPUINFO_INT_REGISTER + SH2_VBR: info->i = sh2->vbr; break;
- case CPUINFO_INT_REGISTER + SH2_MACH: info->i = sh2->mach; break;
- case CPUINFO_INT_REGISTER + SH2_MACL: info->i = sh2->macl; break;
- case CPUINFO_INT_REGISTER + SH2_R0: info->i = sh2->r[ 0]; break;
- case CPUINFO_INT_REGISTER + SH2_R1: info->i = sh2->r[ 1]; break;
- case CPUINFO_INT_REGISTER + SH2_R2: info->i = sh2->r[ 2]; break;
- case CPUINFO_INT_REGISTER + SH2_R3: info->i = sh2->r[ 3]; break;
- case CPUINFO_INT_REGISTER + SH2_R4: info->i = sh2->r[ 4]; break;
- case CPUINFO_INT_REGISTER + SH2_R5: info->i = sh2->r[ 5]; break;
- case CPUINFO_INT_REGISTER + SH2_R6: info->i = sh2->r[ 6]; break;
- case CPUINFO_INT_REGISTER + SH2_R7: info->i = sh2->r[ 7]; break;
- case CPUINFO_INT_REGISTER + SH2_R8: info->i = sh2->r[ 8]; break;
- case CPUINFO_INT_REGISTER + SH2_R9: info->i = sh2->r[ 9]; break;
- case CPUINFO_INT_REGISTER + SH2_R10: info->i = sh2->r[10]; break;
- case CPUINFO_INT_REGISTER + SH2_R11: info->i = sh2->r[11]; break;
- case CPUINFO_INT_REGISTER + SH2_R12: info->i = sh2->r[12]; break;
- case CPUINFO_INT_REGISTER + SH2_R13: info->i = sh2->r[13]; break;
- case CPUINFO_INT_REGISTER + SH2_R14: info->i = sh2->r[14]; break;
- case CPUINFO_INT_REGISTER + SH2_R15: info->i = sh2->r[15]; break;
- case CPUINFO_INT_REGISTER + SH2_EA: info->i = sh2->ea; break;
-
- /* --- the following bits of info are returned as pointers to data or functions --- */
- case CPUINFO_FCT_SET_INFO: info->setinfo = CPU_SET_INFO_NAME(sh2); break;
- case CPUINFO_FCT_INIT: info->init = CPU_INIT_NAME(sh2); break;
- case CPUINFO_FCT_RESET: info->reset = CPU_RESET_NAME(sh2); break;
- case CPUINFO_FCT_EXECUTE: info->execute = CPU_EXECUTE_NAME(sh2); break;
- case CPUINFO_FCT_BURN: info->burn = NULL; break;
- case CPUINFO_FCT_DISASSEMBLE: info->disassemble = CPU_DISASSEMBLE_NAME(sh2); break;
- case CPUINFO_PTR_INSTRUCTION_COUNTER: info->icount = &sh2->icount; break;
-
- /* --- the following bits of info are returned as NULL-terminated strings --- */
- case CPUINFO_STR_NAME: strcpy(info->s, "SH-2"); break;
- case CPUINFO_STR_SHORTNAME: strcpy(info->s, "sh2"); break;
- case CPUINFO_STR_FAMILY: strcpy(info->s, "Hitachi SH7600"); break;
- case CPUINFO_STR_VERSION: strcpy(info->s, "1.01"); break;
- case CPUINFO_STR_SOURCE_FILE: strcpy(info->s, __FILE__); break;
- case CPUINFO_STR_CREDITS: strcpy(info->s, "Copyright Juergen Buchmueller, all rights reserved."); break;
-
- case CPUINFO_STR_FLAGS:
- sprintf(info->s, "%c%c%d%c%c",
- sh2->sr & M ? 'M':'.',
- sh2->sr & Q ? 'Q':'.',
- (sh2->sr & I) >> 4,
- sh2->sr & S ? 'S':'.',
- sh2->sr & T ? 'T':'.');
+ case SH2_PC:
+ m_sh2_state->pc = m_debugger_temp;
+ m_delay = 0;
break;
- case CPUINFO_STR_REGISTER + SH2_PC: sprintf(info->s, "PC :%08X", sh2->pc); break;
- case CPUINFO_STR_REGISTER + SH2_SR: sprintf(info->s, "SR :%08X", sh2->sr); break;
- case CPUINFO_STR_REGISTER + SH2_PR: sprintf(info->s, "PR :%08X", sh2->pr); break;
- case CPUINFO_STR_REGISTER + SH2_GBR: sprintf(info->s, "GBR :%08X", sh2->gbr); break;
- case CPUINFO_STR_REGISTER + SH2_VBR: sprintf(info->s, "VBR :%08X", sh2->vbr); break;
- case CPUINFO_STR_REGISTER + SH2_MACH: sprintf(info->s, "MACH:%08X", sh2->mach); break;
- case CPUINFO_STR_REGISTER + SH2_MACL: sprintf(info->s, "MACL:%08X", sh2->macl); break;
- case CPUINFO_STR_REGISTER + SH2_R0: sprintf(info->s, "R0 :%08X", sh2->r[ 0]); break;
- case CPUINFO_STR_REGISTER + SH2_R1: sprintf(info->s, "R1 :%08X", sh2->r[ 1]); break;
- case CPUINFO_STR_REGISTER + SH2_R2: sprintf(info->s, "R2 :%08X", sh2->r[ 2]); break;
- case CPUINFO_STR_REGISTER + SH2_R3: sprintf(info->s, "R3 :%08X", sh2->r[ 3]); break;
- case CPUINFO_STR_REGISTER + SH2_R4: sprintf(info->s, "R4 :%08X", sh2->r[ 4]); break;
- case CPUINFO_STR_REGISTER + SH2_R5: sprintf(info->s, "R5 :%08X", sh2->r[ 5]); break;
- case CPUINFO_STR_REGISTER + SH2_R6: sprintf(info->s, "R6 :%08X", sh2->r[ 6]); break;
- case CPUINFO_STR_REGISTER + SH2_R7: sprintf(info->s, "R7 :%08X", sh2->r[ 7]); break;
- case CPUINFO_STR_REGISTER + SH2_R8: sprintf(info->s, "R8 :%08X", sh2->r[ 8]); break;
- case CPUINFO_STR_REGISTER + SH2_R9: sprintf(info->s, "R9 :%08X", sh2->r[ 9]); break;
- case CPUINFO_STR_REGISTER + SH2_R10: sprintf(info->s, "R10 :%08X", sh2->r[10]); break;
- case CPUINFO_STR_REGISTER + SH2_R11: sprintf(info->s, "R11 :%08X", sh2->r[11]); break;
- case CPUINFO_STR_REGISTER + SH2_R12: sprintf(info->s, "R12 :%08X", sh2->r[12]); break;
- case CPUINFO_STR_REGISTER + SH2_R13: sprintf(info->s, "R13 :%08X", sh2->r[13]); break;
- case CPUINFO_STR_REGISTER + SH2_R14: sprintf(info->s, "R14 :%08X", sh2->r[14]); break;
- case CPUINFO_STR_REGISTER + SH2_R15: sprintf(info->s, "R15 :%08X", sh2->r[15]); break;
- case CPUINFO_STR_REGISTER + SH2_EA: sprintf(info->s, "EA :%08X", sh2->ea); break;
+ case SH2_SR:
+ CHECK_PENDING_IRQ("sh2_set_reg");
+ break;
+ }
+}
+
+void sh2_device::state_export(const device_state_entry &entry)
+{
+ switch (entry.index())
+ {
+ case SH2_PC:
+ m_debugger_temp = (m_delay) ? (m_delay & AM) : (m_sh2_state->pc & AM);
+ break;
}
}
-CPU_GET_INFO( sh1_int )
+
+void sh2_device::execute_set_input(int irqline, int state)
{
- switch (state)
+ if (irqline == INPUT_LINE_NMI)
{
- /* --- the following bits of info are returned as pointers to data or functions --- */
- case CPUINFO_FCT_RESET: info->reset = CPU_RESET_NAME(sh1); break;
+ if (m_nmi_line_state == state)
+ return;
+ m_nmi_line_state = state;
+
+ if( state == CLEAR_LINE )
+ {
+ LOG(("SH-2 '%s' cleared nmi\n", tag()));
+ }
+ else
+ {
+ LOG(("SH-2 '%s' assert nmi\n", tag()));
- /* --- the following bits of info are returned as NULL-terminated strings --- */
- case CPUINFO_STR_NAME: strcpy(info->s, "SH-1"); break;
- case CPUINFO_STR_SHORTNAME: strcpy(info->s, "sh1"); break;
+ sh2_exception("Set IRQ line", 16);
- default: CPU_GET_INFO_CALL(sh2_int); break;
+ if (m_isdrc)
+ m_sh2_state->pending_nmi = 1;
+ }
}
-}
+ else
+ {
+ if (m_irq_line_state[irqline] == state)
+ return;
+ m_irq_line_state[irqline] = state;
-DEFINE_LEGACY_CPU_DEVICE(SH1_INT, sh1_int);
-DEFINE_LEGACY_CPU_DEVICE(SH2_INT, sh2_int);
+ if( state == CLEAR_LINE )
+ {
+ LOG(("SH-2 '%s' cleared irq #%d\n", tag(), irqline));
+ m_sh2_state->pending_irq &= ~(1 << irqline);
+ }
+ else
+ {
+ LOG(("SH-2 '%s' assert irq #%d\n", tag(), irqline));
+ m_sh2_state->pending_irq |= 1 << irqline;
+ if (m_isdrc)
+ {
+ m_test_irq = 1;
+ } else {
+ if(m_delay)
+ m_test_irq = 1;
+ else
+ CHECK_PENDING_IRQ("sh2_set_irq_line");
+ }
+ }
+ }
+}
+#include "sh2comn.c"
+#include "sh2drc.c"
-const device_type SH1 = &legacy_device_creator_drc<sh1_int_device, sh1_drc_device>;
-const device_type SH2 = &legacy_device_creator_drc<sh2_int_device, sh2_drc_device>;
diff --git a/src/emu/cpu/sh2/sh2.h b/src/emu/cpu/sh2/sh2.h
index 8f6a32194cd..f73ef8830d6 100644
--- a/src/emu/cpu/sh2/sh2.h
+++ b/src/emu/cpu/sh2/sh2.h
@@ -30,6 +30,9 @@
#ifndef __SH2_H__
#define __SH2_H__
+#include "cpu/drcfe.h"
+#include "cpu/drcuml.h"
+
#define SH2_INT_NONE -1
#define SH2_INT_VBLIN 0
@@ -64,19 +67,6 @@ struct sh2_cpu_core
int (*dma_callback_fifo_data_available)(device_t *device, UINT32 src, UINT32 dst, UINT32 data, int size);
};
-DECLARE_LEGACY_CPU_DEVICE(SH1_INT, sh1_int);
-DECLARE_LEGACY_CPU_DEVICE(SH2_INT, sh2_int);
-DECLARE_LEGACY_CPU_DEVICE(SH1_DRC, sh1_drc);
-DECLARE_LEGACY_CPU_DEVICE(SH2_DRC, sh2_drc);
-
-extern const device_type SH1;
-extern const device_type SH2;
-
-DECLARE_WRITE32_HANDLER( sh2_internal_w );
-DECLARE_READ32_HANDLER( sh2_internal_r );
-
-void sh2_set_ftcsr_read_callback(device_t *device, void (*callback)(UINT32));
-void sh2_set_frt_input(device_t *device, int state);
/***************************************************************************
COMPILER-SPECIFIC OPTIONS
@@ -103,8 +93,435 @@ enum
#define SH2_MAX_FASTRAM 4
-void sh2drc_set_options(device_t *device, UINT32 options);
-void sh2drc_add_pcflush(device_t *device, offs_t address);
-void sh2drc_add_fastram(device_t *device, offs_t start, offs_t end, UINT8 readonly, void *base);
+class sh2_frontend;
+
+class sh2_device : public cpu_device
+ , public sh2_cpu_core
+{
+ friend class sh2_frontend;
+
+public:
+ // construction/destruction
+ sh2_device(const machine_config &mconfig, const char *_tag, device_t *_owner, UINT32 _clock);
+ sh2_device(const machine_config &mconfig, device_type type, const char *name, const char *tag, device_t *owner, UINT32 clock, const char *shortname, const char *source, int cpu_type);
+
+ DECLARE_WRITE32_MEMBER( sh2_internal_w );
+ DECLARE_READ32_MEMBER( sh2_internal_r );
+ DECLARE_READ32_MEMBER(sh2_internal_a5);
+
+ void sh2_set_ftcsr_read_callback(void (*callback)(UINT32));
+ void sh2_set_frt_input(int state);
+ void sh2drc_set_options(UINT32 options);
+ void sh2drc_add_pcflush(offs_t address);
+ void sh2drc_add_fastram(offs_t start, offs_t end, UINT8 readonly, void *base);
+
+ void sh2_notify_dma_data_available();
+
+protected:
+ // device-level overrides
+ virtual void device_config_complete();
+ virtual void device_start();
+ virtual void device_reset();
+ virtual void device_stop();
+
+ // device_execute_interface overrides
+ virtual UINT32 execute_min_cycles() const { return 1; }
+ virtual UINT32 execute_max_cycles() const { return 4; }
+ virtual UINT32 execute_input_lines() const { return 16; }
+ virtual UINT32 execute_default_irq_vector() const { return 0; }
+ virtual void execute_run();
+ virtual void execute_set_input(int inputnum, int state);
+
+ // device_memory_interface overrides
+ virtual const address_space_config *memory_space_config(address_spacenum spacenum = AS_0) const { return (spacenum == AS_PROGRAM) ? &m_program_config : NULL; }
+
+ // device_state_interface overrides
+ virtual void state_import(const device_state_entry &entry);
+ virtual void state_export(const device_state_entry &entry);
+ void state_string_export(const device_state_entry &entry, astring &string);
+
+ // device_disasm_interface overrides
+ virtual UINT32 disasm_min_opcode_bytes() const { return 2; }
+ virtual UINT32 disasm_max_opcode_bytes() const { return 2; }
+ virtual offs_t disasm_disassemble(char *buffer, offs_t pc, const UINT8 *oprom, const UINT8 *opram, UINT32 options);
+
+private:
+ address_space_config m_program_config;
+
+ // Data that needs to be stored close to the generated DRC code
+ struct internal_sh2_state
+ {
+ UINT32 ppc;
+ UINT32 pc;
+ UINT32 pr;
+ UINT32 sr;
+ UINT32 gbr;
+ UINT32 vbr;
+ UINT32 mach;
+ UINT32 macl;
+ UINT32 r[16];
+ UINT32 ea;
+ UINT32 pending_irq;
+ UINT32 pending_nmi;
+ INT32 irqline;
+ UINT32 evec; // exception vector for DRC
+ UINT32 irqsr; // IRQ-time old SR for DRC
+ UINT32 target; // target for jmp/jsr/etc so the delay slot can't kill it
+ int internal_irq_level;
+ int icount;
+ UINT8 sleep_mode;
+ UINT32 arg0; /* print_debug argument 1 */
+ };
+
+ UINT32 m_delay;
+ UINT32 m_cpu_off;
+ UINT32 m_dvsr, m_dvdnth, m_dvdntl, m_dvcr;
+ UINT32 m_test_irq;
+ struct
+ {
+ int irq_vector;
+ int irq_priority;
+ } m_irq_queue[16];
+
+ bool m_isdrc;
+
+ int m_pcfsel; // last pcflush entry set
+ int m_maxpcfsel; // highest valid pcflush entry
+ UINT32 m_pcflushes[16]; // pcflush entries
+
+ INT8 m_irq_line_state[17];
+ address_space *m_program;
+protected:
+ direct_read_data *m_direct;
+private:
+ address_space *m_internal;
+ UINT32 m_m[0x200/4];
+ INT8 m_nmi_line_state;
+
+ UINT16 m_frc;
+ UINT16 m_ocra, m_ocrb, m_icr;
+ UINT64 m_frc_base;
+
+ int m_frt_input;
+ int m_internal_irq_vector;
+
+ emu_timer *m_timer;
+ emu_timer *m_dma_current_active_timer[2];
+ int m_dma_timer_active[2];
+ UINT8 m_dma_irq[2];
+
+ int m_active_dma_incs[2];
+ int m_active_dma_incd[2];
+ int m_active_dma_size[2];
+ int m_active_dma_steal[2];
+ UINT32 m_active_dma_src[2];
+ UINT32 m_active_dma_dst[2];
+ UINT32 m_active_dma_count[2];
+ UINT16 m_wtcnt;
+ UINT8 m_wtcsr;
+
+ int m_is_slave, m_cpu_type;
+ int (*m_dma_callback_kludge)(device_t *device, UINT32 src, UINT32 dst, UINT32 data, int size);
+ int (*m_dma_callback_fifo_data_available)(device_t *device, UINT32 src, UINT32 dst, UINT32 data, int size);
+
+ void (*m_ftcsr_read_callback)(UINT32 data);
+
+ drc_cache m_cache; /* pointer to the DRC code cache */
+ drcuml_state * m_drcuml; /* DRC UML generator state */
+ sh2_frontend * m_drcfe; /* pointer to the DRC front-end state */
+ UINT32 m_drcoptions; /* configurable DRC options */
+
+ internal_sh2_state *m_sh2_state;
+
+ /* internal stuff */
+ UINT8 m_cache_dirty; /* true if we need to flush the cache */
+
+ /* parameters for subroutines */
+ UINT64 m_numcycles; /* return value from gettotalcycles */
+ UINT32 m_arg1; /* print_debug argument 2 */
+ UINT32 m_irq; /* irq we're taking */
+
+ /* register mappings */
+ uml::parameter m_regmap[16]; /* parameter to register mappings for all 16 integer registers */
+
+ uml::code_handle * m_entry; /* entry point */
+ uml::code_handle * m_read8; /* read byte */
+ uml::code_handle * m_write8; /* write byte */
+ uml::code_handle * m_read16; /* read half */
+ uml::code_handle * m_write16; /* write half */
+ uml::code_handle * m_read32; /* read word */
+ uml::code_handle * m_write32; /* write word */
+
+ uml::code_handle * m_interrupt; /* interrupt */
+ uml::code_handle * m_nocode; /* nocode */
+ uml::code_handle * m_out_of_cycles; /* out of cycles exception handler */
+
+ /* fast RAM */
+ UINT32 m_fastram_select;
+ struct
+ {
+ offs_t start; /* start of the RAM block */
+ offs_t end; /* end of the RAM block */
+ UINT8 readonly; /* TRUE if read-only */
+ void * base; /* base in memory where the RAM lives */
+ } m_fastram[SH2_MAX_FASTRAM];
+
+ UINT32 m_debugger_temp;
+
+ inline UINT8 RB(offs_t A);
+ inline UINT16 RW(offs_t A);
+ inline UINT32 RL(offs_t A);
+ inline void WB(offs_t A, UINT8 V);
+ inline void WW(offs_t A, UINT16 V);
+ inline void WL(offs_t A, UINT32 V);
+ inline void ADD(UINT32 m, UINT32 n);
+ inline void ADDI(UINT32 i, UINT32 n);
+ inline void ADDC(UINT32 m, UINT32 n);
+ inline void ADDV(UINT32 m, UINT32 n);
+ inline void AND(UINT32 m, UINT32 n);
+ inline void ANDI(UINT32 i);
+ inline void ANDM(UINT32 i);
+ inline void BF(UINT32 d);
+ inline void BFS(UINT32 d);
+ inline void BRA(UINT32 d);
+ inline void BRAF(UINT32 m);
+ inline void BSR(UINT32 d);
+ inline void BSRF(UINT32 m);
+ inline void BT(UINT32 d);
+ inline void BTS(UINT32 d);
+ inline void CLRMAC();
+ inline void CLRT();
+ inline void CMPEQ(UINT32 m, UINT32 n);
+ inline void CMPGE(UINT32 m, UINT32 n);
+ inline void CMPGT(UINT32 m, UINT32 n);
+ inline void CMPHI(UINT32 m, UINT32 n);
+ inline void CMPHS(UINT32 m, UINT32 n);
+ inline void CMPPL(UINT32 n);
+ inline void CMPPZ(UINT32 n);
+ inline void CMPSTR(UINT32 m, UINT32 n);
+ inline void CMPIM(UINT32 i);
+ inline void DIV0S(UINT32 m, UINT32 n);
+ inline void DIV0U();
+ inline void DIV1(UINT32 m, UINT32 n);
+ inline void DMULS(UINT32 m, UINT32 n);
+ inline void DMULU(UINT32 m, UINT32 n);
+ inline void DT(UINT32 n);
+ inline void EXTSB(UINT32 m, UINT32 n);
+ inline void EXTSW(UINT32 m, UINT32 n);
+ inline void EXTUB(UINT32 m, UINT32 n);
+ inline void EXTUW(UINT32 m, UINT32 n);
+ inline void ILLEGAL();
+ inline void JMP(UINT32 m);
+ inline void JSR(UINT32 m);
+ inline void LDCSR(UINT32 m);
+ inline void LDCGBR(UINT32 m);
+ inline void LDCVBR(UINT32 m);
+ inline void LDCMSR(UINT32 m);
+ inline void LDCMGBR(UINT32 m);
+ inline void LDCMVBR(UINT32 m);
+ inline void LDSMACH(UINT32 m);
+ inline void LDSMACL(UINT32 m);
+ inline void LDSPR(UINT32 m);
+ inline void LDSMMACH(UINT32 m);
+ inline void LDSMMACL(UINT32 m);
+ inline void LDSMPR(UINT32 m);
+ inline void MAC_L(UINT32 m, UINT32 n);
+ inline void MAC_W(UINT32 m, UINT32 n);
+ inline void MOV(UINT32 m, UINT32 n);
+ inline void MOVBS(UINT32 m, UINT32 n);
+ inline void MOVWS(UINT32 m, UINT32 n);
+ inline void MOVLS(UINT32 m, UINT32 n);
+ inline void MOVBL(UINT32 m, UINT32 n);
+ inline void MOVWL(UINT32 m, UINT32 n);
+ inline void MOVLL(UINT32 m, UINT32 n);
+ inline void MOVBM(UINT32 m, UINT32 n);
+ inline void MOVWM(UINT32 m, UINT32 n);
+ inline void MOVLM(UINT32 m, UINT32 n);
+ inline void MOVBP(UINT32 m, UINT32 n);
+ inline void MOVWP(UINT32 m, UINT32 n);
+ inline void MOVLP(UINT32 m, UINT32 n);
+ inline void MOVBS0(UINT32 m, UINT32 n);
+ inline void MOVWS0(UINT32 m, UINT32 n);
+ inline void MOVLS0(UINT32 m, UINT32 n);
+ inline void MOVBL0(UINT32 m, UINT32 n);
+ inline void MOVWL0(UINT32 m, UINT32 n);
+ inline void MOVLL0(UINT32 m, UINT32 n);
+ inline void MOVI(UINT32 i, UINT32 n);
+ inline void MOVWI(UINT32 d, UINT32 n);
+ inline void MOVLI(UINT32 d, UINT32 n);
+ inline void MOVBLG(UINT32 d);
+ inline void MOVWLG(UINT32 d);
+ inline void MOVLLG(UINT32 d);
+ inline void MOVBSG(UINT32 d);
+ inline void MOVWSG(UINT32 d);
+ inline void MOVLSG(UINT32 d);
+ inline void MOVBS4(UINT32 d, UINT32 n);
+ inline void MOVWS4(UINT32 d, UINT32 n);
+ inline void MOVLS4(UINT32 m, UINT32 d, UINT32 n);
+ inline void MOVBL4(UINT32 m, UINT32 d);
+ inline void MOVWL4(UINT32 m, UINT32 d);
+ inline void MOVLL4(UINT32 m, UINT32 d, UINT32 n);
+ inline void MOVA(UINT32 d);
+ inline void MOVT(UINT32 n);
+ inline void MULL(UINT32 m, UINT32 n);
+ inline void MULS(UINT32 m, UINT32 n);
+ inline void MULU(UINT32 m, UINT32 n);
+ inline void NEG(UINT32 m, UINT32 n);
+ inline void NEGC(UINT32 m, UINT32 n);
+ inline void NOP(void);
+ inline void NOT(UINT32 m, UINT32 n);
+ inline void OR(UINT32 m, UINT32 n);
+ inline void ORI(UINT32 i);
+ inline void ORM(UINT32 i);
+ inline void ROTCL(UINT32 n);
+ inline void ROTCR(UINT32 n);
+ inline void ROTL(UINT32 n);
+ inline void ROTR(UINT32 n);
+ inline void RTE();
+ inline void RTS();
+ inline void SETT();
+ inline void SHAL(UINT32 n);
+ inline void SHAR(UINT32 n);
+ inline void SHLL(UINT32 n);
+ inline void SHLL2(UINT32 n);
+ inline void SHLL8(UINT32 n);
+ inline void SHLL16(UINT32 n);
+ inline void SHLR(UINT32 n);
+ inline void SHLR2(UINT32 n);
+ inline void SHLR8(UINT32 n);
+ inline void SHLR16(UINT32 n);
+ inline void SLEEP();
+ inline void STCSR(UINT32 n);
+ inline void STCGBR(UINT32 n);
+ inline void STCVBR(UINT32 n);
+ inline void STCMSR(UINT32 n);
+ inline void STCMGBR(UINT32 n);
+ inline void STCMVBR(UINT32 n);
+ inline void STSMACH(UINT32 n);
+ inline void STSMACL(UINT32 n);
+ inline void STSPR(UINT32 n);
+ inline void STSMMACH(UINT32 n);
+ inline void STSMMACL(UINT32 n);
+ inline void STSMPR(UINT32 n);
+ inline void SUB(UINT32 m, UINT32 n);
+ inline void SUBC(UINT32 m, UINT32 n);
+ inline void SUBV(UINT32 m, UINT32 n);
+ inline void SWAPB(UINT32 m, UINT32 n);
+ inline void SWAPW(UINT32 m, UINT32 n);
+ inline void TAS(UINT32 n);
+ inline void TRAPA(UINT32 i);
+ inline void TST(UINT32 m, UINT32 n);
+ inline void TSTI(UINT32 i);
+ inline void TSTM(UINT32 i);
+ inline void XOR(UINT32 m, UINT32 n);
+ inline void XORI(UINT32 i);
+ inline void XORM(UINT32 i);
+ inline void XTRCT(UINT32 m, UINT32 n);
+ inline void op0000(UINT16 opcode);
+ inline void op0001(UINT16 opcode);
+ inline void op0010(UINT16 opcode);
+ inline void op0011(UINT16 opcode);
+ inline void op0100(UINT16 opcode);
+ inline void op0101(UINT16 opcode);
+ inline void op0110(UINT16 opcode);
+ inline void op0111(UINT16 opcode);
+ inline void op1000(UINT16 opcode);
+ inline void op1001(UINT16 opcode);
+ inline void op1010(UINT16 opcode);
+ inline void op1011(UINT16 opcode);
+ inline void op1100(UINT16 opcode);
+ inline void op1101(UINT16 opcode);
+ inline void op1110(UINT16 opcode);
+ inline void op1111(UINT16 opcode);
+ TIMER_CALLBACK_MEMBER( sh2_timer_callback );
+ TIMER_CALLBACK_MEMBER( sh2_dma_current_active_callback );
+ void sh2_timer_resync();
+ void sh2_timer_activate();
+ void sh2_do_dma(int dma);
+ void sh2_exception(const char *message, int irqline);
+ void sh2_dmac_check(int dma);
+ void sh2_recalc_irq();
+
+ /* internal compiler state */
+ struct compiler_state
+ {
+ UINT32 cycles; /* accumulated cycles */
+ UINT8 checkints; /* need to check interrupts before next instruction */
+ uml::code_label labelnum; /* index for local labels */
+ };
+
+ inline UINT32 epc(const opcode_desc *desc);
+ inline void alloc_handle(drcuml_state *drcuml, uml::code_handle **handleptr, const char *name);
+ inline void load_fast_iregs(drcuml_block *block);
+ inline void save_fast_iregs(drcuml_block *block);
+
+ void code_flush_cache();
+ void execute_run_drc();
+ void code_compile_block(UINT8 mode, offs_t pc);
+ void static_generate_entry_point();
+ void static_generate_nocode_handler();
+ void static_generate_out_of_cycles();
+ void static_generate_memory_accessor(int size, int iswrite, const char *name, uml::code_handle **handleptr);
+ const char *log_desc_flags_to_string(UINT32 flags);
+ void log_register_list(drcuml_state *drcuml, const char *string, const UINT32 *reglist, const UINT32 *regnostarlist);
+ void log_opcode_desc(drcuml_state *drcuml, const opcode_desc *desclist, int indent);
+ void log_add_disasm_comment(drcuml_block *block, UINT32 pc, UINT32 op);
+ void generate_update_cycles(drcuml_block *block, compiler_state *compiler, uml::parameter param, int allow_exception);
+ void generate_checksum_block(drcuml_block *block, compiler_state *compiler, const opcode_desc *seqhead, const opcode_desc *seqlast);
+ void generate_sequence_instruction(drcuml_block *block, compiler_state *compiler, const opcode_desc *desc, UINT32 ovrpc);
+ void generate_delay_slot(drcuml_block *block, compiler_state *compiler, const opcode_desc *desc, UINT32 ovrpc);
+ int generate_opcode(drcuml_block *block, compiler_state *compiler, const opcode_desc *desc, UINT32 ovrpc);
+ int generate_group_0(drcuml_block *block, compiler_state *compiler, const opcode_desc *desc, UINT16 opcode, int in_delay_slot, UINT32 ovrpc);
+ int generate_group_2(drcuml_block *block, compiler_state *compiler, const opcode_desc *desc, UINT16 opcode, int in_delay_slot, UINT32 ovrpc);
+ int generate_group_3(drcuml_block *block, compiler_state *compiler, const opcode_desc *desc, UINT16 opcode, UINT32 ovrpc);
+ int generate_group_4(drcuml_block *block, compiler_state *compiler, const opcode_desc *desc, UINT16 opcode, int in_delay_slot, UINT32 ovrpc);
+ int generate_group_6(drcuml_block *block, compiler_state *compiler, const opcode_desc *desc, UINT16 opcode, int in_delay_slot, UINT32 ovrpc);
+ int generate_group_8(drcuml_block *block, compiler_state *compiler, const opcode_desc *desc, UINT16 opcode, int in_delay_slot, UINT32 ovrpc);
+ int generate_group_12(drcuml_block *block, compiler_state *compiler, const opcode_desc *desc, UINT16 opcode, int in_delay_slot, UINT32 ovrpc);
+
+public:
+ void func_printf_probe();
+ void func_unimplemented();
+ void func_fastirq();
+ void func_MAC_W();
+ void func_MAC_L();
+ void func_DIV1();
+ void func_ADDV();
+ void func_SUBV();
+};
+
+
+class sh1_device : public sh2_device
+{
+public:
+ // construction/destruction
+ sh1_device(const machine_config &mconfig, const char *_tag, device_t *_owner, UINT32 _clock);
+};
+
+
+class sh2_frontend : public drc_frontend
+{
+public:
+ sh2_frontend(sh2_device *device, UINT32 window_start, UINT32 window_end, UINT32 max_sequence);
+
+protected:
+ virtual bool describe(opcode_desc &desc, const opcode_desc *prev);
+
+private:
+ bool describe_group_0(opcode_desc &desc, const opcode_desc *prev, UINT16 opcode);
+ bool describe_group_2(opcode_desc &desc, const opcode_desc *prev, UINT16 opcode);
+ bool describe_group_3(opcode_desc &desc, const opcode_desc *prev, UINT16 opcode);
+ bool describe_group_4(opcode_desc &desc, const opcode_desc *prev, UINT16 opcode);
+ bool describe_group_6(opcode_desc &desc, const opcode_desc *prev, UINT16 opcode);
+ bool describe_group_8(opcode_desc &desc, const opcode_desc *prev, UINT16 opcode);
+ bool describe_group_12(opcode_desc &desc, const opcode_desc *prev, UINT16 opcode);
+
+ sh2_device *m_sh2;
+};
+
+
+extern const device_type SH1;
+extern const device_type SH2;
+
#endif /* __SH2_H__ */
diff --git a/src/emu/cpu/sh2/sh2comn.c b/src/emu/cpu/sh2/sh2comn.c
index 14679b27aa2..0ca03f2d788 100644
--- a/src/emu/cpu/sh2/sh2comn.c
+++ b/src/emu/cpu/sh2/sh2comn.c
@@ -17,138 +17,86 @@
#define LOG(x) do { if (VERBOSE) logerror x; } while (0)
-INLINE sh2_state *GET_SH2(device_t *dev)
-{
- if (dev->machine().options().drc()) {
- return *(sh2_state **)downcast<legacy_cpu_device *>(dev)->token();
- } else {
- return (sh2_state *)downcast<legacy_cpu_device *>(dev)->token();
- }
-}
-
static const int div_tab[4] = { 3, 5, 7, 0 };
-INLINE UINT32 RL(sh2_state *sh2, offs_t A)
-{
- if (A >= 0xe0000000) /* I/O */
- return sh2_internal_r(*sh2->internal, (A & 0x1fc)>>2, 0xffffffff);
-
- if (A >= 0xc0000000) /* Cache Data Array */
- return sh2->program->read_dword(A);
-
- /* 0x60000000 Cache Address Data Array */
- if (A >= 0x40000000) /* Cache Associative Purge Area */
- return 0xa5a5a5a5;
-
- /* 0x20000000 no Cache */
- /* 0x00000000 read thru Cache if CE bit is 1 */
- return sh2->program->read_dword(A & AM);
-}
-
-INLINE void WL(sh2_state *sh2, offs_t A, UINT32 V)
+void sh2_device::sh2_timer_resync()
{
- if (A >= 0xe0000000) /* I/O */
- {
- sh2_internal_w(*sh2->internal, (A & 0x1fc)>>2, V, 0xffffffff);
- return;
- }
-
- if (A >= 0xc0000000) /* Cache Data Array */
- {
- sh2->program->write_dword(A,V);
- return;
- }
-
- /* 0x60000000 Cache Address Data Array */
-
- if (A >= 0x40000000) /* Cache Associative Purge Area */
- return;
-
- /* 0x20000000 no Cache */
- /* 0x00000000 read thru Cache if CE bit is 1 */
- sh2->program->write_dword(A & AM,V);
-}
-
-static void sh2_timer_resync(sh2_state *sh2)
-{
- int divider = div_tab[(sh2->m[5] >> 8) & 3];
- UINT64 cur_time = sh2->device->total_cycles();
- UINT64 add = (cur_time - sh2->frc_base) >> divider;
+ int divider = div_tab[(m_m[5] >> 8) & 3];
+ UINT64 cur_time = total_cycles();
+ UINT64 add = (cur_time - m_frc_base) >> divider;
if (add > 0)
{
if(divider)
- sh2->frc += add;
+ m_frc += add;
- sh2->frc_base = cur_time;
+ m_frc_base = cur_time;
}
}
-static void sh2_timer_activate(sh2_state *sh2)
+void sh2_device::sh2_timer_activate()
{
int max_delta = 0xfffff;
UINT16 frc;
- sh2->timer->adjust(attotime::never);
+ m_timer->adjust(attotime::never);
- frc = sh2->frc;
- if(!(sh2->m[4] & OCFA)) {
- UINT16 delta = sh2->ocra - frc;
+ frc = m_frc;
+ if(!(m_m[4] & OCFA)) {
+ UINT16 delta = m_ocra - frc;
if(delta < max_delta)
max_delta = delta;
}
- if(!(sh2->m[4] & OCFB) && (sh2->ocra <= sh2->ocrb || !(sh2->m[4] & 0x010000))) {
- UINT16 delta = sh2->ocrb - frc;
+ if(!(m_m[4] & OCFB) && (m_ocra <= m_ocrb || !(m_m[4] & 0x010000))) {
+ UINT16 delta = m_ocrb - frc;
if(delta < max_delta)
max_delta = delta;
}
- if(!(sh2->m[4] & OVF) && !(sh2->m[4] & 0x010000)) {
+ if(!(m_m[4] & OVF) && !(m_m[4] & 0x010000)) {
int delta = 0x10000 - frc;
if(delta < max_delta)
max_delta = delta;
}
if(max_delta != 0xfffff) {
- int divider = div_tab[(sh2->m[5] >> 8) & 3];
+ int divider = div_tab[(m_m[5] >> 8) & 3];
if(divider) {
max_delta <<= divider;
- sh2->frc_base = sh2->device->total_cycles();
- sh2->timer->adjust(sh2->device->cycles_to_attotime(max_delta));
+ m_frc_base = total_cycles();
+ m_timer->adjust(cycles_to_attotime(max_delta));
} else {
- logerror("SH2.%s: Timer event in %d cycles of external clock", sh2->device->tag(), max_delta);
+ logerror("SH2.%s: Timer event in %d cycles of external clock", tag(), max_delta);
}
}
}
-
-static TIMER_CALLBACK( sh2_timer_callback )
+TIMER_CALLBACK_MEMBER( sh2_device::sh2_timer_callback )
{
- sh2_state *sh2 = (sh2_state *)ptr;
UINT16 frc;
- sh2_timer_resync(sh2);
+ sh2_timer_resync();
- frc = sh2->frc;
+ frc = m_frc;
- if(frc == sh2->ocrb)
- sh2->m[4] |= OCFB;
+ if(frc == m_ocrb)
+ m_m[4] |= OCFB;
if(frc == 0x0000)
- sh2->m[4] |= OVF;
+ m_m[4] |= OVF;
- if(frc == sh2->ocra)
+ if(frc == m_ocra)
{
- sh2->m[4] |= OCFA;
+ m_m[4] |= OCFA;
- if(sh2->m[4] & 0x010000)
- sh2->frc = 0;
+ if(m_m[4] & 0x010000)
+ m_frc = 0;
}
- sh2_recalc_irq(sh2);
- sh2_timer_activate(sh2);
+ sh2_recalc_irq();
+ sh2_timer_activate();
}
@@ -176,35 +124,34 @@ static TIMER_CALLBACK( sh2_timer_callback )
-void sh2_notify_dma_data_available(device_t *device)
+void sh2_device::sh2_notify_dma_data_available()
{
- sh2_state *sh2 = GET_SH2(device);
//printf("call notify\n");
for (int dma=0;dma<2;dma++)
{
- //printf("sh2->dma_timer_active[dma] %04x\n",sh2->dma_timer_active[dma]);
+ //printf("m_dma_timer_active[dma] %04x\n",m_dma_timer_active[dma]);
- if (sh2->dma_timer_active[dma]==2) // 2 = stalled
+ if (m_dma_timer_active[dma]==2) // 2 = stalled
{
// printf("resuming stalled dma\n");
- sh2->dma_timer_active[dma]=1;
- sh2->dma_current_active_timer[dma]->adjust(attotime::zero, dma);
+ m_dma_timer_active[dma]=1;
+ m_dma_current_active_timer[dma]->adjust(attotime::zero, dma);
}
}
}
-void sh2_do_dma(sh2_state *sh2, int dma)
+void sh2_device::sh2_do_dma(int dma)
{
UINT32 dmadata;
UINT32 tempsrc, tempdst;
- if (sh2->active_dma_count[dma] > 0)
+ if (m_active_dma_count[dma] > 0)
{
// process current DMA
- switch(sh2->active_dma_size[dma])
+ switch(m_active_dma_size[dma])
{
case 0:
{
@@ -212,197 +159,197 @@ void sh2_do_dma(sh2_state *sh2, int dma)
// to allow for the callback to check if we can process the DMA at this
// time (we need to know where we're reading / writing to/from)
- if(sh2->active_dma_incs[dma] == 2)
- tempsrc = sh2->active_dma_src[dma] - 1;
+ if(m_active_dma_incs[dma] == 2)
+ tempsrc = m_active_dma_src[dma] - 1;
else
- tempsrc = sh2->active_dma_src[dma];
+ tempsrc = m_active_dma_src[dma];
- if(sh2->active_dma_incd[dma] == 2)
- tempdst = sh2->active_dma_dst[dma] - 1;
+ if(m_active_dma_incd[dma] == 2)
+ tempdst = m_active_dma_dst[dma] - 1;
else
- tempdst = sh2->active_dma_dst[dma];
+ tempdst = m_active_dma_dst[dma];
- if (sh2->dma_callback_fifo_data_available)
+ if (m_dma_callback_fifo_data_available)
{
- int available = sh2->dma_callback_fifo_data_available(sh2->device, tempsrc, tempdst, 0, sh2->active_dma_size[dma]);
+ int available = m_dma_callback_fifo_data_available(this, tempsrc, tempdst, 0, m_active_dma_size[dma]);
if (!available)
{
//printf("dma stalled\n");
- sh2->dma_timer_active[dma]=2;// mark as stalled
+ m_dma_timer_active[dma]=2;// mark as stalled
return;
}
}
#ifdef USE_TIMER_FOR_DMA
//schedule next DMA callback
- sh2->dma_current_active_timer[dma]->adjust(sh2->device->cycles_to_attotime(2), dma);
+ m_dma_current_active_timer[dma]->adjust(cycles_to_attotime(2), dma);
#endif
- dmadata = sh2->program->read_byte(tempsrc);
- if (sh2->dma_callback_kludge) dmadata = sh2->dma_callback_kludge(sh2->device, tempsrc, tempdst, dmadata, sh2->active_dma_size[dma]);
- sh2->program->write_byte(tempdst, dmadata);
+ dmadata = m_program->read_byte(tempsrc);
+ if (m_dma_callback_kludge) dmadata = m_dma_callback_kludge(this, tempsrc, tempdst, dmadata, m_active_dma_size[dma]);
+ m_program->write_byte(tempdst, dmadata);
- if(sh2->active_dma_incs[dma] == 2)
- sh2->active_dma_src[dma] --;
- if(sh2->active_dma_incd[dma] == 2)
- sh2->active_dma_dst[dma] --;
+ if(m_active_dma_incs[dma] == 2)
+ m_active_dma_src[dma] --;
+ if(m_active_dma_incd[dma] == 2)
+ m_active_dma_dst[dma] --;
- if(sh2->active_dma_incs[dma] == 1)
- sh2->active_dma_src[dma] ++;
- if(sh2->active_dma_incd[dma] == 1)
- sh2->active_dma_dst[dma] ++;
+ if(m_active_dma_incs[dma] == 1)
+ m_active_dma_src[dma] ++;
+ if(m_active_dma_incd[dma] == 1)
+ m_active_dma_dst[dma] ++;
- sh2->active_dma_count[dma] --;
+ m_active_dma_count[dma] --;
}
break;
case 1:
{
- if(sh2->active_dma_incs[dma] == 2)
- tempsrc = sh2->active_dma_src[dma] - 2;
+ if(m_active_dma_incs[dma] == 2)
+ tempsrc = m_active_dma_src[dma] - 2;
else
- tempsrc = sh2->active_dma_src[dma];
+ tempsrc = m_active_dma_src[dma];
- if(sh2->active_dma_incd[dma] == 2)
- tempdst = sh2->active_dma_dst[dma] - 2;
+ if(m_active_dma_incd[dma] == 2)
+ tempdst = m_active_dma_dst[dma] - 2;
else
- tempdst = sh2->active_dma_dst[dma];
+ tempdst = m_active_dma_dst[dma];
- if (sh2->dma_callback_fifo_data_available)
+ if (m_dma_callback_fifo_data_available)
{
- int available = sh2->dma_callback_fifo_data_available(sh2->device, tempsrc, tempdst, 0, sh2->active_dma_size[dma]);
+ int available = m_dma_callback_fifo_data_available(this, tempsrc, tempdst, 0, m_active_dma_size[dma]);
if (!available)
{
//printf("dma stalled\n");
- sh2->dma_timer_active[dma]=2;// mark as stalled
+ m_dma_timer_active[dma]=2;// mark as stalled
return;
}
}
#ifdef USE_TIMER_FOR_DMA
//schedule next DMA callback
- sh2->dma_current_active_timer[dma]->adjust(sh2->device->cycles_to_attotime(2), dma);
+ m_dma_current_active_timer[dma]->adjust(cycles_to_attotime(2), dma);
#endif
// check: should this really be using read_word_32 / write_word_32?
- dmadata = sh2->program->read_word(tempsrc);
- if (sh2->dma_callback_kludge) dmadata = sh2->dma_callback_kludge(sh2->device, tempsrc, tempdst, dmadata, sh2->active_dma_size[dma]);
- sh2->program->write_word(tempdst, dmadata);
+ dmadata = m_program->read_word(tempsrc);
+ if (m_dma_callback_kludge) dmadata = m_dma_callback_kludge(this, tempsrc, tempdst, dmadata, m_active_dma_size[dma]);
+ m_program->write_word(tempdst, dmadata);
- if(sh2->active_dma_incs[dma] == 2)
- sh2->active_dma_src[dma] -= 2;
- if(sh2->active_dma_incd[dma] == 2)
- sh2->active_dma_dst[dma] -= 2;
+ if(m_active_dma_incs[dma] == 2)
+ m_active_dma_src[dma] -= 2;
+ if(m_active_dma_incd[dma] == 2)
+ m_active_dma_dst[dma] -= 2;
- if(sh2->active_dma_incs[dma] == 1)
- sh2->active_dma_src[dma] += 2;
- if(sh2->active_dma_incd[dma] == 1)
- sh2->active_dma_dst[dma] += 2;
+ if(m_active_dma_incs[dma] == 1)
+ m_active_dma_src[dma] += 2;
+ if(m_active_dma_incd[dma] == 1)
+ m_active_dma_dst[dma] += 2;
- sh2->active_dma_count[dma] --;
+ m_active_dma_count[dma] --;
}
break;
case 2:
{
- if(sh2->active_dma_incs[dma] == 2)
- tempsrc = sh2->active_dma_src[dma] - 4;
+ if(m_active_dma_incs[dma] == 2)
+ tempsrc = m_active_dma_src[dma] - 4;
else
- tempsrc = sh2->active_dma_src[dma];
+ tempsrc = m_active_dma_src[dma];
- if(sh2->active_dma_incd[dma] == 2)
- tempdst = sh2->active_dma_dst[dma] - 4;
+ if(m_active_dma_incd[dma] == 2)
+ tempdst = m_active_dma_dst[dma] - 4;
else
- tempdst = sh2->active_dma_dst[dma];
+ tempdst = m_active_dma_dst[dma];
- if (sh2->dma_callback_fifo_data_available)
+ if (m_dma_callback_fifo_data_available)
{
- int available = sh2->dma_callback_fifo_data_available(sh2->device, tempsrc, tempdst, 0, sh2->active_dma_size[dma]);
+ int available = m_dma_callback_fifo_data_available(this, tempsrc, tempdst, 0, m_active_dma_size[dma]);
if (!available)
{
//printf("dma stalled\n");
- sh2->dma_timer_active[dma]=2;// mark as stalled
+ m_dma_timer_active[dma]=2;// mark as stalled
return;
}
}
#ifdef USE_TIMER_FOR_DMA
//schedule next DMA callback
- sh2->dma_current_active_timer[dma]->adjust(sh2->device->cycles_to_attotime(2), dma);
+ m_dma_current_active_timer[dma]->adjust(cycles_to_attotime(2), dma);
#endif
- dmadata = sh2->program->read_dword(tempsrc);
- if (sh2->dma_callback_kludge) dmadata = sh2->dma_callback_kludge(sh2->device, tempsrc, tempdst, dmadata, sh2->active_dma_size[dma]);
- sh2->program->write_dword(tempdst, dmadata);
+ dmadata = m_program->read_dword(tempsrc);
+ if (m_dma_callback_kludge) dmadata = m_dma_callback_kludge(this, tempsrc, tempdst, dmadata, m_active_dma_size[dma]);
+ m_program->write_dword(tempdst, dmadata);
- if(sh2->active_dma_incs[dma] == 2)
- sh2->active_dma_src[dma] -= 4;
- if(sh2->active_dma_incd[dma] == 2)
- sh2->active_dma_dst[dma] -= 4;
+ if(m_active_dma_incs[dma] == 2)
+ m_active_dma_src[dma] -= 4;
+ if(m_active_dma_incd[dma] == 2)
+ m_active_dma_dst[dma] -= 4;
- if(sh2->active_dma_incs[dma] == 1)
- sh2->active_dma_src[dma] += 4;
- if(sh2->active_dma_incd[dma] == 1)
- sh2->active_dma_dst[dma] += 4;
+ if(m_active_dma_incs[dma] == 1)
+ m_active_dma_src[dma] += 4;
+ if(m_active_dma_incd[dma] == 1)
+ m_active_dma_dst[dma] += 4;
- sh2->active_dma_count[dma] --;
+ m_active_dma_count[dma] --;
}
break;
case 3:
{
// shouldn't this really be 4 calls here instead?
- tempsrc = sh2->active_dma_src[dma];
+ tempsrc = m_active_dma_src[dma];
- if(sh2->active_dma_incd[dma] == 2)
- tempdst = sh2->active_dma_dst[dma] - 16;
+ if(m_active_dma_incd[dma] == 2)
+ tempdst = m_active_dma_dst[dma] - 16;
else
- tempdst = sh2->active_dma_dst[dma];
+ tempdst = m_active_dma_dst[dma];
- if (sh2->dma_callback_fifo_data_available)
+ if (m_dma_callback_fifo_data_available)
{
- int available = sh2->dma_callback_fifo_data_available(sh2->device, tempsrc, tempdst, 0, sh2->active_dma_size[dma]);
+ int available = m_dma_callback_fifo_data_available(this, tempsrc, tempdst, 0, m_active_dma_size[dma]);
if (!available)
{
//printf("dma stalled\n");
- sh2->dma_timer_active[dma]=2;// mark as stalled
+ m_dma_timer_active[dma]=2;// mark as stalled
fatalerror("SH2 dma_callback_fifo_data_available == 0 in unsupported mode\n");
}
}
#ifdef USE_TIMER_FOR_DMA
//schedule next DMA callback
- sh2->dma_current_active_timer[dma]->adjust(sh2->device->cycles_to_attotime(2), dma);
+ m_dma_current_active_timer[dma]->adjust(cycles_to_attotime(2), dma);
#endif
- dmadata = sh2->program->read_dword(tempsrc);
- if (sh2->dma_callback_kludge) dmadata = sh2->dma_callback_kludge(sh2->device, tempsrc, tempdst, dmadata, sh2->active_dma_size[dma]);
- sh2->program->write_dword(tempdst, dmadata);
+ dmadata = m_program->read_dword(tempsrc);
+ if (m_dma_callback_kludge) dmadata = m_dma_callback_kludge(this, tempsrc, tempdst, dmadata, m_active_dma_size[dma]);
+ m_program->write_dword(tempdst, dmadata);
- dmadata = sh2->program->read_dword(tempsrc+4);
- if (sh2->dma_callback_kludge) dmadata = sh2->dma_callback_kludge(sh2->device, tempsrc, tempdst, dmadata, sh2->active_dma_size[dma]);
- sh2->program->write_dword(tempdst+4, dmadata);
+ dmadata = m_program->read_dword(tempsrc+4);
+ if (m_dma_callback_kludge) dmadata = m_dma_callback_kludge(this, tempsrc, tempdst, dmadata, m_active_dma_size[dma]);
+ m_program->write_dword(tempdst+4, dmadata);
- dmadata = sh2->program->read_dword(tempsrc+8);
- if (sh2->dma_callback_kludge) dmadata = sh2->dma_callback_kludge(sh2->device, tempsrc, tempdst, dmadata, sh2->active_dma_size[dma]);
- sh2->program->write_dword(tempdst+8, dmadata);
+ dmadata = m_program->read_dword(tempsrc+8);
+ if (m_dma_callback_kludge) dmadata = m_dma_callback_kludge(this, tempsrc, tempdst, dmadata, m_active_dma_size[dma]);
+ m_program->write_dword(tempdst+8, dmadata);
- dmadata = sh2->program->read_dword(tempsrc+12);
- if (sh2->dma_callback_kludge) dmadata = sh2->dma_callback_kludge(sh2->device, tempsrc, tempdst, dmadata, sh2->active_dma_size[dma]);
- sh2->program->write_dword(tempdst+12, dmadata);
+ dmadata = m_program->read_dword(tempsrc+12);
+ if (m_dma_callback_kludge) dmadata = m_dma_callback_kludge(this, tempsrc, tempdst, dmadata, m_active_dma_size[dma]);
+ m_program->write_dword(tempdst+12, dmadata);
- if(sh2->active_dma_incd[dma] == 2)
- sh2->active_dma_dst[dma] -= 16;
+ if(m_active_dma_incd[dma] == 2)
+ m_active_dma_dst[dma] -= 16;
- sh2->active_dma_src[dma] += 16;
- if(sh2->active_dma_incd[dma] == 1)
- sh2->active_dma_dst[dma] += 16;
+ m_active_dma_src[dma] += 16;
+ if(m_active_dma_incd[dma] == 1)
+ m_active_dma_dst[dma] += 16;
- sh2->active_dma_count[dma]-=4;
+ m_active_dma_count[dma]-=4;
}
break;
}
@@ -410,78 +357,76 @@ void sh2_do_dma(sh2_state *sh2, int dma)
else // the dma is complete
{
// int dma = param & 1;
- // sh2_state *sh2 = (sh2_state *)ptr;
// fever soccer uses cycle-stealing mode, resume the CPU now DMA has finished
- if (sh2->active_dma_steal[dma])
+ if (m_active_dma_steal[dma])
{
- sh2->device->resume(SUSPEND_REASON_HALT );
+ resume(SUSPEND_REASON_HALT );
}
- LOG(("SH2.%s: DMA %d complete\n", sh2->device->tag(), dma));
- sh2->m[0x63+4*dma] |= 2;
- sh2->dma_timer_active[dma] = 0;
- sh2->dma_irq[dma] |= 1;
- sh2_recalc_irq(sh2);
+ LOG(("SH2.%s: DMA %d complete\n", tag(), dma));
+ m_m[0x63+4*dma] |= 2;
+ m_dma_timer_active[dma] = 0;
+ m_dma_irq[dma] |= 1;
+ sh2_recalc_irq();
}
}
-static TIMER_CALLBACK( sh2_dma_current_active_callback )
+TIMER_CALLBACK_MEMBER( sh2_device::sh2_dma_current_active_callback )
{
int dma = param & 1;
- sh2_state *sh2 = (sh2_state *)ptr;
- sh2_do_dma(sh2, dma);
+ sh2_do_dma(dma);
}
-static void sh2_dmac_check(sh2_state *sh2, int dma)
+void sh2_device::sh2_dmac_check(int dma)
{
- if(sh2->m[0x63+4*dma] & sh2->m[0x6c] & 1)
+ if(m_m[0x63+4*dma] & m_m[0x6c] & 1)
{
- if(!sh2->dma_timer_active[dma] && !(sh2->m[0x63+4*dma] & 2))
+ if(!m_dma_timer_active[dma] && !(m_m[0x63+4*dma] & 2))
{
- sh2->active_dma_incd[dma] = (sh2->m[0x63+4*dma] >> 14) & 3;
- sh2->active_dma_incs[dma] = (sh2->m[0x63+4*dma] >> 12) & 3;
- sh2->active_dma_size[dma] = (sh2->m[0x63+4*dma] >> 10) & 3;
- sh2->active_dma_steal[dma] = (sh2->m[0x63+4*dma] &0x10);
+ m_active_dma_incd[dma] = (m_m[0x63+4*dma] >> 14) & 3;
+ m_active_dma_incs[dma] = (m_m[0x63+4*dma] >> 12) & 3;
+ m_active_dma_size[dma] = (m_m[0x63+4*dma] >> 10) & 3;
+ m_active_dma_steal[dma] = (m_m[0x63+4*dma] &0x10);
- if(sh2->active_dma_incd[dma] == 3 || sh2->active_dma_incs[dma] == 3)
+ if(m_active_dma_incd[dma] == 3 || m_active_dma_incs[dma] == 3)
{
- logerror("SH2: DMA: bad increment values (%d, %d, %d, %04x)\n", sh2->active_dma_incd[dma], sh2->active_dma_incs[dma], sh2->active_dma_size[dma], sh2->m[0x63+4*dma]);
+ logerror("SH2: DMA: bad increment values (%d, %d, %d, %04x)\n", m_active_dma_incd[dma], m_active_dma_incs[dma], m_active_dma_size[dma], m_m[0x63+4*dma]);
return;
}
- sh2->active_dma_src[dma] = sh2->m[0x60+4*dma];
- sh2->active_dma_dst[dma] = sh2->m[0x61+4*dma];
- sh2->active_dma_count[dma] = sh2->m[0x62+4*dma];
- if(!sh2->active_dma_count[dma])
- sh2->active_dma_count[dma] = 0x1000000;
+ m_active_dma_src[dma] = m_m[0x60+4*dma];
+ m_active_dma_dst[dma] = m_m[0x61+4*dma];
+ m_active_dma_count[dma] = m_m[0x62+4*dma];
+ if(!m_active_dma_count[dma])
+ m_active_dma_count[dma] = 0x1000000;
- LOG(("SH2: DMA %d start %x, %x, %x, %04x, %d, %d, %d\n", dma, sh2->active_dma_src[dma], sh2->active_dma_dst[dma], sh2->active_dma_count[dma], sh2->m[0x63+4*dma], sh2->active_dma_incs[dma], sh2->active_dma_incd[dma], sh2->active_dma_size[dma]));
+ LOG(("SH2: DMA %d start %x, %x, %x, %04x, %d, %d, %d\n", dma, m_active_dma_src[dma], m_active_dma_dst[dma], m_active_dma_count[dma], m_m[0x63+4*dma], m_active_dma_incs[dma], m_active_dma_incd[dma], m_active_dma_size[dma]));
- sh2->dma_timer_active[dma] = 1;
+ m_dma_timer_active[dma] = 1;
- sh2->active_dma_src[dma] &= AM;
- sh2->active_dma_dst[dma] &= AM;
+ m_active_dma_src[dma] &= AM;
+ m_active_dma_dst[dma] &= AM;
- switch(sh2->active_dma_size[dma])
+ switch(m_active_dma_size[dma])
{
case 0:
break;
case 1:
- sh2->active_dma_src[dma] &= ~1;
- sh2->active_dma_dst[dma] &= ~1;
+ m_active_dma_src[dma] &= ~1;
+ m_active_dma_dst[dma] &= ~1;
break;
case 2:
- sh2->active_dma_src[dma] &= ~3;
- sh2->active_dma_dst[dma] &= ~3;
+ m_active_dma_src[dma] &= ~3;
+ m_active_dma_dst[dma] &= ~3;
break;
case 3:
- sh2->active_dma_src[dma] &= ~3;
- sh2->active_dma_dst[dma] &= ~3;
- sh2->active_dma_count[dma] &= ~3;
+ m_active_dma_src[dma] &= ~3;
+ m_active_dma_dst[dma] &= ~3;
+ m_active_dma_count[dma] &= ~3;
break;
}
@@ -492,41 +437,40 @@ static void sh2_dmac_check(sh2_state *sh2, int dma)
// start DMA timer
// fever soccer uses cycle-stealing mode, requiring the CPU to be halted
- if (sh2->active_dma_steal[dma])
+ if (m_active_dma_steal[dma])
{
//printf("cycle stealing DMA\n");
- sh2->device->suspend(SUSPEND_REASON_HALT, 1 );
+ suspend(SUSPEND_REASON_HALT, 1 );
}
- sh2->dma_current_active_timer[dma]->adjust(sh2->device->cycles_to_attotime(2), dma);
+ m_dma_current_active_timer[dma]->adjust(cycles_to_attotime(2), dma);
#endif
}
}
else
{
- if(sh2->dma_timer_active[dma])
+ if(m_dma_timer_active[dma])
{
logerror("SH2: DMA %d cancelled in-flight\n", dma);
- //sh2->dma_complete_timer[dma]->adjust(attotime::never);
- sh2->dma_current_active_timer[dma]->adjust(attotime::never);
+ //m_dma_complete_timer[dma]->adjust(attotime::never);
+ m_dma_current_active_timer[dma]->adjust(attotime::never);
- sh2->dma_timer_active[dma] = 0;
+ m_dma_timer_active[dma] = 0;
}
}
}
-WRITE32_HANDLER( sh2_internal_w )
+WRITE32_MEMBER( sh2_device::sh2_internal_w )
{
- sh2_state *sh2 = GET_SH2(&space.device());
UINT32 old;
- if (sh2->isdrc)
+ if (m_isdrc)
offset &= 0x7f;
- old = sh2->m[offset];
- COMBINE_DATA(sh2->m+offset);
+ old = m_m[offset];
+ COMBINE_DATA(m_m+offset);
// if(offset != 0x20)
// logerror("sh2_internal_w: Write %08x (%x), %08x @ %08x\n", 0xfffffe00+offset*4, offset, data, mem_mask);
@@ -547,23 +491,23 @@ WRITE32_HANDLER( sh2_internal_w )
case 0x04: // TIER, FTCSR, FRC
if((mem_mask & 0x00ffffff) != 0)
{
- sh2_timer_resync(sh2);
+ sh2_timer_resync();
}
-// printf("SH2.%s: TIER write %04x @ %04x\n", sh2->device->tag(), data >> 16, mem_mask>>16);
- sh2->m[4] = (sh2->m[4] & ~(ICF|OCFA|OCFB|OVF)) | (old & sh2->m[4] & (ICF|OCFA|OCFB|OVF));
- COMBINE_DATA(&sh2->frc);
+// printf("SH2.%s: TIER write %04x @ %04x\n", m_device->tag(), data >> 16, mem_mask>>16);
+ m_m[4] = (m_m[4] & ~(ICF|OCFA|OCFB|OVF)) | (old & m_m[4] & (ICF|OCFA|OCFB|OVF));
+ COMBINE_DATA(&m_frc);
if((mem_mask & 0x00ffffff) != 0)
- sh2_timer_activate(sh2);
- sh2_recalc_irq(sh2);
+ sh2_timer_activate();
+ sh2_recalc_irq();
break;
case 0x05: // OCRx, TCR, TOCR
-// printf("SH2.%s: TCR write %08x @ %08x\n", sh2->device->tag(), data, mem_mask);
- sh2_timer_resync(sh2);
- if(sh2->m[5] & 0x10)
- sh2->ocrb = (sh2->ocrb & (~mem_mask >> 16)) | ((data & mem_mask) >> 16);
+// printf("SH2.%s: TCR write %08x @ %08x\n", m_device->tag(), data, mem_mask);
+ sh2_timer_resync();
+ if(m_m[5] & 0x10)
+ m_ocrb = (m_ocrb & (~mem_mask >> 16)) | ((data & mem_mask) >> 16);
else
- sh2->ocra = (sh2->ocra & (~mem_mask >> 16)) | ((data & mem_mask) >> 16);
- sh2_timer_activate(sh2);
+ m_ocra = (m_ocra & (~mem_mask >> 16)) | ((data & mem_mask) >> 16);
+ sh2_timer_activate();
break;
case 0x06: // ICR
@@ -573,7 +517,7 @@ WRITE32_HANDLER( sh2_internal_w )
case 0x18: // IPRB, VCRA
case 0x19: // VCRB, VCRC
case 0x1a: // VCRD
- sh2_recalc_irq(sh2);
+ sh2_recalc_irq();
break;
// DMA
@@ -582,10 +526,10 @@ WRITE32_HANDLER( sh2_internal_w )
// Watchdog
case 0x20: // WTCNT, RSTCSR
- if((sh2->m[0x20] & 0xff000000) == 0x5a000000)
- sh2->wtcnt = (sh2->m[0x20] >> 16) & 0xff;
+ if((m_m[0x20] & 0xff000000) == 0x5a000000)
+ m_wtcnt = (m_m[0x20] >> 16) & 0xff;
- if((sh2->m[0x20] & 0xff000000) == 0xa5000000)
+ if((m_m[0x20] & 0xff000000) == 0xa5000000)
{
/*
WTCSR
@@ -596,17 +540,17 @@ WRITE32_HANDLER( sh2_internal_w )
---- -xxx Clock select
*/
- sh2->wtcsr = (sh2->m[0x20] >> 16) & 0xff;
+ m_wtcsr = (m_m[0x20] >> 16) & 0xff;
}
- if((sh2->m[0x20] & 0x0000ff00) == 0x00005a00)
+ if((m_m[0x20] & 0x0000ff00) == 0x00005a00)
{
// -x-- ---- RSTE (1: resets wtcnt when overflows 0: no reset)
// --x- ---- RSTS (0: power-on reset 1: Manual reset)
// ...
}
- if((sh2->m[0x20] & 0x0000ff00) == 0x0000a500)
+ if((m_m[0x20] & 0x0000ff00) == 0x0000a500)
{
// clear WOVF
// ...
@@ -640,59 +584,59 @@ WRITE32_HANDLER( sh2_internal_w )
break;
case 0x41: // DVDNT
{
- INT32 a = sh2->m[0x41];
- INT32 b = sh2->m[0x40];
- LOG(("SH2 '%s' div+mod %d/%d\n", sh2->device->tag(), a, b));
+ INT32 a = m_m[0x41];
+ INT32 b = m_m[0x40];
+ LOG(("SH2 '%s' div+mod %d/%d\n", tag(), a, b));
if (b)
{
- sh2->m[0x45] = a / b;
- sh2->m[0x44] = a % b;
+ m_m[0x45] = a / b;
+ m_m[0x44] = a % b;
}
else
{
- sh2->m[0x42] |= 0x00010000;
- sh2->m[0x45] = 0x7fffffff;
- sh2->m[0x44] = 0x7fffffff;
- sh2_recalc_irq(sh2);
+ m_m[0x42] |= 0x00010000;
+ m_m[0x45] = 0x7fffffff;
+ m_m[0x44] = 0x7fffffff;
+ sh2_recalc_irq();
}
break;
}
case 0x42: // DVCR
- sh2->m[0x42] = (sh2->m[0x42] & ~0x00001000) | (old & sh2->m[0x42] & 0x00010000);
- sh2_recalc_irq(sh2);
+ m_m[0x42] = (m_m[0x42] & ~0x00001000) | (old & m_m[0x42] & 0x00010000);
+ sh2_recalc_irq();
break;
case 0x43: // VCRDIV
- sh2_recalc_irq(sh2);
+ sh2_recalc_irq();
break;
case 0x44: // DVDNTH
break;
case 0x45: // DVDNTL
{
- INT64 a = sh2->m[0x45] | ((UINT64)(sh2->m[0x44]) << 32);
- INT64 b = (INT32)sh2->m[0x40];
- LOG(("SH2 '%s' div+mod %" I64FMT "d/%" I64FMT "d\n", sh2->device->tag(), a, b));
+ INT64 a = m_m[0x45] | ((UINT64)(m_m[0x44]) << 32);
+ INT64 b = (INT32)m_m[0x40];
+ LOG(("SH2 '%s' div+mod %" I64FMT "d/%" I64FMT "d\n", tag(), a, b));
if (b)
{
INT64 q = a / b;
if (q != (INT32)q)
{
- sh2->m[0x42] |= 0x00010000;
- sh2->m[0x45] = 0x7fffffff;
- sh2->m[0x44] = 0x7fffffff;
- sh2_recalc_irq(sh2);
+ m_m[0x42] |= 0x00010000;
+ m_m[0x45] = 0x7fffffff;
+ m_m[0x44] = 0x7fffffff;
+ sh2_recalc_irq();
}
else
{
- sh2->m[0x45] = q;
- sh2->m[0x44] = a % b;
+ m_m[0x45] = q;
+ m_m[0x44] = a % b;
}
}
else
{
- sh2->m[0x42] |= 0x00010000;
- sh2->m[0x45] = 0x7fffffff;
- sh2->m[0x44] = 0x7fffffff;
- sh2_recalc_irq(sh2);
+ m_m[0x42] |= 0x00010000;
+ m_m[0x45] = 0x7fffffff;
+ m_m[0x44] = 0x7fffffff;
+ sh2_recalc_irq();
}
break;
}
@@ -702,30 +646,30 @@ WRITE32_HANDLER( sh2_internal_w )
case 0x61: // DAR0
break;
case 0x62: // DTCR0
- sh2->m[0x62] &= 0xffffff;
+ m_m[0x62] &= 0xffffff;
break;
case 0x63: // CHCR0
- sh2->m[0x63] = (sh2->m[0x63] & ~2) | (old & sh2->m[0x63] & 2);
- sh2_dmac_check(sh2, 0);
+ m_m[0x63] = (m_m[0x63] & ~2) | (old & m_m[0x63] & 2);
+ sh2_dmac_check(0);
break;
case 0x64: // SAR1
case 0x65: // DAR1
break;
case 0x66: // DTCR1
- sh2->m[0x66] &= 0xffffff;
+ m_m[0x66] &= 0xffffff;
break;
case 0x67: // CHCR1
- sh2->m[0x67] = (sh2->m[0x67] & ~2) | (old & sh2->m[0x67] & 2);
- sh2_dmac_check(sh2, 1);
+ m_m[0x67] = (m_m[0x67] & ~2) | (old & m_m[0x67] & 2);
+ sh2_dmac_check(1);
break;
case 0x68: // VCRDMA0
case 0x6a: // VCRDMA1
- sh2_recalc_irq(sh2);
+ sh2_recalc_irq();
break;
case 0x6c: // DMAOR
- sh2->m[0x6c] = (sh2->m[0x6c] & ~6) | (old & sh2->m[0x6c] & 6);
- sh2_dmac_check(sh2, 0);
- sh2_dmac_check(sh2, 1);
+ m_m[0x6c] = (m_m[0x6c] & ~6) | (old & m_m[0x6c] & 6);
+ sh2_dmac_check(0);
+ sh2_dmac_check(1);
break;
// Bus controller
@@ -744,11 +688,9 @@ WRITE32_HANDLER( sh2_internal_w )
}
}
-READ32_HANDLER( sh2_internal_r )
+READ32_MEMBER( sh2_device::sh2_internal_r )
{
- sh2_state *sh2 = GET_SH2(&space.device());
-
- if (sh2->isdrc)
+ if (m_isdrc)
offset &= 0x7f;
// logerror("sh2_internal_r: Read %08x (%x) @ %08x\n", 0xfffffe00+offset*4, offset, mem_mask);
@@ -757,72 +699,69 @@ READ32_HANDLER( sh2_internal_r )
case 0x00:
break;
case 0x01:
- return sh2->m[1] | 0x80000000; // TDRE: Trasmit Data Register Empty. Force it to be '1' for the time being.
+ return m_m[1] | 0x80000000; // TDRE: Trasmit Data Register Empty. Force it to be '1' for the time being.
case 0x04: // TIER, FTCSR, FRC
if ( mem_mask == 0x00ff0000 )
{
- if ( sh2->ftcsr_read_callback != NULL )
+ if ( m_ftcsr_read_callback != NULL )
{
- sh2->ftcsr_read_callback( (sh2->m[4] & 0xffff0000) | sh2->frc );
+ m_ftcsr_read_callback( (m_m[4] & 0xffff0000) | m_frc );
}
}
- sh2_timer_resync(sh2);
- return (sh2->m[4] & 0xffff0000) | sh2->frc;
+ sh2_timer_resync();
+ return (m_m[4] & 0xffff0000) | m_frc;
case 0x05: // OCRx, TCR, TOCR
- if(sh2->m[5] & 0x10)
- return (sh2->ocrb << 16) | (sh2->m[5] & 0xffff);
+ if(m_m[5] & 0x10)
+ return (m_ocrb << 16) | (m_m[5] & 0xffff);
else
- return (sh2->ocra << 16) | (sh2->m[5] & 0xffff);
+ return (m_ocra << 16) | (m_m[5] & 0xffff);
case 0x06: // ICR
- return sh2->icr << 16;
+ return m_icr << 16;
case 0x20:
- return (((sh2->wtcsr | 0x18) & 0xff) << 24) | ((sh2->wtcnt & 0xff) << 16);
+ return (((m_wtcsr | 0x18) & 0xff) << 24) | ((m_wtcnt & 0xff) << 16);
case 0x24: // SBYCR, CCR
- return sh2->m[0x24] & ~0x3000; /* bit 4-5 of CCR are always zero */
+ return m_m[0x24] & ~0x3000; /* bit 4-5 of CCR are always zero */
case 0x38: // ICR, IPRA
- return (sh2->m[0x38] & 0x7fffffff) | (sh2->nmi_line_state == ASSERT_LINE ? 0 : 0x80000000);
+ return (m_m[0x38] & 0x7fffffff) | (m_nmi_line_state == ASSERT_LINE ? 0 : 0x80000000);
case 0x78: // BCR1
- return sh2->is_slave ? 0x00008000 : 0;
+ return m_is_slave ? 0x00008000 : 0;
case 0x41: // dvdntl mirrors
case 0x47:
- return sh2->m[0x45];
+ return m_m[0x45];
case 0x46: // dvdnth mirror
- return sh2->m[0x44];
+ return m_m[0x44];
}
- return sh2->m[offset];
+ return m_m[offset];
}
-void sh2_set_ftcsr_read_callback(device_t *device, void (*callback)(UINT32))
+void sh2_device::sh2_set_ftcsr_read_callback(void (*callback)(UINT32))
{
- sh2_state *sh2 = GET_SH2(device);
- sh2->ftcsr_read_callback = callback;
+ m_ftcsr_read_callback = callback;
}
-void sh2_set_frt_input(device_t *device, int state)
+void sh2_device::sh2_set_frt_input(int state)
{
- sh2_state *sh2 = GET_SH2(device);
-
if(state == PULSE_LINE)
{
- sh2_set_frt_input(device, ASSERT_LINE);
- sh2_set_frt_input(device, CLEAR_LINE);
+ sh2_set_frt_input(ASSERT_LINE);
+ sh2_set_frt_input(CLEAR_LINE);
return;
}
- if(sh2->frt_input == state) {
+ if(m_frt_input == state) {
return;
}
- sh2->frt_input = state;
+ m_frt_input = state;
- if(sh2->m[5] & 0x8000) {
+ if(m_m[5] & 0x8000) {
if(state == CLEAR_LINE) {
return;
}
@@ -832,256 +771,125 @@ void sh2_set_frt_input(device_t *device, int state)
}
}
- sh2_timer_resync(sh2);
- sh2->icr = sh2->frc;
- sh2->m[4] |= ICF;
- //logerror("SH2.%s: ICF activated (%x)\n", sh2->device->tag(), sh2->pc & AM);
- sh2_recalc_irq(sh2);
+ sh2_timer_resync();
+ m_icr = m_frc;
+ m_m[4] |= ICF;
+ //logerror("SH2.%s: ICF activated (%x)\n", tag(), m_sh2_state->pc & AM);
+ sh2_recalc_irq();
}
-void sh2_set_irq_line(sh2_state *sh2, int irqline, int state)
-{
- if (irqline == INPUT_LINE_NMI)
- {
- if (sh2->nmi_line_state == state)
- return;
- sh2->nmi_line_state = state;
-
- if( state == CLEAR_LINE )
- {
- LOG(("SH-2 '%s' cleared nmi\n", sh2->device->tag()));
- }
- else
- {
- LOG(("SH-2 '%s' assert nmi\n", sh2->device->tag()));
-
- sh2_exception(sh2, "Set IRQ line", 16);
-
- if (sh2->isdrc)
- sh2->pending_nmi = 1;
- }
- }
- else
- {
- if (sh2->irq_line_state[irqline] == state)
- return;
- sh2->irq_line_state[irqline] = state;
-
- if( state == CLEAR_LINE )
- {
- LOG(("SH-2 '%s' cleared irq #%d\n", sh2->device->tag(), irqline));
- sh2->pending_irq &= ~(1 << irqline);
- }
- else
- {
- LOG(("SH-2 '%s' assert irq #%d\n", sh2->device->tag(), irqline));
- sh2->pending_irq |= 1 << irqline;
- if (sh2->isdrc)
- {
- sh2->test_irq = 1;
- } else {
- if(sh2->delay)
- sh2->test_irq = 1;
- else
- CHECK_PENDING_IRQ("sh2_set_irq_line");
- }
- }
- }
-}
-
-void sh2_recalc_irq(sh2_state *sh2)
+void sh2_device::sh2_recalc_irq()
{
int irq = 0, vector = -1;
int level;
// Timer irqs
- if((sh2->m[4]>>8) & sh2->m[4] & (ICF|OCFA|OCFB|OVF))
+ if((m_m[4]>>8) & m_m[4] & (ICF|OCFA|OCFB|OVF))
{
- level = (sh2->m[0x18] >> 24) & 15;
+ level = (m_m[0x18] >> 24) & 15;
if(level > irq)
{
- int mask = (sh2->m[4]>>8) & sh2->m[4];
+ int mask = (m_m[4]>>8) & m_m[4];
irq = level;
if(mask & ICF)
- vector = (sh2->m[0x19] >> 8) & 0x7f;
+ vector = (m_m[0x19] >> 8) & 0x7f;
else if(mask & (OCFA|OCFB))
- vector = sh2->m[0x19] & 0x7f;
+ vector = m_m[0x19] & 0x7f;
else
- vector = (sh2->m[0x1a] >> 24) & 0x7f;
+ vector = (m_m[0x1a] >> 24) & 0x7f;
}
}
// DMA irqs
- if((sh2->m[0x63] & 6) == 6 && sh2->dma_irq[0]) {
- level = (sh2->m[0x38] >> 8) & 15;
+ if((m_m[0x63] & 6) == 6 && m_dma_irq[0]) {
+ level = (m_m[0x38] >> 8) & 15;
if(level > irq) {
irq = level;
- sh2->dma_irq[0] &= ~1;
- vector = (sh2->m[0x68]) & 0x7f;
+ m_dma_irq[0] &= ~1;
+ vector = (m_m[0x68]) & 0x7f;
}
}
- else if((sh2->m[0x67] & 6) == 6 && sh2->dma_irq[1]) {
- level = (sh2->m[0x38] >> 8) & 15;
+ else if((m_m[0x67] & 6) == 6 && m_dma_irq[1]) {
+ level = (m_m[0x38] >> 8) & 15;
if(level > irq) {
irq = level;
- sh2->dma_irq[1] &= ~1;
- vector = (sh2->m[0x6a]) & 0x7f;
+ m_dma_irq[1] &= ~1;
+ vector = (m_m[0x6a]) & 0x7f;
}
}
- sh2->internal_irq_level = irq;
- sh2->internal_irq_vector = vector;
- sh2->test_irq = 1;
+ m_sh2_state->internal_irq_level = irq;
+ m_internal_irq_vector = vector;
+ m_test_irq = 1;
}
-void sh2_exception(sh2_state *sh2, const char *message, int irqline)
+void sh2_device::sh2_exception(const char *message, int irqline)
{
int vector;
if (irqline != 16)
{
- if (irqline <= ((sh2->sr >> 4) & 15)) /* If the cpu forbids this interrupt */
+ if (irqline <= ((m_sh2_state->sr >> 4) & 15)) /* If the cpu forbids this interrupt */
return;
// if this is an sh2 internal irq, use its vector
- if (sh2->internal_irq_level == irqline)
+ if (m_sh2_state->internal_irq_level == irqline)
{
- vector = sh2->internal_irq_vector;
+ vector = m_internal_irq_vector;
/* avoid spurious irqs with this (TODO: needs a better fix) */
- sh2->internal_irq_level = -1;
- LOG(("SH-2 '%s' exception #%d (internal vector: $%x) after [%s]\n", sh2->device->tag(), irqline, vector, message));
+ m_sh2_state->internal_irq_level = -1;
+ LOG(("SH-2 '%s' exception #%d (internal vector: $%x) after [%s]\n", tag(), irqline, vector, message));
}
else
{
- if(sh2->m[0x38] & 0x00010000)
+ if(m_m[0x38] & 0x00010000)
{
- vector = sh2->irq_callback(sh2->device, irqline);
- LOG(("SH-2 '%s' exception #%d (external vector: $%x) after [%s]\n", sh2->device->tag(), irqline, vector, message));
+ vector = standard_irq_callback(irqline);
+ LOG(("SH-2 '%s' exception #%d (external vector: $%x) after [%s]\n", tag(), irqline, vector, message));
}
else
{
- sh2->irq_callback(sh2->device, irqline);
+ standard_irq_callback(irqline);
vector = 64 + irqline/2;
- LOG(("SH-2 '%s' exception #%d (autovector: $%x) after [%s]\n", sh2->device->tag(), irqline, vector, message));
+ LOG(("SH-2 '%s' exception #%d (autovector: $%x) after [%s]\n", tag(), irqline, vector, message));
}
}
}
else
{
vector = 11;
- LOG(("SH-2 '%s' nmi exception (autovector: $%x) after [%s]\n", sh2->device->tag(), vector, message));
+ LOG(("SH-2 '%s' nmi exception (autovector: $%x) after [%s]\n", tag(), vector, message));
}
- if (sh2->isdrc)
+ if (m_isdrc)
{
- sh2->evec = RL( sh2, sh2->vbr + vector * 4 );
- sh2->evec &= AM;
- sh2->irqsr = sh2->sr;
+ m_sh2_state->evec = RL( m_sh2_state->vbr + vector * 4 );
+ m_sh2_state->evec &= AM;
+ m_sh2_state->irqsr = m_sh2_state->sr;
- /* set I flags in SR */
- if (irqline > SH2_INT_15)
- sh2->sr = sh2->sr | I;
- else
- sh2->sr = (sh2->sr & ~I) | (irqline << 4);
+ /* set I flags in SR */
+ if (irqline > SH2_INT_15)
+ m_sh2_state->sr = m_sh2_state->sr | I;
+ else
+ m_sh2_state->sr = (m_sh2_state->sr & ~I) | (irqline << 4);
-// printf("sh2_exception [%s] irqline %x evec %x save SR %x new SR %x\n", message, irqline, sh2->evec, sh2->irqsr, sh2->sr);
+// printf("sh2_exception [%s] irqline %x evec %x save SR %x new SR %x\n", message, irqline, m_sh2_state->evec, m_sh2_state->irqsr, m_sh2_state->sr);
} else {
- sh2->r[15] -= 4;
- WL( sh2, sh2->r[15], sh2->sr ); /* push SR onto stack */
- sh2->r[15] -= 4;
- WL( sh2, sh2->r[15], sh2->pc ); /* push PC onto stack */
-
- /* set I flags in SR */
- if (irqline > SH2_INT_15)
- sh2->sr = sh2->sr | I;
- else
- sh2->sr = (sh2->sr & ~I) | (irqline << 4);
+ m_sh2_state->r[15] -= 4;
+ WL( m_sh2_state->r[15], m_sh2_state->sr ); /* push SR onto stack */
+ m_sh2_state->r[15] -= 4;
+ WL( m_sh2_state->r[15], m_sh2_state->pc ); /* push PC onto stack */
+
+ /* set I flags in SR */
+ if (irqline > SH2_INT_15)
+ m_sh2_state->sr = m_sh2_state->sr | I;
+ else
+ m_sh2_state->sr = (m_sh2_state->sr & ~I) | (irqline << 4);
- /* fetch PC */
- sh2->pc = RL( sh2, sh2->vbr + vector * 4 );
+ /* fetch PC */
+ m_sh2_state->pc = RL( m_sh2_state->vbr + vector * 4 );
}
- if(sh2->sleep_mode == 1) { sh2->sleep_mode = 2; }
+ if(m_sh2_state->sleep_mode == 1) { m_sh2_state->sleep_mode = 2; }
}
-void sh2_common_init(sh2_state *sh2, legacy_cpu_device *device, device_irq_acknowledge_callback irqcallback, bool drc)
-{
- const sh2_cpu_core *conf = (const sh2_cpu_core *)device->static_config();
- int i;
-
- sh2->isdrc = drc;
- sh2->timer = device->machine().scheduler().timer_alloc(FUNC(sh2_timer_callback), sh2);
- sh2->timer->adjust(attotime::never);
-
- sh2->dma_current_active_timer[0] = device->machine().scheduler().timer_alloc(FUNC(sh2_dma_current_active_callback), sh2);
- sh2->dma_current_active_timer[0]->adjust(attotime::never);
-
- sh2->dma_current_active_timer[1] = device->machine().scheduler().timer_alloc(FUNC(sh2_dma_current_active_callback), sh2);
- sh2->dma_current_active_timer[1]->adjust(attotime::never);
-
- if(conf)
- {
- sh2->is_slave = conf->is_slave;
- sh2->dma_callback_kludge = conf->dma_callback_kludge;
- sh2->dma_callback_fifo_data_available = conf->dma_callback_fifo_data_available;
- }
- else
- {
- sh2->is_slave = 0;
- sh2->dma_callback_kludge = NULL;
- sh2->dma_callback_fifo_data_available = NULL;
-
- }
- sh2->irq_callback = irqcallback;
- sh2->device = device;
- sh2->program = &device->space(AS_PROGRAM);
- sh2->direct = &sh2->program->direct();
- sh2->internal = &device->space(AS_PROGRAM);
-
- device->save_item(NAME(sh2->pc));
- device->save_item(NAME(sh2->sr));
- device->save_item(NAME(sh2->pr));
- device->save_item(NAME(sh2->gbr));
- device->save_item(NAME(sh2->vbr));
- device->save_item(NAME(sh2->mach));
- device->save_item(NAME(sh2->macl));
- device->save_item(NAME(sh2->r));
- device->save_item(NAME(sh2->ea));
- device->save_item(NAME(sh2->delay));
- device->save_item(NAME(sh2->cpu_off));
- device->save_item(NAME(sh2->dvsr));
- device->save_item(NAME(sh2->dvdnth));
- device->save_item(NAME(sh2->dvdntl));
- device->save_item(NAME(sh2->dvcr));
- device->save_item(NAME(sh2->pending_irq));
- device->save_item(NAME(sh2->test_irq));
- device->save_item(NAME(sh2->pending_nmi));
- device->save_item(NAME(sh2->irqline));
- device->save_item(NAME(sh2->evec));
- device->save_item(NAME(sh2->irqsr));
- device->save_item(NAME(sh2->target));
- for (i = 0; i < 16; ++i)
- {
- device->save_item(NAME(sh2->irq_queue[i].irq_vector), i);
- device->save_item(NAME(sh2->irq_queue[i].irq_priority), i);
- }
- device->save_item(NAME(sh2->pcfsel));
- device->save_item(NAME(sh2->maxpcfsel));
- device->save_item(NAME(sh2->pcflushes));
- device->save_item(NAME(sh2->irq_line_state));
- device->save_pointer(NAME(sh2->m), 0x200/4);
- device->save_item(NAME(sh2->nmi_line_state));
- device->save_item(NAME(sh2->frc));
- device->save_item(NAME(sh2->ocra));
- device->save_item(NAME(sh2->ocrb));
- device->save_item(NAME(sh2->icr));
- device->save_item(NAME(sh2->frc_base));
- device->save_item(NAME(sh2->frt_input));
- device->save_item(NAME(sh2->internal_irq_level));
- device->save_item(NAME(sh2->internal_irq_vector));
- device->save_item(NAME(sh2->dma_timer_active));
- device->save_item(NAME(sh2->dma_irq));
- device->save_item(NAME(sh2->wtcnt));
- device->save_item(NAME(sh2->wtcsr));
- device->save_item(NAME(sh2->sleep_mode));
-}
diff --git a/src/emu/cpu/sh2/sh2comn.h b/src/emu/cpu/sh2/sh2comn.h
index 813b5685abf..f92407e6d27 100644
--- a/src/emu/cpu/sh2/sh2comn.h
+++ b/src/emu/cpu/sh2/sh2comn.h
@@ -16,19 +16,11 @@
// do we use a timer for the DMA, or have it in CPU_EXECUTE
#define USE_TIMER_FOR_DMA
-#include "cpu/drcfe.h"
#include "cpu/drcuml.h"
#include "cpu/drcumlsh.h"
-class sh2_frontend;
#define SH2_CODE_XOR(a) ((a) ^ NATIVE_ENDIAN_VALUE_LE_BE(2,0))
-struct irq_entry
-{
- int irq_vector;
- int irq_priority;
-};
-
enum
{
ICF = 0x00800000,
@@ -66,164 +58,26 @@ enum
#define CHECK_PENDING_IRQ(message) \
do { \
int irq = -1; \
- if (sh2->pending_irq & (1 << 0)) irq = 0; \
- if (sh2->pending_irq & (1 << 1)) irq = 1; \
- if (sh2->pending_irq & (1 << 2)) irq = 2; \
- if (sh2->pending_irq & (1 << 3)) irq = 3; \
- if (sh2->pending_irq & (1 << 4)) irq = 4; \
- if (sh2->pending_irq & (1 << 5)) irq = 5; \
- if (sh2->pending_irq & (1 << 6)) irq = 6; \
- if (sh2->pending_irq & (1 << 7)) irq = 7; \
- if (sh2->pending_irq & (1 << 8)) irq = 8; \
- if (sh2->pending_irq & (1 << 9)) irq = 9; \
- if (sh2->pending_irq & (1 << 10)) irq = 10; \
- if (sh2->pending_irq & (1 << 11)) irq = 11; \
- if (sh2->pending_irq & (1 << 12)) irq = 12; \
- if (sh2->pending_irq & (1 << 13)) irq = 13; \
- if (sh2->pending_irq & (1 << 14)) irq = 14; \
- if (sh2->pending_irq & (1 << 15)) irq = 15; \
- if ((sh2->internal_irq_level != -1) && (sh2->internal_irq_level > irq)) irq = sh2->internal_irq_level; \
+ if (m_sh2_state->pending_irq & (1 << 0)) irq = 0; \
+ if (m_sh2_state->pending_irq & (1 << 1)) irq = 1; \
+ if (m_sh2_state->pending_irq & (1 << 2)) irq = 2; \
+ if (m_sh2_state->pending_irq & (1 << 3)) irq = 3; \
+ if (m_sh2_state->pending_irq & (1 << 4)) irq = 4; \
+ if (m_sh2_state->pending_irq & (1 << 5)) irq = 5; \
+ if (m_sh2_state->pending_irq & (1 << 6)) irq = 6; \
+ if (m_sh2_state->pending_irq & (1 << 7)) irq = 7; \
+ if (m_sh2_state->pending_irq & (1 << 8)) irq = 8; \
+ if (m_sh2_state->pending_irq & (1 << 9)) irq = 9; \
+ if (m_sh2_state->pending_irq & (1 << 10)) irq = 10; \
+ if (m_sh2_state->pending_irq & (1 << 11)) irq = 11; \
+ if (m_sh2_state->pending_irq & (1 << 12)) irq = 12; \
+ if (m_sh2_state->pending_irq & (1 << 13)) irq = 13; \
+ if (m_sh2_state->pending_irq & (1 << 14)) irq = 14; \
+ if (m_sh2_state->pending_irq & (1 << 15)) irq = 15; \
+ if ((m_sh2_state->internal_irq_level != -1) && (m_sh2_state->internal_irq_level > irq)) irq = m_sh2_state->internal_irq_level; \
if (irq >= 0) \
- sh2_exception(sh2,message,irq); \
+ sh2_exception(message,irq); \
} while(0)
-/* fast RAM info */
-struct fast_ram_info
-{
- offs_t start; /* start of the RAM block */
- offs_t end; /* end of the RAM block */
- UINT8 readonly; /* TRUE if read-only */
- void * base; /* base in memory where the RAM lives */
-};
-
-struct sh2_state
-{
- UINT32 ppc;
- UINT32 pc;
- UINT32 pr;
- UINT32 sr;
- UINT32 gbr, vbr;
- UINT32 mach, macl;
- UINT32 r[16];
- UINT32 ea;
- UINT32 delay;
- UINT32 cpu_off;
- UINT32 dvsr, dvdnth, dvdntl, dvcr;
- UINT32 pending_irq;
- UINT32 test_irq;
- UINT32 pending_nmi;
- INT32 irqline;
- UINT32 evec; // exception vector for DRC
- UINT32 irqsr; // IRQ-time old SR for DRC
- UINT32 target; // target for jmp/jsr/etc so the delay slot can't kill it
- irq_entry irq_queue[16];
-
- bool isdrc;
-
- int pcfsel; // last pcflush entry set
- int maxpcfsel; // highest valid pcflush entry
- UINT32 pcflushes[16]; // pcflush entries
-
- INT8 irq_line_state[17];
- device_irq_acknowledge_callback irq_callback;
- legacy_cpu_device *device;
- address_space *program;
- direct_read_data *direct;
- address_space *internal;
- UINT32 m[0x200/4];
- INT8 nmi_line_state;
-
- UINT16 frc;
- UINT16 ocra, ocrb, icr;
- UINT64 frc_base;
-
- int frt_input;
- int internal_irq_level;
- int internal_irq_vector;
- int icount;
-
- emu_timer *timer;
- emu_timer *dma_current_active_timer[2];
- int dma_timer_active[2];
- UINT8 dma_irq[2];
-
- int active_dma_incs[2];
- int active_dma_incd[2];
- int active_dma_size[2];
- int active_dma_steal[2];
- UINT32 active_dma_src[2];
- UINT32 active_dma_dst[2];
- UINT32 active_dma_count[2];
- UINT16 wtcnt;
- UINT8 wtcsr;
-
- UINT8 sleep_mode;
-
- int is_slave, cpu_type;
- int (*dma_callback_kludge)(device_t *device, UINT32 src, UINT32 dst, UINT32 data, int size);
- int (*dma_callback_fifo_data_available)(device_t *device, UINT32 src, UINT32 dst, UINT32 data, int size);
-
- void (*ftcsr_read_callback)(UINT32 data);
-
- drc_cache * cache; /* pointer to the DRC code cache */
- drcuml_state * drcuml; /* DRC UML generator state */
- sh2_frontend * drcfe; /* pointer to the DRC front-end state */
- UINT32 drcoptions; /* configurable DRC options */
-
- /* internal stuff */
- UINT8 cache_dirty; /* true if we need to flush the cache */
-
- /* parameters for subroutines */
- UINT64 numcycles; /* return value from gettotalcycles */
- UINT32 arg0; /* print_debug argument 1 */
- UINT32 arg1; /* print_debug argument 2 */
- UINT32 irq; /* irq we're taking */
-
- /* register mappings */
- uml::parameter regmap[16]; /* parameter to register mappings for all 16 integer registers */
-
- uml::code_handle * entry; /* entry point */
- uml::code_handle * read8; /* read byte */
- uml::code_handle * write8; /* write byte */
- uml::code_handle * read16; /* read half */
- uml::code_handle * write16; /* write half */
- uml::code_handle * read32; /* read word */
- uml::code_handle * write32; /* write word */
-
- uml::code_handle * interrupt; /* interrupt */
- uml::code_handle * nocode; /* nocode */
- uml::code_handle * out_of_cycles; /* out of cycles exception handler */
-
- /* fast RAM */
- UINT32 fastram_select;
- fast_ram_info fastram[SH2_MAX_FASTRAM];
-};
-
-class sh2_frontend : public drc_frontend
-{
-public:
- sh2_frontend(sh2_state &state, UINT32 window_start, UINT32 window_end, UINT32 max_sequence);
-
-protected:
- virtual bool describe(opcode_desc &desc, const opcode_desc *prev);
-
-private:
- bool describe_group_0(opcode_desc &desc, const opcode_desc *prev, UINT16 opcode);
- bool describe_group_2(opcode_desc &desc, const opcode_desc *prev, UINT16 opcode);
- bool describe_group_3(opcode_desc &desc, const opcode_desc *prev, UINT16 opcode);
- bool describe_group_4(opcode_desc &desc, const opcode_desc *prev, UINT16 opcode);
- bool describe_group_6(opcode_desc &desc, const opcode_desc *prev, UINT16 opcode);
- bool describe_group_8(opcode_desc &desc, const opcode_desc *prev, UINT16 opcode);
- bool describe_group_12(opcode_desc &desc, const opcode_desc *prev, UINT16 opcode);
-
- sh2_state &m_context;
-};
-
-void sh2_common_init(sh2_state *sh2, legacy_cpu_device *device, device_irq_acknowledge_callback irqcallback, bool drc);
-void sh2_recalc_irq(sh2_state *sh2);
-void sh2_set_irq_line(sh2_state *sh2, int irqline, int state);
-void sh2_exception(sh2_state *sh2, const char *message, int irqline);
-void sh2_do_dma(sh2_state *sh2, int dma);
-void sh2_notify_dma_data_available(device_t *device);
#endif /* __SH2COMN_H__ */
diff --git a/src/emu/cpu/sh2/sh2drc.c b/src/emu/cpu/sh2/sh2drc.c
index d4a6c5b577b..faa6dd99cbc 100644
--- a/src/emu/cpu/sh2/sh2drc.c
+++ b/src/emu/cpu/sh2/sh2drc.c
@@ -12,7 +12,6 @@
#include "sh2.h"
#include "sh2comn.h"
-CPU_DISASSEMBLE( sh2 );
extern unsigned DasmSH2(char *buffer, unsigned pc, UINT16 opcode);
using namespace uml;
@@ -21,21 +20,12 @@ using namespace uml;
DEBUGGING
***************************************************************************/
-#define LOG_UML (0) // log UML assembly
-#define LOG_NATIVE (0) // log native assembly
-
#define SET_EA (0) // makes slower but "shows work" in the EA fake register like the interpreter
-#define DISABLE_FAST_REGISTERS (0) // set to 1 to turn off usage of register caching
-#define SINGLE_INSTRUCTION_MODE (0)
-
#define ADDSUBV_DIRECT (0)
-#define VERBOSE 0
-#define LOG(x) do { if (VERBOSE) logerror x; } while (0)
-
#if SET_EA
-#define SETEA(x) UML_MOV(block, mem(&sh2->ea), ireg(x))
+#define SETEA(x) UML_MOV(block, mem(&m_sh2_state->ea), ireg(x))
#else
#define SETEA(x)
#endif
@@ -48,15 +38,6 @@ using namespace uml;
#define MAPVAR_PC M0
#define MAPVAR_CYCLES M1
-/* size of the execution code cache */
-#define CACHE_SIZE (32 * 1024 * 1024)
-
-/* compilation boundaries -- how far back/forward does the analysis extend? */
-#define COMPILE_BACKWARDS_BYTES 64
-#define COMPILE_FORWARDS_BYTES 256
-#define COMPILE_MAX_INSTRUCTIONS ((COMPILE_BACKWARDS_BYTES/2) + (COMPILE_FORWARDS_BYTES/2))
-#define COMPILE_MAX_SEQUENCE 64
-
/* exit codes */
#define EXECUTE_OUT_OF_CYCLES 0
#define EXECUTE_MISSING_CODE 1
@@ -65,103 +46,23 @@ using namespace uml;
#define PROBE_ADDRESS ~0
-extern int sh2_describe(void *param, opcode_desc *desc, const opcode_desc *prev);
/***************************************************************************
MACROS
***************************************************************************/
-#define R32(reg) sh2->regmap[reg]
-
-/***************************************************************************
- STRUCTURES & TYPEDEFS
-***************************************************************************/
-
-/* internal compiler state */
-struct compiler_state
-{
- UINT32 cycles; /* accumulated cycles */
- UINT8 checkints; /* need to check interrupts before next instruction */
- code_label labelnum; /* index for local labels */
-};
-
-/***************************************************************************
- FUNCTION PROTOTYPES
-***************************************************************************/
-
-static void static_generate_entry_point(sh2_state *sh2);
-static void static_generate_nocode_handler(sh2_state *sh2);
-static void static_generate_out_of_cycles(sh2_state *sh2);
-static void static_generate_memory_accessor(sh2_state *sh2, int size, int iswrite, const char *name, code_handle **handleptr);
-
-static void generate_update_cycles(sh2_state *sh2, drcuml_block *block, compiler_state *compiler, parameter param, int allow_exception);
-static void generate_checksum_block(sh2_state *sh2, drcuml_block *block, compiler_state *compiler, const opcode_desc *seqhead, const opcode_desc *seqlast);
-static void generate_sequence_instruction(sh2_state *sh2, drcuml_block *block, compiler_state *compiler, const opcode_desc *desc, UINT32 ovrpc);
-static void generate_delay_slot(sh2_state *sh2, drcuml_block *block, compiler_state *compiler, const opcode_desc *desc, UINT32 ovrpc);
-
-static int generate_opcode(sh2_state *sh2, drcuml_block *block, compiler_state *compiler, const opcode_desc *desc, UINT32 ovrpc);
-static int generate_group_0(sh2_state *sh2, drcuml_block *block, compiler_state *compiler, const opcode_desc *desc, UINT16 opcode, int in_delay_slot, UINT32 ovrpc);
-static int generate_group_2(sh2_state *sh2, drcuml_block *block, compiler_state *compiler, const opcode_desc *desc, UINT16 opcode, int in_delay_slot, UINT32 ovrpc);
-static int generate_group_3(sh2_state *sh2, drcuml_block *block, compiler_state *compiler, const opcode_desc *desc, UINT16 opcode, UINT32 ovrpc);
-static int generate_group_4(sh2_state *sh2, drcuml_block *block, compiler_state *compiler, const opcode_desc *desc, UINT16 opcode, int in_delay_slot, UINT32 ovrpc);
-static int generate_group_6(sh2_state *sh2, drcuml_block *block, compiler_state *compiler, const opcode_desc *desc, UINT16 opcode, int in_delay_slot, UINT32 ovrpc);
-static int generate_group_8(sh2_state *sh2, drcuml_block *block, compiler_state *compiler, const opcode_desc *desc, UINT16 opcode, int in_delay_slot, UINT32 ovrpc);
-static int generate_group_12(sh2_state *sh2, drcuml_block *block, compiler_state *compiler, const opcode_desc *desc, UINT16 opcode, int in_delay_slot, UINT32 ovrpc);
-
-static void code_compile_block(sh2_state *sh2, UINT8 mode, offs_t pc);
-
-static void log_opcode_desc(drcuml_state *drcuml, const opcode_desc *desclist, int indent);
-static void log_register_list(drcuml_state *drcuml, const char *string, const UINT32 *reglist, const UINT32 *regnostarlist);
-static void log_add_disasm_comment(drcuml_block *block, UINT32 pc, UINT32 op);
-static const char *log_desc_flags_to_string(UINT32 flags);
-
-static void cfunc_printf_probe(void *param);
-static void cfunc_unimplemented(void *param);
-static void cfunc_fastirq(void *param);
-static void cfunc_MAC_W(void *param);
-static void cfunc_MAC_L(void *param);
-static void cfunc_DIV1(void *param);
+#define R32(reg) m_regmap[reg]
/***************************************************************************
INLINE FUNCTIONS
***************************************************************************/
-INLINE sh2_state *get_safe_token(device_t *device)
-{
- assert(device != NULL);
- assert(device->type() == SH1_DRC ||
- device->type() == SH2_DRC);
- return *(sh2_state **)downcast<legacy_cpu_device *>(device)->token();
-}
-
-INLINE UINT16 RW(sh2_state *sh2, offs_t A)
-{
- if (A >= 0xe0000000)
- return sh2_internal_r(*sh2->internal, (A & 0x1fc)>>2, 0xffff << (((~A) & 2)*8)) >> (((~A) & 2)*8);
-
- if (A >= 0xc0000000)
- return sh2->program->read_word(A);
-
- return sh2->program->read_word(A & AM);
-}
-
-INLINE UINT32 RL(sh2_state *sh2, offs_t A)
-{
- if (A >= 0xe0000000)
- return sh2_internal_r(*sh2->internal, (A & 0x1fc)>>2, 0xffffffff);
-
- if (A >= 0xc0000000)
- return sh2->program->read_dword(A);
-
- return sh2->program->read_dword(A & AM);
-}
-
/*-------------------------------------------------
epc - compute the exception PC from a
descriptor
-------------------------------------------------*/
-INLINE UINT32 epc(const opcode_desc *desc)
+UINT32 sh2_device::epc(const opcode_desc *desc)
{
return (desc->flags & OPFLAG_IN_DELAY_SLOT) ? (desc->pc - 1) : desc->pc;
}
@@ -171,7 +72,7 @@ INLINE UINT32 epc(const opcode_desc *desc)
already allocated
-------------------------------------------------*/
-INLINE void alloc_handle(drcuml_state *drcuml, code_handle **handleptr, const char *name)
+void sh2_device::alloc_handle(drcuml_state *drcuml, code_handle **handleptr, const char *name)
{
if (*handleptr == NULL)
*handleptr = drcuml->handle_alloc(name);
@@ -182,15 +83,15 @@ INLINE void alloc_handle(drcuml_state *drcuml, code_handle **handleptr, const ch
registers
-------------------------------------------------*/
-INLINE void load_fast_iregs(sh2_state *sh2, drcuml_block *block)
+void sh2_device::load_fast_iregs(drcuml_block *block)
{
int regnum;
- for (regnum = 0; regnum < ARRAY_LENGTH(sh2->regmap); regnum++)
+ for (regnum = 0; regnum < ARRAY_LENGTH(m_regmap); regnum++)
{
- if (sh2->regmap[regnum].is_int_register())
+ if (m_regmap[regnum].is_int_register())
{
- UML_MOV(block, parameter::make_ireg(sh2->regmap[regnum].ireg()), mem(&sh2->r[regnum]));
+ UML_MOV(block, parameter::make_ireg(m_regmap[regnum].ireg()), mem(&m_sh2_state->r[regnum]));
}
}
}
@@ -201,15 +102,15 @@ INLINE void load_fast_iregs(sh2_state *sh2, drcuml_block *block)
registers
-------------------------------------------------*/
-INLINE void save_fast_iregs(sh2_state *sh2, drcuml_block *block)
+void sh2_device::save_fast_iregs(drcuml_block *block)
{
int regnum;
- for (regnum = 0; regnum < ARRAY_LENGTH(sh2->regmap); regnum++)
+ for (regnum = 0; regnum < ARRAY_LENGTH(m_regmap); regnum++)
{
- if (sh2->regmap[regnum].is_int_register())
+ if (m_regmap[regnum].is_int_register())
{
- UML_MOV(block, mem(&sh2->r[regnum]), parameter::make_ireg(sh2->regmap[regnum].ireg()));
+ UML_MOV(block, mem(&m_sh2_state->r[regnum]), parameter::make_ireg(m_regmap[regnum].ireg()));
}
}
}
@@ -221,37 +122,41 @@ INLINE void save_fast_iregs(sh2_state *sh2, drcuml_block *block)
static void cfunc_printf_probe(void *param)
{
- sh2_state *sh2 = (sh2_state *)param;
- UINT32 pc = sh2->pc;
+ ((sh2_device *)param)->func_printf_probe();
+}
+
+void sh2_device::func_printf_probe()
+{
+ UINT32 pc = m_sh2_state->pc;
printf(" PC=%08X r0=%08X r1=%08X r2=%08X\n",
pc,
- (UINT32)sh2->r[0],
- (UINT32)sh2->r[1],
- (UINT32)sh2->r[2]);
+ (UINT32)m_sh2_state->r[0],
+ (UINT32)m_sh2_state->r[1],
+ (UINT32)m_sh2_state->r[2]);
printf(" r3=%08X r4=%08X r5=%08X r6=%08X\n",
- (UINT32)sh2->r[3],
- (UINT32)sh2->r[4],
- (UINT32)sh2->r[5],
- (UINT32)sh2->r[6]);
+ (UINT32)m_sh2_state->r[3],
+ (UINT32)m_sh2_state->r[4],
+ (UINT32)m_sh2_state->r[5],
+ (UINT32)m_sh2_state->r[6]);
printf(" r7=%08X r8=%08X r9=%08X r10=%08X\n",
- (UINT32)sh2->r[7],
- (UINT32)sh2->r[8],
- (UINT32)sh2->r[9],
- (UINT32)sh2->r[10]);
+ (UINT32)m_sh2_state->r[7],
+ (UINT32)m_sh2_state->r[8],
+ (UINT32)m_sh2_state->r[9],
+ (UINT32)m_sh2_state->r[10]);
printf(" r11=%08X r12=%08X r13=%08X r14=%08X\n",
- (UINT32)sh2->r[11],
- (UINT32)sh2->r[12],
- (UINT32)sh2->r[13],
- (UINT32)sh2->r[14]);
+ (UINT32)m_sh2_state->r[11],
+ (UINT32)m_sh2_state->r[12],
+ (UINT32)m_sh2_state->r[13],
+ (UINT32)m_sh2_state->r[14]);
printf(" r15=%08X macl=%08X mach=%08X gbr=%08X\n",
- (UINT32)sh2->r[15],
- (UINT32)sh2->macl,
- (UINT32)sh2->mach,
- (UINT32)sh2->gbr);
+ (UINT32)m_sh2_state->r[15],
+ (UINT32)m_sh2_state->macl,
+ (UINT32)m_sh2_state->mach,
+ (UINT32)m_sh2_state->gbr);
printf(" evec %x irqsr %x pc=%08x\n",
- (UINT32)sh2->evec,
- (UINT32)sh2->irqsr, (UINT32)sh2->pc);
+ (UINT32)m_sh2_state->evec,
+ (UINT32)m_sh2_state->irqsr, (UINT32)m_sh2_state->pc);
}
/*-------------------------------------------------
@@ -261,14 +166,17 @@ static void cfunc_printf_probe(void *param)
static void cfunc_unimplemented(void *param)
{
- sh2_state *sh2 = (sh2_state *)param;
+ ((sh2_device *)param)->func_unimplemented();
+}
+void sh2_device::func_unimplemented()
+{
// set up an invalid opcode exception
- sh2->evec = RL( sh2, sh2->vbr + 4 * 4 );
- sh2->evec &= AM;
- sh2->irqsr = sh2->sr;
+ m_sh2_state->evec = RL( m_sh2_state->vbr + 4 * 4 );
+ m_sh2_state->evec &= AM;
+ m_sh2_state->irqsr = m_sh2_state->sr;
// claim it's an NMI, because it pretty much is
- sh2->pending_nmi = 1;
+ m_sh2_state->pending_nmi = 1;
}
/*-------------------------------------------------
@@ -276,8 +184,12 @@ static void cfunc_unimplemented(void *param)
-------------------------------------------------*/
static void cfunc_fastirq(void *param)
{
- sh2_state *sh2 = (sh2_state *)param;
- sh2_exception(sh2, "fastirq",sh2->irqline);
+ ((sh2_device *)param)->func_fastirq();
+}
+
+void sh2_device::func_fastirq()
+{
+ sh2_exception("fastirq",m_sh2_state->irqline);
}
/*-------------------------------------------------
@@ -285,26 +197,30 @@ static void cfunc_fastirq(void *param)
-------------------------------------------------*/
static void cfunc_MAC_W(void *param)
{
- sh2_state *sh2 = (sh2_state *)param;
+ ((sh2_device *)param)->func_MAC_W();
+}
+
+void sh2_device::func_MAC_W()
+{
INT32 tempm, tempn, dest, src, ans;
UINT32 templ;
UINT16 opcode;
int n, m;
// recover the opcode
- opcode = sh2->arg0;
+ opcode = m_sh2_state->arg0;
// extract the operands
n = Rn;
m = Rm;
- tempn = (INT32) RW( sh2, sh2->r[n] );
- sh2->r[n] += 2;
- tempm = (INT32) RW( sh2, sh2->r[m] );
- sh2->r[m] += 2;
- templ = sh2->macl;
+ tempn = (INT32) RW( m_sh2_state->r[n] );
+ m_sh2_state->r[n] += 2;
+ tempm = (INT32) RW( m_sh2_state->r[m] );
+ m_sh2_state->r[m] += 2;
+ templ = m_sh2_state->macl;
tempm = ((INT32) (short) tempn * (INT32) (short) tempm);
- if ((INT32) sh2->macl >= 0)
+ if ((INT32) m_sh2_state->macl >= 0)
dest = 0;
else
dest = 1;
@@ -319,43 +235,43 @@ static void cfunc_MAC_W(void *param)
tempn = 0xffffffff;
}
src += dest;
- sh2->macl += tempm;
- if ((INT32) sh2->macl >= 0)
+ m_sh2_state->macl += tempm;
+ if ((INT32) m_sh2_state->macl >= 0)
ans = 0;
else
ans = 1;
ans += dest;
- if (sh2->sr & S)
+ if (m_sh2_state->sr & S)
{
if (ans == 1)
{
- if ((sh2->cpu_type == CPU_TYPE_SH1) && ((src == 0) || (src == 2)))
+ if ((m_cpu_type == CPU_TYPE_SH1) && ((src == 0) || (src == 2)))
{
- sh2->mach |= 0x00000001;
+ m_sh2_state->mach |= 0x00000001;
}
if (src == 0)
- sh2->macl = 0x7fffffff;
+ m_sh2_state->macl = 0x7fffffff;
if (src == 2)
- sh2->macl = 0x80000000;
+ m_sh2_state->macl = 0x80000000;
}
}
else
{
- sh2->mach += tempn;
- if (templ > sh2->macl)
- sh2->mach += 1;
+ m_sh2_state->mach += tempn;
+ if (templ > m_sh2_state->macl)
+ m_sh2_state->mach += 1;
// SH-1 has limited precision
- if (sh2->cpu_type == CPU_TYPE_SH1)
+ if (m_cpu_type == CPU_TYPE_SH1)
{
- if ((sh2->mach & 0x200) == 0)
+ if ((m_sh2_state->mach & 0x200) == 0)
{
- sh2->mach &= 0x3ff;
+ m_sh2_state->mach &= 0x3ff;
}
else
{
- sh2->mach |= 0xfffffc00;
+ m_sh2_state->mach |= 0xfffffc00;
}
}
@@ -368,7 +284,11 @@ static void cfunc_MAC_W(void *param)
-------------------------------------------------*/
static void cfunc_MAC_L(void *param)
{
- sh2_state *sh2 = (sh2_state *)param;
+ ((sh2_device *)param)->func_MAC_L();
+}
+
+void sh2_device::func_MAC_L()
+{
UINT32 RnL, RnH, RmL, RmH, Res0, Res1, Res2;
UINT32 temp0, temp1, temp2, temp3;
INT32 tempm, tempn, fnLmL;
@@ -376,16 +296,16 @@ static void cfunc_MAC_L(void *param)
int n, m;
// recover the opcode
- opcode = sh2->arg0;
+ opcode = m_sh2_state->arg0;
// extract the operands
n = Rn;
m = Rm;
- tempn = (INT32) RL( sh2, sh2->r[n] );
- sh2->r[n] += 4;
- tempm = (INT32) RL( sh2, sh2->r[m] );
- sh2->r[m] += 4;
+ tempn = (INT32) RL( m_sh2_state->r[n] );
+ m_sh2_state->r[n] += 4;
+ tempm = (INT32) RL( m_sh2_state->r[m] );
+ m_sh2_state->r[m] += 4;
if ((INT32) (tempn ^ tempm) < 0)
fnLmL = -1;
else
@@ -421,12 +341,12 @@ static void cfunc_MAC_L(void *param)
else
Res0 = (~Res0) + 1;
}
- if (sh2->sr & S)
+ if (m_sh2_state->sr & S)
{
- Res0 = sh2->macl + Res0;
- if (sh2->macl > Res0)
+ Res0 = m_sh2_state->macl + Res0;
+ if (m_sh2_state->macl > Res0)
Res2++;
- Res2 += (sh2->mach & 0x0000ffff);
+ Res2 += (m_sh2_state->mach & 0x0000ffff);
if (((INT32) Res2 < 0) && (Res2 < 0xffff8000))
{
Res2 = 0x00008000;
@@ -437,17 +357,17 @@ static void cfunc_MAC_L(void *param)
Res2 = 0x00007fff;
Res0 = 0xffffffff;
}
- sh2->mach = Res2;
- sh2->macl = Res0;
+ m_sh2_state->mach = Res2;
+ m_sh2_state->macl = Res0;
}
else
{
- Res0 = sh2->macl + Res0;
- if (sh2->macl > Res0)
+ Res0 = m_sh2_state->macl + Res0;
+ if (m_sh2_state->macl > Res0)
Res2++;
- Res2 += sh2->mach;
- sh2->mach = Res2;
- sh2->macl = Res0;
+ Res2 += m_sh2_state->mach;
+ m_sh2_state->mach = Res2;
+ m_sh2_state->macl = Res0;
}
}
@@ -456,103 +376,107 @@ static void cfunc_MAC_L(void *param)
-------------------------------------------------*/
static void cfunc_DIV1(void *param)
{
- sh2_state *sh2 = (sh2_state *)param;
+ ((sh2_device *)param)->func_DIV1();
+}
+
+void sh2_device::func_DIV1()
+{
UINT32 tmp0;
UINT32 old_q;
UINT16 opcode;
int n, m;
// recover the opcode
- opcode = sh2->arg0;
+ opcode = m_sh2_state->arg0;
// extract the operands
n = Rn;
m = Rm;
- old_q = sh2->sr & Q;
- if (0x80000000 & sh2->r[n])
- sh2->sr |= Q;
+ old_q = m_sh2_state->sr & Q;
+ if (0x80000000 & m_sh2_state->r[n])
+ m_sh2_state->sr |= Q;
else
- sh2->sr &= ~Q;
+ m_sh2_state->sr &= ~Q;
- sh2->r[n] = (sh2->r[n] << 1) | (sh2->sr & T);
+ m_sh2_state->r[n] = (m_sh2_state->r[n] << 1) | (m_sh2_state->sr & T);
if (!old_q)
{
- if (!(sh2->sr & M))
+ if (!(m_sh2_state->sr & M))
{
- tmp0 = sh2->r[n];
- sh2->r[n] -= sh2->r[m];
- if(!(sh2->sr & Q))
- if(sh2->r[n] > tmp0)
- sh2->sr |= Q;
+ tmp0 = m_sh2_state->r[n];
+ m_sh2_state->r[n] -= m_sh2_state->r[m];
+ if(!(m_sh2_state->sr & Q))
+ if(m_sh2_state->r[n] > tmp0)
+ m_sh2_state->sr |= Q;
else
- sh2->sr &= ~Q;
+ m_sh2_state->sr &= ~Q;
else
- if(sh2->r[n] > tmp0)
- sh2->sr &= ~Q;
+ if(m_sh2_state->r[n] > tmp0)
+ m_sh2_state->sr &= ~Q;
else
- sh2->sr |= Q;
+ m_sh2_state->sr |= Q;
}
else
{
- tmp0 = sh2->r[n];
- sh2->r[n] += sh2->r[m];
- if(!(sh2->sr & Q))
+ tmp0 = m_sh2_state->r[n];
+ m_sh2_state->r[n] += m_sh2_state->r[m];
+ if(!(m_sh2_state->sr & Q))
{
- if(sh2->r[n] < tmp0)
- sh2->sr &= ~Q;
+ if(m_sh2_state->r[n] < tmp0)
+ m_sh2_state->sr &= ~Q;
else
- sh2->sr |= Q;
+ m_sh2_state->sr |= Q;
}
else
{
- if(sh2->r[n] < tmp0)
- sh2->sr |= Q;
+ if(m_sh2_state->r[n] < tmp0)
+ m_sh2_state->sr |= Q;
else
- sh2->sr &= ~Q;
+ m_sh2_state->sr &= ~Q;
}
}
}
else
{
- if (!(sh2->sr & M))
+ if (!(m_sh2_state->sr & M))
{
- tmp0 = sh2->r[n];
- sh2->r[n] += sh2->r[m];
- if(!(sh2->sr & Q))
- if(sh2->r[n] < tmp0)
- sh2->sr |= Q;
+ tmp0 = m_sh2_state->r[n];
+ m_sh2_state->r[n] += m_sh2_state->r[m];
+ if(!(m_sh2_state->sr & Q))
+ if(m_sh2_state->r[n] < tmp0)
+ m_sh2_state->sr |= Q;
else
- sh2->sr &= ~Q;
+ m_sh2_state->sr &= ~Q;
else
- if(sh2->r[n] < tmp0)
- sh2->sr &= ~Q;
+ if(m_sh2_state->r[n] < tmp0)
+ m_sh2_state->sr &= ~Q;
else
- sh2->sr |= Q;
+ m_sh2_state->sr |= Q;
}
else
{
- tmp0 = sh2->r[n];
- sh2->r[n] -= sh2->r[m];
- if(!(sh2->sr & Q))
- if(sh2->r[n] > tmp0)
- sh2->sr &= ~Q;
+ tmp0 = m_sh2_state->r[n];
+ m_sh2_state->r[n] -= m_sh2_state->r[m];
+ if(!(m_sh2_state->sr & Q))
+ if(m_sh2_state->r[n] > tmp0)
+ m_sh2_state->sr &= ~Q;
else
- sh2->sr |= Q;
+ m_sh2_state->sr |= Q;
else
- if(sh2->r[n] > tmp0)
- sh2->sr |= Q;
+ if(m_sh2_state->r[n] > tmp0)
+ m_sh2_state->sr |= Q;
else
- sh2->sr &= ~Q;
+ m_sh2_state->sr &= ~Q;
}
}
- tmp0 = (sh2->sr & (Q | M));
+ tmp0 = (m_sh2_state->sr & (Q | M));
if((!tmp0) || (tmp0 == 0x300)) /* if Q == M set T else clear T */
- sh2->sr |= T;
+ m_sh2_state->sr |= T;
else
- sh2->sr &= ~T;
+ m_sh2_state->sr &= ~T;
}
#if (!ADDSUBV_DIRECT)
@@ -561,29 +485,33 @@ static void cfunc_DIV1(void *param)
-------------------------------------------------*/
static void cfunc_ADDV(void *param)
{
- sh2_state *sh2 = (sh2_state *)param;
+ ((sh2_device *)param)->func_ADDV();
+}
+
+void sh2_device::func_ADDV()
+{
INT32 dest, src, ans;
UINT16 opcode;
int n, m;
// recover the opcode
- opcode = sh2->arg0;
+ opcode = m_sh2_state->arg0;
// extract the operands
n = Rn;
m = Rm;
- if ((INT32) sh2->r[n] >= 0)
+ if ((INT32) m_sh2_state->r[n] >= 0)
dest = 0;
else
dest = 1;
- if ((INT32) sh2->r[m] >= 0)
+ if ((INT32) m_sh2_state->r[m] >= 0)
src = 0;
else
src = 1;
src += dest;
- sh2->r[n] += sh2->r[m];
- if ((INT32) sh2->r[n] >= 0)
+ m_sh2_state->r[n] += m_sh2_state->r[m];
+ if ((INT32) m_sh2_state->r[n] >= 0)
ans = 0;
else
ans = 1;
@@ -591,12 +519,12 @@ static void cfunc_ADDV(void *param)
if (src == 0 || src == 2)
{
if (ans == 1)
- sh2->sr |= T;
+ m_sh2_state->sr |= T;
else
- sh2->sr &= ~T;
+ m_sh2_state->sr &= ~T;
}
else
- sh2->sr &= ~T;
+ m_sh2_state->sr &= ~T;
}
/*-------------------------------------------------
@@ -604,29 +532,33 @@ static void cfunc_ADDV(void *param)
-------------------------------------------------*/
static void cfunc_SUBV(void *param)
{
- sh2_state *sh2 = (sh2_state *)param;
+ ((sh2_device *)param)->func_SUBV();
+}
+
+void sh2_device::func_SUBV()
+{
INT32 dest, src, ans;
UINT16 opcode;
int n, m;
// recover the opcode
- opcode = sh2->arg0;
+ opcode = m_sh2_state->arg0;
// extract the operands
n = Rn;
m = Rm;
- if ((INT32) sh2->r[n] >= 0)
+ if ((INT32) m_sh2_state->r[n] >= 0)
dest = 0;
else
dest = 1;
- if ((INT32) sh2->r[m] >= 0)
+ if ((INT32) m_sh2_state->r[m] >= 0)
src = 0;
else
src = 1;
src += dest;
- sh2->r[n] -= sh2->r[m];
- if ((INT32) sh2->r[n] >= 0)
+ m_sh2_state->r[n] -= m_sh2_state->r[m];
+ if ((INT32) m_sh2_state->r[n] >= 0)
ans = 0;
else
ans = 1;
@@ -634,176 +566,26 @@ static void cfunc_SUBV(void *param)
if (src == 1)
{
if (ans == 1)
- sh2->sr |= T;
+ m_sh2_state->sr |= T;
else
- sh2->sr &= ~T;
+ m_sh2_state->sr &= ~T;
}
else
- sh2->sr &= ~T;
+ m_sh2_state->sr &= ~T;
}
+#else
+void sh2_device::func_ADDV() {}
+void sh2_device::func_SUBV() {}
#endif
/*-------------------------------------------------
- sh2_init - initialize the processor
--------------------------------------------------*/
-
-static CPU_INIT( sh2 )
-{
- sh2_state *sh2 = get_safe_token(device);
- drc_cache *cache;
- drcbe_info beinfo;
- UINT32 flags = 0;
- int regnum;
-
- /* allocate enough space for the cache and the core */
- cache = auto_alloc(device->machine(), drc_cache(CACHE_SIZE + sizeof(sh2_state)));
-
- /* allocate the core memory */
- *(sh2_state **)device->token() = sh2 = (sh2_state *)cache->alloc_near(sizeof(sh2_state));
- memset(sh2, 0, sizeof(sh2_state));
-
- /* initialize the common core parts */
- sh2_common_init(sh2, device, irqcallback,true);
-
- /* allocate the implementation-specific state from the full cache */
- sh2->cache = cache;
-
- /* reset per-driver pcflushes */
- sh2->pcfsel = 0;
-
- /* initialize the UML generator */
- if (LOG_UML)
- flags |= DRCUML_OPTION_LOG_UML;
- if (LOG_NATIVE)
- flags |= DRCUML_OPTION_LOG_NATIVE;
- sh2->drcuml = auto_alloc(device->machine(), drcuml_state(*device, *cache, flags, 1, 32, 1));
-
- /* add symbols for our stuff */
- sh2->drcuml->symbol_add(&sh2->pc, sizeof(sh2->pc), "pc");
- sh2->drcuml->symbol_add(&sh2->icount, sizeof(sh2->icount), "icount");
- for (regnum = 0; regnum < 16; regnum++)
- {
- char buf[10];
- sprintf(buf, "r%d", regnum);
- sh2->drcuml->symbol_add(&sh2->r[regnum], sizeof(sh2->r[regnum]), buf);
- }
- sh2->drcuml->symbol_add(&sh2->pr, sizeof(sh2->pr), "pr");
- sh2->drcuml->symbol_add(&sh2->sr, sizeof(sh2->sr), "sr");
- sh2->drcuml->symbol_add(&sh2->gbr, sizeof(sh2->gbr), "gbr");
- sh2->drcuml->symbol_add(&sh2->vbr, sizeof(sh2->vbr), "vbr");
- sh2->drcuml->symbol_add(&sh2->macl, sizeof(sh2->macl), "macl");
- sh2->drcuml->symbol_add(&sh2->mach, sizeof(sh2->macl), "mach");
-
- /* initialize the front-end helper */
- sh2->drcfe = auto_alloc(device->machine(), sh2_frontend(*sh2, COMPILE_BACKWARDS_BYTES, COMPILE_FORWARDS_BYTES, SINGLE_INSTRUCTION_MODE ? 1 : COMPILE_MAX_SEQUENCE));
-
- /* compute the register parameters */
- for (regnum = 0; regnum < 16; regnum++)
- {
- sh2->regmap[regnum] = mem(&sh2->r[regnum]);
- }
-
- /* if we have registers to spare, assign r0, r1, r2 to leftovers */
- /* WARNING: do not use synthetic registers that are mapped here! */
- if (!DISABLE_FAST_REGISTERS)
- {
- sh2->drcuml->get_backend_info(beinfo);
- if (beinfo.direct_iregs > 4)
- {
- sh2->regmap[0] = I4;
- }
- if (beinfo.direct_iregs > 5)
- {
- sh2->regmap[1] = I5;
- }
- if (beinfo.direct_iregs > 6)
- {
- sh2->regmap[2] = I6;
- }
- }
-
- /* mark the cache dirty so it is updated on next execute */
- sh2->cache_dirty = TRUE;
-}
-
-/*-------------------------------------------------
- sh2_exit - cleanup from execution
--------------------------------------------------*/
-
-static CPU_EXIT( sh2 )
-{
- sh2_state *sh2 = get_safe_token(device);
-
- /* clean up the DRC */
- auto_free(device->machine(), sh2->drcfe);
- auto_free(device->machine(), sh2->drcuml);
- auto_free(device->machine(), sh2->cache);
-}
-
-
-/*-------------------------------------------------
- sh2_reset - reset the processor
--------------------------------------------------*/
-
-static CPU_RESET( sh2 )
-{
- sh2_state *sh2 = get_safe_token(device);
-
- void (*f)(UINT32 data);
- device_irq_acknowledge_callback save_irqcallback;
-
- f = sh2->ftcsr_read_callback;
- save_irqcallback = sh2->irq_callback;
-
- sh2->ppc = sh2->pc = sh2->pr = sh2->sr = sh2->gbr = sh2->vbr = sh2->mach = sh2->macl = 0;
- sh2->evec = sh2->irqsr = 0;
- memset(&sh2->r[0], 0, sizeof(sh2->r[0])*16);
- sh2->ea = sh2->delay = sh2->cpu_off = sh2->dvsr = sh2->dvdnth = sh2->dvdntl = sh2->dvcr = 0;
- sh2->pending_irq = sh2->test_irq = 0;
- memset(&sh2->irq_queue[0], 0, sizeof(sh2->irq_queue[0])*16);
- memset(&sh2->irq_line_state[0], 0, sizeof(sh2->irq_line_state[0])*17);
- sh2->frc = sh2->ocra = sh2->ocrb = sh2->icr = 0;
- sh2->frc_base = 0;
- sh2->frt_input = sh2->internal_irq_level = sh2->internal_irq_vector = 0;
- sh2->dma_timer_active[0] = sh2->dma_timer_active[1] = 0;
- sh2->dma_irq[0] = sh2->dma_irq[1] = 0;
-
- sh2->ftcsr_read_callback = f;
- sh2->irq_callback = save_irqcallback;
- sh2->device = device;
-
- memset(sh2->m, 0, 0x200);
-
- sh2->pc = sh2->program->read_dword(0);
- sh2->r[15] = sh2->program->read_dword(4);
- sh2->sr = I;
-
- sh2->internal_irq_level = -1;
-
- sh2->cache_dirty = TRUE;
-
- sh2->cpu_type = CPU_TYPE_SH2;
-}
-
-/*-------------------------------------------------
- sh1_reset - reset the processor
--------------------------------------------------*/
-
-static CPU_RESET( sh1 )
-{
- sh2_state *sh2 = get_safe_token(device);
- CPU_RESET_CALL(sh2);
- sh2->cpu_type = CPU_TYPE_SH1;
-}
-
-/*-------------------------------------------------
code_flush_cache - flush the cache and
regenerate static code
-------------------------------------------------*/
-static void code_flush_cache(sh2_state *sh2)
+void sh2_device::code_flush_cache()
{
- drcuml_state *drcuml = sh2->drcuml;
+ drcuml_state *drcuml = m_drcuml;
/* empty the transient cache contents */
drcuml->reset();
@@ -811,67 +593,66 @@ static void code_flush_cache(sh2_state *sh2)
try
{
/* generate the entry point and out-of-cycles handlers */
- static_generate_nocode_handler(sh2);
- static_generate_out_of_cycles(sh2);
- static_generate_entry_point(sh2);
+ static_generate_nocode_handler();
+ static_generate_out_of_cycles();
+ static_generate_entry_point();
/* add subroutines for memory accesses */
- static_generate_memory_accessor(sh2, 1, FALSE, "read8", &sh2->read8);
- static_generate_memory_accessor(sh2, 1, TRUE, "write8", &sh2->write8);
- static_generate_memory_accessor(sh2, 2, FALSE, "read16", &sh2->read16);
- static_generate_memory_accessor(sh2, 2, TRUE, "write16", &sh2->write16);
- static_generate_memory_accessor(sh2, 4, FALSE, "read32", &sh2->read32);
- static_generate_memory_accessor(sh2, 4, TRUE, "write32", &sh2->write32);
+ static_generate_memory_accessor(1, FALSE, "read8", &m_read8);
+ static_generate_memory_accessor(1, TRUE, "write8", &m_write8);
+ static_generate_memory_accessor(2, FALSE, "read16", &m_read16);
+ static_generate_memory_accessor(2, TRUE, "write16", &m_write16);
+ static_generate_memory_accessor(4, FALSE, "read32", &m_read32);
+ static_generate_memory_accessor(4, TRUE, "write32", &m_write32);
}
catch (drcuml_block::abort_compilation &)
{
fatalerror("Unable to generate SH2 static code\n");
}
- sh2->cache_dirty = FALSE;
+ m_cache_dirty = FALSE;
}
/* Execute cycles - returns number of cycles actually run */
-static CPU_EXECUTE( sh2 )
+void sh2_device::execute_run_drc()
{
- sh2_state *sh2 = get_safe_token(device);
- drcuml_state *drcuml = sh2->drcuml;
+ drcuml_state *drcuml = m_drcuml;
int execute_result;
// run any active DMAs now
#ifndef USE_TIMER_FOR_DMA
- for ( int i = 0; i < sh2->icount ; i++)
+ for ( int i = 0; i < m_sh2_state->icount ; i++)
{
for( int dma=0;dma<1;dma++)
{
- if (sh2->dma_timer_active[dma])
- sh2_do_dma(sh2, dma);
+ if (m_dma_timer_active[dma])
+ sh2_do_dma(dma);
}
}
#endif
/* reset the cache if dirty */
- if (sh2->cache_dirty)
- code_flush_cache(sh2);
+ if (m_cache_dirty)
+ code_flush_cache();
/* execute */
do
{
/* run as much as we can */
- execute_result = drcuml->execute(*sh2->entry);
+ execute_result = drcuml->execute(*m_entry);
/* if we need to recompile, do it */
if (execute_result == EXECUTE_MISSING_CODE)
{
- code_compile_block(sh2, 0, sh2->pc);
+ code_compile_block(0, m_sh2_state->pc);
}
else if (execute_result == EXECUTE_UNMAPPED_CODE)
{
- fatalerror("Attempted to execute unmapped code at PC=%08X\n", sh2->pc);
+ fatalerror("Attempted to execute unmapped code at PC=%08X\n", m_sh2_state->pc);
}
else if (execute_result == EXECUTE_RESET_CACHE)
{
- code_flush_cache(sh2);
+ code_flush_cache();
}
} while (execute_result != EXECUTE_OUT_OF_CYCLES);
}
@@ -881,9 +662,9 @@ static CPU_EXECUTE( sh2 )
given mode at the specified pc
-------------------------------------------------*/
-static void code_compile_block(sh2_state *sh2, UINT8 mode, offs_t pc)
+void sh2_device::code_compile_block(UINT8 mode, offs_t pc)
{
- drcuml_state *drcuml = sh2->drcuml;
+ drcuml_state *drcuml = m_drcuml;
compiler_state compiler = { 0 };
const opcode_desc *seqhead, *seqlast;
const opcode_desc *desclist;
@@ -893,7 +674,7 @@ static void code_compile_block(sh2_state *sh2, UINT8 mode, offs_t pc)
g_profiler.start(PROFILER_DRC_COMPILE);
/* get a description of this sequence */
- desclist = sh2->drcfe->describe_code(pc);
+ desclist = m_drcfe->describe_code(pc);
if (LOG_UML || LOG_NATIVE)
log_opcode_desc(drcuml, desclist, 0);
@@ -937,14 +718,14 @@ static void code_compile_block(sh2_state *sh2, UINT8 mode, offs_t pc)
else
{
UML_LABEL(block, seqhead->pc | 0x80000000); // label seqhead->pc | 0x80000000
- UML_HASHJMP(block, 0, seqhead->pc, *sh2->nocode);
+ UML_HASHJMP(block, 0, seqhead->pc, *m_nocode);
// hashjmp <mode>,seqhead->pc,nocode
continue;
}
/* validate this code block if we're not pointing into ROM */
- if (sh2->program->get_write_ptr(seqhead->physpc) != NULL)
- generate_checksum_block(sh2, block, &compiler, seqhead, seqlast);
+ if (m_program->get_write_ptr(seqhead->physpc) != NULL)
+ generate_checksum_block(block, &compiler, seqhead, seqlast);
/* label this instruction, if it may be jumped to locally */
if (seqhead->flags & OPFLAG_IS_BRANCH_TARGET)
@@ -955,7 +736,7 @@ static void code_compile_block(sh2_state *sh2, UINT8 mode, offs_t pc)
/* iterate over instructions in the sequence and compile them */
for (curdesc = seqhead; curdesc != seqlast->next(); curdesc = curdesc->next())
{
- generate_sequence_instruction(sh2, block, &compiler, curdesc, 0xffffffff);
+ generate_sequence_instruction(block, &compiler, curdesc, 0xffffffff);
}
/* if we need to return to the start, do it */
@@ -970,12 +751,12 @@ static void code_compile_block(sh2_state *sh2, UINT8 mode, offs_t pc)
}
/* count off cycles and go there */
- generate_update_cycles(sh2, block, &compiler, nextpc, TRUE); // <subtract cycles>
+ generate_update_cycles(block, &compiler, nextpc, TRUE); // <subtract cycles>
/* SH2 has no modes */
if (seqlast->next() == NULL || seqlast->next()->pc != nextpc)
{
- UML_HASHJMP(block, 0, nextpc, *sh2->nocode);
+ UML_HASHJMP(block, 0, nextpc, *m_nocode);
}
// hashjmp <mode>,nextpc,nocode
}
@@ -987,7 +768,7 @@ static void code_compile_block(sh2_state *sh2, UINT8 mode, offs_t pc)
}
catch (drcuml_block::abort_compilation &)
{
- code_flush_cache(sh2);
+ code_flush_cache();
}
}
}
@@ -997,9 +778,9 @@ static void code_compile_block(sh2_state *sh2, UINT8 mode, offs_t pc)
static entry point
-------------------------------------------------*/
-static void static_generate_entry_point(sh2_state *sh2)
+void sh2_device::static_generate_entry_point()
{
- drcuml_state *drcuml = sh2->drcuml;
+ drcuml_state *drcuml = m_drcuml;
code_label skip = 1;
drcuml_block *block;
@@ -1007,67 +788,67 @@ static void static_generate_entry_point(sh2_state *sh2)
block = drcuml->begin_block(200);
/* forward references */
- alloc_handle(drcuml, &sh2->nocode, "nocode");
- alloc_handle(drcuml, &sh2->write32, "write32"); // necessary?
- alloc_handle(drcuml, &sh2->entry, "entry");
- UML_HANDLE(block, *sh2->entry); // handle entry
+ alloc_handle(drcuml, &m_nocode, "nocode");
+ alloc_handle(drcuml, &m_write32, "write32"); // necessary?
+ alloc_handle(drcuml, &m_entry, "entry");
+ UML_HANDLE(block, *m_entry); // handle entry
/* load fast integer registers */
- load_fast_iregs(sh2, block);
+ load_fast_iregs(block);
/* check for interrupts */
- UML_MOV(block, mem(&sh2->irqline), 0xffffffff); // mov irqline, #-1
- UML_CMP(block, mem(&sh2->pending_nmi), 0); // cmp pending_nmi, #0
+ UML_MOV(block, mem(&m_sh2_state->irqline), 0xffffffff); // mov irqline, #-1
+ UML_CMP(block, mem(&m_sh2_state->pending_nmi), 0); // cmp pending_nmi, #0
UML_JMPc(block, COND_Z, skip+2); // jz skip+2
- UML_MOV(block, mem(&sh2->pending_nmi), 0); // zap pending_nmi
+ UML_MOV(block, mem(&m_sh2_state->pending_nmi), 0); // zap pending_nmi
UML_JMP(block, skip+1); // and then go take it (evec is already set)
UML_LABEL(block, skip+2); // skip+2:
- UML_MOV(block, mem(&sh2->evec), 0xffffffff); // mov evec, -1
+ UML_MOV(block, mem(&m_sh2_state->evec), 0xffffffff); // mov evec, -1
UML_MOV(block, I0, 0xffffffff); // mov r0, -1 (r0 = irq)
UML_AND(block, I1, I0, 0xffff); // and r1, 0xffff
- UML_LZCNT(block, I1, mem(&sh2->pending_irq)); // lzcnt r1, r1
+ UML_LZCNT(block, I1, mem(&m_sh2_state->pending_irq)); // lzcnt r1, r1
UML_CMP(block, I1, 32); // cmp r1, #32
UML_JMPc(block, COND_Z, skip+4); // jz skip+4
- UML_SUB(block, mem(&sh2->irqline), 31, I1); // sub irqline, #31, r1
+ UML_SUB(block, mem(&m_sh2_state->irqline), 31, I1); // sub irqline, #31, r1
UML_LABEL(block, skip+4); // skip+4:
- UML_CMP(block, mem(&sh2->internal_irq_level), 0xffffffff); // cmp internal_irq_level, #-1
+ UML_CMP(block, mem(&m_sh2_state->internal_irq_level), 0xffffffff); // cmp internal_irq_level, #-1
UML_JMPc(block, COND_Z, skip+3); // jz skip+3
- UML_CMP(block, mem(&sh2->internal_irq_level), mem(&sh2->irqline)); // cmp internal_irq_level, irqline
+ UML_CMP(block, mem(&m_sh2_state->internal_irq_level), mem(&m_sh2_state->irqline)); // cmp internal_irq_level, irqline
UML_JMPc(block, COND_LE, skip+3); // jle skip+3
- UML_MOV(block, mem(&sh2->irqline), mem(&sh2->internal_irq_level)); // mov r0, internal_irq_level
+ UML_MOV(block, mem(&m_sh2_state->irqline), mem(&m_sh2_state->internal_irq_level)); // mov r0, internal_irq_level
UML_LABEL(block, skip+3); // skip+3:
- UML_CMP(block, mem(&sh2->irqline), 0xffffffff); // cmp irqline, #-1
+ UML_CMP(block, mem(&m_sh2_state->irqline), 0xffffffff); // cmp irqline, #-1
UML_JMPc(block, COND_Z, skip+1); // jz skip+1
- UML_CALLC(block, cfunc_fastirq, sh2); // callc fastirq
+ UML_CALLC(block, cfunc_fastirq, this); // callc fastirq
UML_LABEL(block, skip+1); // skip+1:
- UML_CMP(block, mem(&sh2->evec), 0xffffffff); // cmp evec, 0xffffffff
+ UML_CMP(block, mem(&m_sh2_state->evec), 0xffffffff); // cmp evec, 0xffffffff
UML_JMPc(block, COND_Z, skip); // jz skip
UML_SUB(block, R32(15), R32(15), 4); // sub R15, R15, #4
UML_MOV(block, I0, R32(15)); // mov r0, R15
- UML_MOV(block, I1, mem(&sh2->irqsr)); // mov r1, irqsr
- UML_CALLH(block, *sh2->write32); // call write32
+ UML_MOV(block, I1, mem(&m_sh2_state->irqsr)); // mov r1, irqsr
+ UML_CALLH(block, *m_write32); // call write32
UML_SUB(block, R32(15), R32(15), 4); // sub R15, R15, #4
UML_MOV(block, I0, R32(15)); // mov r0, R15
- UML_MOV(block, I1, mem(&sh2->pc)); // mov r1, pc
- UML_CALLH(block, *sh2->write32); // call write32
+ UML_MOV(block, I1, mem(&m_sh2_state->pc)); // mov r1, pc
+ UML_CALLH(block, *m_write32); // call write32
- UML_MOV(block, mem(&sh2->pc), mem(&sh2->evec)); // mov pc, evec
+ UML_MOV(block, mem(&m_sh2_state->pc), mem(&m_sh2_state->evec)); // mov pc, evec
UML_LABEL(block, skip); // skip:
/* generate a hash jump via the current mode and PC */
- UML_HASHJMP(block, 0, mem(&sh2->pc), *sh2->nocode); // hashjmp <mode>,<pc>,nocode
+ UML_HASHJMP(block, 0, mem(&m_sh2_state->pc), *m_nocode); // hashjmp <mode>,<pc>,nocode
block->end();
}
@@ -1077,20 +858,20 @@ static void static_generate_entry_point(sh2_state *sh2)
exception handler for "out of code"
-------------------------------------------------*/
-static void static_generate_nocode_handler(sh2_state *sh2)
+void sh2_device::static_generate_nocode_handler()
{
- drcuml_state *drcuml = sh2->drcuml;
+ drcuml_state *drcuml = m_drcuml;
drcuml_block *block;
/* begin generating */
block = drcuml->begin_block(10);
/* generate a hash jump via the current mode and PC */
- alloc_handle(drcuml, &sh2->nocode, "nocode");
- UML_HANDLE(block, *sh2->nocode); // handle nocode
+ alloc_handle(drcuml, &m_nocode, "nocode");
+ UML_HANDLE(block, *m_nocode); // handle nocode
UML_GETEXP(block, I0); // getexp i0
- UML_MOV(block, mem(&sh2->pc), I0); // mov [pc],i0
- save_fast_iregs(sh2, block);
+ UML_MOV(block, mem(&m_sh2_state->pc), I0); // mov [pc],i0
+ save_fast_iregs(block);
UML_EXIT(block, EXECUTE_MISSING_CODE); // exit EXECUTE_MISSING_CODE
block->end();
@@ -1102,20 +883,20 @@ static void static_generate_nocode_handler(sh2_state *sh2)
out of cycles exception handler
-------------------------------------------------*/
-static void static_generate_out_of_cycles(sh2_state *sh2)
+void sh2_device::static_generate_out_of_cycles()
{
- drcuml_state *drcuml = sh2->drcuml;
+ drcuml_state *drcuml = m_drcuml;
drcuml_block *block;
/* begin generating */
block = drcuml->begin_block(10);
/* generate a hash jump via the current mode and PC */
- alloc_handle(drcuml, &sh2->out_of_cycles, "out_of_cycles");
- UML_HANDLE(block, *sh2->out_of_cycles); // handle out_of_cycles
+ alloc_handle(drcuml, &m_out_of_cycles, "out_of_cycles");
+ UML_HANDLE(block, *m_out_of_cycles); // handle out_of_cycles
UML_GETEXP(block, I0); // getexp i0
- UML_MOV(block, mem(&sh2->pc), I0); // mov <pc>,i0
- save_fast_iregs(sh2,block);
+ UML_MOV(block, mem(&m_sh2_state->pc), I0); // mov <pc>,i0
+ save_fast_iregs(block);
UML_EXIT(block, EXECUTE_OUT_OF_CYCLES); // exit EXECUTE_OUT_OF_CYCLES
block->end();
@@ -1125,12 +906,12 @@ static void static_generate_out_of_cycles(sh2_state *sh2)
static_generate_memory_accessor
------------------------------------------------------------------*/
-static void static_generate_memory_accessor(sh2_state *sh2, int size, int iswrite, const char *name, code_handle **handleptr)
+void sh2_device::static_generate_memory_accessor(int size, int iswrite, const char *name, code_handle **handleptr)
{
/* on entry, address is in I0; data for writes is in I1 */
/* on exit, read result is in I0 */
/* routine trashes I0 */
- drcuml_state *drcuml = sh2->drcuml;
+ drcuml_state *drcuml = m_drcuml;
drcuml_block *block;
int label = 1;
@@ -1156,18 +937,18 @@ static void static_generate_memory_accessor(sh2_state *sh2, int size, int iswrit
#if 0 // DO NOT ENABLE - SEVERE AARON DAMAGE
for (int ramnum = 0; ramnum < SH2_MAX_FASTRAM; ramnum++)
{
- if (sh2->fastram[ramnum].base != NULL && (!iswrite || !sh2->fastram[ramnum].readonly))
+ if (m_fastram[ramnum].base != NULL && (!iswrite || !m_fastram[ramnum].readonly))
{
- void *fastbase = (UINT8 *)sh2->fastram[ramnum].base - sh2->fastram[ramnum].start;
+ void *fastbase = (UINT8 *)m_fastram[ramnum].base - m_fastram[ramnum].start;
UINT32 skip = label++;
- if (sh2->fastram[ramnum].end != 0xffffffff)
+ if (m_fastram[ramnum].end != 0xffffffff)
{
- UML_CMP(block, I0, sh2->fastram[ramnum].end); // cmp i0,end
+ UML_CMP(block, I0, m_fastram[ramnum].end); // cmp i0,end
UML_JMPc(block, COND_A, skip); // ja skip
}
- if (sh2->fastram[ramnum].start != 0x00000000)
+ if (m_fastram[ramnum].start != 0x00000000)
{
- UML_CMP(block, I0, sh2->fastram[ramnum].start);// cmp i0,fastram_start
+ UML_CMP(block, I0, m_fastram[ramnum].start);// cmp i0,fastram_start
UML_JMPc(block, COND_B, skip); // jb skip
}
@@ -1259,7 +1040,7 @@ static void static_generate_memory_accessor(sh2_state *sh2, int size, int iswrit
flags
-------------------------------------------------*/
-static const char *log_desc_flags_to_string(UINT32 flags)
+const char *sh2_device::log_desc_flags_to_string(UINT32 flags)
{
static char tempbuf[30];
char *dest = tempbuf;
@@ -1313,7 +1094,7 @@ static const char *log_desc_flags_to_string(UINT32 flags)
log_register_list - log a list of GPR registers
-------------------------------------------------*/
-static void log_register_list(drcuml_state *drcuml, const char *string, const UINT32 *reglist, const UINT32 *regnostarlist)
+void sh2_device::log_register_list(drcuml_state *drcuml, const char *string, const UINT32 *reglist, const UINT32 *regnostarlist)
{
int count = 0;
int regnum;
@@ -1383,7 +1164,7 @@ static void log_register_list(drcuml_state *drcuml, const char *string, const UI
log_opcode_desc - log a list of descriptions
-------------------------------------------------*/
-static void log_opcode_desc(drcuml_state *drcuml, const opcode_desc *desclist, int indent)
+void sh2_device::log_opcode_desc(drcuml_state *drcuml, const opcode_desc *desclist, int indent)
{
/* open the file, creating it if necessary */
if (indent == 0)
@@ -1425,7 +1206,7 @@ static void log_opcode_desc(drcuml_state *drcuml, const opcode_desc *desclist, i
including disassembly of an SH2 instruction
-------------------------------------------------*/
-static void log_add_disasm_comment(drcuml_block *block, UINT32 pc, UINT32 op)
+void sh2_device::log_add_disasm_comment(drcuml_block *block, UINT32 pc, UINT32 op)
{
#if (LOG_UML)
char buffer[100];
@@ -1439,7 +1220,7 @@ static void log_add_disasm_comment(drcuml_block *block, UINT32 pc, UINT32 op)
subtract cycles from the icount and generate
an exception if out
-------------------------------------------------*/
-static void generate_update_cycles(sh2_state *sh2, drcuml_block *block, compiler_state *compiler, parameter param, int allow_exception)
+void sh2_device::generate_update_cycles(drcuml_block *block, compiler_state *compiler, parameter param, int allow_exception)
{
/* check full interrupts if pending */
if (compiler->checkints)
@@ -1450,52 +1231,52 @@ static void generate_update_cycles(sh2_state *sh2, drcuml_block *block, compiler
compiler->labelnum += 4;
/* check for interrupts */
- UML_MOV(block, mem(&sh2->irqline), 0xffffffff); // mov irqline, #-1
- UML_CMP(block, mem(&sh2->pending_nmi), 0); // cmp pending_nmi, #0
+ UML_MOV(block, mem(&m_sh2_state->irqline), 0xffffffff); // mov irqline, #-1
+ UML_CMP(block, mem(&m_sh2_state->pending_nmi), 0); // cmp pending_nmi, #0
UML_JMPc(block, COND_Z, skip+2); // jz skip+2
- UML_MOV(block, mem(&sh2->pending_nmi), 0); // zap pending_nmi
+ UML_MOV(block, mem(&m_sh2_state->pending_nmi), 0); // zap pending_nmi
UML_JMP(block, skip+1); // and then go take it (evec is already set)
UML_LABEL(block, skip+2); // skip+2:
- UML_MOV(block, mem(&sh2->evec), 0xffffffff); // mov evec, -1
+ UML_MOV(block, mem(&m_sh2_state->evec), 0xffffffff); // mov evec, -1
UML_MOV(block, I0, 0xffffffff); // mov r0, -1 (r0 = irq)
UML_AND(block, I1, I0, 0xffff); // and r1, r0, 0xffff
- UML_LZCNT(block, I1, mem(&sh2->pending_irq)); // lzcnt r1, pending_irq
+ UML_LZCNT(block, I1, mem(&m_sh2_state->pending_irq)); // lzcnt r1, pending_irq
UML_CMP(block, I1, 32); // cmp r1, #32
UML_JMPc(block, COND_Z, skip+4); // jz skip+4
- UML_SUB(block, mem(&sh2->irqline), 31, I1); // sub irqline, #31, r1
+ UML_SUB(block, mem(&m_sh2_state->irqline), 31, I1); // sub irqline, #31, r1
UML_LABEL(block, skip+4); // skip+4:
- UML_CMP(block, mem(&sh2->internal_irq_level), 0xffffffff); // cmp internal_irq_level, #-1
+ UML_CMP(block, mem(&m_sh2_state->internal_irq_level), 0xffffffff); // cmp internal_irq_level, #-1
UML_JMPc(block, COND_Z, skip+3); // jz skip+3
- UML_CMP(block, mem(&sh2->internal_irq_level), mem(&sh2->irqline)); // cmp internal_irq_level, irqline
+ UML_CMP(block, mem(&m_sh2_state->internal_irq_level), mem(&m_sh2_state->irqline)); // cmp internal_irq_level, irqline
UML_JMPc(block, COND_LE, skip+3); // jle skip+3
- UML_MOV(block, mem(&sh2->irqline), mem(&sh2->internal_irq_level)); // mov r0, internal_irq_level
+ UML_MOV(block, mem(&m_sh2_state->irqline), mem(&m_sh2_state->internal_irq_level)); // mov r0, internal_irq_level
UML_LABEL(block, skip+3); // skip+3:
- UML_CMP(block, mem(&sh2->irqline), 0xffffffff); // cmp irqline, #-1
+ UML_CMP(block, mem(&m_sh2_state->irqline), 0xffffffff); // cmp irqline, #-1
UML_JMPc(block, COND_Z, skip+1); // jz skip+1
- UML_CALLC(block, cfunc_fastirq, sh2); // callc fastirq
+ UML_CALLC(block, cfunc_fastirq, this); // callc fastirq
UML_LABEL(block, skip+1); // skip+1:
- UML_CMP(block, mem(&sh2->evec), 0xffffffff); // cmp evec, 0xffffffff
+ UML_CMP(block, mem(&m_sh2_state->evec), 0xffffffff); // cmp evec, 0xffffffff
UML_JMPc(block, COND_Z, skip); // jz skip
UML_SUB(block, R32(15), R32(15), 4); // sub R15, R15, #4
UML_MOV(block, I0, R32(15)); // mov r0, R15
- UML_MOV(block, I1, mem(&sh2->irqsr)); // mov r1, irqsr
- UML_CALLH(block, *sh2->write32); // call write32
+ UML_MOV(block, I1, mem(&m_sh2_state->irqsr)); // mov r1, irqsr
+ UML_CALLH(block, *m_write32); // call write32
UML_SUB(block, R32(15), R32(15), 4); // sub R15, R15, #4
UML_MOV(block, I0, R32(15)); // mov r0, R15
UML_MOV(block, I1, param); // mov r1, nextpc
- UML_CALLH(block, *sh2->write32); // call write32
+ UML_CALLH(block, *m_write32); // call write32
- UML_HASHJMP(block, 0, mem(&sh2->evec), *sh2->nocode); // hashjmp sh2->evec
+ UML_HASHJMP(block, 0, mem(&m_sh2_state->evec), *m_nocode); // hashjmp m_sh2_state->evec
UML_LABEL(block, skip); // skip:
}
@@ -1503,10 +1284,10 @@ static void generate_update_cycles(sh2_state *sh2, drcuml_block *block, compiler
/* account for cycles */
if (compiler->cycles > 0)
{
- UML_SUB(block, mem(&sh2->icount), mem(&sh2->icount), MAPVAR_CYCLES); // sub icount,icount,cycles
+ UML_SUB(block, mem(&m_sh2_state->icount), mem(&m_sh2_state->icount), MAPVAR_CYCLES); // sub icount,icount,cycles
UML_MAPVAR(block, MAPVAR_CYCLES, 0); // mapvar cycles,0
if (allow_exception)
- UML_EXHc(block, COND_S, *sh2->out_of_cycles, param);
+ UML_EXHc(block, COND_S, *m_out_of_cycles, param);
// exh out_of_cycles,nextpc
}
compiler->cycles = 0;
@@ -1517,21 +1298,21 @@ static void generate_update_cycles(sh2_state *sh2, drcuml_block *block, compiler
validate a sequence of opcodes
-------------------------------------------------*/
-static void generate_checksum_block(sh2_state *sh2, drcuml_block *block, compiler_state *compiler, const opcode_desc *seqhead, const opcode_desc *seqlast)
+void sh2_device::generate_checksum_block(drcuml_block *block, compiler_state *compiler, const opcode_desc *seqhead, const opcode_desc *seqlast)
{
const opcode_desc *curdesc;
if (LOG_UML)
block->append_comment("[Validation for %08X]", seqhead->pc); // comment
/* loose verify or single instruction: just compare and fail */
- if (!(sh2->drcoptions & SH2DRC_STRICT_VERIFY) || seqhead->next() == NULL)
+ if (!(m_drcoptions & SH2DRC_STRICT_VERIFY) || seqhead->next() == NULL)
{
if (!(seqhead->flags & OPFLAG_VIRTUAL_NOOP))
{
- void *base = sh2->direct->read_decrypted_ptr(seqhead->physpc, SH2_CODE_XOR(0));
+ void *base = m_direct->read_decrypted_ptr(seqhead->physpc, SH2_CODE_XOR(0));
UML_LOAD(block, I0, base, 0, SIZE_WORD, SCALE_x2); // load i0,base,word
UML_CMP(block, I0, seqhead->opptr.w[0]); // cmp i0,*opptr
- UML_EXHc(block, COND_NE, *sh2->nocode, epc(seqhead)); // exne nocode,seqhead->pc
+ UML_EXHc(block, COND_NE, *m_nocode, epc(seqhead)); // exne nocode,seqhead->pc
}
}
@@ -1542,26 +1323,26 @@ static void generate_checksum_block(sh2_state *sh2, drcuml_block *block, compile
for (curdesc = seqhead->next(); curdesc != seqlast->next(); curdesc = curdesc->next())
if (!(curdesc->flags & OPFLAG_VIRTUAL_NOOP))
{
- base = sh2->direct->read_decrypted_ptr(curdesc->physpc, SH2_CODE_XOR(0));
+ base = m_direct->read_decrypted_ptr(curdesc->physpc, SH2_CODE_XOR(0));
UML_LOAD(block, I0, curdesc->opptr.w, 0, SIZE_WORD, SCALE_x2); // load i0,*opptr,0,word
UML_CMP(block, I0, curdesc->opptr.w[0]); // cmp i0,*opptr
- UML_EXHc(block, COND_NE, *sh2->nocode, epc(seqhead)); // exne nocode,seqhead->pc
+ UML_EXHc(block, COND_NE, *m_nocode, epc(seqhead)); // exne nocode,seqhead->pc
}
#else
UINT32 sum = 0;
- void *base = sh2->direct->read_decrypted_ptr(seqhead->physpc, SH2_CODE_XOR(0));
+ void *base = m_direct->read_decrypted_ptr(seqhead->physpc, SH2_CODE_XOR(0));
UML_LOAD(block, I0, base, 0, SIZE_WORD, SCALE_x4); // load i0,base,word
sum += seqhead->opptr.w[0];
for (curdesc = seqhead->next(); curdesc != seqlast->next(); curdesc = curdesc->next())
if (!(curdesc->flags & OPFLAG_VIRTUAL_NOOP))
{
- base = sh2->direct->read_decrypted_ptr(curdesc->physpc, SH2_CODE_XOR(0));
+ base = m_direct->read_decrypted_ptr(curdesc->physpc, SH2_CODE_XOR(0));
UML_LOAD(block, I1, base, 0, SIZE_WORD, SCALE_x2); // load i1,*opptr,word
UML_ADD(block, I0, I0, I1); // add i0,i0,i1
sum += curdesc->opptr.w[0];
}
UML_CMP(block, I0, sum); // cmp i0,sum
- UML_EXHc(block, COND_NE, *sh2->nocode, epc(seqhead)); // exne nocode,seqhead->pc
+ UML_EXHc(block, COND_NE, *m_nocode, epc(seqhead)); // exne nocode,seqhead->pc
#endif
}
}
@@ -1572,7 +1353,7 @@ static void generate_checksum_block(sh2_state *sh2, drcuml_block *block, compile
for a single instruction in a sequence
-------------------------------------------------*/
-static void generate_sequence_instruction(sh2_state *sh2, drcuml_block *block, compiler_state *compiler, const opcode_desc *desc, UINT32 ovrpc)
+void sh2_device::generate_sequence_instruction(drcuml_block *block, compiler_state *compiler, const opcode_desc *desc, UINT32 ovrpc)
{
offs_t expc;
@@ -1593,32 +1374,32 @@ static void generate_sequence_instruction(sh2_state *sh2, drcuml_block *block, c
/* if we want a probe, add it here */
if (desc->pc == PROBE_ADDRESS)
{
- UML_MOV(block, mem(&sh2->pc), desc->pc); // mov [pc],desc->pc
- UML_CALLC(block, cfunc_printf_probe, sh2); // callc cfunc_printf_probe,sh2
+ UML_MOV(block, mem(&m_sh2_state->pc), desc->pc); // mov [pc],desc->pc
+ UML_CALLC(block, cfunc_printf_probe, this); // callc cfunc_printf_probe,sh2
}
/* if we are debugging, call the debugger */
- if ((sh2->device->machine().debug_flags & DEBUG_FLAG_ENABLED) != 0)
+ if ((machine().debug_flags & DEBUG_FLAG_ENABLED) != 0)
{
- UML_MOV(block, mem(&sh2->pc), desc->pc); // mov [pc],desc->pc
- save_fast_iregs(sh2, block);
+ UML_MOV(block, mem(&m_sh2_state->pc), desc->pc); // mov [pc],desc->pc
+ save_fast_iregs(block);
UML_DEBUG(block, desc->pc); // debug desc->pc
}
else // not debug, see what other reasons there are for flushing the PC
{
- if (sh2->drcoptions & SH2DRC_FLUSH_PC) // always flush?
+ if (m_drcoptions & SH2DRC_FLUSH_PC) // always flush?
{
- UML_MOV(block, mem(&sh2->pc), desc->pc); // mov sh2->pc, desc->pc
+ UML_MOV(block, mem(&m_sh2_state->pc), desc->pc); // mov m_sh2_state->pc, desc->pc
}
else // check for driver-selected flushes
{
int pcflush;
- for (pcflush = 0; pcflush < sh2->pcfsel; pcflush++)
+ for (pcflush = 0; pcflush < m_pcfsel; pcflush++)
{
- if (desc->pc == sh2->pcflushes[pcflush])
+ if (desc->pc == m_pcflushes[pcflush])
{
- UML_MOV(block, mem(&sh2->pc), desc->pc); // mov sh2->pc, desc->pc
+ UML_MOV(block, mem(&m_sh2_state->pc), desc->pc); // mov m_sh2_state->pc, desc->pc
}
}
}
@@ -1628,8 +1409,8 @@ static void generate_sequence_instruction(sh2_state *sh2, drcuml_block *block, c
/* if we hit an unmapped address, fatal error */
if (desc->flags & OPFLAG_COMPILER_UNMAPPED)
{
- UML_MOV(block, mem(&sh2->pc), desc->pc); // mov [pc],desc->pc
- save_fast_iregs(sh2, block);
+ UML_MOV(block, mem(&m_sh2_state->pc), desc->pc); // mov [pc],desc->pc
+ save_fast_iregs(block);
UML_EXIT(block, EXECUTE_UNMAPPED_CODE); // exit EXECUTE_UNMAPPED_CODE
}
@@ -1643,12 +1424,12 @@ static void generate_sequence_instruction(sh2_state *sh2, drcuml_block *block, c
else if (!(desc->flags & OPFLAG_VIRTUAL_NOOP))
{
/* compile the instruction */
- if (!generate_opcode(sh2, block, compiler, desc, ovrpc))
+ if (!generate_opcode(block, compiler, desc, ovrpc))
{
// handle an illegal op
- UML_MOV(block, mem(&sh2->pc), desc->pc); // mov [pc],desc->pc
- UML_MOV(block, mem(&sh2->arg0), desc->opptr.w[0]); // mov [arg0],opcode
- UML_CALLC(block, cfunc_unimplemented, sh2); // callc cfunc_unimplemented
+ UML_MOV(block, mem(&m_sh2_state->pc), desc->pc); // mov [pc],desc->pc
+ UML_MOV(block, mem(&m_sh2_state->arg0), desc->opptr.w[0]); // mov [arg0],opcode
+ UML_CALLC(block, cfunc_unimplemented, this); // callc cfunc_unimplemented
}
}
}
@@ -1657,13 +1438,13 @@ static void generate_sequence_instruction(sh2_state *sh2, drcuml_block *block, c
generate_delay_slot
------------------------------------------------------------------*/
-static void generate_delay_slot(sh2_state *sh2, drcuml_block *block, compiler_state *compiler, const opcode_desc *desc, UINT32 ovrpc)
+void sh2_device::generate_delay_slot(drcuml_block *block, compiler_state *compiler, const opcode_desc *desc, UINT32 ovrpc)
{
compiler_state compiler_temp = *compiler;
/* compile the delay slot using temporary compiler state */
assert(desc->delay.first() != NULL);
- generate_sequence_instruction(sh2, block, &compiler_temp, desc->delay.first(), ovrpc); // <next instruction>
+ generate_sequence_instruction(block, &compiler_temp, desc->delay.first(), ovrpc); // <next instruction>
/* update the label */
compiler->labelnum = compiler_temp.labelnum;
@@ -1674,7 +1455,7 @@ static void generate_delay_slot(sh2_state *sh2, drcuml_block *block, compiler_st
opcode
-------------------------------------------------*/
-static int generate_opcode(sh2_state *sh2, drcuml_block *block, compiler_state *compiler, const opcode_desc *desc, UINT32 ovrpc)
+int sh2_device::generate_opcode(drcuml_block *block, compiler_state *compiler, const opcode_desc *desc, UINT32 ovrpc)
{
UINT32 scratch, scratch2;
INT32 disp;
@@ -1685,39 +1466,39 @@ static int generate_opcode(sh2_state *sh2, drcuml_block *block, compiler_state *
switch (opswitch)
{
case 0:
- return generate_group_0(sh2, block, compiler, desc, opcode, in_delay_slot, ovrpc);
+ return generate_group_0(block, compiler, desc, opcode, in_delay_slot, ovrpc);
case 1: // MOVLS4
scratch = (opcode & 0x0f) * 4;
UML_ADD(block, I0, R32(Rn), scratch); // add r0, Rn, scratch
UML_MOV(block, I1, R32(Rm)); // mov r1, Rm
SETEA(0); // set ea for debug
- UML_CALLH(block, *sh2->write32);
+ UML_CALLH(block, *m_write32);
if (!in_delay_slot)
- generate_update_cycles(sh2, block, compiler, desc->pc + 2, TRUE);
+ generate_update_cycles(block, compiler, desc->pc + 2, TRUE);
return TRUE;
case 2:
- return generate_group_2(sh2, block, compiler, desc, opcode, in_delay_slot, ovrpc);
+ return generate_group_2(block, compiler, desc, opcode, in_delay_slot, ovrpc);
case 3:
- return generate_group_3(sh2, block, compiler, desc, opcode, ovrpc);
+ return generate_group_3(block, compiler, desc, opcode, ovrpc);
case 4:
- return generate_group_4(sh2, block, compiler, desc, opcode, in_delay_slot, ovrpc);
+ return generate_group_4(block, compiler, desc, opcode, in_delay_slot, ovrpc);
case 5: // MOVLL4
scratch = (opcode & 0x0f) * 4;
UML_ADD(block, I0, R32(Rm), scratch); // add r0, Rm, scratch
SETEA(0); // set ea for debug
- UML_CALLH(block, *sh2->read32); // call read32
+ UML_CALLH(block, *m_read32); // call read32
UML_MOV(block, R32(Rn), I0); // mov Rn, r0
if (!in_delay_slot)
- generate_update_cycles(sh2, block, compiler, desc->pc + 2, TRUE);
+ generate_update_cycles(block, compiler, desc->pc + 2, TRUE);
return TRUE;
case 6:
- return generate_group_6(sh2, block, compiler, desc, opcode, in_delay_slot, ovrpc);
+ return generate_group_6(block, compiler, desc, opcode, in_delay_slot, ovrpc);
case 7: // ADDI
scratch = opcode & 0xff;
@@ -1726,7 +1507,7 @@ static int generate_opcode(sh2_state *sh2, drcuml_block *block, compiler_state *
return TRUE;
case 8:
- return generate_group_8(sh2, block, compiler, desc, opcode, in_delay_slot, ovrpc);
+ return generate_group_8(block, compiler, desc, opcode, in_delay_slot, ovrpc);
case 9: // MOVWI
if (ovrpc == 0xffffffff)
@@ -1738,49 +1519,49 @@ static int generate_opcode(sh2_state *sh2, drcuml_block *block, compiler_state *
scratch = (ovrpc + 2) + ((opcode & 0xff) * 2) + 2;
}
- if (sh2->drcoptions & SH2DRC_STRICT_PCREL)
+ if (m_drcoptions & SH2DRC_STRICT_PCREL)
{
UML_MOV(block, I0, scratch); // mov r0, scratch
SETEA(0); // set ea for debug
- UML_CALLH(block, *sh2->read16); // read16(r0, r1)
+ UML_CALLH(block, *m_read16); // read16(r0, r1)
UML_SEXT(block, R32(Rn), I0, SIZE_WORD); // sext Rn, r0, WORD
}
else
{
- scratch2 = (UINT32)(INT32)(INT16) RW(sh2, scratch);
+ scratch2 = (UINT32)(INT32)(INT16) RW(scratch);
UML_MOV(block, R32(Rn), scratch2); // mov Rn, scratch2
}
if (!in_delay_slot)
- generate_update_cycles(sh2, block, compiler, desc->pc + 2, TRUE);
+ generate_update_cycles(block, compiler, desc->pc + 2, TRUE);
return TRUE;
case 10: // BRA
disp = ((INT32)opcode << 20) >> 20;
- sh2->ea = (desc->pc + 2) + disp * 2 + 2; // sh2->ea = pc+4 + disp*2 + 2
+ m_sh2_state->ea = (desc->pc + 2) + disp * 2 + 2; // m_sh2_state->ea = pc+4 + disp*2 + 2
- generate_delay_slot(sh2, block, compiler, desc, sh2->ea-2);
+ generate_delay_slot(block, compiler, desc, m_sh2_state->ea-2);
- generate_update_cycles(sh2, block, compiler, sh2->ea, TRUE); // <subtract cycles>
- UML_HASHJMP(block, 0, sh2->ea, *sh2->nocode); // hashjmp sh2->ea
+ generate_update_cycles(block, compiler, m_sh2_state->ea, TRUE); // <subtract cycles>
+ UML_HASHJMP(block, 0, m_sh2_state->ea, *m_nocode); // hashjmp m_sh2_state->ea
return TRUE;
case 11: // BSR
// panicstr @ 403da22 relies on the delay slot clobbering the PR set by a BSR, so
// do this before running the delay slot
- UML_ADD(block, mem(&sh2->pr), desc->pc, 4); // add sh2->pr, desc->pc, #4 (skip the current insn & delay slot)
+ UML_ADD(block, mem(&m_sh2_state->pr), desc->pc, 4); // add m_pr, desc->pc, #4 (skip the current insn & delay slot)
disp = ((INT32)opcode << 20) >> 20;
- sh2->ea = (desc->pc + 2) + disp * 2 + 2; // sh2->ea = pc+4 + disp*2 + 2
+ m_sh2_state->ea = (desc->pc + 2) + disp * 2 + 2; // m_sh2_state->ea = pc+4 + disp*2 + 2
- generate_delay_slot(sh2, block, compiler, desc, sh2->ea-2);
+ generate_delay_slot(block, compiler, desc, m_sh2_state->ea-2);
- generate_update_cycles(sh2, block, compiler, sh2->ea, TRUE); // <subtract cycles>
- UML_HASHJMP(block, 0, sh2->ea, *sh2->nocode); // hashjmp sh2->ea
+ generate_update_cycles(block, compiler, m_sh2_state->ea, TRUE); // <subtract cycles>
+ UML_HASHJMP(block, 0, m_sh2_state->ea, *m_nocode); // hashjmp m_sh2_state->ea
return TRUE;
case 12:
- return generate_group_12(sh2, block, compiler, desc, opcode, in_delay_slot, ovrpc);
+ return generate_group_12(block, compiler, desc, opcode, in_delay_slot, ovrpc);
case 13: // MOVLI
if (ovrpc == 0xffffffff)
@@ -1792,20 +1573,20 @@ static int generate_opcode(sh2_state *sh2, drcuml_block *block, compiler_state *
scratch = ((ovrpc + 4) & ~3) + ((opcode & 0xff) * 4);
}
- if (sh2->drcoptions & SH2DRC_STRICT_PCREL)
+ if (m_drcoptions & SH2DRC_STRICT_PCREL)
{
UML_MOV(block, I0, scratch); // mov r0, scratch
- UML_CALLH(block, *sh2->read32); // read32(r0, r1)
+ UML_CALLH(block, *m_read32); // read32(r0, r1)
UML_MOV(block, R32(Rn), I0); // mov Rn, r0
}
else
{
- scratch2 = RL(sh2, scratch);
+ scratch2 = RL(scratch);
UML_MOV(block, R32(Rn), scratch2); // mov Rn, scratch2
}
if (!in_delay_slot)
- generate_update_cycles(sh2, block, compiler, desc->pc + 2, TRUE);
+ generate_update_cycles(block, compiler, desc->pc + 2, TRUE);
return TRUE;
case 14: // MOVI
@@ -1821,7 +1602,7 @@ static int generate_opcode(sh2_state *sh2, drcuml_block *block, compiler_state *
return FALSE;
}
-static int generate_group_0(sh2_state *sh2, drcuml_block *block, compiler_state *compiler, const opcode_desc *desc, UINT16 opcode, int in_delay_slot, UINT32 ovrpc)
+int sh2_device::generate_group_0(drcuml_block *block, compiler_state *compiler, const opcode_desc *desc, UINT16 opcode, int in_delay_slot, UINT32 ovrpc)
{
switch (opcode & 0x3F)
{
@@ -1846,23 +1627,23 @@ static int generate_group_0(sh2_state *sh2, drcuml_block *block, compiler_state
return TRUE;
case 0x02: // STCSR(Rn);
- UML_MOV(block, R32(Rn), mem(&sh2->sr));
+ UML_MOV(block, R32(Rn), mem(&m_sh2_state->sr));
return TRUE;
case 0x03: // BSRF(Rn);
- if (sh2->cpu_type > CPU_TYPE_SH1)
+ if (m_cpu_type > CPU_TYPE_SH1)
{
- UML_ADD(block, mem(&sh2->target), R32(Rn), 4); // add target, Rm, #4
- UML_ADD(block, mem(&sh2->target), mem(&sh2->target), desc->pc); // add target, target, pc
+ UML_ADD(block, mem(&m_sh2_state->target), R32(Rn), 4); // add target, Rm, #4
+ UML_ADD(block, mem(&m_sh2_state->target), mem(&m_sh2_state->target), desc->pc); // add target, target, pc
// 32x Cosmic Carnage @ 6002cb0 relies on the delay slot
// clobbering the calculated PR, so do it first
- UML_ADD(block, mem(&sh2->pr), desc->pc, 4); // add sh2->pr, desc->pc, #4 (skip the current insn & delay slot)
+ UML_ADD(block, mem(&m_sh2_state->pr), desc->pc, 4); // add m_pr, desc->pc, #4 (skip the current insn & delay slot)
- generate_delay_slot(sh2, block, compiler, desc, sh2->target);
+ generate_delay_slot(block, compiler, desc, m_sh2_state->target);
- generate_update_cycles(sh2, block, compiler, mem(&sh2->target), TRUE); // <subtract cycles>
- UML_HASHJMP(block, 0, mem(&sh2->target), *sh2->nocode); // jmp target
+ generate_update_cycles(block, compiler, mem(&m_sh2_state->target), TRUE); // <subtract cycles>
+ UML_HASHJMP(block, 0, mem(&m_sh2_state->target), *m_nocode); // jmp target
return TRUE;
}
break;
@@ -1873,10 +1654,10 @@ static int generate_group_0(sh2_state *sh2, drcuml_block *block, compiler_state
case 0x34: // MOVBS0(Rm, Rn);
UML_ADD(block, I0, R32(0), R32(Rn)); // add r0, R0, Rn
UML_AND(block, I1, R32(Rm), 0x000000ff); // and r1, Rm, 0xff
- UML_CALLH(block, *sh2->write8); // call write8
+ UML_CALLH(block, *m_write8); // call write8
if (!in_delay_slot)
- generate_update_cycles(sh2, block, compiler, desc->pc + 2, TRUE);
+ generate_update_cycles(block, compiler, desc->pc + 2, TRUE);
return TRUE;
case 0x05: // MOVWS0(Rm, Rn);
@@ -1885,10 +1666,10 @@ static int generate_group_0(sh2_state *sh2, drcuml_block *block, compiler_state
case 0x35: // MOVWS0(Rm, Rn);
UML_ADD(block, I0, R32(0), R32(Rn)); // add r0, R0, Rn
UML_AND(block, I1, R32(Rm), 0x0000ffff); // and r1, Rm, 0xffff
- UML_CALLH(block, *sh2->write16); // call write16
+ UML_CALLH(block, *m_write16); // call write16
if (!in_delay_slot)
- generate_update_cycles(sh2, block, compiler, desc->pc + 2, TRUE);
+ generate_update_cycles(block, compiler, desc->pc + 2, TRUE);
return TRUE;
case 0x06: // MOVLS0(Rm, Rn);
@@ -1897,38 +1678,38 @@ static int generate_group_0(sh2_state *sh2, drcuml_block *block, compiler_state
case 0x36: // MOVLS0(Rm, Rn);
UML_ADD(block, I0, R32(0), R32(Rn)); // add r0, R0, Rn
UML_MOV(block, I1, R32(Rm)); // mov r1, Rm
- UML_CALLH(block, *sh2->write32); // call write32
+ UML_CALLH(block, *m_write32); // call write32
if (!in_delay_slot)
- generate_update_cycles(sh2, block, compiler, desc->pc + 2, TRUE);
+ generate_update_cycles(block, compiler, desc->pc + 2, TRUE);
return TRUE;
case 0x07: // MULL(Rm, Rn);
case 0x17: // MULL(Rm, Rn);
case 0x27: // MULL(Rm, Rn);
case 0x37: // MULL(Rm, Rn);
- if (sh2->cpu_type > CPU_TYPE_SH1)
+ if (m_cpu_type > CPU_TYPE_SH1)
{
- UML_MULU(block, mem(&sh2->macl), mem(&sh2->ea), R32(Rn), R32(Rm)); // mulu macl, ea, Rn, Rm
+ UML_MULU(block, mem(&m_sh2_state->macl), mem(&m_sh2_state->ea), R32(Rn), R32(Rm)); // mulu macl, ea, Rn, Rm
return TRUE;
}
break;
case 0x08: // CLRT();
- UML_AND(block, mem(&sh2->sr), mem(&sh2->sr), ~T); // and r0, sr, ~T (clear the T bit)
+ UML_AND(block, mem(&m_sh2_state->sr), mem(&m_sh2_state->sr), ~T); // and r0, sr, ~T (clear the T bit)
return TRUE;
case 0x0a: // STSMACH(Rn);
- UML_MOV(block, R32(Rn), mem(&sh2->mach)); // mov Rn, mach
+ UML_MOV(block, R32(Rn), mem(&m_sh2_state->mach)); // mov Rn, mach
return TRUE;
case 0x0b: // RTS();
- UML_MOV(block, mem(&sh2->target), mem(&sh2->pr)); // mov target, pr (in case of d-slot shenanigans)
+ UML_MOV(block, mem(&m_sh2_state->target), mem(&m_sh2_state->pr)); // mov target, pr (in case of d-slot shenanigans)
- generate_delay_slot(sh2, block, compiler, desc, sh2->target);
+ generate_delay_slot(block, compiler, desc, m_sh2_state->target);
- generate_update_cycles(sh2, block, compiler, mem(&sh2->target), TRUE); // <subtract cycles>
- UML_HASHJMP(block, 0, mem(&sh2->target), *sh2->nocode);
+ generate_update_cycles(block, compiler, mem(&m_sh2_state->target), TRUE); // <subtract cycles>
+ UML_HASHJMP(block, 0, mem(&m_sh2_state->target), *m_nocode);
return TRUE;
case 0x0c: // MOVBL0(Rm, Rn);
@@ -1936,11 +1717,11 @@ static int generate_group_0(sh2_state *sh2, drcuml_block *block, compiler_state
case 0x2c: // MOVBL0(Rm, Rn);
case 0x3c: // MOVBL0(Rm, Rn);
UML_ADD(block, I0, R32(0), R32(Rm)); // add r0, R0, Rm
- UML_CALLH(block, *sh2->read8); // call read8
+ UML_CALLH(block, *m_read8); // call read8
UML_SEXT(block, R32(Rn), I0, SIZE_BYTE); // sext Rn, r0, BYTE
if (!in_delay_slot)
- generate_update_cycles(sh2, block, compiler, desc->pc + 2, TRUE);
+ generate_update_cycles(block, compiler, desc->pc + 2, TRUE);
return TRUE;
case 0x0d: // MOVWL0(Rm, Rn);
@@ -1948,11 +1729,11 @@ static int generate_group_0(sh2_state *sh2, drcuml_block *block, compiler_state
case 0x2d: // MOVWL0(Rm, Rn);
case 0x3d: // MOVWL0(Rm, Rn);
UML_ADD(block, I0, R32(0), R32(Rm)); // add r0, R0, Rm
- UML_CALLH(block, *sh2->read16); // call read16
+ UML_CALLH(block, *m_read16); // call read16
UML_SEXT(block, R32(Rn), I0, SIZE_WORD); // sext Rn, r0, WORD
if (!in_delay_slot)
- generate_update_cycles(sh2, block, compiler, desc->pc + 2, TRUE);
+ generate_update_cycles(block, compiler, desc->pc + 2, TRUE);
return TRUE;
case 0x0e: // MOVLL0(Rm, Rn);
@@ -1960,107 +1741,107 @@ static int generate_group_0(sh2_state *sh2, drcuml_block *block, compiler_state
case 0x2e: // MOVLL0(Rm, Rn);
case 0x3e: // MOVLL0(Rm, Rn);
UML_ADD(block, I0, R32(0), R32(Rm)); // add r0, R0, Rm
- UML_CALLH(block, *sh2->read32); // call read32
+ UML_CALLH(block, *m_read32); // call read32
UML_MOV(block, R32(Rn), I0); // mov Rn, r0
if (!in_delay_slot)
- generate_update_cycles(sh2, block, compiler, desc->pc + 2, TRUE);
+ generate_update_cycles(block, compiler, desc->pc + 2, TRUE);
return TRUE;
case 0x0f: // MAC_L(Rm, Rn);
case 0x1f: // MAC_L(Rm, Rn);
case 0x2f: // MAC_L(Rm, Rn);
case 0x3f: // MAC_L(Rm, Rn);
- if (sh2->cpu_type > CPU_TYPE_SH1)
+ if (m_cpu_type > CPU_TYPE_SH1)
{
- save_fast_iregs(sh2, block);
- UML_MOV(block, mem(&sh2->arg0), desc->opptr.w[0]);
- UML_CALLC(block, cfunc_MAC_L, sh2);
- load_fast_iregs(sh2, block);
+ save_fast_iregs(block);
+ UML_MOV(block, mem(&m_sh2_state->arg0), desc->opptr.w[0]);
+ UML_CALLC(block, cfunc_MAC_L, this);
+ load_fast_iregs(block);
return TRUE;
}
break;
case 0x12: // STCGBR(Rn);
- UML_MOV(block, R32(Rn), mem(&sh2->gbr)); // mov Rn, gbr
+ UML_MOV(block, R32(Rn), mem(&m_sh2_state->gbr)); // mov Rn, gbr
return TRUE;
case 0x18: // SETT();
- UML_OR(block, mem(&sh2->sr), mem(&sh2->sr), T); // or sr, sr, T
+ UML_OR(block, mem(&m_sh2_state->sr), mem(&m_sh2_state->sr), T); // or sr, sr, T
return TRUE;
case 0x19: // DIV0U();
- UML_AND(block, mem(&sh2->sr), mem(&sh2->sr), ~(M|Q|T)); // and sr, sr, ~(M|Q|T)
+ UML_AND(block, mem(&m_sh2_state->sr), mem(&m_sh2_state->sr), ~(M|Q|T)); // and sr, sr, ~(M|Q|T)
return TRUE;
case 0x1a: // STSMACL(Rn);
- UML_MOV(block, R32(Rn), mem(&sh2->macl)); // mov Rn, macl
+ UML_MOV(block, R32(Rn), mem(&m_sh2_state->macl)); // mov Rn, macl
return TRUE;
case 0x1b: // SLEEP();
- UML_MOV(block, I0, mem(&sh2->sleep_mode)); // mov i0, sleep_mode
+ UML_MOV(block, I0, mem(&m_sh2_state->sleep_mode)); // mov i0, sleep_mode
UML_CMP(block, I0, 0x2); // cmp i0, #2
UML_JMPc(block, COND_E, compiler->labelnum); // beq labelnum
// sleep mode != 2
- UML_MOV(block, mem(&sh2->sleep_mode), 0x1); // mov sleep_mode, #1
- generate_update_cycles(sh2, block, compiler, desc->pc, TRUE); // repeat this insn
+ UML_MOV(block, mem(&m_sh2_state->sleep_mode), 0x1); // mov sleep_mode, #1
+ generate_update_cycles(block, compiler, desc->pc, TRUE); // repeat this insn
UML_JMP(block, compiler->labelnum+1); // jmp labelnum+1
UML_LABEL(block, compiler->labelnum++); // labelnum:
// sleep_mode == 2
- UML_MOV(block, mem(&sh2->sleep_mode), 0x0); // sleep_mode = 0
- generate_update_cycles(sh2, block, compiler, desc->pc+2, TRUE); // go to next insn
+ UML_MOV(block, mem(&m_sh2_state->sleep_mode), 0x0); // sleep_mode = 0
+ generate_update_cycles(block, compiler, desc->pc+2, TRUE); // go to next insn
UML_LABEL(block, compiler->labelnum++); // labelnum+1:
return TRUE;
case 0x22: // STCVBR(Rn);
- UML_MOV(block, R32(Rn), mem(&sh2->vbr)); // mov Rn, vbr
+ UML_MOV(block, R32(Rn), mem(&m_sh2_state->vbr)); // mov Rn, vbr
return TRUE;
case 0x23: // BRAF(Rn);
- if (sh2->cpu_type > CPU_TYPE_SH1)
+ if (m_cpu_type > CPU_TYPE_SH1)
{
- UML_ADD(block, mem(&sh2->target), R32(Rn), desc->pc+4); // add target, Rn, pc+4
+ UML_ADD(block, mem(&m_sh2_state->target), R32(Rn), desc->pc+4); // add target, Rn, pc+4
- generate_delay_slot(sh2, block, compiler, desc, sh2->target);
+ generate_delay_slot(block, compiler, desc, m_sh2_state->target);
- generate_update_cycles(sh2, block, compiler, mem(&sh2->target), TRUE); // <subtract cycles>
- UML_HASHJMP(block, 0, mem(&sh2->target), *sh2->nocode); // jmp target
+ generate_update_cycles(block, compiler, mem(&m_sh2_state->target), TRUE); // <subtract cycles>
+ UML_HASHJMP(block, 0, mem(&m_sh2_state->target), *m_nocode); // jmp target
return TRUE;
}
break;
case 0x28: // CLRMAC();
- UML_MOV(block, mem(&sh2->macl), 0); // mov macl, #0
- UML_MOV(block, mem(&sh2->mach), 0); // mov mach, #0
+ UML_MOV(block, mem(&m_sh2_state->macl), 0); // mov macl, #0
+ UML_MOV(block, mem(&m_sh2_state->mach), 0); // mov mach, #0
return TRUE;
case 0x29: // MOVT(Rn);
- UML_AND(block, R32(Rn), mem(&sh2->sr), T); // and Rn, sr, T
+ UML_AND(block, R32(Rn), mem(&m_sh2_state->sr), T); // and Rn, sr, T
return TRUE;
case 0x2a: // STSPR(Rn);
- UML_MOV(block, R32(Rn), mem(&sh2->pr)); // mov Rn, pr
+ UML_MOV(block, R32(Rn), mem(&m_sh2_state->pr)); // mov Rn, pr
return TRUE;
case 0x2b: // RTE();
- generate_delay_slot(sh2, block, compiler, desc, 0xffffffff);
+ generate_delay_slot(block, compiler, desc, 0xffffffff);
UML_MOV(block, I0, R32(15)); // mov r0, R15
- UML_CALLH(block, *sh2->read32); // call read32
- UML_MOV(block, mem(&sh2->pc), I0); // mov pc, r0
+ UML_CALLH(block, *m_read32); // call read32
+ UML_MOV(block, mem(&m_sh2_state->pc), I0); // mov pc, r0
UML_ADD(block, R32(15), R32(15), 4); // add R15, R15, #4
UML_MOV(block, I0, R32(15)); // mov r0, R15
- UML_CALLH(block, *sh2->read32); // call read32
- UML_MOV(block, mem(&sh2->sr), I0); // mov sr, r0
+ UML_CALLH(block, *m_read32); // call read32
+ UML_MOV(block, mem(&m_sh2_state->sr), I0); // mov sr, r0
UML_ADD(block, R32(15), R32(15), 4); // add R15, R15, #4
compiler->checkints = TRUE;
- UML_MOV(block, mem(&sh2->ea), mem(&sh2->pc)); // mov ea, pc
- generate_update_cycles(sh2, block, compiler, mem(&sh2->ea), TRUE); // <subtract cycles>
- UML_HASHJMP(block, 0, mem(&sh2->pc), *sh2->nocode); // and jump to the "resume PC"
+ UML_MOV(block, mem(&m_sh2_state->ea), mem(&m_sh2_state->pc)); // mov ea, pc
+ generate_update_cycles(block, compiler, mem(&m_sh2_state->ea), TRUE); // <subtract cycles>
+ UML_HASHJMP(block, 0, mem(&m_sh2_state->pc), *m_nocode); // and jump to the "resume PC"
return TRUE;
}
@@ -2068,35 +1849,35 @@ static int generate_group_0(sh2_state *sh2, drcuml_block *block, compiler_state
return FALSE;
}
-static int generate_group_2(sh2_state *sh2, drcuml_block *block, compiler_state *compiler, const opcode_desc *desc, UINT16 opcode, int in_delay_slot, UINT32 ovrpc)
+int sh2_device::generate_group_2(drcuml_block *block, compiler_state *compiler, const opcode_desc *desc, UINT16 opcode, int in_delay_slot, UINT32 ovrpc)
{
switch (opcode & 15)
{
case 0: // MOVBS(Rm, Rn);
UML_MOV(block, I0, R32(Rn)); // mov r0, Rn
UML_AND(block, I1, R32(Rm), 0xff); // and r1, Rm, 0xff
- UML_CALLH(block, *sh2->write8);
+ UML_CALLH(block, *m_write8);
if (!in_delay_slot)
- generate_update_cycles(sh2, block, compiler, desc->pc + 2, TRUE);
+ generate_update_cycles(block, compiler, desc->pc + 2, TRUE);
return TRUE;
case 1: // MOVWS(Rm, Rn);
UML_MOV(block, I0, R32(Rn)); // mov r0, Rn
UML_AND(block, I1, R32(Rm), 0xffff); // and r1, Rm, 0xffff
- UML_CALLH(block, *sh2->write16);
+ UML_CALLH(block, *m_write16);
if (!in_delay_slot)
- generate_update_cycles(sh2, block, compiler, desc->pc + 2, TRUE);
+ generate_update_cycles(block, compiler, desc->pc + 2, TRUE);
return TRUE;
case 2: // MOVLS(Rm, Rn);
UML_MOV(block, I0, R32(Rn)); // mov r0, Rn
UML_MOV(block, I1, R32(Rm)); // mov r1, Rm
- UML_CALLH(block, *sh2->write32);
+ UML_CALLH(block, *m_write32);
if (!in_delay_slot)
- generate_update_cycles(sh2, block, compiler, desc->pc + 2, TRUE);
+ generate_update_cycles(block, compiler, desc->pc + 2, TRUE);
return TRUE;
case 3:
@@ -2106,30 +1887,30 @@ static int generate_group_2(sh2_state *sh2, drcuml_block *block, compiler_state
UML_MOV(block, I1, R32(Rm)); // mov r1, Rm
UML_SUB(block, R32(Rn), R32(Rn), 1); // sub Rn, Rn, 1
UML_MOV(block, I0, R32(Rn)); // mov r0, Rn
- UML_CALLH(block, *sh2->write8); // call write8
+ UML_CALLH(block, *m_write8); // call write8
if (!in_delay_slot)
- generate_update_cycles(sh2, block, compiler, desc->pc + 2, TRUE);
+ generate_update_cycles(block, compiler, desc->pc + 2, TRUE);
return TRUE;
case 5: // MOVWM(Rm, Rn);
UML_MOV(block, I1, R32(Rm)); // mov r1, Rm
UML_SUB(block, R32(Rn), R32(Rn), 2); // sub Rn, Rn, 2
UML_MOV(block, I0, R32(Rn)); // mov r0, Rn
- UML_CALLH(block, *sh2->write16); // call write16
+ UML_CALLH(block, *m_write16); // call write16
if (!in_delay_slot)
- generate_update_cycles(sh2, block, compiler, desc->pc + 2, TRUE);
+ generate_update_cycles(block, compiler, desc->pc + 2, TRUE);
return TRUE;
case 6: // MOVLM(Rm, Rn);
UML_MOV(block, I1, R32(Rm)); // mov r1, Rm
UML_SUB(block, R32(Rn), R32(Rn), 4); // sub Rn, Rn, 4
UML_MOV(block, I0, R32(Rn)); // mov r0, Rn
- UML_CALLH(block, *sh2->write32); // call write32
+ UML_CALLH(block, *m_write32); // call write32
if (!in_delay_slot)
- generate_update_cycles(sh2, block, compiler, desc->pc + 2, TRUE);
+ generate_update_cycles(block, compiler, desc->pc + 2, TRUE);
return TRUE;
case 13: // XTRCT(Rm, Rn);
@@ -2143,7 +1924,7 @@ static int generate_group_2(sh2_state *sh2, drcuml_block *block, compiler_state
return TRUE;
case 7: // DIV0S(Rm, Rn);
- UML_MOV(block, I0, mem(&sh2->sr)); // move r0, sr
+ UML_MOV(block, I0, mem(&m_sh2_state->sr)); // move r0, sr
UML_AND(block, I0, I0, ~(Q|M|T)); // and r0, r0, ~(Q|M|T) (clear the Q,M, and T bits)
UML_TEST(block, R32(Rn), 0x80000000); // test Rn, #0x80000000
@@ -2164,18 +1945,18 @@ static int generate_group_2(sh2_state *sh2, drcuml_block *block, compiler_state
UML_OR(block, I0, I0, T); // or r0, r0, T
UML_LABEL(block, compiler->labelnum++); // labelnum:
- UML_MOV(block, mem(&sh2->sr), I0); // mov sr, r0
+ UML_MOV(block, mem(&m_sh2_state->sr), I0); // mov sr, r0
return TRUE;
case 8: // TST(Rm, Rn);
- UML_AND(block, I0, mem(&sh2->sr), ~T); // and r0, sr, ~T (clear the T bit)
+ UML_AND(block, I0, mem(&m_sh2_state->sr), ~T); // and r0, sr, ~T (clear the T bit)
UML_TEST(block, R32(Rm), R32(Rn)); // test Rm, Rn
UML_JMPc(block, COND_NZ, compiler->labelnum); // jnz compiler->labelnum
UML_OR(block, I0, I0, T); // or r0, r0, T
UML_LABEL(block, compiler->labelnum++); // desc->pc:
- UML_MOV(block, mem(&sh2->sr), I0); // mov sh2->sr, r0
+ UML_MOV(block, mem(&m_sh2_state->sr), I0); // mov m_sh2_state->sr, r0
return TRUE;
case 12: // CMPSTR(Rm, Rn);
@@ -2192,7 +1973,7 @@ static int generate_group_2(sh2_state *sh2, drcuml_block *block, compiler_state
UML_AND(block, I7, I0, 0xff); // and r7, r0, #0xff (LL)
- UML_AND(block, mem(&sh2->sr), mem(&sh2->sr), ~T); // and sr, sr, ~T (clear the T bit)
+ UML_AND(block, mem(&m_sh2_state->sr), mem(&m_sh2_state->sr), ~T); // and sr, sr, ~T (clear the T bit)
UML_CMP(block, I1, 0); // cmp r1, #0
UML_JMPc(block, COND_Z, compiler->labelnum); // jnz labelnum
@@ -2204,7 +1985,7 @@ static int generate_group_2(sh2_state *sh2, drcuml_block *block, compiler_state
UML_JMPc(block, COND_NZ, compiler->labelnum+1); // jnz labelnum
UML_LABEL(block, compiler->labelnum++); // labelnum:
- UML_OR(block, mem(&sh2->sr), mem(&sh2->sr), T); // or sr, sr, T
+ UML_OR(block, mem(&m_sh2_state->sr), mem(&m_sh2_state->sr), T); // or sr, sr, T
UML_LABEL(block, compiler->labelnum++); // labelnum+1:
return TRUE;
@@ -2224,51 +2005,51 @@ static int generate_group_2(sh2_state *sh2, drcuml_block *block, compiler_state
case 14: // MULU(Rm, Rn);
UML_AND(block, I0, R32(Rm), 0xffff); // and r0, Rm, 0xffff
UML_AND(block, I1, R32(Rn), 0xffff); // and r1, Rn, 0xffff
- UML_MULU(block, mem(&sh2->macl), mem(&sh2->ea), I0, I1); // mulu macl, ea, r0, r1
+ UML_MULU(block, mem(&m_sh2_state->macl), mem(&m_sh2_state->ea), I0, I1); // mulu macl, ea, r0, r1
return TRUE;
case 15: // MULS(Rm, Rn);
UML_SEXT(block, I0, R32(Rm), SIZE_WORD); // sext r0, Rm
UML_SEXT(block, I1, R32(Rn), SIZE_WORD); // sext r1, Rn
- UML_MULS(block, mem(&sh2->macl), mem(&sh2->ea), I0, I1); // muls macl, ea, r0, r1
+ UML_MULS(block, mem(&m_sh2_state->macl), mem(&m_sh2_state->ea), I0, I1); // muls macl, ea, r0, r1
return TRUE;
}
return FALSE;
}
-static int generate_group_3(sh2_state *sh2, drcuml_block *block, compiler_state *compiler, const opcode_desc *desc, UINT16 opcode, UINT32 ovrpc)
+int sh2_device::generate_group_3(drcuml_block *block, compiler_state *compiler, const opcode_desc *desc, UINT16 opcode, UINT32 ovrpc)
{
switch (opcode & 15)
{
case 0: // CMPEQ(Rm, Rn); (equality)
UML_CMP(block, R32(Rn), R32(Rm)); // cmp Rn, Rm
UML_SETc(block, COND_E, I0); // set E, r0
- UML_ROLINS(block, mem(&sh2->sr), I0, 0, 1); // rolins sr, r0, 0, 1
+ UML_ROLINS(block, mem(&m_sh2_state->sr), I0, 0, 1); // rolins sr, r0, 0, 1
return TRUE;
case 2: // CMPHS(Rm, Rn); (unsigned greater than or equal)
UML_CMP(block, R32(Rn), R32(Rm)); // cmp Rn, Rm
UML_SETc(block, COND_AE, I0); // set AE, r0
- UML_ROLINS(block, mem(&sh2->sr), I0, 0, 1); // rolins sr, r0, 0, 1
+ UML_ROLINS(block, mem(&m_sh2_state->sr), I0, 0, 1); // rolins sr, r0, 0, 1
return TRUE;
case 3: // CMPGE(Rm, Rn); (signed greater than or equal)
UML_CMP(block, R32(Rn), R32(Rm)); // cmp Rn, Rm
UML_SETc(block, COND_GE, I0); // set GE, r0
- UML_ROLINS(block, mem(&sh2->sr), I0, 0, 1); // rolins sr, r0, 0, 1
+ UML_ROLINS(block, mem(&m_sh2_state->sr), I0, 0, 1); // rolins sr, r0, 0, 1
return TRUE;
case 6: // CMPHI(Rm, Rn); (unsigned greater than)
UML_CMP(block, R32(Rn), R32(Rm)); // cmp Rn, Rm
UML_SETc(block, COND_A, I0); // set A, r0
- UML_ROLINS(block, mem(&sh2->sr), I0, 0, 1); // rolins sr, r0, 0, 1
+ UML_ROLINS(block, mem(&m_sh2_state->sr), I0, 0, 1); // rolins sr, r0, 0, 1
return TRUE;
case 7: // CMPGT(Rm, Rn); (signed greater than)
UML_CMP(block, R32(Rn), R32(Rm)); // cmp Rn, Rm
UML_SETc(block, COND_G, I0); // set G, r0
- UML_ROLINS(block, mem(&sh2->sr), I0, 0, 1); // rolins sr, r0, 0, 1
+ UML_ROLINS(block, mem(&m_sh2_state->sr), I0, 0, 1); // rolins sr, r0, 0, 1
return TRUE;
case 1:
@@ -2276,24 +2057,24 @@ static int generate_group_3(sh2_state *sh2, drcuml_block *block, compiler_state
return FALSE;
case 4: // DIV1(Rm, Rn);
- save_fast_iregs(sh2, block);
- UML_MOV(block, mem(&sh2->arg0), desc->opptr.w[0]);
- UML_CALLC(block, cfunc_DIV1, sh2);
- load_fast_iregs(sh2, block);
+ save_fast_iregs(block);
+ UML_MOV(block, mem(&m_sh2_state->arg0), desc->opptr.w[0]);
+ UML_CALLC(block, cfunc_DIV1, this);
+ load_fast_iregs(block);
return TRUE;
case 5: // DMULU(Rm, Rn);
- if (sh2->cpu_type > CPU_TYPE_SH1)
+ if (m_cpu_type > CPU_TYPE_SH1)
{
- UML_MULU(block, mem(&sh2->macl), mem(&sh2->mach), R32(Rn), R32(Rm));
+ UML_MULU(block, mem(&m_sh2_state->macl), mem(&m_sh2_state->mach), R32(Rn), R32(Rm));
return TRUE;
}
break;
case 13: // DMULS(Rm, Rn);
- if (sh2->cpu_type > CPU_TYPE_SH1)
+ if (m_cpu_type > CPU_TYPE_SH1)
{
- UML_MULS(block, mem(&sh2->macl), mem(&sh2->mach), R32(Rn), R32(Rm));
+ UML_MULS(block, mem(&m_sh2_state->macl), mem(&m_sh2_state->mach), R32(Rn), R32(Rm));
return TRUE;
}
break;
@@ -2307,119 +2088,119 @@ static int generate_group_3(sh2_state *sh2, drcuml_block *block, compiler_state
return TRUE;
case 10: // SUBC(Rm, Rn);
- UML_CARRY(block, mem(&sh2->sr), 0); // carry = T (T is bit 0 of SR)
+ UML_CARRY(block, mem(&m_sh2_state->sr), 0); // carry = T (T is bit 0 of SR)
UML_SUBB(block, R32(Rn), R32(Rn), R32(Rm)); // addc Rn, Rn, Rm
UML_SETc(block, COND_C, I0); // setc i0, C
- UML_ROLINS(block, mem(&sh2->sr), I0, 0, T); // rolins sr,i0,0,T
+ UML_ROLINS(block, mem(&m_sh2_state->sr), I0, 0, T); // rolins sr,i0,0,T
return TRUE;
case 11: // SUBV(Rm, Rn);
#if ADDSUBV_DIRECT
UML_SUB(block, R32(Rn), R32(Rn), R32(Rm)); // sub Rn, Rn, Rm
UML_SETc(block, COND_V, I0); // setc i0, V
- UML_ROLINS(block, mem(&sh2->sr), I0, 0, T); // rolins [sr],i0,0,T
+ UML_ROLINS(block, mem(&m_sh2_state->sr), I0, 0, T); // rolins [sr],i0,0,T
#else
- save_fast_iregs(sh2, block);
- UML_MOV(block, mem(&sh2->arg0), desc->opptr.w[0]);
- UML_CALLC(block, cfunc_SUBV, sh2);
- load_fast_iregs(sh2, block);
+ save_fast_iregs(block);
+ UML_MOV(block, mem(&m_sh2_state->arg0), desc->opptr.w[0]);
+ UML_CALLC(block, cfunc_SUBV, this);
+ load_fast_iregs(block);
#endif
return TRUE;
case 14: // ADDC(Rm, Rn);
- UML_CARRY(block, mem(&sh2->sr), 0); // carry = T (T is bit 0 of SR)
+ UML_CARRY(block, mem(&m_sh2_state->sr), 0); // carry = T (T is bit 0 of SR)
UML_ADDC(block, R32(Rn), R32(Rn), R32(Rm)); // addc Rn, Rn, Rm
UML_SETc(block, COND_C, I0); // setc i0, C
- UML_ROLINS(block, mem(&sh2->sr), I0, 0, T); // rolins sr,i0,0,T
+ UML_ROLINS(block, mem(&m_sh2_state->sr), I0, 0, T); // rolins sr,i0,0,T
return TRUE;
case 15: // ADDV(Rm, Rn);
#if ADDSUBV_DIRECT
UML_ADD(block, R32(Rn), R32(Rn), R32(Rm)); // add Rn, Rn, Rm
UML_SETc(block, COND_V, I0); // setc i0, V
- UML_ROLINS(block, mem(&sh2->sr), I0, 0, T); // rolins [sr],i0,0,T
+ UML_ROLINS(block, mem(&m_sh2_state->sr), I0, 0, T); // rolins [sr],i0,0,T
#else
- save_fast_iregs(sh2, block);
- UML_MOV(block, mem(&sh2->arg0), desc->opptr.w[0]);
- UML_CALLC(block, cfunc_ADDV, sh2);
- load_fast_iregs(sh2, block);
+ save_fast_iregs(block);
+ UML_MOV(block, mem(&m_sh2_state->arg0), desc->opptr.w[0]);
+ UML_CALLC(block, cfunc_ADDV, this);
+ load_fast_iregs(block);
#endif
return TRUE;
}
return FALSE;
}
-static int generate_group_4(sh2_state *sh2, drcuml_block *block, compiler_state *compiler, const opcode_desc *desc, UINT16 opcode, int in_delay_slot, UINT32 ovrpc)
+int sh2_device::generate_group_4(drcuml_block *block, compiler_state *compiler, const opcode_desc *desc, UINT16 opcode, int in_delay_slot, UINT32 ovrpc)
{
switch (opcode & 0x3F)
{
case 0x00: // SHLL(Rn);
UML_SHL(block, R32(Rn), R32(Rn), 1); // shl Rn, Rn, 1
UML_SETc(block, COND_C, I0); // set i0,C
- UML_ROLINS(block, mem(&sh2->sr), I0, 0, T); // rolins [sr],i0,0,T
+ UML_ROLINS(block, mem(&m_sh2_state->sr), I0, 0, T); // rolins [sr],i0,0,T
return TRUE;
case 0x01: // SHLR(Rn);
UML_SHR(block, R32(Rn), R32(Rn), 1); // shr Rn, Rn, 1
UML_SETc(block, COND_C, I0); // set i0,C
- UML_ROLINS(block, mem(&sh2->sr), I0, 0, T); // rolins [sr],i0,0,T
+ UML_ROLINS(block, mem(&m_sh2_state->sr), I0, 0, T); // rolins [sr],i0,0,T
return TRUE;
case 0x04: // ROTL(Rn);
UML_ROL(block, R32(Rn), R32(Rn), 1); // rol Rn, Rn, 1
UML_SETc(block, COND_C, I0); // set i0,C
- UML_ROLINS(block, mem(&sh2->sr), I0, 0, T); // rolins [sr],i0,0,T
+ UML_ROLINS(block, mem(&m_sh2_state->sr), I0, 0, T); // rolins [sr],i0,0,T
return TRUE;
case 0x05: // ROTR(Rn);
UML_ROR(block, R32(Rn), R32(Rn), 1); // ror Rn, Rn, 1
UML_SETc(block, COND_C, I0); // set i0,C
- UML_ROLINS(block, mem(&sh2->sr), I0, 0, T); // rolins [sr],i0,0,T
+ UML_ROLINS(block, mem(&m_sh2_state->sr), I0, 0, T); // rolins [sr],i0,0,T
return TRUE;
case 0x02: // STSMMACH(Rn);
UML_SUB(block, R32(Rn), R32(Rn), 4); // sub Rn, Rn, #4
UML_MOV(block, I0, R32(Rn)); // mov r0, Rn
- UML_MOV(block, I1, mem(&sh2->mach)); // mov r1, mach
+ UML_MOV(block, I1, mem(&m_sh2_state->mach)); // mov r1, mach
SETEA(0); // set ea for debug
- UML_CALLH(block, *sh2->write32); // call write32
+ UML_CALLH(block, *m_write32); // call write32
if (!in_delay_slot)
- generate_update_cycles(sh2, block, compiler, desc->pc + 2, TRUE);
+ generate_update_cycles(block, compiler, desc->pc + 2, TRUE);
return TRUE;
case 0x03: // STCMSR(Rn);
UML_SUB(block, R32(Rn), R32(Rn), 4); // sub Rn, Rn, #4
UML_MOV(block, I0, R32(Rn)); // mov r0, Rn
- UML_MOV(block, I1, mem(&sh2->sr)); // mov r1, sr
+ UML_MOV(block, I1, mem(&m_sh2_state->sr)); // mov r1, sr
SETEA(0); // set ea for debug
- UML_CALLH(block, *sh2->write32); // call write32
+ UML_CALLH(block, *m_write32); // call write32
if (!in_delay_slot)
- generate_update_cycles(sh2, block, compiler, desc->pc + 2, TRUE);
+ generate_update_cycles(block, compiler, desc->pc + 2, TRUE);
return TRUE;
case 0x06: // LDSMMACH(Rn);
UML_MOV(block, I0, R32(Rn)); // mov r0, Rn
SETEA(0);
- UML_CALLH(block, *sh2->read32); // call read32
+ UML_CALLH(block, *m_read32); // call read32
UML_ADD(block, R32(Rn), R32(Rn), 4); // add Rn, #4
- UML_MOV(block, mem(&sh2->mach), I0); // mov mach, r0
+ UML_MOV(block, mem(&m_sh2_state->mach), I0); // mov mach, r0
if (!in_delay_slot)
- generate_update_cycles(sh2, block, compiler, desc->pc + 2, TRUE);
+ generate_update_cycles(block, compiler, desc->pc + 2, TRUE);
return TRUE;
case 0x07: // LDCMSR(Rn);
UML_MOV(block, I0, R32(Rn)); // mov r0, Rn
SETEA(0);
- UML_CALLH(block, *sh2->read32); // call read32
+ UML_CALLH(block, *m_read32); // call read32
UML_ADD(block, R32(Rn), R32(Rn), 4); // add Rn, #4
- UML_MOV(block, mem(&sh2->sr), I0); // mov sr, r0
+ UML_MOV(block, mem(&m_sh2_state->sr), I0); // mov sr, r0
compiler->checkints = TRUE;
if (!in_delay_slot)
- generate_update_cycles(sh2, block, compiler, desc->pc + 2, TRUE);
+ generate_update_cycles(block, compiler, desc->pc + 2, TRUE);
return TRUE;
@@ -2448,24 +2229,24 @@ static int generate_group_4(sh2_state *sh2, drcuml_block *block, compiler_state
return TRUE;
case 0x0a: // LDSMACH(Rn);
- UML_MOV(block, mem(&sh2->mach), R32(Rn)); // mov mach, Rn
+ UML_MOV(block, mem(&m_sh2_state->mach), R32(Rn)); // mov mach, Rn
return TRUE;
case 0x0b: // JSR(Rn);
- UML_MOV(block, mem(&sh2->target), R32(Rn)); // mov target, Rn
+ UML_MOV(block, mem(&m_sh2_state->target), R32(Rn)); // mov target, Rn
- UML_ADD(block, mem(&sh2->pr), desc->pc, 4); // add sh2->pr, desc->pc, #4 (skip the current insn & delay slot)
+ UML_ADD(block, mem(&m_sh2_state->pr), desc->pc, 4); // add m_pr, desc->pc, #4 (skip the current insn & delay slot)
- generate_delay_slot(sh2, block, compiler, desc, sh2->target-4);
+ generate_delay_slot(block, compiler, desc, m_sh2_state->target-4);
- generate_update_cycles(sh2, block, compiler, mem(&sh2->target), TRUE); // <subtract cycles>
- UML_HASHJMP(block, 0, mem(&sh2->target), *sh2->nocode); // and do the jump
+ generate_update_cycles(block, compiler, mem(&m_sh2_state->target), TRUE); // <subtract cycles>
+ UML_HASHJMP(block, 0, mem(&m_sh2_state->target), *m_nocode); // and do the jump
return TRUE;
case 0x0e: // LDCSR(Rn);
UML_MOV(block, I0, R32(Rn)); // mov r0, Rn
UML_AND(block, I0, I0, FLAGS); // and r0, r0, FLAGS
- UML_MOV(block, mem(&sh2->sr), I0);
+ UML_MOV(block, mem(&m_sh2_state->sr), I0);
compiler->checkints = TRUE;
return TRUE;
@@ -2474,29 +2255,29 @@ static int generate_group_4(sh2_state *sh2, drcuml_block *block, compiler_state
case 0x1f: // MAC_W(Rm, Rn);
case 0x2f: // MAC_W(Rm, Rn);
case 0x3f: // MAC_W(Rm, Rn);
- save_fast_iregs(sh2, block);
- UML_MOV(block, mem(&sh2->arg0), desc->opptr.w[0]);
- UML_CALLC(block, cfunc_MAC_W, sh2);
- load_fast_iregs(sh2, block);
+ save_fast_iregs(block);
+ UML_MOV(block, mem(&m_sh2_state->arg0), desc->opptr.w[0]);
+ UML_CALLC(block, cfunc_MAC_W, this);
+ load_fast_iregs(block);
return TRUE;
case 0x10: // DT(Rn);
- if (sh2->cpu_type > CPU_TYPE_SH1)
+ if (m_cpu_type > CPU_TYPE_SH1)
{
- UML_AND(block, I0, mem(&sh2->sr), ~T); // and r0, sr, ~T (clear the T bit)
+ UML_AND(block, I0, mem(&m_sh2_state->sr), ~T); // and r0, sr, ~T (clear the T bit)
UML_SUB(block, R32(Rn), R32(Rn), 1); // sub Rn, Rn, 1
UML_JMPc(block, COND_NZ, compiler->labelnum); // jz compiler->labelnum
UML_OR(block, I0, I0, T); // or r0, r0, T
UML_LABEL(block, compiler->labelnum++); // desc->pc:
- UML_MOV(block, mem(&sh2->sr), I0); // mov sh2->sr, r0
+ UML_MOV(block, mem(&m_sh2_state->sr), I0); // mov m_sh2_state->sr, r0
return TRUE;
}
break;
case 0x11: // CMPPZ(Rn);
- UML_AND(block, I0, mem(&sh2->sr), ~T); // and r0, sr, ~T (clear the T bit)
+ UML_AND(block, I0, mem(&m_sh2_state->sr), ~T); // and r0, sr, ~T (clear the T bit)
UML_CMP(block, R32(Rn), 0); // cmp Rn, 0
UML_JMPc(block, COND_S, compiler->labelnum); // js compiler->labelnum (if negative)
@@ -2504,11 +2285,11 @@ static int generate_group_4(sh2_state *sh2, drcuml_block *block, compiler_state
UML_OR(block, I0, I0, T); // or r0, r0, T
UML_LABEL(block, compiler->labelnum++); // desc->pc:
- UML_MOV(block, mem(&sh2->sr), I0); // mov sh2->sr, r0
+ UML_MOV(block, mem(&m_sh2_state->sr), I0); // mov m_sh2_state->sr, r0
return TRUE;
case 0x15: // CMPPL(Rn);
- UML_AND(block, I0, mem(&sh2->sr), ~T); // and r0, sr, ~T (clear the T bit)
+ UML_AND(block, I0, mem(&m_sh2_state->sr), ~T); // and r0, sr, ~T (clear the T bit)
UML_CMP(block, R32(Rn), 0); // cmp Rn, 0
@@ -2518,96 +2299,96 @@ static int generate_group_4(sh2_state *sh2, drcuml_block *block, compiler_state
UML_OR(block, I0, I0, T); // or r0, r0, T
UML_LABEL(block, compiler->labelnum++); // desc->pc:
- UML_MOV(block, mem(&sh2->sr), I0); // mov sh2->sr, r0
+ UML_MOV(block, mem(&m_sh2_state->sr), I0); // mov m_sh2_state->sr, r0
return TRUE;
case 0x12: // STSMMACL(Rn);
UML_SUB(block, R32(Rn), R32(Rn), 4); // sub Rn, Rn, #4
UML_MOV(block, I0, R32(Rn)); // mov r0, Rn
- UML_MOV(block, I1, mem(&sh2->macl)); // mov r1, macl
+ UML_MOV(block, I1, mem(&m_sh2_state->macl)); // mov r1, macl
SETEA(0); // set ea for debug
- UML_CALLH(block, *sh2->write32); // call write32
+ UML_CALLH(block, *m_write32); // call write32
if (!in_delay_slot)
- generate_update_cycles(sh2, block, compiler, desc->pc + 2, TRUE);
+ generate_update_cycles(block, compiler, desc->pc + 2, TRUE);
return TRUE;
case 0x13: // STCMGBR(Rn);
UML_SUB(block, R32(Rn), R32(Rn), 4); // sub Rn, Rn, #4
UML_MOV(block, I0, R32(Rn)); // mov r0, Rn
- UML_MOV(block, I1, mem(&sh2->gbr)); // mov r1, gbr
+ UML_MOV(block, I1, mem(&m_sh2_state->gbr)); // mov r1, gbr
SETEA(0); // set ea for debug
- UML_CALLH(block, *sh2->write32); // call write32
+ UML_CALLH(block, *m_write32); // call write32
if (!in_delay_slot)
- generate_update_cycles(sh2, block, compiler, desc->pc + 2, TRUE);
+ generate_update_cycles(block, compiler, desc->pc + 2, TRUE);
return TRUE;
case 0x16: // LDSMMACL(Rn);
UML_MOV(block, I0, R32(Rn)); // mov r0, Rn
SETEA(0);
- UML_CALLH(block, *sh2->read32); // call read32
+ UML_CALLH(block, *m_read32); // call read32
UML_ADD(block, R32(Rn), R32(Rn), 4); // add Rn, #4
- UML_MOV(block, mem(&sh2->macl), I0); // mov macl, r0
+ UML_MOV(block, mem(&m_sh2_state->macl), I0); // mov macl, r0
if (!in_delay_slot)
- generate_update_cycles(sh2, block, compiler, desc->pc + 2, TRUE);
+ generate_update_cycles(block, compiler, desc->pc + 2, TRUE);
return TRUE;
case 0x17: // LDCMGBR(Rn);
UML_MOV(block, I0, R32(Rn)); // mov r0, Rn
SETEA(0);
- UML_CALLH(block, *sh2->read32); // call read32
+ UML_CALLH(block, *m_read32); // call read32
UML_ADD(block, R32(Rn), R32(Rn), 4); // add Rn, #4
- UML_MOV(block, mem(&sh2->gbr), I0); // mov gbr, r0
+ UML_MOV(block, mem(&m_sh2_state->gbr), I0); // mov gbr, r0
if (!in_delay_slot)
- generate_update_cycles(sh2, block, compiler, desc->pc + 2, TRUE);
+ generate_update_cycles(block, compiler, desc->pc + 2, TRUE);
return TRUE;
case 0x1a: // LDSMACL(Rn);
- UML_MOV(block, mem(&sh2->macl), R32(Rn)); // mov macl, Rn
+ UML_MOV(block, mem(&m_sh2_state->macl), R32(Rn)); // mov macl, Rn
return TRUE;
case 0x1b: // TAS(Rn);
UML_MOV(block, I0, R32(Rn)); // mov r0, Rn
SETEA(0);
- UML_CALLH(block, *sh2->read8); // call read8
+ UML_CALLH(block, *m_read8); // call read8
- UML_AND(block, mem(&sh2->sr), mem(&sh2->sr), ~T); // and sr, sr, ~T
+ UML_AND(block, mem(&m_sh2_state->sr), mem(&m_sh2_state->sr), ~T); // and sr, sr, ~T
UML_CMP(block, I0, 0); // cmp r0, #0
UML_JMPc(block, COND_NZ, compiler->labelnum); // jnz labelnum
- UML_OR(block, mem(&sh2->sr), mem(&sh2->sr), T); // or sr, sr, T
+ UML_OR(block, mem(&m_sh2_state->sr), mem(&m_sh2_state->sr), T); // or sr, sr, T
UML_LABEL(block, compiler->labelnum++); // labelnum:
UML_OR(block, I1, I0, 0x80); // or r1, r0, #0x80
UML_MOV(block, I0, R32(Rn)); // mov r0, Rn
- UML_CALLH(block, *sh2->write8); // write the value back
+ UML_CALLH(block, *m_write8); // write the value back
if (!in_delay_slot)
- generate_update_cycles(sh2, block, compiler, desc->pc + 2, TRUE);
+ generate_update_cycles(block, compiler, desc->pc + 2, TRUE);
return TRUE;
case 0x1e: // LDCGBR(Rn);
- UML_MOV(block, mem(&sh2->gbr), R32(Rn)); // mov gbr, Rn
+ UML_MOV(block, mem(&m_sh2_state->gbr), R32(Rn)); // mov gbr, Rn
return TRUE;
case 0x20: // SHAL(Rn);
- UML_AND(block, mem(&sh2->sr), mem(&sh2->sr), ~T); // and sr, sr, ~T
+ UML_AND(block, mem(&m_sh2_state->sr), mem(&m_sh2_state->sr), ~T); // and sr, sr, ~T
UML_SHR(block, I0, R32(Rn), 31); // shr r0, Rn, 31
UML_AND(block, I0, I0, T); // and r0, r0, T
- UML_OR(block, mem(&sh2->sr), mem(&sh2->sr), I0); // or sr, sr, r0
+ UML_OR(block, mem(&m_sh2_state->sr), mem(&m_sh2_state->sr), I0); // or sr, sr, r0
UML_SHL(block, R32(Rn), R32(Rn), 1); // shl Rn, Rn, 1
return TRUE;
case 0x21: // SHAR(Rn);
- UML_AND(block, mem(&sh2->sr), mem(&sh2->sr), ~T); // and sr, sr, ~T
+ UML_AND(block, mem(&m_sh2_state->sr), mem(&m_sh2_state->sr), ~T); // and sr, sr, ~T
UML_AND(block, I0, R32(Rn), T); // and r0, Rn, T
- UML_OR(block, mem(&sh2->sr), mem(&sh2->sr), I0); // or sr, sr, r0
+ UML_OR(block, mem(&m_sh2_state->sr), mem(&m_sh2_state->sr), I0); // or sr, sr, r0
UML_SAR(block, R32(Rn), R32(Rn), 1); // sar Rn, Rn, 1
return TRUE;
@@ -2615,75 +2396,75 @@ static int generate_group_4(sh2_state *sh2, drcuml_block *block, compiler_state
UML_SUB(block, R32(Rn), R32(Rn), 4); // sub Rn, Rn, 4
UML_MOV(block, I0, R32(Rn)); // mov r0, Rn
SETEA(0);
- UML_MOV(block, I1, mem(&sh2->pr)); // mov r1, pr
- UML_CALLH(block, *sh2->write32); // call write32
+ UML_MOV(block, I1, mem(&m_sh2_state->pr)); // mov r1, pr
+ UML_CALLH(block, *m_write32); // call write32
if (!in_delay_slot)
- generate_update_cycles(sh2, block, compiler, desc->pc + 2, TRUE);
+ generate_update_cycles(block, compiler, desc->pc + 2, TRUE);
return TRUE;
case 0x23: // STCMVBR(Rn);
UML_SUB(block, R32(Rn), R32(Rn), 4); // sub Rn, Rn, 4
UML_MOV(block, I0, R32(Rn)); // mov r0, Rn
SETEA(0);
- UML_MOV(block, I1, mem(&sh2->vbr)); // mov r1, vbr
- UML_CALLH(block, *sh2->write32); // call write32
+ UML_MOV(block, I1, mem(&m_sh2_state->vbr)); // mov r1, vbr
+ UML_CALLH(block, *m_write32); // call write32
if (!in_delay_slot)
- generate_update_cycles(sh2, block, compiler, desc->pc + 2, TRUE);
+ generate_update_cycles(block, compiler, desc->pc + 2, TRUE);
return TRUE;
case 0x24: // ROTCL(Rn);
- UML_CARRY(block, mem(&sh2->sr), 0); // carry sr,0
+ UML_CARRY(block, mem(&m_sh2_state->sr), 0); // carry sr,0
UML_ROLC(block, R32(Rn), R32(Rn), 1); // rolc Rn,Rn,1
UML_SETc(block, COND_C, I0); // set i0,C
- UML_ROLINS(block, mem(&sh2->sr), I0, 0, T); // rolins sr,i0,0,T
+ UML_ROLINS(block, mem(&m_sh2_state->sr), I0, 0, T); // rolins sr,i0,0,T
return TRUE;
case 0x25: // ROTCR(Rn);
- UML_CARRY(block, mem(&sh2->sr), 0); // carry sr,0
+ UML_CARRY(block, mem(&m_sh2_state->sr), 0); // carry sr,0
UML_RORC(block, R32(Rn), R32(Rn), 1); // rorc Rn,Rn,1
UML_SETc(block, COND_C, I0); // set i0,C
- UML_ROLINS(block, mem(&sh2->sr), I0, 0, T); // rolins sr,i0,0,T
+ UML_ROLINS(block, mem(&m_sh2_state->sr), I0, 0, T); // rolins sr,i0,0,T
return TRUE;
case 0x26: // LDSMPR(Rn);
UML_MOV(block, I0, R32(Rn)); // mov r0, Rn
SETEA(0);
- UML_CALLH(block, *sh2->read32); // call read32
- UML_MOV(block, mem(&sh2->pr), I0); // mov sh2->pr, r0
+ UML_CALLH(block, *m_read32); // call read32
+ UML_MOV(block, mem(&m_sh2_state->pr), I0); // mov m_pr, r0
UML_ADD(block, R32(Rn), R32(Rn), 4); // add Rn, Rn, #4
if (!in_delay_slot)
- generate_update_cycles(sh2, block, compiler, desc->pc + 2, TRUE);
+ generate_update_cycles(block, compiler, desc->pc + 2, TRUE);
return TRUE;
case 0x27: // LDCMVBR(Rn);
UML_MOV(block, I0, R32(Rn)); // mov r0, Rn
SETEA(0);
- UML_CALLH(block, *sh2->read32); // call read32
- UML_MOV(block, mem(&sh2->vbr), I0); // mov sh2->vbr, r0
+ UML_CALLH(block, *m_read32); // call read32
+ UML_MOV(block, mem(&m_sh2_state->vbr), I0); // mov m_sh2_state->vbr, r0
UML_ADD(block, R32(Rn), R32(Rn), 4); // add Rn, Rn, #4
if (!in_delay_slot)
- generate_update_cycles(sh2, block, compiler, desc->pc + 2, TRUE);
+ generate_update_cycles(block, compiler, desc->pc + 2, TRUE);
return TRUE;
case 0x2a: // LDSPR(Rn);
- UML_MOV(block, mem(&sh2->pr), R32(Rn)); // mov sh2->pr, Rn
+ UML_MOV(block, mem(&m_sh2_state->pr), R32(Rn)); // mov m_pr, Rn
return TRUE;
case 0x2b: // JMP(Rn);
- UML_MOV(block, mem(&sh2->target), R32(Rn)); // mov target, Rn
+ UML_MOV(block, mem(&m_sh2_state->target), R32(Rn)); // mov target, Rn
- generate_delay_slot(sh2, block, compiler, desc, sh2->target);
+ generate_delay_slot(block, compiler, desc, m_sh2_state->target);
- generate_update_cycles(sh2, block, compiler, mem(&sh2->target), TRUE); // <subtract cycles>
- UML_HASHJMP(block, 0, mem(&sh2->target), *sh2->nocode); // jmp (target)
+ generate_update_cycles(block, compiler, mem(&m_sh2_state->target), TRUE); // <subtract cycles>
+ UML_HASHJMP(block, 0, mem(&m_sh2_state->target), *m_nocode); // jmp (target)
return TRUE;
case 0x2e: // LDCVBR(Rn);
- UML_MOV(block, mem(&sh2->vbr), R32(Rn)); // mov vbr, Rn
+ UML_MOV(block, mem(&m_sh2_state->vbr), R32(Rn)); // mov vbr, Rn
return TRUE;
case 0x0c:
@@ -2714,38 +2495,38 @@ static int generate_group_4(sh2_state *sh2, drcuml_block *block, compiler_state
return FALSE;
}
-static int generate_group_6(sh2_state *sh2, drcuml_block *block, compiler_state *compiler, const opcode_desc *desc, UINT16 opcode, int in_delay_slot, UINT32 ovrpc)
+int sh2_device::generate_group_6(drcuml_block *block, compiler_state *compiler, const opcode_desc *desc, UINT16 opcode, int in_delay_slot, UINT32 ovrpc)
{
switch (opcode & 15)
{
case 0: // MOVBL(Rm, Rn);
UML_MOV(block, I0, R32(Rm)); // mov r0, Rm
SETEA(0); // debug: ea = r0
- UML_CALLH(block, *sh2->read8); // call read8
+ UML_CALLH(block, *m_read8); // call read8
UML_SEXT(block, R32(Rn), I0, SIZE_BYTE); // sext Rn, r0, BYTE
if (!in_delay_slot)
- generate_update_cycles(sh2, block, compiler, desc->pc + 2, TRUE);
+ generate_update_cycles(block, compiler, desc->pc + 2, TRUE);
return TRUE;
case 1: // MOVWL(Rm, Rn);
UML_MOV(block, I0, R32(Rm)); // mov r0, Rm
SETEA(0); // debug: ea = r0
- UML_CALLH(block, *sh2->read16); // call read16
+ UML_CALLH(block, *m_read16); // call read16
UML_SEXT(block, R32(Rn), I0, SIZE_WORD); // sext Rn, r0, WORD
if (!in_delay_slot)
- generate_update_cycles(sh2, block, compiler, desc->pc + 2, TRUE);
+ generate_update_cycles(block, compiler, desc->pc + 2, TRUE);
return TRUE;
case 2: // MOVLL(Rm, Rn);
UML_MOV(block, I0, R32(Rm)); // mov r0, Rm
SETEA(0); // debug: ea = r0
- UML_CALLH(block, *sh2->read32); // call read32
+ UML_CALLH(block, *m_read32); // call read32
UML_MOV(block, R32(Rn), I0); // mov Rn, r0
if (!in_delay_slot)
- generate_update_cycles(sh2, block, compiler, desc->pc + 2, TRUE);
+ generate_update_cycles(block, compiler, desc->pc + 2, TRUE);
return TRUE;
case 3: // MOV(Rm, Rn);
@@ -2782,38 +2563,38 @@ static int generate_group_6(sh2_state *sh2, drcuml_block *block, compiler_state
case 4: // MOVBP(Rm, Rn);
UML_MOV(block, I0, R32(Rm)); // mov r0, Rm
- UML_CALLH(block, *sh2->read8); // call read8
+ UML_CALLH(block, *m_read8); // call read8
UML_SEXT(block, R32(Rn), I0, SIZE_BYTE); // sext Rn, r0, BYTE
if (Rm != Rn)
UML_ADD(block, R32(Rm), R32(Rm), 1); // add Rm, Rm, #1
if (!in_delay_slot)
- generate_update_cycles(sh2, block, compiler, desc->pc + 2, TRUE);
+ generate_update_cycles(block, compiler, desc->pc + 2, TRUE);
return TRUE;
case 5: // MOVWP(Rm, Rn);
UML_MOV(block, I0, R32(Rm)); // mov r0, Rm
- UML_CALLH(block, *sh2->read16); // call read16
+ UML_CALLH(block, *m_read16); // call read16
UML_SEXT(block, R32(Rn), I0, SIZE_WORD); // sext Rn, r0, WORD
if (Rm != Rn)
UML_ADD(block, R32(Rm), R32(Rm), 2); // add Rm, Rm, #2
if (!in_delay_slot)
- generate_update_cycles(sh2, block, compiler, desc->pc + 2, TRUE);
+ generate_update_cycles(block, compiler, desc->pc + 2, TRUE);
return TRUE;
case 6: // MOVLP(Rm, Rn);
UML_MOV(block, I0, R32(Rm)); // mov r0, Rm
- UML_CALLH(block, *sh2->read32); // call read32
+ UML_CALLH(block, *m_read32); // call read32
UML_MOV(block, R32(Rn), I0); // mov Rn, r0
if (Rm != Rn)
UML_ADD(block, R32(Rm), R32(Rm), 4); // add Rm, Rm, #4
if (!in_delay_slot)
- generate_update_cycles(sh2, block, compiler, desc->pc + 2, TRUE);
+ generate_update_cycles(block, compiler, desc->pc + 2, TRUE);
return TRUE;
case 8: // SWAPB(Rm, Rn);
@@ -2827,14 +2608,14 @@ static int generate_group_6(sh2_state *sh2, drcuml_block *block, compiler_state
return TRUE;
case 10: // NEGC(Rm, Rn);
- UML_MOV(block, I0, mem(&sh2->sr)); // mov r0, sr (save SR)
- UML_AND(block, mem(&sh2->sr), mem(&sh2->sr), ~T); // and sr, sr, ~T (clear the T bit)
+ UML_MOV(block, I0, mem(&m_sh2_state->sr)); // mov r0, sr (save SR)
+ UML_AND(block, mem(&m_sh2_state->sr), mem(&m_sh2_state->sr), ~T); // and sr, sr, ~T (clear the T bit)
UML_CARRY(block, I0, 0); // carry = T (T is bit 0 of SR)
UML_SUBB(block, R32(Rn), 0, R32(Rm)); // subb Rn, #0, Rm
UML_JMPc(block, COND_NC, compiler->labelnum); // jnc labelnum
- UML_OR(block, mem(&sh2->sr), mem(&sh2->sr), T); // or sr, sr, T
+ UML_OR(block, mem(&m_sh2_state->sr), mem(&m_sh2_state->sr), T); // or sr, sr, T
UML_LABEL(block, compiler->labelnum++); // labelnum:
@@ -2844,7 +2625,7 @@ static int generate_group_6(sh2_state *sh2, drcuml_block *block, compiler_state
return FALSE;
}
-static int generate_group_8(sh2_state *sh2, drcuml_block *block, compiler_state *compiler, const opcode_desc *desc, UINT16 opcode, int in_delay_slot, UINT32 ovrpc)
+int sh2_device::generate_group_8(drcuml_block *block, compiler_state *compiler, const opcode_desc *desc, UINT16 opcode, int in_delay_slot, UINT32 ovrpc)
{
INT32 disp;
UINT32 udisp;
@@ -2856,20 +2637,20 @@ static int generate_group_8(sh2_state *sh2, drcuml_block *block, compiler_state
udisp = (opcode & 0x0f);
UML_ADD(block, I0, R32(Rm), udisp); // add r0, Rm, udisp
UML_MOV(block, I1, R32(0)); // mov r1, R0
- UML_CALLH(block, *sh2->write8); // call write8
+ UML_CALLH(block, *m_write8); // call write8
if (!in_delay_slot)
- generate_update_cycles(sh2, block, compiler, desc->pc + 2, TRUE);
+ generate_update_cycles(block, compiler, desc->pc + 2, TRUE);
return TRUE;
case 1 << 8: // MOVWS4(opcode & 0x0f, Rm);
udisp = (opcode & 0x0f) * 2;
UML_ADD(block, I0, R32(Rm), udisp); // add r0, Rm, udisp
UML_MOV(block, I1, R32(0)); // mov r1, R0
- UML_CALLH(block, *sh2->write16); // call write16
+ UML_CALLH(block, *m_write16); // call write16
if (!in_delay_slot)
- generate_update_cycles(sh2, block, compiler, desc->pc + 2, TRUE);
+ generate_update_cycles(block, compiler, desc->pc + 2, TRUE);
return TRUE;
case 2<< 8:
@@ -2885,26 +2666,26 @@ static int generate_group_8(sh2_state *sh2, drcuml_block *block, compiler_state
udisp = opcode & 0x0f;
UML_ADD(block, I0, R32(Rm), udisp); // add r0, Rm, udisp
SETEA(0);
- UML_CALLH(block, *sh2->read8); // call read8
+ UML_CALLH(block, *m_read8); // call read8
UML_SEXT(block, R32(0), I0, SIZE_BYTE); // sext R0, r0, BYTE
if (!in_delay_slot)
- generate_update_cycles(sh2, block, compiler, desc->pc + 2, TRUE);
+ generate_update_cycles(block, compiler, desc->pc + 2, TRUE);
return TRUE;
case 5<< 8: // MOVWL4(Rm, opcode & 0x0f);
udisp = (opcode & 0x0f)*2;
UML_ADD(block, I0, R32(Rm), udisp); // add r0, Rm, udisp
SETEA(0);
- UML_CALLH(block, *sh2->read16); // call read16
+ UML_CALLH(block, *m_read16); // call read16
UML_SEXT(block, R32(0), I0, SIZE_WORD); // sext R0, r0, WORD
if (!in_delay_slot)
- generate_update_cycles(sh2, block, compiler, desc->pc + 2, TRUE);
+ generate_update_cycles(block, compiler, desc->pc + 2, TRUE);
return TRUE;
case 8<< 8: // CMPIM(opcode & 0xff);
- UML_AND(block, I0, mem(&sh2->sr), ~T); // and r0, sr, ~T (clear the T bit)
+ UML_AND(block, I0, mem(&m_sh2_state->sr), ~T); // and r0, sr, ~T (clear the T bit)
UML_SEXT(block, I1, opcode&0xff, SIZE_BYTE); // sext r1, opcode&0xff, BYTE
UML_CMP(block, I1, R32(0)); // cmp r1, R0
@@ -2913,50 +2694,50 @@ static int generate_group_8(sh2_state *sh2, drcuml_block *block, compiler_state
UML_OR(block, I0, I0, T); // or r0, r0, T
UML_LABEL(block, compiler->labelnum++); // labelnum:
- UML_MOV(block, mem(&sh2->sr), I0); // mov sh2->sr, r0
+ UML_MOV(block, mem(&m_sh2_state->sr), I0); // mov m_sh2_state->sr, r0
return TRUE;
case 9<< 8: // BT(opcode & 0xff);
- UML_TEST(block, mem(&sh2->sr), T); // test sh2->sr, T
+ UML_TEST(block, mem(&m_sh2_state->sr), T); // test m_sh2_state->sr, T
UML_JMPc(block, COND_Z, compiler->labelnum); // jz compiler->labelnum
disp = ((INT32)opcode << 24) >> 24;
- sh2->ea = (desc->pc + 2) + disp * 2 + 2; // sh2->ea = destination
+ m_sh2_state->ea = (desc->pc + 2) + disp * 2 + 2; // m_sh2_state->ea = destination
- generate_update_cycles(sh2, block, compiler, sh2->ea, TRUE); // <subtract cycles>
- UML_HASHJMP(block, 0, sh2->ea, *sh2->nocode); // jmp sh2->ea
+ generate_update_cycles(block, compiler, m_sh2_state->ea, TRUE); // <subtract cycles>
+ UML_HASHJMP(block, 0, m_sh2_state->ea, *m_nocode); // jmp m_sh2_state->ea
UML_LABEL(block, compiler->labelnum++); // labelnum:
return TRUE;
case 11<< 8: // BF(opcode & 0xff);
- UML_TEST(block, mem(&sh2->sr), T); // test sh2->sr, T
+ UML_TEST(block, mem(&m_sh2_state->sr), T); // test m_sh2_state->sr, T
UML_JMPc(block, COND_NZ, compiler->labelnum); // jnz compiler->labelnum
disp = ((INT32)opcode << 24) >> 24;
- sh2->ea = (desc->pc + 2) + disp * 2 + 2; // sh2->ea = destination
+ m_sh2_state->ea = (desc->pc + 2) + disp * 2 + 2; // m_sh2_state->ea = destination
- generate_update_cycles(sh2, block, compiler, sh2->ea, TRUE); // <subtract cycles>
- UML_HASHJMP(block, 0, sh2->ea, *sh2->nocode); // jmp sh2->ea
+ generate_update_cycles(block, compiler, m_sh2_state->ea, TRUE); // <subtract cycles>
+ UML_HASHJMP(block, 0, m_sh2_state->ea, *m_nocode); // jmp m_sh2_state->ea
UML_LABEL(block, compiler->labelnum++); // labelnum:
return TRUE;
case 13<< 8: // BTS(opcode & 0xff);
- if (sh2->cpu_type > CPU_TYPE_SH1)
+ if (m_cpu_type > CPU_TYPE_SH1)
{
- UML_TEST(block, mem(&sh2->sr), T); // test sh2->sr, T
+ UML_TEST(block, mem(&m_sh2_state->sr), T); // test m_sh2_state->sr, T
UML_JMPc(block, COND_Z, compiler->labelnum); // jz compiler->labelnum
disp = ((INT32)opcode << 24) >> 24;
- sh2->ea = (desc->pc + 2) + disp * 2 + 2; // sh2->ea = destination
+ m_sh2_state->ea = (desc->pc + 2) + disp * 2 + 2; // m_sh2_state->ea = destination
templabel = compiler->labelnum; // save our label
compiler->labelnum++; // make sure the delay slot doesn't use it
- generate_delay_slot(sh2, block, compiler, desc, sh2->ea-2);
+ generate_delay_slot(block, compiler, desc, m_sh2_state->ea-2);
- generate_update_cycles(sh2, block, compiler, sh2->ea, TRUE); // <subtract cycles>
- UML_HASHJMP(block, 0, sh2->ea, *sh2->nocode); // jmp sh2->ea
+ generate_update_cycles(block, compiler, m_sh2_state->ea, TRUE); // <subtract cycles>
+ UML_HASHJMP(block, 0, m_sh2_state->ea, *m_nocode); // jmp m_sh2_state->ea
UML_LABEL(block, templabel); // labelnum:
return TRUE;
@@ -2964,20 +2745,20 @@ static int generate_group_8(sh2_state *sh2, drcuml_block *block, compiler_state
break;
case 15<< 8: // BFS(opcode & 0xff);
- if (sh2->cpu_type > CPU_TYPE_SH1)
+ if (m_cpu_type > CPU_TYPE_SH1)
{
- UML_TEST(block, mem(&sh2->sr), T); // test sh2->sr, T
+ UML_TEST(block, mem(&m_sh2_state->sr), T); // test m_sh2_state->sr, T
UML_JMPc(block, COND_NZ, compiler->labelnum); // jnz compiler->labelnum
disp = ((INT32)opcode << 24) >> 24;
- sh2->ea = (desc->pc + 2) + disp * 2 + 2; // sh2->ea = destination
+ m_sh2_state->ea = (desc->pc + 2) + disp * 2 + 2; // m_sh2_state->ea = destination
templabel = compiler->labelnum; // save our label
compiler->labelnum++; // make sure the delay slot doesn't use it
- generate_delay_slot(sh2, block, compiler, desc, sh2->ea-2); // delay slot only if the branch is taken
+ generate_delay_slot(block, compiler, desc, m_sh2_state->ea-2); // delay slot only if the branch is taken
- generate_update_cycles(sh2, block, compiler, sh2->ea, TRUE); // <subtract cycles>
- UML_HASHJMP(block, 0, sh2->ea, *sh2->nocode); // jmp sh2->ea
+ generate_update_cycles(block, compiler, m_sh2_state->ea, TRUE); // <subtract cycles>
+ UML_HASHJMP(block, 0, m_sh2_state->ea, *m_nocode); // jmp m_sh2_state->ea
UML_LABEL(block, templabel); // labelnum:
return TRUE;
@@ -2988,7 +2769,7 @@ static int generate_group_8(sh2_state *sh2, drcuml_block *block, compiler_state
return FALSE;
}
-static int generate_group_12(sh2_state *sh2, drcuml_block *block, compiler_state *compiler, const opcode_desc *desc, UINT16 opcode, int in_delay_slot, UINT32 ovrpc)
+int sh2_device::generate_group_12(drcuml_block *block, compiler_state *compiler, const opcode_desc *desc, UINT16 opcode, int in_delay_slot, UINT32 ovrpc)
{
UINT32 scratch;
@@ -2996,82 +2777,82 @@ static int generate_group_12(sh2_state *sh2, drcuml_block *block, compiler_state
{
case 0<<8: // MOVBSG(opcode & 0xff);
scratch = (opcode & 0xff);
- UML_ADD(block, I0, mem(&sh2->gbr), scratch); // add r0, gbr, scratch
+ UML_ADD(block, I0, mem(&m_sh2_state->gbr), scratch); // add r0, gbr, scratch
UML_AND(block, I1, R32(0), 0xff); // and r1, R0, 0xff
- UML_CALLH(block, *sh2->write8); // call write8
+ UML_CALLH(block, *m_write8); // call write8
if (!in_delay_slot)
- generate_update_cycles(sh2, block, compiler, desc->pc + 2, TRUE);
+ generate_update_cycles(block, compiler, desc->pc + 2, TRUE);
return TRUE;
case 1<<8: // MOVWSG(opcode & 0xff);
scratch = (opcode & 0xff) * 2;
- UML_ADD(block, I0, mem(&sh2->gbr), scratch); // add r0, gbr, scratch
+ UML_ADD(block, I0, mem(&m_sh2_state->gbr), scratch); // add r0, gbr, scratch
UML_AND(block, I1, R32(0), 0xffff); // and r1, R0, 0xffff
- UML_CALLH(block, *sh2->write16); // call write16
+ UML_CALLH(block, *m_write16); // call write16
if (!in_delay_slot)
- generate_update_cycles(sh2, block, compiler, desc->pc + 2, TRUE);
+ generate_update_cycles(block, compiler, desc->pc + 2, TRUE);
return TRUE;
case 2<<8: // MOVLSG(opcode & 0xff);
scratch = (opcode & 0xff) * 4;
- UML_ADD(block, I0, mem(&sh2->gbr), scratch); // add r0, gbr, scratch
+ UML_ADD(block, I0, mem(&m_sh2_state->gbr), scratch); // add r0, gbr, scratch
UML_MOV(block, I1, R32(0)); // mov r1, R0
- UML_CALLH(block, *sh2->write32); // call write32
+ UML_CALLH(block, *m_write32); // call write32
if (!in_delay_slot)
- generate_update_cycles(sh2, block, compiler, desc->pc + 2, TRUE);
+ generate_update_cycles(block, compiler, desc->pc + 2, TRUE);
return TRUE;
case 3<<8: // TRAPA(opcode & 0xff);
scratch = (opcode & 0xff) * 4;
- UML_ADD(block, mem(&sh2->ea), mem(&sh2->vbr), scratch); // add ea, vbr, scratch
+ UML_ADD(block, mem(&m_sh2_state->ea), mem(&m_sh2_state->vbr), scratch); // add ea, vbr, scratch
UML_SUB(block, R32(15), R32(15), 4); // sub R15, R15, #4
UML_MOV(block, I0, R32(15)); // mov r0, R15
- UML_MOV(block, I1, mem(&sh2->sr)); // mov r1, sr
- UML_CALLH(block, *sh2->write32); // write32
+ UML_MOV(block, I1, mem(&m_sh2_state->sr)); // mov r1, sr
+ UML_CALLH(block, *m_write32); // write32
UML_SUB(block, R32(15), R32(15), 4); // sub R15, R15, #4
UML_MOV(block, I0, R32(15)); // mov r0, R15
UML_MOV(block, I1, desc->pc+2); // mov r1, pc+2
- UML_CALLH(block, *sh2->write32); // write32
+ UML_CALLH(block, *m_write32); // write32
- UML_MOV(block, I0, mem(&sh2->ea)); // mov r0, ea
- UML_CALLH(block, *sh2->read32); // read32
- UML_HASHJMP(block, 0, I0, *sh2->nocode); // jmp (r0)
+ UML_MOV(block, I0, mem(&m_sh2_state->ea)); // mov r0, ea
+ UML_CALLH(block, *m_read32); // read32
+ UML_HASHJMP(block, 0, I0, *m_nocode); // jmp (r0)
return TRUE;
case 4<<8: // MOVBLG(opcode & 0xff);
scratch = (opcode & 0xff);
- UML_ADD(block, I0, mem(&sh2->gbr), scratch); // add r0, gbr, scratch
- UML_CALLH(block, *sh2->read8); // call read16
+ UML_ADD(block, I0, mem(&m_sh2_state->gbr), scratch); // add r0, gbr, scratch
+ UML_CALLH(block, *m_read8); // call read16
UML_SEXT(block, R32(0), I0, SIZE_BYTE); // sext R0, r0, BYTE
if (!in_delay_slot)
- generate_update_cycles(sh2, block, compiler, desc->pc + 2, TRUE);
+ generate_update_cycles(block, compiler, desc->pc + 2, TRUE);
return TRUE;
case 5<<8: // MOVWLG(opcode & 0xff);
scratch = (opcode & 0xff) * 2;
- UML_ADD(block, I0, mem(&sh2->gbr), scratch); // add r0, gbr, scratch
- UML_CALLH(block, *sh2->read16); // call read16
+ UML_ADD(block, I0, mem(&m_sh2_state->gbr), scratch); // add r0, gbr, scratch
+ UML_CALLH(block, *m_read16); // call read16
UML_SEXT(block, R32(0), I0, SIZE_WORD); // sext R0, r0, WORD
if (!in_delay_slot)
- generate_update_cycles(sh2, block, compiler, desc->pc + 2, TRUE);
+ generate_update_cycles(block, compiler, desc->pc + 2, TRUE);
return TRUE;
case 6<<8: // MOVLLG(opcode & 0xff);
scratch = (opcode & 0xff) * 4;
- UML_ADD(block, I0, mem(&sh2->gbr), scratch); // add r0, gbr, scratch
- UML_CALLH(block, *sh2->read32); // call read32
+ UML_ADD(block, I0, mem(&m_sh2_state->gbr), scratch); // add r0, gbr, scratch
+ UML_CALLH(block, *m_read32); // call read32
UML_MOV(block, R32(0), I0); // mov R0, r0
if (!in_delay_slot)
- generate_update_cycles(sh2, block, compiler, desc->pc + 2, TRUE);
+ generate_update_cycles(block, compiler, desc->pc + 2, TRUE);
return TRUE;
case 7<<8: // MOVA(opcode & 0xff);
@@ -3084,12 +2865,12 @@ static int generate_group_12(sh2_state *sh2, drcuml_block *block, compiler_state
case 8<<8: // TSTI(opcode & 0xff);
scratch = opcode & 0xff;
- UML_AND(block, mem(&sh2->sr), mem(&sh2->sr), ~T); // and sr, sr, ~T (clear the T bit)
+ UML_AND(block, mem(&m_sh2_state->sr), mem(&m_sh2_state->sr), ~T); // and sr, sr, ~T (clear the T bit)
UML_AND(block, I0, R32(0), scratch); // and r0, R0, scratch
UML_CMP(block, I0, 0); // cmp r0, #0
UML_JMPc(block, COND_NZ, compiler->labelnum); // jnz labelnum
- UML_OR(block, mem(&sh2->sr), mem(&sh2->sr), T); // or sr, sr, T
+ UML_OR(block, mem(&m_sh2_state->sr), mem(&m_sh2_state->sr), T); // or sr, sr, T
UML_LABEL(block, compiler->labelnum++); // labelnum:
return TRUE;
@@ -3107,47 +2888,47 @@ static int generate_group_12(sh2_state *sh2, drcuml_block *block, compiler_state
return TRUE;
case 12<<8: // TSTM(opcode & 0xff);
- UML_AND(block, mem(&sh2->sr), mem(&sh2->sr), ~T); // and sr, sr, ~T (clear the T bit)
- UML_ADD(block, I0, R32(0), mem(&sh2->gbr)); // add r0, R0, gbr
- UML_CALLH(block, *sh2->read8); // read8
+ UML_AND(block, mem(&m_sh2_state->sr), mem(&m_sh2_state->sr), ~T); // and sr, sr, ~T (clear the T bit)
+ UML_ADD(block, I0, R32(0), mem(&m_sh2_state->gbr)); // add r0, R0, gbr
+ UML_CALLH(block, *m_read8); // read8
UML_AND(block, I0, I0, opcode & 0xff);
UML_CMP(block, I0, 0); // cmp r0, #0
UML_JMPc(block, COND_NZ, compiler->labelnum); // jnz labelnum
- UML_OR(block, mem(&sh2->sr), mem(&sh2->sr), T); // or sr, sr, T
+ UML_OR(block, mem(&m_sh2_state->sr), mem(&m_sh2_state->sr), T); // or sr, sr, T
UML_LABEL(block, compiler->labelnum++); // labelnum:
return TRUE;
case 13<<8: // ANDM(opcode & 0xff);
- UML_ADD(block, I0, R32(0), mem(&sh2->gbr)); // add r0, R0, gbr
- UML_CALLH(block, *sh2->read8); // read8
+ UML_ADD(block, I0, R32(0), mem(&m_sh2_state->gbr)); // add r0, R0, gbr
+ UML_CALLH(block, *m_read8); // read8
UML_AND(block, I1, I0, opcode&0xff); // and r1, r0, #opcode&0xff
- UML_ADD(block, I0, R32(0), mem(&sh2->gbr)); // add r0, R0, gbr
+ UML_ADD(block, I0, R32(0), mem(&m_sh2_state->gbr)); // add r0, R0, gbr
SETEA(0);
- UML_CALLH(block, *sh2->write8); // write8
+ UML_CALLH(block, *m_write8); // write8
return TRUE;
case 14<<8: // XORM(opcode & 0xff);
- UML_ADD(block, I0, R32(0), mem(&sh2->gbr)); // add r0, R0, gbr
- UML_CALLH(block, *sh2->read8); // read8
+ UML_ADD(block, I0, R32(0), mem(&m_sh2_state->gbr)); // add r0, R0, gbr
+ UML_CALLH(block, *m_read8); // read8
UML_XOR(block, I1, I0, opcode&0xff); // xor r1, r0, #opcode&0xff
- UML_ADD(block, I0, R32(0), mem(&sh2->gbr)); // add r0, R0, gbr
+ UML_ADD(block, I0, R32(0), mem(&m_sh2_state->gbr)); // add r0, R0, gbr
SETEA(0);
- UML_CALLH(block, *sh2->write8); // write8
+ UML_CALLH(block, *m_write8); // write8
return TRUE;
case 15<<8: // ORM(opcode & 0xff);
- UML_ADD(block, I0, R32(0), mem(&sh2->gbr)); // add r0, R0, gbr
- UML_CALLH(block, *sh2->read8); // read8
+ UML_ADD(block, I0, R32(0), mem(&m_sh2_state->gbr)); // add r0, R0, gbr
+ UML_CALLH(block, *m_read8); // read8
UML_OR(block, I1, I0, opcode&0xff); // or r1, r0, #opcode&0xff
- UML_ADD(block, I0, R32(0), mem(&sh2->gbr)); // add r0, R0, gbr
+ UML_ADD(block, I0, R32(0), mem(&m_sh2_state->gbr)); // add r0, R0, gbr
SETEA(0);
- UML_CALLH(block, *sh2->write8); // write8
+ UML_CALLH(block, *m_write8); // write8
return TRUE;
}
@@ -3162,11 +2943,10 @@ static int generate_group_12(sh2_state *sh2, drcuml_block *block, compiler_state
sh2drc_set_options - configure DRC options
-------------------------------------------------*/
-void sh2drc_set_options(device_t *device, UINT32 options)
+void sh2_device::sh2drc_set_options(UINT32 options)
{
- if (!device->machine().options().drc()) return;
- sh2_state *sh2 = get_safe_token(device);
- sh2->drcoptions = options;
+ if (!machine().options().drc()) return;
+ m_drcoptions = options;
}
@@ -3175,13 +2955,12 @@ void sh2drc_set_options(device_t *device, UINT32 options)
the PC must be flushed for speedups to work
-------------------------------------------------*/
-void sh2drc_add_pcflush(device_t *device, offs_t address)
+void sh2_device::sh2drc_add_pcflush(offs_t address)
{
- if (!device->machine().options().drc()) return;
- sh2_state *sh2 = get_safe_token(device);
+ if (!machine().options().drc()) return;
- if (sh2->pcfsel < ARRAY_LENGTH(sh2->pcflushes))
- sh2->pcflushes[sh2->pcfsel++] = address;
+ if (m_pcfsel < ARRAY_LENGTH(m_pcflushes))
+ m_pcflushes[m_pcfsel++] = address;
}
@@ -3190,256 +2969,15 @@ void sh2drc_add_pcflush(device_t *device, offs_t address)
region
-------------------------------------------------*/
-void sh2drc_add_fastram(device_t *device, offs_t start, offs_t end, UINT8 readonly, void *base)
+void sh2_device::sh2drc_add_fastram(offs_t start, offs_t end, UINT8 readonly, void *base)
{
- sh2_state *sh2 = get_safe_token(device);
- if (sh2->fastram_select < ARRAY_LENGTH(sh2->fastram))
+ if (m_fastram_select < ARRAY_LENGTH(m_fastram))
{
- sh2->fastram[sh2->fastram_select].start = start;
- sh2->fastram[sh2->fastram_select].end = end;
- sh2->fastram[sh2->fastram_select].readonly = readonly;
- sh2->fastram[sh2->fastram_select].base = base;
- sh2->fastram_select++;
- }
-}
-
-/*-------------------------------------------------
- sh2_internal_a5 - read handler for
- SH2 internal map
--------------------------------------------------*/
-
-static READ32_HANDLER(sh2_internal_a5)
-{
- return 0xa5a5a5a5;
-}
-
-
-/*-------------------------------------------------
- sh2_internal_map - maps SH2 built-ins
--------------------------------------------------*/
-
-static ADDRESS_MAP_START( sh2_internal_map, AS_PROGRAM, 32, legacy_cpu_device )
- AM_RANGE(0x40000000, 0xbfffffff) AM_READ_LEGACY(sh2_internal_a5)
- AM_RANGE(0xe0000000, 0xffffffff) AM_READWRITE_LEGACY(sh2_internal_r, sh2_internal_w)
-ADDRESS_MAP_END
-
-/*-------------------------------------------------
- sh2_set_info - set information about a given
- CPU instance
--------------------------------------------------*/
-
-static CPU_SET_INFO( sh2 )
-{
- sh2_state *sh2 = get_safe_token(device);
- switch (state)
- {
- /* --- the following bits of info are set as 64-bit signed integers --- */
- case CPUINFO_INT_INPUT_STATE + SH2_INT_VBLIN: sh2_set_irq_line(sh2, SH2_INT_VBLIN, info->i); break;
- case CPUINFO_INT_INPUT_STATE + SH2_INT_VBLOUT: sh2_set_irq_line(sh2, SH2_INT_VBLOUT, info->i); break;
- case CPUINFO_INT_INPUT_STATE + SH2_INT_HBLIN: sh2_set_irq_line(sh2, SH2_INT_HBLIN, info->i); break;
- case CPUINFO_INT_INPUT_STATE + SH2_INT_TIMER0: sh2_set_irq_line(sh2, SH2_INT_TIMER0, info->i); break;
- case CPUINFO_INT_INPUT_STATE + SH2_INT_TIMER1: sh2_set_irq_line(sh2, SH2_INT_TIMER1, info->i); break;
- case CPUINFO_INT_INPUT_STATE + SH2_INT_DSP: sh2_set_irq_line(sh2, SH2_INT_DSP, info->i); break;
- case CPUINFO_INT_INPUT_STATE + SH2_INT_SOUND: sh2_set_irq_line(sh2, SH2_INT_SOUND, info->i); break;
- case CPUINFO_INT_INPUT_STATE + SH2_INT_SMPC: sh2_set_irq_line(sh2, SH2_INT_SMPC, info->i); break;
- case CPUINFO_INT_INPUT_STATE + SH2_INT_PAD: sh2_set_irq_line(sh2, SH2_INT_PAD, info->i); break;
- case CPUINFO_INT_INPUT_STATE + SH2_INT_DMA2: sh2_set_irq_line(sh2, SH2_INT_DMA2, info->i); break;
- case CPUINFO_INT_INPUT_STATE + SH2_INT_DMA1: sh2_set_irq_line(sh2, SH2_INT_DMA1, info->i); break;
- case CPUINFO_INT_INPUT_STATE + SH2_INT_DMA0: sh2_set_irq_line(sh2, SH2_INT_DMA0, info->i); break;
- case CPUINFO_INT_INPUT_STATE + SH2_INT_DMAILL: sh2_set_irq_line(sh2, SH2_INT_DMAILL, info->i); break;
- case CPUINFO_INT_INPUT_STATE + SH2_INT_SPRITE: sh2_set_irq_line(sh2, SH2_INT_SPRITE, info->i); break;
- case CPUINFO_INT_INPUT_STATE + SH2_INT_14: sh2_set_irq_line(sh2, SH2_INT_14, info->i); break;
- case CPUINFO_INT_INPUT_STATE + SH2_INT_15: sh2_set_irq_line(sh2, SH2_INT_15, info->i); break;
- case CPUINFO_INT_INPUT_STATE + SH2_INT_ABUS: sh2_set_irq_line(sh2, SH2_INT_ABUS, info->i); break;
- case CPUINFO_INT_INPUT_STATE + INPUT_LINE_NMI: sh2_set_irq_line(sh2, INPUT_LINE_NMI, info->i); break;
-
- case CPUINFO_INT_REGISTER + SH2_PC:
- case CPUINFO_INT_PC: sh2->pc = info->i; sh2->delay = 0; break;
- case CPUINFO_INT_SP: sh2->r[15] = info->i; break;
- case CPUINFO_INT_REGISTER + SH2_PR: sh2->pr = info->i; break;
- case CPUINFO_INT_REGISTER + SH2_SR: sh2->sr = info->i; break;
- case CPUINFO_INT_REGISTER + SH2_GBR: sh2->gbr = info->i; break;
- case CPUINFO_INT_REGISTER + SH2_VBR: sh2->vbr = info->i; break;
- case CPUINFO_INT_REGISTER + SH2_MACH: sh2->mach = info->i; break;
- case CPUINFO_INT_REGISTER + SH2_MACL: sh2->macl = info->i; break;
- case CPUINFO_INT_REGISTER + SH2_R0: sh2->r[ 0] = info->i; break;
- case CPUINFO_INT_REGISTER + SH2_R1: sh2->r[ 1] = info->i; break;
- case CPUINFO_INT_REGISTER + SH2_R2: sh2->r[ 2] = info->i; break;
- case CPUINFO_INT_REGISTER + SH2_R3: sh2->r[ 3] = info->i; break;
- case CPUINFO_INT_REGISTER + SH2_R4: sh2->r[ 4] = info->i; break;
- case CPUINFO_INT_REGISTER + SH2_R5: sh2->r[ 5] = info->i; break;
- case CPUINFO_INT_REGISTER + SH2_R6: sh2->r[ 6] = info->i; break;
- case CPUINFO_INT_REGISTER + SH2_R7: sh2->r[ 7] = info->i; break;
- case CPUINFO_INT_REGISTER + SH2_R8: sh2->r[ 8] = info->i; break;
- case CPUINFO_INT_REGISTER + SH2_R9: sh2->r[ 9] = info->i; break;
- case CPUINFO_INT_REGISTER + SH2_R10: sh2->r[10] = info->i; break;
- case CPUINFO_INT_REGISTER + SH2_R11: sh2->r[11] = info->i; break;
- case CPUINFO_INT_REGISTER + SH2_R12: sh2->r[12] = info->i; break;
- case CPUINFO_INT_REGISTER + SH2_R13: sh2->r[13] = info->i; break;
- case CPUINFO_INT_REGISTER + SH2_R14: sh2->r[14] = info->i; break;
- case CPUINFO_INT_REGISTER + SH2_R15: sh2->r[15] = info->i; break;
- case CPUINFO_INT_REGISTER + SH2_EA: sh2->ea = info->i; break;
- }
-}
-
-/*-------------------------------------------------
- sh2_get_info - return information about a
- given CPU instance
--------------------------------------------------*/
-
-CPU_GET_INFO( sh2_drc )
-{
- sh2_state *sh2 = (device != NULL && device->token() != NULL) ? get_safe_token(device) : NULL;
- switch (state)
- {
- /* --- the following bits of info are returned as 64-bit signed integers --- */
- case CPUINFO_INT_CONTEXT_SIZE: info->i = sizeof(sh2_state *); break;
- case CPUINFO_INT_INPUT_LINES: info->i = 16; break;
- case CPUINFO_INT_DEFAULT_IRQ_VECTOR: info->i = 0; break;
- case CPUINFO_INT_ENDIANNESS: info->i = ENDIANNESS_BIG; break;
- case CPUINFO_INT_CLOCK_MULTIPLIER: info->i = 1; break;
- case CPUINFO_INT_CLOCK_DIVIDER: info->i = 1; break;
- case CPUINFO_INT_MIN_INSTRUCTION_BYTES: info->i = 2; break;
- case CPUINFO_INT_MAX_INSTRUCTION_BYTES: info->i = 2; break;
- case CPUINFO_INT_MIN_CYCLES: info->i = 1; break;
- case CPUINFO_INT_MAX_CYCLES: info->i = 4; break;
-
- case CPUINFO_INT_DATABUS_WIDTH + AS_PROGRAM: info->i = 32; break;
- case CPUINFO_INT_ADDRBUS_WIDTH + AS_PROGRAM: info->i = 32; break;
- case CPUINFO_INT_ADDRBUS_SHIFT + AS_PROGRAM: info->i = 0; break;
- case CPUINFO_INT_DATABUS_WIDTH + AS_DATA: info->i = 0; break;
- case CPUINFO_INT_ADDRBUS_WIDTH + AS_DATA: info->i = 0; break;
- case CPUINFO_INT_ADDRBUS_SHIFT + AS_DATA: info->i = 0; break;
- case CPUINFO_INT_DATABUS_WIDTH + AS_IO: info->i = 0; break;
- case CPUINFO_INT_ADDRBUS_WIDTH + AS_IO: info->i = 0; break;
- case CPUINFO_INT_ADDRBUS_SHIFT + AS_IO: info->i = 0; break;
-
- // Internal maps
- case CPUINFO_PTR_INTERNAL_MEMORY_MAP + AS_PROGRAM: info->internal_map32 = ADDRESS_MAP_NAME(sh2_internal_map); break;
- case CPUINFO_PTR_INTERNAL_MEMORY_MAP + AS_DATA: info->internal_map32 = NULL; break;
- case CPUINFO_PTR_INTERNAL_MEMORY_MAP + AS_IO: info->internal_map32 = NULL; break;
-
- case CPUINFO_INT_INPUT_STATE + SH2_INT_VBLIN: info->i = sh2->irq_line_state[SH2_INT_VBLIN]; break;
- case CPUINFO_INT_INPUT_STATE + SH2_INT_VBLOUT: info->i = sh2->irq_line_state[SH2_INT_VBLOUT]; break;
- case CPUINFO_INT_INPUT_STATE + SH2_INT_HBLIN: info->i = sh2->irq_line_state[SH2_INT_HBLIN]; break;
- case CPUINFO_INT_INPUT_STATE + SH2_INT_TIMER0: info->i = sh2->irq_line_state[SH2_INT_TIMER0]; break;
- case CPUINFO_INT_INPUT_STATE + SH2_INT_TIMER1: info->i = sh2->irq_line_state[SH2_INT_TIMER1]; break;
- case CPUINFO_INT_INPUT_STATE + SH2_INT_DSP: info->i = sh2->irq_line_state[SH2_INT_DSP]; break;
- case CPUINFO_INT_INPUT_STATE + SH2_INT_SOUND: info->i = sh2->irq_line_state[SH2_INT_SOUND]; break;
- case CPUINFO_INT_INPUT_STATE + SH2_INT_SMPC: info->i = sh2->irq_line_state[SH2_INT_SMPC]; break;
- case CPUINFO_INT_INPUT_STATE + SH2_INT_PAD: info->i = sh2->irq_line_state[SH2_INT_PAD]; break;
- case CPUINFO_INT_INPUT_STATE + SH2_INT_DMA2: info->i = sh2->irq_line_state[SH2_INT_DMA2]; break;
- case CPUINFO_INT_INPUT_STATE + SH2_INT_DMA1: info->i = sh2->irq_line_state[SH2_INT_DMA1]; break;
- case CPUINFO_INT_INPUT_STATE + SH2_INT_DMA0: info->i = sh2->irq_line_state[SH2_INT_DMA0]; break;
- case CPUINFO_INT_INPUT_STATE + SH2_INT_DMAILL: info->i = sh2->irq_line_state[SH2_INT_DMAILL]; break;
- case CPUINFO_INT_INPUT_STATE + SH2_INT_SPRITE: info->i = sh2->irq_line_state[SH2_INT_SPRITE]; break;
- case CPUINFO_INT_INPUT_STATE + SH2_INT_14: info->i = sh2->irq_line_state[SH2_INT_14]; break;
- case CPUINFO_INT_INPUT_STATE + SH2_INT_15: info->i = sh2->irq_line_state[SH2_INT_15]; break;
- case CPUINFO_INT_INPUT_STATE + SH2_INT_ABUS: info->i = sh2->irq_line_state[SH2_INT_ABUS]; break;
- case CPUINFO_INT_INPUT_STATE + INPUT_LINE_NMI: info->i = sh2->nmi_line_state; break;
-
- case CPUINFO_INT_PREVIOUSPC: info->i = sh2->ppc; break;
-
- case CPUINFO_INT_PC:
- case CPUINFO_INT_REGISTER + SH2_PC: info->i = (sh2->delay) ? (sh2->delay & AM) : (sh2->pc & AM); break;
- case CPUINFO_INT_SP: info->i = sh2->r[15]; break;
- case CPUINFO_INT_REGISTER + SH2_PR: info->i = sh2->pr; break;
- case CPUINFO_INT_REGISTER + SH2_SR: info->i = sh2->sr; break;
- case CPUINFO_INT_REGISTER + SH2_GBR: info->i = sh2->gbr; break;
- case CPUINFO_INT_REGISTER + SH2_VBR: info->i = sh2->vbr; break;
- case CPUINFO_INT_REGISTER + SH2_MACH: info->i = sh2->mach; break;
- case CPUINFO_INT_REGISTER + SH2_MACL: info->i = sh2->macl; break;
- case CPUINFO_INT_REGISTER + SH2_R0: info->i = sh2->r[ 0]; break;
- case CPUINFO_INT_REGISTER + SH2_R1: info->i = sh2->r[ 1]; break;
- case CPUINFO_INT_REGISTER + SH2_R2: info->i = sh2->r[ 2]; break;
- case CPUINFO_INT_REGISTER + SH2_R3: info->i = sh2->r[ 3]; break;
- case CPUINFO_INT_REGISTER + SH2_R4: info->i = sh2->r[ 4]; break;
- case CPUINFO_INT_REGISTER + SH2_R5: info->i = sh2->r[ 5]; break;
- case CPUINFO_INT_REGISTER + SH2_R6: info->i = sh2->r[ 6]; break;
- case CPUINFO_INT_REGISTER + SH2_R7: info->i = sh2->r[ 7]; break;
- case CPUINFO_INT_REGISTER + SH2_R8: info->i = sh2->r[ 8]; break;
- case CPUINFO_INT_REGISTER + SH2_R9: info->i = sh2->r[ 9]; break;
- case CPUINFO_INT_REGISTER + SH2_R10: info->i = sh2->r[10]; break;
- case CPUINFO_INT_REGISTER + SH2_R11: info->i = sh2->r[11]; break;
- case CPUINFO_INT_REGISTER + SH2_R12: info->i = sh2->r[12]; break;
- case CPUINFO_INT_REGISTER + SH2_R13: info->i = sh2->r[13]; break;
- case CPUINFO_INT_REGISTER + SH2_R14: info->i = sh2->r[14]; break;
- case CPUINFO_INT_REGISTER + SH2_R15: info->i = sh2->r[15]; break;
- case CPUINFO_INT_REGISTER + SH2_EA: info->i = sh2->ea; break;
-
- /* --- the following bits of info are returned as pointers to data or functions --- */
- case CPUINFO_FCT_SET_INFO: info->setinfo = CPU_SET_INFO_NAME(sh2); break;
- case CPUINFO_FCT_INIT: info->init = CPU_INIT_NAME(sh2); break;
- case CPUINFO_FCT_RESET: info->reset = CPU_RESET_NAME(sh2); break;
- case CPUINFO_FCT_EXIT: info->exit = CPU_EXIT_NAME(sh2); break;
- case CPUINFO_FCT_EXECUTE: info->execute = CPU_EXECUTE_NAME(sh2); break;
- case CPUINFO_FCT_BURN: info->burn = NULL; break;
- case CPUINFO_FCT_DISASSEMBLE: info->disassemble = CPU_DISASSEMBLE_NAME(sh2); break;
- case CPUINFO_PTR_INSTRUCTION_COUNTER: info->icount = &sh2->icount; break;
-
- /* --- the following bits of info are returned as NULL-terminated strings --- */
- case CPUINFO_STR_NAME: strcpy(info->s, "SH-2 DRC"); break;
- case CPUINFO_STR_SHORTNAME: strcpy(info->s, "sh2_drc"); break;
- case CPUINFO_STR_FAMILY: strcpy(info->s, "Hitachi SuperH RISC"); break;
- case CPUINFO_STR_VERSION: strcpy(info->s, "2.0"); break;
- case CPUINFO_STR_SOURCE_FILE: strcpy(info->s, __FILE__); break;
- case CPUINFO_STR_CREDITS: strcpy(info->s, "Copyright Nicola Salmoria and the MAME team, all rights reserved."); break;
-
- case CPUINFO_STR_FLAGS:
- sprintf(info->s, "%c%c%d%c%c",
- sh2->sr & M ? 'M':'.',
- sh2->sr & Q ? 'Q':'.',
- (sh2->sr & I) >> 4,
- sh2->sr & S ? 'S':'.',
- sh2->sr & T ? 'T':'.');
- break;
-
- case CPUINFO_STR_REGISTER + SH2_PC: sprintf(info->s, "PC :%08X", sh2->pc); break;
- case CPUINFO_STR_REGISTER + SH2_SR: sprintf(info->s, "SR :%08X", sh2->sr); break;
- case CPUINFO_STR_REGISTER + SH2_PR: sprintf(info->s, "PR :%08X", sh2->pr); break;
- case CPUINFO_STR_REGISTER + SH2_GBR: sprintf(info->s, "GBR :%08X", sh2->gbr); break;
- case CPUINFO_STR_REGISTER + SH2_VBR: sprintf(info->s, "VBR :%08X", sh2->vbr); break;
- case CPUINFO_STR_REGISTER + SH2_MACH: sprintf(info->s, "MACH:%08X", sh2->mach); break;
- case CPUINFO_STR_REGISTER + SH2_MACL: sprintf(info->s, "MACL:%08X", sh2->macl); break;
- case CPUINFO_STR_REGISTER + SH2_R0: sprintf(info->s, "R0 :%08X", sh2->r[ 0]); break;
- case CPUINFO_STR_REGISTER + SH2_R1: sprintf(info->s, "R1 :%08X", sh2->r[ 1]); break;
- case CPUINFO_STR_REGISTER + SH2_R2: sprintf(info->s, "R2 :%08X", sh2->r[ 2]); break;
- case CPUINFO_STR_REGISTER + SH2_R3: sprintf(info->s, "R3 :%08X", sh2->r[ 3]); break;
- case CPUINFO_STR_REGISTER + SH2_R4: sprintf(info->s, "R4 :%08X", sh2->r[ 4]); break;
- case CPUINFO_STR_REGISTER + SH2_R5: sprintf(info->s, "R5 :%08X", sh2->r[ 5]); break;
- case CPUINFO_STR_REGISTER + SH2_R6: sprintf(info->s, "R6 :%08X", sh2->r[ 6]); break;
- case CPUINFO_STR_REGISTER + SH2_R7: sprintf(info->s, "R7 :%08X", sh2->r[ 7]); break;
- case CPUINFO_STR_REGISTER + SH2_R8: sprintf(info->s, "R8 :%08X", sh2->r[ 8]); break;
- case CPUINFO_STR_REGISTER + SH2_R9: sprintf(info->s, "R9 :%08X", sh2->r[ 9]); break;
- case CPUINFO_STR_REGISTER + SH2_R10: sprintf(info->s, "R10 :%08X", sh2->r[10]); break;
- case CPUINFO_STR_REGISTER + SH2_R11: sprintf(info->s, "R11 :%08X", sh2->r[11]); break;
- case CPUINFO_STR_REGISTER + SH2_R12: sprintf(info->s, "R12 :%08X", sh2->r[12]); break;
- case CPUINFO_STR_REGISTER + SH2_R13: sprintf(info->s, "R13 :%08X", sh2->r[13]); break;
- case CPUINFO_STR_REGISTER + SH2_R14: sprintf(info->s, "R14 :%08X", sh2->r[14]); break;
- case CPUINFO_STR_REGISTER + SH2_R15: sprintf(info->s, "R15 :%08X", sh2->r[15]); break;
- case CPUINFO_STR_REGISTER + SH2_EA: sprintf(info->s, "EA :%08X", sh2->ea); break;
- }
-}
-
-/*-------------------------------------------------
- sh1_get_info - return information about a
- given CPU instance
--------------------------------------------------*/
-
-CPU_GET_INFO( sh1_drc )
-{
- switch (state)
- {
- /* --- the following bits of info are returned as pointers to data or functions --- */
- case CPUINFO_FCT_RESET: info->reset = CPU_RESET_NAME(sh1); break;
-
- /* --- the following bits of info are returned as NULL-terminated strings --- */
- case CPUINFO_STR_NAME: strcpy(info->s, "SH-1 DRC"); break;
- case CPUINFO_STR_SHORTNAME: strcpy(info->s, "sh1_drc"); break;
-
- default: CPU_GET_INFO_CALL(sh2_drc); break;
+ m_fastram[m_fastram_select].start = start;
+ m_fastram[m_fastram_select].end = end;
+ m_fastram[m_fastram_select].readonly = readonly;
+ m_fastram[m_fastram_select].base = base;
+ m_fastram_select++;
}
}
-DEFINE_LEGACY_CPU_DEVICE(SH1_DRC, sh1_drc);
-DEFINE_LEGACY_CPU_DEVICE(SH2_DRC, sh2_drc);
diff --git a/src/emu/cpu/sh2/sh2fe.c b/src/emu/cpu/sh2/sh2fe.c
index c79b27cd456..9cc2be5c048 100644
--- a/src/emu/cpu/sh2/sh2fe.c
+++ b/src/emu/cpu/sh2/sh2fe.c
@@ -13,13 +13,14 @@
#include "sh2comn.h"
#include "cpu/drcfe.h"
+
/***************************************************************************
INSTRUCTION PARSERS
***************************************************************************/
-sh2_frontend::sh2_frontend(sh2_state &state, UINT32 window_start, UINT32 window_end, UINT32 max_sequence)
- : drc_frontend(*state.device, window_start, window_end, max_sequence),
- m_context(state)
+sh2_frontend::sh2_frontend(sh2_device *device, UINT32 window_start, UINT32 window_end, UINT32 max_sequence)
+ : drc_frontend(*device, window_start, window_end, max_sequence)
+ , m_sh2(device)
{
}
@@ -33,7 +34,7 @@ bool sh2_frontend::describe(opcode_desc &desc, const opcode_desc *prev)
UINT16 opcode;
/* fetch the opcode */
- opcode = desc.opptr.w[0] = m_context.direct->read_decrypted_word(desc.physpc, SH2_CODE_XOR(0));
+ opcode = desc.opptr.w[0] = m_sh2->m_direct->read_decrypted_word(desc.physpc, SH2_CODE_XOR(0));
/* all instructions are 2 bytes and most are a single cycle */
desc.length = 2;
diff --git a/src/emu/imagedev/floppy.c b/src/emu/imagedev/floppy.c
index 562a43b29e5..1eb1d5a1e40 100644
--- a/src/emu/imagedev/floppy.c
+++ b/src/emu/imagedev/floppy.c
@@ -16,7 +16,7 @@
*/
// Show step operation
-#define TRACE_STEP 0
+#define TRACE_STEP 1
// device type definition
const device_type FLOPPY_CONNECTOR = &device_creator<floppy_connector>;
@@ -759,7 +759,6 @@ void floppy_image_device::set_write_splice(attotime when)
attotime base;
int splice_pos = find_position(base, when);
image->set_write_splice_position(cyl, ss, splice_pos);
- logerror("%s: Track %d head %d set splice pos %d\n", tag(), cyl, ss, splice_pos);
}
UINT32 floppy_image_device::get_form_factor() const
diff --git a/src/emu/machine/6522via.c b/src/emu/machine/6522via.c
index a6316a75406..6c9f44361fa 100644
--- a/src/emu/machine/6522via.c
+++ b/src/emu/machine/6522via.c
@@ -842,6 +842,11 @@ void via6522_device::write_pa(int line, int state)
m_in_a &= ~(1 << line);
}
+WRITE8_MEMBER( via6522_device::write_pa )
+{
+ m_in_a = data;
+}
+
/*-------------------------------------------------
ca1_w - interface setting VIA port CA1 input
-------------------------------------------------*/
@@ -902,6 +907,11 @@ void via6522_device::write_pb(int line, int state)
m_in_b &= ~(1 << line);
}
+WRITE8_MEMBER( via6522_device::write_pb )
+{
+ m_in_b = data;
+}
+
/*-------------------------------------------------
cb1_w - interface setting VIA port CB1 input
-------------------------------------------------*/
diff --git a/src/emu/machine/6522via.h b/src/emu/machine/6522via.h
index 87f09277405..5b0f640fd5c 100644
--- a/src/emu/machine/6522via.h
+++ b/src/emu/machine/6522via.h
@@ -88,6 +88,7 @@ public:
DECLARE_WRITE_LINE_MEMBER( write_pa5 ) { write_pa(5, state); }
DECLARE_WRITE_LINE_MEMBER( write_pa6 ) { write_pa(6, state); }
DECLARE_WRITE_LINE_MEMBER( write_pa7 ) { write_pa(7, state); }
+ DECLARE_WRITE8_MEMBER( write_pa );
DECLARE_WRITE_LINE_MEMBER( write_ca1 );
DECLARE_WRITE_LINE_MEMBER( write_ca2 );
@@ -99,6 +100,7 @@ public:
DECLARE_WRITE_LINE_MEMBER( write_pb5 ) { write_pb(5, state); }
DECLARE_WRITE_LINE_MEMBER( write_pb6 ) { write_pb(6, state); }
DECLARE_WRITE_LINE_MEMBER( write_pb7 ) { write_pb(7, state); }
+ DECLARE_WRITE8_MEMBER( write_pb );
DECLARE_WRITE_LINE_MEMBER( write_cb1 );
DECLARE_WRITE_LINE_MEMBER( write_cb2 );
diff --git a/src/emu/machine/saturn.c b/src/emu/machine/saturn.c
index ea08344ccb1..66751a9eb7d 100644
--- a/src/emu/machine/saturn.c
+++ b/src/emu/machine/saturn.c
@@ -590,7 +590,7 @@ WRITE32_MEMBER(saturn_state::minit_w)
machine().scheduler().boost_interleave(m_minit_boost_timeslice, attotime::from_usec(m_minit_boost));
machine().scheduler().trigger(1000);
machine().scheduler().synchronize(); // force resync
- sh2_set_frt_input(m_slave, PULSE_LINE);
+ m_slave->sh2_set_frt_input(PULSE_LINE);
}
WRITE32_MEMBER(saturn_state::sinit_w)
@@ -598,7 +598,7 @@ WRITE32_MEMBER(saturn_state::sinit_w)
//logerror("cpu %s (PC=%08X) SINIT write = %08x\n", space.device().tag(), space.device().safe_pc(),data);
machine().scheduler().boost_interleave(m_sinit_boost_timeslice, attotime::from_usec(m_sinit_boost));
machine().scheduler().synchronize(); // force resync
- sh2_set_frt_input(m_maincpu, PULSE_LINE);
+ m_maincpu->sh2_set_frt_input(PULSE_LINE);
}
/*
@@ -631,7 +631,7 @@ WRITE32_MEMBER(saturn_state::saturn_minit_w)
machine().scheduler().trigger(1000);
}
- sh2_set_frt_input(m_slave, PULSE_LINE);
+ m_slave->sh2_set_frt_input(PULSE_LINE);
}
WRITE32_MEMBER(saturn_state::saturn_sinit_w)
@@ -642,7 +642,7 @@ WRITE32_MEMBER(saturn_state::saturn_sinit_w)
else
machine().scheduler().boost_interleave(m_sinit_boost_timeslice, attotime::from_usec(m_sinit_boost));
- sh2_set_frt_input(m_maincpu, PULSE_LINE);
+ m_maincpu->sh2_set_frt_input(PULSE_LINE);
}
diff --git a/src/emu/machine/wd_fdc.c b/src/emu/machine/wd_fdc.c
index c2dafac8e13..c83683b6361 100644
--- a/src/emu/machine/wd_fdc.c
+++ b/src/emu/machine/wd_fdc.c
@@ -38,7 +38,7 @@ const device_type WD1773x = &device_creator<wd1773_t>;
#define TRACE_COMP 0
// Shows command invocation
-#define TRACE_COMMAND 0
+#define TRACE_COMMAND 1
// Shows sync actions
#define TRACE_SYNC 0
@@ -223,7 +223,7 @@ void wd_fdc_t::command_end()
void wd_fdc_t::seek_start(int state)
{
- if (TRACE_COMMAND) logerror("%s: seek %d\n", tag(), data);
+ if (TRACE_COMMAND) logerror("%s: seek %d (track=%d)\n", tag(), data, track);
main_state = state;
status = (status & ~(S_CRC|S_RNF|S_SPIN)) | S_BUSY;
if(head_control) {
@@ -264,8 +264,10 @@ void wd_fdc_t::seek_continue()
delay_cycles(t_gen, step_times[command & 3]);
}
- if(main_state == SEEK && track == data)
+ if(main_state == SEEK && track == data) {
+ logerror("track=%d data=%d\n", track, data);
sub_state = SEEK_DONE;
+ }
if(sub_state == SPINUP_DONE) {
counter = 0;
@@ -1184,10 +1186,9 @@ void wd_fdc_t::spinup()
counter = 0;
}
- status |= S_MON;
+ status |= S_MON|S_SPIN;
if(floppy)
floppy->mon_w(0);
-
}
void wd_fdc_t::ready_callback(floppy_image_device *floppy, int state)
@@ -2669,7 +2670,7 @@ wd1770_t::wd1770_t(const machine_config &mconfig, const char *tag, device_t *own
{
step_times = wd_digital_step_times;
delay_register_commit = 32;
- delay_command_commit = 48;
+ delay_command_commit = 36; // official 48 is too high for oric jasmin boot
disable_mfm = false;
inverted_bus = false;
side_control = false;
diff --git a/src/lib/formats/mfi_dsk.c b/src/lib/formats/mfi_dsk.c
index e7ca391ad88..ccb441c7a25 100644
--- a/src/lib/formats/mfi_dsk.c
+++ b/src/lib/formats/mfi_dsk.c
@@ -99,7 +99,7 @@ int mfi_format::identify(io_generic *io, UINT32 form_factor)
if(memcmp( h.sign, sign, 16 ) == 0 &&
h.cyl_count <= 160 &&
h.head_count <= 2 &&
- (!form_factor || h.form_factor == form_factor))
+ (!form_factor || !h.form_factor || h.form_factor == form_factor))
return 100;
return 0;
}
diff --git a/src/lib/formats/oric_dsk.c b/src/lib/formats/oric_dsk.c
index eb3bd159f89..95a2c34d427 100644
--- a/src/lib/formats/oric_dsk.c
+++ b/src/lib/formats/oric_dsk.c
@@ -1,3 +1,5 @@
+// license:BSD-3-Clause
+// copyright-holders:Olivier Galibert
/*********************************************************************
formats/oric_dsk.c
@@ -6,311 +8,107 @@
*********************************************************************/
-#include <string.h>
+#include "emu.h"
+#include "formats/oric_dsk.h"
-#include "imageutl.h"
-#include "flopimg.h"
-#include "oric_dsk.h"
-#include "basicdsk.h"
-
-
-#define mfm_disk_header_size 0x0100
-#define MFM_ID "MFM_DISK"
-
-#define TRACK_SIZE_MFM 0x1900
-
-struct mfm_disk_sector_info
-{
- int id_ptr;
- int data_ptr;
- int sector_size;
- UINT8 ddam;
-};
-
-struct oricdsk_tag
-{
- int tracks;
- int heads;
- int geometry;
- int tracksize;
- int num_sectors;
- struct mfm_disk_sector_info sector_data[32];
-};
-
-
-static struct oricdsk_tag *get_tag(floppy_image_legacy *floppy)
+oric_dsk_format::oric_dsk_format()
{
- struct oricdsk_tag *tag;
- tag = (oricdsk_tag *)floppy_tag(floppy);
- return tag;
}
-
-static FLOPPY_IDENTIFY(oric_dsk_identify)
+const char *oric_dsk_format::name() const
{
- UINT8 header[mfm_disk_header_size];
-
- floppy_image_read(floppy, header, 0, mfm_disk_header_size);
- if ( memcmp( header, MFM_ID, 8 ) ==0) {
- UINT32 heads = pick_integer_le(header, 8, 4);
- UINT32 tracks = pick_integer_le(header, 12, 4);
-
- if (floppy_image_size(floppy)==((tracks*heads*TRACK_SIZE_MFM)+mfm_disk_header_size)) {
- *vote = 100;
- } else {
- *vote = 0;
- }
- } else {
- *vote = 0;
- }
- return FLOPPY_ERROR_SUCCESS;
+ return "oric_dsk";
}
-static int oric_get_track_offset(floppy_image_legacy *floppy,int track, int head)
+
+const char *oric_dsk_format::description() const
{
- if (get_tag(floppy)->geometry==1) {
- return mfm_disk_header_size + (get_tag(floppy)->tracksize * track) + (head * get_tag(floppy)->tracksize * get_tag(floppy)->tracks);
- } else {
- return mfm_disk_header_size + (get_tag(floppy)->tracksize*((track * get_tag(floppy)->heads)+head));
- }
+ return "Oric disk image";
}
-static int oric_get_heads_per_disk(floppy_image_legacy *floppy)
+const char *oric_dsk_format::extensions() const
{
- return get_tag(floppy)->heads;
+ return "dsk";
}
-static int oric_get_tracks_per_disk(floppy_image_legacy *floppy)
+bool oric_dsk_format::supports_save() const
{
- return get_tag(floppy)->tracks;
+ return true;
}
-static void mfm_info_cache_sector_info(floppy_image_legacy *floppy,int track,int head)
+int oric_dsk_format::identify(io_generic *io, UINT32 form_factor)
{
- UINT8 track_data[TRACK_SIZE_MFM];
+ UINT8 h[256];
+ io_generic_read(io, h, 0, 256);
- /* initialise these with single density values if single density */
- UINT8 IdMark = 0x0fe;
- UINT8 DataMark = 0x0fb;
- UINT8 DeletedDataMark = 0x0f8;
+ if(memcmp(h, "MFM_DISK", 8))
+ return 0;
- UINT8 SectorCount;
- UINT8 SearchCode = 0;
- UINT8 sector_number = 0;
- int ptr = 0;
- int track_offset = oric_get_track_offset(floppy,track,head);
- floppy_image_read(floppy, track_data, track_offset, TRACK_SIZE_MFM);
- SectorCount = 0;
+ int sides = (h[11] << 24) | (h[10] << 16) | (h[ 9] << 8) | h[ 8];
+ int tracks = (h[15] << 24) | (h[14] << 16) | (h[13] << 8) | h[12];
+ int geom = (h[19] << 24) | (h[18] << 16) | (h[17] << 8) | h[16];
- do
- {
- switch (SearchCode)
- {
- /* searching for id's */
- case 0:
- {
- /* found id mark? */
- if (track_data[ptr] == IdMark)
- {
- sector_number = track_data[ptr+3]-1;
- /* store pointer to id mark */
- get_tag(floppy)->sector_data[sector_number].id_ptr = ptr + track_offset;
- SectorCount++;
+ int size = io_generic_size(io);
+ if(sides < 0 || sides > 2 || geom != 1 || size != 256+6400*sides*tracks)
+ return 0;
- /* grab N value - used to skip data in data field */
- get_tag(floppy)->sector_data[sector_number].sector_size = (1<< (track_data[ptr+4]+7));
-
- /* skip past id field and crc */
- ptr+=7;
+ return 100;
+}
- /* now looking for data field */
- SearchCode = 1;
- }
- else
- {
- /* update position */
- ptr++;
- }
- }
- break;
+bool oric_dsk_format::load(io_generic *io, UINT32 form_factor, floppy_image *image)
+{
+ UINT8 h[256];
+ UINT8 t[6250+3];
+ UINT32 stream[100000];
- /* searching for data id's */
- case 1:
- {
- /* found data or deleted data? */
- if ((track_data[ptr] == DataMark) || (track_data[ptr] == DeletedDataMark))
- {
- /* yes */
- get_tag(floppy)->sector_data[sector_number].data_ptr = ptr + track_offset + 1;
- get_tag(floppy)->sector_data[sector_number].ddam = (track_data[ptr] == DeletedDataMark) ? ID_FLAG_DELETED_DATA : 0;
+ t[6250] = t[6251] = t[6252] = 0;
+ io_generic_read(io, h, 0, 256);
- /* skip data field and id */
- ptr += get_tag(floppy)->sector_data[sector_number].sector_size + 3;
+ int sides = (h[11] << 24) | (h[10] << 16) | (h[ 9] << 8) | h[ 8];
+ int tracks = (h[15] << 24) | (h[14] << 16) | (h[13] << 8) | h[12];
- /* now looking for id field */
- SearchCode = 0;
+ for(int side=0; side<sides; side++)
+ for(int track=0; track<tracks; track++) {
+ io_generic_read(io, t, 256+6400*(tracks*side + track), 6250);
+ int pos = 0;
+ int sector_size = 128;
+ for(int i=0; i<6250; i++) {
+ if(t[i] == 0xc2 && t[i+1] == 0xc2 && t[i+2] == 0xc2) {
+ raw_w(stream, pos, 16, 0x5224);
+ raw_w(stream, pos, 16, 0x5224);
+ raw_w(stream, pos, 16, 0x5224);
+ i += 2;
+ continue;
}
- else
- {
- ptr++;
+ if(t[i] == 0xa1 && t[i+1] == 0xa1 && t[i+2] == 0xa1) {
+ raw_w(stream, pos, 16, 0x4489);
+ raw_w(stream, pos, 16, 0x4489);
+ raw_w(stream, pos, 16, 0x4489);
+ int copy;
+ if(t[i+3] == 0xfe) {
+ copy = 7;
+ sector_size = 128 << (t[i+7] & 3);
+ logerror("%02x %x - %02x %02x %02x %02x\n",
+ track, side, t[i+4], t[i+5], t[i+6], t[i+7]);
+ } else if(t[i+3] == 0xfb)
+ copy = sector_size+3;
+ else
+ copy = 0;
+ for(int j=0; j<copy; j++)
+ mfm_w(stream, pos, 8, t[i+3+j]);
+ i += 2+copy;
+ continue;
}
+ mfm_w(stream, pos, 8, t[i]);
}
- break;
-
- default:
- break;
+ generate_track_from_levels(track, side, stream, 100000, 0, image);
}
- }
- while (ptr < TRACK_SIZE_MFM);
- get_tag(floppy)->num_sectors = SectorCount;
-
-}
-
-static floperr_t get_offset(floppy_image_legacy *floppy, int head, int track, int sector, int sector_is_index, UINT64 *offset)
-{
- UINT64 offs;
-
- /* translate the sector to a raw sector */
- if (!sector_is_index)
- {
- sector -= 1;
- }
- mfm_info_cache_sector_info(floppy,track,head);
-
- /* check to see if we are out of range */
- if ((head < 0) || (head >= get_tag(floppy)->heads) || (track < 0) || (track >= get_tag(floppy)->tracks)
- || (sector < 0) || (sector >=get_tag(floppy)->num_sectors))
- return FLOPPY_ERROR_SEEKERROR;
-
- offs = get_tag(floppy)->sector_data[sector].data_ptr;
- if (offset)
- *offset = offs;
- return FLOPPY_ERROR_SUCCESS;
-}
-
-
-
-static floperr_t internal_oric_read_sector(floppy_image_legacy *floppy, int head, int track, int sector, int sector_is_index, void *buffer, size_t buflen)
-{
- UINT64 offset;
- floperr_t err;
- err = get_offset(floppy, head, track, sector, sector_is_index, &offset);
- if (err)
- return err;
- floppy_image_read(floppy, buffer, offset, buflen);
- return FLOPPY_ERROR_SUCCESS;
-}
-
-
-
-static floperr_t internal_oric_write_sector(floppy_image_legacy *floppy, int head, int track, int sector, int sector_is_index, const void *buffer, size_t buflen, int ddam)
-{
- UINT64 offset;
- floperr_t err;
-
- err = get_offset(floppy, head, track, sector, sector_is_index, &offset);
- if (err)
- return err;
-
- floppy_image_write(floppy, buffer, offset, buflen);
- return FLOPPY_ERROR_SUCCESS;
-}
-
-
-
-static floperr_t oric_read_sector(floppy_image_legacy *floppy, int head, int track, int sector, void *buffer, size_t buflen)
-{
- return internal_oric_read_sector(floppy, head, track, sector, FALSE, buffer, buflen);
+
+ return true;
}
-static floperr_t oric_write_sector(floppy_image_legacy *floppy, int head, int track, int sector, const void *buffer, size_t buflen, int ddam)
+bool oric_dsk_format::save(io_generic *io, floppy_image *image)
{
- return internal_oric_write_sector(floppy, head, track, sector, FALSE, buffer, buflen, ddam);
-}
-
-static floperr_t oric_read_indexed_sector(floppy_image_legacy *floppy, int head, int track, int sector, void *buffer, size_t buflen)
-{
- return internal_oric_read_sector(floppy, head, track, sector, TRUE, buffer, buflen);
-}
-
-static floperr_t oric_write_indexed_sector(floppy_image_legacy *floppy, int head, int track, int sector, const void *buffer, size_t buflen, int ddam)
-{
- return internal_oric_write_sector(floppy, head, track, sector, TRUE, buffer, buflen, ddam);
-}
-
-static floperr_t oric_get_sector_length(floppy_image_legacy *floppy, int head, int track, int sector, UINT32 *sector_length)
-{
- floperr_t err;
- err = get_offset(floppy, head, track, sector, FALSE, NULL);
- if (err)
- return err;
-
- if (sector_length) {
- *sector_length = get_tag(floppy)->sector_data[sector].sector_size;
- }
- return FLOPPY_ERROR_SUCCESS;
-}
-
-
-
-static floperr_t oric_get_indexed_sector_info(floppy_image_legacy *floppy, int head, int track, int sector_index, int *cylinder, int *side, int *sector, UINT32 *sector_length, unsigned long *flags)
-{
- floperr_t retVal;
-
- sector_index += 1;
-
- retVal = oric_get_sector_length(floppy, head, track, sector_index, sector_length);
- if (sector_length!=NULL) {
- *sector_length = get_tag(floppy)->sector_data[sector_index-1].sector_size;
- }
- if (cylinder)
- *cylinder = track;
- if (side)
- *side = head;
- if (sector)
- *sector = sector_index;
- if (flags)
- *flags = get_tag(floppy)->sector_data[sector_index].ddam;
- return retVal;
-}
-
-
-static FLOPPY_CONSTRUCT(oric_dsk_construct)
-{
- struct FloppyCallbacks *callbacks;
- struct oricdsk_tag *tag;
- UINT8 header[mfm_disk_header_size];
-
- floppy_image_read(floppy, header, 0, mfm_disk_header_size);
-
- tag = (struct oricdsk_tag *) floppy_create_tag(floppy, sizeof(struct oricdsk_tag));
- if (!tag)
- return FLOPPY_ERROR_OUTOFMEMORY;
-
- tag->heads = pick_integer_le(header, 8, 4);
- tag->tracks = pick_integer_le(header, 12, 4);
- tag->geometry = pick_integer_le(header, 16, 4);
- tag->tracksize = TRACK_SIZE_MFM;
- memset(tag->sector_data,0,sizeof(tag->sector_data));
-
- callbacks = floppy_callbacks(floppy);
- callbacks->read_sector = oric_read_sector;
- callbacks->write_sector = oric_write_sector;
- callbacks->read_indexed_sector = oric_read_indexed_sector;
- callbacks->write_indexed_sector = oric_write_indexed_sector;
- callbacks->get_sector_length = oric_get_sector_length;
- callbacks->get_heads_per_disk = oric_get_heads_per_disk;
- callbacks->get_tracks_per_disk = oric_get_tracks_per_disk;
- callbacks->get_indexed_sector_info = oric_get_indexed_sector_info;
- return FLOPPY_ERROR_SUCCESS;
+ return true;
}
-/* ----------------------------------------------------------------------- */
-LEGACY_FLOPPY_OPTIONS_START( oric )
- LEGACY_FLOPPY_OPTION( oricmfm, "dsk", "Oric MFM floppy disk image", oric_dsk_identify, oric_dsk_construct, NULL, NULL)
- LEGACY_FLOPPY_OPTION( oric, "dsk", "Oric disk image", basicdsk_identify_default, basicdsk_construct_default, NULL,
- HEADS([2])
- TRACKS([80])
- SECTORS([9])
- SECTOR_LENGTH([512])
- FIRST_SECTOR_ID([1]))
-LEGACY_FLOPPY_OPTIONS_END
+const floppy_format_type FLOPPY_ORIC_DSK_FORMAT = &floppy_image_format_creator<oric_dsk_format>;
diff --git a/src/lib/formats/oric_dsk.h b/src/lib/formats/oric_dsk.h
index 851544da3d2..98d5458f082 100644
--- a/src/lib/formats/oric_dsk.h
+++ b/src/lib/formats/oric_dsk.h
@@ -11,8 +11,20 @@
#include "flopimg.h"
-/**************************************************************************/
-
-LEGACY_FLOPPY_OPTIONS_EXTERN(oric);
+class oric_dsk_format : public floppy_image_format_t
+{
+public:
+ oric_dsk_format();
+ virtual int identify(io_generic *io, UINT32 form_factor);
+ virtual bool load(io_generic *io, UINT32 form_factor, floppy_image *image);
+ virtual bool save(io_generic *io, floppy_image *image);
+
+ virtual const char *name() const;
+ virtual const char *description() const;
+ virtual const char *extensions() const;
+ virtual bool supports_save() const;
+};
+
+extern const floppy_format_type FLOPPY_ORIC_DSK_FORMAT;
#endif /* ORIC_DSK_H */
diff --git a/src/mame/drivers/coolridr.c b/src/mame/drivers/coolridr.c
index fc5e80a9138..ee0ed0b9f5d 100644
--- a/src/mame/drivers/coolridr.c
+++ b/src/mame/drivers/coolridr.c
@@ -344,8 +344,8 @@ public:
UINT32 m_clipvals[2][3];
UINT8 m_clipblitterMode[2]; // hack
- required_device<cpu_device> m_maincpu;
- required_device<cpu_device> m_subcpu;
+ required_device<sh2_device> m_maincpu;
+ required_device<sh2_device> m_subcpu;
required_device<cpu_device> m_soundcpu;
//required_device<am9517a_device> m_dmac;
@@ -3704,8 +3704,8 @@ DRIVER_INIT_MEMBER(coolridr_state,coolridr)
{
m_maincpu->space(AS_PROGRAM).install_read_handler(0x60d8894, 0x060d8897, read32_delegate(FUNC(coolridr_state::coolridr_hack2_r), this));
- sh2drc_set_options(m_maincpu, SH2DRC_FASTEST_OPTIONS);
- sh2drc_set_options(m_subcpu, SH2DRC_FASTEST_OPTIONS);
+ m_maincpu->sh2drc_set_options(SH2DRC_FASTEST_OPTIONS);
+ m_subcpu->sh2drc_set_options(SH2DRC_FASTEST_OPTIONS);
}
GAME( 1995, coolridr, 0, coolridr, coolridr, coolridr_state, coolridr, ROT0, "Sega", "Cool Riders",GAME_IMPERFECT_SOUND) // region is set in test mode, this set is for Japan, USA and Export (all regions)
diff --git a/src/mame/drivers/cps3.c b/src/mame/drivers/cps3.c
index 3a922f2f448..9b4448071ad 100644
--- a/src/mame/drivers/cps3.c
+++ b/src/mame/drivers/cps3.c
@@ -799,7 +799,7 @@ void cps3_state::init_crypt(UINT32 key1, UINT32 key2, int altEncryption)
if (!m_user5region) m_user5region = auto_alloc_array(machine(), UINT8, USER5REGION_LENGTH);
// set strict verify
- sh2drc_set_options(m_maincpu, SH2DRC_STRICT_VERIFY);
+ m_maincpu->sh2drc_set_options(SH2DRC_STRICT_VERIFY);
cps3_decrypt_bios();
m_decrypted_gamerom = auto_alloc_array(machine(), UINT32, 0x1000000/4);
diff --git a/src/mame/drivers/deco_mlc.c b/src/mame/drivers/deco_mlc.c
index 3e0a6ea583e..3e226f6aa36 100644
--- a/src/mame/drivers/deco_mlc.c
+++ b/src/mame/drivers/deco_mlc.c
@@ -835,11 +835,11 @@ READ32_MEMBER(deco_mlc_state::avengrgs_speedup_r)
DRIVER_INIT_MEMBER(deco_mlc_state,avengrgs)
{
// init options
- sh2drc_set_options(m_maincpu, SH2DRC_FASTEST_OPTIONS);
+ m_maincpu->sh2drc_set_options(SH2DRC_FASTEST_OPTIONS);
// set up speed cheat
- sh2drc_add_pcflush(m_maincpu, 0x3234);
- sh2drc_add_pcflush(m_maincpu, 0x32dc);
+ m_maincpu->sh2drc_add_pcflush(0x3234);
+ m_maincpu->sh2drc_add_pcflush(0x32dc);
m_mainCpuIsArm = 0;
m_maincpu->space(AS_PROGRAM).install_read_handler(0x01089a0, 0x01089a3, read32_delegate(FUNC(deco_mlc_state::avengrgs_speedup_r),this));
diff --git a/src/mame/drivers/psikyosh.c b/src/mame/drivers/psikyosh.c
index ba613bf40d8..68de80482fa 100644
--- a/src/mame/drivers/psikyosh.c
+++ b/src/mame/drivers/psikyosh.c
@@ -1172,58 +1172,58 @@ ROM_END
DRIVER_INIT_MEMBER(psikyosh_state,soldivid)
{
- sh2drc_set_options(m_maincpu, SH2DRC_FASTEST_OPTIONS);
+ m_maincpu->sh2drc_set_options(SH2DRC_FASTEST_OPTIONS);
}
DRIVER_INIT_MEMBER(psikyosh_state,s1945ii)
{
- sh2drc_set_options(m_maincpu, SH2DRC_FASTEST_OPTIONS);
+ m_maincpu->sh2drc_set_options(SH2DRC_FASTEST_OPTIONS);
}
DRIVER_INIT_MEMBER(psikyosh_state,daraku)
{
UINT8 *RAM = memregion("maincpu")->base();
membank("bank1")->set_base(&RAM[0x100000]);
- sh2drc_set_options(m_maincpu, SH2DRC_FASTEST_OPTIONS);
+ m_maincpu->sh2drc_set_options(SH2DRC_FASTEST_OPTIONS);
}
DRIVER_INIT_MEMBER(psikyosh_state,sbomberb)
{
- sh2drc_set_options(m_maincpu, SH2DRC_FASTEST_OPTIONS);
+ m_maincpu->sh2drc_set_options(SH2DRC_FASTEST_OPTIONS);
}
DRIVER_INIT_MEMBER(psikyosh_state,gunbird2)
{
UINT8 *RAM = memregion("maincpu")->base();
membank("bank1")->set_base(&RAM[0x100000]);
- sh2drc_set_options(m_maincpu, SH2DRC_FASTEST_OPTIONS);
+ m_maincpu->sh2drc_set_options(SH2DRC_FASTEST_OPTIONS);
}
DRIVER_INIT_MEMBER(psikyosh_state,s1945iii)
{
UINT8 *RAM = memregion("maincpu")->base();
membank("bank1")->set_base(&RAM[0x100000]);
- sh2drc_set_options(m_maincpu, SH2DRC_FASTEST_OPTIONS);
+ m_maincpu->sh2drc_set_options(SH2DRC_FASTEST_OPTIONS);
}
DRIVER_INIT_MEMBER(psikyosh_state,dragnblz)
{
- sh2drc_set_options(m_maincpu, SH2DRC_FASTEST_OPTIONS);
+ m_maincpu->sh2drc_set_options(SH2DRC_FASTEST_OPTIONS);
}
DRIVER_INIT_MEMBER(psikyosh_state,gnbarich)
{
- sh2drc_set_options(m_maincpu, SH2DRC_FASTEST_OPTIONS);
+ m_maincpu->sh2drc_set_options(SH2DRC_FASTEST_OPTIONS);
}
DRIVER_INIT_MEMBER(psikyosh_state,tgm2)
{
- sh2drc_set_options(m_maincpu, SH2DRC_FASTEST_OPTIONS);
+ m_maincpu->sh2drc_set_options(SH2DRC_FASTEST_OPTIONS);
}
DRIVER_INIT_MEMBER(psikyosh_state,mjgtaste)
{
- sh2drc_set_options(m_maincpu, SH2DRC_FASTEST_OPTIONS);
+ m_maincpu->sh2drc_set_options(SH2DRC_FASTEST_OPTIONS);
/* needs to install mahjong controls too (can select joystick in test mode tho) */
m_maincpu->space(AS_PROGRAM).install_read_handler(0x03000000, 0x03000003, read32_delegate(FUNC(psikyosh_state::mjgtaste_input_r),this));
}
diff --git a/src/mame/drivers/stv.c b/src/mame/drivers/stv.c
index 0869a109492..0fb5f4a8116 100644
--- a/src/mame/drivers/stv.c
+++ b/src/mame/drivers/stv.c
@@ -359,11 +359,11 @@ WRITE32_MEMBER(stv_state::magzun_ioga_w32)
void stv_state::install_stvbios_speedups( void )
{
// flushes 0 & 1 on both CPUs are for the BIOS speedups
- sh2drc_add_pcflush(m_maincpu, 0x60154b2);
- sh2drc_add_pcflush(m_maincpu, 0x6013aee);
+ m_maincpu->sh2drc_add_pcflush(0x60154b2);
+ m_maincpu->sh2drc_add_pcflush(0x6013aee);
- sh2drc_add_pcflush(m_slave, 0x60154b2);
- sh2drc_add_pcflush(m_slave, 0x6013aee);
+ m_slave->sh2drc_add_pcflush(0x60154b2);
+ m_slave->sh2drc_add_pcflush(0x6013aee);
}
DRIVER_INIT_MEMBER(stv_state,stv)
@@ -387,8 +387,8 @@ DRIVER_INIT_MEMBER(stv_state,stv)
// do strict overwrite verification - maruchan and rsgun crash after coinup without this.
// cottonbm needs strict PCREL
// todo: test what games need this and don't turn it on for them...
- sh2drc_set_options(m_maincpu, SH2DRC_STRICT_VERIFY|SH2DRC_STRICT_PCREL);
- sh2drc_set_options(m_slave, SH2DRC_STRICT_VERIFY|SH2DRC_STRICT_PCREL);
+ m_maincpu->sh2drc_set_options(SH2DRC_STRICT_VERIFY|SH2DRC_STRICT_PCREL);
+ m_slave->sh2drc_set_options(SH2DRC_STRICT_VERIFY|SH2DRC_STRICT_PCREL);
m_maincpu->space(AS_PROGRAM).install_readwrite_handler(0x00400000, 0x0040003f, read32_delegate(FUNC(stv_state::stv_ioga_r32),this), write32_delegate(FUNC(stv_state::stv_ioga_w32),this));
m_slave->space(AS_PROGRAM).install_readwrite_handler(0x00400000, 0x0040003f, read32_delegate(FUNC(stv_state::stv_ioga_r32),this), write32_delegate(FUNC(stv_state::stv_ioga_w32),this));
@@ -429,9 +429,9 @@ READ32_MEMBER(stv_state::magzun_rx_hack_r)
DRIVER_INIT_MEMBER(stv_state,magzun)
{
- sh2drc_add_pcflush(m_maincpu, 0x604bf20);
- sh2drc_add_pcflush(m_maincpu, 0x604bfbe);
- sh2drc_add_pcflush(m_maincpu, 0x604c006);
+ m_maincpu->sh2drc_add_pcflush(0x604bf20);
+ m_maincpu->sh2drc_add_pcflush(0x604bfbe);
+ m_maincpu->sh2drc_add_pcflush(0x604c006);
DRIVER_INIT_CALL(stv);
@@ -463,9 +463,9 @@ DRIVER_INIT_MEMBER(stv_state,stvmp)
DRIVER_INIT_MEMBER(stv_state,shienryu)
{
// master
- sh2drc_add_pcflush(m_maincpu, 0x60041c6);
+ m_maincpu->sh2drc_add_pcflush(0x60041c6);
// slave
- sh2drc_add_pcflush(m_slave, 0x600440e);
+ m_slave->sh2drc_add_pcflush(0x600440e);
DRIVER_INIT_CALL(stv);
}
@@ -481,9 +481,9 @@ DRIVER_INIT_MEMBER(stv_state,prikura)
*/
// master
- sh2drc_add_pcflush(m_maincpu, 0x6018640);
+ m_maincpu->sh2drc_add_pcflush(0x6018640);
// slave
- sh2drc_add_pcflush(m_slave, 0x6018c6e);
+ m_slave->sh2drc_add_pcflush(0x6018c6e);
DRIVER_INIT_CALL(stv);
@@ -510,7 +510,7 @@ DRIVER_INIT_MEMBER(stv_state,hanagumi)
(loops for 288688 instructions)
*/
- sh2drc_add_pcflush(m_maincpu, 0x6010160);
+ m_maincpu->sh2drc_add_pcflush(0x6010160);
DRIVER_INIT_CALL(stv);
}
@@ -536,9 +536,9 @@ CPU0: Aids Screen
DRIVER_INIT_MEMBER(stv_state,puyosun)
{
- sh2drc_add_pcflush(m_maincpu, 0x6021cf0);
+ m_maincpu->sh2drc_add_pcflush(0x6021cf0);
- sh2drc_add_pcflush(m_slave, 0x60236fe);
+ m_slave->sh2drc_add_pcflush(0x60236fe);
DRIVER_INIT_CALL(stv);
@@ -558,7 +558,7 @@ CPU0 Data East Logo:
DRIVER_INIT_MEMBER(stv_state,mausuke)
{
- sh2drc_add_pcflush(m_maincpu, 0x60461A0);
+ m_maincpu->sh2drc_add_pcflush(0x60461A0);
DRIVER_INIT_CALL(stv);
@@ -568,8 +568,8 @@ DRIVER_INIT_MEMBER(stv_state,mausuke)
DRIVER_INIT_MEMBER(stv_state,cottonbm)
{
-// sh2drc_add_pcflush(m_maincpu, 0x6030ee2);
-// sh2drc_add_pcflush(m_slave, 0x6032b52);
+// m_maincpu->sh2drc_add_pcflush(0x6030ee2);
+// m_slave->sh2drc_add_pcflush(0x6032b52);
DRIVER_INIT_CALL(stv);
@@ -578,8 +578,8 @@ DRIVER_INIT_MEMBER(stv_state,cottonbm)
DRIVER_INIT_MEMBER(stv_state,cotton2)
{
- sh2drc_add_pcflush(m_maincpu, 0x6031c7a);
- sh2drc_add_pcflush(m_slave, 0x60338ea);
+ m_maincpu->sh2drc_add_pcflush(0x6031c7a);
+ m_slave->sh2drc_add_pcflush(0x60338ea);
DRIVER_INIT_CALL(stv);
@@ -589,13 +589,13 @@ DRIVER_INIT_MEMBER(stv_state,cotton2)
DRIVER_INIT_MEMBER(stv_state,dnmtdeka)
{
// install all 3 speedups on both master and slave
- sh2drc_add_pcflush(m_maincpu, 0x6027c90);
- sh2drc_add_pcflush(m_maincpu, 0xd04);
- sh2drc_add_pcflush(m_maincpu, 0x60051f2);
+ m_maincpu->sh2drc_add_pcflush(0x6027c90);
+ m_maincpu->sh2drc_add_pcflush(0xd04);
+ m_maincpu->sh2drc_add_pcflush(0x60051f2);
- sh2drc_add_pcflush(m_slave, 0x6027c90);
- sh2drc_add_pcflush(m_slave, 0xd04);
- sh2drc_add_pcflush(m_slave, 0x60051f2);
+ m_slave->sh2drc_add_pcflush(0x6027c90);
+ m_slave->sh2drc_add_pcflush(0xd04);
+ m_slave->sh2drc_add_pcflush(0x60051f2);
DRIVER_INIT_CALL(stv);
}
@@ -603,22 +603,22 @@ DRIVER_INIT_MEMBER(stv_state,dnmtdeka)
DRIVER_INIT_MEMBER(stv_state,diehard)
{
// install all 3 speedups on both master and slave
- sh2drc_add_pcflush(m_maincpu, 0x6027c98);
- sh2drc_add_pcflush(m_maincpu, 0xd04);
- sh2drc_add_pcflush(m_maincpu, 0x60051f2);
+ m_maincpu->sh2drc_add_pcflush(0x6027c98);
+ m_maincpu->sh2drc_add_pcflush(0xd04);
+ m_maincpu->sh2drc_add_pcflush(0x60051f2);
- sh2drc_add_pcflush(m_slave, 0x6027c98);
- sh2drc_add_pcflush(m_slave, 0xd04);
- sh2drc_add_pcflush(m_slave, 0x60051f2);
+ m_slave->sh2drc_add_pcflush(0x6027c98);
+ m_slave->sh2drc_add_pcflush(0xd04);
+ m_slave->sh2drc_add_pcflush(0x60051f2);
DRIVER_INIT_CALL(stv);
}
DRIVER_INIT_MEMBER(stv_state,fhboxers)
{
- sh2drc_add_pcflush(m_maincpu, 0x60041c2);
- sh2drc_add_pcflush(m_maincpu, 0x600bb0a);
- sh2drc_add_pcflush(m_maincpu, 0x600b31e);
+ m_maincpu->sh2drc_add_pcflush(0x60041c2);
+ m_maincpu->sh2drc_add_pcflush(0x600bb0a);
+ m_maincpu->sh2drc_add_pcflush(0x600b31e);
DRIVER_INIT_CALL(stv);
@@ -627,11 +627,11 @@ DRIVER_INIT_MEMBER(stv_state,fhboxers)
DRIVER_INIT_MEMBER(stv_state,groovef)
{
- sh2drc_add_pcflush(m_maincpu, 0x6005e7c);
- sh2drc_add_pcflush(m_maincpu, 0x6005e86);
- sh2drc_add_pcflush(m_maincpu, 0x60a4970);
+ m_maincpu->sh2drc_add_pcflush(0x6005e7c);
+ m_maincpu->sh2drc_add_pcflush(0x6005e86);
+ m_maincpu->sh2drc_add_pcflush(0x60a4970);
- sh2drc_add_pcflush(m_slave, 0x60060c2);
+ m_slave->sh2drc_add_pcflush(0x60060c2);
DRIVER_INIT_CALL(stv);
@@ -641,9 +641,9 @@ DRIVER_INIT_MEMBER(stv_state,groovef)
DRIVER_INIT_MEMBER(stv_state,danchih)
{
- sh2drc_add_pcflush(m_maincpu, 0x6028b28);
- sh2drc_add_pcflush(m_maincpu, 0x6028c8e);
- sh2drc_add_pcflush(m_slave, 0x602ae26);
+ m_maincpu->sh2drc_add_pcflush(0x6028b28);
+ m_maincpu->sh2drc_add_pcflush(0x6028c8e);
+ m_slave->sh2drc_add_pcflush(0x602ae26);
DRIVER_INIT_CALL(stvmp);
@@ -652,9 +652,9 @@ DRIVER_INIT_MEMBER(stv_state,danchih)
DRIVER_INIT_MEMBER(stv_state,danchiq)
{
- sh2drc_add_pcflush(m_maincpu, 0x6028b28);
- sh2drc_add_pcflush(m_maincpu, 0x6028c8e);
- sh2drc_add_pcflush(m_slave, 0x602ae26);
+ m_maincpu->sh2drc_add_pcflush(0x6028b28);
+ m_maincpu->sh2drc_add_pcflush(0x6028c8e);
+ m_slave->sh2drc_add_pcflush(0x602ae26);
DRIVER_INIT_CALL(stv);
@@ -663,8 +663,8 @@ DRIVER_INIT_MEMBER(stv_state,danchiq)
DRIVER_INIT_MEMBER(stv_state,astrass)
{
- sh2drc_add_pcflush(m_maincpu, 0x60011ba);
- sh2drc_add_pcflush(m_maincpu, 0x605b9da);
+ m_maincpu->sh2drc_add_pcflush(0x60011ba);
+ m_maincpu->sh2drc_add_pcflush(0x605b9da);
install_astrass_protection();
@@ -673,9 +673,9 @@ DRIVER_INIT_MEMBER(stv_state,astrass)
DRIVER_INIT_MEMBER(stv_state,thunt)
{
- sh2drc_add_pcflush(m_maincpu, 0x602A024);
- sh2drc_add_pcflush(m_maincpu, 0x6013EEA);
- sh2drc_add_pcflush(m_slave, 0x602AAF8);
+ m_maincpu->sh2drc_add_pcflush(0x602A024);
+ m_maincpu->sh2drc_add_pcflush(0x6013EEA);
+ m_slave->sh2drc_add_pcflush(0x602AAF8);
DRIVER_INIT_CALL(stv);
@@ -684,9 +684,9 @@ DRIVER_INIT_MEMBER(stv_state,thunt)
DRIVER_INIT_MEMBER(stv_state,sandor)
{
- sh2drc_add_pcflush(m_maincpu, 0x602a0f8);
- sh2drc_add_pcflush(m_maincpu, 0x6013fbe);
- sh2drc_add_pcflush(m_slave, 0x602abcc);
+ m_maincpu->sh2drc_add_pcflush(0x602a0f8);
+ m_maincpu->sh2drc_add_pcflush(0x6013fbe);
+ m_slave->sh2drc_add_pcflush(0x602abcc);
DRIVER_INIT_CALL(stv);
m_minit_boost_timeslice = m_sinit_boost_timeslice = attotime::from_usec(1);
@@ -694,8 +694,8 @@ DRIVER_INIT_MEMBER(stv_state,sandor)
DRIVER_INIT_MEMBER(stv_state,grdforce)
{
- sh2drc_add_pcflush(m_maincpu, 0x6041e32);
- sh2drc_add_pcflush(m_slave, 0x6043aa2);
+ m_maincpu->sh2drc_add_pcflush(0x6041e32);
+ m_slave->sh2drc_add_pcflush(0x6043aa2);
DRIVER_INIT_CALL(stv);
@@ -704,8 +704,8 @@ DRIVER_INIT_MEMBER(stv_state,grdforce)
DRIVER_INIT_MEMBER(stv_state,batmanfr)
{
- sh2drc_add_pcflush(m_maincpu, 0x60121c0);
- sh2drc_add_pcflush(m_slave, 0x60125bc);
+ m_maincpu->sh2drc_add_pcflush(0x60121c0);
+ m_slave->sh2drc_add_pcflush(0x60125bc);
DRIVER_INIT_CALL(stv);
@@ -718,7 +718,7 @@ DRIVER_INIT_MEMBER(stv_state,batmanfr)
DRIVER_INIT_MEMBER(stv_state,colmns97)
{
- sh2drc_add_pcflush(m_slave, 0x60298a2);
+ m_slave->sh2drc_add_pcflush(0x60298a2);
DRIVER_INIT_CALL(stv);
@@ -727,8 +727,8 @@ DRIVER_INIT_MEMBER(stv_state,colmns97)
DRIVER_INIT_MEMBER(stv_state,winterht)
{
- sh2drc_add_pcflush(m_maincpu, 0x6098aea);
- sh2drc_add_pcflush(m_slave, 0x609ae4e);
+ m_maincpu->sh2drc_add_pcflush(0x6098aea);
+ m_slave->sh2drc_add_pcflush(0x609ae4e);
DRIVER_INIT_CALL(stv);
@@ -737,8 +737,8 @@ DRIVER_INIT_MEMBER(stv_state,winterht)
DRIVER_INIT_MEMBER(stv_state,seabass)
{
- sh2drc_add_pcflush(m_maincpu, 0x602cbfa);
- sh2drc_add_pcflush(m_slave, 0x60321ee);
+ m_maincpu->sh2drc_add_pcflush(0x602cbfa);
+ m_slave->sh2drc_add_pcflush(0x60321ee);
DRIVER_INIT_CALL(stv);
@@ -747,8 +747,8 @@ DRIVER_INIT_MEMBER(stv_state,seabass)
DRIVER_INIT_MEMBER(stv_state,vfremix)
{
- sh2drc_add_pcflush(m_maincpu, 0x602c30c);
- sh2drc_add_pcflush(m_slave, 0x604c332);
+ m_maincpu->sh2drc_add_pcflush(0x602c30c);
+ m_slave->sh2drc_add_pcflush(0x604c332);
DRIVER_INIT_CALL(stv);
@@ -757,8 +757,8 @@ DRIVER_INIT_MEMBER(stv_state,vfremix)
DRIVER_INIT_MEMBER(stv_state,sss)
{
- sh2drc_add_pcflush(m_maincpu, 0x6026398);
- sh2drc_add_pcflush(m_slave, 0x6028cd6);
+ m_maincpu->sh2drc_add_pcflush(0x6026398);
+ m_slave->sh2drc_add_pcflush(0x6028cd6);
install_sss_protection();
@@ -769,8 +769,8 @@ DRIVER_INIT_MEMBER(stv_state,sss)
DRIVER_INIT_MEMBER(stv_state,othellos)
{
- sh2drc_add_pcflush(m_maincpu, 0x602bcbe);
- sh2drc_add_pcflush(m_slave, 0x602d92e);
+ m_maincpu->sh2drc_add_pcflush(0x602bcbe);
+ m_slave->sh2drc_add_pcflush(0x602d92e);
DRIVER_INIT_CALL(stv);
@@ -779,7 +779,7 @@ DRIVER_INIT_MEMBER(stv_state,othellos)
DRIVER_INIT_MEMBER(stv_state,sasissu)
{
- sh2drc_add_pcflush(m_slave, 0x60710be);
+ m_slave->sh2drc_add_pcflush(0x60710be);
DRIVER_INIT_CALL(stv);
@@ -788,14 +788,14 @@ DRIVER_INIT_MEMBER(stv_state,sasissu)
DRIVER_INIT_MEMBER(stv_state,gaxeduel)
{
-// sh2drc_add_pcflush(m_maincpu, 0x6012ee4);
+// m_maincpu->sh2drc_add_pcflush(0x6012ee4);
DRIVER_INIT_CALL(stv);
}
DRIVER_INIT_MEMBER(stv_state,suikoenb)
{
- sh2drc_add_pcflush(m_maincpu, 0x6013f7a);
+ m_maincpu->sh2drc_add_pcflush(0x6013f7a);
DRIVER_INIT_CALL(stv);
}
@@ -810,8 +810,8 @@ DRIVER_INIT_MEMBER(stv_state,sokyugrt)
DRIVER_INIT_MEMBER(stv_state,znpwfv)
{
- sh2drc_add_pcflush(m_maincpu, 0x6012ec2);
- sh2drc_add_pcflush(m_slave, 0x60175a6);
+ m_maincpu->sh2drc_add_pcflush(0x6012ec2);
+ m_slave->sh2drc_add_pcflush(0x60175a6);
DRIVER_INIT_CALL(stv);
m_minit_boost_timeslice = m_sinit_boost_timeslice = attotime::from_nsec(500);
@@ -819,8 +819,8 @@ DRIVER_INIT_MEMBER(stv_state,znpwfv)
DRIVER_INIT_MEMBER(stv_state,twcup98)
{
- sh2drc_add_pcflush(m_maincpu, 0x605edde);
- sh2drc_add_pcflush(m_slave, 0x6062bca);
+ m_maincpu->sh2drc_add_pcflush(0x605edde);
+ m_slave->sh2drc_add_pcflush(0x6062bca);
DRIVER_INIT_CALL(stv);
install_twcup98_protection();
@@ -830,8 +830,8 @@ DRIVER_INIT_MEMBER(stv_state,twcup98)
DRIVER_INIT_MEMBER(stv_state,smleague)
{
- sh2drc_add_pcflush(m_maincpu, 0x6063bf4);
- sh2drc_add_pcflush(m_slave, 0x6062bca);
+ m_maincpu->sh2drc_add_pcflush(0x6063bf4);
+ m_slave->sh2drc_add_pcflush(0x6062bca);
DRIVER_INIT_CALL(stv);
@@ -842,7 +842,7 @@ DRIVER_INIT_MEMBER(stv_state,smleague)
DRIVER_INIT_MEMBER(stv_state,finlarch)
{
- sh2drc_add_pcflush(m_maincpu, 0x6064d60);
+ m_maincpu->sh2drc_add_pcflush(0x6064d60);
DRIVER_INIT_CALL(stv);
@@ -853,8 +853,8 @@ DRIVER_INIT_MEMBER(stv_state,finlarch)
DRIVER_INIT_MEMBER(stv_state,maruchan)
{
- sh2drc_add_pcflush(m_maincpu, 0x601ba46);
- sh2drc_add_pcflush(m_slave, 0x601ba46);
+ m_maincpu->sh2drc_add_pcflush(0x601ba46);
+ m_slave->sh2drc_add_pcflush(0x601ba46);
DRIVER_INIT_CALL(stv);
@@ -863,22 +863,22 @@ DRIVER_INIT_MEMBER(stv_state,maruchan)
DRIVER_INIT_MEMBER(stv_state,pblbeach)
{
- sh2drc_add_pcflush(m_maincpu, 0x605eb78);
+ m_maincpu->sh2drc_add_pcflush(0x605eb78);
DRIVER_INIT_CALL(stv);
}
DRIVER_INIT_MEMBER(stv_state,shanhigw)
{
- sh2drc_add_pcflush(m_maincpu, 0x6020c5c);
+ m_maincpu->sh2drc_add_pcflush(0x6020c5c);
DRIVER_INIT_CALL(stv);
}
DRIVER_INIT_MEMBER(stv_state,elandore)
{
- sh2drc_add_pcflush(m_maincpu, 0x604eac0);
- sh2drc_add_pcflush(m_slave, 0x605340a);
+ m_maincpu->sh2drc_add_pcflush(0x604eac0);
+ m_slave->sh2drc_add_pcflush(0x605340a);
install_elandore_protection();
@@ -888,8 +888,8 @@ DRIVER_INIT_MEMBER(stv_state,elandore)
DRIVER_INIT_MEMBER(stv_state,rsgun)
{
- sh2drc_add_pcflush(m_maincpu, 0x6034d04);
- sh2drc_add_pcflush(m_slave, 0x6036152);
+ m_maincpu->sh2drc_add_pcflush(0x6034d04);
+ m_slave->sh2drc_add_pcflush(0x6036152);
install_rsgun_protection();
@@ -915,8 +915,8 @@ DRIVER_INIT_MEMBER(stv_state,decathlt)
DRIVER_INIT_MEMBER(stv_state,nameclv3)
{
- sh2drc_add_pcflush(m_maincpu, 0x601eb4c);
- sh2drc_add_pcflush(m_slave, 0x602b80e);
+ m_maincpu->sh2drc_add_pcflush(0x601eb4c);
+ m_slave->sh2drc_add_pcflush(0x602b80e);
DRIVER_INIT_CALL(stv);
}
diff --git a/src/mame/drivers/suprnova.c b/src/mame/drivers/suprnova.c
index 39b3a5301a6..fb5b1718b9b 100644
--- a/src/mame/drivers/suprnova.c
+++ b/src/mame/drivers/suprnova.c
@@ -945,12 +945,12 @@ READ32_MEMBER(skns_state::sengekij_speedup_r)// 60006ee 600308e
void skns_state::init_skns()
{
// init DRC to fastest options
- sh2drc_set_options(m_maincpu, SH2DRC_FASTEST_OPTIONS);
+ m_maincpu->sh2drc_set_options(SH2DRC_FASTEST_OPTIONS);
}
void skns_state::set_drc_pcflush(UINT32 addr)
{
- sh2drc_add_pcflush(m_maincpu, addr);
+ m_maincpu->sh2drc_add_pcflush(addr);
}
DRIVER_INIT_MEMBER(skns_state,galpani4) { machine().device<sknsspr_device>("spritegen")->skns_sprite_kludge(-5,-1); init_skns(); }
diff --git a/src/mame/includes/cps3.h b/src/mame/includes/cps3.h
index ad76a240550..fdea9d919ce 100644
--- a/src/mame/includes/cps3.h
+++ b/src/mame/includes/cps3.h
@@ -5,6 +5,7 @@
****************************************************************************/
#include "machine/intelfsh.h"
+#include "cpu/sh2/sh2.h"
class cps3_state : public driver_device
{
@@ -132,7 +133,7 @@ public:
int transparency, int transparent_color,
int scalex, int scaley, bitmap_ind8 *pri_buffer, UINT32 pri_mask);
- required_device<cpu_device> m_maincpu;
+ required_device<sh2_device> m_maincpu;
required_device<gfxdecode_device> m_gfxdecode;
required_device<palette_device> m_palette;
};
diff --git a/src/mame/includes/deco_mlc.h b/src/mame/includes/deco_mlc.h
index b67d5a94a7e..d2ddb525f99 100644
--- a/src/mame/includes/deco_mlc.h
+++ b/src/mame/includes/deco_mlc.h
@@ -1,6 +1,8 @@
#include "machine/eepromser.h"
#include "machine/deco146.h"
#include "sound/ymz280b.h"
+#include "cpu/sh2/sh2.h"
+
class deco_mlc_state : public driver_device
{
@@ -67,7 +69,7 @@ public:
void blitRaster(bitmap_rgb32 &bitmap, int rasterMode);
void draw_sprites( const rectangle &cliprect, int scanline, UINT32* dest);
void descramble_sound( );
- required_device<cpu_device> m_maincpu;
+ required_device<sh2_device> m_maincpu;
required_device<eeprom_serial_93cxx_device> m_eeprom;
required_device<ymz280b_device> m_ymz;
required_device<gfxdecode_device> m_gfxdecode;
diff --git a/src/mame/includes/psikyosh.h b/src/mame/includes/psikyosh.h
index 3033e95853f..0cfb237aafb 100644
--- a/src/mame/includes/psikyosh.h
+++ b/src/mame/includes/psikyosh.h
@@ -1,5 +1,7 @@
#include "video/bufsprite.h"
#include "machine/eepromser.h"
+#include "cpu/sh2/sh2.h"
+
#define MASTER_CLOCK 57272700 // main oscillator frequency
@@ -49,7 +51,7 @@ public:
UINT8 m_alphatable[256];
/* devices */
- required_device<cpu_device> m_maincpu;
+ required_device<sh2_device> m_maincpu;
required_device<eeprom_serial_93cxx_device> m_eeprom;
required_device<gfxdecode_device> m_gfxdecode;
required_device<screen_device> m_screen;
diff --git a/src/mame/includes/stv.h b/src/mame/includes/stv.h
index ce7769abb6c..d59ae5a8ac4 100644
--- a/src/mame/includes/stv.h
+++ b/src/mame/includes/stv.h
@@ -4,6 +4,7 @@
#include "cpu/m68000/m68000.h"
#include "cpu/adsp2100/adsp2100.h"
#include "cpu/scudsp/scudsp.h"
+#include "cpu/sh2/sh2.h"
#define MAX_FILTERS (24)
#define MAX_BLOCKS (200)
@@ -144,8 +145,8 @@ public:
UINT8 m_system_output;
UINT16 m_serial_tx;
- required_device<cpu_device> m_maincpu;
- required_device<cpu_device> m_slave;
+ required_device<sh2_device> m_maincpu;
+ required_device<sh2_device> m_slave;
required_device<m68000_base_device> m_audiocpu;
required_device<scudsp_cpu_device> m_scudsp;
optional_device<eeprom_serial_93cxx_device> m_eeprom;
diff --git a/src/mame/includes/suprnova.h b/src/mame/includes/suprnova.h
index 29864f42e88..29d0a70a452 100644
--- a/src/mame/includes/suprnova.h
+++ b/src/mame/includes/suprnova.h
@@ -1,3 +1,7 @@
+
+#include "cpu/sh2/sh2.h"
+
+
struct hit_t
{
UINT16 x1p, y1p, z1p, x1s, y1s, z1s;
@@ -34,7 +38,7 @@ public:
m_gfxdecode(*this, "gfxdecode"),
m_palette(*this, "palette") { }
- required_device<cpu_device> m_maincpu;
+ required_device<sh2_device> m_maincpu;
required_shared_ptr<UINT32> m_spriteram;
sknsspr_device* m_spritegen;
diff --git a/src/mess/drivers/oric.c b/src/mess/drivers/oric.c
index 7aa721e3c18..b1a09433cd0 100644
--- a/src/mess/drivers/oric.c
+++ b/src/mess/drivers/oric.c
@@ -12,321 +12,768 @@
Pravetz is a Bulgarian copy of the Oric Atmos and uses
Apple 2 disc drives for storage.
- This driver originally by Paul Cook, rewritten by Kevin Thacker.
+ This driver originally by Paul Cook, rewritten by Kevin Thacker,
+ re-rewritten by Olivier Galibert.
*********************************************************************/
-#include "includes/oric.h"
+#include "emu.h"
+#include "bus/oricext/oricext.h"
+#include "cpu/m6502/m6502.h"
+#include "sound/ay8910.h"
+#include "sound/wave.h"
+#include "machine/6522via.h"
+#include "machine/mos6551.h"
+#include "bus/centronics/ctronics.h"
+#include "imagedev/floppy.h"
+#include "imagedev/cassette.h"
+#include "machine/wd_fdc.h"
+#include "formats/oric_dsk.h"
+#include "formats/oric_tap.h"
+
+class oric_state : public driver_device
+{
+public:
+ // Permanent attributes (kept from one line to the other) and line
+ // attributes (reset at start of line)
+ enum {
+ PATTR_50HZ = 0x02,
+ PATTR_HIRES = 0x04,
+ LATTR_ALT = 0x01,
+ LATTR_DSIZE = 0x02,
+ LATTR_BLINK = 0x04
+ };
+
+ oric_state(const machine_config &mconfig, device_type type, const char *tag)
+ : driver_device(mconfig, type, tag),
+ m_maincpu(*this, "maincpu"),
+ m_psg(*this, "ay8912"),
+ m_centronics(*this, "centronics"),
+ m_cent_data_out(*this, "cent_data_out"),
+ m_cassette(*this, "cassette"),
+ m_via(*this, "via6522"),
+ m_ram(*this, "ram"),
+ m_rom(*this, "maincpu"),
+ m_bank_c000_r(*this, "bank_c000_r"),
+ m_bank_e000_r(*this, "bank_e000_r"),
+ m_bank_f800_r(*this, "bank_f800_r"),
+ m_bank_c000_w(*this, "bank_c000_w"),
+ m_bank_e000_w(*this, "bank_e000_w"),
+ m_bank_f800_w(*this, "bank_f800_w"),
+ m_config(*this, "CONFIG") { }
+
+ DECLARE_INPUT_CHANGED_MEMBER(nmi_pressed);
+ DECLARE_WRITE8_MEMBER(via_a_w);
+ DECLARE_WRITE8_MEMBER(via_b_w);
+ DECLARE_WRITE_LINE_MEMBER(via_ca2_w);
+ DECLARE_WRITE_LINE_MEMBER(via_cb2_w);
+ DECLARE_WRITE_LINE_MEMBER(via_irq_w);
+ DECLARE_WRITE_LINE_MEMBER(ext_irq_w);
+ DECLARE_WRITE8_MEMBER(psg_a_w);
+ TIMER_DEVICE_CALLBACK_MEMBER(update_tape);
+
+ virtual void machine_start();
+ virtual void video_start();
+ UINT32 screen_update_oric(screen_device &screen, bitmap_rgb32 &bitmap, const rectangle &cliprect);
+ void vblank_w(screen_device &screen, bool state);
+
+protected:
+ required_device<cpu_device> m_maincpu;
+ required_device<ay8910_device> m_psg;
+ required_device<centronics_device> m_centronics;
+ required_device<output_latch_device> m_cent_data_out;
+ required_device<cassette_image_device> m_cassette;
+ required_device<via6522_device> m_via;
+ required_shared_ptr<UINT8> m_ram;
+ optional_memory_region m_rom;
+ required_memory_bank m_bank_c000_r;
+ optional_memory_bank m_bank_e000_r;
+ optional_memory_bank m_bank_f800_r;
+ required_memory_bank m_bank_c000_w;
+ optional_memory_bank m_bank_e000_w;
+ optional_memory_bank m_bank_f800_w;
+ required_ioport m_config;
+ ioport_port *m_kbd_row[8];
+
+ int m_blink_counter;
+ UINT8 m_pattr;
+ UINT8 m_via_a, m_via_b, m_psg_a;
+ bool m_via_ca2, m_via_cb2, m_via_irq;
+ bool m_ext_irq;
+
+ virtual void update_irq();
+ void update_psg(address_space &space);
+ void update_keyboard();
+ void machine_start_common();
+};
+
+class telestrat_state : public oric_state
+{
+public:
+ telestrat_state(const machine_config &mconfig, device_type type, const char *tag) :
+ oric_state(mconfig, type, tag),
+ m_via2(*this, "via6522_2"),
+ m_fdc(*this, "fdc"),
+ m_telmatic(*this, "telmatic"),
+ m_teleass(*this, "teleass"),
+ m_hyperbas(*this, "hyperbas"),
+ m_telmon24(*this, "telmon24"),
+ m_joy1(*this, "JOY1"),
+ m_joy2(*this, "JOY2")
+ { }
+
+ DECLARE_WRITE8_MEMBER(via2_a_w);
+ DECLARE_WRITE8_MEMBER(via2_b_w);
+ DECLARE_WRITE_LINE_MEMBER(via2_ca2_w);
+ DECLARE_WRITE_LINE_MEMBER(via2_cb2_w);
+ DECLARE_WRITE_LINE_MEMBER(via2_irq_w);
+ DECLARE_WRITE8_MEMBER(port_314_w);
+ DECLARE_READ8_MEMBER(port_314_r);
+ DECLARE_READ8_MEMBER(port_318_r);
+
+ DECLARE_WRITE_LINE_MEMBER(acia_irq_w);
+
+ DECLARE_WRITE_LINE_MEMBER(fdc_irq_w);
+ DECLARE_WRITE_LINE_MEMBER(fdc_drq_w);
+ DECLARE_WRITE_LINE_MEMBER(fdc_hld_w);
+
+ DECLARE_FLOPPY_FORMATS(floppy_formats);
+
+ virtual void machine_start();
+ virtual void machine_reset();
+
+protected:
+ enum {
+ P_IRQEN = 0x01,
+ P_DDS = 0x04,
+ P_DDEN = 0x08,
+ P_SS = 0x10,
+ P_DRIVE = 0x60
+ };
+
+ required_device<via6522_device> m_via2;
+ required_device<fd1793_t> m_fdc;
+ required_memory_region m_telmatic;
+ required_memory_region m_teleass;
+ required_memory_region m_hyperbas;
+ required_memory_region m_telmon24;
+ required_ioport m_joy1;
+ required_ioport m_joy2;
+
+ floppy_image_device *m_floppies[4];
+ UINT8 m_port_314;
+ UINT8 m_via2_a, m_via2_b;
+ bool m_via2_ca2, m_via2_cb2, m_via2_irq;
+ bool m_acia_irq;
+ bool m_fdc_irq, m_fdc_drq, m_fdc_hld;
+
+ UINT8 m_junk_read[0x4000], m_junk_write[0x4000];
+
+ virtual void update_irq();
+ void remap();
+};
+
+/* Ram is 64K, with 16K hidden by the rom. The 300-3ff is also hidden by the i/o */
+static ADDRESS_MAP_START(oric_mem, AS_PROGRAM, 8, oric_state )
+ AM_RANGE( 0x0300, 0x030f) AM_DEVREADWRITE("via6522", via6522_device, read, write) AM_MIRROR(0xf0)
+ AM_RANGE( 0xc000, 0xdfff) AM_READ_BANK("bank_c000_r") AM_WRITE_BANK("bank_c000_w")
+ AM_RANGE( 0xe000, 0xf7ff) AM_READ_BANK("bank_e000_r") AM_WRITE_BANK("bank_e000_w")
+ AM_RANGE( 0xf800, 0xffff) AM_READ_BANK("bank_f800_r") AM_WRITE_BANK("bank_f800_w")
+ AM_RANGE( 0x0000, 0xffff) AM_RAM AM_SHARE("ram")
+ADDRESS_MAP_END
/*
- Explanation of memory regions:
+The telestrat has the memory regions split into 16k blocks.
+Memory region &c000-&ffff can be ram or rom. */
+static ADDRESS_MAP_START(telestrat_mem, AS_PROGRAM, 8, telestrat_state )
+ AM_RANGE( 0x0300, 0x030f) AM_DEVREADWRITE("via6522", via6522_device, read, write)
+ AM_RANGE( 0x0310, 0x0313) AM_DEVREADWRITE("fdc", fd1793_t, read, write)
+ AM_RANGE( 0x0314, 0x0314) AM_READWRITE(port_314_r, port_314_w)
+ AM_RANGE( 0x0318, 0x0318) AM_READ(port_318_r)
+ AM_RANGE( 0x031c, 0x031f) AM_DEVREADWRITE("acia", mos6551_device, read, write)
+ AM_RANGE( 0x0320, 0x032f) AM_DEVREADWRITE("via6522_2", via6522_device, read, write)
+ AM_RANGE( 0xc000, 0xffff) AM_READ_BANK("bank_c000_r") AM_WRITE_BANK("bank_c000_w")
+ AM_RANGE( 0x0000, 0xffff) AM_RAM AM_SHARE("ram")
+ADDRESS_MAP_END
+
+UINT32 oric_state::screen_update_oric(screen_device &screen, bitmap_rgb32 &bitmap, const rectangle &cliprect)
+{
+ static const UINT32 colors[8] = {
+ 0x000000,
+ 0xff0000,
+ 0x00ff00,
+ 0xffff00,
+ 0x0000ff,
+ 0xff00ff,
+ 0x00ffff,
+ 0xffffff
+ };
+
+ bool blink_state = m_blink_counter & 0x20;
+ m_blink_counter = (m_blink_counter + 1) & 0x3f;
+
+ UINT8 pattr = m_pattr;
+
+ for(int y=0; y<224; y++) {
+ // Line attributes and current colors
+ UINT8 lattr = 0;
+ UINT32 fgcol = colors[7];
+ UINT32 bgcol = colors[0];
+
+ UINT32 *p = &bitmap.pix32(y);
+
+ for(int x=0; x<40; x++) {
+ // Lookup the byte and, if needed, the pattern data
+ UINT8 ch, pat;
+ if((pattr & PATTR_HIRES) && y < 200)
+ ch = pat = m_ram[0xa000 + y*40 + x];
+
+ else {
+ ch = m_ram[0xbb80 + (y>>3)*40 + x];
+ int off = (lattr & LATTR_DSIZE ? y >> 1 : y ) & 7;
+ const UINT8 *base;
+ if(pattr & PATTR_HIRES)
+ if(lattr & LATTR_ALT)
+ base = m_ram + 0x9c00;
+ else
+ base = m_ram + 0x9800;
+ else
+ if(lattr & LATTR_ALT)
+ base = m_ram + 0xb800;
+ else
+ base = m_ram + 0xb400;
+ pat = base[((ch & 0x7f) << 3) | off];
+ }
+
+ // Handle state-chaging attributes
+ if(!(ch & 0x60)) {
+ pat = 0x00;
+ switch(ch & 0x18) {
+ case 0x00: fgcol = colors[ch & 7]; break;
+ case 0x08: lattr = ch & 7; break;
+ case 0x10: bgcol = colors[ch & 7]; break;
+ case 0x18: pattr = ch & 7; break;
+ }
+ }
+
+ // Pick up the colors for the pattern
+ UINT32 c_fgcol = fgcol;
+ UINT32 c_bgcol = bgcol;
+
+ // inverse video
+ if(ch & 0x80) {
+ c_bgcol = c_bgcol ^ 0xffffff;
+ c_fgcol = c_fgcol ^ 0xffffff;
+ }
+ // blink
+ if((lattr & LATTR_BLINK) && blink_state)
+ c_fgcol = c_bgcol;
+
+ // Draw the pattern
+ *p++ = pat & 0x20 ? c_fgcol : c_bgcol;
+ *p++ = pat & 0x10 ? c_fgcol : c_bgcol;
+ *p++ = pat & 0x08 ? c_fgcol : c_bgcol;
+ *p++ = pat & 0x04 ? c_fgcol : c_bgcol;
+ *p++ = pat & 0x02 ? c_fgcol : c_bgcol;
+ *p++ = pat & 0x01 ? c_fgcol : c_bgcol;
+ }
+ }
+
+ m_pattr = pattr;
- I have split the memory region &c000-&ffff in this way because:
+ return 0;
+}
- All roms (os, microdisc and jasmin) use the 6502 IRQ vectors at the end
- of memory &fff8-&ffff, but they are different sizes. The os is 16k, microdisc
- is 8k and jasmin is 2k.
+void oric_state::update_keyboard()
+{
+ m_via->write_pb3((m_kbd_row[m_via_b & 7]->read() | m_psg_a) != 0xff);
+}
+
+void oric_state::update_psg(address_space &space)
+{
+ if(m_via_ca2)
+ if(m_via_cb2)
+ m_psg->address_w(space, 0, m_via_a);
+ else
+ m_via->write_pa(space, 0, m_psg->data_r(space, 0));
+ else if(m_via_cb2)
+ m_psg->data_w(space, 0, m_via_a);
+}
- There is also 16k of ram at &c000-&ffff which is normally masked
- by the os rom, but when the microdisc or jasmin interfaces are used,
- this ram can be accessed. For the microdisc and jasmin, the ram not
- covered by the roms for these interfaces, can be accessed
- if it is enabled.
+void oric_state::update_irq()
+{
+ m_maincpu->set_input_line(m6502_device::IRQ_LINE, m_via_irq || m_ext_irq ? ASSERT_LINE : CLEAR_LINE);
+}
- SMH_BANK(1),SMH_BANK(2) and SMH_BANK(3) are used for a 16k rom.
- SMH_BANK(2) and SMH_BANK(3) are used for a 8k rom.
- SMH_BANK(3) is used for a 2k rom.
+INPUT_CHANGED_MEMBER(oric_state::nmi_pressed)
+{
+ m_maincpu->set_input_line(m6502_device::NMI_LINE, newval ? ASSERT_LINE : CLEAR_LINE);
+}
- 0x0300-0x03ff is I/O access. It is not defined below because the
- memory is setup dynamically depending on hardware that has been selected (microdisc, jasmin, apple2) etc.
+WRITE8_MEMBER(oric_state::via_a_w)
+{
+ m_via_a = data;
+ m_cent_data_out->write(space, 0, m_via_a);
+ update_psg(space);
+}
-*/
+WRITE8_MEMBER(oric_state::via_b_w)
+{
+ m_via_b = data;
+ update_keyboard();
+ m_centronics->write_strobe(data & 0x10 ? 1 : 0);
+ m_cassette->change_state(data & 0x40 ? CASSETTE_MOTOR_ENABLED : CASSETTE_MOTOR_DISABLED,
+ CASSETTE_MOTOR_DISABLED);
+ m_cassette->output(data & 0x80 ? -1.0 : +1.0);
+}
+WRITE_LINE_MEMBER(oric_state::via_ca2_w)
+{
+ m_via_ca2 = state;
+ update_psg(m_maincpu->space(AS_PROGRAM));
+}
-static ADDRESS_MAP_START(oric_mem, AS_PROGRAM, 8, oric_state )
- AM_RANGE( 0x0000, 0xbfff) AM_RAM AM_SHARE("ram")
- AM_RANGE( 0xc000, 0xdfff) AM_READ_BANK("bank1") AM_WRITE_BANK("bank5")
- AM_RANGE( 0xe000, 0xf7ff) AM_READ_BANK("bank2") AM_WRITE_BANK("bank6")
- AM_RANGE( 0xf800, 0xffff) AM_READ_BANK("bank3") AM_WRITE_BANK("bank7")
-ADDRESS_MAP_END
+WRITE_LINE_MEMBER(oric_state::via_cb2_w)
+{
+ m_via_cb2 = state;
+ update_psg(m_maincpu->space(AS_PROGRAM));
+}
+
+WRITE_LINE_MEMBER(oric_state::via_irq_w)
+{
+ m_via_irq = state;
+ update_irq();
+}
+
+WRITE_LINE_MEMBER(oric_state::ext_irq_w)
+{
+ m_ext_irq = state;
+ update_irq();
+}
+
+WRITE8_MEMBER(oric_state::psg_a_w)
+{
+ m_psg_a = data;
+ update_keyboard();
+}
+
+TIMER_DEVICE_CALLBACK_MEMBER(oric_state::update_tape)
+{
+ if(!m_config->read())
+ m_via->write_cb1(m_cassette->input() > 0.0038);
+}
+
+void oric_state::vblank_w(screen_device &screen, bool state)
+{
+ if(m_config->read())
+ m_via->write_cb1(state);
+}
+
+void oric_state::video_start()
+{
+ m_blink_counter = 0;
+ m_pattr = 0;
+}
+
+void oric_state::machine_start_common()
+{
+ m_via_a = 0xff;
+ m_via_b = 0xff;
+ m_psg_a = 0x00;
+ m_via_ca2 = false;
+ m_via_cb2 = false;
+ m_via_irq = false;
+ m_ext_irq = false;
+
+ for(int i=0; i<8; i++) {
+ char name[10];
+ sprintf(name, "ROW%d", i);
+ m_kbd_row[i] = machine().root_device().ioport(name);
+ }
+}
+
+void oric_state::machine_start()
+{
+ machine_start_common();
+ m_bank_c000_r->set_base(m_rom->base());
+ m_bank_e000_r->set_base(m_rom->base() + 0x2000);
+ m_bank_f800_r->set_base(m_rom->base() + 0x3800);
+}
+
+
+void telestrat_state::machine_start()
+{
+ machine_start_common();
+ for(int i=0; i<4; i++) {
+ char name[32];
+ sprintf(name, "fdc:%d", i);
+ m_floppies[i] = subdevice<floppy_connector>(name)->get_device();
+ }
+ m_fdc_irq = m_fdc_drq = m_fdc_hld = false;
+ m_acia_irq = false;
+
+ memset(m_junk_read, 0x00, sizeof(m_junk_read));
+ memset(m_junk_write, 0x00, sizeof(m_junk_write));
+}
+
+void telestrat_state::machine_reset()
+{
+ m_port_314 = 0x00;
+ m_via2_a = 0xff;
+ remap();
+}
+
+void telestrat_state::update_irq()
+{
+ m_maincpu->set_input_line(m6502_device::IRQ_LINE,
+ m_via_irq ||
+ m_ext_irq ||
+ (m_fdc_irq && (m_port_314 & P_IRQEN)) ||
+ m_via2_irq ||
+ m_acia_irq ? ASSERT_LINE : CLEAR_LINE);
+}
+
+WRITE8_MEMBER(telestrat_state::via2_a_w)
+{
+ m_via2_a = data;
+ remap();
+}
+
+WRITE8_MEMBER(telestrat_state::via2_b_w)
+{
+ m_via2_b = data;
+ UINT8 port = 0xff;
+ if(!(m_via2_b & 0x40))
+ port &= m_joy1->read();
+ if(!(m_via2_b & 0x80))
+ port &= m_joy2->read();
+
+ m_via2->write_pb(space, 0, port);
+}
+
+WRITE_LINE_MEMBER(telestrat_state::via2_ca2_w)
+{
+ m_via2_ca2 = state;
+}
+
+WRITE_LINE_MEMBER(telestrat_state::via2_cb2_w)
+{
+ m_via2_cb2 = state;
+}
+
+WRITE_LINE_MEMBER(telestrat_state::via2_irq_w)
+{
+ m_via2_irq = state;
+ update_irq();
+}
+
+WRITE8_MEMBER(telestrat_state::port_314_w)
+{
+ m_port_314 = data;
+ floppy_image_device *floppy = m_floppies[(m_port_314 >> 5) & 3];
+ m_fdc->set_floppy(floppy);
+ m_fdc->dden_w(m_port_314 & P_DDEN);
+ if(floppy) {
+ floppy->ss_w(m_port_314 & P_SS ? 1 : 0);
+ floppy->mon_w(0);
+ }
+ update_irq();
+}
+
+READ8_MEMBER(telestrat_state::port_314_r)
+{
+ return (m_fdc_irq && (m_port_314 & P_IRQEN)) ? 0x7f : 0xff;
+}
+
+READ8_MEMBER(telestrat_state::port_318_r)
+{
+ return m_fdc_drq ? 0x7f : 0xff;
+}
+
+
+WRITE_LINE_MEMBER(telestrat_state::acia_irq_w)
+{
+ m_acia_irq = state;
+ update_irq();
+}
+
+WRITE_LINE_MEMBER(telestrat_state::fdc_irq_w)
+{
+ m_fdc_irq = state;
+ update_irq();
+}
+
+WRITE_LINE_MEMBER(telestrat_state::fdc_drq_w)
+{
+ m_fdc_drq = state;
+}
+
+WRITE_LINE_MEMBER(telestrat_state::fdc_hld_w)
+{
+ m_fdc_hld = state;
+}
+
+void telestrat_state::remap()
+{
+ // Theorically, these are cartridges. There's no real point to
+ // making them configurable, when only 4 existed and there are 7
+ // slots.
+
+ switch(m_via2_a & 7) {
+ case 0:
+ m_bank_c000_r->set_base(m_ram+0xc000);
+ m_bank_c000_w->set_base(m_ram+0xc000);
+ break;
+ case 1:
+ case 2:
+ case 3:
+ m_bank_c000_r->set_base(m_junk_read);
+ m_bank_c000_w->set_base(m_junk_write);
+ break;
+ case 4:
+ m_bank_c000_r->set_base(m_telmatic->base());
+ m_bank_c000_w->set_base(m_junk_write);
+ break;
+ case 5:
+ m_bank_c000_r->set_base(m_teleass->base());
+ m_bank_c000_w->set_base(m_junk_write);
+ break;
+ case 6:
+ m_bank_c000_r->set_base(m_hyperbas->base());
+ m_bank_c000_w->set_base(m_junk_write);
+ break;
+ case 7:
+ m_bank_c000_r->set_base(m_telmon24->base());
+ m_bank_c000_w->set_base(m_junk_write);
+ break;
+ }
+}
-/*
-The telestrat has the memory regions split into 16k blocks.
-Memory region &c000-&ffff can be ram or rom. */
-static ADDRESS_MAP_START(telestrat_mem, AS_PROGRAM, 8, oric_state )
- AM_RANGE( 0x0000, 0x02ff) AM_RAM
- AM_RANGE( 0x0300, 0x030f) AM_DEVREADWRITE("via6522_0", via6522_device, read, write)
- AM_RANGE( 0x0310, 0x031b) AM_READWRITE(oric_microdisc_r, oric_microdisc_w )
- AM_RANGE( 0x031c, 0x031f) AM_DEVREADWRITE("acia", mos6551_device, read, write)
- AM_RANGE( 0x0320, 0x032f) AM_DEVREADWRITE("via6522_1", via6522_device, read, write)
- AM_RANGE( 0x0400, 0xbfff) AM_RAM
- AM_RANGE( 0xc000, 0xffff) AM_READ_BANK("bank1") AM_WRITE_BANK("bank2")
-ADDRESS_MAP_END
static INPUT_PORTS_START(oric)
PORT_START("ROW0")
- PORT_BIT(0x80, IP_ACTIVE_HIGH, IPT_KEYBOARD) PORT_CODE(KEYCODE_3) PORT_CHAR('3') PORT_CHAR('#')
- PORT_BIT(0x40, IP_ACTIVE_HIGH, IPT_KEYBOARD) PORT_CODE(KEYCODE_X) PORT_CHAR('x') PORT_CHAR('X')
- PORT_BIT(0x20, IP_ACTIVE_HIGH, IPT_KEYBOARD) PORT_CODE(KEYCODE_1) PORT_CHAR('1') PORT_CHAR('!')
- PORT_BIT(0x10, 0x00, IPT_UNUSED)
- PORT_BIT(0x08, IP_ACTIVE_HIGH, IPT_KEYBOARD) PORT_CODE(KEYCODE_V) PORT_CHAR('v') PORT_CHAR('V')
- PORT_BIT(0x04, IP_ACTIVE_HIGH, IPT_KEYBOARD) PORT_CODE(KEYCODE_5) PORT_CHAR('5') PORT_CHAR('%')
- PORT_BIT(0x02, IP_ACTIVE_HIGH, IPT_KEYBOARD) PORT_CODE(KEYCODE_N) PORT_CHAR('n') PORT_CHAR('N')
- PORT_BIT(0x01, IP_ACTIVE_HIGH, IPT_KEYBOARD) PORT_CODE(KEYCODE_7) PORT_CHAR('7') PORT_CHAR('&')
+ PORT_BIT(0x80, IP_ACTIVE_LOW, IPT_KEYBOARD) PORT_CODE(KEYCODE_3) PORT_CHAR('3') PORT_CHAR('#')
+ PORT_BIT(0x40, IP_ACTIVE_LOW, IPT_KEYBOARD) PORT_CODE(KEYCODE_X) PORT_CHAR('x') PORT_CHAR('X')
+ PORT_BIT(0x20, IP_ACTIVE_LOW, IPT_KEYBOARD) PORT_CODE(KEYCODE_1) PORT_CHAR('1') PORT_CHAR('!')
+ PORT_BIT(0x10, IP_ACTIVE_LOW, IPT_UNUSED)
+ PORT_BIT(0x08, IP_ACTIVE_LOW, IPT_KEYBOARD) PORT_CODE(KEYCODE_V) PORT_CHAR('v') PORT_CHAR('V')
+ PORT_BIT(0x04, IP_ACTIVE_LOW, IPT_KEYBOARD) PORT_CODE(KEYCODE_5) PORT_CHAR('5') PORT_CHAR('%')
+ PORT_BIT(0x02, IP_ACTIVE_LOW, IPT_KEYBOARD) PORT_CODE(KEYCODE_N) PORT_CHAR('n') PORT_CHAR('N')
+ PORT_BIT(0x01, IP_ACTIVE_LOW, IPT_KEYBOARD) PORT_CODE(KEYCODE_7) PORT_CHAR('7') PORT_CHAR('&')
PORT_START("ROW1")
- PORT_BIT(0x80, IP_ACTIVE_HIGH, IPT_KEYBOARD) PORT_CODE(KEYCODE_D) PORT_CHAR('d') PORT_CHAR('D')
- PORT_BIT(0x40, IP_ACTIVE_HIGH, IPT_KEYBOARD) PORT_CODE(KEYCODE_Q) PORT_CHAR('q') PORT_CHAR('Q')
- PORT_BIT(0x20, IP_ACTIVE_HIGH, IPT_KEYBOARD) PORT_CODE(KEYCODE_TAB) PORT_CHAR(UCHAR_MAMEKEY(ESC))
- PORT_BIT(0x10, 0x00, IPT_UNUSED)
- PORT_BIT(0x08, IP_ACTIVE_HIGH, IPT_KEYBOARD) PORT_CODE(KEYCODE_F) PORT_CHAR('f') PORT_CHAR('F')
- PORT_BIT(0x04, IP_ACTIVE_HIGH, IPT_KEYBOARD) PORT_CODE(KEYCODE_R) PORT_CHAR('r') PORT_CHAR('R')
- PORT_BIT(0x02, IP_ACTIVE_HIGH, IPT_KEYBOARD) PORT_CODE(KEYCODE_T) PORT_CHAR('t') PORT_CHAR('T')
- PORT_BIT(0x01, IP_ACTIVE_HIGH, IPT_KEYBOARD) PORT_CODE(KEYCODE_J) PORT_CHAR('j') PORT_CHAR('J')
+ PORT_BIT(0x80, IP_ACTIVE_LOW, IPT_KEYBOARD) PORT_CODE(KEYCODE_D) PORT_CHAR('d') PORT_CHAR('D')
+ PORT_BIT(0x40, IP_ACTIVE_LOW, IPT_KEYBOARD) PORT_CODE(KEYCODE_Q) PORT_CHAR('q') PORT_CHAR('Q')
+ PORT_BIT(0x20, IP_ACTIVE_LOW, IPT_KEYBOARD) PORT_CODE(KEYCODE_TAB) PORT_CHAR(UCHAR_MAMEKEY(ESC))
+ PORT_BIT(0x10, IP_ACTIVE_LOW, IPT_UNUSED)
+ PORT_BIT(0x08, IP_ACTIVE_LOW, IPT_KEYBOARD) PORT_CODE(KEYCODE_F) PORT_CHAR('f') PORT_CHAR('F')
+ PORT_BIT(0x04, IP_ACTIVE_LOW, IPT_KEYBOARD) PORT_CODE(KEYCODE_R) PORT_CHAR('r') PORT_CHAR('R')
+ PORT_BIT(0x02, IP_ACTIVE_LOW, IPT_KEYBOARD) PORT_CODE(KEYCODE_T) PORT_CHAR('t') PORT_CHAR('T')
+ PORT_BIT(0x01, IP_ACTIVE_LOW, IPT_KEYBOARD) PORT_CODE(KEYCODE_J) PORT_CHAR('j') PORT_CHAR('J')
PORT_START("ROW2")
- PORT_BIT(0x80, IP_ACTIVE_HIGH, IPT_KEYBOARD) PORT_CODE(KEYCODE_C) PORT_CHAR('c') PORT_CHAR('C')
- PORT_BIT(0x40, IP_ACTIVE_HIGH, IPT_KEYBOARD) PORT_CODE(KEYCODE_2) PORT_CHAR('2') PORT_CHAR('@')
- PORT_BIT(0x20, IP_ACTIVE_HIGH, IPT_KEYBOARD) PORT_CODE(KEYCODE_Z) PORT_CHAR('z') PORT_CHAR('Z')
- PORT_BIT(0x10, IP_ACTIVE_HIGH, IPT_KEYBOARD) PORT_CODE(KEYCODE_LCONTROL) PORT_CODE(KEYCODE_LCONTROL) PORT_CHAR(UCHAR_SHIFT_2)
- PORT_BIT(0x08, IP_ACTIVE_HIGH, IPT_KEYBOARD) PORT_CODE(KEYCODE_4) PORT_CHAR('4') PORT_CHAR('$')
- PORT_BIT(0x04, IP_ACTIVE_HIGH, IPT_KEYBOARD) PORT_CODE(KEYCODE_B) PORT_CHAR('b') PORT_CHAR('B')
- PORT_BIT(0x02, IP_ACTIVE_HIGH, IPT_KEYBOARD) PORT_CODE(KEYCODE_6) PORT_CHAR('6') PORT_CHAR('^')
- PORT_BIT(0x01, IP_ACTIVE_HIGH, IPT_KEYBOARD) PORT_CODE(KEYCODE_M) PORT_CHAR('m') PORT_CHAR('M')
+ PORT_BIT(0x80, IP_ACTIVE_LOW, IPT_KEYBOARD) PORT_CODE(KEYCODE_C) PORT_CHAR('c') PORT_CHAR('C')
+ PORT_BIT(0x40, IP_ACTIVE_LOW, IPT_KEYBOARD) PORT_CODE(KEYCODE_2) PORT_CHAR('2') PORT_CHAR('@')
+ PORT_BIT(0x20, IP_ACTIVE_LOW, IPT_KEYBOARD) PORT_CODE(KEYCODE_Z) PORT_CHAR('z') PORT_CHAR('Z')
+ PORT_BIT(0x10, IP_ACTIVE_LOW, IPT_KEYBOARD) PORT_CODE(KEYCODE_LCONTROL) PORT_CODE(KEYCODE_LCONTROL) PORT_CHAR(UCHAR_SHIFT_2)
+ PORT_BIT(0x08, IP_ACTIVE_LOW, IPT_KEYBOARD) PORT_CODE(KEYCODE_4) PORT_CHAR('4') PORT_CHAR('$')
+ PORT_BIT(0x04, IP_ACTIVE_LOW, IPT_KEYBOARD) PORT_CODE(KEYCODE_B) PORT_CHAR('b') PORT_CHAR('B')
+ PORT_BIT(0x02, IP_ACTIVE_LOW, IPT_KEYBOARD) PORT_CODE(KEYCODE_6) PORT_CHAR('6') PORT_CHAR('^')
+ PORT_BIT(0x01, IP_ACTIVE_LOW, IPT_KEYBOARD) PORT_CODE(KEYCODE_M) PORT_CHAR('m') PORT_CHAR('M')
PORT_START("ROW3")
- PORT_BIT(0x80, IP_ACTIVE_HIGH, IPT_KEYBOARD) PORT_CODE(KEYCODE_QUOTE) PORT_CHAR('\'') PORT_CHAR('"')
- PORT_BIT(0x40, IP_ACTIVE_HIGH, IPT_KEYBOARD) PORT_CODE(KEYCODE_BACKSLASH2) PORT_CHAR('\\') PORT_CHAR('|')
- PORT_BIT(0x20, 0x00, IPT_UNUSED)
- PORT_BIT(0x10, 0x00, IPT_UNUSED)
- PORT_BIT(0x08, IP_ACTIVE_HIGH, IPT_KEYBOARD) PORT_CODE(KEYCODE_MINUS) PORT_CHAR('-') PORT_CHAR('\xA3')
- PORT_BIT(0x04, IP_ACTIVE_HIGH, IPT_KEYBOARD) PORT_CODE(KEYCODE_COLON) PORT_CHAR(';') PORT_CHAR(':')
- PORT_BIT(0x02, IP_ACTIVE_HIGH, IPT_KEYBOARD) PORT_CODE(KEYCODE_9) PORT_CHAR('9') PORT_CHAR('(')
- PORT_BIT(0x01, IP_ACTIVE_HIGH, IPT_KEYBOARD) PORT_CODE(KEYCODE_K) PORT_CHAR('k') PORT_CHAR('K')
+ PORT_BIT(0x80, IP_ACTIVE_LOW, IPT_KEYBOARD) PORT_CODE(KEYCODE_QUOTE) PORT_CHAR('\'') PORT_CHAR('"')
+ PORT_BIT(0x40, IP_ACTIVE_LOW, IPT_KEYBOARD) PORT_CODE(KEYCODE_BACKSLASH2) PORT_CHAR('\\') PORT_CHAR('|')
+ PORT_BIT(0x20, IP_ACTIVE_LOW, IPT_UNUSED)
+ PORT_BIT(0x10, IP_ACTIVE_LOW, IPT_UNUSED)
+ PORT_BIT(0x08, IP_ACTIVE_LOW, IPT_KEYBOARD) PORT_CODE(KEYCODE_MINUS) PORT_CHAR('-') PORT_CHAR('\xA3')
+ PORT_BIT(0x04, IP_ACTIVE_LOW, IPT_KEYBOARD) PORT_CODE(KEYCODE_COLON) PORT_CHAR(';') PORT_CHAR(':')
+ PORT_BIT(0x02, IP_ACTIVE_LOW, IPT_KEYBOARD) PORT_CODE(KEYCODE_9) PORT_CHAR('9') PORT_CHAR('(')
+ PORT_BIT(0x01, IP_ACTIVE_LOW, IPT_KEYBOARD) PORT_CODE(KEYCODE_K) PORT_CHAR('k') PORT_CHAR('K')
PORT_START("ROW4")
- PORT_BIT(0x80, IP_ACTIVE_HIGH, IPT_KEYBOARD) PORT_CODE(KEYCODE_RIGHT) PORT_CHAR(UCHAR_MAMEKEY(RIGHT))
- PORT_BIT(0x40, IP_ACTIVE_HIGH, IPT_KEYBOARD) PORT_CODE(KEYCODE_DOWN) PORT_CHAR(UCHAR_MAMEKEY(DOWN))
- PORT_BIT(0x20, IP_ACTIVE_HIGH, IPT_KEYBOARD) PORT_CODE(KEYCODE_LEFT) PORT_CHAR(UCHAR_MAMEKEY(LEFT))
- PORT_BIT(0x10, IP_ACTIVE_HIGH, IPT_KEYBOARD) PORT_CODE(KEYCODE_LSHIFT) PORT_CHAR(UCHAR_MAMEKEY(LSHIFT))
- PORT_BIT(0x08, IP_ACTIVE_HIGH, IPT_KEYBOARD) PORT_CODE(KEYCODE_UP) PORT_CHAR(UCHAR_MAMEKEY(UP))
- PORT_BIT(0x04, IP_ACTIVE_HIGH, IPT_KEYBOARD) PORT_CODE(KEYCODE_STOP) PORT_CHAR('.') PORT_CHAR('>')
- PORT_BIT(0x02, IP_ACTIVE_HIGH, IPT_KEYBOARD) PORT_CODE(KEYCODE_COMMA) PORT_CHAR(',') PORT_CHAR('<')
- PORT_BIT(0x01, IP_ACTIVE_HIGH, IPT_KEYBOARD) PORT_CODE(KEYCODE_SPACE) PORT_CHAR(' ')
+ PORT_BIT(0x80, IP_ACTIVE_LOW, IPT_KEYBOARD) PORT_CODE(KEYCODE_RIGHT) PORT_CHAR(UCHAR_MAMEKEY(RIGHT))
+ PORT_BIT(0x40, IP_ACTIVE_LOW, IPT_KEYBOARD) PORT_CODE(KEYCODE_DOWN) PORT_CHAR(UCHAR_MAMEKEY(DOWN))
+ PORT_BIT(0x20, IP_ACTIVE_LOW, IPT_KEYBOARD) PORT_CODE(KEYCODE_LEFT) PORT_CHAR(UCHAR_MAMEKEY(LEFT))
+ PORT_BIT(0x10, IP_ACTIVE_LOW, IPT_KEYBOARD) PORT_CODE(KEYCODE_LSHIFT) PORT_CHAR(UCHAR_MAMEKEY(LSHIFT))
+ PORT_BIT(0x08, IP_ACTIVE_LOW, IPT_KEYBOARD) PORT_CODE(KEYCODE_UP) PORT_CHAR(UCHAR_MAMEKEY(UP))
+ PORT_BIT(0x04, IP_ACTIVE_LOW, IPT_KEYBOARD) PORT_CODE(KEYCODE_STOP) PORT_CHAR('.') PORT_CHAR('>')
+ PORT_BIT(0x02, IP_ACTIVE_LOW, IPT_KEYBOARD) PORT_CODE(KEYCODE_COMMA) PORT_CHAR(',') PORT_CHAR('<')
+ PORT_BIT(0x01, IP_ACTIVE_LOW, IPT_KEYBOARD) PORT_CODE(KEYCODE_SPACE) PORT_CHAR(' ')
PORT_START("ROW5")
- PORT_BIT(0x80, IP_ACTIVE_HIGH, IPT_KEYBOARD) PORT_CODE(KEYCODE_OPENBRACE) PORT_CHAR('[') PORT_CHAR('{')
- PORT_BIT(0x40, IP_ACTIVE_HIGH, IPT_KEYBOARD) PORT_CODE(KEYCODE_CLOSEBRACE) PORT_CHAR(']') PORT_CHAR('}')
- PORT_BIT(0x20, IP_ACTIVE_HIGH, IPT_KEYBOARD) PORT_NAME("Del") PORT_CODE(KEYCODE_BACKSPACE) PORT_CHAR(8)
- PORT_BIT(0x10, 0x00, IPT_UNUSED)
- PORT_BIT(0x08, IP_ACTIVE_HIGH, IPT_KEYBOARD) PORT_CODE(KEYCODE_P) PORT_CHAR('p') PORT_CHAR('P')
- PORT_BIT(0x04, IP_ACTIVE_HIGH, IPT_KEYBOARD) PORT_CODE(KEYCODE_O) PORT_CHAR('o') PORT_CHAR('O')
- PORT_BIT(0x02, IP_ACTIVE_HIGH, IPT_KEYBOARD) PORT_CODE(KEYCODE_I) PORT_CHAR('i') PORT_CHAR('I')
- PORT_BIT(0x01, IP_ACTIVE_HIGH, IPT_KEYBOARD) PORT_CODE(KEYCODE_U) PORT_CHAR('u') PORT_CHAR('U')
+ PORT_BIT(0x80, IP_ACTIVE_LOW, IPT_KEYBOARD) PORT_CODE(KEYCODE_OPENBRACE) PORT_CHAR('[') PORT_CHAR('{')
+ PORT_BIT(0x40, IP_ACTIVE_LOW, IPT_KEYBOARD) PORT_CODE(KEYCODE_CLOSEBRACE) PORT_CHAR(']') PORT_CHAR('}')
+ PORT_BIT(0x20, IP_ACTIVE_LOW, IPT_KEYBOARD) PORT_NAME("Del") PORT_CODE(KEYCODE_BACKSPACE) PORT_CHAR(8)
+ PORT_BIT(0x10, IP_ACTIVE_LOW, IPT_UNUSED)
+ PORT_BIT(0x08, IP_ACTIVE_LOW, IPT_KEYBOARD) PORT_CODE(KEYCODE_P) PORT_CHAR('p') PORT_CHAR('P')
+ PORT_BIT(0x04, IP_ACTIVE_LOW, IPT_KEYBOARD) PORT_CODE(KEYCODE_O) PORT_CHAR('o') PORT_CHAR('O')
+ PORT_BIT(0x02, IP_ACTIVE_LOW, IPT_KEYBOARD) PORT_CODE(KEYCODE_I) PORT_CHAR('i') PORT_CHAR('I')
+ PORT_BIT(0x01, IP_ACTIVE_LOW, IPT_KEYBOARD) PORT_CODE(KEYCODE_U) PORT_CHAR('u') PORT_CHAR('U')
PORT_START("ROW6")
- PORT_BIT(0x80, IP_ACTIVE_HIGH, IPT_KEYBOARD) PORT_CODE(KEYCODE_W) PORT_CHAR('w') PORT_CHAR('W')
- PORT_BIT(0x40, IP_ACTIVE_HIGH, IPT_KEYBOARD) PORT_CODE(KEYCODE_S) PORT_CHAR('s') PORT_CHAR('S')
- PORT_BIT(0x20, IP_ACTIVE_HIGH, IPT_KEYBOARD) PORT_CODE(KEYCODE_A) PORT_CHAR('a') PORT_CHAR('A')
- PORT_BIT(0x10, 0x00, IPT_UNUSED)
- PORT_BIT(0x08, IP_ACTIVE_HIGH, IPT_KEYBOARD) PORT_CODE(KEYCODE_E) PORT_CHAR('e') PORT_CHAR('E')
- PORT_BIT(0x04, IP_ACTIVE_HIGH, IPT_KEYBOARD) PORT_CODE(KEYCODE_G) PORT_CHAR('g') PORT_CHAR('G')
- PORT_BIT(0x02, IP_ACTIVE_HIGH, IPT_KEYBOARD) PORT_CODE(KEYCODE_H) PORT_CHAR('h') PORT_CHAR('H')
- PORT_BIT(0x01, IP_ACTIVE_HIGH, IPT_KEYBOARD) PORT_CODE(KEYCODE_Y) PORT_CHAR('y') PORT_CHAR('Y')
+ PORT_BIT(0x80, IP_ACTIVE_LOW, IPT_KEYBOARD) PORT_CODE(KEYCODE_W) PORT_CHAR('w') PORT_CHAR('W')
+ PORT_BIT(0x40, IP_ACTIVE_LOW, IPT_KEYBOARD) PORT_CODE(KEYCODE_S) PORT_CHAR('s') PORT_CHAR('S')
+ PORT_BIT(0x20, IP_ACTIVE_LOW, IPT_KEYBOARD) PORT_CODE(KEYCODE_A) PORT_CHAR('a') PORT_CHAR('A')
+ PORT_BIT(0x10, IP_ACTIVE_LOW, IPT_UNUSED)
+ PORT_BIT(0x08, IP_ACTIVE_LOW, IPT_KEYBOARD) PORT_CODE(KEYCODE_E) PORT_CHAR('e') PORT_CHAR('E')
+ PORT_BIT(0x04, IP_ACTIVE_LOW, IPT_KEYBOARD) PORT_CODE(KEYCODE_G) PORT_CHAR('g') PORT_CHAR('G')
+ PORT_BIT(0x02, IP_ACTIVE_LOW, IPT_KEYBOARD) PORT_CODE(KEYCODE_H) PORT_CHAR('h') PORT_CHAR('H')
+ PORT_BIT(0x01, IP_ACTIVE_LOW, IPT_KEYBOARD) PORT_CODE(KEYCODE_Y) PORT_CHAR('y') PORT_CHAR('Y')
PORT_START("ROW7")
- PORT_BIT(0x80, IP_ACTIVE_HIGH, IPT_KEYBOARD) PORT_CODE(KEYCODE_EQUALS) PORT_CHAR('=') PORT_CHAR('+')
- PORT_BIT(0x40, 0x00, IPT_UNUSED)
- PORT_BIT(0x20, IP_ACTIVE_HIGH, IPT_KEYBOARD) PORT_NAME("Return") PORT_CODE(KEYCODE_ENTER) PORT_CHAR(13)
- PORT_BIT(0x10, IP_ACTIVE_HIGH, IPT_KEYBOARD) PORT_CODE(KEYCODE_RSHIFT) PORT_CHAR(UCHAR_MAMEKEY(RSHIFT))
- PORT_BIT(0x08, IP_ACTIVE_HIGH, IPT_KEYBOARD) PORT_CODE(KEYCODE_SLASH) PORT_CHAR('/') PORT_CHAR('?')
- PORT_BIT(0x04, IP_ACTIVE_HIGH, IPT_KEYBOARD) PORT_CODE(KEYCODE_0) PORT_CHAR('0') PORT_CHAR(')')
- PORT_BIT(0x02, IP_ACTIVE_HIGH, IPT_KEYBOARD) PORT_CODE(KEYCODE_L) PORT_CHAR('l') PORT_CHAR('L')
- PORT_BIT(0x01, IP_ACTIVE_HIGH, IPT_KEYBOARD) PORT_CODE(KEYCODE_8) PORT_CHAR('8') PORT_CHAR('*')
-
- PORT_START("FLOPPY")
- /* floppy interface */
- PORT_CONFNAME( 0x03, 0x00, "Floppy disc interface" )
- PORT_CONFSETTING( 0x00, DEF_STR( None ) )
- PORT_CONFSETTING( 0x01, "Microdisc" )
- PORT_CONFSETTING( 0x02, "Jasmin" )
-/* PORT_CONFSETTING( 0x03, "Low 8D DOS" ) */
-/* PORT_CONFSETTING( 0x04, "High 8D DOS" ) */
+ PORT_BIT(0x80, IP_ACTIVE_LOW, IPT_KEYBOARD) PORT_CODE(KEYCODE_EQUALS) PORT_CHAR('=') PORT_CHAR('+')
+ PORT_BIT(0x40, IP_ACTIVE_LOW, IPT_UNUSED)
+ PORT_BIT(0x20, IP_ACTIVE_LOW, IPT_KEYBOARD) PORT_NAME("Return") PORT_CODE(KEYCODE_ENTER) PORT_CHAR(13)
+ PORT_BIT(0x10, IP_ACTIVE_LOW, IPT_KEYBOARD) PORT_CODE(KEYCODE_RSHIFT) PORT_CHAR(UCHAR_MAMEKEY(RSHIFT))
+ PORT_BIT(0x08, IP_ACTIVE_LOW, IPT_KEYBOARD) PORT_CODE(KEYCODE_SLASH) PORT_CHAR('/') PORT_CHAR('?')
+ PORT_BIT(0x04, IP_ACTIVE_LOW, IPT_KEYBOARD) PORT_CODE(KEYCODE_0) PORT_CHAR('0') PORT_CHAR(')')
+ PORT_BIT(0x02, IP_ACTIVE_LOW, IPT_KEYBOARD) PORT_CODE(KEYCODE_L) PORT_CHAR('l') PORT_CHAR('L')
+ PORT_BIT(0x01, IP_ACTIVE_LOW, IPT_KEYBOARD) PORT_CODE(KEYCODE_8) PORT_CHAR('8') PORT_CHAR('*')
+
+ PORT_START("NMI")
+ PORT_BIT( 0x01, IP_ACTIVE_HIGH, IPT_KEYBOARD ) PORT_NAME("NMI") PORT_CODE(KEYCODE_F2) PORT_CHAR(UCHAR_MAMEKEY(F2)) PORT_CHANGED_MEMBER(DEVICE_SELF, oric_state, nmi_pressed, 0)
/* vsync cable hardware. This is a simple cable connected to the video output
to the monitor/television. The sync signal is connected to the cassette input
allowing interrupts to be generated from the vsync signal. */
- PORT_CONFNAME(0x08, 0x00, "Vsync cable hardware")
- PORT_CONFSETTING( 0x00, DEF_STR( Off ) )
- PORT_CONFSETTING( 0x08, DEF_STR( On ) )
- PORT_BIT(0x10, IP_ACTIVE_HIGH, IPT_CUSTOM) PORT_VBLANK("screen")
+ PORT_START("CONFIG")
+ PORT_CONFNAME(0x01, 0x00, "Tape input")
+ PORT_CONFSETTING( 0x00, "Tape")
+ PORT_CONFSETTING( 0x01, "VSync cable")
INPUT_PORTS_END
static INPUT_PORTS_START(orica)
PORT_INCLUDE( oric )
PORT_MODIFY("ROW5")
- PORT_BIT(0x10, IP_ACTIVE_HIGH, IPT_KEYBOARD) PORT_NAME("Funct") PORT_CODE(KEYCODE_END) PORT_CHAR(UCHAR_MAMEKEY(F1))
+ PORT_BIT(0x10, IP_ACTIVE_LOW, IPT_KEYBOARD) PORT_NAME("Funct") PORT_CODE(KEYCODE_LALT) PORT_CHAR(UCHAR_MAMEKEY(LALT))
INPUT_PORTS_END
static INPUT_PORTS_START(prav8d)
PORT_START("ROW0")
- PORT_BIT(0x80, IP_ACTIVE_HIGH, IPT_KEYBOARD) PORT_CODE(KEYCODE_3) PORT_CHAR('3') PORT_CHAR('#')
- PORT_BIT(0x40, IP_ACTIVE_HIGH, IPT_KEYBOARD) PORT_NAME("X \xd0\xac") PORT_CODE(KEYCODE_X) PORT_CHAR('X')
- PORT_BIT(0x20, IP_ACTIVE_HIGH, IPT_KEYBOARD) PORT_CODE(KEYCODE_1) PORT_CHAR('1') PORT_CHAR('!')
- PORT_BIT(0x10, IP_ACTIVE_HIGH, IPT_UNUSED)
- PORT_BIT(0x08, IP_ACTIVE_HIGH, IPT_KEYBOARD) PORT_NAME("V \xd0\x96") PORT_CODE(KEYCODE_V) PORT_CHAR('V')
- PORT_BIT(0x04, IP_ACTIVE_HIGH, IPT_KEYBOARD) PORT_CODE(KEYCODE_5) PORT_CHAR('5') PORT_CHAR('%')
- PORT_BIT(0x02, IP_ACTIVE_HIGH, IPT_KEYBOARD) PORT_NAME("N \xd0\x9d") PORT_CODE(KEYCODE_N) PORT_CHAR('N')
- PORT_BIT(0x01, IP_ACTIVE_HIGH, IPT_KEYBOARD) PORT_CODE(KEYCODE_7) PORT_CHAR('7') PORT_CHAR('\'')
+ PORT_BIT(0x80, IP_ACTIVE_LOW, IPT_KEYBOARD) PORT_CODE(KEYCODE_3) PORT_CHAR('3') PORT_CHAR('#')
+ PORT_BIT(0x40, IP_ACTIVE_LOW, IPT_KEYBOARD) PORT_NAME("X \xd0\xac") PORT_CODE(KEYCODE_X) PORT_CHAR('X')
+ PORT_BIT(0x20, IP_ACTIVE_LOW, IPT_KEYBOARD) PORT_CODE(KEYCODE_1) PORT_CHAR('1') PORT_CHAR('!')
+ PORT_BIT(0x10, IP_ACTIVE_LOW, IPT_UNUSED)
+ PORT_BIT(0x08, IP_ACTIVE_LOW, IPT_KEYBOARD) PORT_NAME("V \xd0\x96") PORT_CODE(KEYCODE_V) PORT_CHAR('V')
+ PORT_BIT(0x04, IP_ACTIVE_LOW, IPT_KEYBOARD) PORT_CODE(KEYCODE_5) PORT_CHAR('5') PORT_CHAR('%')
+ PORT_BIT(0x02, IP_ACTIVE_LOW, IPT_KEYBOARD) PORT_NAME("N \xd0\x9d") PORT_CODE(KEYCODE_N) PORT_CHAR('N')
+ PORT_BIT(0x01, IP_ACTIVE_LOW, IPT_KEYBOARD) PORT_CODE(KEYCODE_7) PORT_CHAR('7') PORT_CHAR('\'')
PORT_START("ROW1")
- PORT_BIT(0x80, IP_ACTIVE_HIGH, IPT_KEYBOARD) PORT_NAME("D \xd0\x94") PORT_CODE(KEYCODE_D) PORT_CHAR('D')
- PORT_BIT(0x40, IP_ACTIVE_HIGH, IPT_KEYBOARD) PORT_NAME("Q \xd0\xaf") PORT_CODE(KEYCODE_Q) PORT_CHAR('Q')
- PORT_BIT(0x20, IP_ACTIVE_HIGH, IPT_KEYBOARD) PORT_NAME("Esc") PORT_CODE(KEYCODE_ESC) PORT_CHAR(UCHAR_MAMEKEY(ESC))
- PORT_BIT(0x10, IP_ACTIVE_HIGH, IPT_UNUSED)
- PORT_BIT(0x08, IP_ACTIVE_HIGH, IPT_KEYBOARD) PORT_NAME("F \xd0\xa4") PORT_CODE(KEYCODE_F) PORT_CHAR('F')
- PORT_BIT(0x04, IP_ACTIVE_HIGH, IPT_KEYBOARD) PORT_NAME("R \xd0\xa0") PORT_CODE(KEYCODE_R) PORT_CHAR('R')
- PORT_BIT(0x02, IP_ACTIVE_HIGH, IPT_KEYBOARD) PORT_NAME("T \xd0\xa2") PORT_CODE(KEYCODE_T) PORT_CHAR('T')
- PORT_BIT(0x01, IP_ACTIVE_HIGH, IPT_KEYBOARD) PORT_NAME("J \xd0\x99") PORT_CODE(KEYCODE_J) PORT_CHAR('J')
+ PORT_BIT(0x80, IP_ACTIVE_LOW, IPT_KEYBOARD) PORT_NAME("D \xd0\x94") PORT_CODE(KEYCODE_D) PORT_CHAR('D')
+ PORT_BIT(0x40, IP_ACTIVE_LOW, IPT_KEYBOARD) PORT_NAME("Q \xd0\xaf") PORT_CODE(KEYCODE_Q) PORT_CHAR('Q')
+ PORT_BIT(0x20, IP_ACTIVE_LOW, IPT_KEYBOARD) PORT_NAME("Esc") PORT_CODE(KEYCODE_ESC) PORT_CHAR(UCHAR_MAMEKEY(ESC))
+ PORT_BIT(0x10, IP_ACTIVE_LOW, IPT_UNUSED)
+ PORT_BIT(0x08, IP_ACTIVE_LOW, IPT_KEYBOARD) PORT_NAME("F \xd0\xa4") PORT_CODE(KEYCODE_F) PORT_CHAR('F')
+ PORT_BIT(0x04, IP_ACTIVE_LOW, IPT_KEYBOARD) PORT_NAME("R \xd0\xa0") PORT_CODE(KEYCODE_R) PORT_CHAR('R')
+ PORT_BIT(0x02, IP_ACTIVE_LOW, IPT_KEYBOARD) PORT_NAME("T \xd0\xa2") PORT_CODE(KEYCODE_T) PORT_CHAR('T')
+ PORT_BIT(0x01, IP_ACTIVE_LOW, IPT_KEYBOARD) PORT_NAME("J \xd0\x99") PORT_CODE(KEYCODE_J) PORT_CHAR('J')
PORT_START("ROW2")
- PORT_BIT(0x80, IP_ACTIVE_HIGH, IPT_KEYBOARD) PORT_NAME("C \xd0\xa6") PORT_CODE(KEYCODE_C) PORT_CHAR('C')
- PORT_BIT(0x40, IP_ACTIVE_HIGH, IPT_KEYBOARD) PORT_CODE(KEYCODE_2) PORT_CHAR('2') PORT_CHAR('"')
- PORT_BIT(0x20, IP_ACTIVE_HIGH, IPT_KEYBOARD) PORT_NAME("Z \xd0\x97") PORT_CODE(KEYCODE_Z) PORT_CHAR('Z')
- PORT_BIT(0x10, IP_ACTIVE_HIGH, IPT_KEYBOARD) PORT_NAME("MK") PORT_CODE(KEYCODE_LCONTROL) PORT_CODE(KEYCODE_LCONTROL) PORT_CHAR(UCHAR_SHIFT_2)
- PORT_BIT(0x08, IP_ACTIVE_HIGH, IPT_KEYBOARD) PORT_CODE(KEYCODE_4) PORT_CHAR('4') PORT_CHAR('$')
- PORT_BIT(0x04, IP_ACTIVE_HIGH, IPT_KEYBOARD) PORT_NAME("B \xd0\x91") PORT_CODE(KEYCODE_B) PORT_CHAR('B')
- PORT_BIT(0x02, IP_ACTIVE_HIGH, IPT_KEYBOARD) PORT_CODE(KEYCODE_6) PORT_CHAR('6') PORT_CHAR('&')
- PORT_BIT(0x01, IP_ACTIVE_HIGH, IPT_KEYBOARD) PORT_NAME("M \xd0\x9c") PORT_CODE(KEYCODE_M) PORT_CHAR('M')
+ PORT_BIT(0x80, IP_ACTIVE_LOW, IPT_KEYBOARD) PORT_NAME("C \xd0\xa6") PORT_CODE(KEYCODE_C) PORT_CHAR('C')
+ PORT_BIT(0x40, IP_ACTIVE_LOW, IPT_KEYBOARD) PORT_CODE(KEYCODE_2) PORT_CHAR('2') PORT_CHAR('"')
+ PORT_BIT(0x20, IP_ACTIVE_LOW, IPT_KEYBOARD) PORT_NAME("Z \xd0\x97") PORT_CODE(KEYCODE_Z) PORT_CHAR('Z')
+ PORT_BIT(0x10, IP_ACTIVE_LOW, IPT_KEYBOARD) PORT_NAME("MK") PORT_CODE(KEYCODE_LCONTROL) PORT_CODE(KEYCODE_LCONTROL) PORT_CHAR(UCHAR_SHIFT_2)
+ PORT_BIT(0x08, IP_ACTIVE_LOW, IPT_KEYBOARD) PORT_CODE(KEYCODE_4) PORT_CHAR('4') PORT_CHAR('$')
+ PORT_BIT(0x04, IP_ACTIVE_LOW, IPT_KEYBOARD) PORT_NAME("B \xd0\x91") PORT_CODE(KEYCODE_B) PORT_CHAR('B')
+ PORT_BIT(0x02, IP_ACTIVE_LOW, IPT_KEYBOARD) PORT_CODE(KEYCODE_6) PORT_CHAR('6') PORT_CHAR('&')
+ PORT_BIT(0x01, IP_ACTIVE_LOW, IPT_KEYBOARD) PORT_NAME("M \xd0\x9c") PORT_CODE(KEYCODE_M) PORT_CHAR('M')
PORT_START("ROW3")
- PORT_BIT(0x80, IP_ACTIVE_HIGH, IPT_KEYBOARD) PORT_NAME("] \xd0\xa9") PORT_CODE(KEYCODE_QUOTE) PORT_CHAR(']')
- PORT_BIT(0x40, IP_ACTIVE_HIGH, IPT_KEYBOARD) PORT_CODE(KEYCODE_BACKSLASH2) PORT_CHAR(';') PORT_CHAR('+')
- PORT_BIT(0x20, IP_ACTIVE_HIGH, IPT_KEYBOARD) PORT_NAME("C/L") PORT_CODE(KEYCODE_CAPSLOCK) PORT_CHAR(UCHAR_MAMEKEY(CAPSLOCK)) // this one is 5th line, 1st key from right
- PORT_BIT(0x10, IP_ACTIVE_HIGH, IPT_UNUSED)
- PORT_BIT(0x08, IP_ACTIVE_HIGH, IPT_KEYBOARD) PORT_CODE(KEYCODE_MINUS) PORT_CHAR(':') PORT_CHAR('*')
- PORT_BIT(0x04, IP_ACTIVE_HIGH, IPT_KEYBOARD) PORT_NAME("[ \xd0\xa8") PORT_CODE(KEYCODE_COLON) PORT_CHAR('[')
- PORT_BIT(0x02, IP_ACTIVE_HIGH, IPT_KEYBOARD) PORT_CODE(KEYCODE_9) PORT_CHAR('9') PORT_CHAR(')')
- PORT_BIT(0x01, IP_ACTIVE_HIGH, IPT_KEYBOARD) PORT_NAME("K \xd0\x9a") PORT_CODE(KEYCODE_K) PORT_CHAR('K')
+ PORT_BIT(0x80, IP_ACTIVE_LOW, IPT_KEYBOARD) PORT_NAME("] \xd0\xa9") PORT_CODE(KEYCODE_QUOTE) PORT_CHAR(']')
+ PORT_BIT(0x40, IP_ACTIVE_LOW, IPT_KEYBOARD) PORT_CODE(KEYCODE_BACKSLASH2) PORT_CHAR(';') PORT_CHAR('+')
+ PORT_BIT(0x20, IP_ACTIVE_LOW, IPT_KEYBOARD) PORT_NAME("C/L") PORT_CODE(KEYCODE_CAPSLOCK) PORT_CHAR(UCHAR_MAMEKEY(CAPSLOCK)) // this one is 5th line, 1st key from right
+ PORT_BIT(0x10, IP_ACTIVE_LOW, IPT_UNUSED)
+ PORT_BIT(0x08, IP_ACTIVE_LOW, IPT_KEYBOARD) PORT_CODE(KEYCODE_MINUS) PORT_CHAR(':') PORT_CHAR('*')
+ PORT_BIT(0x04, IP_ACTIVE_LOW, IPT_KEYBOARD) PORT_NAME("[ \xd0\xa8") PORT_CODE(KEYCODE_COLON) PORT_CHAR('[')
+ PORT_BIT(0x02, IP_ACTIVE_LOW, IPT_KEYBOARD) PORT_CODE(KEYCODE_9) PORT_CHAR('9') PORT_CHAR(')')
+ PORT_BIT(0x01, IP_ACTIVE_LOW, IPT_KEYBOARD) PORT_NAME("K \xd0\x9a") PORT_CODE(KEYCODE_K) PORT_CHAR('K')
PORT_START("ROW4")
- PORT_BIT(0x80, IP_ACTIVE_HIGH, IPT_KEYBOARD) PORT_NAME(UTF8_RIGHT) PORT_CODE(KEYCODE_RIGHT) PORT_CHAR(UCHAR_MAMEKEY(RIGHT))
- PORT_BIT(0x40, IP_ACTIVE_HIGH, IPT_KEYBOARD) PORT_NAME(UTF8_DOWN) PORT_CODE(KEYCODE_DOWN) PORT_CHAR(UCHAR_MAMEKEY(DOWN))
- PORT_BIT(0x20, IP_ACTIVE_HIGH, IPT_KEYBOARD) PORT_NAME(UTF8_LEFT) PORT_CODE(KEYCODE_LEFT) PORT_CHAR(UCHAR_MAMEKEY(LEFT))
- PORT_BIT(0x10, IP_ACTIVE_HIGH, IPT_KEYBOARD) PORT_CODE(KEYCODE_LSHIFT) PORT_CHAR(UCHAR_MAMEKEY(LSHIFT))
- PORT_BIT(0x08, IP_ACTIVE_HIGH, IPT_KEYBOARD) PORT_NAME(UTF8_UP) PORT_CODE(KEYCODE_UP) PORT_CHAR(UCHAR_MAMEKEY(UP))
- PORT_BIT(0x04, IP_ACTIVE_HIGH, IPT_KEYBOARD) PORT_CODE(KEYCODE_STOP) PORT_CHAR('.') PORT_CHAR('>')
- PORT_BIT(0x02, IP_ACTIVE_HIGH, IPT_KEYBOARD) PORT_CODE(KEYCODE_COMMA) PORT_CHAR(',') PORT_CHAR('<')
- PORT_BIT(0x01, IP_ACTIVE_HIGH, IPT_KEYBOARD) PORT_CODE(KEYCODE_SPACE) PORT_CHAR(' ')
+ PORT_BIT(0x80, IP_ACTIVE_LOW, IPT_KEYBOARD) PORT_NAME(UTF8_RIGHT) PORT_CODE(KEYCODE_RIGHT) PORT_CHAR(UCHAR_MAMEKEY(RIGHT))
+ PORT_BIT(0x40, IP_ACTIVE_LOW, IPT_KEYBOARD) PORT_NAME(UTF8_DOWN) PORT_CODE(KEYCODE_DOWN) PORT_CHAR(UCHAR_MAMEKEY(DOWN))
+ PORT_BIT(0x20, IP_ACTIVE_LOW, IPT_KEYBOARD) PORT_NAME(UTF8_LEFT) PORT_CODE(KEYCODE_LEFT) PORT_CHAR(UCHAR_MAMEKEY(LEFT))
+ PORT_BIT(0x10, IP_ACTIVE_LOW, IPT_KEYBOARD) PORT_CODE(KEYCODE_LSHIFT) PORT_CHAR(UCHAR_MAMEKEY(LSHIFT))
+ PORT_BIT(0x08, IP_ACTIVE_LOW, IPT_KEYBOARD) PORT_NAME(UTF8_UP) PORT_CODE(KEYCODE_UP) PORT_CHAR(UCHAR_MAMEKEY(UP))
+ PORT_BIT(0x04, IP_ACTIVE_LOW, IPT_KEYBOARD) PORT_CODE(KEYCODE_STOP) PORT_CHAR('.') PORT_CHAR('>')
+ PORT_BIT(0x02, IP_ACTIVE_LOW, IPT_KEYBOARD) PORT_CODE(KEYCODE_COMMA) PORT_CHAR(',') PORT_CHAR('<')
+ PORT_BIT(0x01, IP_ACTIVE_LOW, IPT_KEYBOARD) PORT_CODE(KEYCODE_SPACE) PORT_CHAR(' ')
PORT_START("ROW5")
- PORT_BIT(0x80, IP_ACTIVE_HIGH, IPT_KEYBOARD) PORT_NAME("@ \xd0\xae") PORT_CODE(KEYCODE_OPENBRACE) PORT_CHAR('@')
- PORT_BIT(0x40, IP_ACTIVE_HIGH, IPT_KEYBOARD) PORT_NAME("\\ \xd0\xad") PORT_CODE(KEYCODE_CLOSEBRACE) PORT_CHAR('\\')
- PORT_BIT(0x20, IP_ACTIVE_HIGH, IPT_KEYBOARD) PORT_NAME("Del") PORT_CODE(KEYCODE_BACKSPACE) PORT_CHAR(8) // this one is 5th line, 1st key from left
- PORT_BIT(0x10, IP_ACTIVE_HIGH, IPT_UNUSED)
- PORT_BIT(0x08, IP_ACTIVE_HIGH, IPT_KEYBOARD) PORT_NAME("P \xd0\x9f") PORT_CODE(KEYCODE_P) PORT_CHAR('P')
- PORT_BIT(0x04, IP_ACTIVE_HIGH, IPT_KEYBOARD) PORT_NAME("O \xd0\x9e") PORT_CODE(KEYCODE_O) PORT_CHAR('O')
- PORT_BIT(0x02, IP_ACTIVE_HIGH, IPT_KEYBOARD) PORT_NAME("I \xd0\x98") PORT_CODE(KEYCODE_I) PORT_CHAR('I')
- PORT_BIT(0x01, IP_ACTIVE_HIGH, IPT_KEYBOARD) PORT_NAME("U \xd0\xa3") PORT_CODE(KEYCODE_U) PORT_CHAR('U')
+ PORT_BIT(0x80, IP_ACTIVE_LOW, IPT_KEYBOARD) PORT_NAME("@ \xd0\xae") PORT_CODE(KEYCODE_OPENBRACE) PORT_CHAR('@')
+ PORT_BIT(0x40, IP_ACTIVE_LOW, IPT_KEYBOARD) PORT_NAME("\\ \xd0\xad") PORT_CODE(KEYCODE_CLOSEBRACE) PORT_CHAR('\\')
+ PORT_BIT(0x20, IP_ACTIVE_LOW, IPT_KEYBOARD) PORT_NAME("Del") PORT_CODE(KEYCODE_BACKSPACE) PORT_CHAR(8) // this one is 5th line, 1st key from left
+ PORT_BIT(0x10, IP_ACTIVE_LOW, IPT_UNUSED)
+ PORT_BIT(0x08, IP_ACTIVE_LOW, IPT_KEYBOARD) PORT_NAME("P \xd0\x9f") PORT_CODE(KEYCODE_P) PORT_CHAR('P')
+ PORT_BIT(0x04, IP_ACTIVE_LOW, IPT_KEYBOARD) PORT_NAME("O \xd0\x9e") PORT_CODE(KEYCODE_O) PORT_CHAR('O')
+ PORT_BIT(0x02, IP_ACTIVE_LOW, IPT_KEYBOARD) PORT_NAME("I \xd0\x98") PORT_CODE(KEYCODE_I) PORT_CHAR('I')
+ PORT_BIT(0x01, IP_ACTIVE_LOW, IPT_KEYBOARD) PORT_NAME("U \xd0\xa3") PORT_CODE(KEYCODE_U) PORT_CHAR('U')
PORT_START("ROW6")
- PORT_BIT(0x80, IP_ACTIVE_HIGH, IPT_KEYBOARD) PORT_NAME("W \xd0\x92") PORT_CODE(KEYCODE_W) PORT_CHAR('W')
- PORT_BIT(0x40, IP_ACTIVE_HIGH, IPT_KEYBOARD) PORT_NAME("S \xd0\xa1") PORT_CODE(KEYCODE_S) PORT_CHAR('S')
- PORT_BIT(0x20, IP_ACTIVE_HIGH, IPT_KEYBOARD) PORT_NAME("A \xd0\x90") PORT_CODE(KEYCODE_A) PORT_CHAR('A')
- PORT_BIT(0x10, IP_ACTIVE_HIGH, IPT_UNUSED)
- PORT_BIT(0x08, IP_ACTIVE_HIGH, IPT_KEYBOARD) PORT_NAME("E \xd0\x95") PORT_CODE(KEYCODE_E) PORT_CHAR('E')
- PORT_BIT(0x04, IP_ACTIVE_HIGH, IPT_KEYBOARD) PORT_NAME("G \xd0\x93") PORT_CODE(KEYCODE_G) PORT_CHAR('G')
- PORT_BIT(0x02, IP_ACTIVE_HIGH, IPT_KEYBOARD) PORT_NAME("H \xd0\xa5") PORT_CODE(KEYCODE_H) PORT_CHAR('H')
- PORT_BIT(0x01, IP_ACTIVE_HIGH, IPT_KEYBOARD) PORT_NAME("Y \xd0\xaa") PORT_CODE(KEYCODE_Y) PORT_CHAR('Y')
+ PORT_BIT(0x80, IP_ACTIVE_LOW, IPT_KEYBOARD) PORT_NAME("W \xd0\x92") PORT_CODE(KEYCODE_W) PORT_CHAR('W')
+ PORT_BIT(0x40, IP_ACTIVE_LOW, IPT_KEYBOARD) PORT_NAME("S \xd0\xa1") PORT_CODE(KEYCODE_S) PORT_CHAR('S')
+ PORT_BIT(0x20, IP_ACTIVE_LOW, IPT_KEYBOARD) PORT_NAME("A \xd0\x90") PORT_CODE(KEYCODE_A) PORT_CHAR('A')
+ PORT_BIT(0x10, IP_ACTIVE_LOW, IPT_UNUSED)
+ PORT_BIT(0x08, IP_ACTIVE_LOW, IPT_KEYBOARD) PORT_NAME("E \xd0\x95") PORT_CODE(KEYCODE_E) PORT_CHAR('E')
+ PORT_BIT(0x04, IP_ACTIVE_LOW, IPT_KEYBOARD) PORT_NAME("G \xd0\x93") PORT_CODE(KEYCODE_G) PORT_CHAR('G')
+ PORT_BIT(0x02, IP_ACTIVE_LOW, IPT_KEYBOARD) PORT_NAME("H \xd0\xa5") PORT_CODE(KEYCODE_H) PORT_CHAR('H')
+ PORT_BIT(0x01, IP_ACTIVE_LOW, IPT_KEYBOARD) PORT_NAME("Y \xd0\xaa") PORT_CODE(KEYCODE_Y) PORT_CHAR('Y')
PORT_START("ROW7")
- PORT_BIT(0x80, IP_ACTIVE_HIGH, IPT_KEYBOARD) PORT_CODE(KEYCODE_EQUALS) PORT_CHAR('-') PORT_CHAR('=')
- PORT_BIT(0x40, IP_ACTIVE_HIGH, IPT_KEYBOARD) PORT_NAME("^ \xd0\xa7") PORT_CODE(KEYCODE_BACKSLASH) PORT_CHAR('^') // this one would be on 2nd line, 3rd key from 'P'
- PORT_BIT(0x20, IP_ACTIVE_HIGH, IPT_KEYBOARD) PORT_NAME("Return") PORT_CODE(KEYCODE_ENTER) PORT_CHAR(13)
- PORT_BIT(0x10, IP_ACTIVE_HIGH, IPT_KEYBOARD) PORT_CODE(KEYCODE_RSHIFT) PORT_CHAR(UCHAR_MAMEKEY(RSHIFT))
- PORT_BIT(0x08, IP_ACTIVE_HIGH, IPT_KEYBOARD) PORT_CODE(KEYCODE_SLASH) PORT_CHAR('/') PORT_CHAR('?')
- PORT_BIT(0x04, IP_ACTIVE_HIGH, IPT_KEYBOARD) PORT_CODE(KEYCODE_0) PORT_CHAR('0')
- PORT_BIT(0x02, IP_ACTIVE_HIGH, IPT_KEYBOARD) PORT_NAME("L \xd0\x9b") PORT_CODE(KEYCODE_L) PORT_CHAR('L')
- PORT_BIT(0x01, IP_ACTIVE_HIGH, IPT_KEYBOARD) PORT_CODE(KEYCODE_8) PORT_CHAR('8') PORT_CHAR('(')
-
- PORT_START("FLOPPY")
- /* force apple2 disc interface for pravetz */
- PORT_START("oric_floppy_interface")
- PORT_CONFNAME( 0x07, 0x00, "Floppy disc interface" )
- PORT_CONFSETTING( 0x00, DEF_STR( None ) )
- PORT_CONFSETTING( 0x03, "Low 8D DOS" )
- PORT_CONFSETTING( 0x04, "High 8D DOS" )
+ PORT_BIT(0x80, IP_ACTIVE_LOW, IPT_KEYBOARD) PORT_CODE(KEYCODE_EQUALS) PORT_CHAR('-') PORT_CHAR('=')
+ PORT_BIT(0x40, IP_ACTIVE_LOW, IPT_KEYBOARD) PORT_NAME("^ \xd0\xa7") PORT_CODE(KEYCODE_BACKSLASH) PORT_CHAR('^') // this one would be on 2nd line, 3rd key from 'P'
+ PORT_BIT(0x20, IP_ACTIVE_LOW, IPT_KEYBOARD) PORT_NAME("Return") PORT_CODE(KEYCODE_ENTER) PORT_CHAR(13)
+ PORT_BIT(0x10, IP_ACTIVE_LOW, IPT_KEYBOARD) PORT_CODE(KEYCODE_RSHIFT) PORT_CHAR(UCHAR_MAMEKEY(RSHIFT))
+ PORT_BIT(0x08, IP_ACTIVE_LOW, IPT_KEYBOARD) PORT_CODE(KEYCODE_SLASH) PORT_CHAR('/') PORT_CHAR('?')
+ PORT_BIT(0x04, IP_ACTIVE_LOW, IPT_KEYBOARD) PORT_CODE(KEYCODE_0) PORT_CHAR('0')
+ PORT_BIT(0x02, IP_ACTIVE_LOW, IPT_KEYBOARD) PORT_NAME("L \xd0\x9b") PORT_CODE(KEYCODE_L) PORT_CHAR('L')
+ PORT_BIT(0x01, IP_ACTIVE_LOW, IPT_KEYBOARD) PORT_CODE(KEYCODE_8) PORT_CHAR('8') PORT_CHAR('(')
+
+ PORT_START("NMI")
+ PORT_BIT( 0x01, IP_ACTIVE_HIGH, IPT_KEYBOARD ) PORT_NAME("NMI") PORT_CODE(KEYCODE_F2) PORT_CHAR(UCHAR_MAMEKEY(F2)) PORT_CHANGED_MEMBER(DEVICE_SELF, oric_state, nmi_pressed, 0)
/* vsync cable hardware. This is a simple cable connected to the video output
to the monitor/television. The sync signal is connected to the cassette input
allowing interrupts to be generated from the vsync signal. */
- PORT_CONFNAME(0x08, 0x00, "Vsync cable hardware")
- PORT_CONFSETTING( 0x00, DEF_STR( Off ) )
- PORT_CONFSETTING( 0x08, DEF_STR( On ) )
- PORT_BIT(0x10, IP_ACTIVE_HIGH, IPT_CUSTOM) PORT_VBLANK("screen")
+ PORT_START("CONFIG")
+ PORT_CONFNAME(0x01, 0x00, "Tape input")
+ PORT_CONFSETTING( 0x00, "Tape")
+ PORT_CONFSETTING( 0x01, "VSync cable")
INPUT_PORTS_END
static INPUT_PORTS_START(telstrat)
- PORT_INCLUDE( oric )
-
- PORT_MODIFY("ROW5")
- PORT_BIT(0x10, IP_ACTIVE_HIGH, IPT_KEYBOARD) PORT_NAME("Funct") PORT_CODE(KEYCODE_END) PORT_CHAR(UCHAR_MAMEKEY(F1))
-
- PORT_MODIFY("FLOPPY")
- /* vsync cable hardware. This is a simple cable connected to the video output
- to the monitor/television. The sync signal is connected to the cassette input
- allowing interrupts to be generated from the vsync signal. */
- PORT_BIT(0x07, 0x00, IPT_UNUSED)
- PORT_CONFNAME(0x08, 0x00, "Vsync cable hardware")
- PORT_CONFSETTING( 0x00, DEF_STR( Off ) )
- PORT_CONFSETTING( 0x08, DEF_STR( On ) )
- PORT_BIT( 0x010, IP_ACTIVE_HIGH, IPT_CUSTOM) PORT_VBLANK("screen")
-
- PORT_START("JOY0") /* left joystick port */
- PORT_BIT(0x01, IP_ACTIVE_LOW, IPT_KEYBOARD) PORT_NAME("Joystick 0 Up") PORT_CODE(JOYCODE_X_RIGHT_SWITCH)
- PORT_BIT(0x02, IP_ACTIVE_LOW, IPT_KEYBOARD) PORT_NAME("Joystick 0 Down") PORT_CODE(JOYCODE_X_LEFT_SWITCH)
- PORT_BIT(0x04, IP_ACTIVE_LOW, IPT_KEYBOARD) PORT_NAME("Joystick 0 Left") PORT_CODE(JOYCODE_BUTTON1)
- PORT_BIT(0x08, IP_ACTIVE_LOW, IPT_KEYBOARD) PORT_NAME("Joystick 0 Right") PORT_CODE(JOYCODE_Y_DOWN_SWITCH)
- PORT_BIT(0x10, IP_ACTIVE_LOW, IPT_KEYBOARD) PORT_NAME("Joystick 0 Fire 1") PORT_CODE(JOYCODE_Y_UP_SWITCH)
-
- PORT_START("JOY1") /* right joystick port */
- PORT_BIT(0x01, IP_ACTIVE_LOW, IPT_KEYBOARD) PORT_NAME("Joystick 1 Up") PORT_CODE(JOYCODE_X_RIGHT_SWITCH)
- PORT_BIT(0x02, IP_ACTIVE_LOW, IPT_KEYBOARD) PORT_NAME("Joystick 1 Down") PORT_CODE(JOYCODE_X_LEFT_SWITCH)
- PORT_BIT(0x04, IP_ACTIVE_LOW, IPT_KEYBOARD) PORT_NAME("Joystick 1 Left") PORT_CODE(JOYCODE_BUTTON1)
- PORT_BIT(0x08, IP_ACTIVE_LOW, IPT_KEYBOARD) PORT_NAME("Joystick 1 Right") PORT_CODE(JOYCODE_Y_DOWN_SWITCH)
- PORT_BIT(0x10, IP_ACTIVE_LOW, IPT_KEYBOARD) PORT_NAME("Joystick 1 Fire 1") PORT_CODE(JOYCODE_Y_UP_SWITCH)
+ PORT_INCLUDE( orica )
+
+// The telestrat does not have the NMI button
+ PORT_MODIFY("NMI")
+ PORT_BIT( 0x01, IP_ACTIVE_HIGH, IPT_UNUSED)
+
+ PORT_START("JOY1") /* left joystick port */
+ PORT_BIT(0x01, IP_ACTIVE_LOW, IPT_JOYSTICK_RIGHT) PORT_8WAY PORT_PLAYER(1)
+ PORT_BIT(0x02, IP_ACTIVE_LOW, IPT_JOYSTICK_LEFT) PORT_8WAY PORT_PLAYER(1)
+ PORT_BIT(0x04, IP_ACTIVE_LOW, IPT_BUTTON1) PORT_PLAYER(1)
+ PORT_BIT(0x08, IP_ACTIVE_LOW, IPT_JOYSTICK_DOWN) PORT_8WAY PORT_PLAYER(1)
+ PORT_BIT(0x10, IP_ACTIVE_LOW, IPT_JOYSTICK_UP) PORT_8WAY PORT_PLAYER(1)
+
+ PORT_START("JOY2") /* right joystick port */
+ PORT_BIT(0x01, IP_ACTIVE_LOW, IPT_JOYSTICK_RIGHT) PORT_8WAY PORT_PLAYER(2)
+ PORT_BIT(0x02, IP_ACTIVE_LOW, IPT_JOYSTICK_LEFT) PORT_8WAY PORT_PLAYER(2)
+ PORT_BIT(0x04, IP_ACTIVE_LOW, IPT_BUTTON1) PORT_PLAYER(2)
+ PORT_BIT(0x08, IP_ACTIVE_LOW, IPT_JOYSTICK_DOWN) PORT_8WAY PORT_PLAYER(2)
+ PORT_BIT(0x10, IP_ACTIVE_LOW, IPT_JOYSTICK_UP) PORT_8WAY PORT_PLAYER(2)
INPUT_PORTS_END
-static const unsigned char oric_palette[8*3] =
-{
- 0x00, 0x00, 0x00, 0xff, 0x00, 0x00,
- 0x00, 0xff, 0x00, 0xff, 0xff, 0x00,
- 0x00, 0x00, 0xff, 0xff, 0x00, 0xff,
- 0x00, 0xff, 0xff, 0xff, 0xff, 0xff,
-};
-
-/* Initialise the palette */
-PALETTE_INIT_MEMBER(oric_state, oric)
-{
- int i;
-
- for ( i = 0; i < sizeof(oric_palette) / 3; i++ ) {
- palette.set_pen_color(i, oric_palette[i*3], oric_palette[i*3+1], oric_palette[i*3+2]);
- }
-}
-
-
-
static const ay8910_interface oric_ay_interface =
{
- AY8910_LEGACY_OUTPUT,
- AY8910_DEFAULT_LOADS,
+ AY8910_DISCRETE_OUTPUT,
+ { 4700, 4700, 4700},
DEVCB_NULL,
DEVCB_NULL,
- DEVCB_DRIVER_MEMBER(oric_state, oric_psg_porta_write),
+ DEVCB_DRIVER_MEMBER(oric_state, psg_a_w),
DEVCB_NULL,
};
@@ -340,39 +787,12 @@ static const cassette_interface oric_cassette_interface =
NULL
};
-static const floppy_interface oric1_floppy_interface =
-{
- DEVCB_NULL,
- DEVCB_NULL,
- DEVCB_NULL,
- DEVCB_NULL,
- DEVCB_NULL,
- FLOPPY_STANDARD_5_25_DSHD,
- LEGACY_FLOPPY_OPTIONS_NAME(oric),
- NULL,
- NULL
-};
-
-static const floppy_interface prav8d_floppy_interface =
-{
- DEVCB_NULL,
- DEVCB_NULL,
- DEVCB_NULL,
- DEVCB_NULL,
- DEVCB_NULL,
- FLOPPY_STANDARD_5_25_DSHD,
- LEGACY_FLOPPY_OPTIONS_NAME(apple2),
- NULL,
- NULL
-};
-
static MACHINE_CONFIG_START( oric, oric_state )
/* basic machine hardware */
- MCFG_CPU_ADD("maincpu", M6502, 1000000)
+ MCFG_CPU_ADD("maincpu", M6502, XTAL_12MHz/12)
MCFG_CPU_PROGRAM_MAP(oric_mem)
MCFG_QUANTUM_TIME(attotime::from_hz(60))
-
/* video hardware */
MCFG_SCREEN_ADD("screen", RASTER)
MCFG_SCREEN_REFRESH_RATE(60)
@@ -380,155 +800,166 @@ static MACHINE_CONFIG_START( oric, oric_state )
MCFG_SCREEN_SIZE(40*6, 28*8)
MCFG_SCREEN_VISIBLE_AREA(0, 40*6-1, 0, 28*8-1)
MCFG_SCREEN_UPDATE_DRIVER(oric_state, screen_update_oric)
- MCFG_SCREEN_PALETTE("palette")
-
- MCFG_PALETTE_ADD("palette", 8)
- MCFG_PALETTE_INIT_OWNER(oric_state, oric)
-
+ MCFG_SCREEN_VBLANK_DRIVER(oric_state, vblank_w)
/* sound hardware */
MCFG_SPEAKER_STANDARD_MONO("mono")
MCFG_SOUND_WAVE_ADD(WAVE_TAG, "cassette")
MCFG_SOUND_ROUTE(ALL_OUTPUTS, "mono", 0.25)
- MCFG_SOUND_ADD("ay8912", AY8912, 1000000)
+ MCFG_SOUND_ADD("ay8912", AY8912, XTAL_12MHz/12)
MCFG_SOUND_CONFIG(oric_ay_interface)
MCFG_SOUND_ROUTE(ALL_OUTPUTS, "mono", 0.25)
/* printer */
MCFG_CENTRONICS_ADD("centronics", centronics_printers, "image")
- MCFG_CENTRONICS_ACK_HANDLER(DEVWRITELINE("via6522_0", via6522_device, write_ca1))
-
+ MCFG_CENTRONICS_ACK_HANDLER(DEVWRITELINE("via6522", via6522_device, write_ca1))
MCFG_CENTRONICS_OUTPUT_LATCH_ADD("cent_data_out", "centronics")
/* cassette */
MCFG_CASSETTE_ADD( "cassette", oric_cassette_interface )
+ MCFG_TIMER_DRIVER_ADD_PERIODIC("tape_timer", oric_state, update_tape, attotime::from_hz(4800))
/* via */
- MCFG_DEVICE_ADD( "via6522_0", VIA6522, 1000000 )
- MCFG_VIA6522_READPA_HANDLER(READ8(oric_state, oric_via_in_a_func))
- MCFG_VIA6522_READPB_HANDLER(READ8(oric_state, oric_via_in_b_func))
- MCFG_VIA6522_WRITEPA_HANDLER(WRITE8(oric_state, oric_via_out_a_func))
- MCFG_VIA6522_WRITEPB_HANDLER(WRITE8(oric_state, oric_via_out_b_func))
- MCFG_VIA6522_CA2_HANDLER(WRITELINE(oric_state, oric_via_out_ca2_func))
- MCFG_VIA6522_CB2_HANDLER(WRITELINE(oric_state, oric_via_out_cb2_func))
- MCFG_VIA6522_IRQ_HANDLER(WRITELINE(oric_state, oric_via_irq_func))
-
- MCFG_WD1770_ADD("wd179x", oric_wd17xx_interface )
-
- MCFG_LEGACY_FLOPPY_4_DRIVES_ADD(oric1_floppy_interface)
+ MCFG_DEVICE_ADD( "via6522", VIA6522, XTAL_12MHz/12 )
+ MCFG_VIA6522_WRITEPA_HANDLER(WRITE8(oric_state, via_a_w))
+ MCFG_VIA6522_WRITEPB_HANDLER(WRITE8(oric_state, via_b_w))
+ MCFG_VIA6522_CA2_HANDLER(WRITELINE(oric_state, via_ca2_w))
+ MCFG_VIA6522_CB2_HANDLER(WRITELINE(oric_state, via_cb2_w))
+ MCFG_VIA6522_IRQ_HANDLER(WRITELINE(oric_state, via_irq_w))
+
+ /* extension port */
+ MCFG_ORICEXT_ADD( "ext", oricext_intf, NULL, "maincpu", WRITELINE(oric_state, ext_irq_w))
MACHINE_CONFIG_END
static MACHINE_CONFIG_DERIVED( prav8d, oric )
- MCFG_LEGACY_FLOPPY_4_DRIVES_REMOVE()
- MCFG_LEGACY_FLOPPY_DRIVE_ADD(FLOPPY_0, prav8d_floppy_interface)
MACHINE_CONFIG_END
-static MACHINE_CONFIG_DERIVED( telstrat, oric )
- MCFG_CPU_MODIFY( "maincpu" )
- MCFG_CPU_PROGRAM_MAP( telestrat_mem)
+FLOPPY_FORMATS_MEMBER( telestrat_state::floppy_formats )
+ FLOPPY_ORIC_DSK_FORMAT
+FLOPPY_FORMATS_END
+
+static SLOT_INTERFACE_START( telestrat_floppies )
+ SLOT_INTERFACE( "3dsdd", FLOPPY_3_DSDD )
+SLOT_INTERFACE_END
- MCFG_MACHINE_START_OVERRIDE(oric_state, telestrat )
+static MACHINE_CONFIG_DERIVED_CLASS( telstrat, oric, telestrat_state )
+ MCFG_CPU_MODIFY( "maincpu" )
+ MCFG_CPU_PROGRAM_MAP(telestrat_mem)
/* acia */
MCFG_DEVICE_ADD("acia", MOS6551, 0)
MCFG_MOS6551_XTAL(XTAL_1_8432MHz)
- MCFG_MOS6551_IRQ_HANDLER(WRITELINE(oric_state, telestrat_acia_callback))
+ MCFG_MOS6551_IRQ_HANDLER(WRITELINE(telestrat_state, acia_irq_w))
/* via */
- MCFG_DEVICE_ADD( "via6522_1", VIA6522, 1000000 )
- MCFG_VIA6522_READPA_HANDLER(READ8(oric_state, telestrat_via2_in_a_func))
- MCFG_VIA6522_READPB_HANDLER(READ8(oric_state, telestrat_via2_in_b_func))
- MCFG_VIA6522_WRITEPA_HANDLER(WRITE8(oric_state, telestrat_via2_out_a_func))
- MCFG_VIA6522_WRITEPB_HANDLER(WRITE8(oric_state, telestrat_via2_out_b_func))
- MCFG_VIA6522_IRQ_HANDLER(WRITELINE(oric_state, telestrat_via2_irq_func))
+ MCFG_DEVICE_ADD( "via6522_2", VIA6522, XTAL_12MHz/12 )
+ MCFG_VIA6522_WRITEPA_HANDLER(WRITE8(telestrat_state, via2_a_w))
+ MCFG_VIA6522_WRITEPB_HANDLER(WRITE8(telestrat_state, via2_b_w))
+ MCFG_VIA6522_CA2_HANDLER(WRITELINE(telestrat_state, via2_ca2_w))
+ MCFG_VIA6522_CB2_HANDLER(WRITELINE(telestrat_state, via2_cb2_w))
+ MCFG_VIA6522_IRQ_HANDLER(WRITELINE(telestrat_state, via2_irq_w))
+
+ /* microdisc */
+ MCFG_FD1793x_ADD("fdc", XTAL_8MHz/8)
+ MCFG_WD_FDC_INTRQ_CALLBACK(WRITELINE(telestrat_state, fdc_irq_w))
+ MCFG_WD_FDC_DRQ_CALLBACK(WRITELINE(telestrat_state, fdc_drq_w))
+ MCFG_WD_FDC_HLD_CALLBACK(WRITELINE(telestrat_state, fdc_hld_w))
+ MCFG_WD_FDC_FORCE_READY
+
+ MCFG_FLOPPY_DRIVE_ADD("fdc:0", telestrat_floppies, "3dsdd", telestrat_state::floppy_formats)
+ MCFG_FLOPPY_DRIVE_ADD("fdc:1", telestrat_floppies, NULL, telestrat_state::floppy_formats)
+ MCFG_FLOPPY_DRIVE_ADD("fdc:2", telestrat_floppies, NULL, telestrat_state::floppy_formats)
+ MCFG_FLOPPY_DRIVE_ADD("fdc:3", telestrat_floppies, NULL, telestrat_state::floppy_formats)
MACHINE_CONFIG_END
ROM_START(oric1)
- ROM_REGION(0x16800, "maincpu", 0) /* 0x10000 + 0x04000 + 0x02000 + 0x00800 */
- ROM_LOAD ("basic10.rom", 0x10000, 0x04000, CRC(f18710b4) SHA1(333116e6884d85aaa4dfc7578a91cceeea66d016))
- ROM_LOAD_OPTIONAL ("microdis.rom", 0x14000, 0x02000, CRC(a9664a9c) SHA1(0d2ef6e67322f48f4b7e08d8bbe68827e2074561) )
- ROM_LOAD_OPTIONAL ("jasmin.rom", 0x16000, 0x00800, CRC(37220e89) SHA1(70e59b8abd67092f050462abc6cb5271e4c15f01) )
+ ROM_REGION(0x4000, "maincpu", 0)
+ ROM_LOAD ("basic10.rom", 0, 0x04000, CRC(f18710b4) SHA1(333116e6884d85aaa4dfc7578a91cceeea66d016))
ROM_END
ROM_START(orica)
- ROM_REGION(0x16800, "maincpu", 0) /* 0x10000 + 0x04000 + 0x02000 + 0x00800 */
+ ROM_REGION(0x4000, "maincpu", 0)
ROM_SYSTEM_BIOS( 0, "ver11", "Basic 1.1")
- ROMX_LOAD ("basic11b.rom", 0x10000, 0x04000, CRC(c3a92bef) SHA1(9451a1a09d8f75944dbd6f91193fc360f1de80ac), ROM_BIOS(1) )
+ ROMX_LOAD ("basic11b.rom", 0, 0x04000, CRC(c3a92bef) SHA1(9451a1a09d8f75944dbd6f91193fc360f1de80ac), ROM_BIOS(1) )
ROM_SYSTEM_BIOS( 1, "ver12", "Basic 1.2 (Pascal Leclerc)") // 1987/1999 - various enhancements and bugfixes
- ROMX_LOAD ("basic12.rom", 0x10000, 0x04000, CRC(dc4f22dc) SHA1(845e1a893de3dc0f856fdf2f69c3b73770b4094f), ROM_BIOS(2) )
+ ROMX_LOAD ("basic12.rom", 0, 0x04000, CRC(dc4f22dc) SHA1(845e1a893de3dc0f856fdf2f69c3b73770b4094f), ROM_BIOS(2) )
ROM_SYSTEM_BIOS( 2, "ver121", "Basic 1.21 (Pascal Leclerc)") // 07.1999 - DRAW enhancement
- ROMX_LOAD ("basic121.rom", 0x10000, 0x04000, CRC(0a2860b1) SHA1(b727d5c3bbc8cb1d510f224eb1e0d90d609e8506), ROM_BIOS(3) )
+ ROMX_LOAD ("basic121.rom", 0, 0x04000, CRC(0a2860b1) SHA1(b727d5c3bbc8cb1d510f224eb1e0d90d609e8506), ROM_BIOS(3) )
ROM_SYSTEM_BIOS( 3, "ver122", "Basic 1.22 (Pascal Leclerc)") // 08.2001 - added EUR symbol
- ROMX_LOAD ("basic122.rom", 0x10000, 0x04000, CRC(5ef2a861) SHA1(9ab6dc47b6e9dc65a4137ce0f0f12fc2b6ca8442), ROM_BIOS(4) )
+ ROMX_LOAD ("basic122.rom", 0, 0x04000, CRC(5ef2a861) SHA1(9ab6dc47b6e9dc65a4137ce0f0f12fc2b6ca8442), ROM_BIOS(4) )
ROM_SYSTEM_BIOS( 4, "ver11de", "Basic 1.1 DE")
- ROMX_LOAD( "bas11_de.rom", 0x10000, 0x04000, CRC(65233b2d) SHA1(b01cabb1a21980a6785a2fe37a8f8572c892123f), ROM_BIOS(5))
+ ROMX_LOAD( "bas11_de.rom", 0, 0x04000, CRC(65233b2d) SHA1(b01cabb1a21980a6785a2fe37a8f8572c892123f), ROM_BIOS(5))
ROM_SYSTEM_BIOS( 5, "ver11es", "Basic 1.1 ES")
- ROMX_LOAD( "bas11_es.rom", 0x10000, 0x04000, CRC(47bf26c7) SHA1(4fdbadd68db9ab8ad1cd56b4e5cbe51a9c3f11ae), ROM_BIOS(6))
+ ROMX_LOAD( "bas11_es.rom", 0, 0x04000, CRC(47bf26c7) SHA1(4fdbadd68db9ab8ad1cd56b4e5cbe51a9c3f11ae), ROM_BIOS(6))
ROM_SYSTEM_BIOS( 6, "ver11fr", "Basic 1.1 FR")
- ROMX_LOAD( "bas11_fr.rom", 0x10000, 0x04000, CRC(603b1fbf) SHA1(2a4583df3b59ca454d67d5631f242c96ec4cf99a), ROM_BIOS(7))
+ ROMX_LOAD( "bas11_fr.rom", 0, 0x04000, CRC(603b1fbf) SHA1(2a4583df3b59ca454d67d5631f242c96ec4cf99a), ROM_BIOS(7))
ROM_SYSTEM_BIOS( 7, "ver11se", "Basic 1.1 SE")
- ROMX_LOAD( "bas11_se.rom", 0x10000, 0x04000, CRC(a71523ac) SHA1(ce53acf84baec6ab5cbac9f9cefa71b3efeb2ead), ROM_BIOS(8))
+ ROMX_LOAD( "bas11_se.rom", 0, 0x04000, CRC(a71523ac) SHA1(ce53acf84baec6ab5cbac9f9cefa71b3efeb2ead), ROM_BIOS(8))
ROM_SYSTEM_BIOS( 8, "ver11uk", "Basic 1.1 UK")
- ROMX_LOAD( "bas11_uk.rom", 0x10000, 0x04000, CRC(303370d1) SHA1(589ff66fac8e06d65af3369491faa67a71f1322a), ROM_BIOS(9))
+ ROMX_LOAD( "bas11_uk.rom", 0, 0x04000, CRC(303370d1) SHA1(589ff66fac8e06d65af3369491faa67a71f1322a), ROM_BIOS(9))
ROM_SYSTEM_BIOS( 9, "ver12es", "Basic 1.2 ES")
- ROMX_LOAD( "bas12es_le.rom", 0x10000, 0x04000, CRC(70de4aeb) SHA1(b327418aa7d8a5a03c135e3d8acdd511df625893), ROM_BIOS(10))
+ ROMX_LOAD( "bas12es_le.rom", 0, 0x04000, CRC(70de4aeb) SHA1(b327418aa7d8a5a03c135e3d8acdd511df625893), ROM_BIOS(10))
ROM_SYSTEM_BIOS( 10, "ver12fr", "Basic 1.2 FR")
- ROMX_LOAD( "bas12fr_le.rom", 0x10000, 0x04000, CRC(47a437fc) SHA1(70271bc3ed5c3bf4d339d6f5de3de8c3c50ff573), ROM_BIOS(11))
+ ROMX_LOAD( "bas12fr_le.rom", 0, 0x04000, CRC(47a437fc) SHA1(70271bc3ed5c3bf4d339d6f5de3de8c3c50ff573), ROM_BIOS(11))
ROM_SYSTEM_BIOS( 11, "ver12ge", "Basic 1.2 GE")
- ROMX_LOAD( "bas12ge_le.rom", 0x10000, 0x04000, CRC(f5f0dd52) SHA1(75359302452ee7b19537698f124aaefd333688d0), ROM_BIOS(12))
+ ROMX_LOAD( "bas12ge_le.rom", 0, 0x04000, CRC(f5f0dd52) SHA1(75359302452ee7b19537698f124aaefd333688d0), ROM_BIOS(12))
ROM_SYSTEM_BIOS( 12, "ver12sw", "Basic 1.2 SW")
- ROMX_LOAD( "bas12sw_le.rom", 0x10000, 0x04000, CRC(100abe68) SHA1(6211d5969c4d7a6acb86ed19c5e51a33a3bef431), ROM_BIOS(13))
+ ROMX_LOAD( "bas12sw_le.rom", 0, 0x04000, CRC(100abe68) SHA1(6211d5969c4d7a6acb86ed19c5e51a33a3bef431), ROM_BIOS(13))
ROM_SYSTEM_BIOS( 13, "ver12uk", "Basic 1.2 UK")
- ROMX_LOAD( "bas12uk_le.rom", 0x10000, 0x04000, CRC(00fce8a6) SHA1(d40558bdf61b8aba6260293c9424fd463be7fad8), ROM_BIOS(14))
+ ROMX_LOAD( "bas12uk_le.rom", 0, 0x04000, CRC(00fce8a6) SHA1(d40558bdf61b8aba6260293c9424fd463be7fad8), ROM_BIOS(14))
ROM_SYSTEM_BIOS( 14, "ver121es", "Basic 1.211 ES")
- ROMX_LOAD( "bas121es_le.rom", 0x10000, 0x04000, CRC(87ec679b) SHA1(5de6a5f5121f69069c9b93d678046e814b5b64e9), ROM_BIOS(15))
+ ROMX_LOAD( "bas121es_le.rom", 0, 0x04000, CRC(87ec679b) SHA1(5de6a5f5121f69069c9b93d678046e814b5b64e9), ROM_BIOS(15))
ROM_SYSTEM_BIOS( 15, "ver121fr", "Basic 1.211 FR")
- ROMX_LOAD( "bas121fr_le.rom", 0x10000, 0x04000, CRC(e683dec2) SHA1(20df7ebc0f13aa835f286d50137f1a7ff7430c29), ROM_BIOS(16))
+ ROMX_LOAD( "bas121fr_le.rom", 0, 0x04000, CRC(e683dec2) SHA1(20df7ebc0f13aa835f286d50137f1a7ff7430c29), ROM_BIOS(16))
ROM_SYSTEM_BIOS( 16, "ver121ge", "Basic 1.211 GE")
- ROMX_LOAD( "bas121ge_le.rom", 0x10000, 0x04000, CRC(94fe32bf) SHA1(1024776d20030d602e432e50014502524658643a), ROM_BIOS(17))
+ ROMX_LOAD( "bas121ge_le.rom", 0, 0x04000, CRC(94fe32bf) SHA1(1024776d20030d602e432e50014502524658643a), ROM_BIOS(17))
ROM_SYSTEM_BIOS( 17, "ver121sw", "Basic 1.211 SW")
- ROMX_LOAD( "bas121sw_le.rom", 0x10000, 0x04000, CRC(e6ad11c7) SHA1(309c94a9861fcb770636dcde1801a5c68ca819b4), ROM_BIOS(18))
+ ROMX_LOAD( "bas121sw_le.rom", 0, 0x04000, CRC(e6ad11c7) SHA1(309c94a9861fcb770636dcde1801a5c68ca819b4), ROM_BIOS(18))
ROM_SYSTEM_BIOS( 18, "ver121uk", "Basic 1.211 UK")
- ROMX_LOAD( "bas121uk_le.rom", 0x10000, 0x04000, CRC(75aa1aa9) SHA1(ca99e244d9cbef625344c2054023504a4f9dcfe4), ROM_BIOS(19))
+ ROMX_LOAD( "bas121uk_le.rom", 0, 0x04000, CRC(75aa1aa9) SHA1(ca99e244d9cbef625344c2054023504a4f9dcfe4), ROM_BIOS(19))
ROM_SYSTEM_BIOS( 19, "ver122es", "Basic 1.22 ES")
- ROMX_LOAD( "bas122es_le.rom", 0x10000, 0x04000, CRC(9144f9e0) SHA1(acf2094078af057e74a31d90d7010be51b9033fa), ROM_BIOS(20))
+ ROMX_LOAD( "bas122es_le.rom", 0, 0x04000, CRC(9144f9e0) SHA1(acf2094078af057e74a31d90d7010be51b9033fa), ROM_BIOS(20))
ROM_SYSTEM_BIOS( 20, "ver122fr", "Basic 1.22 FR")
- ROMX_LOAD( "bas122fr_le.rom", 0x10000, 0x04000, CRC(370cfda4) SHA1(fad9a0661256e59bcc2915578647573e4128e1bb), ROM_BIOS(21))
+ ROMX_LOAD( "bas122fr_le.rom", 0, 0x04000, CRC(370cfda4) SHA1(fad9a0661256e59bcc2915578647573e4128e1bb), ROM_BIOS(21))
ROM_SYSTEM_BIOS( 21, "ver122ge", "Basic 1.22 GE")
- ROMX_LOAD( "bas122ge_le.rom", 0x10000, 0x04000, CRC(9a42bd62) SHA1(8a9c80f314daf4e5e64fa202e583b8a65796db8b), ROM_BIOS(22))
+ ROMX_LOAD( "bas122ge_le.rom", 0, 0x04000, CRC(9a42bd62) SHA1(8a9c80f314daf4e5e64fa202e583b8a65796db8b), ROM_BIOS(22))
ROM_SYSTEM_BIOS( 22, "ver122sw", "Basic 1.22 SW")
- ROMX_LOAD( "bas122sw_le.rom", 0x10000, 0x04000, CRC(e7fd57a4) SHA1(c75cbf7cfafaa02712dc7ca2f972220aef86fb8d), ROM_BIOS(23))
+ ROMX_LOAD( "bas122sw_le.rom", 0, 0x04000, CRC(e7fd57a4) SHA1(c75cbf7cfafaa02712dc7ca2f972220aef86fb8d), ROM_BIOS(23))
ROM_SYSTEM_BIOS( 23, "ver122uk", "Basic 1.22 UK")
- ROMX_LOAD( "bas122uk_le.rom", 0x10000, 0x04000, CRC(9865bcd7) SHA1(2a92e2d119463e682bf10647e3880e26656d65b5), ROM_BIOS(24))
-
- ROM_LOAD_OPTIONAL ("microdis.rom", 0x14000, 0x02000, CRC(a9664a9c) SHA1(0d2ef6e67322f48f4b7e08d8bbe68827e2074561) )
- ROM_LOAD_OPTIONAL ("jasmin.rom", 0x16000, 0x00800, CRC(37220e89) SHA1(70e59b8abd67092f050462abc6cb5271e4c15f01) )
+ ROMX_LOAD( "bas122uk_le.rom", 0, 0x04000, CRC(9865bcd7) SHA1(2a92e2d119463e682bf10647e3880e26656d65b5), ROM_BIOS(24))
ROM_END
ROM_START(telstrat)
- ROM_REGION(0x30000, "maincpu", 0) /* 0x10000 + (0x04000 * 4) */
- ROM_LOAD ("telmatic.rom", 0x010000, 0x02000, CRC(94358dc6) SHA1(35f92a0477a88f5cf564971125047ffcfa02ec10) )
- ROM_LOAD ("teleass.rom", 0x014000, 0x04000, CRC(68b0fde6) SHA1(9e9af51dae3199cccf49ab3f0d47e2b9be4ba97d) )
- ROM_LOAD ("hyperbas.rom", 0x018000, 0x04000, CRC(1d96ab50) SHA1(f5f70a0eb59f8cd6c261e179ae78ef906f68ed63) )
- ROM_LOAD ("telmon24.rom", 0x01c000, 0x04000, CRC(aa727c5d) SHA1(86fc8dc0932f983efa199e31ae05a4424772f959) )
+ ROM_REGION(0x4000, "telmatic", 0)
+ ROM_LOAD ("telmatic.rom", 0, 0x2000, CRC(94358dc6) SHA1(35f92a0477a88f5cf564971125047ffcfa02ec10) )
+ ROM_RELOAD (0x2000, 0x2000)
+
+ ROM_REGION(0x4000, "teleass", 0)
+ ROM_LOAD ("teleass.rom", 0, 0x4000, CRC(68b0fde6) SHA1(9e9af51dae3199cccf49ab3f0d47e2b9be4ba97d) )
+
+ ROM_REGION(0x4000, "hyperbas", 0)
+ ROM_LOAD ("hyperbas.rom", 0, 0x4000, CRC(1d96ab50) SHA1(f5f70a0eb59f8cd6c261e179ae78ef906f68ed63) )
+
+ ROM_REGION(0x4000, "telmon24", 0)
+ ROM_LOAD ("telmon24.rom", 0, 0x4000, CRC(aa727c5d) SHA1(86fc8dc0932f983efa199e31ae05a4424772f959) )
ROM_END
ROM_START(prav8d)
- ROM_REGION(0x14300, "maincpu", 0) /* 0x10000 + 0x04000 + 0x00100 + 0x00200 */
- ROM_LOAD( "pravetzt.rom", 0x10000, 0x4000, CRC(58079502) SHA1(7afc276cb118adff72e4f16698f94bf3b2c64146) )
- ROM_LOAD_OPTIONAL( "8ddoslo.rom", 0x014000, 0x0100, CRC(0c82f636) SHA1(b29d151a0dfa3c7cd50439b51d0a8f95559bc2b6) )
- ROM_LOAD_OPTIONAL( "8ddoshi.rom", 0x014100, 0x0200, CRC(66309641) SHA1(9c2e82b3c4d385ade6215fcb89f8b92e6fd2bf4b) )
+ ROM_REGION(0x4000, "maincpu", 0) /* 0x10000 + 0x04000 + 0x00100 + 0x00200 */
+ ROM_LOAD( "pravetzt.rom", 0, 0x4000, CRC(58079502) SHA1(7afc276cb118adff72e4f16698f94bf3b2c64146) )
+// ROM_LOAD_OPTIONAL( "8ddoslo.rom", 0x014000, 0x0100, CRC(0c82f636) SHA1(b29d151a0dfa3c7cd50439b51d0a8f95559bc2b6) )
+// ROM_LOAD_OPTIONAL( "8ddoshi.rom", 0x014100, 0x0200, CRC(66309641) SHA1(9c2e82b3c4d385ade6215fcb89f8b92e6fd2bf4b) )
ROM_END
ROM_START(prav8dd)
- ROM_REGION(0x14300, "maincpu", 0) /* 0x10000 + 0x04000 + 0x00100 + 0x00200 */
+ ROM_REGION(0x4000, "maincpu", 0) /* 0x10000 + 0x04000 + 0x00100 + 0x00200 */
ROM_SYSTEM_BIOS( 0, "default", "Disk ROM, 1989")
- ROMX_LOAD( "8d.rom", 0x10000, 0x4000, CRC(b48973ef) SHA1(fd47c977fc215a3b577596a7483df53e8a1e9c83), ROM_BIOS(1) )
+ ROMX_LOAD( "8d.rom", 0, 0x4000, CRC(b48973ef) SHA1(fd47c977fc215a3b577596a7483df53e8a1e9c83), ROM_BIOS(1) )
ROM_SYSTEM_BIOS( 1, "radosoft", "RadoSoft Disk ROM, 1992")
- ROMX_LOAD( "pravetzd.rom", 0x10000, 0x4000, CRC(f8d23821) SHA1(f87ad3c5832773b6e0614905552a80c98dc8e2a5), ROM_BIOS(2) )
- ROM_LOAD_OPTIONAL( "8ddoslo.rom", 0x014000, 0x0100, CRC(0c82f636) SHA1(b29d151a0dfa3c7cd50439b51d0a8f95559bc2b6) )
- ROM_LOAD_OPTIONAL( "8ddoshi.rom", 0x014100, 0x0200, CRC(66309641) SHA1(9c2e82b3c4d385ade6215fcb89f8b92e6fd2bf4b) )
+ ROMX_LOAD( "pravetzd.rom", 0, 0x4000, CRC(f8d23821) SHA1(f87ad3c5832773b6e0614905552a80c98dc8e2a5), ROM_BIOS(2) )
+// ROM_LOAD_OPTIONAL( "8ddoslo.rom", 0x014000, 0x0100, CRC(0c82f636) SHA1(b29d151a0dfa3c7cd50439b51d0a8f95559bc2b6) )
+// ROM_LOAD_OPTIONAL( "8ddoshi.rom", 0x014100, 0x0200, CRC(66309641) SHA1(9c2e82b3c4d385ade6215fcb89f8b92e6fd2bf4b) )
ROM_END
@@ -537,4 +968,4 @@ COMP( 1983, oric1, 0, 0, oric, oric, driver_device, 0
COMP( 1984, orica, oric1, 0, oric, orica, driver_device, 0, "Tangerine", "Oric Atmos" , 0)
COMP( 1985, prav8d, oric1, 0, prav8d, prav8d, driver_device, 0, "Pravetz", "Pravetz 8D", 0)
COMP( 1989, prav8dd, oric1, 0, prav8d, prav8d, driver_device, 0, "Pravetz", "Pravetz 8D (Disk ROM)", GAME_UNOFFICIAL)
-COMP( 1986, telstrat, oric1, 0, telstrat, telstrat, driver_device, 0, "Tangerine", "Oric Telestrat", GAME_NOT_WORKING )
+COMP( 1986, telstrat, oric1, 0, telstrat, telstrat, driver_device, 0, "Tangerine", "Oric Telestrat", 0 )
diff --git a/src/mess/drivers/saturn.c b/src/mess/drivers/saturn.c
index 956da98c673..742518cd41a 100644
--- a/src/mess/drivers/saturn.c
+++ b/src/mess/drivers/saturn.c
@@ -818,8 +818,8 @@ void sat_console_state::saturn_init_driver(int rgn)
m_vdp2.pal = (rgn == 12) ? 1 : 0;
// set compatible options
- sh2drc_set_options(m_maincpu, SH2DRC_STRICT_VERIFY|SH2DRC_STRICT_PCREL);
- sh2drc_set_options(m_slave, SH2DRC_STRICT_VERIFY|SH2DRC_STRICT_PCREL);
+ m_maincpu->sh2drc_set_options(SH2DRC_STRICT_VERIFY|SH2DRC_STRICT_PCREL);
+ m_slave->sh2drc_set_options(SH2DRC_STRICT_VERIFY|SH2DRC_STRICT_PCREL);
/* amount of time to boost interleave for on MINIT / SINIT, needed for communication to work */
m_minit_boost = 400;
diff --git a/src/mess/includes/oric.h b/src/mess/includes/oric.h
deleted file mode 100644
index 97cfa666818..00000000000
--- a/src/mess/includes/oric.h
+++ /dev/null
@@ -1,204 +0,0 @@
-/*****************************************************************************
- *
- * includes/oric.h
- *
- ****************************************************************************/
-
-#ifndef ORIC_H_
-#define ORIC_H_
-
-#include "emu.h"
-#include "cpu/m6502/m6502.h"
-#include "sound/ay8910.h"
-#include "sound/wave.h"
-#include "machine/6522via.h"
-#include "machine/mos6551.h"
-#include "machine/buffer.h"
-#include "bus/centronics/ctronics.h"
-#include "machine/wd17xx.h"
-//#include <stdio.h>
-#include "machine/applefdc.h"
-#include "imagedev/flopdrv.h"
-#include "imagedev/cassette.h"
-#include "formats/oric_dsk.h"
-#include "formats/ap2_dsk.h"
-#include "formats/oric_tap.h"
-
-enum
-{
- TELESTRAT_MEM_BLOCK_UNDEFINED,
- TELESTRAT_MEM_BLOCK_RAM,
- TELESTRAT_MEM_BLOCK_ROM
-};
-
-struct telestrat_mem_block
-{
- int MemType;
- unsigned char *ptr;
-};
-
-
-/* current state of the display */
-/* some attributes persist until they are turned off.
-This structure holds this persistant information */
-struct oric_vh_state
-{
- /* foreground and background colour used for rendering */
- /* if flash attribute is set, these two will both be equal to background colour */
- UINT8 active_foreground_colour;
- UINT8 active_background_colour;
- /* current foreground and background colour */
- UINT8 foreground_colour;
- UINT8 background_colour;
- UINT8 mode;
- /* text attributes */
- UINT8 text_attributes;
-
- offs_t read_addr;
-
- /* current addr to fetch data */
- UINT8 *char_data;
- /* base of char data */
- UINT8 *char_base;
-
- /* if (1<<3), display graphics, if 0, hide graphics */
- /* current count */
- UINT8 flash_count;
-};
-
-
-class oric_state : public driver_device
-{
-public:
- oric_state(const machine_config &mconfig, device_type type, const char *tag)
- : driver_device(mconfig, type, tag),
- m_ram(*this, "ram"),
- m_maincpu(*this, "maincpu"),
- m_ay8912(*this, "ay8912"),
- m_centronics(*this, "centronics"),
- m_cent_data_out(*this, "cent_data_out"),
- m_cassette(*this, "cassette"),
- m_via6522_0(*this, "via6522_0"),
- m_region_maincpu(*this, "maincpu"),
- m_bank1(*this, "bank1"),
- m_bank2(*this, "bank2"),
- m_bank3(*this, "bank3"),
- m_bank4(NULL),
- m_bank5(*this, "bank5"),
- m_bank6(*this, "bank6"),
- m_bank7(*this, "bank7"),
- m_io_row0(*this, "ROW0"),
- m_io_row1(*this, "ROW1"),
- m_io_row2(*this, "ROW2"),
- m_io_row3(*this, "ROW3"),
- m_io_row4(*this, "ROW4"),
- m_io_row5(*this, "ROW5"),
- m_io_row6(*this, "ROW6"),
- m_io_row7(*this, "ROW7"),
- m_io_floppy(*this, "FLOPPY") { }
-
- optional_shared_ptr<UINT8> m_ram;
- bool m_is_telestrat;
- UINT8 m_irqs;
- UINT8 *m_ram_0x0c000;
- UINT8 m_keyboard_line;
- UINT8 m_key_sense_bit;
- UINT8 m_keyboard_mask;
- UINT8 m_via_port_a_data;
- UINT8 m_psg_control;
- UINT8 m_previous_portb_data;
- UINT8 m_port_3fa_w;
- UINT8 m_port_3fb_w;
- UINT8 m_wd179x_int_state;
- UINT8 m_port_314_r;
- UINT8 m_port_318_r;
- UINT8 m_port_314_w;
- UINT8 m_telestrat_bank_selection;
- UINT8 m_telestrat_via2_port_a_data;
- UINT8 m_telestrat_via2_port_b_data;
- telestrat_mem_block m_telestrat_blocks[8];
- oric_vh_state m_vh_state;
- DECLARE_WRITE8_MEMBER(oric_psg_porta_write);
- DECLARE_WRITE8_MEMBER(apple2_v2_interface_w);
- DECLARE_READ8_MEMBER(oric_jasmin_r);
- DECLARE_WRITE8_MEMBER(oric_jasmin_w);
- DECLARE_READ8_MEMBER(oric_microdisc_r);
- DECLARE_WRITE8_MEMBER(oric_microdisc_w);
- DECLARE_READ8_MEMBER(oric_IO_r);
- DECLARE_WRITE8_MEMBER(oric_IO_w);
- virtual void machine_start();
- virtual void machine_reset();
- virtual void video_start();
- DECLARE_PALETTE_INIT(oric);
- DECLARE_MACHINE_START(telestrat);
- UINT32 screen_update_oric(screen_device &screen, bitmap_ind16 &bitmap, const rectangle &cliprect);
- TIMER_CALLBACK_MEMBER(oric_refresh_tape);
- TIMER_CALLBACK_MEMBER(oric_vh_timer_callback);
- DECLARE_READ8_MEMBER(oric_via_in_a_func);
- DECLARE_READ8_MEMBER(oric_via_in_b_func);
- DECLARE_WRITE8_MEMBER(oric_via_out_a_func);
- DECLARE_WRITE8_MEMBER(oric_via_out_b_func);
- DECLARE_WRITE_LINE_MEMBER(oric_via_out_ca2_func);
- DECLARE_WRITE_LINE_MEMBER(oric_via_out_cb2_func);
- DECLARE_WRITE_LINE_MEMBER(oric_jasmin_wd179x_drq_w);
- DECLARE_WRITE_LINE_MEMBER(oric_microdisc_wd179x_intrq_w);
- DECLARE_WRITE_LINE_MEMBER(oric_microdisc_wd179x_drq_w);
- DECLARE_WRITE_LINE_MEMBER(oric_wd179x_intrq_w);
- DECLARE_WRITE_LINE_MEMBER(oric_wd179x_drq_w);
- DECLARE_WRITE_LINE_MEMBER(oric_via_irq_func);
- DECLARE_READ8_MEMBER(telestrat_via2_in_a_func);
- DECLARE_WRITE8_MEMBER(telestrat_via2_out_a_func);
- DECLARE_READ8_MEMBER(telestrat_via2_in_b_func);
- DECLARE_WRITE8_MEMBER(telestrat_via2_out_b_func);
- DECLARE_WRITE_LINE_MEMBER(telestrat_via2_irq_func);
- DECLARE_WRITE_LINE_MEMBER(telestrat_acia_callback);
-
-protected:
- required_device<cpu_device> m_maincpu;
- required_device<ay8910_device> m_ay8912;
- required_device<centronics_device> m_centronics;
- required_device<output_latch_device> m_cent_data_out;
- required_device<cassette_image_device> m_cassette;
- required_device<via6522_device> m_via6522_0;
- required_memory_region m_region_maincpu;
- required_memory_bank m_bank1;
- required_memory_bank m_bank2;
- optional_memory_bank m_bank3;
- memory_bank *m_bank4;
- optional_memory_bank m_bank5;
- optional_memory_bank m_bank6;
- optional_memory_bank m_bank7;
- required_ioport m_io_row0;
- required_ioport m_io_row1;
- required_ioport m_io_row2;
- required_ioport m_io_row3;
- required_ioport m_io_row4;
- required_ioport m_io_row5;
- required_ioport m_io_row6;
- required_ioport m_io_row7;
- required_ioport m_io_floppy;
-
- void oric_microdisc_refresh_wd179x_ints();
- void oric_refresh_ints();
- void oric_keyboard_sense_refresh();
- void oric_psg_connection_refresh(address_space &space);
- void oric_common_init_machine();
- void oric_install_apple2_interface();
- void oric_install_apple2_v2_interface();
- void oric_install_microdisc_interface();
- void oric_install_jasmin_interface();
- void oric_microdisc_set_mem_0x0c000();
- void telestrat_refresh_mem();
- void oric_enable_memory(int low, int high, int rd, int wr);
- void oric_jasmin_set_mem_0x0c000();
-
- void oric_vh_update_attribute(UINT8 c);
- void oric_vh_update_flash();
- void oric_refresh_charset();
- void oric_vh_render_6pixels(bitmap_ind16 &bitmap, int x, UINT8 y, UINT8 fg, UINT8 bg, UINT8 data, bool invert_flag);
-};
-
-/*----------- defined in machine/oric.c -----------*/
-extern const wd17xx_interface oric_wd17xx_interface;
-
-#endif /* ORIC_H_ */
diff --git a/src/mess/machine/mega32x.c b/src/mess/machine/mega32x.c
index 52af206c90a..048ef718ab7 100644
--- a/src/mess/machine/mega32x.c
+++ b/src/mess/machine/mega32x.c
@@ -575,8 +575,8 @@ WRITE16_MEMBER( sega_32x_device::_32x_dreq_common_w )
current_fifo_block = fifo_block_b;
current_fifo_readblock = fifo_block_a;
// incase we have a stalled DMA in progress, let the SH2 know there is data available
- sh2_notify_dma_data_available(m_master_cpu);
- sh2_notify_dma_data_available(m_slave_cpu);
+ m_master_cpu->sh2_notify_dma_data_available();
+ m_slave_cpu->sh2_notify_dma_data_available();
}
current_fifo_write_pos = 0;
@@ -590,8 +590,8 @@ WRITE16_MEMBER( sega_32x_device::_32x_dreq_common_w )
current_fifo_block = fifo_block_a;
current_fifo_readblock = fifo_block_b;
// incase we have a stalled DMA in progress, let the SH2 know there is data available
- sh2_notify_dma_data_available(m_master_cpu);
- sh2_notify_dma_data_available(m_slave_cpu);
+ m_master_cpu->sh2_notify_dma_data_available();
+ m_slave_cpu->sh2_notify_dma_data_available();
}
@@ -1931,8 +1931,8 @@ void sega_32x_device::device_reset()
// checking if these help brutal, they don't.
- sh2drc_set_options(m_master_cpu, SH2DRC_COMPATIBLE_OPTIONS);
- sh2drc_set_options(m_slave_cpu, SH2DRC_COMPATIBLE_OPTIONS);
+ m_master_cpu->sh2drc_set_options(SH2DRC_COMPATIBLE_OPTIONS);
+ m_slave_cpu->sh2drc_set_options(SH2DRC_COMPATIBLE_OPTIONS);
// install these now, otherwise we'll get the following (incorrect) warnings on startup..
diff --git a/src/mess/machine/mega32x.h b/src/mess/machine/mega32x.h
index ad10677c403..548c463195b 100644
--- a/src/mess/machine/mega32x.h
+++ b/src/mess/machine/mega32x.h
@@ -31,8 +31,8 @@ class sega_32x_device : public device_t
public:
sega_32x_device(const machine_config &mconfig, device_type type, const char *name, const char *tag, device_t *owner, UINT32 clock, const char *shortname, const char *source);
- required_device<cpu_device> m_master_cpu;
- required_device<cpu_device> m_slave_cpu;
+ required_device<sh2_device> m_master_cpu;
+ required_device<sh2_device> m_slave_cpu;
required_device<dac_device> m_lch_pwm;
required_device<dac_device> m_rch_pwm;
diff --git a/src/mess/machine/oric.c b/src/mess/machine/oric.c
deleted file mode 100644
index 9930f2a351d..00000000000
--- a/src/mess/machine/oric.c
+++ /dev/null
@@ -1,1357 +0,0 @@
-/*********************************************************************
-
- machine/oric.c
-
- Paul Cook
- Kev Thacker
-
- Thankyou to Fabrice Frances for his ORIC documentation which helped with this driver
- http://oric.ifrance.com/oric/
-
- TODO:
- - there are problems loading some .wav's. Try to fix these.
- - fix more graphics display problems
- - check the printer works
- - fix more disc drive/wd179x problems so more software will run
-
-*********************************************************************/
-
-
-#include "includes/oric.h"
-
-
-
-
-/* ==0 if oric1 or oric atmos, !=0 if telestrat */
-
-/* This does not exist in the real hardware. I have used it to
-know which sources are interrupting */
-/* bit 2 = telestrat 2nd via interrupt,
-1 = microdisc interface,
-0 = oric 1st via interrupt */
-
-enum
-{
- ORIC_FLOPPY_NONE,
- ORIC_FLOPPY_MFM_DISK,
- ORIC_FLOPPY_BASIC_DISK
-};
-
-/* type of disc interface connected to oric/oric atmos */
-/* telestrat always has a microdisc interface */
-enum
-{
- ORIC_FLOPPY_INTERFACE_NONE = 0,
- ORIC_FLOPPY_INTERFACE_MICRODISC = 1,
- ORIC_FLOPPY_INTERFACE_JASMIN = 2,
- ORIC_FLOPPY_INTERFACE_APPLE2 = 3,
- ORIC_FLOPPY_INTERFACE_APPLE2_V2 = 4
-};
-
-/* called when ints are changed - cleared/set */
-void oric_state::oric_refresh_ints()
-{
- /* telestrat has floppy hardware built-in! */
- if (m_is_telestrat==0)
- {
- /* oric 1 or oric atmos */
-
- /* if floppy disc hardware is disabled, do not allow interrupts from it */
- if ((m_io_floppy->manager().safe_to_read()) && ((m_io_floppy->read() & 0x07) == ORIC_FLOPPY_INTERFACE_NONE))
- {
- m_irqs &=~(1<<1);
- }
- }
-
- /* any irq set? */
- if (m_irqs & 0x0f)
- {
- m_maincpu->set_input_line(0, HOLD_LINE);
- }
- else
- {
- m_maincpu->set_input_line(0, CLEAR_LINE);
- }
-}
-
-
-
-/* index of keyboard line to scan */
-/* sense result */
-/* mask to read keys */
-
-
-
-
-
-/* refresh keyboard sense */
-void oric_state::oric_keyboard_sense_refresh()
-{
- /* The following assumes that if a 0 is written, it can be used to detect if any key has been pressed.. */
- /* for each bit that is 0, it combines it's pressed state with the pressed state so far */
-
- int i;
- unsigned char key_bit = 0;
-
- /* what if data is 0, can it sense if any of the keys on a line are pressed? */
- int input_port_data = 0;
-
- switch ( m_keyboard_line )
- {
- case 0: input_port_data = m_io_row0->read(); break;
- case 1: input_port_data = m_io_row1->read(); break;
- case 2: input_port_data = m_io_row2->read(); break;
- case 3: input_port_data = m_io_row3->read(); break;
- case 4: input_port_data = m_io_row4->read(); break;
- case 5: input_port_data = m_io_row5->read(); break;
- case 6: input_port_data = m_io_row6->read(); break;
- case 7: input_port_data = m_io_row7->read(); break;
- }
-
- /* go through all bits in line */
- for (i=0; i<8; i++)
- {
- /* sense this bit? */
- if (((~m_keyboard_mask) & (1<<i)) != 0)
- {
- /* is key pressed? */
- if (input_port_data & (1<<i))
- {
- /* yes */
- key_bit |= 1;
- }
- }
- }
-
- /* clear sense result */
- m_key_sense_bit = 0;
-
- /* any keys pressed on this line? */
- if (key_bit!=0)
- {
- /* set sense result */
- m_key_sense_bit = (1<<3);
- }
-}
-
-
-/* this is executed when a write to psg port a is done */
-WRITE8_MEMBER(oric_state::oric_psg_porta_write)
-{
- m_keyboard_mask = data;
-}
-
-
-/* PSG control pins */
-/* bit 1 = BDIR state */
-/* bit 0 = BC1 state */
-
-/* this port is also used to read printer data */
-READ8_MEMBER(oric_state::oric_via_in_a_func)
-{
- /*logerror("port a read\r\n"); */
-
- /* access psg? */
- if (m_psg_control!=0)
- {
- /* if psg is in read register state return reg data */
- if (m_psg_control==0x01)
- {
- return m_ay8912->data_r(space, 0);
- }
-
- /* return high-impedance */
- return 0x0ff;
- }
-
- /* correct?? */
- return m_via_port_a_data;
-}
-
-READ8_MEMBER(oric_state::oric_via_in_b_func)
-{
- int data;
-
- oric_keyboard_sense_refresh();
-
- data = m_key_sense_bit;
- data |= m_keyboard_line & 0x07;
-
- return data;
-}
-
-
-/* read/write data depending on state of bdir, bc1 pins and data output to psg */
-void oric_state::oric_psg_connection_refresh(address_space &space)
-{
- if (m_psg_control!=0)
- {
- switch (m_psg_control)
- {
- /* PSG inactive */
- case 0:
- break;
-
- /* read register data */
- case 1:
- //m_via_port_a_data = ay8910_read_port_0_r(space, 0);
- break;
-
- /* write register data */
- case 2:
- m_ay8912->data_w(space, 0, m_via_port_a_data);
- break;
-
- /* write register index */
- case 3:
- m_ay8912->address_w(space, 0, m_via_port_a_data);
- break;
-
- default:
- break;
- }
-
- return;
- }
-}
-
-WRITE8_MEMBER(oric_state::oric_via_out_a_func)
-{
- m_via_port_a_data = data;
-
- oric_psg_connection_refresh(space);
-
- if (m_psg_control==0)
- {
- /* if psg not selected, write to printer */
- m_cent_data_out->write(space, 0, data);
- }
-}
-
-/*
-PB0..PB2
- keyboard lines-demultiplexer line 7
-
-PB3
- keyboard sense line 0
-
-PB4
- printer strobe line 1
-
-PB5
- (not connected) ?? 1
-
-PB6
- tape connector motor control 0
-
-PB7
- tape connector output high 1
-
- */
-
-
-/* not called yet - this will update the via with the state of the tape data.
-This allows the via to trigger on bit changes and issue interrupts */
-TIMER_CALLBACK_MEMBER(oric_state::oric_refresh_tape)
-{
- int data;
- int input_port_9;
-
- data = 0;
-
- if (m_cassette->input() > 0.0038)
- {
- data |= 1;
- }
-
- /* "A simple cable to catch the vertical retrace signal !
- This cable connects the video output for the television/monitor
- to the via cb1 input. Interrupts can be generated from the vertical
- sync, and flicker free games can be produced */
-
- input_port_9 = m_io_floppy->read();
- /* cable is enabled? */
- if ((input_port_9 & 0x08)!=0)
- {
- /* return state of vsync */
- data = input_port_9>>4;
- }
-
- m_via6522_0->write_cb1(data);
-}
-
-WRITE8_MEMBER(oric_state::oric_via_out_b_func)
-{
- /* KEYBOARD */
- m_keyboard_line = data & 0x07;
-
- /* CASSETTE */
- /* cassette motor control */
- m_cassette->change_state(
- (data & 0x40) ? CASSETTE_MOTOR_ENABLED : CASSETTE_MOTOR_DISABLED,
- CASSETTE_MOTOR_DISABLED);
-
- /* cassette data out */
- m_cassette->output((data & (1<<7)) ? -1.0 : +1.0);
-
- /* centronics STROBE is connected to PB4 */
- m_centronics->write_strobe(BIT(data, 4));
-
- oric_psg_connection_refresh(space);
- m_previous_portb_data = data;
-}
-
-
-WRITE_LINE_MEMBER(oric_state::oric_via_out_ca2_func)
-{
- if (state)
- m_psg_control |=1;
- else
- m_psg_control &=~1;
-
- oric_psg_connection_refresh(generic_space());
-}
-
-WRITE_LINE_MEMBER(oric_state::oric_via_out_cb2_func)
-{
- if (state)
- m_psg_control |=2;
- else
- m_psg_control &=~2;
-
- oric_psg_connection_refresh(generic_space());
-}
-
-
-WRITE_LINE_MEMBER(oric_state::oric_via_irq_func)
-{
- m_irqs &= ~(1<<0);
-
- if (state)
- {
- m_irqs |=(1<<0);
- }
-
- oric_refresh_ints();
-}
-
-
-/*
-VIA Lines
- Oric usage
-
-PA0..PA7
- PSG data bus, printer data lines
-
-CA1
- printer acknowledge line
-
-CA2
- PSG BC1 line
-
-PB0..PB2
- keyboard lines-demultiplexer
-
-PB3
- keyboard sense line
-
-PB4
- printer strobe line
-
-PB5
- (not connected)
-
-PB6
- tape connector motor control
-
-PB7
- tape connector output
-
-CB1
- tape connector input
-
-CB2
- PSG BDIR line
-
-*/
-
-
-
-
-/*********************/
-/* APPLE 2 INTERFACE */
-
-/*
-apple2 disc drive accessed through 0x0310-0x031f (read/write)
-oric via accessed through 0x0300-0x030f. (read/write)
-disk interface rom accessed through 0x0320-0x03ff (read only)
-
-CALL &320 to start, or use BOBY rom.
-*/
-
-void oric_state::oric_install_apple2_interface()
-{
- applefdc_base_device *fdc = machine().device<applefdc_base_device>("fdc");
- address_space &space = m_maincpu->space(AS_PROGRAM);
-
- if (m_is_telestrat)
- {
- return;
- }
-
- space.install_read_handler(0x0300, 0x030f, read8_delegate(FUNC(oric_state::oric_IO_r), this));
- space.install_read_handler(0x0310, 0x031f, read8_delegate(FUNC(applefdc_base_device::read), fdc));
- space.install_read_bank(0x0320, 0x03ff, "bank4");
- m_bank4 = membank("bank4");
-
- space.install_write_handler(0x0300, 0x030f, write8_delegate(FUNC(oric_state::oric_IO_w), this));
- space.install_write_handler(0x0310, 0x031f, write8_delegate(FUNC(applefdc_base_device::write), fdc));
- m_bank4->set_base( m_region_maincpu->base() + 0x014000 + 0x020);
-}
-
-
-void oric_state::oric_enable_memory(int low, int high, int rd, int wr)
-{
- int i;
- address_space &space = m_maincpu->space(AS_PROGRAM);
-
- if (m_is_telestrat)
- {
- return;
- }
-
- for (i = low; i <= high; i++)
- {
- switch(i) {
- case 1:
- if (rd) {
- space.install_read_bank(0xc000, 0xdfff, "bank1");
- } else {
- space.nop_read(0xc000, 0xdfff);
- }
- if (wr) {
- space.install_write_bank(0xc000, 0xdfff, "bank5");
- } else {
- space.unmap_write(0xc000, 0xdfff);
- }
- break;
- case 2:
- if (rd) {
- space.install_read_bank(0xe000, 0xf7ff, "bank2");
- } else {
- space.nop_read(0xe000, 0xf7ff);
- }
- if (wr) {
- space.install_write_bank(0xe000, 0xf7ff, "bank6");
- } else {
- space.unmap_write(0xe000, 0xf7ff);
- }
- break;
- case 3:
- if (rd) {
- space.install_read_bank(0xf800, 0xffff, "bank3");
- } else {
- space.nop_read(0xf800, 0xffff);
- }
- break;
- }
- }
-}
-
-
-
-/************************/
-/* APPLE 2 INTERFACE V2 */
-
-/*
-apple2 disc drive accessed through 0x0310-0x031f (read/write)
-oric via accessed through 0x0300-0x030f. (read/write)
-disk interface rom accessed through 0x0320-0x03ff (read only)
-v2 registers accessed through 0x0380-0x0383 (write only)
-
-CALL &320 to start, or use BOBY rom.
-*/
-
-WRITE8_MEMBER(oric_state::apple2_v2_interface_w)
-{
- /* data is ignored, address is used to decode operation */
- if (m_is_telestrat)
- return;
-
-/* logerror("apple 2 interface v2 rom page: %01x\n",(offset & 0x02)>>1); */
-
- /* bit 0 is 0 for page 0, 1 for page 1 */
- m_bank4->set_base(m_region_maincpu->base() + 0x014000 + 0x0100 + (((offset & 0x02)>>1)<<8));
-
- oric_enable_memory(1, 3, TRUE, TRUE);
-
- /* bit 1 is 0, rom enabled, bit 1 is 1 ram enabled */
- if ((offset & 0x01)==0)
- {
- unsigned char *rom_ptr;
-
- /* logerror("apple 2 interface v2: rom enabled\n"); */
-
- /* enable rom */
- rom_ptr = m_region_maincpu->base() + 0x010000;
- m_bank1->set_base(rom_ptr);
- m_bank2->set_base(rom_ptr+0x02000);
- m_bank3->set_base(rom_ptr+0x03800);
- m_bank5->set_base(m_ram_0x0c000);
- m_bank6->set_base(m_ram_0x0c000+0x02000);
- m_bank7->set_base(m_ram_0x0c000+0x03800);
- }
- else
- {
- /*logerror("apple 2 interface v2: ram enabled\n"); */
-
- /* enable ram */
- m_bank1->set_base(m_ram_0x0c000);
- m_bank2->set_base(m_ram_0x0c000+0x02000);
- m_bank3->set_base(m_ram_0x0c000+0x03800);
- m_bank5->set_base(m_ram_0x0c000);
- m_bank6->set_base(m_ram_0x0c000+0x02000);
- m_bank7->set_base(m_ram_0x0c000+0x03800);
- }
-}
-
-
-/* APPLE 2 INTERFACE V2 */
-void oric_state::oric_install_apple2_v2_interface()
-{
- applefdc_base_device *fdc = machine().device<applefdc_base_device>("fdc");
- address_space &space = m_maincpu->space(AS_PROGRAM);
-
- space.install_read_handler(0x0300, 0x030f, read8_delegate(FUNC(oric_state::oric_IO_r), this));
- space.install_read_handler(0x0310, 0x031f, read8_delegate(FUNC(applefdc_base_device::read), fdc));
- space.install_read_bank(0x0320, 0x03ff, "bank4");
- m_bank4 = membank("bank4");
-
- space.install_write_handler(0x0300, 0x030f, write8_delegate(FUNC(oric_state::oric_IO_w), this));
- space.install_write_handler(0x0310, 0x031f, write8_delegate(FUNC(applefdc_base_device::write), fdc));
- space.install_write_handler(0x0380, 0x0383, write8_delegate(FUNC(oric_state::apple2_v2_interface_w),this));
-
- apple2_v2_interface_w(space, 0, 0);
-}
-
-/********************/
-/* JASMIN INTERFACE */
-
-
-/* bit 0: overlay ram access (1 means overlay ram enabled) */
-
-/* bit 0: ROMDIS (1 means internal Basic rom disabled) */
-
-
-void oric_state::oric_jasmin_set_mem_0x0c000()
-{
- /* assumption:
- 1. It is possible to access all 16k overlay ram.
- 2. If os is enabled, and overlay ram is enabled, all 16k can be accessed.
- 3. if os is disabled, and overlay ram is enabled, jasmin rom takes priority.
- */
- if (m_is_telestrat)
- {
- return;
- }
-
- /* the ram is disabled in the jasmin rom which indicates that jasmin takes
- priority over the ram */
-
- /* basic rom disabled? */
- if ((m_port_3fb_w & 0x01)==0)
- {
- /* no, it is enabled! */
-
- /* overlay ram enabled? */
- if ((m_port_3fa_w & 0x01)==0)
- {
- unsigned char *rom_ptr;
-
- /* no it is disabled */
- /*logerror("&c000-&ffff is os rom\n"); */
-
- oric_enable_memory(1, 3, TRUE, FALSE);
-
- rom_ptr = m_region_maincpu->base() + 0x010000;
- m_bank1->set_base(rom_ptr);
- m_bank2->set_base(rom_ptr+0x02000);
- m_bank3->set_base(rom_ptr+0x03800);
- }
- else
- {
- /*logerror("&c000-&ffff is ram\n"); */
-
- oric_enable_memory(1, 3, TRUE, TRUE);
-
- m_bank1->set_base(m_ram_0x0c000);
- m_bank2->set_base(m_ram_0x0c000+0x02000);
- m_bank3->set_base(m_ram_0x0c000+0x03800);
- m_bank5->set_base(m_ram_0x0c000);
- m_bank6->set_base(m_ram_0x0c000+0x02000);
- m_bank7->set_base(m_ram_0x0c000+0x03800);
- }
- }
- else
- {
- /* yes, basic rom is disabled */
-
- if ((m_port_3fa_w & 0x01)==0)
- {
- /* overlay ram disabled */
-
- /*logerror("&c000-&f8ff is nothing!\n"); */
- oric_enable_memory(1, 2, FALSE, FALSE);
- }
- else
- {
- /*logerror("&c000-&f8ff is ram!\n"); */
- oric_enable_memory(1, 2, TRUE, TRUE);
-
- m_bank1->set_base(m_ram_0x0c000);
- m_bank2->set_base(m_ram_0x0c000+0x02000);
- m_bank5->set_base(m_ram_0x0c000);
- m_bank6->set_base(m_ram_0x0c000+0x02000);
- }
-
- {
- /* basic rom disabled */
- unsigned char *rom_ptr;
-
- /*logerror("&f800-&ffff is jasmin rom\n"); */
- /* jasmin rom enabled */
- oric_enable_memory(3, 3, TRUE, TRUE);
- rom_ptr = m_region_maincpu->base() + 0x010000+0x04000+0x02000;
- m_bank3->set_base(rom_ptr);
- m_bank7->set_base(rom_ptr);
- }
- }
-}
-
-/* DRQ is connected to interrupt */
-WRITE_LINE_MEMBER(oric_state::oric_jasmin_wd179x_drq_w)
-{
- if (state)
- m_irqs |= (1<<1);
- else
- m_irqs &=~(1<<1);
-
- oric_refresh_ints();
-}
-
-READ8_MEMBER(oric_state::oric_jasmin_r)
-{
- wd1770_device *fdc = machine().device<wd1770_device>("wd179x");
- unsigned char data = 0x0ff;
-
- switch (offset & 0x0f)
- {
- /* jasmin floppy disc interface */
- case 0x04:
- data = fdc->status_r(space, 0);
- break;
- case 0x05:
- data = fdc->track_r(space, 0);
- break;
- case 0x06:
- data = fdc->sector_r(space, 0);
- break;
- case 0x07:
- data = fdc->data_r(space, 0);
- break;
- default:
- data = m_via6522_0->read(space,offset & 0x0f);
- //logerror("unhandled io read: %04x %02x\n", offset, data);
- break;
-
- }
-
- return data;
-}
-
-WRITE8_MEMBER(oric_state::oric_jasmin_w)
-{
- wd1770_device *fdc = machine().device<wd1770_device>("wd179x");
- switch (offset & 0x0f)
- {
- /* microdisc floppy disc interface */
- case 0x04:
- fdc->command_w( space, 0, data);
- break;
- case 0x05:
- fdc->track_w(space, 0, data);
- break;
- case 0x06:
- fdc->sector_w(space, 0, data);
- break;
- case 0x07:
- fdc->data_w(space, 0, data);
- break;
- /* bit 0 = side */
- case 0x08:
- fdc->set_side(data & 0x01);
- break;
- /* any write will cause wd179x to reset */
- case 0x09:
- fdc->reset();
- break;
- case 0x0a:
- //logerror("jasmin overlay ram w: %02x PC: %04x\n", data, m_maincpu->pc());
- m_port_3fa_w = data;
- oric_jasmin_set_mem_0x0c000();
- break;
- case 0x0b:
- //logerror("jasmin romdis w: %02x PC: %04x\n", data, m_maincpu->pc());
- m_port_3fb_w = data;
- oric_jasmin_set_mem_0x0c000();
- break;
- /* bit 0,1 of addr is the drive */
- case 0x0c:
- case 0x0d:
- case 0x0e:
- case 0x0f:
- fdc->set_drive(offset & 0x03);
- break;
-
- default:
- m_via6522_0->write(space,offset & 0x0f, data);
- break;
- }
-}
-
-
-void oric_state::oric_install_jasmin_interface()
-{
- address_space &space = m_maincpu->space(AS_PROGRAM);
- /* romdis */
- m_port_3fb_w = 1;
- oric_jasmin_set_mem_0x0c000();
-
- space.install_read_handler(0x0300, 0x03ef, read8_delegate(FUNC(oric_state::oric_IO_r),this));
- space.install_read_handler(0x03f0, 0x03ff, read8_delegate(FUNC(oric_state::oric_jasmin_r),this));
-
- space.install_write_handler(0x0300, 0x03ef, write8_delegate(FUNC(oric_state::oric_IO_w),this));
- space.install_write_handler(0x03f0, 0x03ff, write8_delegate(FUNC(oric_state::oric_jasmin_w),this));
-}
-
-/*********************************/
-/* MICRODISC INTERFACE variables */
-
-/* used by Microdisc interfaces */
-
-/* bit 7 is intrq state */
-/* bit 7 is drq state (active low) */
-/* bit 6,5: drive */
-/* bit 4: side */
-/* bit 3: double density enable */
-/* bit 0: enable FDC IRQ to trigger IRQ on CPU */
-
-
-void oric_state::oric_microdisc_refresh_wd179x_ints()
-{
- m_irqs &=~(1<<1);
-
- if ((m_wd179x_int_state) && (m_port_314_w & (1<<0)))
- {
- /*logerror("oric microdisc interrupt\n"); */
-
- m_irqs |=(1<<1);
- }
-
- oric_refresh_ints();
-}
-
-WRITE_LINE_MEMBER(oric_state::oric_microdisc_wd179x_intrq_w)
-{
- m_wd179x_int_state = state;
-
- if (state)
- m_port_314_r &= ~(1<<7);
- else
- m_port_314_r |=(1<<7);
-
- oric_microdisc_refresh_wd179x_ints();
-}
-
-WRITE_LINE_MEMBER(oric_state::oric_microdisc_wd179x_drq_w)
-{
- if (state)
- m_port_318_r &=~(1<<7);
- else
- m_port_318_r |= (1<<7);
-}
-
-void oric_state::oric_microdisc_set_mem_0x0c000()
-{
- if (m_is_telestrat)
- {
- return;
- }
-
- /* for 0x0c000-0x0dfff: */
- /* if os disabled, ram takes priority */
- /* /ROMDIS */
- if ((m_port_314_w & (1<<1))==0)
- {
- /*logerror("&c000-&dfff is ram\n"); */
- /* rom disabled enable ram */
- oric_enable_memory(1, 1, TRUE, TRUE);
- m_bank1->set_base(m_ram_0x0c000);
- m_bank5->set_base(m_ram_0x0c000);
- }
- else
- {
- unsigned char *rom_ptr;
- /*logerror("&c000-&dfff is os rom\n"); */
- /* basic rom */
- oric_enable_memory(1, 1, TRUE, FALSE);
- rom_ptr = m_region_maincpu->base() + 0x010000;
- m_bank1->set_base(rom_ptr);
- m_bank5->set_base(rom_ptr);
- }
-
- /* for 0x0e000-0x0ffff */
- /* if not disabled, os takes priority */
- if ((m_port_314_w & (1<<1))!=0)
- {
- unsigned char *rom_ptr;
- /*logerror("&e000-&ffff is os rom\n"); */
- /* basic rom */
- oric_enable_memory(2, 3, TRUE, FALSE);
- rom_ptr = m_region_maincpu->base() + 0x010000;
- m_bank2->set_base(rom_ptr+0x02000);
- m_bank3->set_base(rom_ptr+0x03800);
- m_bank6->set_base(rom_ptr+0x02000);
- m_bank7->set_base(rom_ptr+0x03800);
-
- }
- else
- {
- /* if eprom is enabled, it takes priority over ram */
- if ((m_port_314_w & (1<<7))==0)
- {
- unsigned char *rom_ptr;
- /*logerror("&e000-&ffff is disk rom\n"); */
- oric_enable_memory(2, 3, TRUE, FALSE);
- /* enable rom of microdisc interface */
- rom_ptr = m_region_maincpu->base() + 0x014000;
- m_bank2->set_base(rom_ptr);
- m_bank3->set_base(rom_ptr+0x01800);
- }
- else
- {
- /*logerror("&e000-&ffff is ram\n"); */
- /* rom disabled enable ram */
- oric_enable_memory(2, 3, TRUE, TRUE);
- m_bank2->set_base(m_ram_0x0c000+0x02000);
- m_bank3->set_base(m_ram_0x0c000+0x03800);
- m_bank6->set_base(m_ram_0x0c000+0x02000);
- m_bank7->set_base(m_ram_0x0c000+0x03800);
- }
- }
-}
-
-
-
-READ8_MEMBER(oric_state::oric_microdisc_r)
-{
- unsigned char data = 0x0ff;
- wd1770_device *fdc = machine().device<wd1770_device>("wd179x");
-
- switch (offset & 0x0ff)
- {
- /* microdisc floppy disc interface */
- case 0x00:
- data = fdc->status_r(space, 0);
- break;
- case 0x01:
- data = fdc->track_r(space, 0);
- break;
- case 0x02:
- data = fdc->sector_r(space, 0);
- break;
- case 0x03:
- data = fdc->data_r(space, 0);
- break;
- case 0x04:
- data = m_port_314_r | 0x07f;
-/* logerror("port_314_r: %02x\n",data); */
- break;
- case 0x08:
- data = m_port_318_r | 0x07f;
-/* logerror("port_318_r: %02x\n",data); */
- break;
-
- default:
- data = m_via6522_0->read(space, offset & 0x0f);
- break;
-
- }
-
- return data;
-}
-
-WRITE8_MEMBER(oric_state::oric_microdisc_w)
-{
- wd1770_device *fdc = machine().device<wd1770_device>("wd179x");
- switch (offset & 0x0ff)
- {
- /* microdisc floppy disc interface */
- case 0x00:
- fdc->command_w(space, 0, data);
- break;
- case 0x01:
- fdc->track_w(space, 0, data);
- break;
- case 0x02:
- fdc->sector_w(space, 0, data);
- break;
- case 0x03:
- fdc->data_w(space, 0, data);
- break;
- case 0x04:
- {
- m_port_314_w = data;
-
- //logerror("port_314_w: %02x\n",data);
-
- /* bit 6,5: drive */
- /* bit 4: side */
- /* bit 3: double density enable */
- /* bit 0: enable FDC IRQ to trigger IRQ on CPU */
- fdc->set_drive((data>>5) & 0x03);
- fdc->set_side((data>>4) & 0x01);
- fdc->dden_w(!BIT(data, 3));
-
- oric_microdisc_set_mem_0x0c000();
- oric_microdisc_refresh_wd179x_ints();
- }
- break;
-
- default:
- m_via6522_0->write(space, offset & 0x0f, data);
- break;
- }
-}
-
-void oric_state::oric_install_microdisc_interface()
-{
- address_space &space = m_maincpu->space(AS_PROGRAM);
-
- space.install_read_handler(0x0300, 0x030f, read8_delegate(FUNC(oric_state::oric_IO_r),this));
- space.install_read_handler(0x0310, 0x031f, read8_delegate(FUNC(oric_state::oric_microdisc_r),this));
- space.install_read_handler(0x0320, 0x03ff, read8_delegate(FUNC(oric_state::oric_IO_r),this));
-
- space.install_write_handler(0x0300, 0x030f, write8_delegate(FUNC(oric_state::oric_IO_w),this));
- space.install_write_handler(0x0310, 0x031f, write8_delegate(FUNC(oric_state::oric_microdisc_w),this));
- space.install_write_handler(0x0320, 0x03ff, write8_delegate(FUNC(oric_state::oric_IO_w),this));
-
- /* disable os rom, enable microdisc rom */
- /* 0x0c000-0x0dfff will be ram, 0x0e000-0x0ffff will be microdisc rom */
- m_port_314_w = 0x0ff^((1<<7) | (1<<1));
-
- oric_microdisc_set_mem_0x0c000();
-}
-
-
-
-/*********************************************************/
-
-WRITE_LINE_MEMBER(oric_state::oric_wd179x_intrq_w)
-{
- if ((m_io_floppy->read() & 0x07) == ORIC_FLOPPY_INTERFACE_MICRODISC)
- {
- oric_microdisc_wd179x_intrq_w(state);
- }
-}
-
-WRITE_LINE_MEMBER(oric_state::oric_wd179x_drq_w)
-{
- switch (m_io_floppy->read() & 0x07)
- {
- default:
- case ORIC_FLOPPY_INTERFACE_NONE:
- case ORIC_FLOPPY_INTERFACE_APPLE2:
- return;
- case ORIC_FLOPPY_INTERFACE_MICRODISC:
- oric_microdisc_wd179x_drq_w(state);
- return;
- case ORIC_FLOPPY_INTERFACE_JASMIN:
- oric_jasmin_wd179x_drq_w(state);
- return;
- }
-}
-
-const wd17xx_interface oric_wd17xx_interface =
-{
- DEVCB_NULL,
- DEVCB_DRIVER_LINE_MEMBER(oric_state,oric_wd179x_intrq_w),
- DEVCB_DRIVER_LINE_MEMBER(oric_state,oric_wd179x_drq_w),
- {FLOPPY_0, FLOPPY_1, FLOPPY_2, FLOPPY_3}
-};
-
-void oric_state::oric_common_init_machine()
-{
- /* clear all irqs */
- m_irqs = 0;
- m_ram_0x0c000 = NULL;
- m_keyboard_line = 0;
- m_key_sense_bit = 0;
- m_keyboard_mask = 0;
- m_via_port_a_data = 0;
- m_psg_control = 0;
- m_previous_portb_data = 0;
- m_port_3fa_w = 0;
- m_port_3fb_w = 0;
- m_wd179x_int_state = 0;
- m_port_314_r = 0;
- m_port_318_r = 0;
- m_port_314_w = 0;
- machine().scheduler().timer_pulse(attotime::from_hz(4800), timer_expired_delegate(FUNC(oric_state::oric_refresh_tape),this));
-}
-
-void oric_state::machine_start()
-{
- oric_common_init_machine();
-
- m_is_telestrat = 0;
-
- m_ram_0x0c000 = auto_alloc_array(machine(), UINT8, 16384);
-}
-
-
-void oric_state::machine_reset()
-{
- int disc_interface_id = m_io_floppy->read() & 0x07;
- address_space &space = m_maincpu->space(AS_PROGRAM);
- if (m_is_telestrat)
- return;
-
- switch (disc_interface_id)
- {
- default:
-
- case ORIC_FLOPPY_INTERFACE_APPLE2:
- case ORIC_FLOPPY_INTERFACE_NONE:
- {
- /* setup memory when there is no disc interface */
- unsigned char *rom_ptr;
-
- /* os rom */
- oric_enable_memory(1, 3, TRUE, FALSE);
- rom_ptr = m_region_maincpu->base() + 0x010000;
- m_bank1->set_base(rom_ptr);
- m_bank2->set_base(rom_ptr+0x02000);
- m_bank3->set_base(rom_ptr+0x03800);
- m_bank5->set_base(rom_ptr);
- m_bank6->set_base(rom_ptr+0x02000);
- m_bank7->set_base(rom_ptr+0x03800);
-
-
- if (disc_interface_id==ORIC_FLOPPY_INTERFACE_APPLE2)
- {
- oric_install_apple2_interface();
- }
- else
- {
- space.install_read_handler(0x0300, 0x03ff, read8_delegate(FUNC(oric_state::oric_IO_r),this));
- space.install_write_handler(0x0300, 0x03ff, write8_delegate(FUNC(oric_state::oric_IO_w),this));
- }
- }
- break;
-
- case ORIC_FLOPPY_INTERFACE_APPLE2_V2:
- {
- oric_install_apple2_v2_interface();
- }
- break;
-
-
- case ORIC_FLOPPY_INTERFACE_MICRODISC:
- {
- oric_install_microdisc_interface();
- }
- break;
-
- case ORIC_FLOPPY_INTERFACE_JASMIN:
- {
- oric_install_jasmin_interface();
- }
- break;
- }
- m_maincpu->reset();
-}
-
-
-READ8_MEMBER(oric_state::oric_IO_r)
-{
- switch (m_io_floppy->read() & 0x07)
- {
- default:
- case ORIC_FLOPPY_INTERFACE_NONE:
- break;
-
- case ORIC_FLOPPY_INTERFACE_MICRODISC:
- {
- if ((offset>=0x010) && (offset<=0x01f))
- {
- return oric_microdisc_r(space, offset);
- }
- }
- break;
-
- case ORIC_FLOPPY_INTERFACE_JASMIN:
- {
- if ((offset>=0x0f4) && (offset<=0x0ff))
- {
- return oric_jasmin_r(space, offset);
- }
- }
- break;
- }
-
- /* it is repeated */
- return m_via6522_0->read(space, offset & 0x0f);
-}
-
-WRITE8_MEMBER(oric_state::oric_IO_w)
-{
- switch (m_io_floppy->read() & 0x07)
- {
- default:
- case ORIC_FLOPPY_INTERFACE_NONE:
- break;
-
- case ORIC_FLOPPY_INTERFACE_MICRODISC:
- {
- if ((offset >= 0x010) && (offset <= 0x01f))
- {
- oric_microdisc_w(space, offset, data);
- return;
- }
- }
- break;
-
- case ORIC_FLOPPY_INTERFACE_JASMIN:
- {
- if ((offset >= 0x0f4) && (offset <= 0x0ff))
- {
- oric_jasmin_w(space, offset, data);
- return;
- }
-
- }
- break;
- }
-
- m_via6522_0->write(space, offset & 0x0f, data);
-}
-
-
-
-/**** TELESTRAT ****/
-
-/*
-VIA lines
- Telestrat usage
-
-PA0..PA2
- Memory bank selection
-
-PA3
- "Midi" port pin 3
-
-PA4
- RS232/Minitel selection
-
-PA5
- Third mouse button (right joystick port pin 5)
-
-PA6
- "Midi" port pin 5
-
-PA7
- Second mouse button (right joystick port pin 9)
-
-CA1
- "Midi" port pin 1
-
-CA2
- not used ?
-
-PB0..PB4
- Joystick ports
-
-PB5
- Joystick doubler switch
-
-PB6
- Select Left Joystick port
-
-PB7
- Select Right Joystick port
-
-CB1
- Phone Ring detection
-
-CB2
- "Midi" port pin 4
-
-*/
-
-
-void oric_state::telestrat_refresh_mem()
-{
- address_space &space = m_maincpu->space(AS_PROGRAM);
-
- telestrat_mem_block *mem_block = &m_telestrat_blocks[m_telestrat_bank_selection];
-
- switch (mem_block->MemType)
- {
- case TELESTRAT_MEM_BLOCK_RAM:
- {
- m_bank1->set_base(mem_block->ptr);
- m_bank2->set_base(mem_block->ptr);
- space.install_read_bank(0xc000, 0xffff, "bank1");
- space.install_write_bank(0xc000, 0xffff, "bank2");
- }
- break;
-
- case TELESTRAT_MEM_BLOCK_ROM:
- {
- m_bank1->set_base(mem_block->ptr);
- space.install_read_bank(0xc000, 0xffff, "bank1");
- space.nop_write(0xc000, 0xffff);
- }
- break;
-
- default:
- case TELESTRAT_MEM_BLOCK_UNDEFINED:
- {
- space.nop_readwrite(0xc000, 0xffff);
- }
- break;
- }
-}
-
-READ8_MEMBER(oric_state::telestrat_via2_in_a_func)
-{
- //logerror("via 2 - port a %02x\n",m_telestrat_via2_port_a_data);
- return m_telestrat_via2_port_a_data;
-}
-
-
-WRITE8_MEMBER(oric_state::telestrat_via2_out_a_func)
-{
- //logerror("via 2 - port a w: %02x\n",data);
-
- m_telestrat_via2_port_a_data = data;
-
- if (((data^m_telestrat_bank_selection) & 0x07)!=0)
- {
- m_telestrat_bank_selection = data & 0x07;
-
- telestrat_refresh_mem();
- }
-}
-
-READ8_MEMBER(oric_state::telestrat_via2_in_b_func)
-{
- unsigned char data = 0x01f;
-
- /* left joystick selected? */
- if (m_telestrat_via2_port_b_data & (1<<6))
- {
- data &= ioport("JOY0")->read();
- }
-
- /* right joystick selected? */
- if (m_telestrat_via2_port_b_data & (1<<7))
- {
- data &= ioport("JOY1")->read();
- }
-
- data |= m_telestrat_via2_port_b_data & ((1<<7) | (1<<6) | (1<<5));
-
- return data;
-}
-
-WRITE8_MEMBER(oric_state::telestrat_via2_out_b_func)
-{
- m_telestrat_via2_port_b_data = data;
-}
-
-
-WRITE_LINE_MEMBER(oric_state::telestrat_via2_irq_func)
-{
- m_irqs &=~(1<<2);
-
- if (state)
- {
- //logerror("telestrat via2 interrupt\n");
-
- m_irqs |=(1<<2);
- }
-
- oric_refresh_ints();
-}
-
-/* interrupt state from acia6551 */
-WRITE_LINE_MEMBER(oric_state::telestrat_acia_callback)
-{
- m_irqs&=~(1<<3);
-
- if (state)
- {
- m_irqs |= (1<<3);
- }
-
- oric_refresh_ints();
-}
-
-MACHINE_START_MEMBER(oric_state,telestrat)
-{
- UINT8 *mem = m_region_maincpu->base();
-
- oric_common_init_machine();
-
- m_telestrat_via2_port_a_data = 0;
- m_telestrat_via2_port_b_data = 0;
- m_is_telestrat = 1;
-
- /* initialise overlay ram */
- m_telestrat_blocks[0].MemType = TELESTRAT_MEM_BLOCK_RAM;
- m_telestrat_blocks[0].ptr = mem+0x020000; //auto_alloc_array(machine(), UINT8, 16384);
-
- m_telestrat_blocks[1].MemType = TELESTRAT_MEM_BLOCK_RAM;
- m_telestrat_blocks[1].ptr = mem+0x024000; //auto_alloc_array(machine(), UINT8, 16384);
-
- m_telestrat_blocks[2].MemType = TELESTRAT_MEM_BLOCK_RAM;
- m_telestrat_blocks[2].ptr = mem+0x028000; //auto_alloc_array(machine(), UINT8, 16384);
-
- /* initialise default cartridge */
- m_telestrat_blocks[3].MemType = TELESTRAT_MEM_BLOCK_ROM;
- m_telestrat_blocks[3].ptr = mem+0x010000; // telmatic.rom
-
- m_telestrat_blocks[4].MemType = TELESTRAT_MEM_BLOCK_RAM;
- m_telestrat_blocks[4].ptr = mem+0x02c000; //auto_alloc_array(machine(), UINT8, 16384);
-
- /* initialise default cartridge */
- m_telestrat_blocks[5].MemType = TELESTRAT_MEM_BLOCK_ROM;
- m_telestrat_blocks[5].ptr = mem+0x014000; // teleass.rom
-
- /* initialise default cartridge */
- m_telestrat_blocks[6].MemType = TELESTRAT_MEM_BLOCK_ROM;
- m_telestrat_blocks[6].ptr = mem+0x018000; // hyperbas.rom
-
- /* initialise default cartridge */
- m_telestrat_blocks[7].MemType = TELESTRAT_MEM_BLOCK_ROM;
- m_telestrat_blocks[7].ptr = mem+0x01c000; // telmon24.rom
-
- m_telestrat_bank_selection = 7;
- telestrat_refresh_mem();
-
- /* disable os rom, enable microdisc rom */
- /* 0x0c000-0x0dfff will be ram, 0x0e000-0x0ffff will be microdisc rom */
- m_port_314_w = 0x0ff^((1<<7) | (1<<1));
-}
diff --git a/src/mess/mess.mak b/src/mess/mess.mak
index 1fd8ec20290..5744756f7c9 100644
--- a/src/mess/mess.mak
+++ b/src/mess/mess.mak
@@ -553,6 +553,7 @@ BUSES += MIDI
BUSES += MEGADRIVE
BUSES += NES
BUSES += NUBUS
+BUSES += ORICEXT
BUSES += PCE
BUSES += PCI
BUSES += PC_JOY
@@ -1788,9 +1789,7 @@ $(MESSOBJ)/tangerin.a: \
$(MESS_VIDEO)/microtan.o \
$(MESS_MACHINE)/microtan.o \
$(MESS_DRIVERS)/microtan.o \
- $(MESS_DRIVERS)/oric.o \
- $(MESS_VIDEO)/oric.o \
- $(MESS_MACHINE)/oric.o \
+ $(MESS_DRIVERS)/oric.o
$(MESSOBJ)/tatung.a: \
$(MESS_DRIVERS)/einstein.o \
diff --git a/src/mess/tools/floptool/main.c b/src/mess/tools/floptool/main.c
index 4a67ce8a940..4f29ba47982 100644
--- a/src/mess/tools/floptool/main.c
+++ b/src/mess/tools/floptool/main.c
@@ -39,6 +39,10 @@
#include "formats/ap_dsk35.h"
#include "formats/ap2_dsk.h"
+#include "formats/oric_dsk.h"
+
+#include "formats/applix_dsk.h"
+
static floppy_format_type floppy_formats[] = {
FLOPPY_MFI_FORMAT,
FLOPPY_DFI_FORMAT,
@@ -60,6 +64,10 @@ static floppy_format_type floppy_formats[] = {
FLOPPY_DC42_FORMAT,
FLOPPY_A216S_FORMAT,
FLOPPY_RWTS18_FORMAT,
+
+ FLOPPY_ORIC_DSK_FORMAT,
+
+ FLOPPY_APPLIX_FORMAT,
};
void CLIB_DECL ATTR_PRINTF(1,2) logerror(const char *format, ...)
diff --git a/src/mess/video/oric.c b/src/mess/video/oric.c
deleted file mode 100644
index 054515d1e92..00000000000
--- a/src/mess/video/oric.c
+++ /dev/null
@@ -1,304 +0,0 @@
-/***************************************************************************
-
- video/oric.c
-
- All graphic effects are supported including mid-line changes.
- There may be some small bugs.
-
- TODO:
- - speed up this code a bit?
-
-***************************************************************************/
-
-#include "includes/oric.h"
-
-TIMER_CALLBACK_MEMBER(oric_state::oric_vh_timer_callback)
-{
- /* update flash count */
- m_vh_state.flash_count++;
-}
-
-void oric_state::oric_vh_update_flash()
-{
- /* flash active? */
- if (BIT(m_vh_state.text_attributes, 2))
- {
- /* yes */
-
- /* show or hide text? */
- if (BIT(m_vh_state.flash_count, 4))
- {
- /* hide */
- /* set foreground and background to be the same */
- m_vh_state.active_foreground_colour = m_vh_state.background_colour;
- m_vh_state.active_background_colour = m_vh_state.background_colour;
- return;
- }
- }
-
-
- /* show */
- m_vh_state.active_foreground_colour = m_vh_state.foreground_colour;
- m_vh_state.active_background_colour = m_vh_state.background_colour;
-}
-
-/* the alternate charset follows from the standard charset.
-Each charset holds 128 chars with 8 bytes for each char.
-
-The start address for the standard charset is dependant on the video mode */
-void oric_state::oric_refresh_charset()
-{
- /* alternate char set? */
- if (BIT(m_vh_state.text_attributes, 0))
- {
- /* yes */
- m_vh_state.char_data = m_vh_state.char_base + (128*8);
- }
- else
- {
- /* no */
- m_vh_state.char_data = m_vh_state.char_base;
- }
-}
-
-/* update video hardware state depending on the new attribute */
-void oric_state::oric_vh_update_attribute(UINT8 c)
-{
- /* attribute */
- UINT8 attribute = c & 0x03f;
- address_space &space = m_maincpu->space(AS_PROGRAM);
-
- switch ((attribute>>3) & 0x03)
- {
- case 0:
- {
- /* set foreground colour 00-07 = black,red,green,yellow,blue,magenta,cyan,white */
- m_vh_state.foreground_colour = attribute & 0x07;
- oric_vh_update_flash();
- }
- break;
-
- case 1:
- {
- m_vh_state.text_attributes = attribute & 0x07;
-
- oric_refresh_charset();
-
- /* text attributes */
- oric_vh_update_flash();
- }
- break;
-
- case 2:
- {
- /* set background colour */
- m_vh_state.background_colour = attribute & 0x07;
- oric_vh_update_flash();
- }
- break;
-
- case 3:
- {
- /* set video mode */
- m_vh_state.mode = attribute & 0x07;
-
- // a different charset base is used depending on the video mode
- // hires takes all the data from 0x0a000 through to about 0x0bf68,
- // so the charset is moved to 0x09800 */
- // text mode starts at 0x0bb80 and so the charset is in a different location
- if (BIT(m_vh_state.mode, 2))
- {
- /* set screen memory base and standard charset location for this mode */
- m_vh_state.read_addr = 0x0a000;
- if (m_ram)
- m_vh_state.char_base = m_ram + (offs_t)0x09800;
- else
- m_vh_state.char_base = (UINT8 *)space.get_read_ptr(0x09800);
- }
- else
- {
- /* set screen memory base and standard charset location for this mode */
- m_vh_state.read_addr = 0x0bb80;
- if (m_ram)
- m_vh_state.char_base = m_ram + (offs_t)0x0b400;
- else
- m_vh_state.char_base = (UINT8 *)space.get_read_ptr(0x0b400);
- }
- /* changing the mode also changes the position of the standard charset and alternative charset */
- oric_refresh_charset();
- }
- break;
-
- default:
- break;
- }
-}
-
-
-/* render 6-pixels using foreground and background colours specified */
-/* used in hires and text mode */
-void oric_state::oric_vh_render_6pixels(bitmap_ind16 &bitmap, int x, UINT8 y, UINT8 fg, UINT8 bg, UINT8 data, bool invert_flag)
-{
- /* invert? */
- if (invert_flag)
- {
- fg ^=0x07;
- bg ^=0x07;
- }
-
- bitmap.pix16(y, x++) = BIT(data, 5) ? fg : bg;
- bitmap.pix16(y, x++) = BIT(data, 4) ? fg : bg;
- bitmap.pix16(y, x++) = BIT(data, 3) ? fg : bg;
- bitmap.pix16(y, x++) = BIT(data, 2) ? fg : bg;
- bitmap.pix16(y, x++) = BIT(data, 1) ? fg : bg;
- bitmap.pix16(y, x++) = BIT(data, 0) ? fg : bg;
-}
-
-
-
-
-
-/***************************************************************************
- oric_vh_screenrefresh
-***************************************************************************/
-UINT32 oric_state::screen_update_oric(screen_device &screen, bitmap_ind16 &bitmap, const rectangle &cliprect)
-{
- UINT8 *RAM, y;
- offs_t byte_offset, read_addr_base;
- bool hires_active;
- address_space &space = m_maincpu->space(AS_PROGRAM);
-
- RAM = m_ram;
-
- /* set initial base */
- read_addr_base = m_vh_state.read_addr;
-
- /* is hires active? */
- hires_active = BIT(m_vh_state.mode, 2);
-
- for (y = 0; y < 224; y++)
- {
- int x = 0;
-
- /* foreground colour white */
- oric_vh_update_attribute(7);
- /* background colour black */
- oric_vh_update_attribute((1<<3));
- oric_vh_update_attribute((1<<4));
-
- for (byte_offset=0; byte_offset<40; byte_offset++)
- {
- UINT8 c;
- offs_t read_addr;
-
- /* after line 200 all rendering is done in text mode */
- if (y<200)
- {
- /* calculate fetch address based on current line and current mode */
- if (hires_active)
- {
- read_addr = read_addr_base + byte_offset + (offs_t)(y*40);
- }
- else
- {
- UINT8 char_line = y>>3;
- read_addr = read_addr_base + byte_offset + (offs_t)(char_line*40);
- }
- }
- else
- {
- UINT8 char_line = (y-200)>>3;
- read_addr = read_addr_base + byte_offset + (offs_t)(char_line*40);
- }
-
- /* fetch data */
- c = RAM ? RAM[read_addr] : space.read_byte(read_addr);
-
- /* if bits 6 and 5 are zero, the byte contains a serial attribute */
- if ((c & ((1 << 6) | (1 << 5))) == 0)
- {
- oric_vh_update_attribute(c);
-
- /* display background colour when attribute has been found */
- oric_vh_render_6pixels(bitmap, x, y, m_vh_state.active_foreground_colour, m_vh_state.active_background_colour, 0, (c & 0x080));
-
- if (y < 200)
- {
- /* is hires active? */
- hires_active = BIT(m_vh_state.mode, 2);
- read_addr_base = m_vh_state.read_addr;
- }
- }
- else
- {
- /* hires? */
- if (hires_active)
- {
- UINT8 pixel_data = c & 0x03f;
- /* plot hires pixels */
- oric_vh_render_6pixels(bitmap,x,y,m_vh_state.active_foreground_colour, m_vh_state.active_background_colour, pixel_data, BIT(c, 7));
- }
- else
- {
- UINT8 char_index, char_data, ch_line;
-
- char_index = (c & 0x07f);
-
- ch_line = y & 7;
-
- /* is double height set? */
- if (BIT(m_vh_state.text_attributes, 1))
- {
- /* if char line is even, top half of character is displayed else bottom half */
- UINT8 double_height_flag = BIT(y, 3);
-
- /* calculate line to fetch */
- ch_line = (ch_line>>1) + (double_height_flag<<2);
- }
-
- /* fetch pixel data for this char line */
- char_data = m_vh_state.char_data[(char_index<<3) | ch_line] & 0x03f;
-
- /* draw! */
- oric_vh_render_6pixels(bitmap,x,y,
- m_vh_state.active_foreground_colour,
- m_vh_state.active_background_colour, char_data, BIT(c, 7));
- }
-
- }
-
- x+=6;
- }
-
- /* after 200 lines have been drawn, force a change of the read address */
- /* there are 200 lines of hires/text mode, then 24 lines of text mode */
- /* the mode can't be changed in the last 24 lines. */
- if (y==199)
- {
- /* mode */
- read_addr_base = (offs_t)0x0bf68;
- hires_active = 0;
- }
- }
- return 0;
-}
-
-
-void oric_state::video_start()
-{
- // initialise variables
- m_vh_state.active_foreground_colour = 0;
- m_vh_state.active_background_colour = 0;
- m_vh_state.foreground_colour = 0;
- m_vh_state.background_colour = 0;
- m_vh_state.mode = 0;
- m_vh_state.text_attributes = 0;
- m_vh_state.read_addr = 0;
- m_vh_state.char_data = 0;
- m_vh_state.char_base = 0;
- /* initialise flash timer */
- m_vh_state.flash_count = 0;
- machine().scheduler().timer_pulse(attotime::from_hz(50), timer_expired_delegate(FUNC(oric_state::oric_vh_timer_callback),this));
- /* mode */
- oric_vh_update_attribute((1<<3)|(1<<4));
-}