diff options
author | 2015-08-08 11:58:30 +0200 | |
---|---|---|
committer | 2015-08-20 11:42:57 +0200 | |
commit | 4043b55acbc5e7ef63170c606c5afa75e4fedc7b (patch) | |
tree | 9417c782a3652c9228f45831c905375711cab741 | |
parent | 70f493692638387862dff42dfa4dd0606ff49ab1 (diff) |
namco system 10 checkpoint, startrgn does a new flash access and
is unhappy with the result (nw)
-rw-r--r-- | src/emu/cpu/psx/psx.c | 8 | ||||
-rw-r--r-- | src/emu/cpu/psx/psx.h | 4 | ||||
-rw-r--r-- | src/mame/drivers/namcos10.c | 191 |
3 files changed, 199 insertions, 4 deletions
diff --git a/src/emu/cpu/psx/psx.c b/src/emu/cpu/psx/psx.c index a60a1204b9f..a262c9bd42c 100644 --- a/src/emu/cpu/psx/psx.c +++ b/src/emu/cpu/psx/psx.c @@ -1417,7 +1417,7 @@ void psxcpu_device::update_rom_config() } } - if( window_size < max_window_size ) + if( window_size < max_window_size && !m_disable_rom_berr) { m_program->install_readwrite_handler( 0x1fc00000 + window_size, 0x1fffffff, read32_delegate( FUNC( psxcpu_device::berr_r ), this ), write32_delegate( FUNC( psxcpu_device::berr_w ), this ) ); m_program->install_readwrite_handler( 0x9fc00000 + window_size, 0x9fffffff, read32_delegate( FUNC( psxcpu_device::berr_r ), this ), write32_delegate( FUNC( psxcpu_device::berr_w ), this ) ); @@ -1756,6 +1756,7 @@ psxcpu_device::psxcpu_device( const machine_config &mconfig, device_type type, c m_cd_write_handler( *this ), m_ram( *this, "ram" ) { + m_disable_rom_berr = false; } cxd8530aq_device::cxd8530aq_device( const machine_config &mconfig, const char *tag, device_t *owner, UINT32 clock ) @@ -3374,6 +3375,11 @@ WRITE8_MEMBER( psxcpu_device::cd_w ) m_cd_write_handler( space, offset, data, mem_mask ); } +void psxcpu_device::set_disable_rom_berr(bool mode) +{ + m_disable_rom_berr = mode; +} + static MACHINE_CONFIG_FRAGMENT( psx ) MCFG_DEVICE_ADD( "irq", PSX_IRQ, 0 ) MCFG_PSX_IRQ_HANDLER( INPUTLINE( DEVICE_SELF, PSXCPU_IRQ0 ) ) diff --git a/src/emu/cpu/psx/psx.h b/src/emu/cpu/psx/psx.h index 4f5895bf4e9..21b6d8adc55 100644 --- a/src/emu/cpu/psx/psx.h +++ b/src/emu/cpu/psx/psx.h @@ -128,6 +128,8 @@ enum devcb = &psxcpu_device::set_cd_read_handler(*device, DEVCB_##_devcb); #define MCFG_PSX_CD_WRITE_HANDLER(_devcb) \ devcb = &psxcpu_device::set_cd_write_handler(*device, DEVCB_##_devcb); +#define MCFG_PSX_DISABLE_ROM_BERR \ + downcast<psxcpu_device *>(device)->set_disable_rom_berr(true); //************************************************************************** // TYPE DEFINITIONS @@ -196,6 +198,7 @@ public: DECLARE_READ32_MEMBER( com_delay_r ); static psxcpu_device *getcpu( device_t &device, const char *cputag ); + void set_disable_rom_berr(bool mode); protected: psxcpu_device(const machine_config &mconfig, device_type type, const char *name, const char *tag, device_t *owner, UINT32 clock, const char *shortname, const char *source); @@ -346,6 +349,7 @@ protected: devcb_write8 m_cd_write_handler; required_device<ram_device> m_ram; memory_region *m_rom; + bool m_disable_rom_berr; private: // disassembler interface diff --git a/src/mame/drivers/namcos10.c b/src/mame/drivers/namcos10.c index 544b6196fe0..26c70f1e559 100644 --- a/src/mame/drivers/namcos10.c +++ b/src/mame/drivers/namcos10.c @@ -294,10 +294,27 @@ public: DECLARE_WRITE16_MEMBER(nand_block_w); DECLARE_READ16_MEMBER(nand_block_r); + DECLARE_READ16_MEMBER (control_r); + DECLARE_WRITE16_MEMBER(control_w); + + DECLARE_READ16_MEMBER (i2c_clock_r); + DECLARE_WRITE16_MEMBER(i2c_clock_w); + DECLARE_READ16_MEMBER (i2c_data_r); + DECLARE_WRITE16_MEMBER(i2c_data_w); + + DECLARE_READ16_MEMBER (sprot_r); + DECLARE_WRITE16_MEMBER(sprot_w); + UINT8 *nand_base; void nand_copy( UINT32 *dst, UINT32 address, int len ); private: + enum { + I2CP_IDLE, + I2CP_RECIEVE_BYTE, + I2CP_RECIEVE_ACK_1, + I2CP_RECIEVE_ACK_0 + }; UINT16 key; UINT8 cnt; UINT32 bank_base; @@ -305,8 +322,16 @@ private: UINT16 block[0x1ff]; ns10_decrypter_device* decrypter; + UINT16 i2c_host_clock, i2c_host_data, i2c_dev_clock, i2c_dev_data, i2c_prev_clock, i2c_prev_data; + int i2cp_mode; + UINT8 i2c_byte; + int i2c_bit; + + int sprot_bit, sprot_byte; UINT16 nand_read( UINT32 address ); UINT16 nand_read2( UINT32 address ); + + void i2c_update(); public: DECLARE_DRIVER_INIT(knpuzzle); DECLARE_DRIVER_INIT(panikuru); @@ -326,9 +351,14 @@ public: static ADDRESS_MAP_START( namcos10_map, AS_PROGRAM, 32, namcos10_state ) - AM_RANGE(0x1f500000, 0x1f5007ff) AM_RAM AM_SHARE("share3") /* ram? stores block numbers */ - AM_RANGE(0x9f500000, 0x9f5007ff) AM_RAM AM_SHARE("share3") /* ram? stores block numbers */ - AM_RANGE(0xbf500000, 0xbf5007ff) AM_RAM AM_SHARE("share3") /* ram? stores block numbers */ + AM_RANGE(0x1f500000, 0x1f501fff) AM_RAM AM_SHARE("share3") /* ram? stores block numbers */ + AM_RANGE(0x9f500000, 0x9f501fff) AM_RAM AM_SHARE("share3") /* ram? stores block numbers */ + AM_RANGE(0xbf500000, 0xbf501fff) AM_RAM AM_SHARE("share3") /* ram? stores block numbers */ + + AM_RANGE(0x1fba0000, 0x1fba0003) AM_READWRITE16(sprot_r, sprot_w, 0xffff0000) + AM_RANGE(0x1fba0008, 0x1fba000b) AM_READWRITE16(i2c_clock_r, i2c_clock_w, 0x0000ffff) + AM_RANGE(0x1fba0008, 0x1fba000b) AM_READWRITE16(i2c_data_r, i2c_data_w, 0xffff0000) + AM_RANGE(0x1fba0000, 0x1fba000f) AM_READWRITE16(control_r, control_w, 0xffffffff) ADDRESS_MAP_END @@ -390,6 +420,141 @@ READ16_MEMBER(namcos10_state::range_r) return dd16; } +READ16_MEMBER(namcos10_state::control_r) +{ + logerror("control_r %d (%x)\n", offset, space.device().safe_pc()); + if(offset == 2) + return 1^0xffff; + return 0; +} + +WRITE16_MEMBER(namcos10_state::control_w) +{ + logerror("control_w %d, %04x (%x)\n", offset, data, space.device().safe_pc()); +} + +WRITE16_MEMBER(namcos10_state::sprot_w) +{ + logerror("sprot_w %04x (%x)\n", data, space.device().safe_pc()); + sprot_bit = 7; + sprot_byte = 0; +} + +// startrgn: +// 8004b6f8: jal 4b730, dies if v0!=0 (answers 1) +// flash access, unhappy with the results + +// 800128d8: jal 37b58 (flash death) +// 800128e0: jal 1649c +// 800128e8: jal 2c47c + +READ16_MEMBER(namcos10_state::sprot_r) +{ + // If line 3 has 0x30/0x31 in it, something happens. That + // something currently kills the system though. + + const static UINT8 prot[0x40] = { + 0x10, 0x11, 0x12, 0x13, 0x14, 0x15, 0x16, 0x17, 0x18, 0x19, 0x1a, 0x1b, 0x1c, 0x1d, 0x1e, 0x1f, + 0x20, 0x21, 0x22, 0x23, 0x24, 0x25, 0x26, 0x27, 0x28, 0x29, 0x2a, 0x2b, 0x2c, 0x2d, 0x2e, 0x2f, + 0x50, 0x51, 0x50, 0x51, 0x50, 0x51, 0x50, 0x51, 0x50, 0x51, 0x50, 0x51, 0x50, 0x51, 0x50, 0x51, + 0x40, 0x41, 0x42, 0x43, 0x44, 0x45, 0x46, 0x47, 0x48, 0x49, 0x4a, 0x4b, 0x4c, 0x4d, 0x4e, 0x4f, + }; + UINT16 res = sprot_byte >= 0x20 ? 0x3 : + (((prot[sprot_byte ] >> sprot_bit) & 1) ? 1 : 0) | + (((prot[sprot_byte+0x20] >> sprot_bit) & 1) ? 2 : 0); + + sprot_bit--; + if(sprot_bit == -1) { + sprot_bit = 7; + sprot_byte++; + } + return res; +} + +READ16_MEMBER(namcos10_state::i2c_clock_r) +{ + UINT16 res = i2c_dev_clock & i2c_host_clock & 1; + // logerror("i2c_clock_r %d (%x)\n", res, space.device().safe_pc()); + return res; +} + + +WRITE16_MEMBER(namcos10_state::i2c_clock_w) +{ + COMBINE_DATA(&i2c_host_clock); + // logerror("i2c_clock_w %d (%x)\n", data, space.device().safe_pc()); + i2c_update(); +} + +READ16_MEMBER(namcos10_state::i2c_data_r) +{ + UINT16 res = i2c_dev_data & i2c_host_data & 1; + // logerror("i2c_data_r %d (%x)\n", res, space.device().safe_pc()); + return res; +} + + +WRITE16_MEMBER(namcos10_state::i2c_data_w) +{ + COMBINE_DATA(&i2c_host_data); + // logerror("i2c_data_w %d (%x)\n", data, space.device().safe_pc()); + i2c_update(); +} + +void namcos10_state::i2c_update() +{ + UINT16 clock = i2c_dev_clock & i2c_host_clock & 1; + UINT16 data = i2c_dev_data & i2c_host_data & 1; + + if(i2c_prev_data == data && i2c_prev_clock == clock) + return; + + switch(i2cp_mode) { + case I2CP_IDLE: + if(clock && !data) { + logerror("i2c: start bit\n"); + i2c_byte = 0; + i2c_bit = 7; + i2cp_mode = I2CP_RECIEVE_BYTE; + } + break; + case I2CP_RECIEVE_BYTE: + if(clock && data && !i2c_prev_data) { + logerror("i2c stop bit\n"); + i2cp_mode = I2CP_IDLE; + } else if(clock && !i2c_prev_clock) { + i2c_byte |= (data << i2c_bit); + // logerror("i2c_byte = %02x (%d)\n", i2c_byte, i2c_bit); + i2c_bit--; + if(i2c_bit < 0) { + i2cp_mode = I2CP_RECIEVE_ACK_1; + logerror("i2c recieved byte %02x\n", i2c_byte); + i2c_dev_data = 0; + data = 0; + } + } + break; + case I2CP_RECIEVE_ACK_1: + if(clock && !i2c_prev_clock) { + // logerror("i2c ack on\n"); + i2cp_mode = I2CP_RECIEVE_ACK_0; + } + break; + case I2CP_RECIEVE_ACK_0: + if(!clock && i2c_prev_clock) { + // logerror("i2c ack off\n"); + i2c_dev_data = 1; + data = i2c_host_data & 1; + i2c_byte = 0; + i2c_bit = 7; + i2cp_mode = I2CP_RECIEVE_BYTE; + } + break; + } + i2c_prev_data = data; + i2c_prev_clock = clock; +} + static ADDRESS_MAP_START( namcos10_memm_map, AS_PROGRAM, 32, namcos10_state ) AM_RANGE(0x1f300000, 0x1f300003) AM_WRITE16(key_w, 0x0000ffff) AM_RANGE(0x1f400000, 0x1f5fffff) AM_READ16(range_r, 0xffffffff) @@ -628,6 +793,12 @@ DRIVER_INIT_MEMBER(namcos10_state,konotako) MACHINE_RESET_MEMBER(namcos10_state,namcos10) { + i2c_dev_clock = i2c_dev_data = 1; + i2c_host_clock = i2c_host_data = 1; + i2c_prev_clock = i2c_prev_data = 1; + i2cp_mode = I2CP_IDLE; + i2c_byte = 0x00; + i2c_bit = 0; } static MACHINE_CONFIG_START( namcos10_memm, namcos10_state ) @@ -635,6 +806,13 @@ static MACHINE_CONFIG_START( namcos10_memm, namcos10_state ) MCFG_CPU_ADD( "maincpu", CXD8606BQ, XTAL_101_4912MHz ) MCFG_CPU_PROGRAM_MAP( namcos10_memm_map ) + // The bios first configures the rom window as 80000-big, then + // switches to 400000. If berr is active, the first configuration + // wipes all handlers after 1fc80000, which kills the system + // afterwards + + MCFG_PSX_DISABLE_ROM_BERR + MCFG_RAM_MODIFY("maincpu:ram") MCFG_RAM_DEFAULT_SIZE("16M") @@ -652,6 +830,13 @@ static MACHINE_CONFIG_START( namcos10_memn, namcos10_state ) MCFG_CPU_ADD( "maincpu", CXD8606BQ, XTAL_101_4912MHz ) MCFG_CPU_PROGRAM_MAP( namcos10_memn_map ) + // The bios first configures the rom window as 80000-big, then + // switches to 400000. If berr is active, the first configuration + // wipes all handlers after 1fc80000, which kills the system + // afterwards + + MCFG_PSX_DISABLE_ROM_BERR + MCFG_RAM_MODIFY("maincpu:ram") MCFG_RAM_DEFAULT_SIZE("16M") |