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author Olivier Galibert <galibert@pobox.com>2021-03-26 22:56:40 +0100
committer Olivier Galibert <galibert@pobox.com>2021-03-26 22:58:00 +0100
commita20c9d1d31f2d8031addf78e3c3a508cfe0cc58a (patch)
tree505d80ba2799d3de172663de63bbbb537fd760e4
parent6ceb297bfc52802afa0d001e310d54557e83ff86 (diff)
ppc: better lswx/stsxw fix
-rw-r--r--src/devices/cpu/powerpc/ppcdrc.cpp16
1 files changed, 10 insertions, 6 deletions
diff --git a/src/devices/cpu/powerpc/ppcdrc.cpp b/src/devices/cpu/powerpc/ppcdrc.cpp
index c81915d2cf9..63660072f7d 100644
--- a/src/devices/cpu/powerpc/ppcdrc.cpp
+++ b/src/devices/cpu/powerpc/ppcdrc.cpp
@@ -3075,9 +3075,11 @@ bool ppc_device::generate_instruction_1f(drcuml_block &block, compiler_state *co
case 0x215: /* LSWX */
UML_ADD(block, mem(&m_core->updateaddr), R32Z(G_RA(op)), R32(G_RB(op))); // add [updateaddr],ra,rb
- UML_AND(block, mem(&m_core->swcount), SPR32(SPR_XER), 0x7f); // and [swcount],[xer],0x7f
- UML_SUB(block, mem(&m_core->icount), mem(&m_core->icount), mem(&m_core->swcount));// sub icount,icount,[swcount]
- UML_CALLH(block, *m_lsw[m_core->mode][G_RD(op)]); // call lsw[rd],nz
+ UML_AND(block, I0, SPR32(SPR_XER), 0x7f); // and i0,[xer],0x7f
+ UML_SUB(block, mem(&m_core->icount), mem(&m_core->icount), I0);// sub icount,icount,i0
+ UML_MOV(block, mem(&m_core->swcount), I0); // mov [swcount],i0
+ UML_TEST(block, I0, I0); // test i0,i0
+ UML_CALLHc(block, COND_NZ, *m_lsw[m_core->mode][G_RD(op)]); // call lsw[rd]
generate_update_cycles(block, compiler, desc->pc + 4, true); // <update cycles>
return true;
@@ -3227,9 +3229,11 @@ bool ppc_device::generate_instruction_1f(drcuml_block &block, compiler_state *co
case 0x295: /* STSWX */
UML_ADD(block, mem(&m_core->updateaddr), R32Z(G_RA(op)), R32(G_RB(op))); // add [updateaddr],ra,rb
- UML_AND(block, mem(&m_core->swcount), SPR32(SPR_XER), 0x7f); // and [swcount],[xer],0x7f
- UML_SUB(block, mem(&m_core->icount), mem(&m_core->icount), mem(&m_core->swcount));// sub icount,icount,[swcount]
- UML_CALLH(block, *m_stsw[m_core->mode][G_RD(op)]); // call stsw[rd]
+ UML_AND(block, I0, SPR32(SPR_XER), 0x7f); // and i0,[xer],0x7f
+ UML_SUB(block, mem(&m_core->icount), mem(&m_core->icount), I0);// sub icount,icount,i0
+ UML_MOV(block, mem(&m_core->swcount), I0); // mov [swcount],i0
+ UML_TEST(block, I0, I0); // test i0,i0
+ UML_CALLHc(block, COND_NZ, *m_stsw[m_core->mode][G_RD(op)]); // call stsw[rd]
generate_update_cycles(block, compiler, desc->pc + 4, true); // <update cycles>
return true;