summaryrefslogtreecommitdiffstatshomepage
diff options
context:
space:
mode:
author Sterophonick <34801996+Sterophonick@users.noreply.github.com>2020-01-25 11:17:29 -0700
committer ajrhacker <ajrhacker@users.noreply.github.com>2020-01-25 13:17:29 -0500
commita09672cc2b9ff8ff5216c8db1f003bf0e4a9d267 (patch)
tree056e975c9e4eb1b12fcc228a5a0cb22f08a25a82
parent86fb011122bae796824d0c58e16b69a95af12130 (diff)
gigatron: Fix copyrights. (#6211)
* gigatron: Fix copyrights. (nw) * gigatron: make capitalization consistent (nw) * gamedrv: fix a minor spelling mistake (nw) * gigatron: change the ROM names to valid characters * gigatron: cpu device work (nw) * gigatron: cpu work (nw) * gigatron: cpu work (nw) * gigatron: cpu device work (nw) * gigatron: cpu device progress * gigatron: driver + cpu work (nw) * gigatron: some more instructions * gigatron: slight fixes (nw) * gigatron: fixes (nw) * gigatron: whoops (nw) * gigatron: make some fixes thanks hap (nw) * gigatron: temporarily fix error with mem address (nw) * gigatron: do a bit of work (nw)
-rw-r--r--src/devices/cpu/gigatron/gigatron.cpp183
-rw-r--r--src/devices/cpu/gigatron/gigatron.h19
-rw-r--r--src/emu/gamedrv.h2
-rw-r--r--src/mame/drivers/gigatron.cpp16
4 files changed, 184 insertions, 36 deletions
diff --git a/src/devices/cpu/gigatron/gigatron.cpp b/src/devices/cpu/gigatron/gigatron.cpp
index b14fb25b68b..cbb26307ebf 100644
--- a/src/devices/cpu/gigatron/gigatron.cpp
+++ b/src/devices/cpu/gigatron/gigatron.cpp
@@ -1,5 +1,5 @@
-// license:BSD-3-Clause
-// copyright-holders:Sterophonick
+// license:BSD-2-Clause
+// copyright-holders:Sterophonick, Phil Thomas
/*****************************************************************************
*
* Skeleton device for Gigatron CPU Core
@@ -13,7 +13,7 @@
#include "gigatrondasm.h"
-DEFINE_DEVICE_TYPE(GTRON, gigatron_cpu_device, "gigatron_cpu", "Gigatron CPU Device")
+DEFINE_DEVICE_TYPE(GTRON, gigatron_cpu_device, "gigatron_cpu", "Gigatron")
/* FLAGS */
@@ -25,9 +25,11 @@ DEFINE_DEVICE_TYPE(GTRON, gigatron_cpu_device, "gigatron_cpu", "Gigatron CPU Dev
#endif
-#define gigatron_readop(A) m_program->read_dword(A)
+#define gigatron_readop(A) m_program->read_word(A)
#define gigatron_readmem16(A) m_data->read_dword(A)
+#define gigatron_readmem8(A) m_data->read_byte(A)
#define gigatron_writemem16(A,B) m_data->write_dword((A),B)
+#define gigatron_writemem8(A,B) m_data->write_byte((A),B)
/***********************************
@@ -54,7 +56,7 @@ void gigatron_cpu_device::execute_run()
uint8_t op = (opcode >> 13) & 0x0007;
uint8_t mode = (opcode >> 10) & 0x0007;
uint8_t bus = (opcode >> 8) & 0x0003;
- uint8_t d = (opcode >> 0) & 0x00ff;
+ uint16_t d = (opcode >> 0) & 0x00ff;
switch( op)
{
@@ -76,7 +78,7 @@ void gigatron_cpu_device::execute_run()
gigatron_illegal();
break;
}
-
+ m_icount--;
} while( m_icount > 0 );
}
@@ -95,6 +97,8 @@ void gigatron_cpu_device::init()
m_x = 0;
m_y = 0;
m_pc = 0;
+ m_npc = (m_pc + 1);
+ m_inReg = 0xFF;
state_add(GTRON_AC, "AC", m_ac);
state_add(GTRON_X, "X", m_x);
state_add(GTRON_Y, "Y", m_y);
@@ -102,29 +106,172 @@ void gigatron_cpu_device::init()
set_icountptr(m_icount);
}
-void gigatron_cpu_device::branchOp(int op, int mode, int bus, int d)
+void gigatron_cpu_device::branchOp(uint8_t op, uint8_t mode, uint8_t bus, uint8_t d)
{
+ const uint8_t ZERO = 0x80;
+ bool c = false;
+ uint8_t ac2 = m_ac ^ ZERO;
+ uint16_t base = m_pc & 0xff00;
+ switch (mode) {
+ case 0:
+ c = true;
+ base = m_y << 8;
+ break;
+ case 1:
+ c = (ac2 > ZERO);
+ break;
+ case 2:
+ c = (ac2 < ZERO);
+ break;
+ case 3:
+ c = (ac2 != ZERO);
+ break;
+ case 4:
+ c = (ac2 == ZERO);
+ break;
+ case 5:
+ c = (ac2 >= ZERO);
+ break;
+ case 6:
+ c = (ac2 <= ZERO);
+ break;
+ case 7:
+ c = true;
+ break;
+ }
+
+ if (c) {
+ uint8_t b = offset(bus, d);
+ m_npc = base | b;
+ }
}
-void gigatron_cpu_device::aluOp(int op, int mode, int bus, int d)
+void gigatron_cpu_device::aluOp(uint8_t op, uint8_t mode, uint8_t bus, uint16_t d)
{
- int b;
- (void)b;
+ uint8_t b = 0;
+ //(void)b;
switch(bus) {
case 0:
b = d;
break;
case 1:
+ b = gigatron_readmem8((uint16_t)(addr(mode, d) & m_ramMask));
+ break;
case 2:
b = m_ac;
break;
case 3:
+ b = m_inReg;
break;
}
+ switch(op) {
+ case 1:
+ b = (m_ac & b);
+ break;
+ case 2:
+ b = (m_ac | b);
+ break;
+ case 3:
+ b = (m_ac ^ b);
+ break;
+ case 4:
+ b = (m_ac + b);
+ break;
+ case 5:
+ b = (m_ac - b);
+ break;
+ }
+ switch (mode) {
+ case 0:
+ case 1:
+ case 2:
+ case 3:
+ m_ac = b;
+ break;
+ case 4:
+ m_x = b;
+ break;
+ case 5:
+ m_y = b;
+ break;
+ case 6:
+ case 7:
+ uint16_t rising = ~(m_out & b);
+ if (rising & 0x40) {
+ m_outx = m_ac;
+ }
+ break;
+
+ }
+}
+
+uint16_t gigatron_cpu_device::addr(uint8_t mode, uint16_t d)
+{
+ switch (mode) {
+ case 0:
+ case 4:
+ case 5:
+ case 6:
+ return d;
+ case 1:
+ return m_x;
+ case 2:
+ return (m_y << 8) | d;
+ case 3:
+ return (m_y << 8) | m_x;
+ case 7:
+ uint16_t addr2 = (m_y << 8) | m_x;
+ m_x = (m_x + 1) & 0xff;
+ return addr2;
+ }
+ return 0;
}
-void gigatron_cpu_device::storeOp(int op, int mode, int bus, int d)
+uint8_t gigatron_cpu_device::offset(uint8_t bus, uint16_t d)
{
+ switch (bus) {
+ case 0:
+ return d;
+ case 1:
+ return gigatron_readmem8(d);
+ case 2:
+ return m_ac;
+ case 3:
+ return m_inReg;
+ }
+ return 0;
+}
+
+void gigatron_cpu_device::storeOp(uint8_t op, uint8_t mode, uint8_t bus, uint16_t d)
+{
+ uint8_t b = 0;
+ switch (bus) {
+ case 0:
+ b = d;
+ break;
+ case 1:
+ b = 0;
+ logerror("UNDEFINED BEHAVIOR! 0x%04x\n", m_pc);
+ break;
+ case 2:
+ b = m_ac;
+ break;
+ case 3:
+ b = m_inReg;
+ break;
+ }
+
+ u16 address = addr(mode, d) & m_ramMask;
+ gigatron_writemem8(address, b);
+
+ switch (mode) {
+ case 4:
+ m_x = b;
+ break;
+ case 5:
+ m_y = b;
+ break;
+ }
}
void gigatron_cpu_device::device_reset()
@@ -136,19 +283,7 @@ void gigatron_cpu_device::execute_set_input(int irqline, int state)
#if 0
switch(irqline)
{
- case GTRON_INT_INTRM: // level-sensitive
- m_intrm_pending = ((ASSERT_LINE == state) || (HOLD_LINE == state));
- m_intrm_state = (ASSERT_LINE == state);
- break;
- case GTRON_RESET: // edge-sensitive
- if (CLEAR_LINE != state)
- m_reset_pending = 1;
- m_reset_state = (ASSERT_LINE == state);
- break;
- case GTRON_INT_INTR: // edge-sensitive
- if (CLEAR_LINE != state)
- m_intr_pending = 1;
- m_intr_state = (ASSERT_LINE == state);
+ default:
break;
}
#endif
diff --git a/src/devices/cpu/gigatron/gigatron.h b/src/devices/cpu/gigatron/gigatron.h
index 6717fd8b2a3..9da67a2cae7 100644
--- a/src/devices/cpu/gigatron/gigatron.h
+++ b/src/devices/cpu/gigatron/gigatron.h
@@ -1,8 +1,8 @@
-// license:BSD-3-Clause
-// copyright-holders:Sterophonick
+// license:BSD-2-Clause
+// copyright-holders:Sterophonick, Phil Thomas
/*****************************************************************************
*
- * Skeleton Device for Gigatron CPU Core
+ * Skeleton device for Gigatron CPU Core
*
*****************************************************************************/
@@ -46,13 +46,20 @@ protected:
// device_memory_interface overrides
virtual space_config_vector memory_space_config() const override;
- void branchOp(int op, int mode, int bus, int d);
- void aluOp(int op, int mode, int bus, int d);
- void storeOp(int op, int mode, int bus, int d);
+ void branchOp(uint8_t op, uint8_t mode, uint8_t bus, uint8_t d);
+ void aluOp(uint8_t op, uint8_t mode, uint8_t bus, uint16_t d);
+ void storeOp(uint8_t op, uint8_t mode, uint8_t bus, uint16_t d);
+ uint8_t offset(uint8_t bus, uint16_t d);
+ uint16_t addr(uint8_t mode, uint16_t d);
uint8_t m_ac;
uint8_t m_x;
uint8_t m_y;
+ uint8_t m_npc;
+ uint8_t m_inReg;
+ uint16_t m_ramMask;
+ uint16_t m_out;
+ uint16_t m_outx;
virtual void init();
diff --git a/src/emu/gamedrv.h b/src/emu/gamedrv.h
index 834f5b16a43..2843e7a36c8 100644
--- a/src/emu/gamedrv.h
+++ b/src/emu/gamedrv.h
@@ -75,7 +75,7 @@ constexpr u64 MACHINE_NO_SOUND_HW = machine_flags::NO_SOUND_HW;
constexpr u64 MACHINE_MECHANICAL = machine_flags::MECHANICAL;
constexpr u64 MACHINE_IS_INCOMPLETE = machine_flags::IS_INCOMPLETE;
-// flags taht map to device feature flags
+// flags that map to device feature flags
constexpr u64 MACHINE_UNEMULATED_PROTECTION = 0x00000001'00000000; // game's protection not fully emulated
constexpr u64 MACHINE_WRONG_COLORS = 0x00000002'00000000; // colors are totally wrong
constexpr u64 MACHINE_IMPERFECT_COLORS = 0x00000004'00000000; // colors are not 100% accurate, but close
diff --git a/src/mame/drivers/gigatron.cpp b/src/mame/drivers/gigatron.cpp
index 5085bc0c2e2..e26d75072ae 100644
--- a/src/mame/drivers/gigatron.cpp
+++ b/src/mame/drivers/gigatron.cpp
@@ -38,6 +38,11 @@ private:
void prog_map(address_map &map);
void data_map(address_map &map);
+
+ DECLARE_READ8_MEMBER(gigatron_random)
+ {
+ return machine().rand() & 0xff;
+ }
required_device<cpu_device> m_maincpu;
};
@@ -54,6 +59,7 @@ void gigatron_state::prog_map(address_map &map)
void gigatron_state::data_map(address_map &map)
{
+ map(0x4000, 0x7fff).r(FUNC(gigatron_state::gigatron_random));
}
void gigatron_state::machine_start()
@@ -75,7 +81,7 @@ void gigatron_state::gigatron(machine_config &config)
/* video hardware */
screen_device &screen(SCREEN(config, "screen", SCREEN_TYPE_RASTER));
- screen.set_refresh_hz(60);
+ screen.set_refresh_hz(59.98);
screen.set_size(640, 480);
screen.set_visarea(0, 640-1, 0, 480-1);
screen.set_screen_update(FUNC(gigatron_state::screen_update));
@@ -88,13 +94,13 @@ void gigatron_state::gigatron(machine_config &config)
ROM_START( gigatron )
ROM_REGION( 0x20000, "maincpu", 0 )
ROM_SYSTEM_BIOS(0, "v4", "Gigatron ROM V4")
- ROMX_LOAD( "romv4.rom", 0x0000, 0x20000, CRC(78995109) SHA1(2395fc48e64099836111f5aeca39ddbf4650ea4e),ROM_BIOS(0))
+ ROMX_LOAD( "gigrom4.rom", 0x0000, 0x20000, CRC(78995109) SHA1(2395fc48e64099836111f5aeca39ddbf4650ea4e),ROM_BIOS(0))
ROM_SYSTEM_BIOS(1, "v3", "Gigatron ROM V3")
- ROMX_LOAD( "romv3.rom", 0x0000, 0x20000, CRC(1536efbe) SHA1(959268069e761a01d620396eedb9abc1ee63c421),ROM_BIOS(1))
+ ROMX_LOAD( "gigrom3.rom", 0x0000, 0x20000, CRC(1536efbe) SHA1(959268069e761a01d620396eedb9abc1ee63c421),ROM_BIOS(1))
ROM_SYSTEM_BIOS(2, "v2", "Gigatron ROM V2")
- ROMX_LOAD( "romv2.rom", 0x0000, 0x20000, CRC(b4a3d936) SHA1(c93f417d589144b912c79f85b9e942d66242c2c3),ROM_BIOS(2))
+ ROMX_LOAD( "gigrom2.rom", 0x0000, 0x20000, CRC(b4a3d936) SHA1(c93f417d589144b912c79f85b9e942d66242c2c3),ROM_BIOS(2))
ROM_SYSTEM_BIOS(3, "v1", "Gigatron ROM V1")
- ROMX_LOAD( "romv1.rom", 0x0000, 0x20000, CRC(8ea5a2af) SHA1(e5758d5cc467c3476bd8f992fd45dfcdf06d0430),ROM_BIOS(3))
+ ROMX_LOAD( "gigrom1.rom", 0x0000, 0x20000, CRC(8ea5a2af) SHA1(e5758d5cc467c3476bd8f992fd45dfcdf06d0430),ROM_BIOS(3))
ROM_END
COMP(2018, gigatron, 0, 0, gigatron, gigatron, gigatron_state, empty_init, "Marcel van Kervinck", "Gigatron TTL Microcomputer", MACHINE_IS_SKELETON)