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author Nigel Barnes <Pernod70@users.noreply.github.com>2017-08-24 15:29:36 +0100
committer Nigel Barnes <Pernod70@users.noreply.github.com>2017-08-25 20:03:44 +0100
commitc967171c7a9ef9358b08e45fc66042590a6d4390 (patch)
tree28b7210e484c7fdd686386278b21cf3ca8b333f5
parent70b91571ce1b77abb593c341419076859e7a9323 (diff)
tube: New TUBE device. Acorn Tube ULA for use in Acorn 2nd Processors
-rw-r--r--scripts/src/machine.lua12
-rw-r--r--scripts/target/mame/mess.lua1
-rw-r--r--src/devices/machine/tube.cpp315
-rw-r--r--src/devices/machine/tube.h94
4 files changed, 422 insertions, 0 deletions
diff --git a/scripts/src/machine.lua b/scripts/src/machine.lua
index 277d6ba95e5..0609734ae24 100644
--- a/scripts/src/machine.lua
+++ b/scripts/src/machine.lua
@@ -2511,6 +2511,18 @@ end
---------------------------------------------------
--
+--@src/devices/machine/tube.h,MACHINES["TUBE"] = true
+---------------------------------------------------
+
+if (MACHINES["TUBE"]~=null) then
+ files {
+ MAME_DIR .. "src/devices/machine/tube.cpp",
+ MAME_DIR .. "src/devices/machine/tube.h",
+ }
+end
+
+---------------------------------------------------
+--
--@src/devices/machine/upd1990a.h,MACHINES["UPD1990A"] = true
---------------------------------------------------
diff --git a/scripts/target/mame/mess.lua b/scripts/target/mame/mess.lua
index be5ab241ff1..df4b9081394 100644
--- a/scripts/target/mame/mess.lua
+++ b/scripts/target/mame/mess.lua
@@ -564,6 +564,7 @@ MACHINES["TTL74175"] = true
MACHINES["TTL74181"] = true
MACHINES["TTL74259"] = true
MACHINES["TTL7474"] = true
+MACHINES["TUBE"] = true
MACHINES["UPD1990A"] = true
--MACHINES["UPD4992"] = true
MACHINES["UPD4701"] = true
diff --git a/src/devices/machine/tube.cpp b/src/devices/machine/tube.cpp
new file mode 100644
index 00000000000..aac084a3158
--- /dev/null
+++ b/src/devices/machine/tube.cpp
@@ -0,0 +1,315 @@
+// license:BSD-3-Clause
+// copyright-holders:Nigel Barnes
+/**********************************************************************
+
+ Acorn Tube ULA emulation
+
+ The Tube ULA acts as a parallel interface between two asynchronous
+ processor systems. It consists of four byte-wide read-only registers
+ and four byte-wide write-only registers. Eight bytes of memory mapped
+ I/O space are used to address these registers, four for the data
+ registers and four for the associated status registers.
+
+**********************************************************************/
+
+#include "emu.h"
+#include "machine/tube.h"
+
+
+
+//**************************************************************************
+// DEVICE DEFINITIONS
+//**************************************************************************
+
+DEFINE_DEVICE_TYPE(TUBE, tube_device, "tube", "Acorn Tube ULA")
+
+
+
+//-------------------------------------------------
+// bbc_tube_slot_device - constructor
+//-------------------------------------------------
+
+tube_device::tube_device(const machine_config &mconfig, const char *tag, device_t *owner, uint32_t clock) :
+ device_t(mconfig, TUBE, tag, owner, clock),
+ m_hirq_handler(*this),
+ m_pnmi_handler(*this),
+ m_pirq_handler(*this),
+ m_drq_handler(*this)
+{
+}
+
+
+//-------------------------------------------------
+// device_start - device-specific startup
+//-------------------------------------------------
+
+void tube_device::device_start()
+{
+ // resolve callbacks
+ m_hirq_handler.resolve_safe();
+ m_pnmi_handler.resolve_safe();
+ m_pirq_handler.resolve_safe();
+ m_drq_handler.resolve_safe();
+}
+
+
+//-------------------------------------------------
+// device_reset - device-specific reset
+//-------------------------------------------------
+
+void tube_device::device_reset()
+{
+ m_ph1pos = m_hp3pos = 0;
+ m_ph3pos = 1;
+ m_r1stat = 0;
+ m_hstat[0] = m_hstat[1] = m_hstat[3] = 0x40;
+ m_hstat[2] = 0xc0;
+ m_pstat[0] = m_pstat[1] = m_pstat[2] = m_pstat[3] = 0x40;
+}
+
+
+void tube_device::update_interrupts()
+{
+ m_hirq_handler(BIT(m_r1stat, 0) && BIT(m_hstat[3], 7) ? ASSERT_LINE : CLEAR_LINE);
+
+ m_pirq_handler((BIT(m_r1stat, 1) && BIT(m_pstat[0], 7)) || (BIT(m_r1stat, 2) && BIT(m_pstat[3], 7)) ? ASSERT_LINE : CLEAR_LINE);
+
+ m_pnmi_handler(BIT(m_r1stat, 3) && ((m_hp3pos > BIT(m_r1stat, 4)) || (m_ph3pos == 0)) ? ASSERT_LINE : CLEAR_LINE);
+
+ m_drq_handler(!BIT(m_r1stat, 4) && ((m_hp3pos > BIT(m_r1stat, 4)) || (m_ph3pos == 0)) ? ASSERT_LINE : CLEAR_LINE);
+}
+
+READ8_MEMBER(tube_device::host_r)
+{
+ uint8_t data = 0xfe;
+
+ switch (offset & 0x07)
+ {
+ case 0: /* Status and Register 1 flags */
+ data = (m_hstat[0] & 0xc0) | m_r1stat;
+ break;
+
+ case 1: /* Register 1 */
+ data = m_ph1[0];
+ for (int i = 0; i < 23; i++) m_ph1[i] = m_ph1[i + 1];
+ m_ph1pos--;
+ m_pstat[0] |= 0x40;
+ if (!m_ph1pos) m_hstat[0] &= ~0x80;
+ break;
+
+ case 2: /* Register 2 flags */
+ data = m_hstat[1];
+ break;
+
+ case 3: /* Register 2 */
+ data = m_ph2;
+ if (m_hstat[1] & 0x80)
+ {
+ m_hstat[1] &= ~0x80;
+ m_pstat[1] |= 0x40;
+ }
+ break;
+
+ case 4: /* Register 3 flags */
+ data = m_hstat[2];
+ break;
+
+ case 5: /* Register 3 */
+ data = m_ph3[0];
+ if (m_ph3pos > 0)
+ {
+ m_ph3[0] = m_ph3[1];
+ m_ph3pos--;
+ m_pstat[2] |= 0x40;
+ if (!m_ph3pos) m_hstat[2] &= ~0x80;
+ }
+ break;
+
+ case 6: /* Register 4 flags */
+ data = m_hstat[3];
+ break;
+
+ case 7: /* Register 4 */
+ data = m_ph4;
+ if (m_hstat[3] & 0x80)
+ {
+ m_hstat[3] &= ~0x80;
+ m_pstat[3] |= 0x40;
+ }
+ break;
+ }
+ update_interrupts();
+
+ return data;
+}
+
+WRITE8_MEMBER(tube_device::host_w)
+{
+ switch (offset & 0x07)
+ {
+ case 0: /* Status flags */
+ if (data & 0x80)
+ m_r1stat |= (data & 0x3f);
+ else
+ m_r1stat &= ~(data & 0x3f);
+ m_hstat[0] = (m_hstat[0] & 0xc0) | (data & 0x3f);
+ break;
+
+ case 1: /* Register 1 */
+ m_hp1 = data;
+ m_pstat[0] |= 0x80;
+ m_hstat[0] &= ~0x40;
+ break;
+
+ case 3: /* Register 2 */
+ m_hp2 = data;
+ m_pstat[1] |= 0x80;
+ m_hstat[1] &= ~0x40;
+ break;
+
+ case 5: /* Register 3 */
+ if (m_r1stat & 0x10)
+ {
+ if (m_hp3pos < 2)
+ m_hp3[m_hp3pos++] = data;
+ if (m_hp3pos == 2)
+ {
+ m_pstat[2] |= 0x80;
+ m_hstat[2] &= ~0x40;
+ }
+ }
+ else
+ {
+ m_hp3[0] = data;
+ m_hp3pos = 1;
+ m_pstat[2] |= 0x80;
+ m_hstat[2] &= ~0x40;
+ }
+ break;
+
+ case 7: /* Register 4 */
+ m_hp4 = data;
+ m_pstat[3] |= 0x80;
+ m_hstat[3] &= ~0x40;
+ break;
+ }
+
+ update_interrupts();
+}
+
+READ8_MEMBER(tube_device::parasite_r)
+{
+ uint8_t data = 0x00;
+
+ switch (offset & 0x07)
+ {
+ case 0: /*Register 1 flags */
+ data = m_pstat[0] | m_r1stat;
+ break;
+
+ case 1: /* Register 1 */
+ data = m_hp1;
+ if (m_pstat[0] & 0x80)
+ {
+ m_pstat[0] &= ~0x80;
+ m_hstat[0] |= 0x40;
+ }
+ break;
+
+ case 2: /* Register 2 flags */
+ data = m_pstat[1];
+ break;
+
+ case 3: /* Register 2 */
+ data = m_hp2;
+ if (m_pstat[1] & 0x80)
+ {
+ m_pstat[1] &= ~0x80;
+ m_hstat[1] |= 0x40;
+ }
+ break;
+
+ case 4: /* Register 3 flags */
+ data = m_pstat[2];
+ break;
+
+ case 5: /* Register 3 */
+ data = m_hp3[0];
+ if (m_hp3pos > 0)
+ {
+ m_hp3[0] = m_hp3[1];
+ m_hp3pos--;
+ if (!m_hp3pos)
+ {
+ m_hstat[2] |= 0x40;
+ m_pstat[2] &= ~0x80;
+ }
+ }
+ break;
+
+ case 6: /* Register 4 flags */
+ data = m_pstat[3];
+ break;
+
+ case 7: /* Register 4 */
+ data = m_hp4;
+ if (m_pstat[3] & 0x80)
+ {
+ m_pstat[3] &= ~0x80;
+ m_hstat[3] |= 0x40;
+ }
+ break;
+ }
+ update_interrupts();
+
+ return data;
+}
+
+WRITE8_MEMBER(tube_device::parasite_w)
+{
+ switch (offset & 0x07)
+ {
+ case 1: /* Register 1 */
+ if (m_ph1pos < 24)
+ {
+ m_ph1[m_ph1pos++] = data;
+ m_hstat[0] |= 0x80;
+ if (m_ph1pos == 24)
+ m_pstat[0] &= ~0x40;
+ }
+ break;
+
+ case 3: /* Register 2 */
+ m_ph2 = data;
+ m_hstat[1] |= 0x80;
+ m_pstat[1] &= ~0x40;
+ break;
+
+ case 5: /* Register 3 */
+ if (m_r1stat & 0x10)
+ {
+ if (m_ph3pos < 2)
+ m_ph3[m_ph3pos++] = data;
+ if (m_ph3pos == 2)
+ {
+ m_hstat[2] |= 0x80;
+ m_pstat[2] &= ~0x40;
+ }
+ }
+ else
+ {
+ m_ph3[0] = data;
+ m_ph3pos = 1;
+ m_hstat[2] |= 0x80;
+ m_pstat[2] &= ~0x40;
+ }
+ break;
+
+ case 7: /* Register 4 */
+ m_ph4 = data;
+ m_hstat[3] |= 0x80;
+ m_pstat[3] &= ~0x40;
+ break;
+ }
+ update_interrupts();
+}
diff --git a/src/devices/machine/tube.h b/src/devices/machine/tube.h
new file mode 100644
index 00000000000..ffa27bac813
--- /dev/null
+++ b/src/devices/machine/tube.h
@@ -0,0 +1,94 @@
+// license:BSD-3-Clause
+// copyright-holders:Nigel Barnes
+/**********************************************************************
+
+ Acorn Tube ULA emulation
+
+**********************************************************************/
+
+#ifndef MAME_MACHINE_TUBE_H
+#define MAME_MACHINE_TUBE_H
+
+#pragma once
+
+
+
+//**************************************************************************
+// INTERFACE CONFIGURATION MACROS
+//**************************************************************************
+
+#define MCFG_TUBE_ADD(_tag) \
+ MCFG_DEVICE_ADD(_tag, TUBE, 0);
+
+#define MCFG_TUBE_HIRQ_HANDLER(_devcb) \
+ devcb = &tube_device::set_hirq_handler(*device, DEVCB_##_devcb);
+
+#define MCFG_TUBE_PNMI_HANDLER(_devcb) \
+ devcb = &tube_device::set_pnmi_handler(*device, DEVCB_##_devcb);
+
+#define MCFG_TUBE_PIRQ_HANDLER(_devcb) \
+ devcb = &tube_device::set_pirq_handler(*device, DEVCB_##_devcb);
+
+#define MCFG_TUBE_DRQ_HANDLER(_devcb) \
+ devcb = &tube_device::set_drq_handler(*device, DEVCB_##_devcb);
+
+
+
+//**************************************************************************
+// TYPE DEFINITIONS
+//**************************************************************************
+
+
+// ======================> tube_device
+
+class tube_device : public device_t
+{
+public:
+ // construction/destruction
+ tube_device(const machine_config &mconfig, const char *tag, device_t *owner, uint32_t clock);
+
+ // callbacks
+ template <class Object> static devcb_base &set_hirq_handler(device_t &device, Object &&cb) { return downcast<tube_device &>(device).m_hirq_handler.set_callback(std::forward<Object>(cb)); }
+ template <class Object> static devcb_base &set_pnmi_handler(device_t &device, Object &&cb) { return downcast<tube_device &>(device).m_pnmi_handler.set_callback(std::forward<Object>(cb)); }
+ template <class Object> static devcb_base &set_pirq_handler(device_t &device, Object &&cb) { return downcast<tube_device &>(device).m_pirq_handler.set_callback(std::forward<Object>(cb)); }
+ template <class Object> static devcb_base &set_drq_handler(device_t &device, Object &&cb) { return downcast<tube_device &>(device).m_drq_handler.set_callback(std::forward<Object>(cb)); }
+
+ DECLARE_READ8_MEMBER(host_r);
+ DECLARE_WRITE8_MEMBER(host_w);
+ DECLARE_READ8_MEMBER(parasite_r);
+ DECLARE_WRITE8_MEMBER(parasite_w);
+
+protected:
+ // device-level overrides
+ virtual void device_start() override;
+ virtual void device_reset() override;
+
+private:
+ uint8_t m_ph1[24];
+ uint8_t m_ph2;
+ uint8_t m_ph3[2];
+ uint8_t m_ph4;
+ uint8_t m_hp1;
+ uint8_t m_hp2;
+ uint8_t m_hp3[2];
+ uint8_t m_hp4;
+ uint8_t m_hstat[4];
+ uint8_t m_pstat[4];
+ uint8_t m_r1stat;
+ int m_ph1pos;
+ int m_ph3pos;
+ int m_hp3pos;
+
+ void update_interrupts();
+
+ devcb_write_line m_hirq_handler;
+ devcb_write_line m_pnmi_handler;
+ devcb_write_line m_pirq_handler;
+ devcb_write_line m_drq_handler;
+};
+
+
+// device type definition
+DECLARE_DEVICE_TYPE(TUBE, tube_device)
+
+#endif // MAME_MACHINE_TUBE_H