diff options
author | R. Belmont <rb6502@users.noreply.github.com> | 2011-06-24 00:43:24 +0000 |
---|---|---|
committer | R. Belmont <rb6502@users.noreply.github.com> | 2011-06-24 00:43:24 +0000 |
commit | fae75d234f7ef2b295882db67d505bda4b29e338 (patch) | |
tree | 9f348a9296bdcd256e842c0ab27a2470bca67261 | |
parent | 2ff0608ea406da68d89c2a03f84903ea90875462 (diff) |
SH4: Misc cleanups, added support for VERSION register. Naomi rev H BIOS now boots games. [O. Galibert, Deunan Knute, R. Belmont]
-rw-r--r-- | src/emu/cpu/sh4/sh4.c | 51 | ||||
-rw-r--r-- | src/emu/cpu/sh4/sh4comn.c | 18 | ||||
-rw-r--r-- | src/emu/cpu/sh4/sh4comn.h | 26 | ||||
-rw-r--r-- | src/emu/cpu/sh4/sh4regs.h | 1 |
4 files changed, 32 insertions, 64 deletions
diff --git a/src/emu/cpu/sh4/sh4.c b/src/emu/cpu/sh4/sh4.c index 58d69892872..0b6c6956c43 100644 --- a/src/emu/cpu/sh4/sh4.c +++ b/src/emu/cpu/sh4/sh4.c @@ -28,8 +28,6 @@ #include "sh4regs.h" #include "sh4comn.h" -//#define SHOW_AARON_BUG - #ifndef USE_SH4DRC CPU_DISASSEMBLE( sh4 ); @@ -119,9 +117,6 @@ UINT32 abs; INLINE UINT8 RB(sh4_state *sh4, offs_t A) { - if (A >= 0xfe000000) - return sh4_internal_r(sh4->internal, ((A & 0x0fc) >> 2) | ((A & 0x1fe0000) >> 11), 0xff << ((A & 3)*8)) >> ((A & 3)*8); - if (A >= 0xe0000000) return sh4->program->read_byte(A); @@ -130,9 +125,6 @@ INLINE UINT8 RB(sh4_state *sh4, offs_t A) INLINE UINT16 RW(sh4_state *sh4, offs_t A) { - if (A >= 0xfe000000) - return sh4_internal_r(sh4->internal, ((A & 0x0fc) >> 2) | ((A & 0x1fe0000) >> 11), 0xffff << ((A & 2)*8)) >> ((A & 2)*8); - if (A >= 0xe0000000) return sh4->program->read_word(A); @@ -141,25 +133,14 @@ INLINE UINT16 RW(sh4_state *sh4, offs_t A) INLINE UINT32 RL(sh4_state *sh4, offs_t A) { - if (A >= 0xfe000000) - return sh4_internal_r(sh4->internal, ((A & 0x0fc) >> 2) | ((A & 0x1fe0000) >> 11), 0xffffffff); - if (A >= 0xe0000000) return sh4->program->read_dword(A); - return sh4->program->read_dword(A & AM); + return sh4->program->read_dword(A & AM); } INLINE void WB(sh4_state *sh4, offs_t A, UINT8 V) { - #ifndef SHOW_AARON_BUG - if (A >= 0xfe000000) - { - sh4_internal_w(sh4->internal, ((A & 0x0fc) >> 2) | ((A & 0x1fe0000) >> 11), V << ((A & 3)*8), 0xff << ((A & 3)*8)); - return; - } - #endif - if (A >= 0xe0000000) { sh4->program->write_byte(A,V); @@ -171,14 +152,6 @@ INLINE void WB(sh4_state *sh4, offs_t A, UINT8 V) INLINE void WW(sh4_state *sh4, offs_t A, UINT16 V) { - #ifndef SHOW_AARON_BUG - if (A >= 0xfe000000) - { - sh4_internal_w(sh4->internal, ((A & 0x0fc) >> 2) | ((A & 0x1fe0000) >> 11), V << ((A & 2)*8), 0xffff << ((A & 2)*8)); - return; - } - #endif - if (A >= 0xe0000000) { sh4->program->write_word(A,V); @@ -190,23 +163,12 @@ INLINE void WW(sh4_state *sh4, offs_t A, UINT16 V) INLINE void WL(sh4_state *sh4, offs_t A, UINT32 V) { - #ifndef SHOW_AARON_BUG - if (A >= 0xfe000000) - { - sh4_internal_w(sh4->internal, ((A & 0x0fc) >> 2) | ((A & 0x1fe0000) >> 11), V, 0xffffffff); - return; - } - #endif - if (A >= 0xe0000000) { sh4->program->write_dword(A,V); return; } -/* if (A >= 0x40000000) - return;*/ - sh4->program->write_dword(A & AM,V); } @@ -3616,22 +3578,13 @@ static ADDRESS_MAP_START( sh4_internal_map, AS_PROGRAM, 64 ) ADDRESS_MAP_END #endif -#ifdef SHOW_AARON_BUG -static WRITE32_HANDLER(sh4_test_w) -{ - printf("offset = %08x, data = %08x, mask = %08x\n", offset, data, mem_mask); -} -#endif - /*When OC index mode is on (CCR.OIX = 1)*/ static ADDRESS_MAP_START( sh4_internal_map, AS_PROGRAM, 64 ) AM_RANGE(0x1C000000, 0x1C000FFF) AM_RAM AM_MIRROR(0x01FFF000) AM_RANGE(0x1E000000, 0x1E000FFF) AM_RAM AM_MIRROR(0x01FFF000) AM_RANGE(0xE0000000, 0xE000003F) AM_RAM AM_MIRROR(0x03FFFFC0) // todo: store queues should be write only on DC's SH4, executing PREFM shouldn't cause an actual memory read access! AM_RANGE(0xF6000000, 0xF7FFFFFF) AM_READWRITE(sh4_tlb_r,sh4_tlb_w) -#ifdef SHOW_AARON_BUG - AM_RANGE(0xFE000000, 0xFFFFFFFF) AM_WRITE32(sh4_test_w, U64(0xffffffffffffffff)) -#endif + AM_RANGE(0xFE000000, 0xFFFFFFFF) AM_READWRITE32(sh4_internal_r, sh4_internal_w, U64(0xffffffffffffffff)) ADDRESS_MAP_END diff --git a/src/emu/cpu/sh4/sh4comn.c b/src/emu/cpu/sh4/sh4comn.c index 9d04bf64b8f..a4b261283cf 100644 --- a/src/emu/cpu/sh4/sh4comn.c +++ b/src/emu/cpu/sh4/sh4comn.c @@ -627,10 +627,13 @@ WRITE32_HANDLER( sh4_internal_w ) { sh4_state *sh4 = get_safe_token(&space->device()); int a; + UINT32 addr = (offset << 2) + 0xfe000000; + offset = ((addr & 0xfc) >> 2) | ((addr & 0x1fe0000) >> 11); + UINT32 old = sh4->m[offset]; COMBINE_DATA(sh4->m+offset); - // logerror("sh4_internal_w: Write %08x (%x), %08x @ %08x\n", 0xfe000000+((offset & 0x3fc0) << 11)+((offset & 0x3f) << 2), offset, data, mem_mask); +// printf("sh4_internal_w: Write %08x (%x), %08x @ %08x\n", 0xfe000000+((offset & 0x3fc0) << 11)+((offset & 0x3f) << 2), offset, data, mem_mask); switch( offset ) { @@ -938,9 +941,20 @@ WRITE32_HANDLER( sh4_internal_w ) READ32_HANDLER( sh4_internal_r ) { sh4_state *sh4 = get_safe_token(&space->device()); - // logerror("sh4_internal_r: Read %08x (%x) @ %08x\n", 0xfe000000+((offset & 0x3fc0) << 11)+((offset & 0x3f) << 2), offset, mem_mask); + + UINT32 addr = (offset << 2) + 0xfe000000; + offset = ((addr & 0xfc) >> 2) | ((addr & 0x1fe0000) >> 11); + +// printf("sh4_internal_r: Read %08x (%x) @ %08x\n", 0xfe000000+((offset & 0x3fc0) << 11)+((offset & 0x3f) << 2), offset, mem_mask); + switch( offset ) { + case VERSION: + return 0x040205c1; // this is what a real SH7750 in a Dreamcast returns - the later Naomi BIOSes check and care! + break; + case IPRD: + return 0x00000000; // SH7750 ignores writes here and always returns zero + break; case RTCNT: if ((sh4->m[RTCSR] >> 3) & 7) { // activated diff --git a/src/emu/cpu/sh4/sh4comn.h b/src/emu/cpu/sh4/sh4comn.h index 42a88141158..ef589829c4c 100644 --- a/src/emu/cpu/sh4/sh4comn.h +++ b/src/emu/cpu/sh4/sh4comn.h @@ -134,19 +134,19 @@ typedef struct UINT32 irq; /* irq we're taking */ /* register mappings */ - drcuml_parameter regmap[16]; /* parameter to register mappings for all 16 integer registers */ - - drcuml_codehandle * entry; /* entry point */ - drcuml_codehandle * read8; /* read byte */ - drcuml_codehandle * write8; /* write byte */ - drcuml_codehandle * read16; /* read half */ - drcuml_codehandle * write16; /* write half */ - drcuml_codehandle * read32; /* read word */ - drcuml_codehandle * write32; /* write word */ - - drcuml_codehandle * interrupt; /* interrupt */ - drcuml_codehandle * nocode; /* nocode */ - drcuml_codehandle * out_of_cycles; /* out of cycles exception handler */ + uml::parameter regmap[16]; /* parameter to register mappings for all 16 integer registers */ + + uml::code_handle * entry; /* entry point */ + uml::code_handle * read8; /* read byte */ + uml::code_handle * write8; /* write byte */ + uml::code_handle * read16; /* read half */ + uml::code_handle * write16; /* write half */ + uml::code_handle * read32; /* read word */ + uml::code_handle * write32; /* write word */ + + uml::code_handle * interrupt; /* interrupt */ + uml::code_handle * nocode; /* nocode */ + uml::code_handle * out_of_cycles; /* out of cycles exception handler */ UINT32 prefadr; UINT32 target; diff --git a/src/emu/cpu/sh4/sh4regs.h b/src/emu/cpu/sh4/sh4regs.h index 44738289a45..b8c2233e3f9 100644 --- a/src/emu/cpu/sh4/sh4regs.h +++ b/src/emu/cpu/sh4/sh4regs.h @@ -15,6 +15,7 @@ #define TRA 0x2008 /* FF000020 */ #define EXPEVT 0x2009 /* FF000024 */ #define INTEVT 0x200A /* FF000028 */ +#define VERSION 0x200C /* FF000030 */ #define PTEA 0x200D /* FF000034 */ #define QACR0 0x200E /* FF000038 */ #define QACR1 0x200F /* FF00003C */ |