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author Ryan Holtz <rholtz@batcountryentertainment.com>2010-10-09 09:58:51 +0000
committer Ryan Holtz <rholtz@batcountryentertainment.com>2010-10-09 09:58:51 +0000
commita21c960b56920acc5bbece27703827518ba7ea56 (patch)
tree97d632029d533b0884e4372acd86d410d33cff3b
parentec998af5e0dd438c1f49bee390413def2f7efae4 (diff)
Added UART Tx/Rx framework to the CD-i 68070 implementation, necessary for Quizard protection. [Harmony]
Changed default CD-i SLAVE video setting to PAL, necessary for Quizard to boot. [Harmony]
-rw-r--r--src/mame/drivers/cdi.c15
-rw-r--r--src/mame/machine/cdi070.c253
-rw-r--r--src/mame/machine/cdi070.h14
-rw-r--r--src/mame/machine/cdislave.c30
4 files changed, 273 insertions, 39 deletions
diff --git a/src/mame/drivers/cdi.c b/src/mame/drivers/cdi.c
index 25f1f8acdc1..4cfde1b9ff3 100644
--- a/src/mame/drivers/cdi.c
+++ b/src/mame/drivers/cdi.c
@@ -131,9 +131,6 @@ static MACHINE_START( cdi )
cdi_state *state = machine->driver_data<cdi_state>();
scc68070_register_globals(machine, &state->scc68070_regs);
-
- state->scc68070_regs.timers.timer0_timer = timer_alloc(machine, scc68070_timer0_callback, 0);
- timer_adjust_oneshot(state->scc68070_regs.timers.timer0_timer, attotime_never, 0);
}
static MACHINE_RESET( cdi )
@@ -309,9 +306,9 @@ ROM_END
/* rom parent machine inp init */
GAME( 1991, cdi, 0, cdi, cdi, 0, ROT0, "Philips", "CD-i (Mono-I) BIOS", GAME_IS_BIOS_ROOT )
-GAME( 1996, quizard, cdi, cdi, cdi, 0, ROT0, "TAB Austria", "Quizard 3.2", GAME_NOT_WORKING )
-GAME( 1995, quizrd22, cdi, cdi, cdi, 0, ROT0, "TAB Austria", "Quizard 2.2", GAME_NOT_WORKING )
-GAME( 1995, quizrd17, cdi, cdi, cdi, 0, ROT0, "TAB Austria", "Quizard 1.7", GAME_NOT_WORKING )
-GAME( 1995, quizrd12, cdi, cdi, cdi, 0, ROT0, "TAB Austria", "Quizard 1.2", GAME_NOT_WORKING )
-GAME( 1998, quizrr42, cdi, cdi, cdi, 0, ROT0, "TAB Austria", "Quizard Rainbow 4.2", GAME_NOT_WORKING )
-GAME( 1998, quizrr41, cdi, cdi, cdi, 0, ROT0, "TAB Austria", "Quizard Rainbow 4.1", GAME_NOT_WORKING )
+GAME( 1996, quizard, cdi, cdi, cdi, 0, ROT0, "TAB Austria", "Quizard 3.2", GAME_NOT_WORKING | GAME_UNEMULATED_PROTECTION )
+GAME( 1995, quizrd22, cdi, cdi, cdi, 0, ROT0, "TAB Austria", "Quizard 2.2", GAME_NOT_WORKING | GAME_UNEMULATED_PROTECTION )
+GAME( 1995, quizrd17, cdi, cdi, cdi, 0, ROT0, "TAB Austria", "Quizard 1.7", GAME_NOT_WORKING | GAME_UNEMULATED_PROTECTION )
+GAME( 1995, quizrd12, cdi, cdi, cdi, 0, ROT0, "TAB Austria", "Quizard 1.2", GAME_NOT_WORKING | GAME_UNEMULATED_PROTECTION )
+GAME( 1998, quizrr42, cdi, cdi, cdi, 0, ROT0, "TAB Austria", "Quizard Rainbow 4.2", GAME_NOT_WORKING | GAME_UNEMULATED_PROTECTION )
+GAME( 1998, quizrr41, cdi, cdi, cdi, 0, ROT0, "TAB Austria", "Quizard Rainbow 4.1", GAME_NOT_WORKING | GAME_UNEMULATED_PROTECTION )
diff --git a/src/mame/machine/cdi070.c b/src/mame/machine/cdi070.c
index 3ccf9efade4..98dfcb3fcd8 100644
--- a/src/mame/machine/cdi070.c
+++ b/src/mame/machine/cdi070.c
@@ -24,6 +24,8 @@ TODO:
#include "machine/cdi070.h"
#include "includes/cdi.h"
+#define ENABLE_QUIZARD_HACK (0)
+
#if ENABLE_VERBOSE_LOG
INLINE void verboselog(running_machine *machine, int n_level, const char *s_fmt, ...)
{
@@ -68,12 +70,161 @@ TIMER_CALLBACK( scc68070_timer0_callback )
{
UINT8 interrupt = scc68070->picr1 & 7;
scc68070->timers.timer_status_register |= TSR_OV0;
- cpu_set_input_line_vector(machine->device("maincpu"), M68K_IRQ_1 + (interrupt - 1), 56 + interrupt);
- cputag_set_input_line(machine, "maincpu", M68K_IRQ_1 + (interrupt - 1), ASSERT_LINE);
+ if(interrupt)
+ {
+ cpu_set_input_line_vector(machine->device("maincpu"), M68K_IRQ_1 + (interrupt - 1), 56 + interrupt);
+ cputag_set_input_line(machine, "maincpu", M68K_IRQ_1 + (interrupt - 1), ASSERT_LINE);
+ }
}
+
+#if ENABLE_QUIZARD_HACK
+ address_space *space = cputag_get_address_space(machine, "maincpu", ADDRESS_SPACE_PROGRAM);
+
+ space->write_byte(0xc000-0x792c,0x01);
+ space->write_byte(0xc000-0x7a6c,0x01);
+ //space->write_byte(0xc000-0x7a6b,0x01);
+ //space->write_byte(0xc000-0x7a6a,0x01);
+ //space->write_byte(0xc000-0x7a69,0x01);
+ //space->write_byte(0xc000-0x7a68,0x01);
+ //space->write_byte(0xc000-0x7a67,0x01);
+ //space->write_byte(0xc000-0x7a66,0x01);
+ //space->write_byte(0xc000-0x7a64,0x01);
+ //space->write_byte(0xc000-0x7a63,0x01);
+ //space->write_byte(0xc000-0x7a62,0x01);
+ //space->write_byte(0xc000-0x7a61,0x01);
+ //space->write_byte(0xc000-0x7a5e,0x01);
+ //space->write_byte(0xc000-0x7a5a,0x01);
+ //space->write_byte(0xc000-0x7a48,0x01);
+ //space->write_byte(0xc000-0x7a4c,0x01);
+ //space->write_byte(0xc000-0x78ce,0x01);
+ //space->write_byte(0xc000-0x78cd,0x01);
+ //space->write_byte(0xc000-0x78cc,0x01);
+#endif
+
scc68070_set_timer_callback(&state->scc68070_regs, 0);
}
+static void scc68070_uart_rx_check(running_machine *machine, scc68070_regs_t *scc68070)
+{
+ if((scc68070->uart.command_register & 3) == 1 &&
+ scc68070->uart.receive_pointer > -1 &&
+ attotime_compare(timer_timeleft(scc68070->uart.rx_timer), attotime_zero) != 0)
+ {
+ UINT32 div = 0x10000 >> ((scc68070->uart.clock_select >> 4) & 7);
+ timer_adjust_oneshot(scc68070->uart.rx_timer, ATTOTIME_IN_HZ((49152000 / div) / 8), 0);
+ }
+ else
+ {
+ scc68070->uart.status_register &= ~USR_RXRDY;
+ timer_adjust_oneshot(scc68070->uart.rx_timer, attotime_never, 0);
+ }
+}
+
+static void scc68070_uart_tx_check(running_machine *machine, scc68070_regs_t *scc68070)
+{
+ if(scc68070->uart.transmit_pointer > -1 &&
+ attotime_compare(timer_timeleft(scc68070->uart.tx_timer), attotime_zero) != 0)
+ {
+ UINT32 div = 0x10000 >> (scc68070->uart.clock_select & 7);
+ timer_adjust_oneshot(scc68070->uart.tx_timer, ATTOTIME_IN_HZ((49152000 / div) / 8), 0);
+ }
+ else
+ {
+ timer_adjust_oneshot(scc68070->uart.tx_timer, attotime_never, 0);
+ }
+}
+
+void scc68070_uart_rx(running_machine *machine, scc68070_regs_t *scc68070, UINT8 data)
+{
+ scc68070->uart.receive_pointer++;
+ scc68070->uart.receive_buffer[scc68070->uart.receive_pointer] = data;
+ scc68070->uart.status_register |= USR_RXRDY;
+ scc68070_uart_rx_check(machine, scc68070);
+}
+
+void scc68070_uart_tx(running_machine *machine, scc68070_regs_t *scc68070, UINT8 data)
+{
+ scc68070->uart.transmit_pointer++;
+ scc68070->uart.transmit_buffer[scc68070->uart.transmit_pointer] = data;
+ scc68070_uart_tx_check(machine, scc68070);
+}
+
+TIMER_CALLBACK( scc68070_rx_callback )
+{
+ cdi_state *state = machine->driver_data<cdi_state>();
+ scc68070_regs_t *scc68070 = &state->scc68070_regs;
+
+ if((scc68070->uart.command_register & 3) == 1)
+ {
+ UINT8 interrupt = (scc68070->picr2 >> 4) & 7;
+ if(interrupt)
+ {
+ cpu_set_input_line_vector(machine->device("maincpu"), M68K_IRQ_1 + (interrupt - 1), 56 + interrupt);
+ cputag_set_input_line(machine, "maincpu", M68K_IRQ_1 + (interrupt - 1), ASSERT_LINE);
+ }
+
+ if(scc68070->uart.receive_pointer > -1)
+ {
+ scc68070->uart.status_register |= USR_RXRDY;
+ UINT32 div = 0x10000 >> ((scc68070->uart.clock_select >> 4) & 7);
+ timer_adjust_oneshot(scc68070->uart.rx_timer, ATTOTIME_IN_HZ((49152000 / div) / 8), 0);
+ }
+ else
+ {
+ scc68070->uart.status_register &= ~USR_RXRDY;
+ timer_adjust_oneshot(scc68070->uart.rx_timer, attotime_never, 0);
+ }
+ }
+ else
+ {
+ scc68070->uart.status_register &= ~USR_RXRDY;
+ timer_adjust_oneshot(scc68070->uart.rx_timer, attotime_never, 0);
+ }
+}
+
+static void scc68070_tx_empty(running_machine *machine, scc68070_regs_t *scc68070)
+{
+ UINT8 interrupt = scc68070->picr2 & 7;
+ scc68070->uart.status_register |= USR_TXRDY;
+ if(interrupt)
+ {
+ cpu_set_input_line_vector(machine->device("maincpu"), M68K_IRQ_1 + (interrupt - 1), 56 + interrupt);
+ cputag_set_input_line(machine, "maincpu", M68K_IRQ_1 + (interrupt - 1), ASSERT_LINE);
+ }
+}
+
+TIMER_CALLBACK( scc68070_tx_callback )
+{
+ cdi_state *state = machine->driver_data<cdi_state>();
+ scc68070_regs_t *scc68070 = &state->scc68070_regs;
+
+ if(((scc68070->uart.command_register >> 2) & 3) == 1)
+ {
+ scc68070->uart.transmit_holding_register = scc68070->uart.transmit_buffer[0];
+ verboselog(machine, 2, "scc68070_tx_callback: Transmitting %02x\n", scc68070->uart.transmit_holding_register);
+ scc68070->uart.transmit_pointer--;
+ for(int index = 0; index < scc68070->uart.transmit_pointer; index++)
+ {
+ scc68070->uart.transmit_buffer[index] = scc68070->uart.transmit_buffer[index+1];
+ }
+
+ if(scc68070->uart.transmit_pointer > -1)
+ {
+ UINT32 div = 0x10000 >> (scc68070->uart.clock_select & 7);
+ timer_adjust_oneshot(scc68070->uart.tx_timer, ATTOTIME_IN_HZ((49152000 / div) / 8), 0);
+ }
+ else
+ {
+ timer_adjust_oneshot(scc68070->uart.tx_timer, attotime_never, 0);
+ scc68070_tx_empty(machine, scc68070);
+ }
+ }
+ else
+ {
+ timer_adjust_oneshot(scc68070->uart.tx_timer, attotime_never, 0);
+ }
+}
+
READ16_HANDLER( scc68070_periphs_r )
{
cdi_state *state = space->machine->driver_data<cdi_state>();
@@ -123,38 +274,75 @@ READ16_HANDLER( scc68070_periphs_r )
{
verboselog(space->machine, 2, "scc68070_periphs_r: UART Mode Register: %04x & %04x\n", scc68070->uart.mode_register, mem_mask);
}
+ else
+ {
+ verboselog(space->machine, 0, "scc68070_periphs_r: Unknown address: %04x & %04x\n", offset * 2, mem_mask);
+ }
return scc68070->uart.mode_register | 0x20;
case 0x2012/2:
+ scc68070->uart.status_register |= (1 << 1);
if(ACCESSING_BITS_0_7)
{
verboselog(space->machine, 2, "scc68070_periphs_r: UART Status Register: %04x & %04x\n", scc68070->uart.status_register, mem_mask);
}
- return scc68070->uart.status_register /*| USR_TXEMT*/ | USR_TXRDY | (1 << 1) | USR_RXRDY;
+ else
+ {
+ verboselog(space->machine, 0, "scc68070_periphs_r: Unknown address: %04x & %04x\n", offset * 2, mem_mask);
+ }
+ return scc68070->uart.status_register;
case 0x2014/2:
if(ACCESSING_BITS_0_7)
{
verboselog(space->machine, 2, "scc68070_periphs_r: UART Clock Select: %04x & %04x\n", scc68070->uart.clock_select, mem_mask);
}
+ else
+ {
+ verboselog(space->machine, 0, "scc68070_periphs_r: Unknown address: %04x & %04x\n", offset * 2, mem_mask);
+ }
return scc68070->uart.clock_select | 0x08;
case 0x2016/2:
if(ACCESSING_BITS_0_7)
{
verboselog(space->machine, 2, "scc68070_periphs_r: UART Command Register: %02x & %04x\n", scc68070->uart.command_register, mem_mask);
}
+ else
+ {
+ verboselog(space->machine, 0, "scc68070_periphs_r: Unknown address: %04x & %04x\n", offset * 2, mem_mask);
+ }
return scc68070->uart.command_register | 0x80;
case 0x2018/2:
if(ACCESSING_BITS_0_7)
{
verboselog(space->machine, 2, "scc68070_periphs_r: UART Transmit Holding Register: %02x & %04x\n", scc68070->uart.transmit_holding_register, mem_mask);
}
+ else
+ {
+ verboselog(space->machine, 0, "scc68070_periphs_r: Unknown address: %04x & %04x\n", offset * 2, mem_mask);
+ }
return scc68070->uart.transmit_holding_register;
case 0x201a/2:
if(ACCESSING_BITS_0_7)
{
+ scc68070->uart.receive_holding_register = 0;
+ if(scc68070->uart.receive_pointer != -1)
+ {
+ scc68070->uart.receive_holding_register = scc68070->uart.receive_buffer[0];
+ scc68070->uart.receive_pointer--;
+ for(int index = 0; index < scc68070->uart.receive_pointer; index++)
+ {
+ scc68070->uart.receive_buffer[index] = scc68070->uart.receive_buffer[index + 1];
+ }
+
+ UINT8 interrupt = (scc68070->picr2 >> 4) & 7;
+ cputag_set_input_line(space->machine, "maincpu", M68K_IRQ_1 + (interrupt - 1), CLEAR_LINE);
+ }
verboselog(space->machine, 2, "scc68070_periphs_r: UART Receive Holding Register: %02x & %04x\n", scc68070->uart.receive_holding_register, mem_mask);
- return scc68070->uart.receive_holding_register;
}
- return 0;
+ else
+ {
+ verboselog(space->machine, 0, "scc68070_periphs_r: Unknown address: %04x & %04x\n", offset * 2, mem_mask);
+ }
+ return scc68070->uart.receive_holding_register;
// Timers: 80002020 to 80002029
case 0x2020/2:
@@ -175,11 +363,9 @@ READ16_HANDLER( scc68070_periphs_r )
return scc68070->timers.timer0;
case 0x2026/2:
verboselog(space->machine, 2, "scc68070_periphs_r: Timer 1: %04x & %04x\n", scc68070->timers.timer1, mem_mask);
- printf( "Timer 1 read\n" );
return scc68070->timers.timer1;
case 0x2028/2:
verboselog(space->machine, 2, "scc68070_periphs_r: Timer 2: %04x & %04x\n", scc68070->timers.timer2, mem_mask);
- printf( "Timer 2 read\n" );
return scc68070->timers.timer2;
// PICR1: 80002045
@@ -196,7 +382,7 @@ READ16_HANDLER( scc68070_periphs_r )
{
verboselog(space->machine, 2, "scc68070_periphs_r: Peripheral Interrupt Control Register 2: %02x & %04x\n", scc68070->picr2, mem_mask);
}
- return scc68070->picr2;
+ return scc68070->picr2 & 0x77;
// DMA controller: 80004000 to 8000406d
case 0x4000/2:
@@ -374,6 +560,10 @@ WRITE16_HANDLER( scc68070_periphs_w )
verboselog(space->machine, 2, "scc68070_periphs_w: UART Mode Register: %04x & %04x\n", data, mem_mask);
scc68070->uart.mode_register = data & 0x00ff;
}
+ else
+ {
+ verboselog(space->machine, 0, "scc68070_periphs_w: Unknown address: %04x = %04x & %04x\n", offset * 2, data, mem_mask);
+ }
break;
case 0x2012/2:
if(ACCESSING_BITS_0_7)
@@ -381,6 +571,10 @@ WRITE16_HANDLER( scc68070_periphs_w )
verboselog(space->machine, 2, "scc68070_periphs_w: UART Status Register: %04x & %04x\n", data, mem_mask);
scc68070->uart.status_register = data & 0x00ff;
}
+ else
+ {
+ verboselog(space->machine, 0, "scc68070_periphs_w: Unknown address: %04x = %04x & %04x\n", offset * 2, data, mem_mask);
+ }
break;
case 0x2014/2:
if(ACCESSING_BITS_0_7)
@@ -388,28 +582,38 @@ WRITE16_HANDLER( scc68070_periphs_w )
verboselog(space->machine, 2, "scc68070_periphs_w: UART Clock Select: %04x & %04x\n", data, mem_mask);
scc68070->uart.clock_select = data & 0x00ff;
}
+ else
+ {
+ verboselog(space->machine, 0, "scc68070_periphs_w: Unknown address: %04x = %04x & %04x\n", offset * 2, data, mem_mask);
+ }
break;
case 0x2016/2:
if(ACCESSING_BITS_0_7)
{
verboselog(space->machine, 2, "scc68070_periphs_w: UART Command Register: %04x & %04x\n", data, mem_mask);
scc68070->uart.command_register = data & 0x00ff;
+ if(((scc68070->uart.command_register >> 2) & 3) == 1 &&
+ scc68070->uart.transmit_pointer == -1)
+ {
+ scc68070_tx_empty(space->machine, scc68070);
+ }
}
+ else
+ {
+ verboselog(space->machine, 0, "scc68070_periphs_w: Unknown address: %04x = %04x & %04x\n", offset * 2, data, mem_mask);
+ }
break;
case 0x2018/2:
if(ACCESSING_BITS_0_7)
{
verboselog(space->machine, 2, "scc68070_periphs_w: UART Transmit Holding Register: %04x & %04x: %c\n", data, mem_mask, (data >= 0x20 && data < 0x7f) ? (data & 0x00ff) : ' ');
- if((data >= 0x20 && data < 0x7f) || data == 0x08)
- {
- printf( "%c", data & 0x00ff );
- }
- if(data == 0x0d)
- {
- printf( "\n" );
- }
+ scc68070_uart_tx(space->machine, scc68070, data & 0x00ff);
scc68070->uart.transmit_holding_register = data & 0x00ff;
}
+ else
+ {
+ verboselog(space->machine, 0, "scc68070_periphs_w: Unknown address: %04x = %04x & %04x\n", offset * 2, data, mem_mask);
+ }
break;
case 0x201a/2:
if(ACCESSING_BITS_0_7)
@@ -417,6 +621,10 @@ WRITE16_HANDLER( scc68070_periphs_w )
verboselog(space->machine, 2, "scc68070_periphs_w: UART Receive Holding Register: %04x & %04x\n", data, mem_mask);
scc68070->uart.receive_holding_register = data & 0x00ff;
}
+ else
+ {
+ verboselog(space->machine, 0, "scc68070_periphs_w: Unknown address: %04x = %04x & %04x\n", offset * 2, data, mem_mask);
+ }
break;
// Timers: 80002020 to 80002029
@@ -449,12 +657,10 @@ WRITE16_HANDLER( scc68070_periphs_w )
case 0x2026/2:
verboselog(space->machine, 2, "scc68070_periphs_w: Timer 1: %04x & %04x\n", data, mem_mask);
COMBINE_DATA(&scc68070->timers.timer1);
- printf( "Timer 1 write: %04x\n", data );
break;
case 0x2028/2:
verboselog(space->machine, 2, "scc68070_periphs_w: Timer 2: %04x & %04x\n", data, mem_mask);
COMBINE_DATA(&scc68070->timers.timer2);
- printf( "Timer 2 write: %04x\n", data );
break;
// PICR1: 80002045
@@ -632,6 +838,8 @@ void scc68070_init(running_machine *machine, scc68070_regs_t *scc68070)
scc68070->uart.command_register = 0;
scc68070->uart.transmit_holding_register = 0;
scc68070->uart.receive_holding_register = 0;
+ scc68070->uart.receive_pointer = -1;
+ scc68070->uart.transmit_pointer = -1;
scc68070->timers.timer_status_register = 0;
scc68070->timers.timer_control_register = 0;
@@ -744,6 +952,15 @@ void scc68070_register_globals(running_machine *machine, scc68070_regs_t *scc680
state_save_register_global(machine, scc68070->mmu.desc[7].length);
state_save_register_global(machine, scc68070->mmu.desc[7].segment);
state_save_register_global(machine, scc68070->mmu.desc[7].base);
+
+ scc68070->timers.timer0_timer = timer_alloc(machine, scc68070_timer0_callback, 0);
+ timer_adjust_oneshot(scc68070->timers.timer0_timer, attotime_never, 0);
+
+ scc68070->uart.rx_timer = timer_alloc(machine, scc68070_rx_callback, 0);
+ timer_adjust_oneshot(scc68070->uart.rx_timer, attotime_never, 0);
+
+ scc68070->uart.tx_timer = timer_alloc(machine, scc68070_tx_callback, 0);
+ timer_adjust_oneshot(scc68070->uart.tx_timer, attotime_never, 0);
}
#if ENABLE_UART_PRINTING
diff --git a/src/mame/machine/cdi070.h b/src/mame/machine/cdi070.h
index 1e43e266110..ef5cdb6d03d 100644
--- a/src/mame/machine/cdi070.h
+++ b/src/mame/machine/cdi070.h
@@ -61,6 +61,14 @@ typedef struct
UINT8 transmit_holding_register;
UINT8 reserved5;
UINT8 receive_holding_register;
+
+ INT16 receive_pointer;
+ UINT8 receive_buffer[32768];
+ emu_timer* rx_timer;
+
+ INT16 transmit_pointer;
+ UINT8 transmit_buffer[32768];
+ emu_timer* tx_timer;
} scc68070_uart_regs_t;
#define UMR_OM 0xc0
@@ -224,9 +232,15 @@ typedef struct
// Member functions
extern TIMER_CALLBACK( scc68070_timer0_callback );
+extern TIMER_CALLBACK( scc68070_rx_callback );
+extern TIMER_CALLBACK( scc68070_tx_callback );
extern READ16_HANDLER( scc68070_periphs_r );
extern WRITE16_HANDLER( scc68070_periphs_w );
+extern READ16_HANDLER( uart_loopback_enable );
+
extern void scc68070_init(running_machine *machine, scc68070_regs_t *scc68070);
+extern void scc68070_uart_rx(running_machine *machine, scc68070_regs_t *scc68070, UINT8 data);
+extern void scc68070_uart_tx(running_machine *machine, scc68070_regs_t *scc68070, UINT8 data);
extern void scc68070_register_globals(running_machine *machine, scc68070_regs_t *scc68070);
#endif // _MACHINE_CDI070_H_
diff --git a/src/mame/machine/cdislave.c b/src/mame/machine/cdislave.c
index e6d4adee5dd..e5db207c037 100644
--- a/src/mame/machine/cdislave.c
+++ b/src/mame/machine/cdislave.c
@@ -173,6 +173,7 @@ UINT16 cdislave_device::register_read(const UINT32 offset, const UINT16 mem_mask
case 0xb1:
case 0xf0:
case 0xf3:
+ case 0xf4:
case 0xf7:
verboselog(&m_machine, 0, "slave_r: De-asserting IRQ2\n" );
cputag_set_input_line(&m_machine, "maincpu", M68K_IRQ_2, CLEAR_LINE);
@@ -337,14 +338,14 @@ void cdislave_device::register_write(const UINT32 offset, const UINT16 data, con
m_in_index++;
switch(data & 0x00ff)
{
- case 0x82: // Mute audio
+ case 0x82: // Mute Audio
verboselog(&m_machine, 0, "slave_w: Channel %d: Mute Audio (0x82)\n", offset );
dmadac_enable(&state->dmadac[0], 2, 0);
m_in_index = 0;
m_in_count = 0;
//timer_adjust_oneshot(cdic->audio_sample_timer, attotime_never, 0);
break;
- case 0x83: // Unmute audio
+ case 0x83: // Unmute Audio
verboselog(&m_machine, 0, "slave_w: Channel %d: Unmute Audio (0x83)\n", offset );
dmadac_enable(&state->dmadac[0], 2, 1);
m_in_index = 0;
@@ -403,31 +404,36 @@ void cdislave_device::register_write(const UINT32 offset, const UINT16 data, con
verboselog(&m_machine, 0, "slave_w: Channel %d: Request Disc Status (0xb0)\n", offset );
m_in_count = 4;
break;
- case 0xb1: // Request Disc Status
+ case 0xb1: // Request Disc Base
verboselog(&m_machine, 0, "slave_w: Channel %d: Request Disc Base (0xb1)\n", offset );
m_in_count = 4;
break;
- case 0xf0: // Get SLAVE revision
- verboselog(&m_machine, 0, "slave_w: Channel %d: Get SLAVE Revision (0xf0)\n", offset );
+ case 0xf0: // Request SLAVE Revision
+ verboselog(&m_machine, 0, "slave_w: Channel %d: Request SLAVE Revision (0xf0)\n", offset );
prepare_readback(ATTOTIME_IN_HZ(10000), 2, 2, 0xf0, 0x32, 0x31, 0, 0xf0);
m_in_index = 0;
break;
- case 0xf3: // Query Pointer Type
- verboselog(&m_machine, 0, "slave_w: Channel %d: Query Pointer Type (0xf3)\n", offset );
+ case 0xf3: // Request Pointer Type
+ verboselog(&m_machine, 0, "slave_w: Channel %d: Request Pointer Type (0xf3)\n", offset );
m_in_index = 0;
prepare_readback(ATTOTIME_IN_HZ(10000), 2, 2, 0xf3, 1, 0, 0, 0xf3);
break;
- case 0xf6: // NTSC/PAL
- verboselog(&m_machine, 0, "slave_w: Channel %d: Check NTSC/PAL (0xf6)\n", offset );
- prepare_readback(attotime_never, 2, 2, 0xf6, 1, 0, 0, 0xf6);
+ case 0xf4: // Request Test Plug Status
+ verboselog(&m_machine, 0, "slave_w: Channel %d: Request Test Plug Status (0xf4)\n", offset );
m_in_index = 0;
+ prepare_readback(ATTOTIME_IN_HZ(10000), 2, 2, 0xf4, 0, 0, 0, 0xf4);
break;
- case 0xf7: // Activate input polling
+ case 0xf6: // Request NTSC/PAL Status
+ verboselog(&m_machine, 0, "slave_w: Channel %d: Request NTSC/PAL Status (0xf6)\n", offset );
+ prepare_readback(attotime_never, 2, 2, 0xf6, 2, 0, 0, 0xf6);
+ m_in_index = 0;
+ break;
+ case 0xf7: // Enable Input Polling
verboselog(&m_machine, 0, "slave_w: Channel %d: Activate Input Polling (0xf7)\n", offset );
m_polling_active = 1;
m_in_index = 0;
break;
- case 0xfa: // Enable X-Bus interrupts
+ case 0xfa: // Enable X-Bus Interrupts
verboselog(&m_machine, 0, "slave_w: Channel %d: X-Bus Interrupt Enable (0xfa)\n", offset );
m_xbus_interrupt_enable = 1;
m_in_index = 0;