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author R. Belmont <rb6502@users.noreply.github.com>2009-09-27 23:39:39 +0000
committer R. Belmont <rb6502@users.noreply.github.com>2009-09-27 23:39:39 +0000
commit42951f5c7a879cc2e722a290a5a4b5ec260f129b (patch)
tree0f223708c264c5d65efb1f0b166c3b636c5f76b8
parent5fc5a8b20329480dd74ca3f2663e661693037373 (diff)
M680x0 update
- Add CPU types 68EC030, 68030, and 68EC040 - Start of 030/040 PMMU, including stubbed PMOVE
-rw-r--r--src/emu/cpu/m68000/m68000.h10
-rw-r--r--src/emu/cpu/m68000/m68k_in.c1072
-rw-r--r--src/emu/cpu/m68000/m68kcpu.c265
-rw-r--r--src/emu/cpu/m68000/m68kcpu.h37
-rw-r--r--src/emu/cpu/m68000/m68kmake.c48
5 files changed, 859 insertions, 573 deletions
diff --git a/src/emu/cpu/m68000/m68000.h b/src/emu/cpu/m68000/m68000.h
index a697a6b3e59..a28cef1e56f 100644
--- a/src/emu/cpu/m68000/m68000.h
+++ b/src/emu/cpu/m68000/m68000.h
@@ -26,7 +26,9 @@ enum
M68K_CPU_TYPE_68010,
M68K_CPU_TYPE_68EC020,
M68K_CPU_TYPE_68020,
- M68K_CPU_TYPE_68030, /* Supported by disassembler ONLY */
+ M68K_CPU_TYPE_68EC030,
+ M68K_CPU_TYPE_68030,
+ M68K_CPU_TYPE_68EC040,
M68K_CPU_TYPE_68040,
M68K_CPU_TYPE_SCC68070
};
@@ -74,6 +76,9 @@ CPU_GET_INFO( m68008 );
CPU_GET_INFO( m68010 );
CPU_GET_INFO( m68ec020 );
CPU_GET_INFO( m68020 );
+CPU_GET_INFO( m68ec030 );
+CPU_GET_INFO( m68030 );
+CPU_GET_INFO( m68ec040 );
CPU_GET_INFO( m68040 );
CPU_GET_INFO( scc68070 );
@@ -83,6 +88,9 @@ CPU_GET_INFO( scc68070 );
#define CPU_M68010 CPU_GET_INFO_NAME( m68010 )
#define CPU_M68EC020 CPU_GET_INFO_NAME( m68ec020 )
#define CPU_M68020 CPU_GET_INFO_NAME( m68020 )
+#define CPU_M68EC030 CPU_GET_INFO_NAME( m68ec030 )
+#define CPU_M68030 CPU_GET_INFO_NAME( m68030 )
+#define CPU_M68EC040 CPU_GET_INFO_NAME( m68ec040 )
#define CPU_M68040 CPU_GET_INFO_NAME( m68040 )
#define CPU_SCC68070 CPU_GET_INFO_NAME( scc68070 )
diff --git a/src/emu/cpu/m68000/m68k_in.c b/src/emu/cpu/m68000/m68k_in.c
index d377bf76ae7..b5c0b28b588 100644
--- a/src/emu/cpu/m68000/m68k_in.c
+++ b/src/emu/cpu/m68000/m68k_in.c
@@ -125,7 +125,7 @@ M68KMAKE_TABLE_HEADER
#include "m68kops.h"
-#define NUM_CPU_TYPES 4
+#define NUM_CPU_TYPES 5
void (*m68ki_instruction_jump_table[0x10000])(m68ki_cpu_core *m68k); /* opcode handler jump table */
unsigned char m68ki_cycles[NUM_CPU_TYPES][0x10000]; /* Cycles used by CPU type */
@@ -150,7 +150,7 @@ static const opcode_handler_struct m68k_opcode_handler_table[] =
XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX
M68KMAKE_TABLE_FOOTER
- {0, 0, 0, {0, 0, 0, 0}}
+ {0, 0, 0, {0, 0, 0, 0, 0}}
};
@@ -351,527 +351,528 @@ cpu cycles: Base number of cycles required to execute this opcode on the
- spec spec allowed ea mode cpu cycles
-name size proc ea bit pattern A+-DXWLdxI 0 1 2 4 000 010 020 040 comments
-====== ==== ==== ==== ================ ========== = = = = === === === === =============
+ spec spec allowed ea mode cpu cycles
+name size proc ea bit pattern A+-DXWLdxI 0 1 2 3 4 000 010 020 030 040 comments
+====== ==== ==== ==== ================ ========== = = = = = === === === === === =============
M68KMAKE_TABLE_START
-1010 0 . . 1010............ .......... U U U U 4 4 4 4
-1111 0 . . 1111............ .......... U U U U 4 4 4 4
-040fpu0 32 . . 11110010........ .......... . . . U . . . 0
-040fpu1 32 . . 11110011........ .......... . . . U . . . 0
-abcd 8 rr . 1100...100000... .......... U U U U 6 6 4 4
-abcd 8 mm ax7 1100111100001... .......... U U U U 18 18 16 16
-abcd 8 mm ay7 1100...100001111 .......... U U U U 18 18 16 16
-abcd 8 mm axy7 1100111100001111 .......... U U U U 18 18 16 16
-abcd 8 mm . 1100...100001... .......... U U U U 18 18 16 16
-add 8 er d 1101...000000... .......... U U U U 4 4 2 2
-add 8 er . 1101...000...... A+-DXWLdxI U U U U 4 4 2 2
-add 16 er d 1101...001000... .......... U U U U 4 4 2 2
-add 16 er a 1101...001001... .......... U U U U 4 4 2 2
-add 16 er . 1101...001...... A+-DXWLdxI U U U U 4 4 2 2
-add 32 er d 1101...010000... .......... U U U U 6 6 2 2
-add 32 er a 1101...010001... .......... U U U U 6 6 2 2
-add 32 er . 1101...010...... A+-DXWLdxI U U U U 6 6 2 2
-add 8 re . 1101...100...... A+-DXWL... U U U U 8 8 4 4
-add 16 re . 1101...101...... A+-DXWL... U U U U 8 8 4 4
-add 32 re . 1101...110...... A+-DXWL... U U U U 12 12 4 4
-adda 16 . d 1101...011000... .......... U U U U 8 8 2 2
-adda 16 . a 1101...011001... .......... U U U U 8 8 2 2
-adda 16 . . 1101...011...... A+-DXWLdxI U U U U 8 8 2 2
-adda 32 . d 1101...111000... .......... U U U U 6 6 2 2
-adda 32 . a 1101...111001... .......... U U U U 6 6 2 2
-adda 32 . . 1101...111...... A+-DXWLdxI U U U U 6 6 2 2
-addi 8 . d 0000011000000... .......... U U U U 8 8 2 2
-addi 8 . . 0000011000...... A+-DXWL... U U U U 12 12 4 4
-addi 16 . d 0000011001000... .......... U U U U 8 8 2 2
-addi 16 . . 0000011001...... A+-DXWL... U U U U 12 12 4 4
-addi 32 . d 0000011010000... .......... U U U U 16 14 2 2
-addi 32 . . 0000011010...... A+-DXWL... U U U U 20 20 4 4
-addq 8 . d 0101...000000... .......... U U U U 4 4 2 2
-addq 8 . . 0101...000...... A+-DXWL... U U U U 8 8 4 4
-addq 16 . d 0101...001000... .......... U U U U 4 4 2 2
-addq 16 . a 0101...001001... .......... U U U U 4 4 2 2
-addq 16 . . 0101...001...... A+-DXWL... U U U U 8 8 4 4
-addq 32 . d 0101...010000... .......... U U U U 8 8 2 2
-addq 32 . a 0101...010001... .......... U U U U 8 8 2 2
-addq 32 . . 0101...010...... A+-DXWL... U U U U 12 12 4 4
-addx 8 rr . 1101...100000... .......... U U U U 4 4 2 2
-addx 16 rr . 1101...101000... .......... U U U U 4 4 2 2
-addx 32 rr . 1101...110000... .......... U U U U 8 6 2 2
-addx 8 mm ax7 1101111100001... .......... U U U U 18 18 12 12
-addx 8 mm ay7 1101...100001111 .......... U U U U 18 18 12 12
-addx 8 mm axy7 1101111100001111 .......... U U U U 18 18 12 12
-addx 8 mm . 1101...100001... .......... U U U U 18 18 12 12
-addx 16 mm . 1101...101001... .......... U U U U 18 18 12 12
-addx 32 mm . 1101...110001... .......... U U U U 30 30 12 12
-and 8 er d 1100...000000... .......... U U U U 4 4 2 2
-and 8 er . 1100...000...... A+-DXWLdxI U U U U 4 4 2 2
-and 16 er d 1100...001000... .......... U U U U 4 4 2 2
-and 16 er . 1100...001...... A+-DXWLdxI U U U U 4 4 2 2
-and 32 er d 1100...010000... .......... U U U U 6 6 2 2
-and 32 er . 1100...010...... A+-DXWLdxI U U U U 6 6 2 2
-and 8 re . 1100...100...... A+-DXWL... U U U U 8 8 4 4
-and 16 re . 1100...101...... A+-DXWL... U U U U 8 8 4 4
-and 32 re . 1100...110...... A+-DXWL... U U U U 12 12 4 4
-andi 16 toc . 0000001000111100 .......... U U U U 20 16 12 12
-andi 16 tos . 0000001001111100 .......... S S S S 20 16 12 12
-andi 8 . d 0000001000000... .......... U U U U 8 8 2 2
-andi 8 . . 0000001000...... A+-DXWL... U U U U 12 12 4 4
-andi 16 . d 0000001001000... .......... U U U U 8 8 2 2
-andi 16 . . 0000001001...... A+-DXWL... U U U U 12 12 4 4
-andi 32 . d 0000001010000... .......... U U U U 14 14 2 2
-andi 32 . . 0000001010...... A+-DXWL... U U U U 20 20 4 4
-asr 8 s . 1110...000000... .......... U U U U 6 6 6 6
-asr 16 s . 1110...001000... .......... U U U U 6 6 6 6
-asr 32 s . 1110...010000... .......... U U U U 8 8 6 6
-asr 8 r . 1110...000100... .......... U U U U 6 6 6 6
-asr 16 r . 1110...001100... .......... U U U U 6 6 6 6
-asr 32 r . 1110...010100... .......... U U U U 8 8 6 6
-asr 16 . . 1110000011...... A+-DXWL... U U U U 8 8 5 5
-asl 8 s . 1110...100000... .......... U U U U 6 6 8 8
-asl 16 s . 1110...101000... .......... U U U U 6 6 8 8
-asl 32 s . 1110...110000... .......... U U U U 8 8 8 8
-asl 8 r . 1110...100100... .......... U U U U 6 6 8 8
-asl 16 r . 1110...101100... .......... U U U U 6 6 8 8
-asl 32 r . 1110...110100... .......... U U U U 8 8 8 8
-asl 16 . . 1110000111...... A+-DXWL... U U U U 8 8 6 6
-bcc 8 . . 0110............ .......... U U U U 10 10 6 6
-bcc 16 . . 0110....00000000 .......... U U U U 10 10 6 6
-bcc 32 . . 0110....11111111 .......... U U U U 10 10 6 6
-bchg 8 r . 0000...101...... A+-DXWL... U U U U 8 8 4 4
-bchg 32 r d 0000...101000... .......... U U U U 8 8 4 4
-bchg 8 s . 0000100001...... A+-DXWL... U U U U 12 12 4 4
-bchg 32 s d 0000100001000... .......... U U U U 12 12 4 4
-bclr 8 r . 0000...110...... A+-DXWL... U U U U 8 10 4 4
-bclr 32 r d 0000...110000... .......... U U U U 10 10 4 4
-bclr 8 s . 0000100010...... A+-DXWL... U U U U 12 12 4 4
-bclr 32 s d 0000100010000... .......... U U U U 14 14 4 4
-bfchg 32 . d 1110101011000... .......... . . U U . . 12 12 timing not quite correct
-bfchg 32 . . 1110101011...... A..DXWL... . . U U . . 20 20
-bfclr 32 . d 1110110011000... .......... . . U U . . 12 12
-bfclr 32 . . 1110110011...... A..DXWL... . . U U . . 20 20
-bfexts 32 . d 1110101111000... .......... . . U U . . 8 8
-bfexts 32 . . 1110101111...... A..DXWLdx. . . U U . . 15 15
-bfextu 32 . d 1110100111000... .......... . . U U . . 8 8
-bfextu 32 . . 1110100111...... A..DXWLdx. . . U U . . 15 15
-bfffo 32 . d 1110110111000... .......... . . U U . . 18 18
-bfffo 32 . . 1110110111...... A..DXWLdx. . . U U . . 28 28
-bfins 32 . d 1110111111000... .......... . . U U . . 10 10
-bfins 32 . . 1110111111...... A..DXWL... . . U U . . 17 17
-bfset 32 . d 1110111011000... .......... . . U U . . 12 12
-bfset 32 . . 1110111011...... A..DXWL... . . U U . . 20 20
-bftst 32 . d 1110100011000... .......... . . U U . . 6 6
-bftst 32 . . 1110100011...... A..DXWLdx. . . U U . . 13 13
-bkpt 0 . . 0100100001001... .......... . U U U . 10 10 10
-bra 8 . . 01100000........ .......... U U U U 10 10 10 10
-bra 16 . . 0110000000000000 .......... U U U U 10 10 10 10
-bra 32 . . 0110000011111111 .......... U U U U 10 10 10 10
-bset 32 r d 0000...111000... .......... U U U U 8 8 4 4
-bset 8 r . 0000...111...... A+-DXWL... U U U U 8 8 4 4
-bset 8 s . 0000100011...... A+-DXWL... U U U U 12 12 4 4
-bset 32 s d 0000100011000... .......... U U U U 12 12 4 4
-bsr 8 . . 01100001........ .......... U U U U 18 18 7 7
-bsr 16 . . 0110000100000000 .......... U U U U 18 18 7 7
-bsr 32 . . 0110000111111111 .......... U U U U 18 18 7 7
-btst 8 r . 0000...100...... A+-DXWLdxI U U U U 4 4 4 4
-btst 32 r d 0000...100000... .......... U U U U 6 6 4 4
-btst 8 s . 0000100000...... A+-DXWLdx. U U U U 8 8 4 4
-btst 32 s d 0000100000000... .......... U U U U 10 10 4 4
-callm 32 . . 0000011011...... A..DXWLdx. . . U U . . 60 60 not properly emulated
-cas 8 . . 0000101011...... A+-DXWL... . . U U . . 12 12
-cas 16 . . 0000110011...... A+-DXWL... . . U U . . 12 12
-cas 32 . . 0000111011...... A+-DXWL... . . U U . . 12 12
-cas2 16 . . 0000110011111100 .......... . . U U . . 12 12
-cas2 32 . . 0000111011111100 .......... . . U U . . 12 12
-chk 16 . d 0100...110000... .......... U U U U 10 8 8 8
-chk 16 . . 0100...110...... A+-DXWLdxI U U U U 10 8 8 8
-chk 32 . d 0100...100000... .......... . . U U . . 8 8
-chk 32 . . 0100...100...... A+-DXWLdxI . . U U . . 8 8
-chk2cmp2 8 . pcdi 0000000011111010 .......... . . U U . . 23 23
-chk2cmp2 8 . pcix 0000000011111011 .......... . . U U . . 23 23
-chk2cmp2 8 . . 0000000011...... A..DXWL... . . U U . . 18 18
-chk2cmp2 16 . pcdi 0000001011111010 .......... . . U U . . 23 23
-chk2cmp2 16 . pcix 0000001011111011 .......... . . U U . . 23 23
-chk2cmp2 16 . . 0000001011...... A..DXWL... . . U U . . 18 18
-chk2cmp2 32 . pcdi 0000010011111010 .......... . . U U . . 23 23
-chk2cmp2 32 . pcix 0000010011111011 .......... . . U U . . 23 23
-chk2cmp2 32 . . 0000010011...... A..DXWL... . . U U . . 18 18
-clr 8 . d 0100001000000... .......... U U U U 4 4 2 2
-clr 8 . . 0100001000...... A+-DXWL... U U U U 8 4 4 4
-clr 16 . d 0100001001000... .......... U U U U 4 4 2 2
-clr 16 . . 0100001001...... A+-DXWL... U U U U 8 4 4 4
-clr 32 . d 0100001010000... .......... U U U U 6 6 2 2
-clr 32 . . 0100001010...... A+-DXWL... U U U U 12 6 4 4
-cmp 8 . d 1011...000000... .......... U U U U 4 4 2 2
-cmp 8 . . 1011...000...... A+-DXWLdxI U U U U 4 4 2 2
-cmp 16 . d 1011...001000... .......... U U U U 4 4 2 2
-cmp 16 . a 1011...001001... .......... U U U U 4 4 2 2
-cmp 16 . . 1011...001...... A+-DXWLdxI U U U U 4 4 2 2
-cmp 32 . d 1011...010000... .......... U U U U 6 6 2 2
-cmp 32 . a 1011...010001... .......... U U U U 6 6 2 2
-cmp 32 . . 1011...010...... A+-DXWLdxI U U U U 6 6 2 2
-cmpa 16 . d 1011...011000... .......... U U U U 6 6 4 4
-cmpa 16 . a 1011...011001... .......... U U U U 6 6 4 4
-cmpa 16 . . 1011...011...... A+-DXWLdxI U U U U 6 6 4 4
-cmpa 32 . d 1011...111000... .......... U U U U 6 6 4 4
-cmpa 32 . a 1011...111001... .......... U U U U 6 6 4 4
-cmpa 32 . . 1011...111...... A+-DXWLdxI U U U U 6 6 4 4
-cmpi 8 . d 0000110000000... .......... U U U U 8 8 2 2
-cmpi 8 . . 0000110000...... A+-DXWL... U U U U 8 8 2 2
-cmpi 8 . pcdi 0000110000111010 .......... . . U U . . 7 7
-cmpi 8 . pcix 0000110000111011 .......... . . U U . . 9 9
-cmpi 16 . d 0000110001000... .......... U U U U 8 8 2 2
-cmpi 16 . . 0000110001...... A+-DXWL... U U U U 8 8 2 2
-cmpi 16 . pcdi 0000110001111010 .......... . . U U . . 7 7
-cmpi 16 . pcix 0000110001111011 .......... . . U U . . 9 9
-cmpi 32 . d 0000110010000... .......... U U U U 14 12 2 2
-cmpi 32 . . 0000110010...... A+-DXWL... U U U U 12 12 2 2
-cmpi 32 . pcdi 0000110010111010 .......... . . U U . . 7 7
-cmpi 32 . pcix 0000110010111011 .......... . . U U . . 9 9
-cmpm 8 . ax7 1011111100001... .......... U U U U 12 12 9 9
-cmpm 8 . ay7 1011...100001111 .......... U U U U 12 12 9 9
-cmpm 8 . axy7 1011111100001111 .......... U U U U 12 12 9 9
-cmpm 8 . . 1011...100001... .......... U U U U 12 12 9 9
-cmpm 16 . . 1011...101001... .......... U U U U 12 12 9 9
-cmpm 32 . . 1011...110001... .......... U U U U 20 20 9 9
-cpbcc 32 . . 1111...01....... .......... . . U . . . 4 . unemulated
-cpdbcc 32 . . 1111...001001... .......... . . U . . . 4 . unemulated
-cpgen 32 . . 1111...000...... .......... . . U . . . 4 . unemulated
-cpscc 32 . . 1111...001...... .......... . . U . . . 4 . unemulated
-cptrapcc 32 . . 1111...001111... .......... . . U . . . 4 . unemulated
-dbt 16 . . 0101000011001... .......... U U U U 12 12 6 6
-dbf 16 . . 0101000111001... .......... U U U U 12 12 6 6
-dbcc 16 . . 0101....11001... .......... U U U U 12 12 6 6
-divs 16 . d 1000...111000... .......... U U U U 158 122 56 56
-divs 16 . . 1000...111...... A+-DXWLdxI U U U U 158 122 56 56
-divu 16 . d 1000...011000... .......... U U U U 140 108 44 44
-divu 16 . . 1000...011...... A+-DXWLdxI U U U U 140 108 44 44
-divl 32 . d 0100110001000... .......... . . U U . . 84 84
-divl 32 . . 0100110001...... A+-DXWLdxI . . U U . . 84 84
-eor 8 . d 1011...100000... .......... U U U U 4 4 2 2
-eor 8 . . 1011...100...... A+-DXWL... U U U U 8 8 4 4
-eor 16 . d 1011...101000... .......... U U U U 4 4 2 2
-eor 16 . . 1011...101...... A+-DXWL... U U U U 8 8 4 4
-eor 32 . d 1011...110000... .......... U U U U 8 6 2 2
-eor 32 . . 1011...110...... A+-DXWL... U U U U 12 12 4 4
-eori 16 toc . 0000101000111100 .......... U U U U 20 16 12 12
-eori 16 tos . 0000101001111100 .......... S S S S 20 16 12 12
-eori 8 . d 0000101000000... .......... U U U U 8 8 2 2
-eori 8 . . 0000101000...... A+-DXWL... U U U U 12 12 4 4
-eori 16 . d 0000101001000... .......... U U U U 8 8 2 2
-eori 16 . . 0000101001...... A+-DXWL... U U U U 12 12 4 4
-eori 32 . d 0000101010000... .......... U U U U 16 14 2 2
-eori 32 . . 0000101010...... A+-DXWL... U U U U 20 20 4 4
-exg 32 dd . 1100...101000... .......... U U U U 6 6 2 2
-exg 32 aa . 1100...101001... .......... U U U U 6 6 2 2
-exg 32 da . 1100...110001... .......... U U U U 6 6 2 2
-ext 16 . . 0100100010000... .......... U U U U 4 4 4 4
-ext 32 . . 0100100011000... .......... U U U U 4 4 4 4
-extb 32 . . 0100100111000... .......... . . U U . . 4 4
-illegal 0 . . 0100101011111100 .......... U U U U 4 4 4 4
-jmp 32 . . 0100111011...... A..DXWLdx. U U U U 4 4 0 0
-jsr 32 . . 0100111010...... A..DXWLdx. U U U U 12 12 0 0
-lea 32 . . 0100...111...... A..DXWLdx. U U U U 0 0 2 2
-link 16 . a7 0100111001010111 .......... U U U U 16 16 5 5
-link 16 . . 0100111001010... .......... U U U U 16 16 5 5
-link 32 . a7 0100100000001111 .......... . . U U . . 6 6
-link 32 . . 0100100000001... .......... . . U U . . 6 6
-lsr 8 s . 1110...000001... .......... U U U U 6 6 4 4
-lsr 16 s . 1110...001001... .......... U U U U 6 6 4 4
-lsr 32 s . 1110...010001... .......... U U U U 8 8 4 4
-lsr 8 r . 1110...000101... .......... U U U U 6 6 6 6
-lsr 16 r . 1110...001101... .......... U U U U 6 6 6 6
-lsr 32 r . 1110...010101... .......... U U U U 8 8 6 6
-lsr 16 . . 1110001011...... A+-DXWL... U U U U 8 8 5 5
-lsl 8 s . 1110...100001... .......... U U U U 6 6 4 4
-lsl 16 s . 1110...101001... .......... U U U U 6 6 4 4
-lsl 32 s . 1110...110001... .......... U U U U 8 8 4 4
-lsl 8 r . 1110...100101... .......... U U U U 6 6 6 6
-lsl 16 r . 1110...101101... .......... U U U U 6 6 6 6
-lsl 32 r . 1110...110101... .......... U U U U 8 8 6 6
-lsl 16 . . 1110001111...... A+-DXWL... U U U U 8 8 5 5
-move 8 d d 0001...000000... .......... U U U U 4 4 2 2
-move 8 d . 0001...000...... A+-DXWLdxI U U U U 4 4 2 2
-move 8 ai d 0001...010000... .......... U U U U 8 8 4 4
-move 8 ai . 0001...010...... A+-DXWLdxI U U U U 8 8 4 4
-move 8 pi d 0001...011000... .......... U U U U 8 8 4 4
-move 8 pi . 0001...011...... A+-DXWLdxI U U U U 8 8 4 4
-move 8 pi7 d 0001111011000... .......... U U U U 8 8 4 4
-move 8 pi7 . 0001111011...... A+-DXWLdxI U U U U 8 8 4 4
-move 8 pd d 0001...100000... .......... U U U U 8 8 5 5
-move 8 pd . 0001...100...... A+-DXWLdxI U U U U 8 8 5 5
-move 8 pd7 d 0001111100000... .......... U U U U 8 8 5 5
-move 8 pd7 . 0001111100...... A+-DXWLdxI U U U U 8 8 5 5
-move 8 di d 0001...101000... .......... U U U U 12 12 5 5
-move 8 di . 0001...101...... A+-DXWLdxI U U U U 12 12 5 5
-move 8 ix d 0001...110000... .......... U U U U 14 14 7 7
-move 8 ix . 0001...110...... A+-DXWLdxI U U U U 14 14 7 7
-move 8 aw d 0001000111000... .......... U U U U 12 12 4 4
-move 8 aw . 0001000111...... A+-DXWLdxI U U U U 12 12 4 4
-move 8 al d 0001001111000... .......... U U U U 16 16 6 6
-move 8 al . 0001001111...... A+-DXWLdxI U U U U 16 16 6 6
-move 16 d d 0011...000000... .......... U U U U 4 4 2 2
-move 16 d a 0011...000001... .......... U U U U 4 4 2 2
-move 16 d . 0011...000...... A+-DXWLdxI U U U U 4 4 2 2
-move 16 ai d 0011...010000... .......... U U U U 8 8 4 4
-move 16 ai a 0011...010001... .......... U U U U 8 8 4 4
-move 16 ai . 0011...010...... A+-DXWLdxI U U U U 8 8 4 4
-move 16 pi d 0011...011000... .......... U U U U 8 8 4 4
-move 16 pi a 0011...011001... .......... U U U U 8 8 4 4
-move 16 pi . 0011...011...... A+-DXWLdxI U U U U 8 8 4 4
-move 16 pd d 0011...100000... .......... U U U U 8 8 5 5
-move 16 pd a 0011...100001... .......... U U U U 8 8 5 5
-move 16 pd . 0011...100...... A+-DXWLdxI U U U U 8 8 5 5
-move 16 di d 0011...101000... .......... U U U U 12 12 5 5
-move 16 di a 0011...101001... .......... U U U U 12 12 5 5
-move 16 di . 0011...101...... A+-DXWLdxI U U U U 12 12 5 5
-move 16 ix d 0011...110000... .......... U U U U 14 14 7 7
-move 16 ix a 0011...110001... .......... U U U U 14 14 7 7
-move 16 ix . 0011...110...... A+-DXWLdxI U U U U 14 14 7 7
-move 16 aw d 0011000111000... .......... U U U U 12 12 4 4
-move 16 aw a 0011000111001... .......... U U U U 12 12 4 4
-move 16 aw . 0011000111...... A+-DXWLdxI U U U U 12 12 4 4
-move 16 al d 0011001111000... .......... U U U U 16 16 6 6
-move 16 al a 0011001111001... .......... U U U U 16 16 6 6
-move 16 al . 0011001111...... A+-DXWLdxI U U U U 16 16 6 6
-move 32 d d 0010...000000... .......... U U U U 4 4 2 2
-move 32 d a 0010...000001... .......... U U U U 4 4 2 2
-move 32 d . 0010...000...... A+-DXWLdxI U U U U 4 4 2 2
-move 32 ai d 0010...010000... .......... U U U U 12 12 4 4
-move 32 ai a 0010...010001... .......... U U U U 12 12 4 4
-move 32 ai . 0010...010...... A+-DXWLdxI U U U U 12 12 4 4
-move 32 pi d 0010...011000... .......... U U U U 12 12 4 4
-move 32 pi a 0010...011001... .......... U U U U 12 12 4 4
-move 32 pi . 0010...011...... A+-DXWLdxI U U U U 12 12 4 4
-move 32 pd d 0010...100000... .......... U U U U 12 14 5 5
-move 32 pd a 0010...100001... .......... U U U U 12 14 5 5
-move 32 pd . 0010...100...... A+-DXWLdxI U U U U 12 14 5 5
-move 32 di d 0010...101000... .......... U U U U 16 16 5 5
-move 32 di a 0010...101001... .......... U U U U 16 16 5 5
-move 32 di . 0010...101...... A+-DXWLdxI U U U U 16 16 5 5
-move 32 ix d 0010...110000... .......... U U U U 18 18 7 7
-move 32 ix a 0010...110001... .......... U U U U 18 18 7 7
-move 32 ix . 0010...110...... A+-DXWLdxI U U U U 18 18 7 7
-move 32 aw d 0010000111000... .......... U U U U 16 16 4 4
-move 32 aw a 0010000111001... .......... U U U U 16 16 4 4
-move 32 aw . 0010000111...... A+-DXWLdxI U U U U 16 16 4 4
-move 32 al d 0010001111000... .......... U U U U 20 20 6 6
-move 32 al a 0010001111001... .......... U U U U 20 20 6 6
-move 32 al . 0010001111...... A+-DXWLdxI U U U U 20 20 6 6
-movea 16 . d 0011...001000... .......... U U U U 4 4 2 2
-movea 16 . a 0011...001001... .......... U U U U 4 4 2 2
-movea 16 . . 0011...001...... A+-DXWLdxI U U U U 4 4 2 2
-movea 32 . d 0010...001000... .......... U U U U 4 4 2 2
-movea 32 . a 0010...001001... .......... U U U U 4 4 2 2
-movea 32 . . 0010...001...... A+-DXWLdxI U U U U 4 4 2 2
-move 16 frc d 0100001011000... .......... . U U U . 4 4 4
-move 16 frc . 0100001011...... A+-DXWL... . U U U . 8 4 4
-move 16 toc d 0100010011000... .......... U U U U 12 12 4 4
-move 16 toc . 0100010011...... A+-DXWLdxI U U U U 12 12 4 4
-move 16 frs d 0100000011000... .......... U S S S 6 4 8 8 U only for 000
-move 16 frs . 0100000011...... A+-DXWL... U S S S 8 8 8 8 U only for 000
-move 16 tos d 0100011011000... .......... S S S S 12 12 8 8
-move 16 tos . 0100011011...... A+-DXWLdxI S S S S 12 12 8 8
-move 32 fru . 0100111001101... .......... S S S S 4 6 2 2
-move 32 tou . 0100111001100... .......... S S S S 4 6 2 2
-movec 32 cr . 0100111001111010 .......... . S S S . 12 6 6
-movec 32 rc . 0100111001111011 .......... . S S S . 10 12 12
-movem 16 re pd 0100100010100... .......... U U U U 8 8 4 4
-movem 16 re . 0100100010...... A..DXWL... U U U U 8 8 4 4
-movem 32 re pd 0100100011100... .......... U U U U 8 8 4 4
-movem 32 re . 0100100011...... A..DXWL... U U U U 8 8 4 4
-movem 16 er pi 0100110010011... .......... U U U U 12 12 8 8
-movem 16 er pcdi 0100110010111010 .......... U U U U 16 16 9 9
-movem 16 er pcix 0100110010111011 .......... U U U U 18 18 11 11
-movem 16 er . 0100110010...... A..DXWL... U U U U 12 12 8 8
-movem 32 er pi 0100110011011... .......... U U U U 12 12 8 8
-movem 32 er pcdi 0100110011111010 .......... U U U U 16 16 9 9
-movem 32 er pcix 0100110011111011 .......... U U U U 18 18 11 11
-movem 32 er . 0100110011...... A..DXWL... U U U U 12 12 8 8
-movep 16 er . 0000...100001... .......... U U U U 16 16 12 12
-movep 32 er . 0000...101001... .......... U U U U 24 24 18 18
-movep 16 re . 0000...110001... .......... U U U U 16 16 11 11
-movep 32 re . 0000...111001... .......... U U U U 24 24 17 17
-moveq 32 . . 0111...0........ .......... U U U U 4 4 2 2
-moves 8 . . 0000111000...... A+-DXWL... . S S S . 14 5 5
-moves 16 . . 0000111001...... A+-DXWL... . S S S . 14 5 5
-moves 32 . . 0000111010...... A+-DXWL... . S S S . 16 5 5
-move16 32 . . 1111011000100... .......... . . . U . . . 4 TODO: correct timing
-muls 16 . d 1100...111000... .......... U U U U 54 32 27 27
-muls 16 . . 1100...111...... A+-DXWLdxI U U U U 54 32 27 27
-mulu 16 . d 1100...011000... .......... U U U U 54 30 27 27
-mulu 16 . . 1100...011...... A+-DXWLdxI U U U U 54 30 27 27
-mull 32 . d 0100110000000... .......... . . U U . . 43 43
-mull 32 . . 0100110000...... A+-DXWLdxI . . U U . . 43 43
-nbcd 8 . d 0100100000000... .......... U U U U 6 6 6 6
-nbcd 8 . . 0100100000...... A+-DXWL... U U U U 8 8 6 6
-neg 8 . d 0100010000000... .......... U U U U 4 4 2 2
-neg 8 . . 0100010000...... A+-DXWL... U U U U 8 8 4 4
-neg 16 . d 0100010001000... .......... U U U U 4 4 2 2
-neg 16 . . 0100010001...... A+-DXWL... U U U U 8 8 4 4
-neg 32 . d 0100010010000... .......... U U U U 6 6 2 2
-neg 32 . . 0100010010...... A+-DXWL... U U U U 12 12 4 4
-negx 8 . d 0100000000000... .......... U U U U 4 4 2 2
-negx 8 . . 0100000000...... A+-DXWL... U U U U 8 8 4 4
-negx 16 . d 0100000001000... .......... U U U U 4 4 2 2
-negx 16 . . 0100000001...... A+-DXWL... U U U U 8 8 4 4
-negx 32 . d 0100000010000... .......... U U U U 6 6 2 2
-negx 32 . . 0100000010...... A+-DXWL... U U U U 12 12 4 4
-nop 0 . . 0100111001110001 .......... U U U U 4 4 2 2
-not 8 . d 0100011000000... .......... U U U U 4 4 2 2
-not 8 . . 0100011000...... A+-DXWL... U U U U 8 8 4 4
-not 16 . d 0100011001000... .......... U U U U 4 4 2 2
-not 16 . . 0100011001...... A+-DXWL... U U U U 8 8 4 4
-not 32 . d 0100011010000... .......... U U U U 6 6 2 2
-not 32 . . 0100011010...... A+-DXWL... U U U U 12 12 4 4
-or 8 er d 1000...000000... .......... U U U U 4 4 2 2
-or 8 er . 1000...000...... A+-DXWLdxI U U U U 4 4 2 2
-or 16 er d 1000...001000... .......... U U U U 4 4 2 2
-or 16 er . 1000...001...... A+-DXWLdxI U U U U 4 4 2 2
-or 32 er d 1000...010000... .......... U U U U 6 6 2 2
-or 32 er . 1000...010...... A+-DXWLdxI U U U U 6 6 2 2
-or 8 re . 1000...100...... A+-DXWL... U U U U 8 8 4 4
-or 16 re . 1000...101...... A+-DXWL... U U U U 8 8 4 4
-or 32 re . 1000...110...... A+-DXWL... U U U U 12 12 4 4
-ori 16 toc . 0000000000111100 .......... U U U U 20 16 12 12
-ori 16 tos . 0000000001111100 .......... S S S S 20 16 12 12
-ori 8 . d 0000000000000... .......... U U U U 8 8 2 2
-ori 8 . . 0000000000...... A+-DXWL... U U U U 12 12 4 4
-ori 16 . d 0000000001000... .......... U U U U 8 8 2 2
-ori 16 . . 0000000001...... A+-DXWL... U U U U 12 12 4 4
-ori 32 . d 0000000010000... .......... U U U U 16 14 2 2
-ori 32 . . 0000000010...... A+-DXWL... U U U U 20 20 4 4
-pack 16 rr . 1000...101000... .......... . . U U . . 6 6
-pack 16 mm ax7 1000111101001... .......... . . U U . . 13 13
-pack 16 mm ay7 1000...101001111 .......... . . U U . . 13 13
-pack 16 mm axy7 1000111101001111 .......... . . U U . . 13 13
-pack 16 mm . 1000...101001... .......... . . U U . . 13 13
-pea 32 . . 0100100001...... A..DXWLdx. U U U U 6 6 5 5
-pflush 32 . . 1111010100011000 .......... . . . S . . . 4 TODO: correct timing
-reset 0 . . 0100111001110000 .......... S S S S 0 0 0 0
-ror 8 s . 1110...000011... .......... U U U U 6 6 8 8
-ror 16 s . 1110...001011... .......... U U U U 6 6 8 8
-ror 32 s . 1110...010011... .......... U U U U 8 8 8 8
-ror 8 r . 1110...000111... .......... U U U U 6 6 8 8
-ror 16 r . 1110...001111... .......... U U U U 6 6 8 8
-ror 32 r . 1110...010111... .......... U U U U 8 8 8 8
-ror 16 . . 1110011011...... A+-DXWL... U U U U 8 8 7 7
-rol 8 s . 1110...100011... .......... U U U U 6 6 8 8
-rol 16 s . 1110...101011... .......... U U U U 6 6 8 8
-rol 32 s . 1110...110011... .......... U U U U 8 8 8 8
-rol 8 r . 1110...100111... .......... U U U U 6 6 8 8
-rol 16 r . 1110...101111... .......... U U U U 6 6 8 8
-rol 32 r . 1110...110111... .......... U U U U 8 8 8 8
-rol 16 . . 1110011111...... A+-DXWL... U U U U 8 8 7 7
-roxr 8 s . 1110...000010... .......... U U U U 6 6 12 12
-roxr 16 s . 1110...001010... .......... U U U U 6 6 12 12
-roxr 32 s . 1110...010010... .......... U U U U 8 8 12 12
-roxr 8 r . 1110...000110... .......... U U U U 6 6 12 12
-roxr 16 r . 1110...001110... .......... U U U U 6 6 12 12
-roxr 32 r . 1110...010110... .......... U U U U 8 8 12 12
-roxr 16 . . 1110010011...... A+-DXWL... U U U U 8 8 5 5
-roxl 8 s . 1110...100010... .......... U U U U 6 6 12 12
-roxl 16 s . 1110...101010... .......... U U U U 6 6 12 12
-roxl 32 s . 1110...110010... .......... U U U U 8 8 12 12
-roxl 8 r . 1110...100110... .......... U U U U 6 6 12 12
-roxl 16 r . 1110...101110... .......... U U U U 6 6 12 12
-roxl 32 r . 1110...110110... .......... U U U U 8 8 12 12
-roxl 16 . . 1110010111...... A+-DXWL... U U U U 8 8 5 5
-rtd 32 . . 0100111001110100 .......... . U U U . 16 10 10
-rte 32 . . 0100111001110011 .......... S S S S 20 24 20 20 bus fault not emulated
-rtm 32 . . 000001101100.... .......... . . U U . . 19 19 not properly emulated
-rtr 32 . . 0100111001110111 .......... U U U U 20 20 14 14
-rts 32 . . 0100111001110101 .......... U U U U 16 16 10 10
-sbcd 8 rr . 1000...100000... .......... U U U U 6 6 4 4
-sbcd 8 mm ax7 1000111100001... .......... U U U U 18 18 16 16
-sbcd 8 mm ay7 1000...100001111 .......... U U U U 18 18 16 16
-sbcd 8 mm axy7 1000111100001111 .......... U U U U 18 18 16 16
-sbcd 8 mm . 1000...100001... .......... U U U U 18 18 16 16
-st 8 . d 0101000011000... .......... U U U U 6 4 4 4
-st 8 . . 0101000011...... A+-DXWL... U U U U 8 8 6 6
-sf 8 . d 0101000111000... .......... U U U U 4 4 4 4
-sf 8 . . 0101000111...... A+-DXWL... U U U U 8 8 6 6
-scc 8 . d 0101....11000... .......... U U U U 4 4 4 4
-scc 8 . . 0101....11...... A+-DXWL... U U U U 8 8 6 6
-stop 0 . . 0100111001110010 .......... S S S S 4 4 8 8
-sub 8 er d 1001...000000... .......... U U U U 4 4 2 2
-sub 8 er . 1001...000...... A+-DXWLdxI U U U U 4 4 2 2
-sub 16 er d 1001...001000... .......... U U U U 4 4 2 2
-sub 16 er a 1001...001001... .......... U U U U 4 4 2 2
-sub 16 er . 1001...001...... A+-DXWLdxI U U U U 4 4 2 2
-sub 32 er d 1001...010000... .......... U U U U 6 6 2 2
-sub 32 er a 1001...010001... .......... U U U U 6 6 2 2
-sub 32 er . 1001...010...... A+-DXWLdxI U U U U 6 6 2 2
-sub 8 re . 1001...100...... A+-DXWL... U U U U 8 8 4 4
-sub 16 re . 1001...101...... A+-DXWL... U U U U 8 8 4 4
-sub 32 re . 1001...110...... A+-DXWL... U U U U 12 12 4 4
-suba 16 . d 1001...011000... .......... U U U U 8 8 2 2
-suba 16 . a 1001...011001... .......... U U U U 8 8 2 2
-suba 16 . . 1001...011...... A+-DXWLdxI U U U U 8 8 2 2
-suba 32 . d 1001...111000... .......... U U U U 6 6 2 2
-suba 32 . a 1001...111001... .......... U U U U 6 6 2 2
-suba 32 . . 1001...111...... A+-DXWLdxI U U U U 6 6 2 2
-subi 8 . d 0000010000000... .......... U U U U 8 8 2 2
-subi 8 . . 0000010000...... A+-DXWL... U U U U 12 12 4 4
-subi 16 . d 0000010001000... .......... U U U U 8 8 2 2
-subi 16 . . 0000010001...... A+-DXWL... U U U U 12 12 4 4
-subi 32 . d 0000010010000... .......... U U U U 16 14 2 2
-subi 32 . . 0000010010...... A+-DXWL... U U U U 20 20 4 4
-subq 8 . d 0101...100000... .......... U U U U 4 4 2 2
-subq 8 . . 0101...100...... A+-DXWL... U U U U 8 8 4 4
-subq 16 . d 0101...101000... .......... U U U U 4 4 2 2
-subq 16 . a 0101...101001... .......... U U U U 8 4 2 2
-subq 16 . . 0101...101...... A+-DXWL... U U U U 8 8 4 4
-subq 32 . d 0101...110000... .......... U U U U 8 8 2 2
-subq 32 . a 0101...110001... .......... U U U U 8 8 2 2
-subq 32 . . 0101...110...... A+-DXWL... U U U U 12 12 4 4
-subx 8 rr . 1001...100000... .......... U U U U 4 4 2 2
-subx 16 rr . 1001...101000... .......... U U U U 4 4 2 2
-subx 32 rr . 1001...110000... .......... U U U U 8 6 2 2
-subx 8 mm ax7 1001111100001... .......... U U U U 18 18 12 12
-subx 8 mm ay7 1001...100001111 .......... U U U U 18 18 12 12
-subx 8 mm axy7 1001111100001111 .......... U U U U 18 18 12 12
-subx 8 mm . 1001...100001... .......... U U U U 18 18 12 12
-subx 16 mm . 1001...101001... .......... U U U U 18 18 12 12
-subx 32 mm . 1001...110001... .......... U U U U 30 30 12 12
-swap 32 . . 0100100001000... .......... U U U U 4 4 4 4
-tas 8 . d 0100101011000... .......... U U U U 4 4 4 4
-tas 8 . . 0100101011...... A+-DXWL... U U U U 14 14 12 12
-trap 0 . . 010011100100.... .......... U U U U 4 4 4 4
-trapt 0 . . 0101000011111100 .......... . . U U . . 4 4
-trapt 16 . . 0101000011111010 .......... . . U U . . 6 6
-trapt 32 . . 0101000011111011 .......... . . U U . . 8 8
-trapf 0 . . 0101000111111100 .......... . . U U . . 4 4
-trapf 16 . . 0101000111111010 .......... . . U U . . 6 6
-trapf 32 . . 0101000111111011 .......... . . U U . . 8 8
-trapcc 0 . . 0101....11111100 .......... . . U U . . 4 4
-trapcc 16 . . 0101....11111010 .......... . . U U . . 6 6
-trapcc 32 . . 0101....11111011 .......... . . U U . . 8 8
-trapv 0 . . 0100111001110110 .......... U U U U 4 4 4 4
-tst 8 . d 0100101000000... .......... U U U U 4 4 2 2
-tst 8 . . 0100101000...... A+-DXWL... U U U U 4 4 2 2
-tst 8 . pcdi 0100101000111010 .......... . . U U . . 7 7
-tst 8 . pcix 0100101000111011 .......... . . U U . . 9 9
-tst 8 . i 0100101000111100 .......... . . U U . . 6 6
-tst 16 . d 0100101001000... .......... U U U U 4 4 2 2
-tst 16 . a 0100101001001... .......... . . U U . . 2 2
-tst 16 . . 0100101001...... A+-DXWL... U U U U 4 4 2 2
-tst 16 . pcdi 0100101001111010 .......... . . U U . . 7 7
-tst 16 . pcix 0100101001111011 .......... . . U U . . 9 9
-tst 16 . i 0100101001111100 .......... . . U U . . 6 6
-tst 32 . d 0100101010000... .......... U U U U 4 4 2 2
-tst 32 . a 0100101010001... .......... . . U U . . 2 2
-tst 32 . . 0100101010...... A+-DXWL... U U U U 4 4 2 2
-tst 32 . pcdi 0100101010111010 .......... . . U U . . 7 7
-tst 32 . pcix 0100101010111011 .......... . . U U . . 9 9
-tst 32 . i 0100101010111100 .......... . . U U . . 6 6
-unlk 32 . a7 0100111001011111 .......... U U U U 12 12 6 6
-unlk 32 . . 0100111001011... .......... U U U U 12 12 6 6
-unpk 16 rr . 1000...110000... .......... . . U U . . 8 8
-unpk 16 mm ax7 1000111110001... .......... . . U U . . 13 13
-unpk 16 mm ay7 1000...110001111 .......... . . U U . . 13 13
-unpk 16 mm axy7 1000111110001111 .......... . . U U . . 13 13
-unpk 16 mm . 1000...110001... .......... . . U U . . 13 13
+1010 0 . . 1010............ .......... U U U U U 4 4 4 4 4
+1111 0 . . 1111............ .......... U U U U U 4 4 4 4 4
+040fpu0 32 . . 11110010........ .......... . . . . U . . . . 0
+040fpu1 32 . . 11110011........ .......... . . . . U . . . . 0
+abcd 8 rr . 1100...100000... .......... U U U U U 6 6 4 4 4
+abcd 8 mm ax7 1100111100001... .......... U U U U U 18 18 16 16 16
+abcd 8 mm ay7 1100...100001111 .......... U U U U U 18 18 16 16 16
+abcd 8 mm axy7 1100111100001111 .......... U U U U U 18 18 16 16 16
+abcd 8 mm . 1100...100001... .......... U U U U U 18 18 16 16 16
+add 8 er d 1101...000000... .......... U U U U U 4 4 2 2 2
+add 8 er . 1101...000...... A+-DXWLdxI U U U U U 4 4 2 2 2
+add 16 er d 1101...001000... .......... U U U U U 4 4 2 2 2
+add 16 er a 1101...001001... .......... U U U U U 4 4 2 2 2
+add 16 er . 1101...001...... A+-DXWLdxI U U U U U 4 4 2 2 2
+add 32 er d 1101...010000... .......... U U U U U 6 6 2 2 2
+add 32 er a 1101...010001... .......... U U U U U 6 6 2 2 2
+add 32 er . 1101...010...... A+-DXWLdxI U U U U U 6 6 2 2 2
+add 8 re . 1101...100...... A+-DXWL... U U U U U 8 8 4 4 4
+add 16 re . 1101...101...... A+-DXWL... U U U U U 8 8 4 4 4
+add 32 re . 1101...110...... A+-DXWL... U U U U U 12 12 4 4 4
+adda 16 . d 1101...011000... .......... U U U U U 8 8 2 2 2
+adda 16 . a 1101...011001... .......... U U U U U 8 8 2 2 2
+adda 16 . . 1101...011...... A+-DXWLdxI U U U U U 8 8 2 2 2
+adda 32 . d 1101...111000... .......... U U U U U 6 6 2 2 2
+adda 32 . a 1101...111001... .......... U U U U U 6 6 2 2 2
+adda 32 . . 1101...111...... A+-DXWLdxI U U U U U 6 6 2 2 2
+addi 8 . d 0000011000000... .......... U U U U U 8 8 2 2 2
+addi 8 . . 0000011000...... A+-DXWL... U U U U U 12 12 4 4 4
+addi 16 . d 0000011001000... .......... U U U U U 8 8 2 2 2
+addi 16 . . 0000011001...... A+-DXWL... U U U U U 12 12 4 4 4
+addi 32 . d 0000011010000... .......... U U U U U 16 14 2 2 2
+addi 32 . . 0000011010...... A+-DXWL... U U U U U 20 20 4 4 4
+addq 8 . d 0101...000000... .......... U U U U U 4 4 2 2 2
+addq 8 . . 0101...000...... A+-DXWL... U U U U U 8 8 4 4 4
+addq 16 . d 0101...001000... .......... U U U U U 4 4 2 2 2
+addq 16 . a 0101...001001... .......... U U U U U 4 4 2 2 2
+addq 16 . . 0101...001...... A+-DXWL... U U U U U 8 8 4 4 4
+addq 32 . d 0101...010000... .......... U U U U U 8 8 2 2 2
+addq 32 . a 0101...010001... .......... U U U U U 8 8 2 2 2
+addq 32 . . 0101...010...... A+-DXWL... U U U U U 12 12 4 4 4
+addx 8 rr . 1101...100000... .......... U U U U U 4 4 2 2 2
+addx 16 rr . 1101...101000... .......... U U U U U 4 4 2 2 2
+addx 32 rr . 1101...110000... .......... U U U U U 8 6 2 2 2
+addx 8 mm ax7 1101111100001... .......... U U U U U 18 18 12 12 12
+addx 8 mm ay7 1101...100001111 .......... U U U U U 18 18 12 12 12
+addx 8 mm axy7 1101111100001111 .......... U U U U U 18 18 12 12 12
+addx 8 mm . 1101...100001... .......... U U U U U 18 18 12 12 12
+addx 16 mm . 1101...101001... .......... U U U U U 18 18 12 12 12
+addx 32 mm . 1101...110001... .......... U U U U U 30 30 12 12 12
+and 8 er d 1100...000000... .......... U U U U U 4 4 2 2 2
+and 8 er . 1100...000...... A+-DXWLdxI U U U U U 4 4 2 2 2
+and 16 er d 1100...001000... .......... U U U U U 4 4 2 2 2
+and 16 er . 1100...001...... A+-DXWLdxI U U U U U 4 4 2 2 2
+and 32 er d 1100...010000... .......... U U U U U 6 6 2 2 2
+and 32 er . 1100...010...... A+-DXWLdxI U U U U U 6 6 2 2 2
+and 8 re . 1100...100...... A+-DXWL... U U U U U 8 8 4 4 4
+and 16 re . 1100...101...... A+-DXWL... U U U U U 8 8 4 4 4
+and 32 re . 1100...110...... A+-DXWL... U U U U U 12 12 4 4 4
+andi 16 toc . 0000001000111100 .......... U U U U U 20 16 12 12 12
+andi 16 tos . 0000001001111100 .......... S S S S S 20 16 12 12 12
+andi 8 . d 0000001000000... .......... U U U U U 8 8 2 2 2
+andi 8 . . 0000001000...... A+-DXWL... U U U U U 12 12 4 4 4
+andi 16 . d 0000001001000... .......... U U U U U 8 8 2 2 2
+andi 16 . . 0000001001...... A+-DXWL... U U U U U 12 12 4 4 4
+andi 32 . d 0000001010000... .......... U U U U U 14 14 2 2 2
+andi 32 . . 0000001010...... A+-DXWL... U U U U U 20 20 4 4 4
+asr 8 s . 1110...000000... .......... U U U U U 6 6 6 6 6
+asr 16 s . 1110...001000... .......... U U U U U 6 6 6 6 6
+asr 32 s . 1110...010000... .......... U U U U U 8 8 6 6 6
+asr 8 r . 1110...000100... .......... U U U U U 6 6 6 6 6
+asr 16 r . 1110...001100... .......... U U U U U 6 6 6 6 6
+asr 32 r . 1110...010100... .......... U U U U U 8 8 6 6 6
+asr 16 . . 1110000011...... A+-DXWL... U U U U U 8 8 5 5 5
+asl 8 s . 1110...100000... .......... U U U U U 6 6 8 8 8
+asl 16 s . 1110...101000... .......... U U U U U 6 6 8 8 8
+asl 32 s . 1110...110000... .......... U U U U U 8 8 8 8 8
+asl 8 r . 1110...100100... .......... U U U U U 6 6 8 8 8
+asl 16 r . 1110...101100... .......... U U U U U 6 6 8 8 8
+asl 32 r . 1110...110100... .......... U U U U U 8 8 8 8 8
+asl 16 . . 1110000111...... A+-DXWL... U U U U U 8 8 6 6 6
+bcc 8 . . 0110............ .......... U U U U U 10 10 6 6 6
+bcc 16 . . 0110....00000000 .......... U U U U U 10 10 6 6 6
+bcc 32 . . 0110....11111111 .......... U U U U U 10 10 6 6 6
+bchg 8 r . 0000...101...... A+-DXWL... U U U U U 8 8 4 4 4
+bchg 32 r d 0000...101000... .......... U U U U U 8 8 4 4 4
+bchg 8 s . 0000100001...... A+-DXWL... U U U U U 12 12 4 4 4
+bchg 32 s d 0000100001000... .......... U U U U U 12 12 4 4 4
+bclr 8 r . 0000...110...... A+-DXWL... U U U U U 8 10 4 4 4
+bclr 32 r d 0000...110000... .......... U U U U U 10 10 4 4 4
+bclr 8 s . 0000100010...... A+-DXWL... U U U U U 12 12 4 4 4
+bclr 32 s d 0000100010000... .......... U U U U U 14 14 4 4 4
+bfchg 32 . d 1110101011000... .......... . . U U U . . 12 12 12 timing not quite correct
+bfchg 32 . . 1110101011...... A..DXWL... . . U U U . . 20 20 20
+bfclr 32 . d 1110110011000... .......... . . U U U . . 12 12 12
+bfclr 32 . . 1110110011...... A..DXWL... . . U U U . . 20 20 20
+bfexts 32 . d 1110101111000... .......... . . U U U . . 8 8 8
+bfexts 32 . . 1110101111...... A..DXWLdx. . . U U U . . 15 15 15
+bfextu 32 . d 1110100111000... .......... . . U U U . . 8 8 8
+bfextu 32 . . 1110100111...... A..DXWLdx. . . U U U . . 15 15 15
+bfffo 32 . d 1110110111000... .......... . . U U U . . 18 18 18
+bfffo 32 . . 1110110111...... A..DXWLdx. . . U U U . . 28 28 28
+bfins 32 . d 1110111111000... .......... . . U U U . . 10 10 10
+bfins 32 . . 1110111111...... A..DXWL... . . U U U . . 17 17 17
+bfset 32 . d 1110111011000... .......... . . U U U . . 12 12 12
+bfset 32 . . 1110111011...... A..DXWL... . . U U U . . 20 20 20
+bftst 32 . d 1110100011000... .......... . . U U U . . 6 6 6
+bftst 32 . . 1110100011...... A..DXWLdx. . . U U U . . 13 13 13
+bkpt 0 . . 0100100001001... .......... . U U U U . 10 10 10 10
+bra 8 . . 01100000........ .......... U U U U U 10 10 10 10 10
+bra 16 . . 0110000000000000 .......... U U U U U 10 10 10 10 10
+bra 32 . . 0110000011111111 .......... U U U U U 10 10 10 10 10
+bset 32 r d 0000...111000... .......... U U U U U 8 8 4 4 4
+bset 8 r . 0000...111...... A+-DXWL... U U U U U 8 8 4 4 4
+bset 8 s . 0000100011...... A+-DXWL... U U U U U 12 12 4 4 4
+bset 32 s d 0000100011000... .......... U U U U U 12 12 4 4 4
+bsr 8 . . 01100001........ .......... U U U U U 18 18 7 7 7
+bsr 16 . . 0110000100000000 .......... U U U U U 18 18 7 7 7
+bsr 32 . . 0110000111111111 .......... U U U U U 18 18 7 7 7
+btst 8 r . 0000...100...... A+-DXWLdxI U U U U U 4 4 4 4 4
+btst 32 r d 0000...100000... .......... U U U U U 6 6 4 4 4
+btst 8 s . 0000100000...... A+-DXWLdx. U U U U U 8 8 4 4 4
+btst 32 s d 0000100000000... .......... U U U U U 10 10 4 4 4
+callm 32 . . 0000011011...... A..DXWLdx. . . U U U . . 60 60 60 not properly emulated
+cas 8 . . 0000101011...... A+-DXWL... . . U U U . . 12 12 12
+cas 16 . . 0000110011...... A+-DXWL... . . U U U . . 12 12 12
+cas 32 . . 0000111011...... A+-DXWL... . . U U U . . 12 12 12
+cas2 16 . . 0000110011111100 .......... . . U U U . . 12 12 12
+cas2 32 . . 0000111011111100 .......... . . U U U . . 12 12 12
+chk 16 . d 0100...110000... .......... U U U U U 10 8 8 8 8
+chk 16 . . 0100...110...... A+-DXWLdxI U U U U U 10 8 8 8 8
+chk 32 . d 0100...100000... .......... . . U U U . . 8 8 8
+chk 32 . . 0100...100...... A+-DXWLdxI . . U U U . . 8 8 8
+chk2cmp2 8 . pcdi 0000000011111010 .......... . . U U U . . 23 23 23
+chk2cmp2 8 . pcix 0000000011111011 .......... . . U U U . . 23 23 23
+chk2cmp2 8 . . 0000000011...... A..DXWL... . . U U U . . 18 18 18
+chk2cmp2 16 . pcdi 0000001011111010 .......... . . U U U . . 23 23 23
+chk2cmp2 16 . pcix 0000001011111011 .......... . . U U U . . 23 23 23
+chk2cmp2 16 . . 0000001011...... A..DXWL... . . U U U . . 18 18 18
+chk2cmp2 32 . pcdi 0000010011111010 .......... . . U U U . . 23 23 23
+chk2cmp2 32 . pcix 0000010011111011 .......... . . U U U . . 23 23 23
+chk2cmp2 32 . . 0000010011...... A..DXWL... . . U U U . . 18 18 18
+clr 8 . d 0100001000000... .......... U U U U U 4 4 2 2 2
+clr 8 . . 0100001000...... A+-DXWL... U U U U U 8 4 4 4 4
+clr 16 . d 0100001001000... .......... U U U U U 4 4 2 2 2
+clr 16 . . 0100001001...... A+-DXWL... U U U U U 8 4 4 4 4
+clr 32 . d 0100001010000... .......... U U U U U 6 6 2 2 2
+clr 32 . . 0100001010...... A+-DXWL... U U U U U 12 6 4 4 4
+cmp 8 . d 1011...000000... .......... U U U U U 4 4 2 2 2
+cmp 8 . . 1011...000...... A+-DXWLdxI U U U U U 4 4 2 2 2
+cmp 16 . d 1011...001000... .......... U U U U U 4 4 2 2 2
+cmp 16 . a 1011...001001... .......... U U U U U 4 4 2 2 2
+cmp 16 . . 1011...001...... A+-DXWLdxI U U U U U 4 4 2 2 2
+cmp 32 . d 1011...010000... .......... U U U U U 6 6 2 2 2
+cmp 32 . a 1011...010001... .......... U U U U U 6 6 2 2 2
+cmp 32 . . 1011...010...... A+-DXWLdxI U U U U U 6 6 2 2 2
+cmpa 16 . d 1011...011000... .......... U U U U U 6 6 4 4 4
+cmpa 16 . a 1011...011001... .......... U U U U U 6 6 4 4 4
+cmpa 16 . . 1011...011...... A+-DXWLdxI U U U U U 6 6 4 4 4
+cmpa 32 . d 1011...111000... .......... U U U U U 6 6 4 4 4
+cmpa 32 . a 1011...111001... .......... U U U U U 6 6 4 4 4
+cmpa 32 . . 1011...111...... A+-DXWLdxI U U U U U 6 6 4 4 4
+cmpi 8 . d 0000110000000... .......... U U U U U 8 8 2 2 2
+cmpi 8 . . 0000110000...... A+-DXWL... U U U U U 8 8 2 2 2
+cmpi 8 . pcdi 0000110000111010 .......... . . U U U . . 7 7 7
+cmpi 8 . pcix 0000110000111011 .......... . . U U U . . 9 9 9
+cmpi 16 . d 0000110001000... .......... U U U U U 8 8 2 2 2
+cmpi 16 . . 0000110001...... A+-DXWL... U U U U U 8 8 2 2 2
+cmpi 16 . pcdi 0000110001111010 .......... . . U U U . . 7 7 7
+cmpi 16 . pcix 0000110001111011 .......... . . U U U . . 9 9 9
+cmpi 32 . d 0000110010000... .......... U U U U U 14 12 2 2 2
+cmpi 32 . . 0000110010...... A+-DXWL... U U U U U 12 12 2 2 2
+cmpi 32 . pcdi 0000110010111010 .......... . . U U U . . 7 7 7
+cmpi 32 . pcix 0000110010111011 .......... . . U U U . . 9 9 9
+cmpm 8 . ax7 1011111100001... .......... U U U U U 12 12 9 9 9
+cmpm 8 . ay7 1011...100001111 .......... U U U U U 12 12 9 9 9
+cmpm 8 . axy7 1011111100001111 .......... U U U U U 12 12 9 9 9
+cmpm 8 . . 1011...100001... .......... U U U U U 12 12 9 9 9
+cmpm 16 . . 1011...101001... .......... U U U U U 12 12 9 9 9
+cmpm 32 . . 1011...110001... .......... U U U U U 20 20 9 9 9
+cpbcc 32 . . 1111...01....... .......... . . U U . . . 4 4 . unemulated
+cpdbcc 32 . . 1111...001001... .......... . . U U . . . 4 4 . unemulated
+cpgen 32 . . 1111...000...... .......... . . U U . . . 4 4 . unemulated
+cpscc 32 . . 1111...001...... .......... . . U U . . . 4 4 . unemulated
+cptrapcc 32 . . 1111...001111... .......... . . U U . . . 4 4 . unemulated
+dbt 16 . . 0101000011001... .......... U U U U U 12 12 6 6 6
+dbf 16 . . 0101000111001... .......... U U U U U 12 12 6 6 6
+dbcc 16 . . 0101....11001... .......... U U U U U 12 12 6 6 6
+divs 16 . d 1000...111000... .......... U U U U U 158 122 56 56 56
+divs 16 . . 1000...111...... A+-DXWLdxI U U U U U 158 122 56 56 56
+divu 16 . d 1000...011000... .......... U U U U U 140 108 44 44 44
+divu 16 . . 1000...011...... A+-DXWLdxI U U U U U 140 108 44 44 44
+divl 32 . d 0100110001000... .......... . . U U U . . 84 84 84
+divl 32 . . 0100110001...... A+-DXWLdxI . . U U U . . 84 84 84
+eor 8 . d 1011...100000... .......... U U U U U 4 4 2 2 2
+eor 8 . . 1011...100...... A+-DXWL... U U U U U 8 8 4 4 4
+eor 16 . d 1011...101000... .......... U U U U U 4 4 2 2 2
+eor 16 . . 1011...101...... A+-DXWL... U U U U U 8 8 4 4 4
+eor 32 . d 1011...110000... .......... U U U U U 8 6 2 2 2
+eor 32 . . 1011...110...... A+-DXWL... U U U U U 12 12 4 4 4
+eori 16 toc . 0000101000111100 .......... U U U U U 20 16 12 12 12
+eori 16 tos . 0000101001111100 .......... S S S S S 20 16 12 12 12
+eori 8 . d 0000101000000... .......... U U U U U 8 8 2 2 2
+eori 8 . . 0000101000...... A+-DXWL... U U U U U 12 12 4 4 4
+eori 16 . d 0000101001000... .......... U U U U U 8 8 2 2 2
+eori 16 . . 0000101001...... A+-DXWL... U U U U U 12 12 4 4 4
+eori 32 . d 0000101010000... .......... U U U U U 16 14 2 2 2
+eori 32 . . 0000101010...... A+-DXWL... U U U U U 20 20 4 4 4
+exg 32 dd . 1100...101000... .......... U U U U U 6 6 2 2 2
+exg 32 aa . 1100...101001... .......... U U U U U 6 6 2 2 2
+exg 32 da . 1100...110001... .......... U U U U U 6 6 2 2 2
+ext 16 . . 0100100010000... .......... U U U U U 4 4 4 4 4
+ext 32 . . 0100100011000... .......... U U U U U 4 4 4 4 4
+extb 32 . . 0100100111000... .......... . . U U U . . 4 4 4
+illegal 0 . . 0100101011111100 .......... U U U U U 4 4 4 4 4
+jmp 32 . . 0100111011...... A..DXWLdx. U U U U U 4 4 0 0 0
+jsr 32 . . 0100111010...... A..DXWLdx. U U U U U 12 12 0 0 0
+lea 32 . . 0100...111...... A..DXWLdx. U U U U U 0 0 2 2 2
+link 16 . a7 0100111001010111 .......... U U U U U 16 16 5 5 5
+link 16 . . 0100111001010... .......... U U U U U 16 16 5 5 5
+link 32 . a7 0100100000001111 .......... . . U U U . . 6 6 6
+link 32 . . 0100100000001... .......... . . U U U . . 6 6 6
+lsr 8 s . 1110...000001... .......... U U U U U 6 6 4 4 4
+lsr 16 s . 1110...001001... .......... U U U U U 6 6 4 4 4
+lsr 32 s . 1110...010001... .......... U U U U U 8 8 4 4 4
+lsr 8 r . 1110...000101... .......... U U U U U 6 6 6 6 6
+lsr 16 r . 1110...001101... .......... U U U U U 6 6 6 6 6
+lsr 32 r . 1110...010101... .......... U U U U U 8 8 6 6 6
+lsr 16 . . 1110001011...... A+-DXWL... U U U U U 8 8 5 5 5
+lsl 8 s . 1110...100001... .......... U U U U U 6 6 4 4 4
+lsl 16 s . 1110...101001... .......... U U U U U 6 6 4 4 4
+lsl 32 s . 1110...110001... .......... U U U U U 8 8 4 4 4
+lsl 8 r . 1110...100101... .......... U U U U U 6 6 6 6 6
+lsl 16 r . 1110...101101... .......... U U U U U 6 6 6 6 6
+lsl 32 r . 1110...110101... .......... U U U U U 8 8 6 6 6
+lsl 16 . . 1110001111...... A+-DXWL... U U U U U 8 8 5 5 5
+move 8 d d 0001...000000... .......... U U U U U 4 4 2 2 2
+move 8 d . 0001...000...... A+-DXWLdxI U U U U U 4 4 2 2 2
+move 8 ai d 0001...010000... .......... U U U U U 8 8 4 4 4
+move 8 ai . 0001...010...... A+-DXWLdxI U U U U U 8 8 4 4 4
+move 8 pi d 0001...011000... .......... U U U U U 8 8 4 4 4
+move 8 pi . 0001...011...... A+-DXWLdxI U U U U U 8 8 4 4 4
+move 8 pi7 d 0001111011000... .......... U U U U U 8 8 4 4 4
+move 8 pi7 . 0001111011...... A+-DXWLdxI U U U U U 8 8 4 4 4
+move 8 pd d 0001...100000... .......... U U U U U 8 8 5 5 5
+move 8 pd . 0001...100...... A+-DXWLdxI U U U U U 8 8 5 5 5
+move 8 pd7 d 0001111100000... .......... U U U U U 8 8 5 5 5
+move 8 pd7 . 0001111100...... A+-DXWLdxI U U U U U 8 8 5 5 5
+move 8 di d 0001...101000... .......... U U U U U 12 12 5 5 5
+move 8 di . 0001...101...... A+-DXWLdxI U U U U U 12 12 5 5 5
+move 8 ix d 0001...110000... .......... U U U U U 14 14 7 7 7
+move 8 ix . 0001...110...... A+-DXWLdxI U U U U U 14 14 7 7 7
+move 8 aw d 0001000111000... .......... U U U U U 12 12 4 4 4
+move 8 aw . 0001000111...... A+-DXWLdxI U U U U U 12 12 4 4 4
+move 8 al d 0001001111000... .......... U U U U U 16 16 6 6 6
+move 8 al . 0001001111...... A+-DXWLdxI U U U U U 16 16 6 6 6
+move 16 d d 0011...000000... .......... U U U U U 4 4 2 2 2
+move 16 d a 0011...000001... .......... U U U U U 4 4 2 2 2
+move 16 d . 0011...000...... A+-DXWLdxI U U U U U 4 4 2 2 2
+move 16 ai d 0011...010000... .......... U U U U U 8 8 4 4 4
+move 16 ai a 0011...010001... .......... U U U U U 8 8 4 4 4
+move 16 ai . 0011...010...... A+-DXWLdxI U U U U U 8 8 4 4 4
+move 16 pi d 0011...011000... .......... U U U U U 8 8 4 4 4
+move 16 pi a 0011...011001... .......... U U U U U 8 8 4 4 4
+move 16 pi . 0011...011...... A+-DXWLdxI U U U U U 8 8 4 4 4
+move 16 pd d 0011...100000... .......... U U U U U 8 8 5 5 5
+move 16 pd a 0011...100001... .......... U U U U U 8 8 5 5 5
+move 16 pd . 0011...100...... A+-DXWLdxI U U U U U 8 8 5 5 5
+move 16 di d 0011...101000... .......... U U U U U 12 12 5 5 5
+move 16 di a 0011...101001... .......... U U U U U 12 12 5 5 5
+move 16 di . 0011...101...... A+-DXWLdxI U U U U U 12 12 5 5 5
+move 16 ix d 0011...110000... .......... U U U U U 14 14 7 7 7
+move 16 ix a 0011...110001... .......... U U U U U 14 14 7 7 7
+move 16 ix . 0011...110...... A+-DXWLdxI U U U U U 14 14 7 7 7
+move 16 aw d 0011000111000... .......... U U U U U 12 12 4 4 4
+move 16 aw a 0011000111001... .......... U U U U U 12 12 4 4 4
+move 16 aw . 0011000111...... A+-DXWLdxI U U U U U 12 12 4 4 4
+move 16 al d 0011001111000... .......... U U U U U 16 16 6 6 6
+move 16 al a 0011001111001... .......... U U U U U 16 16 6 6 6
+move 16 al . 0011001111...... A+-DXWLdxI U U U U U 16 16 6 6 6
+move 32 d d 0010...000000... .......... U U U U U 4 4 2 2 2
+move 32 d a 0010...000001... .......... U U U U U 4 4 2 2 2
+move 32 d . 0010...000...... A+-DXWLdxI U U U U U 4 4 2 2 2
+move 32 ai d 0010...010000... .......... U U U U U 12 12 4 4 4
+move 32 ai a 0010...010001... .......... U U U U U 12 12 4 4 4
+move 32 ai . 0010...010...... A+-DXWLdxI U U U U U 12 12 4 4 4
+move 32 pi d 0010...011000... .......... U U U U U 12 12 4 4 4
+move 32 pi a 0010...011001... .......... U U U U U 12 12 4 4 4
+move 32 pi . 0010...011...... A+-DXWLdxI U U U U U 12 12 4 4 4
+move 32 pd d 0010...100000... .......... U U U U U 12 14 5 5 5
+move 32 pd a 0010...100001... .......... U U U U U 12 14 5 5 5
+move 32 pd . 0010...100...... A+-DXWLdxI U U U U U 12 14 5 5 5
+move 32 di d 0010...101000... .......... U U U U U 16 16 5 5 5
+move 32 di a 0010...101001... .......... U U U U U 16 16 5 5 5
+move 32 di . 0010...101...... A+-DXWLdxI U U U U U 16 16 5 5 5
+move 32 ix d 0010...110000... .......... U U U U U 18 18 7 7 7
+move 32 ix a 0010...110001... .......... U U U U U 18 18 7 7 7
+move 32 ix . 0010...110...... A+-DXWLdxI U U U U U 18 18 7 7 7
+move 32 aw d 0010000111000... .......... U U U U U 16 16 4 4 4
+move 32 aw a 0010000111001... .......... U U U U U 16 16 4 4 4
+move 32 aw . 0010000111...... A+-DXWLdxI U U U U U 16 16 4 4 4
+move 32 al d 0010001111000... .......... U U U U U 20 20 6 6 6
+move 32 al a 0010001111001... .......... U U U U U 20 20 6 6 6
+move 32 al . 0010001111...... A+-DXWLdxI U U U U U 20 20 6 6 6
+movea 16 . d 0011...001000... .......... U U U U U 4 4 2 2 2
+movea 16 . a 0011...001001... .......... U U U U U 4 4 2 2 2
+movea 16 . . 0011...001...... A+-DXWLdxI U U U U U 4 4 2 2 2
+movea 32 . d 0010...001000... .......... U U U U U 4 4 2 2 2
+movea 32 . a 0010...001001... .......... U U U U U 4 4 2 2 2
+movea 32 . . 0010...001...... A+-DXWLdxI U U U U U 4 4 2 2 2
+move 16 frc d 0100001011000... .......... . U U U U . 4 4 4 4
+move 16 frc . 0100001011...... A+-DXWL... . U U U U . 8 4 4 4
+move 16 toc d 0100010011000... .......... U U U U U 12 12 4 4 4
+move 16 toc . 0100010011...... A+-DXWLdxI U U U U U 12 12 4 4 4
+move 16 frs d 0100000011000... .......... U S S S S 6 4 8 8 8 U only for 000
+move 16 frs . 0100000011...... A+-DXWL... U S S S S 8 8 8 8 8 U only for 000
+move 16 tos d 0100011011000... .......... S S S S S 12 12 8 8 8
+move 16 tos . 0100011011...... A+-DXWLdxI S S S S S 12 12 8 8 8
+move 32 fru . 0100111001101... .......... S S S S S 4 6 2 2 2
+move 32 tou . 0100111001100... .......... S S S S S 4 6 2 2 2
+movec 32 cr . 0100111001111010 .......... . S S S S . 12 6 6 6
+movec 32 rc . 0100111001111011 .......... . S S S S . 10 12 12 12
+movem 16 re pd 0100100010100... .......... U U U U U 8 8 4 4 4
+movem 16 re . 0100100010...... A..DXWL... U U U U U 8 8 4 4 4
+movem 32 re pd 0100100011100... .......... U U U U U 8 8 4 4 4
+movem 32 re . 0100100011...... A..DXWL... U U U U U 8 8 4 4 4
+movem 16 er pi 0100110010011... .......... U U U U U 12 12 8 8 8
+movem 16 er pcdi 0100110010111010 .......... U U U U U 16 16 9 9 9
+movem 16 er pcix 0100110010111011 .......... U U U U U 18 18 11 11 11
+movem 16 er . 0100110010...... A..DXWL... U U U U U 12 12 8 8 8
+movem 32 er pi 0100110011011... .......... U U U U U 12 12 8 8 8
+movem 32 er pcdi 0100110011111010 .......... U U U U U 16 16 9 9 9
+movem 32 er pcix 0100110011111011 .......... U U U U U 18 18 11 11 11
+movem 32 er . 0100110011...... A..DXWL... U U U U U 12 12 8 8 8
+movep 16 er . 0000...100001... .......... U U U U U 16 16 12 12 12
+movep 32 er . 0000...101001... .......... U U U U U 24 24 18 18 18
+movep 16 re . 0000...110001... .......... U U U U U 16 16 11 11 11
+movep 32 re . 0000...111001... .......... U U U U U 24 24 17 17 17
+moveq 32 . . 0111...0........ .......... U U U U U 4 4 2 2 2
+moves 8 . . 0000111000...... A+-DXWL... . S S S S . 14 5 5 5
+moves 16 . . 0000111001...... A+-DXWL... . S S S S . 14 5 5 5
+moves 32 . . 0000111010...... A+-DXWL... . S S S S . 16 5 5 5
+move16 32 . . 1111011000100... .......... . . . . U . . . . 4 TODO: correct timing
+muls 16 . d 1100...111000... .......... U U U U U 54 32 27 27 27
+muls 16 . . 1100...111...... A+-DXWLdxI U U U U U 54 32 27 27 27
+mulu 16 . d 1100...011000... .......... U U U U U 54 30 27 27 27
+mulu 16 . . 1100...011...... A+-DXWLdxI U U U U U 54 30 27 27 27
+mull 32 . d 0100110000000... .......... . . U U U . . 43 43 43
+mull 32 . . 0100110000...... A+-DXWLdxI . . U U U . . 43 43 43
+nbcd 8 . d 0100100000000... .......... U U U U U 6 6 6 6 6
+nbcd 8 . . 0100100000...... A+-DXWL... U U U U U 8 8 6 6 6
+neg 8 . d 0100010000000... .......... U U U U U 4 4 2 2 2
+neg 8 . . 0100010000...... A+-DXWL... U U U U U 8 8 4 4 4
+neg 16 . d 0100010001000... .......... U U U U U 4 4 2 2 2
+neg 16 . . 0100010001...... A+-DXWL... U U U U U 8 8 4 4 4
+neg 32 . d 0100010010000... .......... U U U U U 6 6 2 2 2
+neg 32 . . 0100010010...... A+-DXWL... U U U U U 12 12 4 4 4
+negx 8 . d 0100000000000... .......... U U U U U 4 4 2 2 2
+negx 8 . . 0100000000...... A+-DXWL... U U U U U 8 8 4 4 4
+negx 16 . d 0100000001000... .......... U U U U U 4 4 2 2 2
+negx 16 . . 0100000001...... A+-DXWL... U U U U U 8 8 4 4 4
+negx 32 . d 0100000010000... .......... U U U U U 6 6 2 2 2
+negx 32 . . 0100000010...... A+-DXWL... U U U U U 12 12 4 4 4
+nop 0 . . 0100111001110001 .......... U U U U U 4 4 2 2 2
+not 8 . d 0100011000000... .......... U U U U U 4 4 2 2 2
+not 8 . . 0100011000...... A+-DXWL... U U U U U 8 8 4 4 4
+not 16 . d 0100011001000... .......... U U U U U 4 4 2 2 2
+not 16 . . 0100011001...... A+-DXWL... U U U U U 8 8 4 4 4
+not 32 . d 0100011010000... .......... U U U U U 6 6 2 2 2
+not 32 . . 0100011010...... A+-DXWL... U U U U U 12 12 4 4 4
+or 8 er d 1000...000000... .......... U U U U U 4 4 2 2 2
+or 8 er . 1000...000...... A+-DXWLdxI U U U U U 4 4 2 2 2
+or 16 er d 1000...001000... .......... U U U U U 4 4 2 2 2
+or 16 er . 1000...001...... A+-DXWLdxI U U U U U 4 4 2 2 2
+or 32 er d 1000...010000... .......... U U U U U 6 6 2 2 2
+or 32 er . 1000...010...... A+-DXWLdxI U U U U U 6 6 2 2 2
+or 8 re . 1000...100...... A+-DXWL... U U U U U 8 8 4 4 4
+or 16 re . 1000...101...... A+-DXWL... U U U U U 8 8 4 4 4
+or 32 re . 1000...110...... A+-DXWL... U U U U U 12 12 4 4 4
+ori 16 toc . 0000000000111100 .......... U U U U U 20 16 12 12 12
+ori 16 tos . 0000000001111100 .......... S S S S S 20 16 12 12 12
+ori 8 . d 0000000000000... .......... U U U U U 8 8 2 2 2
+ori 8 . . 0000000000...... A+-DXWL... U U U U U 12 12 4 4 4
+ori 16 . d 0000000001000... .......... U U U U U 8 8 2 2 2
+ori 16 . . 0000000001...... A+-DXWL... U U U U U 12 12 4 4 4
+ori 32 . d 0000000010000... .......... U U U U U 16 14 2 2 2
+ori 32 . . 0000000010...... A+-DXWL... U U U U U 20 20 4 4 4
+pack 16 rr . 1000...101000... .......... . . U U U . . 6 6 6
+pack 16 mm ax7 1000111101001... .......... . . U U U . . 13 13 13
+pack 16 mm ay7 1000...101001111 .......... . . U U U . . 13 13 13
+pack 16 mm axy7 1000111101001111 .......... . . U U U . . 13 13 13
+pack 16 mm . 1000...101001... .......... . . U U U . . 13 13 13
+pea 32 . . 0100100001...... A..DXWLdx. U U U U U 6 6 5 5 5
+pflush 32 . . 1111010100011000 .......... . . . . S . . . . 4 TODO: correct timing
+pmove 32 . . 1111000000...... A..DXWLdx. . . S S S . . 8 8 8
+reset 0 . . 0100111001110000 .......... S S S S S 0 0 0 0 0
+ror 8 s . 1110...000011... .......... U U U U U 6 6 8 8 8
+ror 16 s . 1110...001011... .......... U U U U U 6 6 8 8 8
+ror 32 s . 1110...010011... .......... U U U U U 8 8 8 8 8
+ror 8 r . 1110...000111... .......... U U U U U 6 6 8 8 8
+ror 16 r . 1110...001111... .......... U U U U U 6 6 8 8 8
+ror 32 r . 1110...010111... .......... U U U U U 8 8 8 8 8
+ror 16 . . 1110011011...... A+-DXWL... U U U U U 8 8 7 7 7
+rol 8 s . 1110...100011... .......... U U U U U 6 6 8 8 8
+rol 16 s . 1110...101011... .......... U U U U U 6 6 8 8 8
+rol 32 s . 1110...110011... .......... U U U U U 8 8 8 8 8
+rol 8 r . 1110...100111... .......... U U U U U 6 6 8 8 8
+rol 16 r . 1110...101111... .......... U U U U U 6 6 8 8 8
+rol 32 r . 1110...110111... .......... U U U U U 8 8 8 8 8
+rol 16 . . 1110011111...... A+-DXWL... U U U U U 8 8 7 7 7
+roxr 8 s . 1110...000010... .......... U U U U U 6 6 12 12 12
+roxr 16 s . 1110...001010... .......... U U U U U 6 6 12 12 12
+roxr 32 s . 1110...010010... .......... U U U U U 8 8 12 12 12
+roxr 8 r . 1110...000110... .......... U U U U U 6 6 12 12 12
+roxr 16 r . 1110...001110... .......... U U U U U 6 6 12 12 12
+roxr 32 r . 1110...010110... .......... U U U U U 8 8 12 12 12
+roxr 16 . . 1110010011...... A+-DXWL... U U U U U 8 8 5 5 5
+roxl 8 s . 1110...100010... .......... U U U U U 6 6 12 12 12
+roxl 16 s . 1110...101010... .......... U U U U U 6 6 12 12 12
+roxl 32 s . 1110...110010... .......... U U U U U 8 8 12 12 12
+roxl 8 r . 1110...100110... .......... U U U U U 6 6 12 12 12
+roxl 16 r . 1110...101110... .......... U U U U U 6 6 12 12 12
+roxl 32 r . 1110...110110... .......... U U U U U 8 8 12 12 12
+roxl 16 . . 1110010111...... A+-DXWL... U U U U U 8 8 5 5 5
+rtd 32 . . 0100111001110100 .......... . U U U U . 16 10 10 10
+rte 32 . . 0100111001110011 .......... S S S S S 20 24 20 20 20 bus fault not emulated
+rtm 32 . . 000001101100.... .......... . . U U U . . 19 19 19 not properly emulated
+rtr 32 . . 0100111001110111 .......... U U U U U 20 20 14 14 14
+rts 32 . . 0100111001110101 .......... U U U U U 16 16 10 10 10
+sbcd 8 rr . 1000...100000... .......... U U U U U 6 6 4 4 4
+sbcd 8 mm ax7 1000111100001... .......... U U U U U 18 18 16 16 16
+sbcd 8 mm ay7 1000...100001111 .......... U U U U U 18 18 16 16 16
+sbcd 8 mm axy7 1000111100001111 .......... U U U U U 18 18 16 16 16
+sbcd 8 mm . 1000...100001... .......... U U U U U 18 18 16 16 16
+st 8 . d 0101000011000... .......... U U U U U 6 4 4 4 4
+st 8 . . 0101000011...... A+-DXWL... U U U U U 8 8 6 6 6
+sf 8 . d 0101000111000... .......... U U U U U 4 4 4 4 4
+sf 8 . . 0101000111...... A+-DXWL... U U U U U 8 8 6 6 6
+scc 8 . d 0101....11000... .......... U U U U U 4 4 4 4 4
+scc 8 . . 0101....11...... A+-DXWL... U U U U U 8 8 6 6 6
+stop 0 . . 0100111001110010 .......... S S S S S 4 4 8 8 8
+sub 8 er d 1001...000000... .......... U U U U U 4 4 2 2 2
+sub 8 er . 1001...000...... A+-DXWLdxI U U U U U 4 4 2 2 2
+sub 16 er d 1001...001000... .......... U U U U U 4 4 2 2 2
+sub 16 er a 1001...001001... .......... U U U U U 4 4 2 2 2
+sub 16 er . 1001...001...... A+-DXWLdxI U U U U U 4 4 2 2 2
+sub 32 er d 1001...010000... .......... U U U U U 6 6 2 2 2
+sub 32 er a 1001...010001... .......... U U U U U 6 6 2 2 2
+sub 32 er . 1001...010...... A+-DXWLdxI U U U U U 6 6 2 2 2
+sub 8 re . 1001...100...... A+-DXWL... U U U U U 8 8 4 4 4
+sub 16 re . 1001...101...... A+-DXWL... U U U U U 8 8 4 4 4
+sub 32 re . 1001...110...... A+-DXWL... U U U U U 12 12 4 4 4
+suba 16 . d 1001...011000... .......... U U U U U 8 8 2 2 2
+suba 16 . a 1001...011001... .......... U U U U U 8 8 2 2 2
+suba 16 . . 1001...011...... A+-DXWLdxI U U U U U 8 8 2 2 2
+suba 32 . d 1001...111000... .......... U U U U U 6 6 2 2 2
+suba 32 . a 1001...111001... .......... U U U U U 6 6 2 2 2
+suba 32 . . 1001...111...... A+-DXWLdxI U U U U U 6 6 2 2 2
+subi 8 . d 0000010000000... .......... U U U U U 8 8 2 2 2
+subi 8 . . 0000010000...... A+-DXWL... U U U U U 12 12 4 4 4
+subi 16 . d 0000010001000... .......... U U U U U 8 8 2 2 2
+subi 16 . . 0000010001...... A+-DXWL... U U U U U 12 12 4 4 4
+subi 32 . d 0000010010000... .......... U U U U U 16 14 2 2 2
+subi 32 . . 0000010010...... A+-DXWL... U U U U U 20 20 4 4 4
+subq 8 . d 0101...100000... .......... U U U U U 4 4 2 2 2
+subq 8 . . 0101...100...... A+-DXWL... U U U U U 8 8 4 4 4
+subq 16 . d 0101...101000... .......... U U U U U 4 4 2 2 2
+subq 16 . a 0101...101001... .......... U U U U U 8 4 2 2 2
+subq 16 . . 0101...101...... A+-DXWL... U U U U U 8 8 4 4 4
+subq 32 . d 0101...110000... .......... U U U U U 8 8 2 2 2
+subq 32 . a 0101...110001... .......... U U U U U 8 8 2 2 2
+subq 32 . . 0101...110...... A+-DXWL... U U U U U 12 12 4 4 4
+subx 8 rr . 1001...100000... .......... U U U U U 4 4 2 2 2
+subx 16 rr . 1001...101000... .......... U U U U U 4 4 2 2 2
+subx 32 rr . 1001...110000... .......... U U U U U 8 6 2 2 2
+subx 8 mm ax7 1001111100001... .......... U U U U U 18 18 12 12 12
+subx 8 mm ay7 1001...100001111 .......... U U U U U 18 18 12 12 12
+subx 8 mm axy7 1001111100001111 .......... U U U U U 18 18 12 12 12
+subx 8 mm . 1001...100001... .......... U U U U U 18 18 12 12 12
+subx 16 mm . 1001...101001... .......... U U U U U 18 18 12 12 12
+subx 32 mm . 1001...110001... .......... U U U U U 30 30 12 12 12
+swap 32 . . 0100100001000... .......... U U U U U 4 4 4 4 4
+tas 8 . d 0100101011000... .......... U U U U U 4 4 4 4 4
+tas 8 . . 0100101011...... A+-DXWL... U U U U U 14 14 12 12 12
+trap 0 . . 010011100100.... .......... U U U U U 4 4 4 4 4
+trapt 0 . . 0101000011111100 .......... . . U U U . . 4 4 4
+trapt 16 . . 0101000011111010 .......... . . U U U . . 6 6 6
+trapt 32 . . 0101000011111011 .......... . . U U U . . 8 8 8
+trapf 0 . . 0101000111111100 .......... . . U U U . . 4 4 4
+trapf 16 . . 0101000111111010 .......... . . U U U . . 6 6 6
+trapf 32 . . 0101000111111011 .......... . . U U U . . 8 8 8
+trapcc 0 . . 0101....11111100 .......... . . U U U . . 4 4 4
+trapcc 16 . . 0101....11111010 .......... . . U U U . . 6 6 6
+trapcc 32 . . 0101....11111011 .......... . . U U U . . 8 8 8
+trapv 0 . . 0100111001110110 .......... U U U U U 4 4 4 4 4
+tst 8 . d 0100101000000... .......... U U U U U 4 4 2 2 2
+tst 8 . . 0100101000...... A+-DXWL... U U U U U 4 4 2 2 2
+tst 8 . pcdi 0100101000111010 .......... . . U U U . . 7 7 7
+tst 8 . pcix 0100101000111011 .......... . . U U U . . 9 9 9
+tst 8 . i 0100101000111100 .......... . . U U U . . 6 6 6
+tst 16 . d 0100101001000... .......... U U U U U 4 4 2 2 2
+tst 16 . a 0100101001001... .......... . . U U U . . 2 2 2
+tst 16 . . 0100101001...... A+-DXWL... U U U U U 4 4 2 2 2
+tst 16 . pcdi 0100101001111010 .......... . . U U U . . 7 7 7
+tst 16 . pcix 0100101001111011 .......... . . U U U . . 9 9 9
+tst 16 . i 0100101001111100 .......... . . U U U . . 6 6 6
+tst 32 . d 0100101010000... .......... U U U U U 4 4 2 2 2
+tst 32 . a 0100101010001... .......... . . U U U . . 2 2 2
+tst 32 . . 0100101010...... A+-DXWL... U U U U U 4 4 2 2 2
+tst 32 . pcdi 0100101010111010 .......... . . U U U . . 7 7 7
+tst 32 . pcix 0100101010111011 .......... . . U U U . . 9 9 9
+tst 32 . i 0100101010111100 .......... . . U U U . . 6 6 6
+unlk 32 . a7 0100111001011111 .......... U U U U U 12 12 6 6 6
+unlk 32 . . 0100111001011... .......... U U U U U 12 12 6 6 6
+unpk 16 rr . 1000...110000... .......... . . U U U . . 8 8 8
+unpk 16 mm ax7 1000111110001... .......... . . U U U . . 13 13 13
+unpk 16 mm ay7 1000...110001111 .......... . . U U U . . 13 13 13
+unpk 16 mm axy7 1000111110001111 .......... . . U U U . . 13 13 13
+unpk 16 mm . 1000...110001... .......... . . U U U . . 13 13 13
@@ -6666,15 +6667,20 @@ M68KMAKE_OP(movec, 32, rc, .)
m68k->dfc = REG_DA[(word2 >> 12) & 15] & 7;
return;
case 0x002: /* CACR */
+ /* Only EC020 and later have CACR */
if(CPU_TYPE_IS_EC020_PLUS(m68k->cpu_type))
{
+ /* 68030 can write all bits except 5-7, 040 can write all */
if (CPU_TYPE_IS_040_PLUS(m68k->cpu_type))
{
m68k->cacr = REG_DA[(word2 >> 12) & 15];
}
+ else if (CPU_TYPE_IS_030_PLUS(m68k->cpu_type))
+ {
+ m68k->cacr = REG_DA[(word2 >> 12) & 15] & 0xff1f;
+ }
else
{
- /* non 68040 can only set the lower 4 bits (C,CE,F,E) */
m68k->cacr = REG_DA[(word2 >> 12) & 15] & 0x0f;
}
return;
@@ -7991,14 +7997,32 @@ M68KMAKE_OP(pea, 32, ., .)
M68KMAKE_OP(pflush, 32, ., .)
{
- if(CPU_TYPE_IS_040_PLUS(m68k->cpu_type))
+ if ((CPU_TYPE_IS_040_PLUS(m68k->cpu_type)) && (m68k->has_pmmu))
{
// Nothing to do, unless address translation cache is emulated
+ logerror("680x0: unhandled PFLUSH\n");
return;
}
m68ki_exception_illegal(m68k);
}
+M68KMAKE_OP(pmove, 32, ., .)
+{
+ UINT16 modes;
+ UINT32 ea;
+
+ modes = m68ki_read_imm_16(m68k);
+ ea = M68KMAKE_GET_EA_AY_32;
+
+ if ((CPU_TYPE_IS_EC020_PLUS(m68k->cpu_type)) && (m68k->has_pmmu))
+ {
+ logerror("680x0: unhandled PMOVE modes %x ea %x\n", modes, ea);
+ }
+ else
+ {
+ m68ki_exception_illegal(m68k);
+ }
+}
M68KMAKE_OP(reset, 0, ., .)
{
diff --git a/src/emu/cpu/m68000/m68kcpu.c b/src/emu/cpu/m68000/m68kcpu.c
index bcf83e85b65..ee25c763a80 100644
--- a/src/emu/cpu/m68000/m68kcpu.c
+++ b/src/emu/cpu/m68000/m68kcpu.c
@@ -5,7 +5,7 @@
#if 0
static const char copyright_notice[] =
"MUSASHI\n"
-"Version 4.00 (2008-11-17)\n"
+"Version 4.10 (2009-09-27)\n"
"A portable Motorola M680x0 processor emulation engine.\n"
"Copyright Karl Stenerud. All rights reserved.\n"
"\n"
@@ -17,7 +17,7 @@ static const char copyright_notice[] =
"(Karl Stenerud).\n"
"\n"
"The latest version of this code can be obtained at:\n"
-"http://kstenerud.cjb.net\n"
+"http://kstenerud.cjb.net or http://mamedev.org\n"
;
#endif
@@ -85,7 +85,7 @@ const UINT32 m68ki_shift_32_table[65] =
/* Number of clock cycles to use for exception processing.
* I used 4 for any vectors that are undocumented for processing times.
*/
-const UINT8 m68ki_exception_cycle_table[4][256] =
+const UINT8 m68ki_exception_cycle_table[5][256] =
{
{ /* 000 */
40, /* 0: Reset - Initial Stack Pointer */
@@ -306,6 +306,79 @@ const UINT8 m68ki_exception_cycle_table[4][256] =
4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,
4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4
},
+ { /* 030 - not correct */
+ 4, /* 0: Reset - Initial Stack Pointer */
+ 4, /* 1: Reset - Initial Program Counter */
+ 50, /* 2: Bus Error (unemulated) */
+ 50, /* 3: Address Error (unemulated) */
+ 20, /* 4: Illegal Instruction */
+ 38, /* 5: Divide by Zero */
+ 40, /* 6: CHK */
+ 20, /* 7: TRAPV */
+ 34, /* 8: Privilege Violation */
+ 25, /* 9: Trace */
+ 20, /* 10: 1010 */
+ 20, /* 11: 1111 */
+ 4, /* 12: RESERVED */
+ 4, /* 13: Coprocessor Protocol Violation (unemulated) */
+ 4, /* 14: Format Error */
+ 30, /* 15: Uninitialized Interrupt */
+ 4, /* 16: RESERVED */
+ 4, /* 17: RESERVED */
+ 4, /* 18: RESERVED */
+ 4, /* 19: RESERVED */
+ 4, /* 20: RESERVED */
+ 4, /* 21: RESERVED */
+ 4, /* 22: RESERVED */
+ 4, /* 23: RESERVED */
+ 30, /* 24: Spurious Interrupt */
+ 30, /* 25: Level 1 Interrupt Autovector */
+ 30, /* 26: Level 2 Interrupt Autovector */
+ 30, /* 27: Level 3 Interrupt Autovector */
+ 30, /* 28: Level 4 Interrupt Autovector */
+ 30, /* 29: Level 5 Interrupt Autovector */
+ 30, /* 30: Level 6 Interrupt Autovector */
+ 30, /* 31: Level 7 Interrupt Autovector */
+ 20, /* 32: TRAP #0 */
+ 20, /* 33: TRAP #1 */
+ 20, /* 34: TRAP #2 */
+ 20, /* 35: TRAP #3 */
+ 20, /* 36: TRAP #4 */
+ 20, /* 37: TRAP #5 */
+ 20, /* 38: TRAP #6 */
+ 20, /* 39: TRAP #7 */
+ 20, /* 40: TRAP #8 */
+ 20, /* 41: TRAP #9 */
+ 20, /* 42: TRAP #10 */
+ 20, /* 43: TRAP #11 */
+ 20, /* 44: TRAP #12 */
+ 20, /* 45: TRAP #13 */
+ 20, /* 46: TRAP #14 */
+ 20, /* 47: TRAP #15 */
+ 4, /* 48: FP Branch or Set on Unknown Condition (unemulated) */
+ 4, /* 49: FP Inexact Result (unemulated) */
+ 4, /* 50: FP Divide by Zero (unemulated) */
+ 4, /* 51: FP Underflow (unemulated) */
+ 4, /* 52: FP Operand Error (unemulated) */
+ 4, /* 53: FP Overflow (unemulated) */
+ 4, /* 54: FP Signaling NAN (unemulated) */
+ 4, /* 55: FP Unimplemented Data Type (unemulated) */
+ 4, /* 56: MMU Configuration Error (unemulated) */
+ 4, /* 57: MMU Illegal Operation Error (unemulated) */
+ 4, /* 58: MMU Access Level Violation Error (unemulated) */
+ 4, /* 59: RESERVED */
+ 4, /* 60: RESERVED */
+ 4, /* 61: RESERVED */
+ 4, /* 62: RESERVED */
+ 4, /* 63: RESERVED */
+ /* 64-255: User Defined */
+ 4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,
+ 4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,
+ 4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,
+ 4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,
+ 4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,
+ 4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4
+ },
{ /* 040 */ // TODO: these values are not correct
4, /* 0: Reset - Initial Stack Pointer */
4, /* 1: Reset - Initial Program Counter */
@@ -407,12 +480,13 @@ const UINT8 m68ki_ea_idx_cycle_table[64] =
CPU STATE DESCRIPTION
***************************************************************************/
-#define MASK_ALL (CPU_TYPE_000 | CPU_TYPE_008 | CPU_TYPE_010 | CPU_TYPE_EC020 | CPU_TYPE_020 | CPU_TYPE_040)
+#define MASK_ALL (CPU_TYPE_000 | CPU_TYPE_008 | CPU_TYPE_010 | CPU_TYPE_EC020 | CPU_TYPE_020 | CPU_TYPE_EC030 | CPU_TYPE_030 | CPU_TYPE_EC040 | CPU_TYPE_040)
#define MASK_24BIT_SPACE (CPU_TYPE_000 | CPU_TYPE_008 | CPU_TYPE_010 | CPU_TYPE_EC020)
-#define MASK_32BIT_SPACE (CPU_TYPE_020 | CPU_TYPE_040)
-#define MASK_010_OR_LATER (CPU_TYPE_010 | CPU_TYPE_EC020 | CPU_TYPE_020 | CPU_TYPE_040)
-#define MASK_020_OR_LATER (CPU_TYPE_EC020 | CPU_TYPE_020 | CPU_TYPE_040)
-#define MASK_040_OR_LATER (CPU_TYPE_040)
+#define MASK_32BIT_SPACE (CPU_TYPE_020 | CPU_TYPE_EC030 | CPU_TYPE_030 | CPU_TYPE_EC040 | CPU_TYPE_040)
+#define MASK_010_OR_LATER (CPU_TYPE_010 | CPU_TYPE_EC020 | CPU_TYPE_020 | CPU_TYPE_030 | CPU_TYPE_EC030 | CPU_TYPE_040 | CPU_TYPE_EC040)
+#define MASK_020_OR_LATER (CPU_TYPE_EC020 | CPU_TYPE_020 | CPU_TYPE_EC030 | CPU_TYPE_030 | CPU_TYPE_EC040 | CPU_TYPE_040)
+#define MASK_030_OR_LATER (CPU_TYPE_030 | CPU_TYPE_EC030 | CPU_TYPE_040 | CPU_TYPE_EC040)
+#define MASK_040_OR_LATER (CPU_TYPE_040 | CPU_TYPE_EC040)
#define M68K_STATE_ENTRY(_name, _format, _member, _datamask, _flags, _mask) \
CPU_STATE_ENTRY(M68K_##_name, #_name, _format, m68ki_cpu_core, _member, _datamask, _mask, _flags)
@@ -484,6 +558,9 @@ INLINE m68ki_cpu_core *get_safe_token(const device_config *device)
cpu_get_type(device) == CPU_M68010 ||
cpu_get_type(device) == CPU_M68EC020 ||
cpu_get_type(device) == CPU_M68020 ||
+ cpu_get_type(device) == CPU_M68EC030 ||
+ cpu_get_type(device) == CPU_M68030 ||
+ cpu_get_type(device) == CPU_M68EC040 ||
cpu_get_type(device) == CPU_M68040 ||
cpu_get_type(device) == CPU_SCC68070);
return (m68ki_cpu_core *)device->token;
@@ -1039,6 +1116,7 @@ static CPU_INIT( m68000 )
m68k->cyc_movem_l = 3;
m68k->cyc_shift = 1;
m68k->cyc_reset = 132;
+ m68k->has_pmmu = 0;
}
CPU_GET_INFO( m68000 )
@@ -1082,6 +1160,7 @@ static CPU_INIT( m68008 )
m68k->cyc_movem_l = 3;
m68k->cyc_shift = 1;
m68k->cyc_reset = 132;
+ m68k->has_pmmu = 0;
}
CPU_GET_INFO( m68008 )
@@ -1129,6 +1208,7 @@ static CPU_INIT( m68010 )
m68k->cyc_movem_l = 3;
m68k->cyc_shift = 1;
m68k->cyc_reset = 130;
+ m68k->has_pmmu = 0;
}
CPU_GET_INFO( m68010 )
@@ -1172,6 +1252,7 @@ static CPU_INIT( m68020 )
m68k->cyc_movem_l = 2;
m68k->cyc_shift = 0;
m68k->cyc_reset = 518;
+ m68k->has_pmmu = 0;
}
CPU_GET_INFO( m68020 )
@@ -1247,6 +1328,7 @@ static CPU_INIT( m68ec020 )
m68k->cyc_movem_l = 2;
m68k->cyc_shift = 0;
m68k->cyc_reset = 518;
+ m68k->has_pmmu = 0;
}
CPU_GET_INFO( m68ec020 )
@@ -1267,6 +1349,125 @@ CPU_GET_INFO( m68ec020 )
}
/****************************************************************************
+ * M68030 section
+ ****************************************************************************/
+
+static CPU_INIT( m68030 )
+{
+ m68ki_cpu_core *m68k = get_safe_token(device);
+
+ CPU_INIT_CALL(m68k);
+
+ m68k->cpu_type = CPU_TYPE_030;
+ m68k->state.subtypemask = m68k->cpu_type;
+ m68k->dasm_type = M68K_CPU_TYPE_68030;
+ m68k->memory = interface_d32;
+ m68k->sr_mask = 0xf71f; /* T1 T0 S M -- I2 I1 I0 -- -- -- X N Z V C */
+ m68k->cyc_instruction = m68ki_cycles[3];
+ m68k->cyc_exception = m68ki_exception_cycle_table[3];
+ m68k->cyc_bcc_notake_b = -2;
+ m68k->cyc_bcc_notake_w = 0;
+ m68k->cyc_dbcc_f_noexp = 0;
+ m68k->cyc_dbcc_f_exp = 4;
+ m68k->cyc_scc_r_true = 0;
+ m68k->cyc_movem_w = 2;
+ m68k->cyc_movem_l = 2;
+ m68k->cyc_shift = 0;
+ m68k->cyc_reset = 518;
+ m68k->has_pmmu = 1;
+}
+
+CPU_GET_INFO( m68030 )
+{
+ m68ki_cpu_core *m68k = (device != NULL && device->token != NULL) ? get_safe_token(device) : NULL;
+ int sr;
+
+ switch (state)
+ {
+ /* --- the following bits of info are returned as 64-bit signed integers --- */
+ case CPUINFO_INT_MAX_INSTRUCTION_BYTES: info->i = 20; break;
+ case CPUINFO_INT_MIN_CYCLES: info->i = 2; break;
+ case CPUINFO_INT_MAX_CYCLES: info->i = 158; break;
+
+ case CPUINFO_INT_DATABUS_WIDTH_PROGRAM: info->i = 32; break;
+ case CPUINFO_INT_ADDRBUS_WIDTH_PROGRAM: info->i = 32; break;
+
+ /* --- the following bits of info are returned as pointers to data or functions --- */
+ case CPUINFO_FCT_INIT: info->init = CPU_INIT_NAME(m68030); break;
+
+ /* --- the following bits of info are returned as NULL-terminated strings --- */
+ case DEVINFO_STR_NAME: strcpy(info->s, "68030"); break;
+
+ case CPUINFO_STR_FLAGS:
+ sr = m68ki_get_sr(m68k);
+ sprintf(info->s, "%c%c%c%c%c%c%c%c%c%c%c%c%c%c%c%c",
+ sr & 0x8000 ? 'T':'.',
+ sr & 0x4000 ? 't':'.',
+ sr & 0x2000 ? 'S':'.',
+ sr & 0x1000 ? 'M':'.',
+ sr & 0x0800 ? '?':'.',
+ sr & 0x0400 ? 'I':'.',
+ sr & 0x0200 ? 'I':'.',
+ sr & 0x0100 ? 'I':'.',
+ sr & 0x0080 ? '?':'.',
+ sr & 0x0040 ? '?':'.',
+ sr & 0x0020 ? '?':'.',
+ sr & 0x0010 ? 'X':'.',
+ sr & 0x0008 ? 'N':'.',
+ sr & 0x0004 ? 'Z':'.',
+ sr & 0x0002 ? 'V':'.',
+ sr & 0x0001 ? 'C':'.');
+ break;
+
+ default: CPU_GET_INFO_CALL(m68k); break;
+ }
+}
+
+
+/****************************************************************************
+ * M680EC30 section
+ ****************************************************************************/
+
+static CPU_INIT( m68ec030 )
+{
+ m68ki_cpu_core *m68k = get_safe_token(device);
+
+ CPU_INIT_CALL(m68k);
+
+ m68k->cpu_type = CPU_TYPE_EC030;
+ m68k->state.subtypemask = m68k->cpu_type;
+ m68k->dasm_type = M68K_CPU_TYPE_68EC030;
+ m68k->memory = interface_d32;
+ m68k->sr_mask = 0xf71f; /* T1 T0 S M -- I2 I1 I0 -- -- -- X N Z V C */
+ m68k->cyc_instruction = m68ki_cycles[3];
+ m68k->cyc_exception = m68ki_exception_cycle_table[3];
+ m68k->cyc_bcc_notake_b = -2;
+ m68k->cyc_bcc_notake_w = 0;
+ m68k->cyc_dbcc_f_noexp = 0;
+ m68k->cyc_dbcc_f_exp = 4;
+ m68k->cyc_scc_r_true = 0;
+ m68k->cyc_movem_w = 2;
+ m68k->cyc_movem_l = 2;
+ m68k->cyc_shift = 0;
+ m68k->cyc_reset = 518;
+ m68k->has_pmmu = 0; /* EC030 lacks the PMMU and is effectively a die-shrink 68020 */
+}
+
+CPU_GET_INFO( m68ec030 )
+{
+ switch (state)
+ {
+ /* --- the following bits of info are returned as pointers to data or functions --- */
+ case CPUINFO_FCT_INIT: info->init = CPU_INIT_NAME(m68ec030); break;
+
+ /* --- the following bits of info are returned as NULL-terminated strings --- */
+ case DEVINFO_STR_NAME: strcpy(info->s, "68EC030"); break;
+
+ default: CPU_GET_INFO_CALL(m68030); break;
+ }
+}
+
+/****************************************************************************
* M68040 section
****************************************************************************/
@@ -1281,8 +1482,8 @@ static CPU_INIT( m68040 )
m68k->dasm_type = M68K_CPU_TYPE_68040;
m68k->memory = interface_d32;
m68k->sr_mask = 0xf71f; /* T1 T0 S M -- I2 I1 I0 -- -- -- X N Z V C */
- m68k->cyc_instruction = m68ki_cycles[2];
- m68k->cyc_exception = m68ki_exception_cycle_table[2];
+ m68k->cyc_instruction = m68ki_cycles[4];
+ m68k->cyc_exception = m68ki_exception_cycle_table[4];
m68k->cyc_bcc_notake_b = -2;
m68k->cyc_bcc_notake_w = 0;
m68k->cyc_dbcc_f_noexp = 0;
@@ -1292,6 +1493,7 @@ static CPU_INIT( m68040 )
m68k->cyc_movem_l = 2;
m68k->cyc_shift = 0;
m68k->cyc_reset = 518;
+ m68k->has_pmmu = 1;
}
CPU_GET_INFO( m68040 )
@@ -1340,6 +1542,48 @@ CPU_GET_INFO( m68040 )
}
}
+/****************************************************************************
+ * M680EC30 section
+ ****************************************************************************/
+
+static CPU_INIT( m68ec040 )
+{
+ m68ki_cpu_core *m68k = get_safe_token(device);
+
+ CPU_INIT_CALL(m68k);
+
+ m68k->cpu_type = CPU_TYPE_EC040;
+ m68k->state.subtypemask = m68k->cpu_type;
+ m68k->dasm_type = M68K_CPU_TYPE_68EC040;
+ m68k->memory = interface_d32;
+ m68k->sr_mask = 0xf71f; /* T1 T0 S M -- I2 I1 I0 -- -- -- X N Z V C */
+ m68k->cyc_instruction = m68ki_cycles[4];
+ m68k->cyc_exception = m68ki_exception_cycle_table[4];
+ m68k->cyc_bcc_notake_b = -2;
+ m68k->cyc_bcc_notake_w = 0;
+ m68k->cyc_dbcc_f_noexp = 0;
+ m68k->cyc_dbcc_f_exp = 4;
+ m68k->cyc_scc_r_true = 0;
+ m68k->cyc_movem_w = 2;
+ m68k->cyc_movem_l = 2;
+ m68k->cyc_shift = 0;
+ m68k->cyc_reset = 518;
+ m68k->has_pmmu = 1;
+}
+
+CPU_GET_INFO( m68ec040 )
+{
+ switch (state)
+ {
+ /* --- the following bits of info are returned as pointers to data or functions --- */
+ case CPUINFO_FCT_INIT: info->init = CPU_INIT_NAME(m68ec040); break;
+
+ /* --- the following bits of info are returned as NULL-terminated strings --- */
+ case DEVINFO_STR_NAME: strcpy(info->s, "68EC040"); break;
+
+ default: CPU_GET_INFO_CALL(m68040); break;
+ }
+}
/****************************************************************************
* SCC-68070 section
@@ -1370,3 +1614,4 @@ CPU_GET_INFO( scc68070 )
default: CPU_GET_INFO_CALL(m68k); break;
}
}
+
diff --git a/src/emu/cpu/m68000/m68kcpu.h b/src/emu/cpu/m68000/m68kcpu.h
index 294d5ed3060..d074569906d 100644
--- a/src/emu/cpu/m68000/m68kcpu.h
+++ b/src/emu/cpu/m68000/m68kcpu.h
@@ -73,14 +73,16 @@ typedef struct _m68ki_cpu_core m68ki_cpu_core;
#define FUNCTION_CODE_CPU_SPACE 7
/* CPU types for deciding what to emulate */
-#define CPU_TYPE_000 1
-#define CPU_TYPE_008 2
-#define CPU_TYPE_010 4
-#define CPU_TYPE_EC020 8
-#define CPU_TYPE_020 16
-#define CPU_TYPE_040 32
-#define CPU_TYPE_060 64
-#define CPU_TYPE_SCC070 128
+#define CPU_TYPE_000 (0x00000001)
+#define CPU_TYPE_008 (0x00000002)
+#define CPU_TYPE_010 (0x00000004)
+#define CPU_TYPE_EC020 (0x00000008)
+#define CPU_TYPE_020 (0x00000010)
+#define CPU_TYPE_EC030 (0x00000020)
+#define CPU_TYPE_030 (0x00000040)
+#define CPU_TYPE_EC040 (0x00000080)
+#define CPU_TYPE_040 (0x00000100)
+#define CPU_TYPE_SCC070 (0x00000200)
/* Different ways to stop the CPU */
#define STOP_LEVEL_STOP 1
@@ -217,20 +219,23 @@ typedef struct _m68ki_cpu_core m68ki_cpu_core;
/* These defines are dependant on the configuration defines in m68kconf.h */
/* Disable certain comparisons if we're not using all CPU types */
-#define CPU_TYPE_IS_040_PLUS(A) ((A) & CPU_TYPE_040)
+#define CPU_TYPE_IS_040_PLUS(A) ((A) & (CPU_TYPE_040 | CPU_TYPE_EC040))
#define CPU_TYPE_IS_040_LESS(A) 1
-#define CPU_TYPE_IS_020_PLUS(A) ((A) & (CPU_TYPE_020 | CPU_TYPE_040))
+#define CPU_TYPE_IS_030_PLUS(A) ((A) & (CPU_TYPE_030 | CPU_TYPE_EC030 | CPU_TYPE_040 | CPU_TYPE_EC040))
+#define CPU_TYPE_IS_030_LESS(A) 1
+
+#define CPU_TYPE_IS_020_PLUS(A) ((A) & (CPU_TYPE_020 | CPU_TYPE_030 | CPU_TYPE_EC030 | CPU_TYPE_040 | CPU_TYPE_EC040))
#define CPU_TYPE_IS_020_LESS(A) 1
#define CPU_TYPE_IS_020_VARIANT(A) ((A) & (CPU_TYPE_EC020 | CPU_TYPE_020))
-#define CPU_TYPE_IS_EC020_PLUS(A) ((A) & (CPU_TYPE_EC020 | CPU_TYPE_020 | CPU_TYPE_040))
+#define CPU_TYPE_IS_EC020_PLUS(A) ((A) & (CPU_TYPE_EC020 | CPU_TYPE_020 | CPU_TYPE_030 | CPU_TYPE_EC030 | CPU_TYPE_040 | CPU_TYPE_EC040))
#define CPU_TYPE_IS_EC020_LESS(A) ((A) & (CPU_TYPE_000 | CPU_TYPE_008 | CPU_TYPE_010 | CPU_TYPE_EC020))
#define CPU_TYPE_IS_010(A) ((A) == CPU_TYPE_010)
-#define CPU_TYPE_IS_010_PLUS(A) ((A) & (CPU_TYPE_010 | CPU_TYPE_EC020 | CPU_TYPE_020 | CPU_TYPE_040))
-#define CPU_TYPE_IS_010_LESS(A) ((A) & (CPU_TYPE_000 | CPU_TYPE_008 | CPU_TYPE_010 | CPU_TYPE_SCC070))
+#define CPU_TYPE_IS_010_PLUS(A) ((A) & (CPU_TYPE_010 | CPU_TYPE_EC020 | CPU_TYPE_020 | CPU_TYPE_EC030 | CPU_TYPE_030 | CPU_TYPE_040 | CPU_TYPE_EC040))
+#define CPU_TYPE_IS_010_LESS(A) ((A) & (CPU_TYPE_000 | CPU_TYPE_008 | CPU_TYPE_010))
#define CPU_TYPE_IS_000(A) ((A) == CPU_TYPE_000 || (A) == CPU_TYPE_008)
@@ -292,7 +297,6 @@ typedef struct _m68ki_cpu_core m68ki_cpu_core;
return m68k->initial_cycles; \
} \
}
-#endif
#define m68ki_check_address_error(m68k, ADDR, WRITE_MODE, FC) \
if((ADDR)&1) \
@@ -302,7 +306,7 @@ typedef struct _m68ki_cpu_core m68ki_cpu_core;
m68k->aerr_fc = FC; \
longjmp(m68k->aerr_trap, 1); \
}
-
+#endif
/* -------------------------- EA / Operand Access ------------------------- */
@@ -543,7 +547,7 @@ struct _m68k_memory_interface
struct _m68ki_cpu_core
{
- UINT32 cpu_type; /* CPU Type: 68000, 68008, 68010, 68EC020, or 68020 */
+ UINT32 cpu_type; /* CPU Type: 68000, 68008, 68010, 68EC020, 68020, 68EC030, 68030, 68EC040, or 68040 */
UINT32 dasm_type; /* disassembly type */
UINT32 dar[16]; /* Data and Address Registers */
UINT32 ppc; /* Previous program counter */
@@ -576,6 +580,7 @@ struct _m68ki_cpu_core
UINT32 sr_mask; /* Implemented status register bits */
UINT32 instr_mode; /* Stores whether we are in instruction mode or group 0/1 exception mode */
UINT32 run_mode; /* Stores whether we are processing a reset, bus error, address error, or something else */
+ int has_pmmu; /* Indicates if a PMMU available (yes on 030, 040, no on EC030) */
/* Clocks required for instructions / exceptions */
UINT32 cyc_bcc_notake_b;
diff --git a/src/emu/cpu/m68000/m68kmake.c b/src/emu/cpu/m68000/m68kmake.c
index d593a526697..ffe26042b50 100644
--- a/src/emu/cpu/m68000/m68kmake.c
+++ b/src/emu/cpu/m68000/m68kmake.c
@@ -3,7 +3,7 @@
/* ======================================================================== */
/*
* MUSASHI
- * Version 3.32
+ * Version 4.10
*
* A portable Motorola M680x0 processor emulation engine.
* Copyright Karl Stenerud. All rights reserved.
@@ -16,12 +16,15 @@
* (Karl Stenerud).
*
* The latest version of this code can be obtained at:
- * http://kstenerud.cjb.net
+ * http://kstenerud.cjb.net or http://mamedev.org/
*/
/*
* Modified For OpenVMS By: Robert Alan Byer
* byer@mail.ourservers.net
+ *
+ * 68030 and PMMU by R. Belmont
+ * 68040 and FPU by Ville Linde
*/
@@ -52,7 +55,7 @@
*/
-static const char g_version[] = "3.32";
+static const char g_version[] = "4.10";
/* ======================================================================== */
/* =============================== INCLUDES =============================== */
@@ -132,6 +135,7 @@ enum
CPU_TYPE_000 = 0,
CPU_TYPE_010,
CPU_TYPE_020,
+ CPU_TYPE_030,
CPU_TYPE_040,
NUM_CPUS
};
@@ -182,7 +186,7 @@ typedef struct
char ea_allowed[EA_ALLOWED_LENGTH]; /* Effective addressing modes allowed */
char cpu_mode[NUM_CPUS]; /* User or supervisor mode */
char cpus[NUM_CPUS+1]; /* Allowed CPUs */
- unsigned char cycles[NUM_CPUS]; /* cycles for 000, 010, 020 */
+ unsigned char cycles[NUM_CPUS]; /* cycles for 000, 010, 020, 030, 040 */
} opcode_struct;
@@ -313,22 +317,22 @@ static const int g_size_select_table[33] =
};
/* Extra cycles required for certain EA modes */
-/* TODO: correct timings for 040 */
+/* TODO: correct timings for 030, 040 */
static const int g_ea_cycle_table[13][NUM_CPUS][3] =
-{/* 000 010 020 040 */
- {{ 0, 0, 0}, { 0, 0, 0}, { 0, 0, 0}, { 0, 0, 0}}, /* EA_MODE_NONE */
- {{ 0, 4, 8}, { 0, 4, 8}, { 0, 4, 4}, { 0, 4, 4}}, /* EA_MODE_AI */
- {{ 0, 4, 8}, { 0, 4, 8}, { 0, 4, 4}, { 0, 4, 4}}, /* EA_MODE_PI */
- {{ 0, 4, 8}, { 0, 4, 8}, { 0, 4, 4}, { 0, 4, 4}}, /* EA_MODE_PI7 */
- {{ 0, 6, 10}, { 0, 6, 10}, { 0, 5, 5}, { 0, 5, 5}}, /* EA_MODE_PD */
- {{ 0, 6, 10}, { 0, 6, 10}, { 0, 5, 5}, { 0, 5, 5}}, /* EA_MODE_PD7 */
- {{ 0, 8, 12}, { 0, 8, 12}, { 0, 5, 5}, { 0, 5, 5}}, /* EA_MODE_DI */
- {{ 0, 10, 14}, { 0, 10, 14}, { 0, 7, 7}, { 0, 7, 7}}, /* EA_MODE_IX */
- {{ 0, 8, 12}, { 0, 8, 12}, { 0, 4, 4}, { 0, 4, 4}}, /* EA_MODE_AW */
- {{ 0, 12, 16}, { 0, 12, 16}, { 0, 4, 4}, { 0, 4, 4}}, /* EA_MODE_AL */
- {{ 0, 8, 12}, { 0, 8, 12}, { 0, 5, 5}, { 0, 5, 5}}, /* EA_MODE_PCDI */
- {{ 0, 10, 14}, { 0, 10, 14}, { 0, 7, 7}, { 0, 7, 7}}, /* EA_MODE_PCIX */
- {{ 0, 4, 8}, { 0, 4, 8}, { 0, 2, 4}, { 0, 2, 4}}, /* EA_MODE_I */
+{/* 000 010 020 030 040 */
+ {{ 0, 0, 0}, { 0, 0, 0}, { 0, 0, 0}, { 0, 0, 0}, { 0, 0, 0}}, /* EA_MODE_NONE */
+ {{ 0, 4, 8}, { 0, 4, 8}, { 0, 4, 4}, { 0, 4, 4}, { 0, 4, 4}}, /* EA_MODE_AI */
+ {{ 0, 4, 8}, { 0, 4, 8}, { 0, 4, 4}, { 0, 4, 4}, { 0, 4, 4}}, /* EA_MODE_PI */
+ {{ 0, 4, 8}, { 0, 4, 8}, { 0, 4, 4}, { 0, 4, 4}, { 0, 4, 4}}, /* EA_MODE_PI7 */
+ {{ 0, 6, 10}, { 0, 6, 10}, { 0, 5, 5}, { 0, 5, 5}, { 0, 5, 5}}, /* EA_MODE_PD */
+ {{ 0, 6, 10}, { 0, 6, 10}, { 0, 5, 5}, { 0, 5, 5}, { 0, 5, 5}}, /* EA_MODE_PD7 */
+ {{ 0, 8, 12}, { 0, 8, 12}, { 0, 5, 5}, { 0, 5, 5}, { 0, 5, 5}}, /* EA_MODE_DI */
+ {{ 0, 10, 14}, { 0, 10, 14}, { 0, 7, 7}, { 0, 7, 7}, { 0, 7, 7}}, /* EA_MODE_IX */
+ {{ 0, 8, 12}, { 0, 8, 12}, { 0, 4, 4}, { 0, 4, 4}, { 0, 4, 4}}, /* EA_MODE_AW */
+ {{ 0, 12, 16}, { 0, 12, 16}, { 0, 4, 4}, { 0, 4, 4}, { 0, 4, 4}}, /* EA_MODE_AL */
+ {{ 0, 8, 12}, { 0, 8, 12}, { 0, 5, 5}, { 0, 5, 5}, { 0, 5, 5}}, /* EA_MODE_PCDI */
+ {{ 0, 10, 14}, { 0, 10, 14}, { 0, 7, 7}, { 0, 7, 7}, { 0, 7, 7}}, /* EA_MODE_PCIX */
+ {{ 0, 4, 8}, { 0, 4, 8}, { 0, 2, 4}, { 0, 2, 4}, { 0, 2, 4}}, /* EA_MODE_I */
};
/* Extra cycles for JMP instruction (000, 010) */
@@ -1073,13 +1077,13 @@ static void populate_table(void)
/* Find the start of the table */
while(strcmp(buff, ID_TABLE_START) != 0)
if(fgetline(buff, MAX_LINE_LENGTH, g_input_file) < 0)
- error_exit("Premature EOF while reading table");
+ error_exit("(table_start) Premature EOF while reading table");
/* Process the entire table */
for(op = g_opcode_input_table;;op++)
{
if(fgetline(buff, MAX_LINE_LENGTH, g_input_file) < 0)
- error_exit("Premature EOF while reading table");
+ error_exit("(inline) Premature EOF while reading table");
if(strlen(buff) == 0)
continue;
/* We finish when we find an input separator */
@@ -1237,7 +1241,7 @@ int main(int argc, char *argv[])
int table_body_read = 0;
int ophandler_body_read = 0;
- printf("\n\tMusashi v%s 68000, 68008, 68010, 68EC020, 68020, 68040 emulator\n", g_version);
+ printf("\n\tMusashi v%s 68000, 68008, 68010, 68EC020, 68020, 68EC030, 68030, 68EC040, 68040 emulator\n", g_version);
printf("\tCopyright Karl Stenerud\n\n");
/* Check if output path and source for the input file are given */