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author R. Belmont <rb6502@users.noreply.github.com>2009-07-17 04:29:37 +0000
committer R. Belmont <rb6502@users.noreply.github.com>2009-07-17 04:29:37 +0000
commit7111f1aece2d556b64312e706e76bd46b4b6091f (patch)
treee6ae83460095e640d6ea5a0d61b2b6fae602f1e4
parent0fa02f401f6e3b2b377f3e3c33b513558a2deeb9 (diff)
ARM7: Add ARMv5+ CLZ instruction
-rw-r--r--src/emu/cpu/arm7/arm7dasm.c4
-rw-r--r--src/emu/cpu/arm7/arm7exec.c9
2 files changed, 13 insertions, 0 deletions
diff --git a/src/emu/cpu/arm7/arm7dasm.c b/src/emu/cpu/arm7/arm7dasm.c
index dbecb52e2fb..15520c8c69d 100644
--- a/src/emu/cpu/arm7/arm7dasm.c
+++ b/src/emu/cpu/arm7/arm7dasm.c
@@ -231,6 +231,10 @@ UINT32 arm7_disasm( char *pBuf, UINT32 pc, UINT32 opcode )
if ((opcode & 0x0f) == 14)
dasmflags = DASMFLAG_STEP_OUT;
}
+ else if ((opcode & 0x0ff000f0) == 0x01600010) // CLZ - v5
+ {
+ pBuf += sprintf(pBuf, "CLZ R%d, R%d", (opcode>>12)&0xf, opcode&0xf);
+ }
else if( (opcode&0x0e000000)==0 && (opcode&0x80) && (opcode&0x10) ) //bits 27-25 == 000, bit 7=1, bit 4=1
{
/* multiply or swap or half word data transfer */
diff --git a/src/emu/cpu/arm7/arm7exec.c b/src/emu/cpu/arm7/arm7exec.c
index 29db2543660..0b023f09f25 100644
--- a/src/emu/cpu/arm7/arm7exec.c
+++ b/src/emu/cpu/arm7/arm7exec.c
@@ -1248,6 +1248,15 @@
R15--;
}
}
+ else if ((insn & 0x0ff000f0) == 0x01600010) // CLZ - v5
+ {
+ UINT32 rm = insn&0xf;
+ UINT32 rd = (insn>>12)&0xf;
+
+ SET_REGISTER(cpustate, rd, count_leading_zeros(GET_REGISTER(cpustate, rm)));
+
+ R15 += 4;
+ }
else
/* Multiply OR Swap OR Half Word Data Transfer */
if ((insn & 0x0e000000) == 0 && (insn & 0x80) && (insn & 0x10)) // bits 27-25=000 bit 7=1 bit 4=1