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author Angelo Salese <angelosa@users.noreply.github.com>2009-06-21 14:54:33 +0000
committer Angelo Salese <angelosa@users.noreply.github.com>2009-06-21 14:54:33 +0000
commitd2d36ebe024ec7bd53e9df4b3e617d3c63dc528c (patch)
tree39d1f8e9265092f936e6c4789df19ca0513275c4
parent38cc1f2cc9e8d87ec27d1d23de6e67bb512469bf (diff)
mc68hc11: Added ROLA, ROLB, SUBD INDX, SUBD INDY, SBCA INDX, SBCA INDY, SBCB INDX, SBCB INDY, added basic hook-up for TEST opcode.
-rw-r--r--src/emu/cpu/mc68hc11/hc11ops.c149
-rw-r--r--src/emu/cpu/mc68hc11/hc11ops.h18
-rw-r--r--src/emu/cpu/mc68hc11/mc68hc11.c2
3 files changed, 159 insertions, 10 deletions
diff --git a/src/emu/cpu/mc68hc11/hc11ops.c b/src/emu/cpu/mc68hc11/hc11ops.c
index 313dcde658f..addae7a4136 100644
--- a/src/emu/cpu/mc68hc11/hc11ops.c
+++ b/src/emu/cpu/mc68hc11/hc11ops.c
@@ -2268,6 +2268,45 @@ static void HC11OP(puly)(hc11_state *cpustate)
CYCLES(cpustate, 6);
}
+/* ROLA 0x49 */
+static void HC11OP(rola)(hc11_state *cpustate)
+{
+ UINT8 c = (REG_A & 0x80);
+ UINT16 r = ((REG_A & 0x7f) << 1) | (cpustate->ccr & CC_C ? 1 : 0);
+ CLEAR_NZVC(cpustate);
+ cpustate->ccr |= (c & 0x80) ? CC_C : 0;
+ REG_A = (UINT16)(r);
+ SET_N8(REG_A);
+ SET_Z8(REG_A);
+
+ if (((cpustate->ccr & CC_N) == CC_N && (cpustate->ccr & CC_C) == 0) ||
+ ((cpustate->ccr & CC_N) == 0 && (cpustate->ccr & CC_C) == CC_C))
+ {
+ cpustate->ccr |= CC_V;
+ }
+
+ CYCLES(cpustate, 2);
+}
+
+/* ROLB 0x59 */
+static void HC11OP(rolb)(hc11_state *cpustate)
+{
+ UINT8 c = (REG_B & 0x80);
+ UINT16 r = (REG_B << 1) | (cpustate->ccr & CC_C ? 1 : 0);
+ CLEAR_NZVC(cpustate);
+ cpustate->ccr |= (c & 0x80) ? CC_C : 0;
+ REG_B = (UINT16)(r);
+ SET_N8(REG_B);
+ SET_Z8(REG_B);
+
+ if (((cpustate->ccr & CC_N) == CC_N && (cpustate->ccr & CC_C) == 0) ||
+ ((cpustate->ccr & CC_N) == 0 && (cpustate->ccr & CC_C) == CC_C))
+ {
+ cpustate->ccr |= CC_V;
+ }
+
+ CYCLES(cpustate, 2);
+}
/* RTS 0x39 */
static void HC11OP(rts)(hc11_state *cpustate)
@@ -2277,6 +2316,74 @@ static void HC11OP(rts)(hc11_state *cpustate)
CYCLES(cpustate, 5);
}
+/* SBCA IND, X 0xA2 */
+static void HC11OP(sbca_indx)(hc11_state *cpustate)
+{
+ int c = (cpustate->ccr & CC_C) ? 1 : 0;
+ UINT8 offset = FETCH(cpustate);
+ UINT8 i = READ8(cpustate, cpustate->ix + offset);
+ UINT16 r = REG_A - i - c;
+ CLEAR_NZVC(cpustate);
+// SET_H(r, i-c, REG_B);
+ SET_N8(r);
+ SET_Z8(r);
+ SET_V_SUB8(r, i-c, REG_A);
+ SET_C8(r);
+ REG_A = (UINT8)r;
+ CYCLES(cpustate, 4);
+}
+
+/* SBCA IND, Y 0x18, 0xA2 */
+static void HC11OP(sbca_indy)(hc11_state *cpustate)
+{
+ int c = (cpustate->ccr & CC_C) ? 1 : 0;
+ UINT8 offset = FETCH(cpustate);
+ UINT8 i = READ8(cpustate, cpustate->iy + offset);
+ UINT16 r = REG_A - i - c;
+ CLEAR_NZVC(cpustate);
+// SET_H(r, i-c, REG_B);
+ SET_N8(r);
+ SET_Z8(r);
+ SET_V_SUB8(r, i-c, REG_A);
+ SET_C8(r);
+ REG_A = (UINT8)r;
+ CYCLES(cpustate, 5);
+}
+
+/* SBCB IND, X 0xE2 */
+static void HC11OP(sbcb_indx)(hc11_state *cpustate)
+{
+ int c = (cpustate->ccr & CC_C) ? 1 : 0;
+ UINT8 offset = FETCH(cpustate);
+ UINT8 i = READ8(cpustate, cpustate->ix + offset);
+ UINT16 r = REG_B - i - c;
+ CLEAR_NZVC(cpustate);
+// SET_H(r, i-c, REG_B);
+ SET_N8(r);
+ SET_Z8(r);
+ SET_V_SUB8(r, i-c, REG_B);
+ SET_C8(r);
+ REG_B = (UINT8)r;
+ CYCLES(cpustate, 4);
+}
+
+/* SBCB IND, Y 0x18, 0xE2 */
+static void HC11OP(sbcb_indy)(hc11_state *cpustate)
+{
+ int c = (cpustate->ccr & CC_C) ? 1 : 0;
+ UINT8 offset = FETCH(cpustate);
+ UINT8 i = READ8(cpustate, cpustate->iy + offset);
+ UINT16 r = REG_B - i - c;
+ CLEAR_NZVC(cpustate);
+// SET_H(r, i-c, REG_B);
+ SET_N8(r);
+ SET_Z8(r);
+ SET_V_SUB8(r, i-c, REG_B);
+ SET_C8(r);
+ REG_B = (UINT8)r;
+ CYCLES(cpustate, 5);
+}
+
/* SEC 0x0D */
static void HC11OP(sec)(hc11_state *cpustate)
{
@@ -2578,6 +2685,36 @@ static void HC11OP(subd_imm)(hc11_state *cpustate)
CYCLES(cpustate, 4);
}
+/* SUBD INDX 0xA3 */
+static void HC11OP(subd_indx)(hc11_state *cpustate)
+{
+ UINT8 offset = FETCH(cpustate);
+ UINT16 i = READ16(cpustate, cpustate->ix + offset);
+ UINT32 r = REG_D - i;
+ CLEAR_NZVC(cpustate);
+ SET_N16(r);
+ SET_Z16(r);
+ SET_V_SUB16(r, i, REG_D);
+ SET_C16(r);
+ REG_D = (UINT16)r;
+ CYCLES(cpustate, 6);
+}
+
+/* SUBD INDY 0x18 0xA3 */
+static void HC11OP(subd_indy)(hc11_state *cpustate)
+{
+ UINT8 offset = FETCH(cpustate);
+ UINT16 i = READ16(cpustate, cpustate->iy + offset);
+ UINT32 r = REG_D - i;
+ CLEAR_NZVC(cpustate);
+ SET_N16(r);
+ SET_Z16(r);
+ SET_V_SUB16(r, i, REG_D);
+ SET_C16(r);
+ REG_D = (UINT16)r;
+ CYCLES(cpustate, 7);
+}
+
/* TAB 0x16 */
static void HC11OP(tab)(hc11_state *cpustate)
{
@@ -2606,6 +2743,18 @@ static void HC11OP(tba)(hc11_state *cpustate)
CYCLES(cpustate, 2);
}
+/* TEST 0x00 */
+static void HC11OP(test)(hc11_state *cpustate)
+{
+// if(cpustate->test_mode)
+ SET_PC(cpustate, cpustate->ppc); // Note: docs says "incremented" but the behaviour makes me think that's actually "decremented".
+// else
+// {
+// TODO: execute an illegal opcode exception here (NMI)
+// }
+
+ CYCLES(cpustate, 1);
+}
/* TPA 0x07 */
static void HC11OP(tpa)(hc11_state *cpustate)
diff --git a/src/emu/cpu/mc68hc11/hc11ops.h b/src/emu/cpu/mc68hc11/hc11ops.h
index bc8cf47ebce..6b6261cc84d 100644
--- a/src/emu/cpu/mc68hc11/hc11ops.h
+++ b/src/emu/cpu/mc68hc11/hc11ops.h
@@ -232,8 +232,8 @@ static const hc11_opcode_list_struct hc11_opcode_list[] =
{ 0, 0x33, HC11OP(pulb) },
{ 0, 0x38, HC11OP(pulx) },
{ 0x18, 0x38, HC11OP(puly) },
-// { 0, 0x49, HC11OP(rola) },
-// { 0, 0x59, HC11OP(rolb) },
+ { 0, 0x49, HC11OP(rola) },
+ { 0, 0x59, HC11OP(rolb) },
// { 0, 0x79, HC11OP(rol_ext) },
// { 0, 0x69, HC11OP(rol_indx) },
// { 0x18, 0x69, HC11OP(rol_indy) },
@@ -248,13 +248,13 @@ static const hc11_opcode_list_struct hc11_opcode_list[] =
// { 0, 0x82, HC11OP(sbca_imm) },
// { 0, 0x92, HC11OP(sbca_dir) },
// { 0, 0xb2, HC11OP(sbca_ext) },
-// { 0, 0xa2, HC11OP(sbca_indx) },
-// { 0x18, 0xa2, HC11OP(sbca_indy) },
+ { 0, 0xa2, HC11OP(sbca_indx) },
+ { 0x18, 0xa2, HC11OP(sbca_indy) },
// { 0, 0xc2, HC11OP(sbcb_imm) },
// { 0, 0xd2, HC11OP(sbcb_dir) },
// { 0, 0xf2, HC11OP(sbcb_ext) },
-// { 0, 0xe2, HC11OP(sbcb_indx) },
-// { 0x18, 0xe2, HC11OP(sbcb_indy) },
+ { 0, 0xe2, HC11OP(sbcb_indx) },
+ { 0x18, 0xe2, HC11OP(sbcb_indy) },
{ 0, 0x0d, HC11OP(sec) },
{ 0, 0x0f, HC11OP(sei) },
{ 0, 0x0b, HC11OP(sev) },
@@ -299,13 +299,13 @@ static const hc11_opcode_list_struct hc11_opcode_list[] =
{ 0, 0x83, HC11OP(subd_imm) },
// { 0, 0x93, HC11OP(subd_dir) },
// { 0, 0xb3, HC11OP(subd_ext) },
-// { 0, 0xa3, HC11OP(subd_indx) },
-// { 0x18, 0xa3, HC11OP(subd_indy) },
+ { 0, 0xa3, HC11OP(subd_indx) },
+ { 0x18, 0xa3, HC11OP(subd_indy) },
// { 0, 0x3f, HC11OP(swi) },
{ 0, 0x16, HC11OP(tab) },
{ 0, 0x06, HC11OP(tap) },
{ 0, 0x17, HC11OP(tba) },
-// { 0, 0x00, HC11OP(test) },
+ { 0, 0x00, HC11OP(test) },
{ 0, 0x07, HC11OP(tpa) },
{ 0, 0x4d, HC11OP(tsta) },
{ 0, 0x5d, HC11OP(tstb) },
diff --git a/src/emu/cpu/mc68hc11/mc68hc11.c b/src/emu/cpu/mc68hc11/mc68hc11.c
index 0e9f6629b98..f2b8cf55735 100644
--- a/src/emu/cpu/mc68hc11/mc68hc11.c
+++ b/src/emu/cpu/mc68hc11/mc68hc11.c
@@ -410,7 +410,7 @@ static CPU_SET_INFO( mc68hc11 )
{
/* --- the following bits of info are set as 64-bit signed integers --- */
case CPUINFO_INT_PC: cpustate->pc = info->i; break;
- case CPUINFO_INT_REGISTER + HC11_PC: cpustate->pc = info->i; break;
+ case CPUINFO_INT_REGISTER + HC11_PC: cpustate->pc = info->i; break;
case CPUINFO_INT_REGISTER + HC11_SP: cpustate->sp = info->i; break;
case CPUINFO_INT_REGISTER + HC11_A: cpustate->d.d8.a = info->i; break;
case CPUINFO_INT_REGISTER + HC11_B: cpustate->d.d8.b = info->i; break;