diff options
author | Aaron Giles <aaron@aarongiles.com> | 2009-12-31 22:03:37 +0000 |
---|---|---|
committer | Aaron Giles <aaron@aarongiles.com> | 2009-12-31 22:03:37 +0000 |
commit | 289a309cd31305cd2763b3a84f5ac58fb5103636 (patch) | |
tree | 4b3ec478e6d4635a1892fb404d30af0b8143abc1 | |
parent | 367c1d7524f4d4f86f0226a2f6621c848d79e511 (diff) |
Cleanups and version bump.mame0136
44 files changed, 2168 insertions, 2168 deletions
diff --git a/src/emu/cpu/drcbex86.c b/src/emu/cpu/drcbex86.c index 3ae1d5d4bc6..dac3280bb19 100644 --- a/src/emu/cpu/drcbex86.c +++ b/src/emu/cpu/drcbex86.c @@ -2897,7 +2897,7 @@ static void emit_rol_r64_p64(drcbe_state *drcbe, x86code **dst, UINT8 reglo, UIN { emit_link skip1, skip2; int tempreg = REG_EAX; -// emit_mov_m32_r32(dst, MBD(REG_ESP, -8), tempreg); // mov [esp-8],ebx +// emit_mov_m32_r32(dst, MBD(REG_ESP, -8), tempreg); // mov [esp-8],ebx emit_mov_r32_p32(drcbe, dst, REG_ECX, param); // mov ecx,param emit_test_r32_imm(dst, REG_ECX, 0x20); // test ecx,0x20 emit_jcc_short_link(dst, COND_Z, &skip1); // jz skip1 @@ -2922,7 +2922,7 @@ static void emit_rol_r64_p64(drcbe_state *drcbe, x86code **dst, UINT8 reglo, UIN emit_shld_r32_r32_cl(dst, reglo, reghi); // shld reglo,reghi,cl if (saveflags) emit_pushf(dst); // pushf emit_shld_r32_r32_cl(dst, reghi, tempreg); // shld reghi,ebx,cl -// emit_mov_r32_m32(dst, tempreg, MBD(REG_ESP, saveflags ? -4 : -8)); // mov ebx,[esp-8] +// emit_mov_r32_m32(dst, tempreg, MBD(REG_ESP, saveflags ? -4 : -8)); // mov ebx,[esp-8] } if (saveflags) emit_combine_z_flags(dst); @@ -2972,7 +2972,7 @@ static void emit_ror_r64_p64(drcbe_state *drcbe, x86code **dst, UINT8 reglo, UIN { emit_link skip1, skip2; int tempreg = REG_EAX; -// emit_mov_m32_r32(dst, MBD(REG_ESP, -8), tempreg); // mov [esp-8],ebx +// emit_mov_m32_r32(dst, MBD(REG_ESP, -8), tempreg); // mov [esp-8],ebx emit_mov_r32_p32(drcbe, dst, REG_ECX, param); // mov ecx,param emit_test_r32_imm(dst, REG_ECX, 0x20); // test ecx,0x20 emit_jcc_short_link(dst, COND_Z, &skip1); // jz skip1 @@ -2997,7 +2997,7 @@ static void emit_ror_r64_p64(drcbe_state *drcbe, x86code **dst, UINT8 reglo, UIN emit_shrd_r32_r32_cl(dst, reglo, reghi); // shrd reglo,reghi,cl if (saveflags) emit_pushf(dst); // pushf emit_shrd_r32_r32_cl(dst, reghi, tempreg); // shrd reghi,ebx,cl -// emit_mov_r32_m32(dst, tempreg, MBD(REG_ESP, saveflags ? -4 : -8)); // mov ebx,[esp-8] +// emit_mov_r32_m32(dst, tempreg, MBD(REG_ESP, saveflags ? -4 : -8)); // mov ebx,[esp-8] } if (saveflags) emit_combine_z_flags(dst); diff --git a/src/emu/cpu/i86/i86.c b/src/emu/cpu/i86/i86.c index 55d36f6882b..89d98c1e51d 100644 --- a/src/emu/cpu/i86/i86.c +++ b/src/emu/cpu/i86/i86.c @@ -185,7 +185,7 @@ static void i8086_state_register(const device_config *device) state_save_register_device_item(device, 0, cpustate->nmi_state); state_save_register_device_item(device, 0, cpustate->irq_state); state_save_register_device_item(device, 0, cpustate->extra_cycles); - state_save_register_device_item(device, 0, cpustate->halted); + state_save_register_device_item(device, 0, cpustate->halted); state_save_register_device_item(device, 0, cpustate->test_state); /* PJB 03/05 */ state_save_register_device_item(device, 0, cpustate->rep_in_progress); /* PJB 03/05 */ } diff --git a/src/emu/cpu/rsp/rsp.h b/src/emu/cpu/rsp/rsp.h index 58084cc55d1..a9a71d32141 100644 --- a/src/emu/cpu/rsp/rsp.h +++ b/src/emu/cpu/rsp/rsp.h @@ -113,10 +113,10 @@ void rspdrc_add_dmem(const device_config *device, void *base); #define FSREG ((op >> 11) & 31) #define FDREG ((op >> 6) & 31) -#define IS_SINGLE(o) (((o) & (1 << 21)) == 0) -#define IS_DOUBLE(o) (((o) & (1 << 21)) != 0) +#define IS_SINGLE(o) (((o) & (1 << 21)) == 0) +#define IS_DOUBLE(o) (((o) & (1 << 21)) != 0) #define IS_FLOAT(o) (((o) & (1 << 23)) == 0) -#define IS_INTEGRAL(o) (((o) & (1 << 23)) != 0) +#define IS_INTEGRAL(o) (((o) & (1 << 23)) != 0) #define SIMMVAL ((INT16)op) #define UIMMVAL ((UINT16)op) diff --git a/src/emu/cpu/rsp/rspdrc.c b/src/emu/cpu/rsp/rspdrc.c index b6066902fc0..51a7143a4dc 100644 --- a/src/emu/cpu/rsp/rspdrc.c +++ b/src/emu/cpu/rsp/rspdrc.c @@ -2,8 +2,8 @@ rspdrc.c - Universal machine language-based Nintendo/SGI RSP emulator. - Written by Harmony of the MESS team. + Universal machine language-based Nintendo/SGI RSP emulator. + Written by Harmony of the MESS team. Copyright the MESS team. Released for general non-commercial use under the MAME license @@ -550,9 +550,9 @@ void rspdrc_add_dmem(const device_config *device, void *base) //static void cfunc_printf_debug(void *param) //{ -// rsp_state *rsp = (rsp_state *)param; -// printf(rsp->impstate->format, rsp->impstate->arg0, rsp->impstate->arg1); -// logerror(rsp->impstate->format, rsp->impstate->arg0, rsp->impstate->arg1); +// rsp_state *rsp = (rsp_state *)param; +// printf(rsp->impstate->format, rsp->impstate->arg0, rsp->impstate->arg1); +// logerror(rsp->impstate->format, rsp->impstate->arg0, rsp->impstate->arg1); //} @@ -563,9 +563,9 @@ void rspdrc_add_dmem(const device_config *device, void *base) //static void cfunc_printf_debug64(void *param) //{ -// rsp_state *rsp = (rsp_state *)param; -// printf(rsp->impstate->format, (UINT32)(rsp->impstate->arg64 >> 32), (UINT32)(rsp->impstate->arg64 & 0x00000000ffffffff)); -// logerror(rsp->impstate->format, (UINT32)(rsp->impstate->arg64 >> 32), (UINT32)(rsp->impstate->arg64 & 0x00000000ffffffff)); +// rsp_state *rsp = (rsp_state *)param; +// printf(rsp->impstate->format, (UINT32)(rsp->impstate->arg64 >> 32), (UINT32)(rsp->impstate->arg64 & 0x00000000ffffffff)); +// logerror(rsp->impstate->format, (UINT32)(rsp->impstate->arg64 >> 32), (UINT32)(rsp->impstate->arg64 & 0x00000000ffffffff)); //} @@ -1455,13 +1455,13 @@ static int generate_lwc2(rsp_state *rsp, drcuml_block *block, compiler_state *co case 0x07: /* LUV */ #if (DRC_LUV) /* - ea = (base) ? rsp->r[base] + (offset * 8) : (offset * 8); + ea = (base) ? rsp->r[base] + (offset * 8) : (offset * 8); - for (i=0; i < 8; i++) - { - W_VREG_S(dest, i, READ8(rsp, ea + (((16-index) + i) & 0xf)) << 7); - } - */ + for (i=0; i < 8; i++) + { + W_VREG_S(dest, i, READ8(rsp, ea + (((16-index) + i) & 0xf)) << 7); + } + */ offset <<= 3; UML_ADD(block, IREG(2), R32(RSREG), IMM(offset)); // add i2,<rsreg>,offset @@ -2118,24 +2118,24 @@ static int generate_swc2(rsp_state *rsp, drcuml_block *block, compiler_state *co static void generate_saturate_accum_unsigned(rsp_state *rsp, drcuml_block *block, compiler_state *compiler, const opcode_desc *desc, int accum) { /* - int skip, skip2; - - UML_CMP(block, VACCUMWMH(accum), IMM(-32768)); - UML_JMPc(block, IF_GE, skip = compiler->labelnum++); - UML_MOV(block, IREG(0), IMM(0)); - UML_JMP(block, skip2 = compiler->labelnum++); - - UML_LABEL(block, skip); - UML_CMP(block, VACCUMWMH(accum), IMM(32767)); - UML_JMPc(block, IF_L, skip = compiler->labelnum++); - UML_MOV(block, IREG(0), IMM(0x0000ffff)); - UML_JMP(block, skip2); - - UML_LABEL(block, skip); - UML_SEXT(block, IREG(0), VACCUMHL(accum), WORD); - UML_AND(block, IREG(0), IREG(0), IMM(0x0000ffff)); - UML_LABEL(block, skip2); - */ + int skip, skip2; + + UML_CMP(block, VACCUMWMH(accum), IMM(-32768)); + UML_JMPc(block, IF_GE, skip = compiler->labelnum++); + UML_MOV(block, IREG(0), IMM(0)); + UML_JMP(block, skip2 = compiler->labelnum++); + + UML_LABEL(block, skip); + UML_CMP(block, VACCUMWMH(accum), IMM(32767)); + UML_JMPc(block, IF_L, skip = compiler->labelnum++); + UML_MOV(block, IREG(0), IMM(0x0000ffff)); + UML_JMP(block, skip2); + + UML_LABEL(block, skip); + UML_SEXT(block, IREG(0), VACCUMHL(accum), WORD); + UML_AND(block, IREG(0), IREG(0), IMM(0x0000ffff)); + UML_LABEL(block, skip2); + */ UML_SEXT(block, IREG(0), VACCUMHL(accum), WORD); UML_AND(block, IREG(0), IREG(0), IMM(0x0000ffff)); UML_CMP(block, VACCUMWMH(accum), IMM(-32768)); @@ -2197,7 +2197,7 @@ INLINE UINT16 SATURATE_ACCUM_SIGNED(rsp_state *rsp, int accum) return ACCUM(accum).h.mid; } -#define WRITEBACK_RESULT() \ +#define WRITEBACK_RESULT() \ do { \ W_VREG_S_X(VDREG, 7, vres[0]); \ W_VREG_S_X(VDREG, 6, vres[1]); \ @@ -2271,54 +2271,54 @@ INLINE void cfunc_rsp_vmulf(void *param) switch(EL) { - case 0: /* 0, 1, 2, 3, 4, 5, 6, 7 - none */ /* 0, 1, 2, 3, 4, 5, 6, 7 - none */ - RSP_VMULF(0, 1, 2, 3, 4, 5, 6, 7, 7, 6, 5, 4, 3, 2, 1, 0, 7, 6, 5, 4, 3, 2, 1, 0); - break; - case 1: /* 0, 1, 2, 3, 4, 5, 6, 7 - ??? */ /* 0, 1, 2, 3, 4, 5, 6, 7 - ??? */ - RSP_VMULF(0, 1, 2, 3, 4, 5, 6, 7, 7, 6, 5, 4, 3, 2, 1, 0, 7, 6, 5, 4, 3, 2, 1, 0); - break; - case 2: /* 1, 3, 5, 7, 0, 2, 4, 6 - 0q */ /* 0, 0, 2, 2, 4, 4, 6, 6 - 0q */ - RSP_VMULF(1, 3, 5, 7, 0, 2, 4, 6, 7, 5, 3, 1, 7, 5, 3, 1, 6, 4, 2, 0, 7, 5, 3, 1); - break; - case 3: /* 0, 2, 4, 6, 1, 3, 5, 7 - 1q */ /* 1, 1, 3, 3, 5, 5, 7, 7 - 1q */ - RSP_VMULF(0, 2, 4, 6, 1, 3, 5, 7, 6, 4, 2, 0, 6, 4, 2, 0, 7, 5, 3, 1, 6, 4, 2, 0); - break; - case 4: /* 1, 2, 3, 5, 6, 7, 0, 4 - 0h */ /* 0, 0, 0, 0, 4, 4, 4, 4 - 0h */ - RSP_VMULF(1, 2, 3, 5, 6, 7, 0, 4, 7, 7, 7, 3, 3, 3, 7, 3, 6, 5, 4, 2, 1, 0, 7, 3); - break; - case 5: /* 0, 2, 3, 4, 6, 7, 1, 5 - 1h */ /* 1, 1, 1, 1, 5, 5, 5, 5 - 1h */ - RSP_VMULF(0, 2, 3, 4, 6, 7, 1, 5, 6, 6, 6, 2, 2, 2, 6, 2, 7, 5, 4, 3, 1, 0, 6, 2); - break; - case 6: /* 0, 1, 3, 4, 5, 7, 2, 6 - 2h */ /* 2, 2, 2, 2, 6, 6, 6, 6 - 2h */ - RSP_VMULF(0, 1, 3, 4, 5, 7, 2, 6, 5, 5, 5, 1, 1, 1, 5, 1, 7, 6, 4, 3, 2, 0, 5, 1); - break; - case 7: /* 0, 1, 2, 4, 5, 6, 3, 7 - 3h */ /* 3, 3, 3, 3, 7, 7, 7, 7 - 3h */ - RSP_VMULF(0, 1, 2, 4, 5, 6, 3, 7, 4, 4, 4, 0, 0, 0, 4, 0, 7, 6, 5, 3, 2, 1, 4, 0); - break; - case 8: /* 1, 2, 3, 4, 5, 6, 7, 0 - 0 */ /* 0, 0, 0, 0, 0, 0, 0, 0 - 0 */ - RSP_VMULF(1, 2, 3, 4, 5, 6, 7, 0, 7, 7, 7, 7, 7, 7, 7, 7, 6, 5, 4, 3, 2, 1, 0, 7); - break; - case 9: /* 0, 2, 3, 4, 5, 6, 7, 1 - 1 */ /* 1, 1, 1, 1, 1, 1, 1, 1 - 0 */ - RSP_VMULF(0, 2, 3, 4, 5, 6, 7, 1, 6, 6, 6, 6, 6, 6, 6, 6, 7, 5, 4, 3, 2, 1, 0, 6); - break; - case 10: /* 0, 1, 3, 4, 5, 6, 7, 2 - 2 */ /* 2, 2, 2, 2, 2, 2, 2, 2 - 0 */ - RSP_VMULF(0, 1, 3, 4, 5, 6, 7, 2, 5, 5, 5, 5, 5, 5, 5, 5, 7, 6, 4, 3, 2, 1, 0, 5); - break; - case 11: /* 0, 1, 2, 4, 5, 6, 7, 3 - 3 */ /* 3, 3, 3, 3, 3, 3, 3, 3 - 0 */ - RSP_VMULF(0, 1, 2, 4, 5, 6, 7, 3, 4, 4, 4, 4, 4, 4, 4, 4, 7, 6, 5, 3, 2, 1, 0, 4); - break; - case 12: /* 0, 1, 2, 3, 5, 6, 7, 4 - 4 */ /* 4, 4, 4, 4, 4, 4, 4, 4 - 0 */ - RSP_VMULF(0, 1, 2, 3, 5, 6, 7, 4, 3, 3, 3, 3, 3, 3, 3, 3, 7, 6, 5, 4, 2, 1, 0, 3); - break; - case 13: /* 0, 1, 2, 3, 4, 6, 7, 5 - 5 */ /* 5, 5, 5, 5, 5, 5, 5, 5 - 0 */ - RSP_VMULF(0, 1, 2, 3, 4, 6, 7, 5, 2, 2, 2, 2, 2, 2, 2, 2, 7, 6, 5, 4, 3, 1, 0, 2); - break; - case 14: /* 0, 1, 2, 3, 4, 5, 7, 6 - 6 */ /* 6, 6, 6, 6, 6, 6, 6, 6 - 0 */ - RSP_VMULF(0, 1, 2, 3, 4, 5, 7, 6, 1, 1, 1, 1, 1, 1, 1, 1, 7, 6, 5, 4, 3, 2, 0, 1); - break; - case 15: /* 0, 1, 2, 3, 4, 5, 6, 7 - 7 */ /* 7, 7, 7, 7, 7, 7, 7, 7 - 0 */ - RSP_VMULF(0, 1, 2, 3, 4, 5, 6, 7, 0, 0, 0, 0, 0, 0, 0, 0, 7, 6, 5, 4, 3, 2, 1, 0); - break; + case 0: /* 0, 1, 2, 3, 4, 5, 6, 7 - none */ /* 0, 1, 2, 3, 4, 5, 6, 7 - none */ + RSP_VMULF(0, 1, 2, 3, 4, 5, 6, 7, 7, 6, 5, 4, 3, 2, 1, 0, 7, 6, 5, 4, 3, 2, 1, 0); + break; + case 1: /* 0, 1, 2, 3, 4, 5, 6, 7 - ??? */ /* 0, 1, 2, 3, 4, 5, 6, 7 - ??? */ + RSP_VMULF(0, 1, 2, 3, 4, 5, 6, 7, 7, 6, 5, 4, 3, 2, 1, 0, 7, 6, 5, 4, 3, 2, 1, 0); + break; + case 2: /* 1, 3, 5, 7, 0, 2, 4, 6 - 0q */ /* 0, 0, 2, 2, 4, 4, 6, 6 - 0q */ + RSP_VMULF(1, 3, 5, 7, 0, 2, 4, 6, 7, 5, 3, 1, 7, 5, 3, 1, 6, 4, 2, 0, 7, 5, 3, 1); + break; + case 3: /* 0, 2, 4, 6, 1, 3, 5, 7 - 1q */ /* 1, 1, 3, 3, 5, 5, 7, 7 - 1q */ + RSP_VMULF(0, 2, 4, 6, 1, 3, 5, 7, 6, 4, 2, 0, 6, 4, 2, 0, 7, 5, 3, 1, 6, 4, 2, 0); + break; + case 4: /* 1, 2, 3, 5, 6, 7, 0, 4 - 0h */ /* 0, 0, 0, 0, 4, 4, 4, 4 - 0h */ + RSP_VMULF(1, 2, 3, 5, 6, 7, 0, 4, 7, 7, 7, 3, 3, 3, 7, 3, 6, 5, 4, 2, 1, 0, 7, 3); + break; + case 5: /* 0, 2, 3, 4, 6, 7, 1, 5 - 1h */ /* 1, 1, 1, 1, 5, 5, 5, 5 - 1h */ + RSP_VMULF(0, 2, 3, 4, 6, 7, 1, 5, 6, 6, 6, 2, 2, 2, 6, 2, 7, 5, 4, 3, 1, 0, 6, 2); + break; + case 6: /* 0, 1, 3, 4, 5, 7, 2, 6 - 2h */ /* 2, 2, 2, 2, 6, 6, 6, 6 - 2h */ + RSP_VMULF(0, 1, 3, 4, 5, 7, 2, 6, 5, 5, 5, 1, 1, 1, 5, 1, 7, 6, 4, 3, 2, 0, 5, 1); + break; + case 7: /* 0, 1, 2, 4, 5, 6, 3, 7 - 3h */ /* 3, 3, 3, 3, 7, 7, 7, 7 - 3h */ + RSP_VMULF(0, 1, 2, 4, 5, 6, 3, 7, 4, 4, 4, 0, 0, 0, 4, 0, 7, 6, 5, 3, 2, 1, 4, 0); + break; + case 8: /* 1, 2, 3, 4, 5, 6, 7, 0 - 0 */ /* 0, 0, 0, 0, 0, 0, 0, 0 - 0 */ + RSP_VMULF(1, 2, 3, 4, 5, 6, 7, 0, 7, 7, 7, 7, 7, 7, 7, 7, 6, 5, 4, 3, 2, 1, 0, 7); + break; + case 9: /* 0, 2, 3, 4, 5, 6, 7, 1 - 1 */ /* 1, 1, 1, 1, 1, 1, 1, 1 - 0 */ + RSP_VMULF(0, 2, 3, 4, 5, 6, 7, 1, 6, 6, 6, 6, 6, 6, 6, 6, 7, 5, 4, 3, 2, 1, 0, 6); + break; + case 10: /* 0, 1, 3, 4, 5, 6, 7, 2 - 2 */ /* 2, 2, 2, 2, 2, 2, 2, 2 - 0 */ + RSP_VMULF(0, 1, 3, 4, 5, 6, 7, 2, 5, 5, 5, 5, 5, 5, 5, 5, 7, 6, 4, 3, 2, 1, 0, 5); + break; + case 11: /* 0, 1, 2, 4, 5, 6, 7, 3 - 3 */ /* 3, 3, 3, 3, 3, 3, 3, 3 - 0 */ + RSP_VMULF(0, 1, 2, 4, 5, 6, 7, 3, 4, 4, 4, 4, 4, 4, 4, 4, 7, 6, 5, 3, 2, 1, 0, 4); + break; + case 12: /* 0, 1, 2, 3, 5, 6, 7, 4 - 4 */ /* 4, 4, 4, 4, 4, 4, 4, 4 - 0 */ + RSP_VMULF(0, 1, 2, 3, 5, 6, 7, 4, 3, 3, 3, 3, 3, 3, 3, 3, 7, 6, 5, 4, 2, 1, 0, 3); + break; + case 13: /* 0, 1, 2, 3, 4, 6, 7, 5 - 5 */ /* 5, 5, 5, 5, 5, 5, 5, 5 - 0 */ + RSP_VMULF(0, 1, 2, 3, 4, 6, 7, 5, 2, 2, 2, 2, 2, 2, 2, 2, 7, 6, 5, 4, 3, 1, 0, 2); + break; + case 14: /* 0, 1, 2, 3, 4, 5, 7, 6 - 6 */ /* 6, 6, 6, 6, 6, 6, 6, 6 - 0 */ + RSP_VMULF(0, 1, 2, 3, 4, 5, 7, 6, 1, 1, 1, 1, 1, 1, 1, 1, 7, 6, 5, 4, 3, 2, 0, 1); + break; + case 15: /* 0, 1, 2, 3, 4, 5, 6, 7 - 7 */ /* 7, 7, 7, 7, 7, 7, 7, 7 - 0 */ + RSP_VMULF(0, 1, 2, 3, 4, 5, 6, 7, 0, 0, 0, 0, 0, 0, 0, 0, 7, 6, 5, 4, 3, 2, 1, 0); + break; } WRITEBACK_RESULT(); @@ -2371,86 +2371,86 @@ INLINE void cfunc_rsp_vmulu(void *param) #define RSP_VMUDL_DRC(E10, E11, E12, E13, E14, E15, E16, E17, E20, E21, E22, E23, E24, E25, E26, E27, I0, I1, I2, I3, I4, I5, I6, I7) \ { \ - UML_SEXT(block, IREG(1), VS(VS1REG, I0), WORD); \ - UML_SEXT(block, IREG(0), VS(VS2REG, E20), WORD); \ - UML_AND(block, IREG(0), IREG(0), IMM(0x0000ffff)); \ - UML_AND(block, IREG(1), IREG(1), IMM(0x0000ffff)); \ + UML_SEXT(block, IREG(1), VS(VS1REG, I0), WORD); \ + UML_SEXT(block, IREG(0), VS(VS2REG, E20), WORD); \ + UML_AND(block, IREG(0), IREG(0), IMM(0x0000ffff)); \ + UML_AND(block, IREG(1), IREG(1), IMM(0x0000ffff)); \ UML_MULS(block, IREG(0), IREG(1), IREG(0), IREG(1)); \ UML_DAND(block, IREG(0), IREG(0), IMM(0x00000000ffff0000)); \ UML_DMOV(block, VACCUML(E10), IREG(0)); \ \ - UML_SEXT(block, IREG(1), VS(VS1REG, I1), WORD); \ - UML_SEXT(block, IREG(0), VS(VS2REG, E21), WORD); \ - UML_AND(block, IREG(0), IREG(0), IMM(0x0000ffff)); \ - UML_AND(block, IREG(1), IREG(1), IMM(0x0000ffff)); \ + UML_SEXT(block, IREG(1), VS(VS1REG, I1), WORD); \ + UML_SEXT(block, IREG(0), VS(VS2REG, E21), WORD); \ + UML_AND(block, IREG(0), IREG(0), IMM(0x0000ffff)); \ + UML_AND(block, IREG(1), IREG(1), IMM(0x0000ffff)); \ UML_MULS(block, IREG(0), IREG(1), IREG(0), IREG(1)); \ UML_DAND(block, IREG(0), IREG(0), IMM(0x00000000ffff0000)); \ UML_DMOV(block, VACCUML(E11), IREG(0)); \ \ - UML_SEXT(block, IREG(1), VS(VS1REG, I2), WORD); \ - UML_SEXT(block, IREG(0), VS(VS2REG, E22), WORD); \ - UML_AND(block, IREG(0), IREG(0), IMM(0x0000ffff)); \ - UML_AND(block, IREG(1), IREG(1), IMM(0x0000ffff)); \ + UML_SEXT(block, IREG(1), VS(VS1REG, I2), WORD); \ + UML_SEXT(block, IREG(0), VS(VS2REG, E22), WORD); \ + UML_AND(block, IREG(0), IREG(0), IMM(0x0000ffff)); \ + UML_AND(block, IREG(1), IREG(1), IMM(0x0000ffff)); \ UML_MULS(block, IREG(0), IREG(1), IREG(0), IREG(1)); \ UML_DAND(block, IREG(0), IREG(0), IMM(0x00000000ffff0000)); \ UML_DMOV(block, VACCUML(E12), IREG(0)); \ \ - UML_SEXT(block, IREG(1), VS(VS1REG, I3), WORD); \ - UML_SEXT(block, IREG(0), VS(VS2REG, E23), WORD); \ - UML_AND(block, IREG(0), IREG(0), IMM(0x0000ffff)); \ - UML_AND(block, IREG(1), IREG(1), IMM(0x0000ffff)); \ + UML_SEXT(block, IREG(1), VS(VS1REG, I3), WORD); \ + UML_SEXT(block, IREG(0), VS(VS2REG, E23), WORD); \ + UML_AND(block, IREG(0), IREG(0), IMM(0x0000ffff)); \ + UML_AND(block, IREG(1), IREG(1), IMM(0x0000ffff)); \ UML_MULS(block, IREG(0), IREG(1), IREG(0), IREG(1)); \ UML_DAND(block, IREG(0), IREG(0), IMM(0x00000000ffff0000)); \ UML_DMOV(block, VACCUML(E13), IREG(0)); \ \ - UML_SEXT(block, IREG(1), VS(VS1REG, I4), WORD); \ - UML_SEXT(block, IREG(0), VS(VS2REG, E24), WORD); \ - UML_AND(block, IREG(0), IREG(0), IMM(0x0000ffff)); \ - UML_AND(block, IREG(1), IREG(1), IMM(0x0000ffff)); \ + UML_SEXT(block, IREG(1), VS(VS1REG, I4), WORD); \ + UML_SEXT(block, IREG(0), VS(VS2REG, E24), WORD); \ + UML_AND(block, IREG(0), IREG(0), IMM(0x0000ffff)); \ + UML_AND(block, IREG(1), IREG(1), IMM(0x0000ffff)); \ UML_MULS(block, IREG(0), IREG(1), IREG(0), IREG(1)); \ UML_DAND(block, IREG(0), IREG(0), IMM(0x00000000ffff0000)); \ UML_DMOV(block, VACCUML(E14), IREG(0)); \ \ - UML_SEXT(block, IREG(1), VS(VS1REG, I5), WORD); \ - UML_SEXT(block, IREG(0), VS(VS2REG, E25), WORD); \ - UML_AND(block, IREG(0), IREG(0), IMM(0x0000ffff)); \ - UML_AND(block, IREG(1), IREG(1), IMM(0x0000ffff)); \ + UML_SEXT(block, IREG(1), VS(VS1REG, I5), WORD); \ + UML_SEXT(block, IREG(0), VS(VS2REG, E25), WORD); \ + UML_AND(block, IREG(0), IREG(0), IMM(0x0000ffff)); \ + UML_AND(block, IREG(1), IREG(1), IMM(0x0000ffff)); \ UML_MULS(block, IREG(0), IREG(1), IREG(0), IREG(1)); \ UML_DAND(block, IREG(0), IREG(0), IMM(0x00000000ffff0000)); \ UML_DMOV(block, VACCUML(E15), IREG(0)); \ \ - UML_SEXT(block, IREG(1), VS(VS1REG, I6), WORD); \ - UML_SEXT(block, IREG(0), VS(VS2REG, E26), WORD); \ - UML_AND(block, IREG(0), IREG(0), IMM(0x0000ffff)); \ - UML_AND(block, IREG(1), IREG(1), IMM(0x0000ffff)); \ + UML_SEXT(block, IREG(1), VS(VS1REG, I6), WORD); \ + UML_SEXT(block, IREG(0), VS(VS2REG, E26), WORD); \ + UML_AND(block, IREG(0), IREG(0), IMM(0x0000ffff)); \ + UML_AND(block, IREG(1), IREG(1), IMM(0x0000ffff)); \ UML_MULS(block, IREG(0), IREG(1), IREG(0), IREG(1)); \ UML_DAND(block, IREG(0), IREG(0), IMM(0x00000000ffff0000)); \ UML_DMOV(block, VACCUML(E16), IREG(0)); \ \ - UML_SEXT(block, IREG(1), VS(VS1REG, I7), WORD); \ - UML_SEXT(block, IREG(0), VS(VS2REG, E27), WORD); \ - UML_AND(block, IREG(0), IREG(0), IMM(0x0000ffff)); \ - UML_AND(block, IREG(1), IREG(1), IMM(0x0000ffff)); \ + UML_SEXT(block, IREG(1), VS(VS1REG, I7), WORD); \ + UML_SEXT(block, IREG(0), VS(VS2REG, E27), WORD); \ + UML_AND(block, IREG(0), IREG(0), IMM(0x0000ffff)); \ + UML_AND(block, IREG(1), IREG(1), IMM(0x0000ffff)); \ UML_MULS(block, IREG(0), IREG(1), IREG(0), IREG(1)); \ UML_DAND(block, IREG(0), IREG(0), IMM(0x00000000ffff0000)); \ UML_DMOV(block, VACCUML(E17), IREG(0)); \ \ - UML_SEXT(block, IREG(0), VACCUMHL(E10), WORD); \ - UML_STORE(block, &rsp->v[VDREG].s[I0], IMM(0), IREG(0), WORD); \ - UML_SEXT(block, IREG(0), VACCUMHL(E11), WORD); \ - UML_STORE(block, &rsp->v[VDREG].s[I1], IMM(0), IREG(0), WORD); \ - UML_SEXT(block, IREG(0), VACCUMHL(E12), WORD); \ - UML_STORE(block, &rsp->v[VDREG].s[I2], IMM(0), IREG(0), WORD); \ - UML_SEXT(block, IREG(0), VACCUMHL(E13), WORD); \ - UML_STORE(block, &rsp->v[VDREG].s[I3], IMM(0), IREG(0), WORD); \ - UML_SEXT(block, IREG(0), VACCUMHL(E14), WORD); \ - UML_STORE(block, &rsp->v[VDREG].s[I4], IMM(0), IREG(0), WORD); \ - UML_SEXT(block, IREG(0), VACCUMHL(E15), WORD); \ - UML_STORE(block, &rsp->v[VDREG].s[I5], IMM(0), IREG(0), WORD); \ - UML_SEXT(block, IREG(0), VACCUMHL(E16), WORD); \ - UML_STORE(block, &rsp->v[VDREG].s[I6], IMM(0), IREG(0), WORD); \ - UML_SEXT(block, IREG(0), VACCUMHL(E17), WORD); \ - UML_STORE(block, &rsp->v[VDREG].s[I7], IMM(0), IREG(0), WORD); \ + UML_SEXT(block, IREG(0), VACCUMHL(E10), WORD); \ + UML_STORE(block, &rsp->v[VDREG].s[I0], IMM(0), IREG(0), WORD); \ + UML_SEXT(block, IREG(0), VACCUMHL(E11), WORD); \ + UML_STORE(block, &rsp->v[VDREG].s[I1], IMM(0), IREG(0), WORD); \ + UML_SEXT(block, IREG(0), VACCUMHL(E12), WORD); \ + UML_STORE(block, &rsp->v[VDREG].s[I2], IMM(0), IREG(0), WORD); \ + UML_SEXT(block, IREG(0), VACCUMHL(E13), WORD); \ + UML_STORE(block, &rsp->v[VDREG].s[I3], IMM(0), IREG(0), WORD); \ + UML_SEXT(block, IREG(0), VACCUMHL(E14), WORD); \ + UML_STORE(block, &rsp->v[VDREG].s[I4], IMM(0), IREG(0), WORD); \ + UML_SEXT(block, IREG(0), VACCUMHL(E15), WORD); \ + UML_STORE(block, &rsp->v[VDREG].s[I5], IMM(0), IREG(0), WORD); \ + UML_SEXT(block, IREG(0), VACCUMHL(E16), WORD); \ + UML_STORE(block, &rsp->v[VDREG].s[I6], IMM(0), IREG(0), WORD); \ + UML_SEXT(block, IREG(0), VACCUMHL(E17), WORD); \ + UML_STORE(block, &rsp->v[VDREG].s[I7], IMM(0), IREG(0), WORD); \ } static int generate_vmudl(rsp_state *rsp, drcuml_block *block, compiler_state *compiler, const opcode_desc *desc) // vmudl @@ -2467,54 +2467,54 @@ static int generate_vmudl(rsp_state *rsp, drcuml_block *block, compiler_state *c // The middle slice of accumulator is stored into destination element switch(EL) { - case 0: /* 0, 1, 2, 3, 4, 5, 6, 7 - none */ /* 0, 1, 2, 3, 4, 5, 6, 7 - none */ - RSP_VMUDL_DRC(0, 1, 2, 3, 4, 5, 6, 7, 7, 6, 5, 4, 3, 2, 1, 0, 7, 6, 5, 4, 3, 2, 1, 0); - return TRUE; - case 1: /* 0, 1, 2, 3, 4, 5, 6, 7 - ??? */ /* 0, 1, 2, 3, 4, 5, 6, 7 - ??? */ - RSP_VMUDL_DRC(0, 1, 2, 3, 4, 5, 6, 7, 7, 6, 5, 4, 3, 2, 1, 0, 7, 6, 5, 4, 3, 2, 1, 0); - return TRUE; - case 2: /* 1, 3, 5, 7, 0, 2, 4, 6 - 0q */ /* 0, 0, 2, 2, 4, 4, 6, 6 - 0q */ - RSP_VMUDL_DRC(1, 3, 5, 7, 0, 2, 4, 6, 7, 5, 3, 1, 7, 5, 3, 1, 6, 4, 2, 0, 7, 5, 3, 1); - return TRUE; - case 3: /* 0, 2, 4, 6, 1, 3, 5, 7 - 1q */ /* 1, 1, 3, 3, 5, 5, 7, 7 - 1q */ - RSP_VMUDL_DRC(0, 2, 4, 6, 1, 3, 5, 7, 6, 4, 2, 0, 6, 4, 2, 0, 7, 5, 3, 1, 6, 4, 2, 0); - return TRUE; - case 4: /* 1, 2, 3, 5, 6, 7, 0, 4 - 0h */ /* 0, 0, 0, 0, 4, 4, 4, 4 - 0h */ - RSP_VMUDL_DRC(1, 2, 3, 5, 6, 7, 0, 4, 7, 7, 7, 3, 3, 3, 7, 3, 6, 5, 4, 2, 1, 0, 7, 3); - return TRUE; - case 5: /* 0, 2, 3, 4, 6, 7, 1, 5 - 1h */ /* 1, 1, 1, 1, 5, 5, 5, 5 - 1h */ - RSP_VMUDL_DRC(0, 2, 3, 4, 6, 7, 1, 5, 6, 6, 6, 2, 2, 2, 6, 2, 7, 5, 4, 3, 1, 0, 6, 2); - return TRUE; - case 6: /* 0, 1, 3, 4, 5, 7, 2, 6 - 2h */ /* 2, 2, 2, 2, 6, 6, 6, 6 - 2h */ - RSP_VMUDL_DRC(0, 1, 3, 4, 5, 7, 2, 6, 5, 5, 5, 1, 1, 1, 5, 1, 7, 6, 4, 3, 2, 0, 5, 1); - return TRUE; - case 7: /* 0, 1, 2, 4, 5, 6, 3, 7 - 3h */ /* 3, 3, 3, 3, 7, 7, 7, 7 - 3h */ - RSP_VMUDL_DRC(0, 1, 2, 4, 5, 6, 3, 7, 4, 4, 4, 0, 0, 0, 4, 0, 7, 6, 5, 3, 2, 1, 4, 0); - return TRUE; - case 8: /* 1, 2, 3, 4, 5, 6, 7, 0 - 0 */ /* 0, 0, 0, 0, 0, 0, 0, 0 - 0 */ - RSP_VMUDL_DRC(1, 2, 3, 4, 5, 6, 7, 0, 7, 7, 7, 7, 7, 7, 7, 7, 6, 5, 4, 3, 2, 1, 0, 7); - return TRUE; - case 9: /* 0, 2, 3, 4, 5, 6, 7, 1 - 1 */ /* 1, 1, 1, 1, 1, 1, 1, 1 - 0 */ - RSP_VMUDL_DRC(0, 2, 3, 4, 5, 6, 7, 1, 6, 6, 6, 6, 6, 6, 6, 6, 7, 5, 4, 3, 2, 1, 0, 6); - return TRUE; - case 10: /* 0, 1, 3, 4, 5, 6, 7, 2 - 2 */ /* 2, 2, 2, 2, 2, 2, 2, 2 - 0 */ - RSP_VMUDL_DRC(0, 1, 3, 4, 5, 6, 7, 2, 5, 5, 5, 5, 5, 5, 5, 5, 7, 6, 4, 3, 2, 1, 0, 5); - return TRUE; - case 11: /* 0, 1, 2, 4, 5, 6, 7, 3 - 3 */ /* 3, 3, 3, 3, 3, 3, 3, 3 - 0 */ - RSP_VMUDL_DRC(0, 1, 2, 4, 5, 6, 7, 3, 4, 4, 4, 4, 4, 4, 4, 4, 7, 6, 5, 3, 2, 1, 0, 4); - return TRUE; - case 12: /* 0, 1, 2, 3, 5, 6, 7, 4 - 4 */ /* 4, 4, 4, 4, 4, 4, 4, 4 - 0 */ - RSP_VMUDL_DRC(0, 1, 2, 3, 5, 6, 7, 4, 3, 3, 3, 3, 3, 3, 3, 3, 7, 6, 5, 4, 2, 1, 0, 3); - return TRUE; - case 13: /* 0, 1, 2, 3, 4, 6, 7, 5 - 5 */ /* 5, 5, 5, 5, 5, 5, 5, 5 - 0 */ - RSP_VMUDL_DRC(0, 1, 2, 3, 4, 6, 7, 5, 2, 2, 2, 2, 2, 2, 2, 2, 7, 6, 5, 4, 3, 1, 0, 2); - return TRUE; - case 14: /* 0, 1, 2, 3, 4, 5, 7, 6 - 6 */ /* 6, 6, 6, 6, 6, 6, 6, 6 - 0 */ - RSP_VMUDL_DRC(0, 1, 2, 3, 4, 5, 7, 6, 1, 1, 1, 1, 1, 1, 1, 1, 7, 6, 5, 4, 3, 2, 0, 1); - return TRUE; - case 15: /* 0, 1, 2, 3, 4, 5, 6, 7 - 7 */ /* 7, 7, 7, 7, 7, 7, 7, 7 - 0 */ - RSP_VMUDL_DRC(0, 1, 2, 3, 4, 5, 6, 7, 0, 0, 0, 0, 0, 0, 0, 0, 7, 6, 5, 4, 3, 2, 1, 0); - return TRUE; + case 0: /* 0, 1, 2, 3, 4, 5, 6, 7 - none */ /* 0, 1, 2, 3, 4, 5, 6, 7 - none */ + RSP_VMUDL_DRC(0, 1, 2, 3, 4, 5, 6, 7, 7, 6, 5, 4, 3, 2, 1, 0, 7, 6, 5, 4, 3, 2, 1, 0); + return TRUE; + case 1: /* 0, 1, 2, 3, 4, 5, 6, 7 - ??? */ /* 0, 1, 2, 3, 4, 5, 6, 7 - ??? */ + RSP_VMUDL_DRC(0, 1, 2, 3, 4, 5, 6, 7, 7, 6, 5, 4, 3, 2, 1, 0, 7, 6, 5, 4, 3, 2, 1, 0); + return TRUE; + case 2: /* 1, 3, 5, 7, 0, 2, 4, 6 - 0q */ /* 0, 0, 2, 2, 4, 4, 6, 6 - 0q */ + RSP_VMUDL_DRC(1, 3, 5, 7, 0, 2, 4, 6, 7, 5, 3, 1, 7, 5, 3, 1, 6, 4, 2, 0, 7, 5, 3, 1); + return TRUE; + case 3: /* 0, 2, 4, 6, 1, 3, 5, 7 - 1q */ /* 1, 1, 3, 3, 5, 5, 7, 7 - 1q */ + RSP_VMUDL_DRC(0, 2, 4, 6, 1, 3, 5, 7, 6, 4, 2, 0, 6, 4, 2, 0, 7, 5, 3, 1, 6, 4, 2, 0); + return TRUE; + case 4: /* 1, 2, 3, 5, 6, 7, 0, 4 - 0h */ /* 0, 0, 0, 0, 4, 4, 4, 4 - 0h */ + RSP_VMUDL_DRC(1, 2, 3, 5, 6, 7, 0, 4, 7, 7, 7, 3, 3, 3, 7, 3, 6, 5, 4, 2, 1, 0, 7, 3); + return TRUE; + case 5: /* 0, 2, 3, 4, 6, 7, 1, 5 - 1h */ /* 1, 1, 1, 1, 5, 5, 5, 5 - 1h */ + RSP_VMUDL_DRC(0, 2, 3, 4, 6, 7, 1, 5, 6, 6, 6, 2, 2, 2, 6, 2, 7, 5, 4, 3, 1, 0, 6, 2); + return TRUE; + case 6: /* 0, 1, 3, 4, 5, 7, 2, 6 - 2h */ /* 2, 2, 2, 2, 6, 6, 6, 6 - 2h */ + RSP_VMUDL_DRC(0, 1, 3, 4, 5, 7, 2, 6, 5, 5, 5, 1, 1, 1, 5, 1, 7, 6, 4, 3, 2, 0, 5, 1); + return TRUE; + case 7: /* 0, 1, 2, 4, 5, 6, 3, 7 - 3h */ /* 3, 3, 3, 3, 7, 7, 7, 7 - 3h */ + RSP_VMUDL_DRC(0, 1, 2, 4, 5, 6, 3, 7, 4, 4, 4, 0, 0, 0, 4, 0, 7, 6, 5, 3, 2, 1, 4, 0); + return TRUE; + case 8: /* 1, 2, 3, 4, 5, 6, 7, 0 - 0 */ /* 0, 0, 0, 0, 0, 0, 0, 0 - 0 */ + RSP_VMUDL_DRC(1, 2, 3, 4, 5, 6, 7, 0, 7, 7, 7, 7, 7, 7, 7, 7, 6, 5, 4, 3, 2, 1, 0, 7); + return TRUE; + case 9: /* 0, 2, 3, 4, 5, 6, 7, 1 - 1 */ /* 1, 1, 1, 1, 1, 1, 1, 1 - 0 */ + RSP_VMUDL_DRC(0, 2, 3, 4, 5, 6, 7, 1, 6, 6, 6, 6, 6, 6, 6, 6, 7, 5, 4, 3, 2, 1, 0, 6); + return TRUE; + case 10: /* 0, 1, 3, 4, 5, 6, 7, 2 - 2 */ /* 2, 2, 2, 2, 2, 2, 2, 2 - 0 */ + RSP_VMUDL_DRC(0, 1, 3, 4, 5, 6, 7, 2, 5, 5, 5, 5, 5, 5, 5, 5, 7, 6, 4, 3, 2, 1, 0, 5); + return TRUE; + case 11: /* 0, 1, 2, 4, 5, 6, 7, 3 - 3 */ /* 3, 3, 3, 3, 3, 3, 3, 3 - 0 */ + RSP_VMUDL_DRC(0, 1, 2, 4, 5, 6, 7, 3, 4, 4, 4, 4, 4, 4, 4, 4, 7, 6, 5, 3, 2, 1, 0, 4); + return TRUE; + case 12: /* 0, 1, 2, 3, 5, 6, 7, 4 - 4 */ /* 4, 4, 4, 4, 4, 4, 4, 4 - 0 */ + RSP_VMUDL_DRC(0, 1, 2, 3, 5, 6, 7, 4, 3, 3, 3, 3, 3, 3, 3, 3, 7, 6, 5, 4, 2, 1, 0, 3); + return TRUE; + case 13: /* 0, 1, 2, 3, 4, 6, 7, 5 - 5 */ /* 5, 5, 5, 5, 5, 5, 5, 5 - 0 */ + RSP_VMUDL_DRC(0, 1, 2, 3, 4, 6, 7, 5, 2, 2, 2, 2, 2, 2, 2, 2, 7, 6, 5, 4, 3, 1, 0, 2); + return TRUE; + case 14: /* 0, 1, 2, 3, 4, 5, 7, 6 - 6 */ /* 6, 6, 6, 6, 6, 6, 6, 6 - 0 */ + RSP_VMUDL_DRC(0, 1, 2, 3, 4, 5, 7, 6, 1, 1, 1, 1, 1, 1, 1, 1, 7, 6, 5, 4, 3, 2, 0, 1); + return TRUE; + case 15: /* 0, 1, 2, 3, 4, 5, 6, 7 - 7 */ /* 7, 7, 7, 7, 7, 7, 7, 7 - 0 */ + RSP_VMUDL_DRC(0, 1, 2, 3, 4, 5, 6, 7, 0, 0, 0, 0, 0, 0, 0, 0, 7, 6, 5, 4, 3, 2, 1, 0); + return TRUE; } return TRUE; @@ -2564,54 +2564,54 @@ INLINE void cfunc_rsp_vmudl(void *param) switch(EL) { - case 0: /* 0, 1, 2, 3, 4, 5, 6, 7 - none */ /* 0, 1, 2, 3, 4, 5, 6, 7 - none */ - RSP_VMUDL(0, 1, 2, 3, 4, 5, 6, 7, 0, 1, 2, 3, 4, 5, 6, 7); - break; - case 1: /* 0, 1, 2, 3, 4, 5, 6, 7 - ??? */ /* 0, 1, 2, 3, 4, 5, 6, 7 - ??? */ - RSP_VMUDL(0, 1, 2, 3, 4, 5, 6, 7, 0, 1, 2, 3, 4, 5, 6, 7); - break; - case 2: /* 1, 3, 5, 7, 0, 2, 4, 6 - 0q */ /* 0, 0, 2, 2, 4, 4, 6, 6 - 0q */ - RSP_VMUDL(1, 3, 5, 7, 0, 2, 4, 6, 0, 2, 4, 6, 0, 2, 4, 6); - break; - case 3: /* 0, 2, 4, 6, 1, 3, 5, 7 - 1q */ /* 1, 1, 3, 3, 5, 5, 7, 7 - 1q */ - RSP_VMUDL(0, 2, 4, 6, 1, 3, 5, 7, 1, 3, 5, 7, 1, 3, 5, 7); - break; - case 4: /* 1, 2, 3, 5, 6, 7, 0, 4 - 0h */ /* 0, 0, 0, 0, 4, 4, 4, 4 - 0h */ - RSP_VMUDL(1, 2, 3, 5, 6, 7, 0, 4, 0, 0, 0, 4, 4, 4, 0, 4); - break; - case 5: /* 0, 2, 3, 4, 6, 7, 1, 5 - 1h */ /* 1, 1, 1, 1, 5, 5, 5, 5 - 1h */ - RSP_VMUDL(0, 2, 3, 4, 6, 7, 1, 5, 1, 1, 1, 5, 5, 5, 1, 5); - break; - case 6: /* 0, 1, 3, 4, 5, 7, 2, 6 - 2h */ /* 2, 2, 2, 2, 6, 6, 6, 6 - 2h */ - RSP_VMUDL(0, 1, 3, 4, 5, 7, 2, 6, 2, 2, 2, 6, 6, 6, 2, 6); - break; - case 7: /* 0, 1, 2, 4, 5, 6, 3, 7 - 3h */ /* 3, 3, 3, 3, 7, 7, 7, 7 - 3h */ - RSP_VMUDL(0, 1, 2, 4, 5, 6, 3, 7, 3, 3, 3, 7, 7, 7, 3, 7); - break; - case 8: /* 1, 2, 3, 4, 5, 6, 7, 0 - 0 */ /* 0, 0, 0, 0, 0, 0, 0, 0 - 0 */ - RSP_VMUDL(1, 2, 3, 4, 5, 6, 7, 0, 0, 0, 0, 0, 0, 0, 0, 0); - break; - case 9: /* 0, 2, 3, 4, 5, 6, 7, 1 - 1 */ /* 1, 1, 1, 1, 1, 1, 1, 1 - 0 */ - RSP_VMUDL(0, 2, 3, 4, 5, 6, 7, 1, 1, 1, 1, 1, 1, 1, 1, 1); - break; - case 10: /* 0, 1, 3, 4, 5, 6, 7, 2 - 2 */ /* 2, 2, 2, 2, 2, 2, 2, 2 - 0 */ - RSP_VMUDL(0, 1, 3, 4, 5, 6, 7, 2, 2, 2, 2, 2, 2, 2, 2, 2); - break; - case 11: /* 0, 1, 2, 4, 5, 6, 7, 3 - 3 */ /* 3, 3, 3, 3, 3, 3, 3, 3 - 0 */ - RSP_VMUDL(0, 1, 2, 4, 5, 6, 7, 3, 3, 3, 3, 3, 3, 3, 3, 3); - break; - case 12: /* 0, 1, 2, 3, 5, 6, 7, 4 - 4 */ /* 4, 4, 4, 4, 4, 4, 4, 4 - 0 */ - RSP_VMUDL(0, 1, 2, 3, 5, 6, 7, 4, 4, 4, 4, 4, 4, 4, 4, 4); - break; - case 13: /* 0, 1, 2, 3, 4, 6, 7, 5 - 5 */ /* 5, 5, 5, 5, 5, 5, 5, 5 - 0 */ - RSP_VMUDL(0, 1, 2, 3, 4, 6, 7, 5, 5, 5, 5, 5, 5, 5, 5, 5); - break; - case 14: /* 0, 1, 2, 3, 4, 5, 7, 6 - 6 */ /* 6, 6, 6, 6, 6, 6, 6, 6 - 0 */ - RSP_VMUDL(0, 1, 2, 3, 4, 5, 7, 6, 6, 6, 6, 6, 6, 6, 6, 6); - break; - case 15: /* 0, 1, 2, 3, 4, 5, 6, 7 - 7 */ /* 7, 7, 7, 7, 7, 7, 7, 7 - 0 */ - RSP_VMUDL(0, 1, 2, 3, 4, 5, 6, 7, 7, 7, 7, 7, 7, 7, 7, 7); - break; + case 0: /* 0, 1, 2, 3, 4, 5, 6, 7 - none */ /* 0, 1, 2, 3, 4, 5, 6, 7 - none */ + RSP_VMUDL(0, 1, 2, 3, 4, 5, 6, 7, 0, 1, 2, 3, 4, 5, 6, 7); + break; + case 1: /* 0, 1, 2, 3, 4, 5, 6, 7 - ??? */ /* 0, 1, 2, 3, 4, 5, 6, 7 - ??? */ + RSP_VMUDL(0, 1, 2, 3, 4, 5, 6, 7, 0, 1, 2, 3, 4, 5, 6, 7); + break; + case 2: /* 1, 3, 5, 7, 0, 2, 4, 6 - 0q */ /* 0, 0, 2, 2, 4, 4, 6, 6 - 0q */ + RSP_VMUDL(1, 3, 5, 7, 0, 2, 4, 6, 0, 2, 4, 6, 0, 2, 4, 6); + break; + case 3: /* 0, 2, 4, 6, 1, 3, 5, 7 - 1q */ /* 1, 1, 3, 3, 5, 5, 7, 7 - 1q */ + RSP_VMUDL(0, 2, 4, 6, 1, 3, 5, 7, 1, 3, 5, 7, 1, 3, 5, 7); + break; + case 4: /* 1, 2, 3, 5, 6, 7, 0, 4 - 0h */ /* 0, 0, 0, 0, 4, 4, 4, 4 - 0h */ + RSP_VMUDL(1, 2, 3, 5, 6, 7, 0, 4, 0, 0, 0, 4, 4, 4, 0, 4); + break; + case 5: /* 0, 2, 3, 4, 6, 7, 1, 5 - 1h */ /* 1, 1, 1, 1, 5, 5, 5, 5 - 1h */ + RSP_VMUDL(0, 2, 3, 4, 6, 7, 1, 5, 1, 1, 1, 5, 5, 5, 1, 5); + break; + case 6: /* 0, 1, 3, 4, 5, 7, 2, 6 - 2h */ /* 2, 2, 2, 2, 6, 6, 6, 6 - 2h */ + RSP_VMUDL(0, 1, 3, 4, 5, 7, 2, 6, 2, 2, 2, 6, 6, 6, 2, 6); + break; + case 7: /* 0, 1, 2, 4, 5, 6, 3, 7 - 3h */ /* 3, 3, 3, 3, 7, 7, 7, 7 - 3h */ + RSP_VMUDL(0, 1, 2, 4, 5, 6, 3, 7, 3, 3, 3, 7, 7, 7, 3, 7); + break; + case 8: /* 1, 2, 3, 4, 5, 6, 7, 0 - 0 */ /* 0, 0, 0, 0, 0, 0, 0, 0 - 0 */ + RSP_VMUDL(1, 2, 3, 4, 5, 6, 7, 0, 0, 0, 0, 0, 0, 0, 0, 0); + break; + case 9: /* 0, 2, 3, 4, 5, 6, 7, 1 - 1 */ /* 1, 1, 1, 1, 1, 1, 1, 1 - 0 */ + RSP_VMUDL(0, 2, 3, 4, 5, 6, 7, 1, 1, 1, 1, 1, 1, 1, 1, 1); + break; + case 10: /* 0, 1, 3, 4, 5, 6, 7, 2 - 2 */ /* 2, 2, 2, 2, 2, 2, 2, 2 - 0 */ + RSP_VMUDL(0, 1, 3, 4, 5, 6, 7, 2, 2, 2, 2, 2, 2, 2, 2, 2); + break; + case 11: /* 0, 1, 2, 4, 5, 6, 7, 3 - 3 */ /* 3, 3, 3, 3, 3, 3, 3, 3 - 0 */ + RSP_VMUDL(0, 1, 2, 4, 5, 6, 7, 3, 3, 3, 3, 3, 3, 3, 3, 3); + break; + case 12: /* 0, 1, 2, 3, 5, 6, 7, 4 - 4 */ /* 4, 4, 4, 4, 4, 4, 4, 4 - 0 */ + RSP_VMUDL(0, 1, 2, 3, 5, 6, 7, 4, 4, 4, 4, 4, 4, 4, 4, 4); + break; + case 13: /* 0, 1, 2, 3, 4, 6, 7, 5 - 5 */ /* 5, 5, 5, 5, 5, 5, 5, 5 - 0 */ + RSP_VMUDL(0, 1, 2, 3, 4, 6, 7, 5, 5, 5, 5, 5, 5, 5, 5, 5); + break; + case 14: /* 0, 1, 2, 3, 4, 5, 7, 6 - 6 */ /* 6, 6, 6, 6, 6, 6, 6, 6 - 0 */ + RSP_VMUDL(0, 1, 2, 3, 4, 5, 7, 6, 6, 6, 6, 6, 6, 6, 6, 6); + break; + case 15: /* 0, 1, 2, 3, 4, 5, 6, 7 - 7 */ /* 7, 7, 7, 7, 7, 7, 7, 7 - 0 */ + RSP_VMUDL(0, 1, 2, 3, 4, 5, 6, 7, 7, 7, 7, 7, 7, 7, 7, 7); + break; } } #endif @@ -2623,86 +2623,86 @@ INLINE void cfunc_rsp_vmudl(void *param) #define RSP_VMUDM_DRC(E10, E11, E12, E13, E14, E15, E16, E17, E20, E21, E22, E23, E24, E25, E26, E27, I0, I1, I2, I3, I4, I5, I6, I7) \ { \ - UML_SEXT(block, IREG(1), VS(VS1REG, I0), WORD); \ - UML_SEXT(block, IREG(0), VS(VS2REG, E20), WORD); \ - UML_AND(block, IREG(0), IREG(0), IMM(0x0000ffff)); \ + UML_SEXT(block, IREG(1), VS(VS1REG, I0), WORD); \ + UML_SEXT(block, IREG(0), VS(VS2REG, E20), WORD); \ + UML_AND(block, IREG(0), IREG(0), IMM(0x0000ffff)); \ UML_MULS(block, IREG(0), IREG(1), IREG(0), IREG(1)); \ UML_DSEXT(block, IREG(0), IREG(0), DWORD); \ UML_DSHL(block, IREG(0), IREG(0), IMM(16)); \ UML_DMOV(block, VACCUML(E10), IREG(0)); \ \ - UML_SEXT(block, IREG(1), VS(VS1REG, I1), WORD); \ - UML_SEXT(block, IREG(0), VS(VS2REG, E21), WORD); \ - UML_AND(block, IREG(0), IREG(0), IMM(0x0000ffff)); \ + UML_SEXT(block, IREG(1), VS(VS1REG, I1), WORD); \ + UML_SEXT(block, IREG(0), VS(VS2REG, E21), WORD); \ + UML_AND(block, IREG(0), IREG(0), IMM(0x0000ffff)); \ UML_MULS(block, IREG(0), IREG(1), IREG(0), IREG(1)); \ UML_DSEXT(block, IREG(0), IREG(0), DWORD); \ UML_DSHL(block, IREG(0), IREG(0), IMM(16)); \ UML_DMOV(block, VACCUML(E11), IREG(0)); \ \ - UML_SEXT(block, IREG(1), VS(VS1REG, I2), WORD); \ - UML_SEXT(block, IREG(0), VS(VS2REG, E22), WORD); \ - UML_AND(block, IREG(0), IREG(0), IMM(0x0000ffff)); \ + UML_SEXT(block, IREG(1), VS(VS1REG, I2), WORD); \ + UML_SEXT(block, IREG(0), VS(VS2REG, E22), WORD); \ + UML_AND(block, IREG(0), IREG(0), IMM(0x0000ffff)); \ UML_MULS(block, IREG(0), IREG(1), IREG(0), IREG(1)); \ UML_DSEXT(block, IREG(0), IREG(0), DWORD); \ UML_DSHL(block, IREG(0), IREG(0), IMM(16)); \ UML_DMOV(block, VACCUML(E12), IREG(0)); \ \ - UML_SEXT(block, IREG(1), VS(VS1REG, I3), WORD); \ - UML_SEXT(block, IREG(0), VS(VS2REG, E23), WORD); \ - UML_AND(block, IREG(0), IREG(0), IMM(0x0000ffff)); \ + UML_SEXT(block, IREG(1), VS(VS1REG, I3), WORD); \ + UML_SEXT(block, IREG(0), VS(VS2REG, E23), WORD); \ + UML_AND(block, IREG(0), IREG(0), IMM(0x0000ffff)); \ UML_MULS(block, IREG(0), IREG(1), IREG(0), IREG(1)); \ UML_DSEXT(block, IREG(0), IREG(0), DWORD); \ UML_DSHL(block, IREG(0), IREG(0), IMM(16)); \ UML_DMOV(block, VACCUML(E13), IREG(0)); \ \ - UML_SEXT(block, IREG(1), VS(VS1REG, I4), WORD); \ - UML_SEXT(block, IREG(0), VS(VS2REG, E24), WORD); \ - UML_AND(block, IREG(0), IREG(0), IMM(0x0000ffff)); \ + UML_SEXT(block, IREG(1), VS(VS1REG, I4), WORD); \ + UML_SEXT(block, IREG(0), VS(VS2REG, E24), WORD); \ + UML_AND(block, IREG(0), IREG(0), IMM(0x0000ffff)); \ UML_MULS(block, IREG(0), IREG(1), IREG(0), IREG(1)); \ UML_DSEXT(block, IREG(0), IREG(0), DWORD); \ UML_DSHL(block, IREG(0), IREG(0), IMM(16)); \ UML_DMOV(block, VACCUML(E14), IREG(0)); \ \ - UML_SEXT(block, IREG(1), VS(VS1REG, I5), WORD); \ - UML_SEXT(block, IREG(0), VS(VS2REG, E25), WORD); \ - UML_AND(block, IREG(0), IREG(0), IMM(0x0000ffff)); \ + UML_SEXT(block, IREG(1), VS(VS1REG, I5), WORD); \ + UML_SEXT(block, IREG(0), VS(VS2REG, E25), WORD); \ + UML_AND(block, IREG(0), IREG(0), IMM(0x0000ffff)); \ UML_MULS(block, IREG(0), IREG(1), IREG(0), IREG(1)); \ UML_DSEXT(block, IREG(0), IREG(0), DWORD); \ UML_DSHL(block, IREG(0), IREG(0), IMM(16)); \ UML_DMOV(block, VACCUML(E15), IREG(0)); \ \ - UML_SEXT(block, IREG(1), VS(VS1REG, I6), WORD); \ - UML_SEXT(block, IREG(0), VS(VS2REG, E26), WORD); \ - UML_AND(block, IREG(0), IREG(0), IMM(0x0000ffff)); \ + UML_SEXT(block, IREG(1), VS(VS1REG, I6), WORD); \ + UML_SEXT(block, IREG(0), VS(VS2REG, E26), WORD); \ + UML_AND(block, IREG(0), IREG(0), IMM(0x0000ffff)); \ UML_MULS(block, IREG(0), IREG(1), IREG(0), IREG(1)); \ UML_DSEXT(block, IREG(0), IREG(0), DWORD); \ UML_DSHL(block, IREG(0), IREG(0), IMM(16)); \ UML_DMOV(block, VACCUML(E16), IREG(0)); \ \ - UML_SEXT(block, IREG(1), VS(VS1REG, I7), WORD); \ - UML_SEXT(block, IREG(0), VS(VS2REG, E27), WORD); \ - UML_AND(block, IREG(0), IREG(0), IMM(0x0000ffff)); \ + UML_SEXT(block, IREG(1), VS(VS1REG, I7), WORD); \ + UML_SEXT(block, IREG(0), VS(VS2REG, E27), WORD); \ + UML_AND(block, IREG(0), IREG(0), IMM(0x0000ffff)); \ UML_MULS(block, IREG(0), IREG(1), IREG(0), IREG(1)); \ UML_DSEXT(block, IREG(0), IREG(0), DWORD); \ UML_DSHL(block, IREG(0), IREG(0), IMM(16)); \ UML_DMOV(block, VACCUML(E17), IREG(0)); \ \ - UML_SEXT(block, IREG(0), VACCUMHM(E10), WORD); \ - UML_STORE(block, &rsp->v[VDREG].s[I0], IMM(0), IREG(0), WORD); \ - UML_SEXT(block, IREG(0), VACCUMHM(E11), WORD); \ - UML_STORE(block, &rsp->v[VDREG].s[I1], IMM(0), IREG(0), WORD); \ - UML_SEXT(block, IREG(0), VACCUMHM(E12), WORD); \ - UML_STORE(block, &rsp->v[VDREG].s[I2], IMM(0), IREG(0), WORD); \ - UML_SEXT(block, IREG(0), VACCUMHM(E13), WORD); \ - UML_STORE(block, &rsp->v[VDREG].s[I3], IMM(0), IREG(0), WORD); \ - UML_SEXT(block, IREG(0), VACCUMHM(E14), WORD); \ - UML_STORE(block, &rsp->v[VDREG].s[I4], IMM(0), IREG(0), WORD); \ - UML_SEXT(block, IREG(0), VACCUMHM(E15), WORD); \ - UML_STORE(block, &rsp->v[VDREG].s[I5], IMM(0), IREG(0), WORD); \ - UML_SEXT(block, IREG(0), VACCUMHM(E16), WORD); \ - UML_STORE(block, &rsp->v[VDREG].s[I6], IMM(0), IREG(0), WORD); \ - UML_SEXT(block, IREG(0), VACCUMHM(E17), WORD); \ - UML_STORE(block, &rsp->v[VDREG].s[I7], IMM(0), IREG(0), WORD); \ + UML_SEXT(block, IREG(0), VACCUMHM(E10), WORD); \ + UML_STORE(block, &rsp->v[VDREG].s[I0], IMM(0), IREG(0), WORD); \ + UML_SEXT(block, IREG(0), VACCUMHM(E11), WORD); \ + UML_STORE(block, &rsp->v[VDREG].s[I1], IMM(0), IREG(0), WORD); \ + UML_SEXT(block, IREG(0), VACCUMHM(E12), WORD); \ + UML_STORE(block, &rsp->v[VDREG].s[I2], IMM(0), IREG(0), WORD); \ + UML_SEXT(block, IREG(0), VACCUMHM(E13), WORD); \ + UML_STORE(block, &rsp->v[VDREG].s[I3], IMM(0), IREG(0), WORD); \ + UML_SEXT(block, IREG(0), VACCUMHM(E14), WORD); \ + UML_STORE(block, &rsp->v[VDREG].s[I4], IMM(0), IREG(0), WORD); \ + UML_SEXT(block, IREG(0), VACCUMHM(E15), WORD); \ + UML_STORE(block, &rsp->v[VDREG].s[I5], IMM(0), IREG(0), WORD); \ + UML_SEXT(block, IREG(0), VACCUMHM(E16), WORD); \ + UML_STORE(block, &rsp->v[VDREG].s[I6], IMM(0), IREG(0), WORD); \ + UML_SEXT(block, IREG(0), VACCUMHM(E17), WORD); \ + UML_STORE(block, &rsp->v[VDREG].s[I7], IMM(0), IREG(0), WORD); \ } static int generate_vmudm(rsp_state *rsp, drcuml_block *block, compiler_state *compiler, const opcode_desc *desc) // vmudl @@ -2719,54 +2719,54 @@ static int generate_vmudm(rsp_state *rsp, drcuml_block *block, compiler_state *c // The middle slice of accumulator is stored into destination element switch(EL) { - case 0: /* 0, 1, 2, 3, 4, 5, 6, 7 - none */ /* 0, 1, 2, 3, 4, 5, 6, 7 - none */ - RSP_VMUDM_DRC(0, 1, 2, 3, 4, 5, 6, 7, 7, 6, 5, 4, 3, 2, 1, 0, 7, 6, 5, 4, 3, 2, 1, 0); - return TRUE; - case 1: /* 0, 1, 2, 3, 4, 5, 6, 7 - ??? */ /* 0, 1, 2, 3, 4, 5, 6, 7 - ??? */ - RSP_VMUDM_DRC(0, 1, 2, 3, 4, 5, 6, 7, 7, 6, 5, 4, 3, 2, 1, 0, 7, 6, 5, 4, 3, 2, 1, 0); - return TRUE; - case 2: /* 1, 3, 5, 7, 0, 2, 4, 6 - 0q */ /* 0, 0, 2, 2, 4, 4, 6, 6 - 0q */ - RSP_VMUDM_DRC(1, 3, 5, 7, 0, 2, 4, 6, 7, 5, 3, 1, 7, 5, 3, 1, 6, 4, 2, 0, 7, 5, 3, 1); - return TRUE; - case 3: /* 0, 2, 4, 6, 1, 3, 5, 7 - 1q */ /* 1, 1, 3, 3, 5, 5, 7, 7 - 1q */ - RSP_VMUDM_DRC(0, 2, 4, 6, 1, 3, 5, 7, 6, 4, 2, 0, 6, 4, 2, 0, 7, 5, 3, 1, 6, 4, 2, 0); - return TRUE; - case 4: /* 1, 2, 3, 5, 6, 7, 0, 4 - 0h */ /* 0, 0, 0, 0, 4, 4, 4, 4 - 0h */ - RSP_VMUDM_DRC(1, 2, 3, 5, 6, 7, 0, 4, 7, 7, 7, 3, 3, 3, 7, 3, 6, 5, 4, 2, 1, 0, 7, 3); - return TRUE; - case 5: /* 0, 2, 3, 4, 6, 7, 1, 5 - 1h */ /* 1, 1, 1, 1, 5, 5, 5, 5 - 1h */ - RSP_VMUDM_DRC(0, 2, 3, 4, 6, 7, 1, 5, 6, 6, 6, 2, 2, 2, 6, 2, 7, 5, 4, 3, 1, 0, 6, 2); - return TRUE; - case 6: /* 0, 1, 3, 4, 5, 7, 2, 6 - 2h */ /* 2, 2, 2, 2, 6, 6, 6, 6 - 2h */ - RSP_VMUDM_DRC(0, 1, 3, 4, 5, 7, 2, 6, 5, 5, 5, 1, 1, 1, 5, 1, 7, 6, 4, 3, 2, 0, 5, 1); - return TRUE; - case 7: /* 0, 1, 2, 4, 5, 6, 3, 7 - 3h */ /* 3, 3, 3, 3, 7, 7, 7, 7 - 3h */ - RSP_VMUDM_DRC(0, 1, 2, 4, 5, 6, 3, 7, 4, 4, 4, 0, 0, 0, 4, 0, 7, 6, 5, 3, 2, 1, 4, 0); - return TRUE; - case 8: /* 1, 2, 3, 4, 5, 6, 7, 0 - 0 */ /* 0, 0, 0, 0, 0, 0, 0, 0 - 0 */ - RSP_VMUDM_DRC(1, 2, 3, 4, 5, 6, 7, 0, 7, 7, 7, 7, 7, 7, 7, 7, 6, 5, 4, 3, 2, 1, 0, 7); - return TRUE; - case 9: /* 0, 2, 3, 4, 5, 6, 7, 1 - 1 */ /* 1, 1, 1, 1, 1, 1, 1, 1 - 0 */ - RSP_VMUDM_DRC(0, 2, 3, 4, 5, 6, 7, 1, 6, 6, 6, 6, 6, 6, 6, 6, 7, 5, 4, 3, 2, 1, 0, 6); - return TRUE; - case 10: /* 0, 1, 3, 4, 5, 6, 7, 2 - 2 */ /* 2, 2, 2, 2, 2, 2, 2, 2 - 0 */ - RSP_VMUDM_DRC(0, 1, 3, 4, 5, 6, 7, 2, 5, 5, 5, 5, 5, 5, 5, 5, 7, 6, 4, 3, 2, 1, 0, 5); - return TRUE; - case 11: /* 0, 1, 2, 4, 5, 6, 7, 3 - 3 */ /* 3, 3, 3, 3, 3, 3, 3, 3 - 0 */ - RSP_VMUDM_DRC(0, 1, 2, 4, 5, 6, 7, 3, 4, 4, 4, 4, 4, 4, 4, 4, 7, 6, 5, 3, 2, 1, 0, 4); - return TRUE; - case 12: /* 0, 1, 2, 3, 5, 6, 7, 4 - 4 */ /* 4, 4, 4, 4, 4, 4, 4, 4 - 0 */ - RSP_VMUDM_DRC(0, 1, 2, 3, 5, 6, 7, 4, 3, 3, 3, 3, 3, 3, 3, 3, 7, 6, 5, 4, 2, 1, 0, 3); - return TRUE; - case 13: /* 0, 1, 2, 3, 4, 6, 7, 5 - 5 */ /* 5, 5, 5, 5, 5, 5, 5, 5 - 0 */ - RSP_VMUDM_DRC(0, 1, 2, 3, 4, 6, 7, 5, 2, 2, 2, 2, 2, 2, 2, 2, 7, 6, 5, 4, 3, 1, 0, 2); - return TRUE; - case 14: /* 0, 1, 2, 3, 4, 5, 7, 6 - 6 */ /* 6, 6, 6, 6, 6, 6, 6, 6 - 0 */ - RSP_VMUDM_DRC(0, 1, 2, 3, 4, 5, 7, 6, 1, 1, 1, 1, 1, 1, 1, 1, 7, 6, 5, 4, 3, 2, 0, 1); - return TRUE; - case 15: /* 0, 1, 2, 3, 4, 5, 6, 7 - 7 */ /* 7, 7, 7, 7, 7, 7, 7, 7 - 0 */ - RSP_VMUDM_DRC(0, 1, 2, 3, 4, 5, 6, 7, 0, 0, 0, 0, 0, 0, 0, 0, 7, 6, 5, 4, 3, 2, 1, 0); - return TRUE; + case 0: /* 0, 1, 2, 3, 4, 5, 6, 7 - none */ /* 0, 1, 2, 3, 4, 5, 6, 7 - none */ + RSP_VMUDM_DRC(0, 1, 2, 3, 4, 5, 6, 7, 7, 6, 5, 4, 3, 2, 1, 0, 7, 6, 5, 4, 3, 2, 1, 0); + return TRUE; + case 1: /* 0, 1, 2, 3, 4, 5, 6, 7 - ??? */ /* 0, 1, 2, 3, 4, 5, 6, 7 - ??? */ + RSP_VMUDM_DRC(0, 1, 2, 3, 4, 5, 6, 7, 7, 6, 5, 4, 3, 2, 1, 0, 7, 6, 5, 4, 3, 2, 1, 0); + return TRUE; + case 2: /* 1, 3, 5, 7, 0, 2, 4, 6 - 0q */ /* 0, 0, 2, 2, 4, 4, 6, 6 - 0q */ + RSP_VMUDM_DRC(1, 3, 5, 7, 0, 2, 4, 6, 7, 5, 3, 1, 7, 5, 3, 1, 6, 4, 2, 0, 7, 5, 3, 1); + return TRUE; + case 3: /* 0, 2, 4, 6, 1, 3, 5, 7 - 1q */ /* 1, 1, 3, 3, 5, 5, 7, 7 - 1q */ + RSP_VMUDM_DRC(0, 2, 4, 6, 1, 3, 5, 7, 6, 4, 2, 0, 6, 4, 2, 0, 7, 5, 3, 1, 6, 4, 2, 0); + return TRUE; + case 4: /* 1, 2, 3, 5, 6, 7, 0, 4 - 0h */ /* 0, 0, 0, 0, 4, 4, 4, 4 - 0h */ + RSP_VMUDM_DRC(1, 2, 3, 5, 6, 7, 0, 4, 7, 7, 7, 3, 3, 3, 7, 3, 6, 5, 4, 2, 1, 0, 7, 3); + return TRUE; + case 5: /* 0, 2, 3, 4, 6, 7, 1, 5 - 1h */ /* 1, 1, 1, 1, 5, 5, 5, 5 - 1h */ + RSP_VMUDM_DRC(0, 2, 3, 4, 6, 7, 1, 5, 6, 6, 6, 2, 2, 2, 6, 2, 7, 5, 4, 3, 1, 0, 6, 2); + return TRUE; + case 6: /* 0, 1, 3, 4, 5, 7, 2, 6 - 2h */ /* 2, 2, 2, 2, 6, 6, 6, 6 - 2h */ + RSP_VMUDM_DRC(0, 1, 3, 4, 5, 7, 2, 6, 5, 5, 5, 1, 1, 1, 5, 1, 7, 6, 4, 3, 2, 0, 5, 1); + return TRUE; + case 7: /* 0, 1, 2, 4, 5, 6, 3, 7 - 3h */ /* 3, 3, 3, 3, 7, 7, 7, 7 - 3h */ + RSP_VMUDM_DRC(0, 1, 2, 4, 5, 6, 3, 7, 4, 4, 4, 0, 0, 0, 4, 0, 7, 6, 5, 3, 2, 1, 4, 0); + return TRUE; + case 8: /* 1, 2, 3, 4, 5, 6, 7, 0 - 0 */ /* 0, 0, 0, 0, 0, 0, 0, 0 - 0 */ + RSP_VMUDM_DRC(1, 2, 3, 4, 5, 6, 7, 0, 7, 7, 7, 7, 7, 7, 7, 7, 6, 5, 4, 3, 2, 1, 0, 7); + return TRUE; + case 9: /* 0, 2, 3, 4, 5, 6, 7, 1 - 1 */ /* 1, 1, 1, 1, 1, 1, 1, 1 - 0 */ + RSP_VMUDM_DRC(0, 2, 3, 4, 5, 6, 7, 1, 6, 6, 6, 6, 6, 6, 6, 6, 7, 5, 4, 3, 2, 1, 0, 6); + return TRUE; + case 10: /* 0, 1, 3, 4, 5, 6, 7, 2 - 2 */ /* 2, 2, 2, 2, 2, 2, 2, 2 - 0 */ + RSP_VMUDM_DRC(0, 1, 3, 4, 5, 6, 7, 2, 5, 5, 5, 5, 5, 5, 5, 5, 7, 6, 4, 3, 2, 1, 0, 5); + return TRUE; + case 11: /* 0, 1, 2, 4, 5, 6, 7, 3 - 3 */ /* 3, 3, 3, 3, 3, 3, 3, 3 - 0 */ + RSP_VMUDM_DRC(0, 1, 2, 4, 5, 6, 7, 3, 4, 4, 4, 4, 4, 4, 4, 4, 7, 6, 5, 3, 2, 1, 0, 4); + return TRUE; + case 12: /* 0, 1, 2, 3, 5, 6, 7, 4 - 4 */ /* 4, 4, 4, 4, 4, 4, 4, 4 - 0 */ + RSP_VMUDM_DRC(0, 1, 2, 3, 5, 6, 7, 4, 3, 3, 3, 3, 3, 3, 3, 3, 7, 6, 5, 4, 2, 1, 0, 3); + return TRUE; + case 13: /* 0, 1, 2, 3, 4, 6, 7, 5 - 5 */ /* 5, 5, 5, 5, 5, 5, 5, 5 - 0 */ + RSP_VMUDM_DRC(0, 1, 2, 3, 4, 6, 7, 5, 2, 2, 2, 2, 2, 2, 2, 2, 7, 6, 5, 4, 3, 1, 0, 2); + return TRUE; + case 14: /* 0, 1, 2, 3, 4, 5, 7, 6 - 6 */ /* 6, 6, 6, 6, 6, 6, 6, 6 - 0 */ + RSP_VMUDM_DRC(0, 1, 2, 3, 4, 5, 7, 6, 1, 1, 1, 1, 1, 1, 1, 1, 7, 6, 5, 4, 3, 2, 0, 1); + return TRUE; + case 15: /* 0, 1, 2, 3, 4, 5, 6, 7 - 7 */ /* 7, 7, 7, 7, 7, 7, 7, 7 - 0 */ + RSP_VMUDM_DRC(0, 1, 2, 3, 4, 5, 6, 7, 0, 0, 0, 0, 0, 0, 0, 0, 7, 6, 5, 4, 3, 2, 1, 0); + return TRUE; } return TRUE; @@ -2817,73 +2817,73 @@ INLINE void cfunc_rsp_vmudm(void *param) switch(EL) { - case 0: /* 0, 1, 2, 3, 4, 5, 6, 7 - none */ /* 0, 1, 2, 3, 4, 5, 6, 7 - none */ - RSP_VMUDM(0, 1, 2, 3, 4, 5, 6, 7, 7, 6, 5, 4, 3, 2, 1, 0, 7, 6, 5, 4, 3, 2, 1, 0); - break; - case 1: /* 0, 1, 2, 3, 4, 5, 6, 7 - ??? */ /* 0, 1, 2, 3, 4, 5, 6, 7 - ??? */ - RSP_VMUDM(0, 1, 2, 3, 4, 5, 6, 7, 7, 6, 5, 4, 3, 2, 1, 0, 7, 6, 5, 4, 3, 2, 1, 0); - break; - case 2: /* 1, 3, 5, 7, 0, 2, 4, 6 - 0q */ /* 0, 0, 2, 2, 4, 4, 6, 6 - 0q */ - RSP_VMUDM(1, 3, 5, 7, 0, 2, 4, 6, 7, 5, 3, 1, 7, 5, 3, 1, 6, 4, 2, 0, 7, 5, 3, 1); - break; - case 3: /* 0, 2, 4, 6, 1, 3, 5, 7 - 1q */ /* 1, 1, 3, 3, 5, 5, 7, 7 - 1q */ - RSP_VMUDM(0, 2, 4, 6, 1, 3, 5, 7, 6, 4, 2, 0, 6, 4, 2, 0, 7, 5, 3, 1, 6, 4, 2, 0); - break; - case 4: /* 1, 2, 3, 5, 6, 7, 0, 4 - 0h */ /* 0, 0, 0, 0, 4, 4, 4, 4 - 0h */ - RSP_VMUDM(1, 2, 3, 5, 6, 7, 0, 4, 7, 7, 7, 3, 3, 3, 7, 3, 6, 5, 4, 2, 1, 0, 7, 3); - break; - case 5: /* 0, 2, 3, 4, 6, 7, 1, 5 - 1h */ /* 1, 1, 1, 1, 5, 5, 5, 5 - 1h */ - RSP_VMUDM(0, 2, 3, 4, 6, 7, 1, 5, 6, 6, 6, 2, 2, 2, 6, 2, 7, 5, 4, 3, 1, 0, 6, 2); - break; - case 6: /* 0, 1, 3, 4, 5, 7, 2, 6 - 2h */ /* 2, 2, 2, 2, 6, 6, 6, 6 - 2h */ - RSP_VMUDM(0, 1, 3, 4, 5, 7, 2, 6, 5, 5, 5, 1, 1, 1, 5, 1, 7, 6, 4, 3, 2, 0, 5, 1); - break; - case 7: /* 0, 1, 2, 4, 5, 6, 3, 7 - 3h */ /* 3, 3, 3, 3, 7, 7, 7, 7 - 3h */ - RSP_VMUDM(0, 1, 2, 4, 5, 6, 3, 7, 4, 4, 4, 0, 0, 0, 4, 0, 7, 6, 5, 3, 2, 1, 4, 0); - break; - case 8: /* 1, 2, 3, 4, 5, 6, 7, 0 - 0 */ /* 0, 0, 0, 0, 0, 0, 0, 0 - 0 */ - RSP_VMUDM(1, 2, 3, 4, 5, 6, 7, 0, 7, 7, 7, 7, 7, 7, 7, 7, 6, 5, 4, 3, 2, 1, 0, 7); - break; - case 9: /* 0, 2, 3, 4, 5, 6, 7, 1 - 1 */ /* 1, 1, 1, 1, 1, 1, 1, 1 - 0 */ - RSP_VMUDM(0, 2, 3, 4, 5, 6, 7, 1, 6, 6, 6, 6, 6, 6, 6, 6, 7, 5, 4, 3, 2, 1, 0, 6); - break; - case 10: /* 0, 1, 3, 4, 5, 6, 7, 2 - 2 */ /* 2, 2, 2, 2, 2, 2, 2, 2 - 0 */ - RSP_VMUDM(0, 1, 3, 4, 5, 6, 7, 2, 5, 5, 5, 5, 5, 5, 5, 5, 7, 6, 4, 3, 2, 1, 0, 5); - break; - case 11: /* 0, 1, 2, 4, 5, 6, 7, 3 - 3 */ /* 3, 3, 3, 3, 3, 3, 3, 3 - 0 */ - RSP_VMUDM(0, 1, 2, 4, 5, 6, 7, 3, 4, 4, 4, 4, 4, 4, 4, 4, 7, 6, 5, 3, 2, 1, 0, 4); - break; - case 12: /* 0, 1, 2, 3, 5, 6, 7, 4 - 4 */ /* 4, 4, 4, 4, 4, 4, 4, 4 - 0 */ - RSP_VMUDM(0, 1, 2, 3, 5, 6, 7, 4, 3, 3, 3, 3, 3, 3, 3, 3, 7, 6, 5, 4, 2, 1, 0, 3); - break; - case 13: /* 0, 1, 2, 3, 4, 6, 7, 5 - 5 */ /* 5, 5, 5, 5, 5, 5, 5, 5 - 0 */ - RSP_VMUDM(0, 1, 2, 3, 4, 6, 7, 5, 2, 2, 2, 2, 2, 2, 2, 2, 7, 6, 5, 4, 3, 1, 0, 2); - break; - case 14: /* 0, 1, 2, 3, 4, 5, 7, 6 - 6 */ /* 6, 6, 6, 6, 6, 6, 6, 6 - 0 */ - RSP_VMUDM(0, 1, 2, 3, 4, 5, 7, 6, 1, 1, 1, 1, 1, 1, 1, 1, 7, 6, 5, 4, 3, 2, 0, 1); - break; - case 15: /* 0, 1, 2, 3, 4, 5, 6, 7 - 7 */ /* 7, 7, 7, 7, 7, 7, 7, 7 - 0 */ - RSP_VMUDM(0, 1, 2, 3, 4, 5, 6, 7, 0, 0, 0, 0, 0, 0, 0, 0, 7, 6, 5, 4, 3, 2, 1, 0); - break; + case 0: /* 0, 1, 2, 3, 4, 5, 6, 7 - none */ /* 0, 1, 2, 3, 4, 5, 6, 7 - none */ + RSP_VMUDM(0, 1, 2, 3, 4, 5, 6, 7, 7, 6, 5, 4, 3, 2, 1, 0, 7, 6, 5, 4, 3, 2, 1, 0); + break; + case 1: /* 0, 1, 2, 3, 4, 5, 6, 7 - ??? */ /* 0, 1, 2, 3, 4, 5, 6, 7 - ??? */ + RSP_VMUDM(0, 1, 2, 3, 4, 5, 6, 7, 7, 6, 5, 4, 3, 2, 1, 0, 7, 6, 5, 4, 3, 2, 1, 0); + break; + case 2: /* 1, 3, 5, 7, 0, 2, 4, 6 - 0q */ /* 0, 0, 2, 2, 4, 4, 6, 6 - 0q */ + RSP_VMUDM(1, 3, 5, 7, 0, 2, 4, 6, 7, 5, 3, 1, 7, 5, 3, 1, 6, 4, 2, 0, 7, 5, 3, 1); + break; + case 3: /* 0, 2, 4, 6, 1, 3, 5, 7 - 1q */ /* 1, 1, 3, 3, 5, 5, 7, 7 - 1q */ + RSP_VMUDM(0, 2, 4, 6, 1, 3, 5, 7, 6, 4, 2, 0, 6, 4, 2, 0, 7, 5, 3, 1, 6, 4, 2, 0); + break; + case 4: /* 1, 2, 3, 5, 6, 7, 0, 4 - 0h */ /* 0, 0, 0, 0, 4, 4, 4, 4 - 0h */ + RSP_VMUDM(1, 2, 3, 5, 6, 7, 0, 4, 7, 7, 7, 3, 3, 3, 7, 3, 6, 5, 4, 2, 1, 0, 7, 3); + break; + case 5: /* 0, 2, 3, 4, 6, 7, 1, 5 - 1h */ /* 1, 1, 1, 1, 5, 5, 5, 5 - 1h */ + RSP_VMUDM(0, 2, 3, 4, 6, 7, 1, 5, 6, 6, 6, 2, 2, 2, 6, 2, 7, 5, 4, 3, 1, 0, 6, 2); + break; + case 6: /* 0, 1, 3, 4, 5, 7, 2, 6 - 2h */ /* 2, 2, 2, 2, 6, 6, 6, 6 - 2h */ + RSP_VMUDM(0, 1, 3, 4, 5, 7, 2, 6, 5, 5, 5, 1, 1, 1, 5, 1, 7, 6, 4, 3, 2, 0, 5, 1); + break; + case 7: /* 0, 1, 2, 4, 5, 6, 3, 7 - 3h */ /* 3, 3, 3, 3, 7, 7, 7, 7 - 3h */ + RSP_VMUDM(0, 1, 2, 4, 5, 6, 3, 7, 4, 4, 4, 0, 0, 0, 4, 0, 7, 6, 5, 3, 2, 1, 4, 0); + break; + case 8: /* 1, 2, 3, 4, 5, 6, 7, 0 - 0 */ /* 0, 0, 0, 0, 0, 0, 0, 0 - 0 */ + RSP_VMUDM(1, 2, 3, 4, 5, 6, 7, 0, 7, 7, 7, 7, 7, 7, 7, 7, 6, 5, 4, 3, 2, 1, 0, 7); + break; + case 9: /* 0, 2, 3, 4, 5, 6, 7, 1 - 1 */ /* 1, 1, 1, 1, 1, 1, 1, 1 - 0 */ + RSP_VMUDM(0, 2, 3, 4, 5, 6, 7, 1, 6, 6, 6, 6, 6, 6, 6, 6, 7, 5, 4, 3, 2, 1, 0, 6); + break; + case 10: /* 0, 1, 3, 4, 5, 6, 7, 2 - 2 */ /* 2, 2, 2, 2, 2, 2, 2, 2 - 0 */ + RSP_VMUDM(0, 1, 3, 4, 5, 6, 7, 2, 5, 5, 5, 5, 5, 5, 5, 5, 7, 6, 4, 3, 2, 1, 0, 5); + break; + case 11: /* 0, 1, 2, 4, 5, 6, 7, 3 - 3 */ /* 3, 3, 3, 3, 3, 3, 3, 3 - 0 */ + RSP_VMUDM(0, 1, 2, 4, 5, 6, 7, 3, 4, 4, 4, 4, 4, 4, 4, 4, 7, 6, 5, 3, 2, 1, 0, 4); + break; + case 12: /* 0, 1, 2, 3, 5, 6, 7, 4 - 4 */ /* 4, 4, 4, 4, 4, 4, 4, 4 - 0 */ + RSP_VMUDM(0, 1, 2, 3, 5, 6, 7, 4, 3, 3, 3, 3, 3, 3, 3, 3, 7, 6, 5, 4, 2, 1, 0, 3); + break; + case 13: /* 0, 1, 2, 3, 4, 6, 7, 5 - 5 */ /* 5, 5, 5, 5, 5, 5, 5, 5 - 0 */ + RSP_VMUDM(0, 1, 2, 3, 4, 6, 7, 5, 2, 2, 2, 2, 2, 2, 2, 2, 7, 6, 5, 4, 3, 1, 0, 2); + break; + case 14: /* 0, 1, 2, 3, 4, 5, 7, 6 - 6 */ /* 6, 6, 6, 6, 6, 6, 6, 6 - 0 */ + RSP_VMUDM(0, 1, 2, 3, 4, 5, 7, 6, 1, 1, 1, 1, 1, 1, 1, 1, 7, 6, 5, 4, 3, 2, 0, 1); + break; + case 15: /* 0, 1, 2, 3, 4, 5, 6, 7 - 7 */ /* 7, 7, 7, 7, 7, 7, 7, 7 - 0 */ + RSP_VMUDM(0, 1, 2, 3, 4, 5, 6, 7, 0, 0, 0, 0, 0, 0, 0, 0, 7, 6, 5, 4, 3, 2, 1, 0); + break; } /* - for (i=0; i < 8; i++) - { - int del = VEC_EL_1(EL, i); - int sel = VEC_EL_2(EL, del); - INT32 s1 = (INT32)(INT16)R_VREG_S(VS1REG, del); - INT32 s2 = (UINT16)R_VREG_S(VS2REG, sel); // not sign-extended - INT32 r = s1 * s2; + for (i=0; i < 8; i++) + { + int del = VEC_EL_1(EL, i); + int sel = VEC_EL_2(EL, del); + INT32 s1 = (INT32)(INT16)R_VREG_S(VS1REG, del); + INT32 s2 = (UINT16)R_VREG_S(VS2REG, sel); // not sign-extended + INT32 r = s1 * s2; - W_ACCUM_H(del, (r < 0) ? 0xffff : 0); // sign-extend to 48-bit - W_ACCUM_M(del, (INT16)(r >> 16)); - W_ACCUM_L(del, (UINT16)(r)); + W_ACCUM_H(del, (r < 0) ? 0xffff : 0); // sign-extend to 48-bit + W_ACCUM_M(del, (INT16)(r >> 16)); + W_ACCUM_L(del, (UINT16)(r)); - vres[del] = ACCUM(del).h.mid; - } - WRITEBACK_RESULT(); - */ + vres[del] = ACCUM(del).h.mid; + } + WRITEBACK_RESULT(); + */ } #endif @@ -2922,54 +2922,54 @@ INLINE void cfunc_rsp_vmudn(void *param) switch(EL) { - case 0: /* 0, 1, 2, 3, 4, 5, 6, 7 - none */ /* 0, 1, 2, 3, 4, 5, 6, 7 - none */ - RSP_VMUDN(0, 1, 2, 3, 4, 5, 6, 7, 0, 1, 2, 3, 4, 5, 6, 7); - break; - case 1: /* 0, 1, 2, 3, 4, 5, 6, 7 - ??? */ /* 0, 1, 2, 3, 4, 5, 6, 7 - ??? */ - RSP_VMUDN(0, 1, 2, 3, 4, 5, 6, 7, 0, 1, 2, 3, 4, 5, 6, 7); - break; - case 2: /* 1, 3, 5, 7, 0, 2, 4, 6 - 0q */ /* 0, 0, 2, 2, 4, 4, 6, 6 - 0q */ - RSP_VMUDN(1, 3, 5, 7, 0, 2, 4, 6, 0, 2, 4, 6, 0, 2, 4, 6); - break; - case 3: /* 0, 2, 4, 6, 1, 3, 5, 7 - 1q */ /* 1, 1, 3, 3, 5, 5, 7, 7 - 1q */ - RSP_VMUDN(0, 2, 4, 6, 1, 3, 5, 7, 1, 3, 5, 7, 1, 3, 5, 7); - break; - case 4: /* 1, 2, 3, 5, 6, 7, 0, 4 - 0h */ /* 0, 0, 0, 0, 4, 4, 4, 4 - 0h */ - RSP_VMUDN(1, 2, 3, 5, 6, 7, 0, 4, 0, 0, 0, 4, 4, 4, 0, 4); - break; - case 5: /* 0, 2, 3, 4, 6, 7, 1, 5 - 1h */ /* 1, 1, 1, 1, 5, 5, 5, 5 - 1h */ - RSP_VMUDN(0, 2, 3, 4, 6, 7, 1, 5, 1, 1, 1, 5, 5, 5, 1, 5); - break; - case 6: /* 0, 1, 3, 4, 5, 7, 2, 6 - 2h */ /* 2, 2, 2, 2, 6, 6, 6, 6 - 2h */ - RSP_VMUDN(0, 1, 3, 4, 5, 7, 2, 6, 2, 2, 2, 6, 6, 6, 2, 6); - break; - case 7: /* 0, 1, 2, 4, 5, 6, 3, 7 - 3h */ /* 3, 3, 3, 3, 7, 7, 7, 7 - 3h */ - RSP_VMUDN(0, 1, 2, 4, 5, 6, 3, 7, 3, 3, 3, 7, 7, 7, 3, 7); - break; - case 8: /* 1, 2, 3, 4, 5, 6, 7, 0 - 0 */ /* 0, 0, 0, 0, 0, 0, 0, 0 - 0 */ - RSP_VMUDN(1, 2, 3, 4, 5, 6, 7, 0, 0, 0, 0, 0, 0, 0, 0, 0); - break; - case 9: /* 0, 2, 3, 4, 5, 6, 7, 1 - 1 */ /* 1, 1, 1, 1, 1, 1, 1, 1 - 0 */ - RSP_VMUDN(0, 2, 3, 4, 5, 6, 7, 1, 1, 1, 1, 1, 1, 1, 1, 1); - break; - case 10: /* 0, 1, 3, 4, 5, 6, 7, 2 - 2 */ /* 2, 2, 2, 2, 2, 2, 2, 2 - 0 */ - RSP_VMUDN(0, 1, 3, 4, 5, 6, 7, 2, 2, 2, 2, 2, 2, 2, 2, 2); - break; - case 11: /* 0, 1, 2, 4, 5, 6, 7, 3 - 3 */ /* 3, 3, 3, 3, 3, 3, 3, 3 - 0 */ - RSP_VMUDN(0, 1, 2, 4, 5, 6, 7, 3, 3, 3, 3, 3, 3, 3, 3, 3); - break; - case 12: /* 0, 1, 2, 3, 5, 6, 7, 4 - 4 */ /* 4, 4, 4, 4, 4, 4, 4, 4 - 0 */ - RSP_VMUDN(0, 1, 2, 3, 5, 6, 7, 4, 4, 4, 4, 4, 4, 4, 4, 4); - break; - case 13: /* 0, 1, 2, 3, 4, 6, 7, 5 - 5 */ /* 5, 5, 5, 5, 5, 5, 5, 5 - 0 */ - RSP_VMUDN(0, 1, 2, 3, 4, 6, 7, 5, 5, 5, 5, 5, 5, 5, 5, 5); - break; - case 14: /* 0, 1, 2, 3, 4, 5, 7, 6 - 6 */ /* 6, 6, 6, 6, 6, 6, 6, 6 - 0 */ - RSP_VMUDN(0, 1, 2, 3, 4, 5, 7, 6, 6, 6, 6, 6, 6, 6, 6, 6); - break; - case 15: /* 0, 1, 2, 3, 4, 5, 6, 7 - 7 */ /* 7, 7, 7, 7, 7, 7, 7, 7 - 0 */ - RSP_VMUDN(0, 1, 2, 3, 4, 5, 6, 7, 7, 7, 7, 7, 7, 7, 7, 7); - break; + case 0: /* 0, 1, 2, 3, 4, 5, 6, 7 - none */ /* 0, 1, 2, 3, 4, 5, 6, 7 - none */ + RSP_VMUDN(0, 1, 2, 3, 4, 5, 6, 7, 0, 1, 2, 3, 4, 5, 6, 7); + break; + case 1: /* 0, 1, 2, 3, 4, 5, 6, 7 - ??? */ /* 0, 1, 2, 3, 4, 5, 6, 7 - ??? */ + RSP_VMUDN(0, 1, 2, 3, 4, 5, 6, 7, 0, 1, 2, 3, 4, 5, 6, 7); + break; + case 2: /* 1, 3, 5, 7, 0, 2, 4, 6 - 0q */ /* 0, 0, 2, 2, 4, 4, 6, 6 - 0q */ + RSP_VMUDN(1, 3, 5, 7, 0, 2, 4, 6, 0, 2, 4, 6, 0, 2, 4, 6); + break; + case 3: /* 0, 2, 4, 6, 1, 3, 5, 7 - 1q */ /* 1, 1, 3, 3, 5, 5, 7, 7 - 1q */ + RSP_VMUDN(0, 2, 4, 6, 1, 3, 5, 7, 1, 3, 5, 7, 1, 3, 5, 7); + break; + case 4: /* 1, 2, 3, 5, 6, 7, 0, 4 - 0h */ /* 0, 0, 0, 0, 4, 4, 4, 4 - 0h */ + RSP_VMUDN(1, 2, 3, 5, 6, 7, 0, 4, 0, 0, 0, 4, 4, 4, 0, 4); + break; + case 5: /* 0, 2, 3, 4, 6, 7, 1, 5 - 1h */ /* 1, 1, 1, 1, 5, 5, 5, 5 - 1h */ + RSP_VMUDN(0, 2, 3, 4, 6, 7, 1, 5, 1, 1, 1, 5, 5, 5, 1, 5); + break; + case 6: /* 0, 1, 3, 4, 5, 7, 2, 6 - 2h */ /* 2, 2, 2, 2, 6, 6, 6, 6 - 2h */ + RSP_VMUDN(0, 1, 3, 4, 5, 7, 2, 6, 2, 2, 2, 6, 6, 6, 2, 6); + break; + case 7: /* 0, 1, 2, 4, 5, 6, 3, 7 - 3h */ /* 3, 3, 3, 3, 7, 7, 7, 7 - 3h */ + RSP_VMUDN(0, 1, 2, 4, 5, 6, 3, 7, 3, 3, 3, 7, 7, 7, 3, 7); + break; + case 8: /* 1, 2, 3, 4, 5, 6, 7, 0 - 0 */ /* 0, 0, 0, 0, 0, 0, 0, 0 - 0 */ + RSP_VMUDN(1, 2, 3, 4, 5, 6, 7, 0, 0, 0, 0, 0, 0, 0, 0, 0); + break; + case 9: /* 0, 2, 3, 4, 5, 6, 7, 1 - 1 */ /* 1, 1, 1, 1, 1, 1, 1, 1 - 0 */ + RSP_VMUDN(0, 2, 3, 4, 5, 6, 7, 1, 1, 1, 1, 1, 1, 1, 1, 1); + break; + case 10: /* 0, 1, 3, 4, 5, 6, 7, 2 - 2 */ /* 2, 2, 2, 2, 2, 2, 2, 2 - 0 */ + RSP_VMUDN(0, 1, 3, 4, 5, 6, 7, 2, 2, 2, 2, 2, 2, 2, 2, 2); + break; + case 11: /* 0, 1, 2, 4, 5, 6, 7, 3 - 3 */ /* 3, 3, 3, 3, 3, 3, 3, 3 - 0 */ + RSP_VMUDN(0, 1, 2, 4, 5, 6, 7, 3, 3, 3, 3, 3, 3, 3, 3, 3); + break; + case 12: /* 0, 1, 2, 3, 5, 6, 7, 4 - 4 */ /* 4, 4, 4, 4, 4, 4, 4, 4 - 0 */ + RSP_VMUDN(0, 1, 2, 3, 5, 6, 7, 4, 4, 4, 4, 4, 4, 4, 4, 4); + break; + case 13: /* 0, 1, 2, 3, 4, 6, 7, 5 - 5 */ /* 5, 5, 5, 5, 5, 5, 5, 5 - 0 */ + RSP_VMUDN(0, 1, 2, 3, 4, 6, 7, 5, 5, 5, 5, 5, 5, 5, 5, 5); + break; + case 14: /* 0, 1, 2, 3, 4, 5, 7, 6 - 6 */ /* 6, 6, 6, 6, 6, 6, 6, 6 - 0 */ + RSP_VMUDN(0, 1, 2, 3, 4, 5, 7, 6, 6, 6, 6, 6, 6, 6, 6, 6); + break; + case 15: /* 0, 1, 2, 3, 4, 5, 6, 7 - 7 */ /* 7, 7, 7, 7, 7, 7, 7, 7 - 0 */ + RSP_VMUDN(0, 1, 2, 3, 4, 5, 6, 7, 7, 7, 7, 7, 7, 7, 7, 7); + break; } } @@ -3051,54 +3051,54 @@ INLINE void cfunc_rsp_vmacf(void *param) switch(EL) { - case 0: /* 0, 1, 2, 3, 4, 5, 6, 7 - none */ /* 0, 1, 2, 3, 4, 5, 6, 7 - none */ - RSP_VMACF(0, 1, 2, 3, 4, 5, 6, 7, 0, 1, 2, 3, 4, 5, 6, 7); - break; - case 1: /* 0, 1, 2, 3, 4, 5, 6, 7 - ??? */ /* 0, 1, 2, 3, 4, 5, 6, 7 - ??? */ - RSP_VMACF(0, 1, 2, 3, 4, 5, 6, 7, 0, 1, 2, 3, 4, 5, 6, 7); - break; - case 2: /* 1, 3, 5, 7, 0, 2, 4, 6 - 0q */ /* 0, 0, 2, 2, 4, 4, 6, 6 - 0q */ - RSP_VMACF(1, 3, 5, 7, 0, 2, 4, 6, 0, 2, 4, 6, 0, 2, 4, 6); - break; - case 3: /* 0, 2, 4, 6, 1, 3, 5, 7 - 1q */ /* 1, 1, 3, 3, 5, 5, 7, 7 - 1q */ - RSP_VMACF(0, 2, 4, 6, 1, 3, 5, 7, 1, 3, 5, 7, 1, 3, 5, 7); - break; - case 4: /* 1, 2, 3, 5, 6, 7, 0, 4 - 0h */ /* 0, 0, 0, 0, 4, 4, 4, 4 - 0h */ - RSP_VMACF(1, 2, 3, 5, 6, 7, 0, 4, 0, 0, 0, 4, 4, 4, 0, 4); - break; - case 5: /* 0, 2, 3, 4, 6, 7, 1, 5 - 1h */ /* 1, 1, 1, 1, 5, 5, 5, 5 - 1h */ - RSP_VMACF(0, 2, 3, 4, 6, 7, 1, 5, 1, 1, 1, 5, 5, 5, 1, 5); - break; - case 6: /* 0, 1, 3, 4, 5, 7, 2, 6 - 2h */ /* 2, 2, 2, 2, 6, 6, 6, 6 - 2h */ - RSP_VMACF(0, 1, 3, 4, 5, 7, 2, 6, 2, 2, 2, 6, 6, 6, 2, 6); - break; - case 7: /* 0, 1, 2, 4, 5, 6, 3, 7 - 3h */ /* 3, 3, 3, 3, 7, 7, 7, 7 - 3h */ - RSP_VMACF(0, 1, 2, 4, 5, 6, 3, 7, 3, 3, 3, 7, 7, 7, 3, 7); - break; - case 8: /* 1, 2, 3, 4, 5, 6, 7, 0 - 0 */ /* 0, 0, 0, 0, 0, 0, 0, 0 - 0 */ - RSP_VMACF(1, 2, 3, 4, 5, 6, 7, 0, 0, 0, 0, 0, 0, 0, 0, 0); - break; - case 9: /* 0, 2, 3, 4, 5, 6, 7, 1 - 1 */ /* 1, 1, 1, 1, 1, 1, 1, 1 - 0 */ - RSP_VMACF(0, 2, 3, 4, 5, 6, 7, 1, 1, 1, 1, 1, 1, 1, 1, 1); - break; - case 10: /* 0, 1, 3, 4, 5, 6, 7, 2 - 2 */ /* 2, 2, 2, 2, 2, 2, 2, 2 - 0 */ - RSP_VMACF(0, 1, 3, 4, 5, 6, 7, 2, 2, 2, 2, 2, 2, 2, 2, 2); - break; - case 11: /* 0, 1, 2, 4, 5, 6, 7, 3 - 3 */ /* 3, 3, 3, 3, 3, 3, 3, 3 - 0 */ - RSP_VMACF(0, 1, 2, 4, 5, 6, 7, 3, 3, 3, 3, 3, 3, 3, 3, 3); - break; - case 12: /* 0, 1, 2, 3, 5, 6, 7, 4 - 4 */ /* 4, 4, 4, 4, 4, 4, 4, 4 - 0 */ - RSP_VMACF(0, 1, 2, 3, 5, 6, 7, 4, 4, 4, 4, 4, 4, 4, 4, 4); - break; - case 13: /* 0, 1, 2, 3, 4, 6, 7, 5 - 5 */ /* 5, 5, 5, 5, 5, 5, 5, 5 - 0 */ - RSP_VMACF(0, 1, 2, 3, 4, 6, 7, 5, 5, 5, 5, 5, 5, 5, 5, 5); - break; - case 14: /* 0, 1, 2, 3, 4, 5, 7, 6 - 6 */ /* 6, 6, 6, 6, 6, 6, 6, 6 - 0 */ - RSP_VMACF(0, 1, 2, 3, 4, 5, 7, 6, 6, 6, 6, 6, 6, 6, 6, 6); - break; - case 15: /* 0, 1, 2, 3, 4, 5, 6, 7 - 7 */ /* 7, 7, 7, 7, 7, 7, 7, 7 - 0 */ - RSP_VMACF(0, 1, 2, 3, 4, 5, 6, 7, 7, 7, 7, 7, 7, 7, 7, 7); - break; + case 0: /* 0, 1, 2, 3, 4, 5, 6, 7 - none */ /* 0, 1, 2, 3, 4, 5, 6, 7 - none */ + RSP_VMACF(0, 1, 2, 3, 4, 5, 6, 7, 0, 1, 2, 3, 4, 5, 6, 7); + break; + case 1: /* 0, 1, 2, 3, 4, 5, 6, 7 - ??? */ /* 0, 1, 2, 3, 4, 5, 6, 7 - ??? */ + RSP_VMACF(0, 1, 2, 3, 4, 5, 6, 7, 0, 1, 2, 3, 4, 5, 6, 7); + break; + case 2: /* 1, 3, 5, 7, 0, 2, 4, 6 - 0q */ /* 0, 0, 2, 2, 4, 4, 6, 6 - 0q */ + RSP_VMACF(1, 3, 5, 7, 0, 2, 4, 6, 0, 2, 4, 6, 0, 2, 4, 6); + break; + case 3: /* 0, 2, 4, 6, 1, 3, 5, 7 - 1q */ /* 1, 1, 3, 3, 5, 5, 7, 7 - 1q */ + RSP_VMACF(0, 2, 4, 6, 1, 3, 5, 7, 1, 3, 5, 7, 1, 3, 5, 7); + break; + case 4: /* 1, 2, 3, 5, 6, 7, 0, 4 - 0h */ /* 0, 0, 0, 0, 4, 4, 4, 4 - 0h */ + RSP_VMACF(1, 2, 3, 5, 6, 7, 0, 4, 0, 0, 0, 4, 4, 4, 0, 4); + break; + case 5: /* 0, 2, 3, 4, 6, 7, 1, 5 - 1h */ /* 1, 1, 1, 1, 5, 5, 5, 5 - 1h */ + RSP_VMACF(0, 2, 3, 4, 6, 7, 1, 5, 1, 1, 1, 5, 5, 5, 1, 5); + break; + case 6: /* 0, 1, 3, 4, 5, 7, 2, 6 - 2h */ /* 2, 2, 2, 2, 6, 6, 6, 6 - 2h */ + RSP_VMACF(0, 1, 3, 4, 5, 7, 2, 6, 2, 2, 2, 6, 6, 6, 2, 6); + break; + case 7: /* 0, 1, 2, 4, 5, 6, 3, 7 - 3h */ /* 3, 3, 3, 3, 7, 7, 7, 7 - 3h */ + RSP_VMACF(0, 1, 2, 4, 5, 6, 3, 7, 3, 3, 3, 7, 7, 7, 3, 7); + break; + case 8: /* 1, 2, 3, 4, 5, 6, 7, 0 - 0 */ /* 0, 0, 0, 0, 0, 0, 0, 0 - 0 */ + RSP_VMACF(1, 2, 3, 4, 5, 6, 7, 0, 0, 0, 0, 0, 0, 0, 0, 0); + break; + case 9: /* 0, 2, 3, 4, 5, 6, 7, 1 - 1 */ /* 1, 1, 1, 1, 1, 1, 1, 1 - 0 */ + RSP_VMACF(0, 2, 3, 4, 5, 6, 7, 1, 1, 1, 1, 1, 1, 1, 1, 1); + break; + case 10: /* 0, 1, 3, 4, 5, 6, 7, 2 - 2 */ /* 2, 2, 2, 2, 2, 2, 2, 2 - 0 */ + RSP_VMACF(0, 1, 3, 4, 5, 6, 7, 2, 2, 2, 2, 2, 2, 2, 2, 2); + break; + case 11: /* 0, 1, 2, 4, 5, 6, 7, 3 - 3 */ /* 3, 3, 3, 3, 3, 3, 3, 3 - 0 */ + RSP_VMACF(0, 1, 2, 4, 5, 6, 7, 3, 3, 3, 3, 3, 3, 3, 3, 3); + break; + case 12: /* 0, 1, 2, 3, 5, 6, 7, 4 - 4 */ /* 4, 4, 4, 4, 4, 4, 4, 4 - 0 */ + RSP_VMACF(0, 1, 2, 3, 5, 6, 7, 4, 4, 4, 4, 4, 4, 4, 4, 4); + break; + case 13: /* 0, 1, 2, 3, 4, 6, 7, 5 - 5 */ /* 5, 5, 5, 5, 5, 5, 5, 5 - 0 */ + RSP_VMACF(0, 1, 2, 3, 4, 6, 7, 5, 5, 5, 5, 5, 5, 5, 5, 5); + break; + case 14: /* 0, 1, 2, 3, 4, 5, 7, 6 - 6 */ /* 6, 6, 6, 6, 6, 6, 6, 6 - 0 */ + RSP_VMACF(0, 1, 2, 3, 4, 5, 7, 6, 6, 6, 6, 6, 6, 6, 6, 6); + break; + case 15: /* 0, 1, 2, 3, 4, 5, 6, 7 - 7 */ /* 7, 7, 7, 7, 7, 7, 7, 7 - 0 */ + RSP_VMACF(0, 1, 2, 3, 4, 5, 6, 7, 7, 7, 7, 7, 7, 7, 7, 7); + break; } #if 0 for (i=0; i < 8; i++) @@ -3218,86 +3218,86 @@ INLINE void cfunc_rsp_vmadl(void *param) #define RSP_VMADM_DRC(E10, E11, E12, E13, E14, E15, E16, E17, E20, E21, E22, E23, E24, E25, E26, E27, I0, I1, I2, I3, I4, I5, I6, I7) \ { \ - UML_SEXT(block, IREG(0), VS(VS1REG, I0), WORD); \ - UML_SEXT(block, IREG(1), VS(VS2REG, E20), WORD); \ - UML_AND(block, IREG(1), IREG(1), IMM(0x0000ffff)); \ + UML_SEXT(block, IREG(0), VS(VS1REG, I0), WORD); \ + UML_SEXT(block, IREG(1), VS(VS2REG, E20), WORD); \ + UML_AND(block, IREG(1), IREG(1), IMM(0x0000ffff)); \ UML_MULS(block, IREG(0), IREG(1), IREG(0), IREG(1)); \ UML_DSEXT(block, IREG(0), IREG(0), DWORD); \ UML_DSHL(block, IREG(0), IREG(0), IMM(16)); \ UML_DADD(block, VACCUML(E10), VACCUML(E10), IREG(0)); \ \ - UML_SEXT(block, IREG(0), VS(VS1REG, I1), WORD); \ - UML_SEXT(block, IREG(1), VS(VS2REG, E21), WORD); \ - UML_AND(block, IREG(1), IREG(1), IMM(0x0000ffff)); \ + UML_SEXT(block, IREG(0), VS(VS1REG, I1), WORD); \ + UML_SEXT(block, IREG(1), VS(VS2REG, E21), WORD); \ + UML_AND(block, IREG(1), IREG(1), IMM(0x0000ffff)); \ UML_MULS(block, IREG(0), IREG(1), IREG(0), IREG(1)); \ UML_DSEXT(block, IREG(0), IREG(0), DWORD); \ UML_DSHL(block, IREG(0), IREG(0), IMM(16)); \ UML_DADD(block, VACCUML(E11), VACCUML(E11), IREG(0)); \ \ - UML_SEXT(block, IREG(0), VS(VS1REG, I2), WORD); \ - UML_SEXT(block, IREG(1), VS(VS2REG, E22), WORD); \ - UML_AND(block, IREG(1), IREG(1), IMM(0x0000ffff)); \ + UML_SEXT(block, IREG(0), VS(VS1REG, I2), WORD); \ + UML_SEXT(block, IREG(1), VS(VS2REG, E22), WORD); \ + UML_AND(block, IREG(1), IREG(1), IMM(0x0000ffff)); \ UML_MULS(block, IREG(0), IREG(1), IREG(0), IREG(1)); \ UML_DSEXT(block, IREG(0), IREG(0), DWORD); \ UML_DSHL(block, IREG(0), IREG(0), IMM(16)); \ UML_DADD(block, VACCUML(E12), VACCUML(E12), IREG(0)); \ \ - UML_SEXT(block, IREG(0), VS(VS1REG, I3), WORD); \ - UML_SEXT(block, IREG(1), VS(VS2REG, E23), WORD); \ - UML_AND(block, IREG(1), IREG(1), IMM(0x0000ffff)); \ + UML_SEXT(block, IREG(0), VS(VS1REG, I3), WORD); \ + UML_SEXT(block, IREG(1), VS(VS2REG, E23), WORD); \ + UML_AND(block, IREG(1), IREG(1), IMM(0x0000ffff)); \ UML_MULS(block, IREG(0), IREG(1), IREG(0), IREG(1)); \ UML_DSEXT(block, IREG(0), IREG(0), DWORD); \ UML_DSHL(block, IREG(0), IREG(0), IMM(16)); \ UML_DADD(block, VACCUML(E13), VACCUML(E13), IREG(0)); \ \ - UML_SEXT(block, IREG(0), VS(VS1REG, I4), WORD); \ - UML_SEXT(block, IREG(1), VS(VS2REG, E24), WORD); \ - UML_AND(block, IREG(1), IREG(1), IMM(0x0000ffff)); \ + UML_SEXT(block, IREG(0), VS(VS1REG, I4), WORD); \ + UML_SEXT(block, IREG(1), VS(VS2REG, E24), WORD); \ + UML_AND(block, IREG(1), IREG(1), IMM(0x0000ffff)); \ UML_MULS(block, IREG(0), IREG(1), IREG(0), IREG(1)); \ UML_DSEXT(block, IREG(0), IREG(0), DWORD); \ UML_DSHL(block, IREG(0), IREG(0), IMM(16)); \ UML_DADD(block, VACCUML(E14), VACCUML(E14), IREG(0)); \ \ - UML_SEXT(block, IREG(0), VS(VS1REG, I5), WORD); \ - UML_SEXT(block, IREG(1), VS(VS2REG, E25), WORD); \ - UML_AND(block, IREG(1), IREG(1), IMM(0x0000ffff)); \ + UML_SEXT(block, IREG(0), VS(VS1REG, I5), WORD); \ + UML_SEXT(block, IREG(1), VS(VS2REG, E25), WORD); \ + UML_AND(block, IREG(1), IREG(1), IMM(0x0000ffff)); \ UML_MULS(block, IREG(0), IREG(1), IREG(0), IREG(1)); \ UML_DSEXT(block, IREG(0), IREG(0), DWORD); \ UML_DSHL(block, IREG(0), IREG(0), IMM(16)); \ UML_DADD(block, VACCUML(E15), VACCUML(E15), IREG(0)); \ \ - UML_SEXT(block, IREG(0), VS(VS1REG, I6), WORD); \ - UML_SEXT(block, IREG(1), VS(VS2REG, E26), WORD); \ - UML_AND(block, IREG(1), IREG(1), IMM(0x0000ffff)); \ + UML_SEXT(block, IREG(0), VS(VS1REG, I6), WORD); \ + UML_SEXT(block, IREG(1), VS(VS2REG, E26), WORD); \ + UML_AND(block, IREG(1), IREG(1), IMM(0x0000ffff)); \ UML_MULS(block, IREG(0), IREG(1), IREG(0), IREG(1)); \ UML_DSEXT(block, IREG(0), IREG(0), DWORD); \ UML_DSHL(block, IREG(0), IREG(0), IMM(16)); \ UML_DADD(block, VACCUML(E16), VACCUML(E16), IREG(0)); \ \ - UML_SEXT(block, IREG(0), VS(VS1REG, I7), WORD); \ - UML_SEXT(block, IREG(1), VS(VS2REG, E27), WORD); \ - UML_AND(block, IREG(1), IREG(1), IMM(0x0000ffff)); \ + UML_SEXT(block, IREG(0), VS(VS1REG, I7), WORD); \ + UML_SEXT(block, IREG(1), VS(VS2REG, E27), WORD); \ + UML_AND(block, IREG(1), IREG(1), IMM(0x0000ffff)); \ UML_MULS(block, IREG(0), IREG(1), IREG(0), IREG(1)); \ UML_DSEXT(block, IREG(0), IREG(0), DWORD); \ UML_DSHL(block, IREG(0), IREG(0), IMM(16)); \ UML_DADD(block, VACCUML(E17), VACCUML(E17), IREG(0)); \ \ - generate_saturate_accum_signed(rsp, block, compiler, desc, E10); \ - UML_STORE(block, &rsp->v[VDREG].s[I0], IMM(0), IREG(0), WORD); \ - generate_saturate_accum_signed(rsp, block, compiler, desc, E11); \ - UML_STORE(block, &rsp->v[VDREG].s[I1], IMM(0), IREG(0), WORD); \ - generate_saturate_accum_signed(rsp, block, compiler, desc, E12); \ - UML_STORE(block, &rsp->v[VDREG].s[I2], IMM(0), IREG(0), WORD); \ - generate_saturate_accum_signed(rsp, block, compiler, desc, E13); \ - UML_STORE(block, &rsp->v[VDREG].s[I3], IMM(0), IREG(0), WORD); \ - generate_saturate_accum_signed(rsp, block, compiler, desc, E14); \ - UML_STORE(block, &rsp->v[VDREG].s[I4], IMM(0), IREG(0), WORD); \ - generate_saturate_accum_signed(rsp, block, compiler, desc, E15); \ - UML_STORE(block, &rsp->v[VDREG].s[I5], IMM(0), IREG(0), WORD); \ - generate_saturate_accum_signed(rsp, block, compiler, desc, E16); \ - UML_STORE(block, &rsp->v[VDREG].s[I6], IMM(0), IREG(0), WORD); \ - generate_saturate_accum_signed(rsp, block, compiler, desc, E17); \ - UML_STORE(block, &rsp->v[VDREG].s[I7], IMM(0), IREG(0), WORD); \ + generate_saturate_accum_signed(rsp, block, compiler, desc, E10); \ + UML_STORE(block, &rsp->v[VDREG].s[I0], IMM(0), IREG(0), WORD); \ + generate_saturate_accum_signed(rsp, block, compiler, desc, E11); \ + UML_STORE(block, &rsp->v[VDREG].s[I1], IMM(0), IREG(0), WORD); \ + generate_saturate_accum_signed(rsp, block, compiler, desc, E12); \ + UML_STORE(block, &rsp->v[VDREG].s[I2], IMM(0), IREG(0), WORD); \ + generate_saturate_accum_signed(rsp, block, compiler, desc, E13); \ + UML_STORE(block, &rsp->v[VDREG].s[I3], IMM(0), IREG(0), WORD); \ + generate_saturate_accum_signed(rsp, block, compiler, desc, E14); \ + UML_STORE(block, &rsp->v[VDREG].s[I4], IMM(0), IREG(0), WORD); \ + generate_saturate_accum_signed(rsp, block, compiler, desc, E15); \ + UML_STORE(block, &rsp->v[VDREG].s[I5], IMM(0), IREG(0), WORD); \ + generate_saturate_accum_signed(rsp, block, compiler, desc, E16); \ + UML_STORE(block, &rsp->v[VDREG].s[I6], IMM(0), IREG(0), WORD); \ + generate_saturate_accum_signed(rsp, block, compiler, desc, E17); \ + UML_STORE(block, &rsp->v[VDREG].s[I7], IMM(0), IREG(0), WORD); \ } static int generate_vmadm(rsp_state *rsp, drcuml_block *block, compiler_state *compiler, const opcode_desc *desc) // vmadm @@ -3314,54 +3314,54 @@ static int generate_vmadm(rsp_state *rsp, drcuml_block *block, compiler_state *c // The middle slice of accumulator is stored into destination element switch(EL) { - case 0: /* 0, 1, 2, 3, 4, 5, 6, 7 - none */ /* 0, 1, 2, 3, 4, 5, 6, 7 - none */ - RSP_VMADM_DRC(0, 1, 2, 3, 4, 5, 6, 7, 7, 6, 5, 4, 3, 2, 1, 0, 7, 6, 5, 4, 3, 2, 1, 0); - return TRUE; - case 1: /* 0, 1, 2, 3, 4, 5, 6, 7 - ??? */ /* 0, 1, 2, 3, 4, 5, 6, 7 - ??? */ - RSP_VMADM_DRC(0, 1, 2, 3, 4, 5, 6, 7, 7, 6, 5, 4, 3, 2, 1, 0, 7, 6, 5, 4, 3, 2, 1, 0); - return TRUE; - case 2: /* 1, 3, 5, 7, 0, 2, 4, 6 - 0q */ /* 0, 0, 2, 2, 4, 4, 6, 6 - 0q */ - RSP_VMADM_DRC(1, 3, 5, 7, 0, 2, 4, 6, 7, 5, 3, 1, 7, 5, 3, 1, 6, 4, 2, 0, 7, 5, 3, 1); - return TRUE; - case 3: /* 0, 2, 4, 6, 1, 3, 5, 7 - 1q */ /* 1, 1, 3, 3, 5, 5, 7, 7 - 1q */ - RSP_VMADM_DRC(0, 2, 4, 6, 1, 3, 5, 7, 6, 4, 2, 0, 6, 4, 2, 0, 7, 5, 3, 1, 6, 4, 2, 0); - return TRUE; - case 4: /* 1, 2, 3, 5, 6, 7, 0, 4 - 0h */ /* 0, 0, 0, 0, 4, 4, 4, 4 - 0h */ - RSP_VMADM_DRC(1, 2, 3, 5, 6, 7, 0, 4, 7, 7, 7, 3, 3, 3, 7, 3, 6, 5, 4, 2, 1, 0, 7, 3); - return TRUE; - case 5: /* 0, 2, 3, 4, 6, 7, 1, 5 - 1h */ /* 1, 1, 1, 1, 5, 5, 5, 5 - 1h */ - RSP_VMADM_DRC(0, 2, 3, 4, 6, 7, 1, 5, 6, 6, 6, 2, 2, 2, 6, 2, 7, 5, 4, 3, 1, 0, 6, 2); - return TRUE; - case 6: /* 0, 1, 3, 4, 5, 7, 2, 6 - 2h */ /* 2, 2, 2, 2, 6, 6, 6, 6 - 2h */ - RSP_VMADM_DRC(0, 1, 3, 4, 5, 7, 2, 6, 5, 5, 5, 1, 1, 1, 5, 1, 7, 6, 4, 3, 2, 0, 5, 1); - return TRUE; - case 7: /* 0, 1, 2, 4, 5, 6, 3, 7 - 3h */ /* 3, 3, 3, 3, 7, 7, 7, 7 - 3h */ - RSP_VMADM_DRC(0, 1, 2, 4, 5, 6, 3, 7, 4, 4, 4, 0, 0, 0, 4, 0, 7, 6, 5, 3, 2, 1, 4, 0); - return TRUE; - case 8: /* 1, 2, 3, 4, 5, 6, 7, 0 - 0 */ /* 0, 0, 0, 0, 0, 0, 0, 0 - 0 */ - RSP_VMADM_DRC(1, 2, 3, 4, 5, 6, 7, 0, 7, 7, 7, 7, 7, 7, 7, 7, 6, 5, 4, 3, 2, 1, 0, 7); - return TRUE; - case 9: /* 0, 2, 3, 4, 5, 6, 7, 1 - 1 */ /* 1, 1, 1, 1, 1, 1, 1, 1 - 0 */ - RSP_VMADM_DRC(0, 2, 3, 4, 5, 6, 7, 1, 6, 6, 6, 6, 6, 6, 6, 6, 7, 5, 4, 3, 2, 1, 0, 6); - return TRUE; - case 10: /* 0, 1, 3, 4, 5, 6, 7, 2 - 2 */ /* 2, 2, 2, 2, 2, 2, 2, 2 - 0 */ - RSP_VMADM_DRC(0, 1, 3, 4, 5, 6, 7, 2, 5, 5, 5, 5, 5, 5, 5, 5, 7, 6, 4, 3, 2, 1, 0, 5); - return TRUE; - case 11: /* 0, 1, 2, 4, 5, 6, 7, 3 - 3 */ /* 3, 3, 3, 3, 3, 3, 3, 3 - 0 */ - RSP_VMADM_DRC(0, 1, 2, 4, 5, 6, 7, 3, 4, 4, 4, 4, 4, 4, 4, 4, 7, 6, 5, 3, 2, 1, 0, 4); - return TRUE; - case 12: /* 0, 1, 2, 3, 5, 6, 7, 4 - 4 */ /* 4, 4, 4, 4, 4, 4, 4, 4 - 0 */ - RSP_VMADM_DRC(0, 1, 2, 3, 5, 6, 7, 4, 3, 3, 3, 3, 3, 3, 3, 3, 7, 6, 5, 4, 2, 1, 0, 3); - return TRUE; - case 13: /* 0, 1, 2, 3, 4, 6, 7, 5 - 5 */ /* 5, 5, 5, 5, 5, 5, 5, 5 - 0 */ - RSP_VMADM_DRC(0, 1, 2, 3, 4, 6, 7, 5, 2, 2, 2, 2, 2, 2, 2, 2, 7, 6, 5, 4, 3, 1, 0, 2); - return TRUE; - case 14: /* 0, 1, 2, 3, 4, 5, 7, 6 - 6 */ /* 6, 6, 6, 6, 6, 6, 6, 6 - 0 */ - RSP_VMADM_DRC(0, 1, 2, 3, 4, 5, 7, 6, 1, 1, 1, 1, 1, 1, 1, 1, 7, 6, 5, 4, 3, 2, 0, 1); - return TRUE; - case 15: /* 0, 1, 2, 3, 4, 5, 6, 7 - 7 */ /* 7, 7, 7, 7, 7, 7, 7, 7 - 0 */ - RSP_VMADM_DRC(0, 1, 2, 3, 4, 5, 6, 7, 0, 0, 0, 0, 0, 0, 0, 0, 7, 6, 5, 4, 3, 2, 1, 0); - return TRUE; + case 0: /* 0, 1, 2, 3, 4, 5, 6, 7 - none */ /* 0, 1, 2, 3, 4, 5, 6, 7 - none */ + RSP_VMADM_DRC(0, 1, 2, 3, 4, 5, 6, 7, 7, 6, 5, 4, 3, 2, 1, 0, 7, 6, 5, 4, 3, 2, 1, 0); + return TRUE; + case 1: /* 0, 1, 2, 3, 4, 5, 6, 7 - ??? */ /* 0, 1, 2, 3, 4, 5, 6, 7 - ??? */ + RSP_VMADM_DRC(0, 1, 2, 3, 4, 5, 6, 7, 7, 6, 5, 4, 3, 2, 1, 0, 7, 6, 5, 4, 3, 2, 1, 0); + return TRUE; + case 2: /* 1, 3, 5, 7, 0, 2, 4, 6 - 0q */ /* 0, 0, 2, 2, 4, 4, 6, 6 - 0q */ + RSP_VMADM_DRC(1, 3, 5, 7, 0, 2, 4, 6, 7, 5, 3, 1, 7, 5, 3, 1, 6, 4, 2, 0, 7, 5, 3, 1); + return TRUE; + case 3: /* 0, 2, 4, 6, 1, 3, 5, 7 - 1q */ /* 1, 1, 3, 3, 5, 5, 7, 7 - 1q */ + RSP_VMADM_DRC(0, 2, 4, 6, 1, 3, 5, 7, 6, 4, 2, 0, 6, 4, 2, 0, 7, 5, 3, 1, 6, 4, 2, 0); + return TRUE; + case 4: /* 1, 2, 3, 5, 6, 7, 0, 4 - 0h */ /* 0, 0, 0, 0, 4, 4, 4, 4 - 0h */ + RSP_VMADM_DRC(1, 2, 3, 5, 6, 7, 0, 4, 7, 7, 7, 3, 3, 3, 7, 3, 6, 5, 4, 2, 1, 0, 7, 3); + return TRUE; + case 5: /* 0, 2, 3, 4, 6, 7, 1, 5 - 1h */ /* 1, 1, 1, 1, 5, 5, 5, 5 - 1h */ + RSP_VMADM_DRC(0, 2, 3, 4, 6, 7, 1, 5, 6, 6, 6, 2, 2, 2, 6, 2, 7, 5, 4, 3, 1, 0, 6, 2); + return TRUE; + case 6: /* 0, 1, 3, 4, 5, 7, 2, 6 - 2h */ /* 2, 2, 2, 2, 6, 6, 6, 6 - 2h */ + RSP_VMADM_DRC(0, 1, 3, 4, 5, 7, 2, 6, 5, 5, 5, 1, 1, 1, 5, 1, 7, 6, 4, 3, 2, 0, 5, 1); + return TRUE; + case 7: /* 0, 1, 2, 4, 5, 6, 3, 7 - 3h */ /* 3, 3, 3, 3, 7, 7, 7, 7 - 3h */ + RSP_VMADM_DRC(0, 1, 2, 4, 5, 6, 3, 7, 4, 4, 4, 0, 0, 0, 4, 0, 7, 6, 5, 3, 2, 1, 4, 0); + return TRUE; + case 8: /* 1, 2, 3, 4, 5, 6, 7, 0 - 0 */ /* 0, 0, 0, 0, 0, 0, 0, 0 - 0 */ + RSP_VMADM_DRC(1, 2, 3, 4, 5, 6, 7, 0, 7, 7, 7, 7, 7, 7, 7, 7, 6, 5, 4, 3, 2, 1, 0, 7); + return TRUE; + case 9: /* 0, 2, 3, 4, 5, 6, 7, 1 - 1 */ /* 1, 1, 1, 1, 1, 1, 1, 1 - 0 */ + RSP_VMADM_DRC(0, 2, 3, 4, 5, 6, 7, 1, 6, 6, 6, 6, 6, 6, 6, 6, 7, 5, 4, 3, 2, 1, 0, 6); + return TRUE; + case 10: /* 0, 1, 3, 4, 5, 6, 7, 2 - 2 */ /* 2, 2, 2, 2, 2, 2, 2, 2 - 0 */ + RSP_VMADM_DRC(0, 1, 3, 4, 5, 6, 7, 2, 5, 5, 5, 5, 5, 5, 5, 5, 7, 6, 4, 3, 2, 1, 0, 5); + return TRUE; + case 11: /* 0, 1, 2, 4, 5, 6, 7, 3 - 3 */ /* 3, 3, 3, 3, 3, 3, 3, 3 - 0 */ + RSP_VMADM_DRC(0, 1, 2, 4, 5, 6, 7, 3, 4, 4, 4, 4, 4, 4, 4, 4, 7, 6, 5, 3, 2, 1, 0, 4); + return TRUE; + case 12: /* 0, 1, 2, 3, 5, 6, 7, 4 - 4 */ /* 4, 4, 4, 4, 4, 4, 4, 4 - 0 */ + RSP_VMADM_DRC(0, 1, 2, 3, 5, 6, 7, 4, 3, 3, 3, 3, 3, 3, 3, 3, 7, 6, 5, 4, 2, 1, 0, 3); + return TRUE; + case 13: /* 0, 1, 2, 3, 4, 6, 7, 5 - 5 */ /* 5, 5, 5, 5, 5, 5, 5, 5 - 0 */ + RSP_VMADM_DRC(0, 1, 2, 3, 4, 6, 7, 5, 2, 2, 2, 2, 2, 2, 2, 2, 7, 6, 5, 4, 3, 1, 0, 2); + return TRUE; + case 14: /* 0, 1, 2, 3, 4, 5, 7, 6 - 6 */ /* 6, 6, 6, 6, 6, 6, 6, 6 - 0 */ + RSP_VMADM_DRC(0, 1, 2, 3, 4, 5, 7, 6, 1, 1, 1, 1, 1, 1, 1, 1, 7, 6, 5, 4, 3, 2, 0, 1); + return TRUE; + case 15: /* 0, 1, 2, 3, 4, 5, 6, 7 - 7 */ /* 7, 7, 7, 7, 7, 7, 7, 7 - 0 */ + RSP_VMADM_DRC(0, 1, 2, 3, 4, 5, 6, 7, 0, 0, 0, 0, 0, 0, 0, 0, 7, 6, 5, 4, 3, 2, 1, 0); + return TRUE; } return TRUE; @@ -3411,54 +3411,54 @@ INLINE void cfunc_rsp_vmadm(void *param) switch(EL) { - case 0: /* 0, 1, 2, 3, 4, 5, 6, 7 - none */ /* 0, 1, 2, 3, 4, 5, 6, 7 - none */ - RSP_VMADM(0, 1, 2, 3, 4, 5, 6, 7, 0, 1, 2, 3, 4, 5, 6, 7); - break; - case 1: /* 0, 1, 2, 3, 4, 5, 6, 7 - ??? */ /* 0, 1, 2, 3, 4, 5, 6, 7 - ??? */ - RSP_VMADM(0, 1, 2, 3, 4, 5, 6, 7, 0, 1, 2, 3, 4, 5, 6, 7); - break; - case 2: /* 1, 3, 5, 7, 0, 2, 4, 6 - 0q */ /* 0, 0, 2, 2, 4, 4, 6, 6 - 0q */ - RSP_VMADM(1, 3, 5, 7, 0, 2, 4, 6, 0, 2, 4, 6, 0, 2, 4, 6); - break; - case 3: /* 0, 2, 4, 6, 1, 3, 5, 7 - 1q */ /* 1, 1, 3, 3, 5, 5, 7, 7 - 1q */ - RSP_VMADM(0, 2, 4, 6, 1, 3, 5, 7, 1, 3, 5, 7, 1, 3, 5, 7); - break; - case 4: /* 1, 2, 3, 5, 6, 7, 0, 4 - 0h */ /* 0, 0, 0, 0, 4, 4, 4, 4 - 0h */ - RSP_VMADM(1, 2, 3, 5, 6, 7, 0, 4, 0, 0, 0, 4, 4, 4, 0, 4); - break; - case 5: /* 0, 2, 3, 4, 6, 7, 1, 5 - 1h */ /* 1, 1, 1, 1, 5, 5, 5, 5 - 1h */ - RSP_VMADM(0, 2, 3, 4, 6, 7, 1, 5, 1, 1, 1, 5, 5, 5, 1, 5); - break; - case 6: /* 0, 1, 3, 4, 5, 7, 2, 6 - 2h */ /* 2, 2, 2, 2, 6, 6, 6, 6 - 2h */ - RSP_VMADM(0, 1, 3, 4, 5, 7, 2, 6, 2, 2, 2, 6, 6, 6, 2, 6); - break; - case 7: /* 0, 1, 2, 4, 5, 6, 3, 7 - 3h */ /* 3, 3, 3, 3, 7, 7, 7, 7 - 3h */ - RSP_VMADM(0, 1, 2, 4, 5, 6, 3, 7, 3, 3, 3, 7, 7, 7, 3, 7); - break; - case 8: /* 1, 2, 3, 4, 5, 6, 7, 0 - 0 */ /* 0, 0, 0, 0, 0, 0, 0, 0 - 0 */ - RSP_VMADM(1, 2, 3, 4, 5, 6, 7, 0, 0, 0, 0, 0, 0, 0, 0, 0); - break; - case 9: /* 0, 2, 3, 4, 5, 6, 7, 1 - 1 */ /* 1, 1, 1, 1, 1, 1, 1, 1 - 0 */ - RSP_VMADM(0, 2, 3, 4, 5, 6, 7, 1, 1, 1, 1, 1, 1, 1, 1, 1); - break; - case 10: /* 0, 1, 3, 4, 5, 6, 7, 2 - 2 */ /* 2, 2, 2, 2, 2, 2, 2, 2 - 0 */ - RSP_VMADM(0, 1, 3, 4, 5, 6, 7, 2, 2, 2, 2, 2, 2, 2, 2, 2); - break; - case 11: /* 0, 1, 2, 4, 5, 6, 7, 3 - 3 */ /* 3, 3, 3, 3, 3, 3, 3, 3 - 0 */ - RSP_VMADM(0, 1, 2, 4, 5, 6, 7, 3, 3, 3, 3, 3, 3, 3, 3, 3); - break; - case 12: /* 0, 1, 2, 3, 5, 6, 7, 4 - 4 */ /* 4, 4, 4, 4, 4, 4, 4, 4 - 0 */ - RSP_VMADM(0, 1, 2, 3, 5, 6, 7, 4, 4, 4, 4, 4, 4, 4, 4, 4); - break; - case 13: /* 0, 1, 2, 3, 4, 6, 7, 5 - 5 */ /* 5, 5, 5, 5, 5, 5, 5, 5 - 0 */ - RSP_VMADM(0, 1, 2, 3, 4, 6, 7, 5, 5, 5, 5, 5, 5, 5, 5, 5); - break; - case 14: /* 0, 1, 2, 3, 4, 5, 7, 6 - 6 */ /* 6, 6, 6, 6, 6, 6, 6, 6 - 0 */ - RSP_VMADM(0, 1, 2, 3, 4, 5, 7, 6, 6, 6, 6, 6, 6, 6, 6, 6); - break; - case 15: /* 0, 1, 2, 3, 4, 5, 6, 7 - 7 */ /* 7, 7, 7, 7, 7, 7, 7, 7 - 0 */ - RSP_VMADM(0, 1, 2, 3, 4, 5, 6, 7, 7, 7, 7, 7, 7, 7, 7, 7); - break; + case 0: /* 0, 1, 2, 3, 4, 5, 6, 7 - none */ /* 0, 1, 2, 3, 4, 5, 6, 7 - none */ + RSP_VMADM(0, 1, 2, 3, 4, 5, 6, 7, 0, 1, 2, 3, 4, 5, 6, 7); + break; + case 1: /* 0, 1, 2, 3, 4, 5, 6, 7 - ??? */ /* 0, 1, 2, 3, 4, 5, 6, 7 - ??? */ + RSP_VMADM(0, 1, 2, 3, 4, 5, 6, 7, 0, 1, 2, 3, 4, 5, 6, 7); + break; + case 2: /* 1, 3, 5, 7, 0, 2, 4, 6 - 0q */ /* 0, 0, 2, 2, 4, 4, 6, 6 - 0q */ + RSP_VMADM(1, 3, 5, 7, 0, 2, 4, 6, 0, 2, 4, 6, 0, 2, 4, 6); + break; + case 3: /* 0, 2, 4, 6, 1, 3, 5, 7 - 1q */ /* 1, 1, 3, 3, 5, 5, 7, 7 - 1q */ + RSP_VMADM(0, 2, 4, 6, 1, 3, 5, 7, 1, 3, 5, 7, 1, 3, 5, 7); + break; + case 4: /* 1, 2, 3, 5, 6, 7, 0, 4 - 0h */ /* 0, 0, 0, 0, 4, 4, 4, 4 - 0h */ + RSP_VMADM(1, 2, 3, 5, 6, 7, 0, 4, 0, 0, 0, 4, 4, 4, 0, 4); + break; + case 5: /* 0, 2, 3, 4, 6, 7, 1, 5 - 1h */ /* 1, 1, 1, 1, 5, 5, 5, 5 - 1h */ + RSP_VMADM(0, 2, 3, 4, 6, 7, 1, 5, 1, 1, 1, 5, 5, 5, 1, 5); + break; + case 6: /* 0, 1, 3, 4, 5, 7, 2, 6 - 2h */ /* 2, 2, 2, 2, 6, 6, 6, 6 - 2h */ + RSP_VMADM(0, 1, 3, 4, 5, 7, 2, 6, 2, 2, 2, 6, 6, 6, 2, 6); + break; + case 7: /* 0, 1, 2, 4, 5, 6, 3, 7 - 3h */ /* 3, 3, 3, 3, 7, 7, 7, 7 - 3h */ + RSP_VMADM(0, 1, 2, 4, 5, 6, 3, 7, 3, 3, 3, 7, 7, 7, 3, 7); + break; + case 8: /* 1, 2, 3, 4, 5, 6, 7, 0 - 0 */ /* 0, 0, 0, 0, 0, 0, 0, 0 - 0 */ + RSP_VMADM(1, 2, 3, 4, 5, 6, 7, 0, 0, 0, 0, 0, 0, 0, 0, 0); + break; + case 9: /* 0, 2, 3, 4, 5, 6, 7, 1 - 1 */ /* 1, 1, 1, 1, 1, 1, 1, 1 - 0 */ + RSP_VMADM(0, 2, 3, 4, 5, 6, 7, 1, 1, 1, 1, 1, 1, 1, 1, 1); + break; + case 10: /* 0, 1, 3, 4, 5, 6, 7, 2 - 2 */ /* 2, 2, 2, 2, 2, 2, 2, 2 - 0 */ + RSP_VMADM(0, 1, 3, 4, 5, 6, 7, 2, 2, 2, 2, 2, 2, 2, 2, 2); + break; + case 11: /* 0, 1, 2, 4, 5, 6, 7, 3 - 3 */ /* 3, 3, 3, 3, 3, 3, 3, 3 - 0 */ + RSP_VMADM(0, 1, 2, 4, 5, 6, 7, 3, 3, 3, 3, 3, 3, 3, 3, 3); + break; + case 12: /* 0, 1, 2, 3, 5, 6, 7, 4 - 4 */ /* 4, 4, 4, 4, 4, 4, 4, 4 - 0 */ + RSP_VMADM(0, 1, 2, 3, 5, 6, 7, 4, 4, 4, 4, 4, 4, 4, 4, 4); + break; + case 13: /* 0, 1, 2, 3, 4, 6, 7, 5 - 5 */ /* 5, 5, 5, 5, 5, 5, 5, 5 - 0 */ + RSP_VMADM(0, 1, 2, 3, 4, 6, 7, 5, 5, 5, 5, 5, 5, 5, 5, 5); + break; + case 14: /* 0, 1, 2, 3, 4, 5, 7, 6 - 6 */ /* 6, 6, 6, 6, 6, 6, 6, 6 - 0 */ + RSP_VMADM(0, 1, 2, 3, 4, 5, 7, 6, 6, 6, 6, 6, 6, 6, 6, 6); + break; + case 15: /* 0, 1, 2, 3, 4, 5, 6, 7 - 7 */ /* 7, 7, 7, 7, 7, 7, 7, 7 - 0 */ + RSP_VMADM(0, 1, 2, 3, 4, 5, 6, 7, 7, 7, 7, 7, 7, 7, 7, 7); + break; } } #endif @@ -3470,86 +3470,86 @@ INLINE void cfunc_rsp_vmadm(void *param) #define RSP_VMADN_DRC(E10, E11, E12, E13, E14, E15, E16, E17, E20, E21, E22, E23, E24, E25, E26, E27, I0, I1, I2, I3, I4, I5, I6, I7) \ { \ - UML_SEXT(block, IREG(1), VS(VS1REG, I0), WORD); \ - UML_SEXT(block, IREG(0), VS(VS2REG, E20), WORD); \ - UML_AND(block, IREG(1), IREG(1), IMM(0x0000ffff)); \ + UML_SEXT(block, IREG(1), VS(VS1REG, I0), WORD); \ + UML_SEXT(block, IREG(0), VS(VS2REG, E20), WORD); \ + UML_AND(block, IREG(1), IREG(1), IMM(0x0000ffff)); \ UML_MULS(block, IREG(0), IREG(1), IREG(0), IREG(1)); \ UML_DSEXT(block, IREG(0), IREG(0), DWORD); \ UML_DSHL(block, IREG(0), IREG(0), IMM(16)); \ UML_DADD(block, VACCUML(E10), VACCUML(E10), IREG(0)); \ \ - UML_SEXT(block, IREG(1), VS(VS1REG, I1), WORD); \ - UML_SEXT(block, IREG(0), VS(VS2REG, E21), WORD); \ - UML_AND(block, IREG(1), IREG(1), IMM(0x0000ffff)); \ + UML_SEXT(block, IREG(1), VS(VS1REG, I1), WORD); \ + UML_SEXT(block, IREG(0), VS(VS2REG, E21), WORD); \ + UML_AND(block, IREG(1), IREG(1), IMM(0x0000ffff)); \ UML_MULS(block, IREG(0), IREG(1), IREG(0), IREG(1)); \ UML_DSEXT(block, IREG(0), IREG(0), DWORD); \ UML_DSHL(block, IREG(0), IREG(0), IMM(16)); \ UML_DADD(block, VACCUML(E11), VACCUML(E11), IREG(0)); \ \ - UML_SEXT(block, IREG(1), VS(VS1REG, I2), WORD); \ - UML_SEXT(block, IREG(0), VS(VS2REG, E22), WORD); \ - UML_AND(block, IREG(1), IREG(1), IMM(0x0000ffff)); \ + UML_SEXT(block, IREG(1), VS(VS1REG, I2), WORD); \ + UML_SEXT(block, IREG(0), VS(VS2REG, E22), WORD); \ + UML_AND(block, IREG(1), IREG(1), IMM(0x0000ffff)); \ UML_MULS(block, IREG(0), IREG(1), IREG(0), IREG(1)); \ UML_DSEXT(block, IREG(0), IREG(0), DWORD); \ UML_DSHL(block, IREG(0), IREG(0), IMM(16)); \ UML_DADD(block, VACCUML(E12), VACCUML(E12), IREG(0)); \ \ - UML_SEXT(block, IREG(1), VS(VS1REG, I3), WORD); \ - UML_SEXT(block, IREG(0), VS(VS2REG, E23), WORD); \ - UML_AND(block, IREG(1), IREG(1), IMM(0x0000ffff)); \ + UML_SEXT(block, IREG(1), VS(VS1REG, I3), WORD); \ + UML_SEXT(block, IREG(0), VS(VS2REG, E23), WORD); \ + UML_AND(block, IREG(1), IREG(1), IMM(0x0000ffff)); \ UML_MULS(block, IREG(0), IREG(1), IREG(0), IREG(1)); \ UML_DSEXT(block, IREG(0), IREG(0), DWORD); \ UML_DSHL(block, IREG(0), IREG(0), IMM(16)); \ UML_DADD(block, VACCUML(E13), VACCUML(E13), IREG(0)); \ \ - UML_SEXT(block, IREG(1), VS(VS1REG, I4), WORD); \ - UML_SEXT(block, IREG(0), VS(VS2REG, E24), WORD); \ - UML_AND(block, IREG(1), IREG(1), IMM(0x0000ffff)); \ + UML_SEXT(block, IREG(1), VS(VS1REG, I4), WORD); \ + UML_SEXT(block, IREG(0), VS(VS2REG, E24), WORD); \ + UML_AND(block, IREG(1), IREG(1), IMM(0x0000ffff)); \ UML_MULS(block, IREG(0), IREG(1), IREG(0), IREG(1)); \ UML_DSEXT(block, IREG(0), IREG(0), DWORD); \ UML_DSHL(block, IREG(0), IREG(0), IMM(16)); \ UML_DADD(block, VACCUML(E14), VACCUML(E14), IREG(0)); \ \ - UML_SEXT(block, IREG(1), VS(VS1REG, I5), WORD); \ - UML_SEXT(block, IREG(0), VS(VS2REG, E25), WORD); \ - UML_AND(block, IREG(1), IREG(1), IMM(0x0000ffff)); \ + UML_SEXT(block, IREG(1), VS(VS1REG, I5), WORD); \ + UML_SEXT(block, IREG(0), VS(VS2REG, E25), WORD); \ + UML_AND(block, IREG(1), IREG(1), IMM(0x0000ffff)); \ UML_MULS(block, IREG(0), IREG(1), IREG(0), IREG(1)); \ UML_DSEXT(block, IREG(0), IREG(0), DWORD); \ UML_DSHL(block, IREG(0), IREG(0), IMM(16)); \ UML_DADD(block, VACCUML(E15), VACCUML(E15), IREG(0)); \ \ - UML_SEXT(block, IREG(1), VS(VS1REG, I6), WORD); \ - UML_SEXT(block, IREG(0), VS(VS2REG, E26), WORD); \ - UML_AND(block, IREG(1), IREG(1), IMM(0x0000ffff)); \ + UML_SEXT(block, IREG(1), VS(VS1REG, I6), WORD); \ + UML_SEXT(block, IREG(0), VS(VS2REG, E26), WORD); \ + UML_AND(block, IREG(1), IREG(1), IMM(0x0000ffff)); \ UML_MULS(block, IREG(0), IREG(1), IREG(0), IREG(1)); \ UML_DSEXT(block, IREG(0), IREG(0), DWORD); \ UML_DSHL(block, IREG(0), IREG(0), IMM(16)); \ UML_DADD(block, VACCUML(E16), VACCUML(E16), IREG(0)); \ \ - UML_SEXT(block, IREG(1), VS(VS1REG, I7), WORD); \ - UML_SEXT(block, IREG(0), VS(VS2REG, E27), WORD); \ - UML_AND(block, IREG(1), IREG(1), IMM(0x0000ffff)); \ + UML_SEXT(block, IREG(1), VS(VS1REG, I7), WORD); \ + UML_SEXT(block, IREG(0), VS(VS2REG, E27), WORD); \ + UML_AND(block, IREG(1), IREG(1), IMM(0x0000ffff)); \ UML_MULS(block, IREG(0), IREG(1), IREG(0), IREG(1)); \ UML_DSEXT(block, IREG(0), IREG(0), DWORD); \ UML_DSHL(block, IREG(0), IREG(0), IMM(16)); \ UML_DADD(block, VACCUML(E17), VACCUML(E17), IREG(0)); \ \ - generate_saturate_accum_unsigned(rsp, block, compiler, desc, E10); \ - UML_STORE(block, &rsp->v[VDREG].s[I0], IMM(0), IREG(0), WORD); \ - generate_saturate_accum_unsigned(rsp, block, compiler, desc, E11); \ - UML_STORE(block, &rsp->v[VDREG].s[I1], IMM(0), IREG(0), WORD); \ - generate_saturate_accum_unsigned(rsp, block, compiler, desc, E12); \ - UML_STORE(block, &rsp->v[VDREG].s[I2], IMM(0), IREG(0), WORD); \ - generate_saturate_accum_unsigned(rsp, block, compiler, desc, E13); \ - UML_STORE(block, &rsp->v[VDREG].s[I3], IMM(0), IREG(0), WORD); \ - generate_saturate_accum_unsigned(rsp, block, compiler, desc, E14); \ - UML_STORE(block, &rsp->v[VDREG].s[I4], IMM(0), IREG(0), WORD); \ - generate_saturate_accum_unsigned(rsp, block, compiler, desc, E15); \ - UML_STORE(block, &rsp->v[VDREG].s[I5], IMM(0), IREG(0), WORD); \ - generate_saturate_accum_unsigned(rsp, block, compiler, desc, E16); \ - UML_STORE(block, &rsp->v[VDREG].s[I6], IMM(0), IREG(0), WORD); \ - generate_saturate_accum_unsigned(rsp, block, compiler, desc, E17); \ - UML_STORE(block, &rsp->v[VDREG].s[I7], IMM(0), IREG(0), WORD); \ + generate_saturate_accum_unsigned(rsp, block, compiler, desc, E10); \ + UML_STORE(block, &rsp->v[VDREG].s[I0], IMM(0), IREG(0), WORD); \ + generate_saturate_accum_unsigned(rsp, block, compiler, desc, E11); \ + UML_STORE(block, &rsp->v[VDREG].s[I1], IMM(0), IREG(0), WORD); \ + generate_saturate_accum_unsigned(rsp, block, compiler, desc, E12); \ + UML_STORE(block, &rsp->v[VDREG].s[I2], IMM(0), IREG(0), WORD); \ + generate_saturate_accum_unsigned(rsp, block, compiler, desc, E13); \ + UML_STORE(block, &rsp->v[VDREG].s[I3], IMM(0), IREG(0), WORD); \ + generate_saturate_accum_unsigned(rsp, block, compiler, desc, E14); \ + UML_STORE(block, &rsp->v[VDREG].s[I4], IMM(0), IREG(0), WORD); \ + generate_saturate_accum_unsigned(rsp, block, compiler, desc, E15); \ + UML_STORE(block, &rsp->v[VDREG].s[I5], IMM(0), IREG(0), WORD); \ + generate_saturate_accum_unsigned(rsp, block, compiler, desc, E16); \ + UML_STORE(block, &rsp->v[VDREG].s[I6], IMM(0), IREG(0), WORD); \ + generate_saturate_accum_unsigned(rsp, block, compiler, desc, E17); \ + UML_STORE(block, &rsp->v[VDREG].s[I7], IMM(0), IREG(0), WORD); \ } static int generate_vmadn(rsp_state *rsp, drcuml_block *block, compiler_state *compiler, const opcode_desc *desc) // vmadn @@ -3566,54 +3566,54 @@ static int generate_vmadn(rsp_state *rsp, drcuml_block *block, compiler_state *c // The low slice of accumulator is stored into destination element switch(EL) { - case 0: /* 0, 1, 2, 3, 4, 5, 6, 7 - none */ /* 0, 1, 2, 3, 4, 5, 6, 7 - none */ - RSP_VMADN_DRC(0, 1, 2, 3, 4, 5, 6, 7, 7, 6, 5, 4, 3, 2, 1, 0, 7, 6, 5, 4, 3, 2, 1, 0); - return TRUE; - case 1: /* 0, 1, 2, 3, 4, 5, 6, 7 - ??? */ /* 0, 1, 2, 3, 4, 5, 6, 7 - ??? */ - RSP_VMADN_DRC(0, 1, 2, 3, 4, 5, 6, 7, 7, 6, 5, 4, 3, 2, 1, 0, 7, 6, 5, 4, 3, 2, 1, 0); - return TRUE; - case 2: /* 1, 3, 5, 7, 0, 2, 4, 6 - 0q */ /* 0, 0, 2, 2, 4, 4, 6, 6 - 0q */ - RSP_VMADN_DRC(1, 3, 5, 7, 0, 2, 4, 6, 7, 5, 3, 1, 7, 5, 3, 1, 6, 4, 2, 0, 7, 5, 3, 1); - return TRUE; - case 3: /* 0, 2, 4, 6, 1, 3, 5, 7 - 1q */ /* 1, 1, 3, 3, 5, 5, 7, 7 - 1q */ - RSP_VMADN_DRC(0, 2, 4, 6, 1, 3, 5, 7, 6, 4, 2, 0, 6, 4, 2, 0, 7, 5, 3, 1, 6, 4, 2, 0); - return TRUE; - case 4: /* 1, 2, 3, 5, 6, 7, 0, 4 - 0h */ /* 0, 0, 0, 0, 4, 4, 4, 4 - 0h */ - RSP_VMADN_DRC(1, 2, 3, 5, 6, 7, 0, 4, 7, 7, 7, 3, 3, 3, 7, 3, 6, 5, 4, 2, 1, 0, 7, 3); - return TRUE; - case 5: /* 0, 2, 3, 4, 6, 7, 1, 5 - 1h */ /* 1, 1, 1, 1, 5, 5, 5, 5 - 1h */ - RSP_VMADN_DRC(0, 2, 3, 4, 6, 7, 1, 5, 6, 6, 6, 2, 2, 2, 6, 2, 7, 5, 4, 3, 1, 0, 6, 2); - return TRUE; - case 6: /* 0, 1, 3, 4, 5, 7, 2, 6 - 2h */ /* 2, 2, 2, 2, 6, 6, 6, 6 - 2h */ - RSP_VMADN_DRC(0, 1, 3, 4, 5, 7, 2, 6, 5, 5, 5, 1, 1, 1, 5, 1, 7, 6, 4, 3, 2, 0, 5, 1); - return TRUE; - case 7: /* 0, 1, 2, 4, 5, 6, 3, 7 - 3h */ /* 3, 3, 3, 3, 7, 7, 7, 7 - 3h */ - RSP_VMADN_DRC(0, 1, 2, 4, 5, 6, 3, 7, 4, 4, 4, 0, 0, 0, 4, 0, 7, 6, 5, 3, 2, 1, 4, 0); - return TRUE; - case 8: /* 1, 2, 3, 4, 5, 6, 7, 0 - 0 */ /* 0, 0, 0, 0, 0, 0, 0, 0 - 0 */ - RSP_VMADN_DRC(1, 2, 3, 4, 5, 6, 7, 0, 7, 7, 7, 7, 7, 7, 7, 7, 6, 5, 4, 3, 2, 1, 0, 7); - return TRUE; - case 9: /* 0, 2, 3, 4, 5, 6, 7, 1 - 1 */ /* 1, 1, 1, 1, 1, 1, 1, 1 - 0 */ - RSP_VMADN_DRC(0, 2, 3, 4, 5, 6, 7, 1, 6, 6, 6, 6, 6, 6, 6, 6, 7, 5, 4, 3, 2, 1, 0, 6); - return TRUE; - case 10: /* 0, 1, 3, 4, 5, 6, 7, 2 - 2 */ /* 2, 2, 2, 2, 2, 2, 2, 2 - 0 */ - RSP_VMADN_DRC(0, 1, 3, 4, 5, 6, 7, 2, 5, 5, 5, 5, 5, 5, 5, 5, 7, 6, 4, 3, 2, 1, 0, 5); - return TRUE; - case 11: /* 0, 1, 2, 4, 5, 6, 7, 3 - 3 */ /* 3, 3, 3, 3, 3, 3, 3, 3 - 0 */ - RSP_VMADN_DRC(0, 1, 2, 4, 5, 6, 7, 3, 4, 4, 4, 4, 4, 4, 4, 4, 7, 6, 5, 3, 2, 1, 0, 4); - return TRUE; - case 12: /* 0, 1, 2, 3, 5, 6, 7, 4 - 4 */ /* 4, 4, 4, 4, 4, 4, 4, 4 - 0 */ - RSP_VMADN_DRC(0, 1, 2, 3, 5, 6, 7, 4, 3, 3, 3, 3, 3, 3, 3, 3, 7, 6, 5, 4, 2, 1, 0, 3); - return TRUE; - case 13: /* 0, 1, 2, 3, 4, 6, 7, 5 - 5 */ /* 5, 5, 5, 5, 5, 5, 5, 5 - 0 */ - RSP_VMADN_DRC(0, 1, 2, 3, 4, 6, 7, 5, 2, 2, 2, 2, 2, 2, 2, 2, 7, 6, 5, 4, 3, 1, 0, 2); - return TRUE; - case 14: /* 0, 1, 2, 3, 4, 5, 7, 6 - 6 */ /* 6, 6, 6, 6, 6, 6, 6, 6 - 0 */ - RSP_VMADN_DRC(0, 1, 2, 3, 4, 5, 7, 6, 1, 1, 1, 1, 1, 1, 1, 1, 7, 6, 5, 4, 3, 2, 0, 1); - return TRUE; - case 15: /* 0, 1, 2, 3, 4, 5, 6, 7 - 7 */ /* 7, 7, 7, 7, 7, 7, 7, 7 - 0 */ - RSP_VMADN_DRC(0, 1, 2, 3, 4, 5, 6, 7, 0, 0, 0, 0, 0, 0, 0, 0, 7, 6, 5, 4, 3, 2, 1, 0); - return TRUE; + case 0: /* 0, 1, 2, 3, 4, 5, 6, 7 - none */ /* 0, 1, 2, 3, 4, 5, 6, 7 - none */ + RSP_VMADN_DRC(0, 1, 2, 3, 4, 5, 6, 7, 7, 6, 5, 4, 3, 2, 1, 0, 7, 6, 5, 4, 3, 2, 1, 0); + return TRUE; + case 1: /* 0, 1, 2, 3, 4, 5, 6, 7 - ??? */ /* 0, 1, 2, 3, 4, 5, 6, 7 - ??? */ + RSP_VMADN_DRC(0, 1, 2, 3, 4, 5, 6, 7, 7, 6, 5, 4, 3, 2, 1, 0, 7, 6, 5, 4, 3, 2, 1, 0); + return TRUE; + case 2: /* 1, 3, 5, 7, 0, 2, 4, 6 - 0q */ /* 0, 0, 2, 2, 4, 4, 6, 6 - 0q */ + RSP_VMADN_DRC(1, 3, 5, 7, 0, 2, 4, 6, 7, 5, 3, 1, 7, 5, 3, 1, 6, 4, 2, 0, 7, 5, 3, 1); + return TRUE; + case 3: /* 0, 2, 4, 6, 1, 3, 5, 7 - 1q */ /* 1, 1, 3, 3, 5, 5, 7, 7 - 1q */ + RSP_VMADN_DRC(0, 2, 4, 6, 1, 3, 5, 7, 6, 4, 2, 0, 6, 4, 2, 0, 7, 5, 3, 1, 6, 4, 2, 0); + return TRUE; + case 4: /* 1, 2, 3, 5, 6, 7, 0, 4 - 0h */ /* 0, 0, 0, 0, 4, 4, 4, 4 - 0h */ + RSP_VMADN_DRC(1, 2, 3, 5, 6, 7, 0, 4, 7, 7, 7, 3, 3, 3, 7, 3, 6, 5, 4, 2, 1, 0, 7, 3); + return TRUE; + case 5: /* 0, 2, 3, 4, 6, 7, 1, 5 - 1h */ /* 1, 1, 1, 1, 5, 5, 5, 5 - 1h */ + RSP_VMADN_DRC(0, 2, 3, 4, 6, 7, 1, 5, 6, 6, 6, 2, 2, 2, 6, 2, 7, 5, 4, 3, 1, 0, 6, 2); + return TRUE; + case 6: /* 0, 1, 3, 4, 5, 7, 2, 6 - 2h */ /* 2, 2, 2, 2, 6, 6, 6, 6 - 2h */ + RSP_VMADN_DRC(0, 1, 3, 4, 5, 7, 2, 6, 5, 5, 5, 1, 1, 1, 5, 1, 7, 6, 4, 3, 2, 0, 5, 1); + return TRUE; + case 7: /* 0, 1, 2, 4, 5, 6, 3, 7 - 3h */ /* 3, 3, 3, 3, 7, 7, 7, 7 - 3h */ + RSP_VMADN_DRC(0, 1, 2, 4, 5, 6, 3, 7, 4, 4, 4, 0, 0, 0, 4, 0, 7, 6, 5, 3, 2, 1, 4, 0); + return TRUE; + case 8: /* 1, 2, 3, 4, 5, 6, 7, 0 - 0 */ /* 0, 0, 0, 0, 0, 0, 0, 0 - 0 */ + RSP_VMADN_DRC(1, 2, 3, 4, 5, 6, 7, 0, 7, 7, 7, 7, 7, 7, 7, 7, 6, 5, 4, 3, 2, 1, 0, 7); + return TRUE; + case 9: /* 0, 2, 3, 4, 5, 6, 7, 1 - 1 */ /* 1, 1, 1, 1, 1, 1, 1, 1 - 0 */ + RSP_VMADN_DRC(0, 2, 3, 4, 5, 6, 7, 1, 6, 6, 6, 6, 6, 6, 6, 6, 7, 5, 4, 3, 2, 1, 0, 6); + return TRUE; + case 10: /* 0, 1, 3, 4, 5, 6, 7, 2 - 2 */ /* 2, 2, 2, 2, 2, 2, 2, 2 - 0 */ + RSP_VMADN_DRC(0, 1, 3, 4, 5, 6, 7, 2, 5, 5, 5, 5, 5, 5, 5, 5, 7, 6, 4, 3, 2, 1, 0, 5); + return TRUE; + case 11: /* 0, 1, 2, 4, 5, 6, 7, 3 - 3 */ /* 3, 3, 3, 3, 3, 3, 3, 3 - 0 */ + RSP_VMADN_DRC(0, 1, 2, 4, 5, 6, 7, 3, 4, 4, 4, 4, 4, 4, 4, 4, 7, 6, 5, 3, 2, 1, 0, 4); + return TRUE; + case 12: /* 0, 1, 2, 3, 5, 6, 7, 4 - 4 */ /* 4, 4, 4, 4, 4, 4, 4, 4 - 0 */ + RSP_VMADN_DRC(0, 1, 2, 3, 5, 6, 7, 4, 3, 3, 3, 3, 3, 3, 3, 3, 7, 6, 5, 4, 2, 1, 0, 3); + return TRUE; + case 13: /* 0, 1, 2, 3, 4, 6, 7, 5 - 5 */ /* 5, 5, 5, 5, 5, 5, 5, 5 - 0 */ + RSP_VMADN_DRC(0, 1, 2, 3, 4, 6, 7, 5, 2, 2, 2, 2, 2, 2, 2, 2, 7, 6, 5, 4, 3, 1, 0, 2); + return TRUE; + case 14: /* 0, 1, 2, 3, 4, 5, 7, 6 - 6 */ /* 6, 6, 6, 6, 6, 6, 6, 6 - 0 */ + RSP_VMADN_DRC(0, 1, 2, 3, 4, 5, 7, 6, 1, 1, 1, 1, 1, 1, 1, 1, 7, 6, 5, 4, 3, 2, 0, 1); + return TRUE; + case 15: /* 0, 1, 2, 3, 4, 5, 6, 7 - 7 */ /* 7, 7, 7, 7, 7, 7, 7, 7 - 0 */ + RSP_VMADN_DRC(0, 1, 2, 3, 4, 5, 6, 7, 0, 0, 0, 0, 0, 0, 0, 0, 7, 6, 5, 4, 3, 2, 1, 0); + return TRUE; } return TRUE; @@ -3662,54 +3662,54 @@ INLINE void cfunc_rsp_vmadn(void *param) // The low slice of accumulator is stored into destination element switch(EL) { - case 0: /* 0, 1, 2, 3, 4, 5, 6, 7 - none */ /* 0, 1, 2, 3, 4, 5, 6, 7 - none */ - RSP_VMADN(0, 1, 2, 3, 4, 5, 6, 7, 7, 6, 5, 4, 3, 2, 1, 0, 7, 6, 5, 4, 3, 2, 1, 0); - break; - case 1: /* 0, 1, 2, 3, 4, 5, 6, 7 - ??? */ /* 0, 1, 2, 3, 4, 5, 6, 7 - ??? */ - RSP_VMADN(0, 1, 2, 3, 4, 5, 6, 7, 7, 6, 5, 4, 3, 2, 1, 0, 7, 6, 5, 4, 3, 2, 1, 0); - break; - case 2: /* 1, 3, 5, 7, 0, 2, 4, 6 - 0q */ /* 0, 0, 2, 2, 4, 4, 6, 6 - 0q */ - RSP_VMADN(1, 3, 5, 7, 0, 2, 4, 6, 7, 5, 3, 1, 7, 5, 3, 1, 6, 4, 2, 0, 7, 5, 3, 1); - break; - case 3: /* 0, 2, 4, 6, 1, 3, 5, 7 - 1q */ /* 1, 1, 3, 3, 5, 5, 7, 7 - 1q */ - RSP_VMADN(0, 2, 4, 6, 1, 3, 5, 7, 6, 4, 2, 0, 6, 4, 2, 0, 7, 5, 3, 1, 6, 4, 2, 0); - break; - case 4: /* 1, 2, 3, 5, 6, 7, 0, 4 - 0h */ /* 0, 0, 0, 0, 4, 4, 4, 4 - 0h */ - RSP_VMADN(1, 2, 3, 5, 6, 7, 0, 4, 7, 7, 7, 3, 3, 3, 7, 3, 6, 5, 4, 2, 1, 0, 7, 3); - break; - case 5: /* 0, 2, 3, 4, 6, 7, 1, 5 - 1h */ /* 1, 1, 1, 1, 5, 5, 5, 5 - 1h */ - RSP_VMADN(0, 2, 3, 4, 6, 7, 1, 5, 6, 6, 6, 2, 2, 2, 6, 2, 7, 5, 4, 3, 1, 0, 6, 2); - break; - case 6: /* 0, 1, 3, 4, 5, 7, 2, 6 - 2h */ /* 2, 2, 2, 2, 6, 6, 6, 6 - 2h */ - RSP_VMADN(0, 1, 3, 4, 5, 7, 2, 6, 5, 5, 5, 1, 1, 1, 5, 1, 7, 6, 4, 3, 2, 0, 5, 1); - break; - case 7: /* 0, 1, 2, 4, 5, 6, 3, 7 - 3h */ /* 3, 3, 3, 3, 7, 7, 7, 7 - 3h */ - RSP_VMADN(0, 1, 2, 4, 5, 6, 3, 7, 4, 4, 4, 0, 0, 0, 4, 0, 7, 6, 5, 3, 2, 1, 4, 0); - break; - case 8: /* 1, 2, 3, 4, 5, 6, 7, 0 - 0 */ /* 0, 0, 0, 0, 0, 0, 0, 0 - 0 */ - RSP_VMADN(1, 2, 3, 4, 5, 6, 7, 0, 7, 7, 7, 7, 7, 7, 7, 7, 6, 5, 4, 3, 2, 1, 0, 7); - break; - case 9: /* 0, 2, 3, 4, 5, 6, 7, 1 - 1 */ /* 1, 1, 1, 1, 1, 1, 1, 1 - 0 */ - RSP_VMADN(0, 2, 3, 4, 5, 6, 7, 1, 6, 6, 6, 6, 6, 6, 6, 6, 7, 5, 4, 3, 2, 1, 0, 6); - break; - case 10: /* 0, 1, 3, 4, 5, 6, 7, 2 - 2 */ /* 2, 2, 2, 2, 2, 2, 2, 2 - 0 */ - RSP_VMADN(0, 1, 3, 4, 5, 6, 7, 2, 5, 5, 5, 5, 5, 5, 5, 5, 7, 6, 4, 3, 2, 1, 0, 5); - break; - case 11: /* 0, 1, 2, 4, 5, 6, 7, 3 - 3 */ /* 3, 3, 3, 3, 3, 3, 3, 3 - 0 */ - RSP_VMADN(0, 1, 2, 4, 5, 6, 7, 3, 4, 4, 4, 4, 4, 4, 4, 4, 7, 6, 5, 3, 2, 1, 0, 4); - break; - case 12: /* 0, 1, 2, 3, 5, 6, 7, 4 - 4 */ /* 4, 4, 4, 4, 4, 4, 4, 4 - 0 */ - RSP_VMADN(0, 1, 2, 3, 5, 6, 7, 4, 3, 3, 3, 3, 3, 3, 3, 3, 7, 6, 5, 4, 2, 1, 0, 3); - break; - case 13: /* 0, 1, 2, 3, 4, 6, 7, 5 - 5 */ /* 5, 5, 5, 5, 5, 5, 5, 5 - 0 */ - RSP_VMADN(0, 1, 2, 3, 4, 6, 7, 5, 2, 2, 2, 2, 2, 2, 2, 2, 7, 6, 5, 4, 3, 1, 0, 2); - break; - case 14: /* 0, 1, 2, 3, 4, 5, 7, 6 - 6 */ /* 6, 6, 6, 6, 6, 6, 6, 6 - 0 */ - RSP_VMADN(0, 1, 2, 3, 4, 5, 7, 6, 1, 1, 1, 1, 1, 1, 1, 1, 7, 6, 5, 4, 3, 2, 0, 1); - break; - case 15: /* 0, 1, 2, 3, 4, 5, 6, 7 - 7 */ /* 7, 7, 7, 7, 7, 7, 7, 7 - 0 */ - RSP_VMADN(0, 1, 2, 3, 4, 5, 6, 7, 0, 0, 0, 0, 0, 0, 0, 0, 7, 6, 5, 4, 3, 2, 1, 0); - break; + case 0: /* 0, 1, 2, 3, 4, 5, 6, 7 - none */ /* 0, 1, 2, 3, 4, 5, 6, 7 - none */ + RSP_VMADN(0, 1, 2, 3, 4, 5, 6, 7, 7, 6, 5, 4, 3, 2, 1, 0, 7, 6, 5, 4, 3, 2, 1, 0); + break; + case 1: /* 0, 1, 2, 3, 4, 5, 6, 7 - ??? */ /* 0, 1, 2, 3, 4, 5, 6, 7 - ??? */ + RSP_VMADN(0, 1, 2, 3, 4, 5, 6, 7, 7, 6, 5, 4, 3, 2, 1, 0, 7, 6, 5, 4, 3, 2, 1, 0); + break; + case 2: /* 1, 3, 5, 7, 0, 2, 4, 6 - 0q */ /* 0, 0, 2, 2, 4, 4, 6, 6 - 0q */ + RSP_VMADN(1, 3, 5, 7, 0, 2, 4, 6, 7, 5, 3, 1, 7, 5, 3, 1, 6, 4, 2, 0, 7, 5, 3, 1); + break; + case 3: /* 0, 2, 4, 6, 1, 3, 5, 7 - 1q */ /* 1, 1, 3, 3, 5, 5, 7, 7 - 1q */ + RSP_VMADN(0, 2, 4, 6, 1, 3, 5, 7, 6, 4, 2, 0, 6, 4, 2, 0, 7, 5, 3, 1, 6, 4, 2, 0); + break; + case 4: /* 1, 2, 3, 5, 6, 7, 0, 4 - 0h */ /* 0, 0, 0, 0, 4, 4, 4, 4 - 0h */ + RSP_VMADN(1, 2, 3, 5, 6, 7, 0, 4, 7, 7, 7, 3, 3, 3, 7, 3, 6, 5, 4, 2, 1, 0, 7, 3); + break; + case 5: /* 0, 2, 3, 4, 6, 7, 1, 5 - 1h */ /* 1, 1, 1, 1, 5, 5, 5, 5 - 1h */ + RSP_VMADN(0, 2, 3, 4, 6, 7, 1, 5, 6, 6, 6, 2, 2, 2, 6, 2, 7, 5, 4, 3, 1, 0, 6, 2); + break; + case 6: /* 0, 1, 3, 4, 5, 7, 2, 6 - 2h */ /* 2, 2, 2, 2, 6, 6, 6, 6 - 2h */ + RSP_VMADN(0, 1, 3, 4, 5, 7, 2, 6, 5, 5, 5, 1, 1, 1, 5, 1, 7, 6, 4, 3, 2, 0, 5, 1); + break; + case 7: /* 0, 1, 2, 4, 5, 6, 3, 7 - 3h */ /* 3, 3, 3, 3, 7, 7, 7, 7 - 3h */ + RSP_VMADN(0, 1, 2, 4, 5, 6, 3, 7, 4, 4, 4, 0, 0, 0, 4, 0, 7, 6, 5, 3, 2, 1, 4, 0); + break; + case 8: /* 1, 2, 3, 4, 5, 6, 7, 0 - 0 */ /* 0, 0, 0, 0, 0, 0, 0, 0 - 0 */ + RSP_VMADN(1, 2, 3, 4, 5, 6, 7, 0, 7, 7, 7, 7, 7, 7, 7, 7, 6, 5, 4, 3, 2, 1, 0, 7); + break; + case 9: /* 0, 2, 3, 4, 5, 6, 7, 1 - 1 */ /* 1, 1, 1, 1, 1, 1, 1, 1 - 0 */ + RSP_VMADN(0, 2, 3, 4, 5, 6, 7, 1, 6, 6, 6, 6, 6, 6, 6, 6, 7, 5, 4, 3, 2, 1, 0, 6); + break; + case 10: /* 0, 1, 3, 4, 5, 6, 7, 2 - 2 */ /* 2, 2, 2, 2, 2, 2, 2, 2 - 0 */ + RSP_VMADN(0, 1, 3, 4, 5, 6, 7, 2, 5, 5, 5, 5, 5, 5, 5, 5, 7, 6, 4, 3, 2, 1, 0, 5); + break; + case 11: /* 0, 1, 2, 4, 5, 6, 7, 3 - 3 */ /* 3, 3, 3, 3, 3, 3, 3, 3 - 0 */ + RSP_VMADN(0, 1, 2, 4, 5, 6, 7, 3, 4, 4, 4, 4, 4, 4, 4, 4, 7, 6, 5, 3, 2, 1, 0, 4); + break; + case 12: /* 0, 1, 2, 3, 5, 6, 7, 4 - 4 */ /* 4, 4, 4, 4, 4, 4, 4, 4 - 0 */ + RSP_VMADN(0, 1, 2, 3, 5, 6, 7, 4, 3, 3, 3, 3, 3, 3, 3, 3, 7, 6, 5, 4, 2, 1, 0, 3); + break; + case 13: /* 0, 1, 2, 3, 4, 6, 7, 5 - 5 */ /* 5, 5, 5, 5, 5, 5, 5, 5 - 0 */ + RSP_VMADN(0, 1, 2, 3, 4, 6, 7, 5, 2, 2, 2, 2, 2, 2, 2, 2, 7, 6, 5, 4, 3, 1, 0, 2); + break; + case 14: /* 0, 1, 2, 3, 4, 5, 7, 6 - 6 */ /* 6, 6, 6, 6, 6, 6, 6, 6 - 0 */ + RSP_VMADN(0, 1, 2, 3, 4, 5, 7, 6, 1, 1, 1, 1, 1, 1, 1, 1, 7, 6, 5, 4, 3, 2, 0, 1); + break; + case 15: /* 0, 1, 2, 3, 4, 5, 6, 7 - 7 */ /* 7, 7, 7, 7, 7, 7, 7, 7 - 0 */ + RSP_VMADN(0, 1, 2, 3, 4, 5, 6, 7, 0, 0, 0, 0, 0, 0, 0, 0, 7, 6, 5, 4, 3, 2, 1, 0); + break; } } #endif @@ -3721,62 +3721,62 @@ INLINE void cfunc_rsp_vmadn(void *param) #define RSP_VMADH_DRC(E10, E11, E12, E13, E14, E15, E16, E17, E20, E21, E22, E23, E24, E25, E26, E27, I0, I1, I2, I3, I4, I5, I6, I7) \ { \ - UML_SEXT(block, IREG(1), VS(VS1REG, I0), WORD); \ - UML_SEXT(block, IREG(0), VS(VS2REG, E20), WORD); \ + UML_SEXT(block, IREG(1), VS(VS1REG, I0), WORD); \ + UML_SEXT(block, IREG(0), VS(VS2REG, E20), WORD); \ UML_MULS(block, IREG(0), IREG(1), IREG(0), IREG(1)); \ UML_ADD(block, VACCUMWMH(E10), VACCUMWMH(E10), IREG(0)); \ \ - UML_SEXT(block, IREG(1), VS(VS1REG, I1), WORD); \ - UML_SEXT(block, IREG(0), VS(VS2REG, E21), WORD); \ + UML_SEXT(block, IREG(1), VS(VS1REG, I1), WORD); \ + UML_SEXT(block, IREG(0), VS(VS2REG, E21), WORD); \ UML_MULS(block, IREG(0), IREG(1), IREG(0), IREG(1)); \ UML_ADD(block, VACCUMWMH(E11), VACCUMWMH(E11), IREG(0)); \ \ - UML_SEXT(block, IREG(1), VS(VS1REG, I2), WORD); \ - UML_SEXT(block, IREG(0), VS(VS2REG, E22), WORD); \ + UML_SEXT(block, IREG(1), VS(VS1REG, I2), WORD); \ + UML_SEXT(block, IREG(0), VS(VS2REG, E22), WORD); \ UML_MULS(block, IREG(0), IREG(1), IREG(0), IREG(1)); \ UML_ADD(block, VACCUMWMH(E12), VACCUMWMH(E12), IREG(0)); \ \ - UML_SEXT(block, IREG(1), VS(VS1REG, I3), WORD); \ - UML_SEXT(block, IREG(0), VS(VS2REG, E23), WORD); \ + UML_SEXT(block, IREG(1), VS(VS1REG, I3), WORD); \ + UML_SEXT(block, IREG(0), VS(VS2REG, E23), WORD); \ UML_MULS(block, IREG(0), IREG(1), IREG(0), IREG(1)); \ UML_ADD(block, VACCUMWMH(E13), VACCUMWMH(E13), IREG(0)); \ \ - UML_SEXT(block, IREG(1), VS(VS1REG, I4), WORD); \ - UML_SEXT(block, IREG(0), VS(VS2REG, E24), WORD); \ + UML_SEXT(block, IREG(1), VS(VS1REG, I4), WORD); \ + UML_SEXT(block, IREG(0), VS(VS2REG, E24), WORD); \ UML_MULS(block, IREG(0), IREG(1), IREG(0), IREG(1)); \ UML_ADD(block, VACCUMWMH(E14), VACCUMWMH(E14), IREG(0)); \ \ - UML_SEXT(block, IREG(1), VS(VS1REG, I5), WORD); \ - UML_SEXT(block, IREG(0), VS(VS2REG, E25), WORD); \ + UML_SEXT(block, IREG(1), VS(VS1REG, I5), WORD); \ + UML_SEXT(block, IREG(0), VS(VS2REG, E25), WORD); \ UML_MULS(block, IREG(0), IREG(1), IREG(0), IREG(1)); \ UML_ADD(block, VACCUMWMH(E15), VACCUMWMH(E15), IREG(0)); \ \ - UML_SEXT(block, IREG(1), VS(VS1REG, I6), WORD); \ - UML_SEXT(block, IREG(0), VS(VS2REG, E26), WORD); \ + UML_SEXT(block, IREG(1), VS(VS1REG, I6), WORD); \ + UML_SEXT(block, IREG(0), VS(VS2REG, E26), WORD); \ UML_MULS(block, IREG(0), IREG(1), IREG(0), IREG(1)); \ UML_ADD(block, VACCUMWMH(E16), VACCUMWMH(E16), IREG(0)); \ \ - UML_SEXT(block, IREG(1), VS(VS1REG, I7), WORD); \ - UML_SEXT(block, IREG(0), VS(VS2REG, E27), WORD); \ + UML_SEXT(block, IREG(1), VS(VS1REG, I7), WORD); \ + UML_SEXT(block, IREG(0), VS(VS2REG, E27), WORD); \ UML_MULS(block, IREG(0), IREG(1), IREG(0), IREG(1)); \ UML_ADD(block, VACCUMWMH(E17), VACCUMWMH(E17), IREG(0)); \ \ - generate_saturate_accum_signed(rsp, block, compiler, desc, E10); \ - UML_STORE(block, &rsp->v[VDREG].s[I0], IMM(0), IREG(0), WORD); \ - generate_saturate_accum_signed(rsp, block, compiler, desc, E11); \ - UML_STORE(block, &rsp->v[VDREG].s[I1], IMM(0), IREG(0), WORD); \ - generate_saturate_accum_signed(rsp, block, compiler, desc, E12); \ - UML_STORE(block, &rsp->v[VDREG].s[I2], IMM(0), IREG(0), WORD); \ - generate_saturate_accum_signed(rsp, block, compiler, desc, E13); \ - UML_STORE(block, &rsp->v[VDREG].s[I3], IMM(0), IREG(0), WORD); \ - generate_saturate_accum_signed(rsp, block, compiler, desc, E14); \ - UML_STORE(block, &rsp->v[VDREG].s[I4], IMM(0), IREG(0), WORD); \ - generate_saturate_accum_signed(rsp, block, compiler, desc, E15); \ - UML_STORE(block, &rsp->v[VDREG].s[I5], IMM(0), IREG(0), WORD); \ - generate_saturate_accum_signed(rsp, block, compiler, desc, E16); \ - UML_STORE(block, &rsp->v[VDREG].s[I6], IMM(0), IREG(0), WORD); \ - generate_saturate_accum_signed(rsp, block, compiler, desc, E17); \ - UML_STORE(block, &rsp->v[VDREG].s[I7], IMM(0), IREG(0), WORD); \ + generate_saturate_accum_signed(rsp, block, compiler, desc, E10); \ + UML_STORE(block, &rsp->v[VDREG].s[I0], IMM(0), IREG(0), WORD); \ + generate_saturate_accum_signed(rsp, block, compiler, desc, E11); \ + UML_STORE(block, &rsp->v[VDREG].s[I1], IMM(0), IREG(0), WORD); \ + generate_saturate_accum_signed(rsp, block, compiler, desc, E12); \ + UML_STORE(block, &rsp->v[VDREG].s[I2], IMM(0), IREG(0), WORD); \ + generate_saturate_accum_signed(rsp, block, compiler, desc, E13); \ + UML_STORE(block, &rsp->v[VDREG].s[I3], IMM(0), IREG(0), WORD); \ + generate_saturate_accum_signed(rsp, block, compiler, desc, E14); \ + UML_STORE(block, &rsp->v[VDREG].s[I4], IMM(0), IREG(0), WORD); \ + generate_saturate_accum_signed(rsp, block, compiler, desc, E15); \ + UML_STORE(block, &rsp->v[VDREG].s[I5], IMM(0), IREG(0), WORD); \ + generate_saturate_accum_signed(rsp, block, compiler, desc, E16); \ + UML_STORE(block, &rsp->v[VDREG].s[I6], IMM(0), IREG(0), WORD); \ + generate_saturate_accum_signed(rsp, block, compiler, desc, E17); \ + UML_STORE(block, &rsp->v[VDREG].s[I7], IMM(0), IREG(0), WORD); \ } static int generate_vmadh(rsp_state *rsp, drcuml_block *block, compiler_state *compiler, const opcode_desc *desc) // vmadh @@ -3793,54 +3793,54 @@ static int generate_vmadh(rsp_state *rsp, drcuml_block *block, compiler_state *c // The low slice of accumulator is stored into destination element switch(EL) { - case 0: /* 0, 1, 2, 3, 4, 5, 6, 7 - none */ /* 0, 1, 2, 3, 4, 5, 6, 7 - none */ - RSP_VMADH_DRC(0, 1, 2, 3, 4, 5, 6, 7, 7, 6, 5, 4, 3, 2, 1, 0, 7, 6, 5, 4, 3, 2, 1, 0); - return TRUE; - case 1: /* 0, 1, 2, 3, 4, 5, 6, 7 - ??? */ /* 0, 1, 2, 3, 4, 5, 6, 7 - ??? */ - RSP_VMADH_DRC(0, 1, 2, 3, 4, 5, 6, 7, 7, 6, 5, 4, 3, 2, 1, 0, 7, 6, 5, 4, 3, 2, 1, 0); - return TRUE; - case 2: /* 1, 3, 5, 7, 0, 2, 4, 6 - 0q */ /* 0, 0, 2, 2, 4, 4, 6, 6 - 0q */ - RSP_VMADH_DRC(1, 3, 5, 7, 0, 2, 4, 6, 7, 5, 3, 1, 7, 5, 3, 1, 6, 4, 2, 0, 7, 5, 3, 1); - return TRUE; - case 3: /* 0, 2, 4, 6, 1, 3, 5, 7 - 1q */ /* 1, 1, 3, 3, 5, 5, 7, 7 - 1q */ - RSP_VMADH_DRC(0, 2, 4, 6, 1, 3, 5, 7, 6, 4, 2, 0, 6, 4, 2, 0, 7, 5, 3, 1, 6, 4, 2, 0); - return TRUE; - case 4: /* 1, 2, 3, 5, 6, 7, 0, 4 - 0h */ /* 0, 0, 0, 0, 4, 4, 4, 4 - 0h */ - RSP_VMADH_DRC(1, 2, 3, 5, 6, 7, 0, 4, 7, 7, 7, 3, 3, 3, 7, 3, 6, 5, 4, 2, 1, 0, 7, 3); - return TRUE; - case 5: /* 0, 2, 3, 4, 6, 7, 1, 5 - 1h */ /* 1, 1, 1, 1, 5, 5, 5, 5 - 1h */ - RSP_VMADH_DRC(0, 2, 3, 4, 6, 7, 1, 5, 6, 6, 6, 2, 2, 2, 6, 2, 7, 5, 4, 3, 1, 0, 6, 2); - return TRUE; - case 6: /* 0, 1, 3, 4, 5, 7, 2, 6 - 2h */ /* 2, 2, 2, 2, 6, 6, 6, 6 - 2h */ - RSP_VMADH_DRC(0, 1, 3, 4, 5, 7, 2, 6, 5, 5, 5, 1, 1, 1, 5, 1, 7, 6, 4, 3, 2, 0, 5, 1); - return TRUE; - case 7: /* 0, 1, 2, 4, 5, 6, 3, 7 - 3h */ /* 3, 3, 3, 3, 7, 7, 7, 7 - 3h */ - RSP_VMADH_DRC(0, 1, 2, 4, 5, 6, 3, 7, 4, 4, 4, 0, 0, 0, 4, 0, 7, 6, 5, 3, 2, 1, 4, 0); - return TRUE; - case 8: /* 1, 2, 3, 4, 5, 6, 7, 0 - 0 */ /* 0, 0, 0, 0, 0, 0, 0, 0 - 0 */ - RSP_VMADH_DRC(1, 2, 3, 4, 5, 6, 7, 0, 7, 7, 7, 7, 7, 7, 7, 7, 6, 5, 4, 3, 2, 1, 0, 7); - return TRUE; - case 9: /* 0, 2, 3, 4, 5, 6, 7, 1 - 1 */ /* 1, 1, 1, 1, 1, 1, 1, 1 - 0 */ - RSP_VMADH_DRC(0, 2, 3, 4, 5, 6, 7, 1, 6, 6, 6, 6, 6, 6, 6, 6, 7, 5, 4, 3, 2, 1, 0, 6); - return TRUE; - case 10: /* 0, 1, 3, 4, 5, 6, 7, 2 - 2 */ /* 2, 2, 2, 2, 2, 2, 2, 2 - 0 */ - RSP_VMADH_DRC(0, 1, 3, 4, 5, 6, 7, 2, 5, 5, 5, 5, 5, 5, 5, 5, 7, 6, 4, 3, 2, 1, 0, 5); - return TRUE; - case 11: /* 0, 1, 2, 4, 5, 6, 7, 3 - 3 */ /* 3, 3, 3, 3, 3, 3, 3, 3 - 0 */ - RSP_VMADH_DRC(0, 1, 2, 4, 5, 6, 7, 3, 4, 4, 4, 4, 4, 4, 4, 4, 7, 6, 5, 3, 2, 1, 0, 4); - return TRUE; - case 12: /* 0, 1, 2, 3, 5, 6, 7, 4 - 4 */ /* 4, 4, 4, 4, 4, 4, 4, 4 - 0 */ - RSP_VMADH_DRC(0, 1, 2, 3, 5, 6, 7, 4, 3, 3, 3, 3, 3, 3, 3, 3, 7, 6, 5, 4, 2, 1, 0, 3); - return TRUE; - case 13: /* 0, 1, 2, 3, 4, 6, 7, 5 - 5 */ /* 5, 5, 5, 5, 5, 5, 5, 5 - 0 */ - RSP_VMADH_DRC(0, 1, 2, 3, 4, 6, 7, 5, 2, 2, 2, 2, 2, 2, 2, 2, 7, 6, 5, 4, 3, 1, 0, 2); - return TRUE; - case 14: /* 0, 1, 2, 3, 4, 5, 7, 6 - 6 */ /* 6, 6, 6, 6, 6, 6, 6, 6 - 0 */ - RSP_VMADH_DRC(0, 1, 2, 3, 4, 5, 7, 6, 1, 1, 1, 1, 1, 1, 1, 1, 7, 6, 5, 4, 3, 2, 0, 1); - return TRUE; - case 15: /* 0, 1, 2, 3, 4, 5, 6, 7 - 7 */ /* 7, 7, 7, 7, 7, 7, 7, 7 - 0 */ - RSP_VMADH_DRC(0, 1, 2, 3, 4, 5, 6, 7, 0, 0, 0, 0, 0, 0, 0, 0, 7, 6, 5, 4, 3, 2, 1, 0); - return TRUE; + case 0: /* 0, 1, 2, 3, 4, 5, 6, 7 - none */ /* 0, 1, 2, 3, 4, 5, 6, 7 - none */ + RSP_VMADH_DRC(0, 1, 2, 3, 4, 5, 6, 7, 7, 6, 5, 4, 3, 2, 1, 0, 7, 6, 5, 4, 3, 2, 1, 0); + return TRUE; + case 1: /* 0, 1, 2, 3, 4, 5, 6, 7 - ??? */ /* 0, 1, 2, 3, 4, 5, 6, 7 - ??? */ + RSP_VMADH_DRC(0, 1, 2, 3, 4, 5, 6, 7, 7, 6, 5, 4, 3, 2, 1, 0, 7, 6, 5, 4, 3, 2, 1, 0); + return TRUE; + case 2: /* 1, 3, 5, 7, 0, 2, 4, 6 - 0q */ /* 0, 0, 2, 2, 4, 4, 6, 6 - 0q */ + RSP_VMADH_DRC(1, 3, 5, 7, 0, 2, 4, 6, 7, 5, 3, 1, 7, 5, 3, 1, 6, 4, 2, 0, 7, 5, 3, 1); + return TRUE; + case 3: /* 0, 2, 4, 6, 1, 3, 5, 7 - 1q */ /* 1, 1, 3, 3, 5, 5, 7, 7 - 1q */ + RSP_VMADH_DRC(0, 2, 4, 6, 1, 3, 5, 7, 6, 4, 2, 0, 6, 4, 2, 0, 7, 5, 3, 1, 6, 4, 2, 0); + return TRUE; + case 4: /* 1, 2, 3, 5, 6, 7, 0, 4 - 0h */ /* 0, 0, 0, 0, 4, 4, 4, 4 - 0h */ + RSP_VMADH_DRC(1, 2, 3, 5, 6, 7, 0, 4, 7, 7, 7, 3, 3, 3, 7, 3, 6, 5, 4, 2, 1, 0, 7, 3); + return TRUE; + case 5: /* 0, 2, 3, 4, 6, 7, 1, 5 - 1h */ /* 1, 1, 1, 1, 5, 5, 5, 5 - 1h */ + RSP_VMADH_DRC(0, 2, 3, 4, 6, 7, 1, 5, 6, 6, 6, 2, 2, 2, 6, 2, 7, 5, 4, 3, 1, 0, 6, 2); + return TRUE; + case 6: /* 0, 1, 3, 4, 5, 7, 2, 6 - 2h */ /* 2, 2, 2, 2, 6, 6, 6, 6 - 2h */ + RSP_VMADH_DRC(0, 1, 3, 4, 5, 7, 2, 6, 5, 5, 5, 1, 1, 1, 5, 1, 7, 6, 4, 3, 2, 0, 5, 1); + return TRUE; + case 7: /* 0, 1, 2, 4, 5, 6, 3, 7 - 3h */ /* 3, 3, 3, 3, 7, 7, 7, 7 - 3h */ + RSP_VMADH_DRC(0, 1, 2, 4, 5, 6, 3, 7, 4, 4, 4, 0, 0, 0, 4, 0, 7, 6, 5, 3, 2, 1, 4, 0); + return TRUE; + case 8: /* 1, 2, 3, 4, 5, 6, 7, 0 - 0 */ /* 0, 0, 0, 0, 0, 0, 0, 0 - 0 */ + RSP_VMADH_DRC(1, 2, 3, 4, 5, 6, 7, 0, 7, 7, 7, 7, 7, 7, 7, 7, 6, 5, 4, 3, 2, 1, 0, 7); + return TRUE; + case 9: /* 0, 2, 3, 4, 5, 6, 7, 1 - 1 */ /* 1, 1, 1, 1, 1, 1, 1, 1 - 0 */ + RSP_VMADH_DRC(0, 2, 3, 4, 5, 6, 7, 1, 6, 6, 6, 6, 6, 6, 6, 6, 7, 5, 4, 3, 2, 1, 0, 6); + return TRUE; + case 10: /* 0, 1, 3, 4, 5, 6, 7, 2 - 2 */ /* 2, 2, 2, 2, 2, 2, 2, 2 - 0 */ + RSP_VMADH_DRC(0, 1, 3, 4, 5, 6, 7, 2, 5, 5, 5, 5, 5, 5, 5, 5, 7, 6, 4, 3, 2, 1, 0, 5); + return TRUE; + case 11: /* 0, 1, 2, 4, 5, 6, 7, 3 - 3 */ /* 3, 3, 3, 3, 3, 3, 3, 3 - 0 */ + RSP_VMADH_DRC(0, 1, 2, 4, 5, 6, 7, 3, 4, 4, 4, 4, 4, 4, 4, 4, 7, 6, 5, 3, 2, 1, 0, 4); + return TRUE; + case 12: /* 0, 1, 2, 3, 5, 6, 7, 4 - 4 */ /* 4, 4, 4, 4, 4, 4, 4, 4 - 0 */ + RSP_VMADH_DRC(0, 1, 2, 3, 5, 6, 7, 4, 3, 3, 3, 3, 3, 3, 3, 3, 7, 6, 5, 4, 2, 1, 0, 3); + return TRUE; + case 13: /* 0, 1, 2, 3, 4, 6, 7, 5 - 5 */ /* 5, 5, 5, 5, 5, 5, 5, 5 - 0 */ + RSP_VMADH_DRC(0, 1, 2, 3, 4, 6, 7, 5, 2, 2, 2, 2, 2, 2, 2, 2, 7, 6, 5, 4, 3, 1, 0, 2); + return TRUE; + case 14: /* 0, 1, 2, 3, 4, 5, 7, 6 - 6 */ /* 6, 6, 6, 6, 6, 6, 6, 6 - 0 */ + RSP_VMADH_DRC(0, 1, 2, 3, 4, 5, 7, 6, 1, 1, 1, 1, 1, 1, 1, 1, 7, 6, 5, 4, 3, 2, 0, 1); + return TRUE; + case 15: /* 0, 1, 2, 3, 4, 5, 6, 7 - 7 */ /* 7, 7, 7, 7, 7, 7, 7, 7 - 0 */ + RSP_VMADH_DRC(0, 1, 2, 3, 4, 5, 6, 7, 0, 0, 0, 0, 0, 0, 0, 0, 7, 6, 5, 4, 3, 2, 1, 0); + return TRUE; } return TRUE; @@ -3890,54 +3890,54 @@ INLINE void cfunc_rsp_vmadh(void *param) switch(EL) { - case 0: /* 0, 1, 2, 3, 4, 5, 6, 7 - none */ /* 0, 1, 2, 3, 4, 5, 6, 7 - none */ - RSP_VMADH(0, 1, 2, 3, 4, 5, 6, 7, 7, 6, 5, 4, 3, 2, 1, 0, 7, 6, 5, 4, 3, 2, 1, 0); - break; - case 1: /* 0, 1, 2, 3, 4, 5, 6, 7 - ??? */ /* 0, 1, 2, 3, 4, 5, 6, 7 - ??? */ - RSP_VMADH(0, 1, 2, 3, 4, 5, 6, 7, 7, 6, 5, 4, 3, 2, 1, 0, 7, 6, 5, 4, 3, 2, 1, 0); - break; - case 2: /* 1, 3, 5, 7, 0, 2, 4, 6 - 0q */ /* 0, 0, 2, 2, 4, 4, 6, 6 - 0q */ - RSP_VMADH(1, 3, 5, 7, 0, 2, 4, 6, 7, 5, 3, 1, 7, 5, 3, 1, 6, 4, 2, 0, 7, 5, 3, 1); - break; - case 3: /* 0, 2, 4, 6, 1, 3, 5, 7 - 1q */ /* 1, 1, 3, 3, 5, 5, 7, 7 - 1q */ - RSP_VMADH(0, 2, 4, 6, 1, 3, 5, 7, 6, 4, 2, 0, 6, 4, 2, 0, 7, 5, 3, 1, 6, 4, 2, 0); - break; - case 4: /* 1, 2, 3, 5, 6, 7, 0, 4 - 0h */ /* 0, 0, 0, 0, 4, 4, 4, 4 - 0h */ - RSP_VMADH(1, 2, 3, 5, 6, 7, 0, 4, 7, 7, 7, 3, 3, 3, 7, 3, 6, 5, 4, 2, 1, 0, 7, 3); - break; - case 5: /* 0, 2, 3, 4, 6, 7, 1, 5 - 1h */ /* 1, 1, 1, 1, 5, 5, 5, 5 - 1h */ - RSP_VMADH(0, 2, 3, 4, 6, 7, 1, 5, 6, 6, 6, 2, 2, 2, 6, 2, 7, 5, 4, 3, 1, 0, 6, 2); - break; - case 6: /* 0, 1, 3, 4, 5, 7, 2, 6 - 2h */ /* 2, 2, 2, 2, 6, 6, 6, 6 - 2h */ - RSP_VMADH(0, 1, 3, 4, 5, 7, 2, 6, 5, 5, 5, 1, 1, 1, 5, 1, 7, 6, 4, 3, 2, 0, 5, 1); - break; - case 7: /* 0, 1, 2, 4, 5, 6, 3, 7 - 3h */ /* 3, 3, 3, 3, 7, 7, 7, 7 - 3h */ - RSP_VMADH(0, 1, 2, 4, 5, 6, 3, 7, 4, 4, 4, 0, 0, 0, 4, 0, 7, 6, 5, 3, 2, 1, 4, 0); - break; - case 8: /* 1, 2, 3, 4, 5, 6, 7, 0 - 0 */ /* 0, 0, 0, 0, 0, 0, 0, 0 - 0 */ - RSP_VMADH(1, 2, 3, 4, 5, 6, 7, 0, 7, 7, 7, 7, 7, 7, 7, 7, 6, 5, 4, 3, 2, 1, 0, 7); - break; - case 9: /* 0, 2, 3, 4, 5, 6, 7, 1 - 1 */ /* 1, 1, 1, 1, 1, 1, 1, 1 - 0 */ - RSP_VMADH(0, 2, 3, 4, 5, 6, 7, 1, 6, 6, 6, 6, 6, 6, 6, 6, 7, 5, 4, 3, 2, 1, 0, 6); - break; - case 10: /* 0, 1, 3, 4, 5, 6, 7, 2 - 2 */ /* 2, 2, 2, 2, 2, 2, 2, 2 - 0 */ - RSP_VMADH(0, 1, 3, 4, 5, 6, 7, 2, 5, 5, 5, 5, 5, 5, 5, 5, 7, 6, 4, 3, 2, 1, 0, 5); - break; - case 11: /* 0, 1, 2, 4, 5, 6, 7, 3 - 3 */ /* 3, 3, 3, 3, 3, 3, 3, 3 - 0 */ - RSP_VMADH(0, 1, 2, 4, 5, 6, 7, 3, 4, 4, 4, 4, 4, 4, 4, 4, 7, 6, 5, 3, 2, 1, 0, 4); - break; - case 12: /* 0, 1, 2, 3, 5, 6, 7, 4 - 4 */ /* 4, 4, 4, 4, 4, 4, 4, 4 - 0 */ - RSP_VMADH(0, 1, 2, 3, 5, 6, 7, 4, 3, 3, 3, 3, 3, 3, 3, 3, 7, 6, 5, 4, 2, 1, 0, 3); - break; - case 13: /* 0, 1, 2, 3, 4, 6, 7, 5 - 5 */ /* 5, 5, 5, 5, 5, 5, 5, 5 - 0 */ - RSP_VMADH(0, 1, 2, 3, 4, 6, 7, 5, 2, 2, 2, 2, 2, 2, 2, 2, 7, 6, 5, 4, 3, 1, 0, 2); - break; - case 14: /* 0, 1, 2, 3, 4, 5, 7, 6 - 6 */ /* 6, 6, 6, 6, 6, 6, 6, 6 - 0 */ - RSP_VMADH(0, 1, 2, 3, 4, 5, 7, 6, 1, 1, 1, 1, 1, 1, 1, 1, 7, 6, 5, 4, 3, 2, 0, 1); - break; - case 15: /* 0, 1, 2, 3, 4, 5, 6, 7 - 7 */ /* 7, 7, 7, 7, 7, 7, 7, 7 - 0 */ - RSP_VMADH(0, 1, 2, 3, 4, 5, 6, 7, 0, 0, 0, 0, 0, 0, 0, 0, 7, 6, 5, 4, 3, 2, 1, 0); - break; + case 0: /* 0, 1, 2, 3, 4, 5, 6, 7 - none */ /* 0, 1, 2, 3, 4, 5, 6, 7 - none */ + RSP_VMADH(0, 1, 2, 3, 4, 5, 6, 7, 7, 6, 5, 4, 3, 2, 1, 0, 7, 6, 5, 4, 3, 2, 1, 0); + break; + case 1: /* 0, 1, 2, 3, 4, 5, 6, 7 - ??? */ /* 0, 1, 2, 3, 4, 5, 6, 7 - ??? */ + RSP_VMADH(0, 1, 2, 3, 4, 5, 6, 7, 7, 6, 5, 4, 3, 2, 1, 0, 7, 6, 5, 4, 3, 2, 1, 0); + break; + case 2: /* 1, 3, 5, 7, 0, 2, 4, 6 - 0q */ /* 0, 0, 2, 2, 4, 4, 6, 6 - 0q */ + RSP_VMADH(1, 3, 5, 7, 0, 2, 4, 6, 7, 5, 3, 1, 7, 5, 3, 1, 6, 4, 2, 0, 7, 5, 3, 1); + break; + case 3: /* 0, 2, 4, 6, 1, 3, 5, 7 - 1q */ /* 1, 1, 3, 3, 5, 5, 7, 7 - 1q */ + RSP_VMADH(0, 2, 4, 6, 1, 3, 5, 7, 6, 4, 2, 0, 6, 4, 2, 0, 7, 5, 3, 1, 6, 4, 2, 0); + break; + case 4: /* 1, 2, 3, 5, 6, 7, 0, 4 - 0h */ /* 0, 0, 0, 0, 4, 4, 4, 4 - 0h */ + RSP_VMADH(1, 2, 3, 5, 6, 7, 0, 4, 7, 7, 7, 3, 3, 3, 7, 3, 6, 5, 4, 2, 1, 0, 7, 3); + break; + case 5: /* 0, 2, 3, 4, 6, 7, 1, 5 - 1h */ /* 1, 1, 1, 1, 5, 5, 5, 5 - 1h */ + RSP_VMADH(0, 2, 3, 4, 6, 7, 1, 5, 6, 6, 6, 2, 2, 2, 6, 2, 7, 5, 4, 3, 1, 0, 6, 2); + break; + case 6: /* 0, 1, 3, 4, 5, 7, 2, 6 - 2h */ /* 2, 2, 2, 2, 6, 6, 6, 6 - 2h */ + RSP_VMADH(0, 1, 3, 4, 5, 7, 2, 6, 5, 5, 5, 1, 1, 1, 5, 1, 7, 6, 4, 3, 2, 0, 5, 1); + break; + case 7: /* 0, 1, 2, 4, 5, 6, 3, 7 - 3h */ /* 3, 3, 3, 3, 7, 7, 7, 7 - 3h */ + RSP_VMADH(0, 1, 2, 4, 5, 6, 3, 7, 4, 4, 4, 0, 0, 0, 4, 0, 7, 6, 5, 3, 2, 1, 4, 0); + break; + case 8: /* 1, 2, 3, 4, 5, 6, 7, 0 - 0 */ /* 0, 0, 0, 0, 0, 0, 0, 0 - 0 */ + RSP_VMADH(1, 2, 3, 4, 5, 6, 7, 0, 7, 7, 7, 7, 7, 7, 7, 7, 6, 5, 4, 3, 2, 1, 0, 7); + break; + case 9: /* 0, 2, 3, 4, 5, 6, 7, 1 - 1 */ /* 1, 1, 1, 1, 1, 1, 1, 1 - 0 */ + RSP_VMADH(0, 2, 3, 4, 5, 6, 7, 1, 6, 6, 6, 6, 6, 6, 6, 6, 7, 5, 4, 3, 2, 1, 0, 6); + break; + case 10: /* 0, 1, 3, 4, 5, 6, 7, 2 - 2 */ /* 2, 2, 2, 2, 2, 2, 2, 2 - 0 */ + RSP_VMADH(0, 1, 3, 4, 5, 6, 7, 2, 5, 5, 5, 5, 5, 5, 5, 5, 7, 6, 4, 3, 2, 1, 0, 5); + break; + case 11: /* 0, 1, 2, 4, 5, 6, 7, 3 - 3 */ /* 3, 3, 3, 3, 3, 3, 3, 3 - 0 */ + RSP_VMADH(0, 1, 2, 4, 5, 6, 7, 3, 4, 4, 4, 4, 4, 4, 4, 4, 7, 6, 5, 3, 2, 1, 0, 4); + break; + case 12: /* 0, 1, 2, 3, 5, 6, 7, 4 - 4 */ /* 4, 4, 4, 4, 4, 4, 4, 4 - 0 */ + RSP_VMADH(0, 1, 2, 3, 5, 6, 7, 4, 3, 3, 3, 3, 3, 3, 3, 3, 7, 6, 5, 4, 2, 1, 0, 3); + break; + case 13: /* 0, 1, 2, 3, 4, 6, 7, 5 - 5 */ /* 5, 5, 5, 5, 5, 5, 5, 5 - 0 */ + RSP_VMADH(0, 1, 2, 3, 4, 6, 7, 5, 2, 2, 2, 2, 2, 2, 2, 2, 7, 6, 5, 4, 3, 1, 0, 2); + break; + case 14: /* 0, 1, 2, 3, 4, 5, 7, 6 - 6 */ /* 6, 6, 6, 6, 6, 6, 6, 6 - 0 */ + RSP_VMADH(0, 1, 2, 3, 4, 5, 7, 6, 1, 1, 1, 1, 1, 1, 1, 1, 7, 6, 5, 4, 3, 2, 0, 1); + break; + case 15: /* 0, 1, 2, 3, 4, 5, 6, 7 - 7 */ /* 7, 7, 7, 7, 7, 7, 7, 7 - 0 */ + RSP_VMADH(0, 1, 2, 3, 4, 5, 6, 7, 0, 0, 0, 0, 0, 0, 0, 0, 7, 6, 5, 4, 3, 2, 1, 0); + break; } } #endif @@ -3971,12 +3971,12 @@ INLINE void cfunc_rsp_vmadh(void *param) UML_CMP(block, IREG(0), IMM(-32768)); \ UML_JMPc(block, IF_G, inrange = compiler->labelnum++); \ \ - UML_MOV(block, IREG(0), IMM(-32768)); \ + UML_MOV(block, IREG(0), IMM(-32768)); \ \ UML_LABEL(block, inrange); \ UML_LABEL(block, outofrange); \ \ - UML_MOV(block, VRES(E10), IREG(0)); \ + UML_MOV(block, VRES(E10), IREG(0)); \ \ \ UML_SEXT(block, IREG(0), VS(VS1REG, I1), WORD); \ @@ -3999,12 +3999,12 @@ INLINE void cfunc_rsp_vmadh(void *param) UML_CMP(block, IREG(0), IMM(-32768)); \ UML_JMPc(block, IF_GE, inrange = compiler->labelnum++); \ \ - UML_MOV(block, IREG(0), IMM(-32768)); \ + UML_MOV(block, IREG(0), IMM(-32768)); \ \ UML_LABEL(block, inrange); \ UML_LABEL(block, outofrange); \ \ - UML_MOV(block, VRES(E11), IREG(0)); \ + UML_MOV(block, VRES(E11), IREG(0)); \ \ \ UML_SEXT(block, IREG(0), VS(VS1REG, I2), WORD); \ @@ -4027,12 +4027,12 @@ INLINE void cfunc_rsp_vmadh(void *param) UML_CMP(block, IREG(0), IMM(-32768)); \ UML_JMPc(block, IF_GE, inrange = compiler->labelnum++); \ \ - UML_MOV(block, IREG(0), IMM(-32768)); \ + UML_MOV(block, IREG(0), IMM(-32768)); \ \ UML_LABEL(block, inrange); \ UML_LABEL(block, outofrange); \ \ - UML_MOV(block, VRES(E12), IREG(0)); \ + UML_MOV(block, VRES(E12), IREG(0)); \ \ \ UML_SEXT(block, IREG(0), VS(VS1REG, I3), WORD); \ @@ -4055,12 +4055,12 @@ INLINE void cfunc_rsp_vmadh(void *param) UML_CMP(block, IREG(0), IMM(-32768)); \ UML_JMPc(block, IF_GE, inrange = compiler->labelnum++); \ \ - UML_MOV(block, IREG(0), IMM(-32768)); \ + UML_MOV(block, IREG(0), IMM(-32768)); \ \ UML_LABEL(block, inrange); \ UML_LABEL(block, outofrange); \ \ - UML_MOV(block, VRES(E13), IREG(0)); \ + UML_MOV(block, VRES(E13), IREG(0)); \ \ \ UML_SEXT(block, IREG(0), VS(VS1REG, I4), WORD); \ @@ -4083,12 +4083,12 @@ INLINE void cfunc_rsp_vmadh(void *param) UML_CMP(block, IREG(0), IMM(-32768)); \ UML_JMPc(block, IF_GE, inrange = compiler->labelnum++); \ \ - UML_MOV(block, IREG(0), IMM(-32768)); \ + UML_MOV(block, IREG(0), IMM(-32768)); \ \ UML_LABEL(block, inrange); \ UML_LABEL(block, outofrange); \ \ - UML_MOV(block, VRES(E14), IREG(0)); \ + UML_MOV(block, VRES(E14), IREG(0)); \ \ \ UML_SEXT(block, IREG(0), VS(VS1REG, I5), WORD); \ @@ -4111,12 +4111,12 @@ INLINE void cfunc_rsp_vmadh(void *param) UML_CMP(block, IREG(0), IMM(-32768)); \ UML_JMPc(block, IF_GE, inrange = compiler->labelnum++); \ \ - UML_MOV(block, IREG(0), IMM(-32768)); \ + UML_MOV(block, IREG(0), IMM(-32768)); \ \ UML_LABEL(block, inrange); \ UML_LABEL(block, outofrange); \ \ - UML_MOV(block, VRES(E15), IREG(0)); \ + UML_MOV(block, VRES(E15), IREG(0)); \ \ \ UML_SEXT(block, IREG(0), VS(VS1REG, I6), WORD); \ @@ -4139,12 +4139,12 @@ INLINE void cfunc_rsp_vmadh(void *param) UML_CMP(block, IREG(0), IMM(-32768)); \ UML_JMPc(block, IF_GE, inrange = compiler->labelnum++); \ \ - UML_MOV(block, IREG(0), IMM(-32768)); \ + UML_MOV(block, IREG(0), IMM(-32768)); \ \ UML_LABEL(block, inrange); \ UML_LABEL(block, outofrange); \ \ - UML_MOV(block, VRES(E16), IREG(0)); \ + UML_MOV(block, VRES(E16), IREG(0)); \ \ \ UML_SEXT(block, IREG(0), VS(VS1REG, I7), WORD); \ @@ -4167,22 +4167,22 @@ INLINE void cfunc_rsp_vmadh(void *param) UML_CMP(block, IREG(0), IMM(-32768)); \ UML_JMPc(block, IF_GE, inrange = compiler->labelnum++); \ \ - UML_MOV(block, IREG(0), IMM(-32768)); \ + UML_MOV(block, IREG(0), IMM(-32768)); \ \ UML_LABEL(block, inrange); \ UML_LABEL(block, outofrange); \ \ - UML_MOV(block, VRES(E17), IREG(0)); \ + UML_MOV(block, VRES(E17), IREG(0)); \ \ \ - UML_STORE(block, &rsp->v[VDREG].s[I0], IMM(0), VRES(E10), WORD); \ - UML_STORE(block, &rsp->v[VDREG].s[I1], IMM(0), VRES(E11), WORD); \ - UML_STORE(block, &rsp->v[VDREG].s[I2], IMM(0), VRES(E12), WORD); \ - UML_STORE(block, &rsp->v[VDREG].s[I3], IMM(0), VRES(E13), WORD); \ - UML_STORE(block, &rsp->v[VDREG].s[I4], IMM(0), VRES(E14), WORD); \ - UML_STORE(block, &rsp->v[VDREG].s[I5], IMM(0), VRES(E15), WORD); \ - UML_STORE(block, &rsp->v[VDREG].s[I6], IMM(0), VRES(E16), WORD); \ - UML_STORE(block, &rsp->v[VDREG].s[I7], IMM(0), VRES(E17), WORD); \ + UML_STORE(block, &rsp->v[VDREG].s[I0], IMM(0), VRES(E10), WORD); \ + UML_STORE(block, &rsp->v[VDREG].s[I1], IMM(0), VRES(E11), WORD); \ + UML_STORE(block, &rsp->v[VDREG].s[I2], IMM(0), VRES(E12), WORD); \ + UML_STORE(block, &rsp->v[VDREG].s[I3], IMM(0), VRES(E13), WORD); \ + UML_STORE(block, &rsp->v[VDREG].s[I4], IMM(0), VRES(E14), WORD); \ + UML_STORE(block, &rsp->v[VDREG].s[I5], IMM(0), VRES(E15), WORD); \ + UML_STORE(block, &rsp->v[VDREG].s[I6], IMM(0), VRES(E16), WORD); \ + UML_STORE(block, &rsp->v[VDREG].s[I7], IMM(0), VRES(E17), WORD); \ } static int generate_vadd(rsp_state *rsp, drcuml_block *block, compiler_state *compiler, const opcode_desc *desc) // vadd @@ -4199,54 +4199,54 @@ static int generate_vadd(rsp_state *rsp, drcuml_block *block, compiler_state *co // The low slice of accumulator is stored into destination element switch(EL) { - case 0: /* 0, 1, 2, 3, 4, 5, 6, 7 - none */ /* 0, 1, 2, 3, 4, 5, 6, 7 - none */ - RSP_VADD_DRC(0, 1, 2, 3, 4, 5, 6, 7, 7, 6, 5, 4, 3, 2, 1, 0, 7, 6, 5, 4, 3, 2, 1, 0); - return TRUE; - case 1: /* 0, 1, 2, 3, 4, 5, 6, 7 - ??? */ /* 0, 1, 2, 3, 4, 5, 6, 7 - ??? */ - RSP_VADD_DRC(0, 1, 2, 3, 4, 5, 6, 7, 7, 6, 5, 4, 3, 2, 1, 0, 7, 6, 5, 4, 3, 2, 1, 0); - return TRUE; - case 2: /* 1, 3, 5, 7, 0, 2, 4, 6 - 0q */ /* 0, 0, 2, 2, 4, 4, 6, 6 - 0q */ - RSP_VADD_DRC(1, 3, 5, 7, 0, 2, 4, 6, 7, 5, 3, 1, 7, 5, 3, 1, 6, 4, 2, 0, 7, 5, 3, 1); - return TRUE; - case 3: /* 0, 2, 4, 6, 1, 3, 5, 7 - 1q */ /* 1, 1, 3, 3, 5, 5, 7, 7 - 1q */ - RSP_VADD_DRC(0, 2, 4, 6, 1, 3, 5, 7, 6, 4, 2, 0, 6, 4, 2, 0, 7, 5, 3, 1, 6, 4, 2, 0); - return TRUE; - case 4: /* 1, 2, 3, 5, 6, 7, 0, 4 - 0h */ /* 0, 0, 0, 0, 4, 4, 4, 4 - 0h */ - RSP_VADD_DRC(1, 2, 3, 5, 6, 7, 0, 4, 7, 7, 7, 3, 3, 3, 7, 3, 6, 5, 4, 2, 1, 0, 7, 3); - return TRUE; - case 5: /* 0, 2, 3, 4, 6, 7, 1, 5 - 1h */ /* 1, 1, 1, 1, 5, 5, 5, 5 - 1h */ - RSP_VADD_DRC(0, 2, 3, 4, 6, 7, 1, 5, 6, 6, 6, 2, 2, 2, 6, 2, 7, 5, 4, 3, 1, 0, 6, 2); - return TRUE; - case 6: /* 0, 1, 3, 4, 5, 7, 2, 6 - 2h */ /* 2, 2, 2, 2, 6, 6, 6, 6 - 2h */ - RSP_VADD_DRC(0, 1, 3, 4, 5, 7, 2, 6, 5, 5, 5, 1, 1, 1, 5, 1, 7, 6, 4, 3, 2, 0, 5, 1); - return TRUE; - case 7: /* 0, 1, 2, 4, 5, 6, 3, 7 - 3h */ /* 3, 3, 3, 3, 7, 7, 7, 7 - 3h */ - RSP_VADD_DRC(0, 1, 2, 4, 5, 6, 3, 7, 4, 4, 4, 0, 0, 0, 4, 0, 7, 6, 5, 3, 2, 1, 4, 0); - return TRUE; - case 8: /* 1, 2, 3, 4, 5, 6, 7, 0 - 0 */ /* 0, 0, 0, 0, 0, 0, 0, 0 - 0 */ - RSP_VADD_DRC(1, 2, 3, 4, 5, 6, 7, 0, 7, 7, 7, 7, 7, 7, 7, 7, 6, 5, 4, 3, 2, 1, 0, 7); - return TRUE; - case 9: /* 0, 2, 3, 4, 5, 6, 7, 1 - 1 */ /* 1, 1, 1, 1, 1, 1, 1, 1 - 0 */ - RSP_VADD_DRC(0, 2, 3, 4, 5, 6, 7, 1, 6, 6, 6, 6, 6, 6, 6, 6, 7, 5, 4, 3, 2, 1, 0, 6); - return TRUE; - case 10: /* 0, 1, 3, 4, 5, 6, 7, 2 - 2 */ /* 2, 2, 2, 2, 2, 2, 2, 2 - 0 */ - RSP_VADD_DRC(0, 1, 3, 4, 5, 6, 7, 2, 5, 5, 5, 5, 5, 5, 5, 5, 7, 6, 4, 3, 2, 1, 0, 5); - return TRUE; - case 11: /* 0, 1, 2, 4, 5, 6, 7, 3 - 3 */ /* 3, 3, 3, 3, 3, 3, 3, 3 - 0 */ - RSP_VADD_DRC(0, 1, 2, 4, 5, 6, 7, 3, 4, 4, 4, 4, 4, 4, 4, 4, 7, 6, 5, 3, 2, 1, 0, 4); - return TRUE; - case 12: /* 0, 1, 2, 3, 5, 6, 7, 4 - 4 */ /* 4, 4, 4, 4, 4, 4, 4, 4 - 0 */ - RSP_VADD_DRC(0, 1, 2, 3, 5, 6, 7, 4, 3, 3, 3, 3, 3, 3, 3, 3, 7, 6, 5, 4, 2, 1, 0, 3); - return TRUE; - case 13: /* 0, 1, 2, 3, 4, 6, 7, 5 - 5 */ /* 5, 5, 5, 5, 5, 5, 5, 5 - 0 */ - RSP_VADD_DRC(0, 1, 2, 3, 4, 6, 7, 5, 2, 2, 2, 2, 2, 2, 2, 2, 7, 6, 5, 4, 3, 1, 0, 2); - return TRUE; - case 14: /* 0, 1, 2, 3, 4, 5, 7, 6 - 6 */ /* 6, 6, 6, 6, 6, 6, 6, 6 - 0 */ - RSP_VADD_DRC(0, 1, 2, 3, 4, 5, 7, 6, 1, 1, 1, 1, 1, 1, 1, 1, 7, 6, 5, 4, 3, 2, 0, 1); - return TRUE; - case 15: /* 0, 1, 2, 3, 4, 5, 6, 7 - 7 */ /* 7, 7, 7, 7, 7, 7, 7, 7 - 0 */ - RSP_VADD_DRC(0, 1, 2, 3, 4, 5, 6, 7, 0, 0, 0, 0, 0, 0, 0, 0, 7, 6, 5, 4, 3, 2, 1, 0); - return TRUE; + case 0: /* 0, 1, 2, 3, 4, 5, 6, 7 - none */ /* 0, 1, 2, 3, 4, 5, 6, 7 - none */ + RSP_VADD_DRC(0, 1, 2, 3, 4, 5, 6, 7, 7, 6, 5, 4, 3, 2, 1, 0, 7, 6, 5, 4, 3, 2, 1, 0); + return TRUE; + case 1: /* 0, 1, 2, 3, 4, 5, 6, 7 - ??? */ /* 0, 1, 2, 3, 4, 5, 6, 7 - ??? */ + RSP_VADD_DRC(0, 1, 2, 3, 4, 5, 6, 7, 7, 6, 5, 4, 3, 2, 1, 0, 7, 6, 5, 4, 3, 2, 1, 0); + return TRUE; + case 2: /* 1, 3, 5, 7, 0, 2, 4, 6 - 0q */ /* 0, 0, 2, 2, 4, 4, 6, 6 - 0q */ + RSP_VADD_DRC(1, 3, 5, 7, 0, 2, 4, 6, 7, 5, 3, 1, 7, 5, 3, 1, 6, 4, 2, 0, 7, 5, 3, 1); + return TRUE; + case 3: /* 0, 2, 4, 6, 1, 3, 5, 7 - 1q */ /* 1, 1, 3, 3, 5, 5, 7, 7 - 1q */ + RSP_VADD_DRC(0, 2, 4, 6, 1, 3, 5, 7, 6, 4, 2, 0, 6, 4, 2, 0, 7, 5, 3, 1, 6, 4, 2, 0); + return TRUE; + case 4: /* 1, 2, 3, 5, 6, 7, 0, 4 - 0h */ /* 0, 0, 0, 0, 4, 4, 4, 4 - 0h */ + RSP_VADD_DRC(1, 2, 3, 5, 6, 7, 0, 4, 7, 7, 7, 3, 3, 3, 7, 3, 6, 5, 4, 2, 1, 0, 7, 3); + return TRUE; + case 5: /* 0, 2, 3, 4, 6, 7, 1, 5 - 1h */ /* 1, 1, 1, 1, 5, 5, 5, 5 - 1h */ + RSP_VADD_DRC(0, 2, 3, 4, 6, 7, 1, 5, 6, 6, 6, 2, 2, 2, 6, 2, 7, 5, 4, 3, 1, 0, 6, 2); + return TRUE; + case 6: /* 0, 1, 3, 4, 5, 7, 2, 6 - 2h */ /* 2, 2, 2, 2, 6, 6, 6, 6 - 2h */ + RSP_VADD_DRC(0, 1, 3, 4, 5, 7, 2, 6, 5, 5, 5, 1, 1, 1, 5, 1, 7, 6, 4, 3, 2, 0, 5, 1); + return TRUE; + case 7: /* 0, 1, 2, 4, 5, 6, 3, 7 - 3h */ /* 3, 3, 3, 3, 7, 7, 7, 7 - 3h */ + RSP_VADD_DRC(0, 1, 2, 4, 5, 6, 3, 7, 4, 4, 4, 0, 0, 0, 4, 0, 7, 6, 5, 3, 2, 1, 4, 0); + return TRUE; + case 8: /* 1, 2, 3, 4, 5, 6, 7, 0 - 0 */ /* 0, 0, 0, 0, 0, 0, 0, 0 - 0 */ + RSP_VADD_DRC(1, 2, 3, 4, 5, 6, 7, 0, 7, 7, 7, 7, 7, 7, 7, 7, 6, 5, 4, 3, 2, 1, 0, 7); + return TRUE; + case 9: /* 0, 2, 3, 4, 5, 6, 7, 1 - 1 */ /* 1, 1, 1, 1, 1, 1, 1, 1 - 0 */ + RSP_VADD_DRC(0, 2, 3, 4, 5, 6, 7, 1, 6, 6, 6, 6, 6, 6, 6, 6, 7, 5, 4, 3, 2, 1, 0, 6); + return TRUE; + case 10: /* 0, 1, 3, 4, 5, 6, 7, 2 - 2 */ /* 2, 2, 2, 2, 2, 2, 2, 2 - 0 */ + RSP_VADD_DRC(0, 1, 3, 4, 5, 6, 7, 2, 5, 5, 5, 5, 5, 5, 5, 5, 7, 6, 4, 3, 2, 1, 0, 5); + return TRUE; + case 11: /* 0, 1, 2, 4, 5, 6, 7, 3 - 3 */ /* 3, 3, 3, 3, 3, 3, 3, 3 - 0 */ + RSP_VADD_DRC(0, 1, 2, 4, 5, 6, 7, 3, 4, 4, 4, 4, 4, 4, 4, 4, 7, 6, 5, 3, 2, 1, 0, 4); + return TRUE; + case 12: /* 0, 1, 2, 3, 5, 6, 7, 4 - 4 */ /* 4, 4, 4, 4, 4, 4, 4, 4 - 0 */ + RSP_VADD_DRC(0, 1, 2, 3, 5, 6, 7, 4, 3, 3, 3, 3, 3, 3, 3, 3, 7, 6, 5, 4, 2, 1, 0, 3); + return TRUE; + case 13: /* 0, 1, 2, 3, 4, 6, 7, 5 - 5 */ /* 5, 5, 5, 5, 5, 5, 5, 5 - 0 */ + RSP_VADD_DRC(0, 1, 2, 3, 4, 6, 7, 5, 2, 2, 2, 2, 2, 2, 2, 2, 7, 6, 5, 4, 3, 1, 0, 2); + return TRUE; + case 14: /* 0, 1, 2, 3, 4, 5, 7, 6 - 6 */ /* 6, 6, 6, 6, 6, 6, 6, 6 - 0 */ + RSP_VADD_DRC(0, 1, 2, 3, 4, 5, 7, 6, 1, 1, 1, 1, 1, 1, 1, 1, 7, 6, 5, 4, 3, 2, 0, 1); + return TRUE; + case 15: /* 0, 1, 2, 3, 4, 5, 6, 7 - 7 */ /* 7, 7, 7, 7, 7, 7, 7, 7 - 0 */ + RSP_VADD_DRC(0, 1, 2, 3, 4, 5, 6, 7, 0, 0, 0, 0, 0, 0, 0, 0, 7, 6, 5, 4, 3, 2, 1, 0); + return TRUE; } return TRUE; @@ -4287,57 +4287,57 @@ INLINE void cfunc_rsp_vadd(void *param) // Adds two vector registers and carry flag, the result is saturated to 32767 // TODO: check VS2REG == VDREG - switch(EL) - { - case 0: /* 0, 1, 2, 3, 4, 5, 6, 7 - none */ /* 0, 1, 2, 3, 4, 5, 6, 7 - none */ - RSP_VADD(0, 1, 2, 3, 4, 5, 6, 7, 7, 6, 5, 4, 3, 2, 1, 0, 7, 6, 5, 4, 3, 2, 1, 0); - break; - case 1: /* 0, 1, 2, 3, 4, 5, 6, 7 - ??? */ /* 0, 1, 2, 3, 4, 5, 6, 7 - ??? */ - RSP_VADD(0, 1, 2, 3, 4, 5, 6, 7, 7, 6, 5, 4, 3, 2, 1, 0, 7, 6, 5, 4, 3, 2, 1, 0); - break; - case 2: /* 1, 3, 5, 7, 0, 2, 4, 6 - 0q */ /* 0, 0, 2, 2, 4, 4, 6, 6 - 0q */ - RSP_VADD(1, 3, 5, 7, 0, 2, 4, 6, 7, 5, 3, 1, 7, 5, 3, 1, 6, 4, 2, 0, 7, 5, 3, 1); - break; - case 3: /* 0, 2, 4, 6, 1, 3, 5, 7 - 1q */ /* 1, 1, 3, 3, 5, 5, 7, 7 - 1q */ - RSP_VADD(0, 2, 4, 6, 1, 3, 5, 7, 6, 4, 2, 0, 6, 4, 2, 0, 7, 5, 3, 1, 6, 4, 2, 0); - break; - case 4: /* 1, 2, 3, 5, 6, 7, 0, 4 - 0h */ /* 0, 0, 0, 0, 4, 4, 4, 4 - 0h */ - RSP_VADD(1, 2, 3, 5, 6, 7, 0, 4, 7, 7, 7, 3, 3, 3, 7, 3, 6, 5, 4, 2, 1, 0, 7, 3); - break; - case 5: /* 0, 2, 3, 4, 6, 7, 1, 5 - 1h */ /* 1, 1, 1, 1, 5, 5, 5, 5 - 1h */ - RSP_VADD(0, 2, 3, 4, 6, 7, 1, 5, 6, 6, 6, 2, 2, 2, 6, 2, 7, 5, 4, 3, 1, 0, 6, 2); - break; - case 6: /* 0, 1, 3, 4, 5, 7, 2, 6 - 2h */ /* 2, 2, 2, 2, 6, 6, 6, 6 - 2h */ - RSP_VADD(0, 1, 3, 4, 5, 7, 2, 6, 5, 5, 5, 1, 1, 1, 5, 1, 7, 6, 4, 3, 2, 0, 5, 1); - break; - case 7: /* 0, 1, 2, 4, 5, 6, 3, 7 - 3h */ /* 3, 3, 3, 3, 7, 7, 7, 7 - 3h */ - RSP_VADD(0, 1, 2, 4, 5, 6, 3, 7, 4, 4, 4, 0, 0, 0, 4, 0, 7, 6, 5, 3, 2, 1, 4, 0); - break; - case 8: /* 1, 2, 3, 4, 5, 6, 7, 0 - 0 */ /* 0, 0, 0, 0, 0, 0, 0, 0 - 0 */ - RSP_VADD(1, 2, 3, 4, 5, 6, 7, 0, 7, 7, 7, 7, 7, 7, 7, 7, 6, 5, 4, 3, 2, 1, 0, 7); - break; - case 9: /* 0, 2, 3, 4, 5, 6, 7, 1 - 1 */ /* 1, 1, 1, 1, 1, 1, 1, 1 - 0 */ - RSP_VADD(0, 2, 3, 4, 5, 6, 7, 1, 6, 6, 6, 6, 6, 6, 6, 6, 7, 5, 4, 3, 2, 1, 0, 6); - break; - case 10: /* 0, 1, 3, 4, 5, 6, 7, 2 - 2 */ /* 2, 2, 2, 2, 2, 2, 2, 2 - 0 */ - RSP_VADD(0, 1, 3, 4, 5, 6, 7, 2, 5, 5, 5, 5, 5, 5, 5, 5, 7, 6, 4, 3, 2, 1, 0, 5); - break; - case 11: /* 0, 1, 2, 4, 5, 6, 7, 3 - 3 */ /* 3, 3, 3, 3, 3, 3, 3, 3 - 0 */ - RSP_VADD(0, 1, 2, 4, 5, 6, 7, 3, 4, 4, 4, 4, 4, 4, 4, 4, 7, 6, 5, 3, 2, 1, 0, 4); - break; - case 12: /* 0, 1, 2, 3, 5, 6, 7, 4 - 4 */ /* 4, 4, 4, 4, 4, 4, 4, 4 - 0 */ - RSP_VADD(0, 1, 2, 3, 5, 6, 7, 4, 3, 3, 3, 3, 3, 3, 3, 3, 7, 6, 5, 4, 2, 1, 0, 3); - break; - case 13: /* 0, 1, 2, 3, 4, 6, 7, 5 - 5 */ /* 5, 5, 5, 5, 5, 5, 5, 5 - 0 */ - RSP_VADD(0, 1, 2, 3, 4, 6, 7, 5, 2, 2, 2, 2, 2, 2, 2, 2, 7, 6, 5, 4, 3, 1, 0, 2); - break; - case 14: /* 0, 1, 2, 3, 4, 5, 7, 6 - 6 */ /* 6, 6, 6, 6, 6, 6, 6, 6 - 0 */ - RSP_VADD(0, 1, 2, 3, 4, 5, 7, 6, 1, 1, 1, 1, 1, 1, 1, 1, 7, 6, 5, 4, 3, 2, 0, 1); - break; - case 15: /* 0, 1, 2, 3, 4, 5, 6, 7 - 7 */ /* 7, 7, 7, 7, 7, 7, 7, 7 - 0 */ - RSP_VADD(0, 1, 2, 3, 4, 5, 6, 7, 0, 0, 0, 0, 0, 0, 0, 0, 7, 6, 5, 4, 3, 2, 1, 0); - break; - } + switch(EL) + { + case 0: /* 0, 1, 2, 3, 4, 5, 6, 7 - none */ /* 0, 1, 2, 3, 4, 5, 6, 7 - none */ + RSP_VADD(0, 1, 2, 3, 4, 5, 6, 7, 7, 6, 5, 4, 3, 2, 1, 0, 7, 6, 5, 4, 3, 2, 1, 0); + break; + case 1: /* 0, 1, 2, 3, 4, 5, 6, 7 - ??? */ /* 0, 1, 2, 3, 4, 5, 6, 7 - ??? */ + RSP_VADD(0, 1, 2, 3, 4, 5, 6, 7, 7, 6, 5, 4, 3, 2, 1, 0, 7, 6, 5, 4, 3, 2, 1, 0); + break; + case 2: /* 1, 3, 5, 7, 0, 2, 4, 6 - 0q */ /* 0, 0, 2, 2, 4, 4, 6, 6 - 0q */ + RSP_VADD(1, 3, 5, 7, 0, 2, 4, 6, 7, 5, 3, 1, 7, 5, 3, 1, 6, 4, 2, 0, 7, 5, 3, 1); + break; + case 3: /* 0, 2, 4, 6, 1, 3, 5, 7 - 1q */ /* 1, 1, 3, 3, 5, 5, 7, 7 - 1q */ + RSP_VADD(0, 2, 4, 6, 1, 3, 5, 7, 6, 4, 2, 0, 6, 4, 2, 0, 7, 5, 3, 1, 6, 4, 2, 0); + break; + case 4: /* 1, 2, 3, 5, 6, 7, 0, 4 - 0h */ /* 0, 0, 0, 0, 4, 4, 4, 4 - 0h */ + RSP_VADD(1, 2, 3, 5, 6, 7, 0, 4, 7, 7, 7, 3, 3, 3, 7, 3, 6, 5, 4, 2, 1, 0, 7, 3); + break; + case 5: /* 0, 2, 3, 4, 6, 7, 1, 5 - 1h */ /* 1, 1, 1, 1, 5, 5, 5, 5 - 1h */ + RSP_VADD(0, 2, 3, 4, 6, 7, 1, 5, 6, 6, 6, 2, 2, 2, 6, 2, 7, 5, 4, 3, 1, 0, 6, 2); + break; + case 6: /* 0, 1, 3, 4, 5, 7, 2, 6 - 2h */ /* 2, 2, 2, 2, 6, 6, 6, 6 - 2h */ + RSP_VADD(0, 1, 3, 4, 5, 7, 2, 6, 5, 5, 5, 1, 1, 1, 5, 1, 7, 6, 4, 3, 2, 0, 5, 1); + break; + case 7: /* 0, 1, 2, 4, 5, 6, 3, 7 - 3h */ /* 3, 3, 3, 3, 7, 7, 7, 7 - 3h */ + RSP_VADD(0, 1, 2, 4, 5, 6, 3, 7, 4, 4, 4, 0, 0, 0, 4, 0, 7, 6, 5, 3, 2, 1, 4, 0); + break; + case 8: /* 1, 2, 3, 4, 5, 6, 7, 0 - 0 */ /* 0, 0, 0, 0, 0, 0, 0, 0 - 0 */ + RSP_VADD(1, 2, 3, 4, 5, 6, 7, 0, 7, 7, 7, 7, 7, 7, 7, 7, 6, 5, 4, 3, 2, 1, 0, 7); + break; + case 9: /* 0, 2, 3, 4, 5, 6, 7, 1 - 1 */ /* 1, 1, 1, 1, 1, 1, 1, 1 - 0 */ + RSP_VADD(0, 2, 3, 4, 5, 6, 7, 1, 6, 6, 6, 6, 6, 6, 6, 6, 7, 5, 4, 3, 2, 1, 0, 6); + break; + case 10: /* 0, 1, 3, 4, 5, 6, 7, 2 - 2 */ /* 2, 2, 2, 2, 2, 2, 2, 2 - 0 */ + RSP_VADD(0, 1, 3, 4, 5, 6, 7, 2, 5, 5, 5, 5, 5, 5, 5, 5, 7, 6, 4, 3, 2, 1, 0, 5); + break; + case 11: /* 0, 1, 2, 4, 5, 6, 7, 3 - 3 */ /* 3, 3, 3, 3, 3, 3, 3, 3 - 0 */ + RSP_VADD(0, 1, 2, 4, 5, 6, 7, 3, 4, 4, 4, 4, 4, 4, 4, 4, 7, 6, 5, 3, 2, 1, 0, 4); + break; + case 12: /* 0, 1, 2, 3, 5, 6, 7, 4 - 4 */ /* 4, 4, 4, 4, 4, 4, 4, 4 - 0 */ + RSP_VADD(0, 1, 2, 3, 5, 6, 7, 4, 3, 3, 3, 3, 3, 3, 3, 3, 7, 6, 5, 4, 2, 1, 0, 3); + break; + case 13: /* 0, 1, 2, 3, 4, 6, 7, 5 - 5 */ /* 5, 5, 5, 5, 5, 5, 5, 5 - 0 */ + RSP_VADD(0, 1, 2, 3, 4, 6, 7, 5, 2, 2, 2, 2, 2, 2, 2, 2, 7, 6, 5, 4, 3, 1, 0, 2); + break; + case 14: /* 0, 1, 2, 3, 4, 5, 7, 6 - 6 */ /* 6, 6, 6, 6, 6, 6, 6, 6 - 0 */ + RSP_VADD(0, 1, 2, 3, 4, 5, 7, 6, 1, 1, 1, 1, 1, 1, 1, 1, 7, 6, 5, 4, 3, 2, 0, 1); + break; + case 15: /* 0, 1, 2, 3, 4, 5, 6, 7 - 7 */ /* 7, 7, 7, 7, 7, 7, 7, 7 - 0 */ + RSP_VADD(0, 1, 2, 3, 4, 5, 6, 7, 0, 0, 0, 0, 0, 0, 0, 0, 7, 6, 5, 4, 3, 2, 1, 0); + break; + } rsp->flag[0] = 0; WRITEBACK_RESULT(); } @@ -4695,54 +4695,54 @@ INLINE void cfunc_rsp_vlt(void *param) switch(EL) { - case 0: /* 0, 1, 2, 3, 4, 5, 6, 7 - none */ /* 0, 1, 2, 3, 4, 5, 6, 7 - none */ - RSP_VLT(0, 1, 2, 3, 4, 5, 6, 7, 7, 6, 5, 4, 3, 2, 1, 0, 7, 6, 5, 4, 3, 2, 1, 0); - break; - case 1: /* 0, 1, 2, 3, 4, 5, 6, 7 - ??? */ /* 0, 1, 2, 3, 4, 5, 6, 7 - ??? */ - RSP_VLT(0, 1, 2, 3, 4, 5, 6, 7, 7, 6, 5, 4, 3, 2, 1, 0, 7, 6, 5, 4, 3, 2, 1, 0); - break; - case 2: /* 1, 3, 5, 7, 0, 2, 4, 6 - 0q */ /* 0, 0, 2, 2, 4, 4, 6, 6 - 0q */ - RSP_VLT(1, 3, 5, 7, 0, 2, 4, 6, 7, 5, 3, 1, 7, 5, 3, 1, 6, 4, 2, 0, 7, 5, 3, 1); - break; - case 3: /* 0, 2, 4, 6, 1, 3, 5, 7 - 1q */ /* 1, 1, 3, 3, 5, 5, 7, 7 - 1q */ - RSP_VLT(0, 2, 4, 6, 1, 3, 5, 7, 6, 4, 2, 0, 6, 4, 2, 0, 7, 5, 3, 1, 6, 4, 2, 0); - break; - case 4: /* 1, 2, 3, 5, 6, 7, 0, 4 - 0h */ /* 0, 0, 0, 0, 4, 4, 4, 4 - 0h */ - RSP_VLT(1, 2, 3, 5, 6, 7, 0, 4, 7, 7, 7, 3, 3, 3, 7, 3, 6, 5, 4, 2, 1, 0, 7, 3); - break; - case 5: /* 0, 2, 3, 4, 6, 7, 1, 5 - 1h */ /* 1, 1, 1, 1, 5, 5, 5, 5 - 1h */ - RSP_VLT(0, 2, 3, 4, 6, 7, 1, 5, 6, 6, 6, 2, 2, 2, 6, 2, 7, 5, 4, 3, 1, 0, 6, 2); - break; - case 6: /* 0, 1, 3, 4, 5, 7, 2, 6 - 2h */ /* 2, 2, 2, 2, 6, 6, 6, 6 - 2h */ - RSP_VLT(0, 1, 3, 4, 5, 7, 2, 6, 5, 5, 5, 1, 1, 1, 5, 1, 7, 6, 4, 3, 2, 0, 5, 1); - break; - case 7: /* 0, 1, 2, 4, 5, 6, 3, 7 - 3h */ /* 3, 3, 3, 3, 7, 7, 7, 7 - 3h */ - RSP_VLT(0, 1, 2, 4, 5, 6, 3, 7, 4, 4, 4, 0, 0, 0, 4, 0, 7, 6, 5, 3, 2, 1, 4, 0); - break; - case 8: /* 1, 2, 3, 4, 5, 6, 7, 0 - 0 */ /* 0, 0, 0, 0, 0, 0, 0, 0 - 0 */ - RSP_VLT(1, 2, 3, 4, 5, 6, 7, 0, 7, 7, 7, 7, 7, 7, 7, 7, 6, 5, 4, 3, 2, 1, 0, 7); - break; - case 9: /* 0, 2, 3, 4, 5, 6, 7, 1 - 1 */ /* 1, 1, 1, 1, 1, 1, 1, 1 - 0 */ - RSP_VLT(0, 2, 3, 4, 5, 6, 7, 1, 6, 6, 6, 6, 6, 6, 6, 6, 7, 5, 4, 3, 2, 1, 0, 6); - break; - case 10: /* 0, 1, 3, 4, 5, 6, 7, 2 - 2 */ /* 2, 2, 2, 2, 2, 2, 2, 2 - 0 */ - RSP_VLT(0, 1, 3, 4, 5, 6, 7, 2, 5, 5, 5, 5, 5, 5, 5, 5, 7, 6, 4, 3, 2, 1, 0, 5); - break; - case 11: /* 0, 1, 2, 4, 5, 6, 7, 3 - 3 */ /* 3, 3, 3, 3, 3, 3, 3, 3 - 0 */ - RSP_VLT(0, 1, 2, 4, 5, 6, 7, 3, 4, 4, 4, 4, 4, 4, 4, 4, 7, 6, 5, 3, 2, 1, 0, 4); - break; - case 12: /* 0, 1, 2, 3, 5, 6, 7, 4 - 4 */ /* 4, 4, 4, 4, 4, 4, 4, 4 - 0 */ - RSP_VLT(0, 1, 2, 3, 5, 6, 7, 4, 3, 3, 3, 3, 3, 3, 3, 3, 7, 6, 5, 4, 2, 1, 0, 3); - break; - case 13: /* 0, 1, 2, 3, 4, 6, 7, 5 - 5 */ /* 5, 5, 5, 5, 5, 5, 5, 5 - 0 */ - RSP_VLT(0, 1, 2, 3, 4, 6, 7, 5, 2, 2, 2, 2, 2, 2, 2, 2, 7, 6, 5, 4, 3, 1, 0, 2); - break; - case 14: /* 0, 1, 2, 3, 4, 5, 7, 6 - 6 */ /* 6, 6, 6, 6, 6, 6, 6, 6 - 0 */ - RSP_VLT(0, 1, 2, 3, 4, 5, 7, 6, 1, 1, 1, 1, 1, 1, 1, 1, 7, 6, 5, 4, 3, 2, 0, 1); - break; - case 15: /* 0, 1, 2, 3, 4, 5, 6, 7 - 7 */ /* 7, 7, 7, 7, 7, 7, 7, 7 - 0 */ - RSP_VLT(0, 1, 2, 3, 4, 5, 6, 7, 0, 0, 0, 0, 0, 0, 0, 0, 7, 6, 5, 4, 3, 2, 1, 0); - break; + case 0: /* 0, 1, 2, 3, 4, 5, 6, 7 - none */ /* 0, 1, 2, 3, 4, 5, 6, 7 - none */ + RSP_VLT(0, 1, 2, 3, 4, 5, 6, 7, 7, 6, 5, 4, 3, 2, 1, 0, 7, 6, 5, 4, 3, 2, 1, 0); + break; + case 1: /* 0, 1, 2, 3, 4, 5, 6, 7 - ??? */ /* 0, 1, 2, 3, 4, 5, 6, 7 - ??? */ + RSP_VLT(0, 1, 2, 3, 4, 5, 6, 7, 7, 6, 5, 4, 3, 2, 1, 0, 7, 6, 5, 4, 3, 2, 1, 0); + break; + case 2: /* 1, 3, 5, 7, 0, 2, 4, 6 - 0q */ /* 0, 0, 2, 2, 4, 4, 6, 6 - 0q */ + RSP_VLT(1, 3, 5, 7, 0, 2, 4, 6, 7, 5, 3, 1, 7, 5, 3, 1, 6, 4, 2, 0, 7, 5, 3, 1); + break; + case 3: /* 0, 2, 4, 6, 1, 3, 5, 7 - 1q */ /* 1, 1, 3, 3, 5, 5, 7, 7 - 1q */ + RSP_VLT(0, 2, 4, 6, 1, 3, 5, 7, 6, 4, 2, 0, 6, 4, 2, 0, 7, 5, 3, 1, 6, 4, 2, 0); + break; + case 4: /* 1, 2, 3, 5, 6, 7, 0, 4 - 0h */ /* 0, 0, 0, 0, 4, 4, 4, 4 - 0h */ + RSP_VLT(1, 2, 3, 5, 6, 7, 0, 4, 7, 7, 7, 3, 3, 3, 7, 3, 6, 5, 4, 2, 1, 0, 7, 3); + break; + case 5: /* 0, 2, 3, 4, 6, 7, 1, 5 - 1h */ /* 1, 1, 1, 1, 5, 5, 5, 5 - 1h */ + RSP_VLT(0, 2, 3, 4, 6, 7, 1, 5, 6, 6, 6, 2, 2, 2, 6, 2, 7, 5, 4, 3, 1, 0, 6, 2); + break; + case 6: /* 0, 1, 3, 4, 5, 7, 2, 6 - 2h */ /* 2, 2, 2, 2, 6, 6, 6, 6 - 2h */ + RSP_VLT(0, 1, 3, 4, 5, 7, 2, 6, 5, 5, 5, 1, 1, 1, 5, 1, 7, 6, 4, 3, 2, 0, 5, 1); + break; + case 7: /* 0, 1, 2, 4, 5, 6, 3, 7 - 3h */ /* 3, 3, 3, 3, 7, 7, 7, 7 - 3h */ + RSP_VLT(0, 1, 2, 4, 5, 6, 3, 7, 4, 4, 4, 0, 0, 0, 4, 0, 7, 6, 5, 3, 2, 1, 4, 0); + break; + case 8: /* 1, 2, 3, 4, 5, 6, 7, 0 - 0 */ /* 0, 0, 0, 0, 0, 0, 0, 0 - 0 */ + RSP_VLT(1, 2, 3, 4, 5, 6, 7, 0, 7, 7, 7, 7, 7, 7, 7, 7, 6, 5, 4, 3, 2, 1, 0, 7); + break; + case 9: /* 0, 2, 3, 4, 5, 6, 7, 1 - 1 */ /* 1, 1, 1, 1, 1, 1, 1, 1 - 0 */ + RSP_VLT(0, 2, 3, 4, 5, 6, 7, 1, 6, 6, 6, 6, 6, 6, 6, 6, 7, 5, 4, 3, 2, 1, 0, 6); + break; + case 10: /* 0, 1, 3, 4, 5, 6, 7, 2 - 2 */ /* 2, 2, 2, 2, 2, 2, 2, 2 - 0 */ + RSP_VLT(0, 1, 3, 4, 5, 6, 7, 2, 5, 5, 5, 5, 5, 5, 5, 5, 7, 6, 4, 3, 2, 1, 0, 5); + break; + case 11: /* 0, 1, 2, 4, 5, 6, 7, 3 - 3 */ /* 3, 3, 3, 3, 3, 3, 3, 3 - 0 */ + RSP_VLT(0, 1, 2, 4, 5, 6, 7, 3, 4, 4, 4, 4, 4, 4, 4, 4, 7, 6, 5, 3, 2, 1, 0, 4); + break; + case 12: /* 0, 1, 2, 3, 5, 6, 7, 4 - 4 */ /* 4, 4, 4, 4, 4, 4, 4, 4 - 0 */ + RSP_VLT(0, 1, 2, 3, 5, 6, 7, 4, 3, 3, 3, 3, 3, 3, 3, 3, 7, 6, 5, 4, 2, 1, 0, 3); + break; + case 13: /* 0, 1, 2, 3, 4, 6, 7, 5 - 5 */ /* 5, 5, 5, 5, 5, 5, 5, 5 - 0 */ + RSP_VLT(0, 1, 2, 3, 4, 6, 7, 5, 2, 2, 2, 2, 2, 2, 2, 2, 7, 6, 5, 4, 3, 1, 0, 2); + break; + case 14: /* 0, 1, 2, 3, 4, 5, 7, 6 - 6 */ /* 6, 6, 6, 6, 6, 6, 6, 6 - 0 */ + RSP_VLT(0, 1, 2, 3, 4, 5, 7, 6, 1, 1, 1, 1, 1, 1, 1, 1, 7, 6, 5, 4, 3, 2, 0, 1); + break; + case 15: /* 0, 1, 2, 3, 4, 5, 6, 7 - 7 */ /* 7, 7, 7, 7, 7, 7, 7, 7 - 0 */ + RSP_VLT(0, 1, 2, 3, 4, 5, 6, 7, 0, 0, 0, 0, 0, 0, 0, 0, 7, 6, 5, 4, 3, 2, 1, 0); + break; } } @@ -5025,54 +5025,54 @@ INLINE void cfunc_rsp_vge(void *param) #if 1 switch(EL) { - case 0: /* 0, 1, 2, 3, 4, 5, 6, 7 - none */ /* 0, 1, 2, 3, 4, 5, 6, 7 - none */ - RSP_VGE(0, 1, 2, 3, 4, 5, 6, 7, 7, 6, 5, 4, 3, 2, 1, 0, 7, 6, 5, 4, 3, 2, 1, 0); - break; - case 1: /* 0, 1, 2, 3, 4, 5, 6, 7 - ??? */ /* 0, 1, 2, 3, 4, 5, 6, 7 - ??? */ - RSP_VGE(0, 1, 2, 3, 4, 5, 6, 7, 7, 6, 5, 4, 3, 2, 1, 0, 7, 6, 5, 4, 3, 2, 1, 0); - break; - case 2: /* 1, 3, 5, 7, 0, 2, 4, 6 - 0q */ /* 0, 0, 2, 2, 4, 4, 6, 6 - 0q */ - RSP_VGE(1, 3, 5, 7, 0, 2, 4, 6, 7, 5, 3, 1, 7, 5, 3, 1, 6, 4, 2, 0, 7, 5, 3, 1); - break; - case 3: /* 0, 2, 4, 6, 1, 3, 5, 7 - 1q */ /* 1, 1, 3, 3, 5, 5, 7, 7 - 1q */ - RSP_VGE(0, 2, 4, 6, 1, 3, 5, 7, 6, 4, 2, 0, 6, 4, 2, 0, 7, 5, 3, 1, 6, 4, 2, 0); - break; - case 4: /* 1, 2, 3, 5, 6, 7, 0, 4 - 0h */ /* 0, 0, 0, 0, 4, 4, 4, 4 - 0h */ - RSP_VGE(1, 2, 3, 5, 6, 7, 0, 4, 7, 7, 7, 3, 3, 3, 7, 3, 6, 5, 4, 2, 1, 0, 7, 3); - break; - case 5: /* 0, 2, 3, 4, 6, 7, 1, 5 - 1h */ /* 1, 1, 1, 1, 5, 5, 5, 5 - 1h */ - RSP_VGE(0, 2, 3, 4, 6, 7, 1, 5, 6, 6, 6, 2, 2, 2, 6, 2, 7, 5, 4, 3, 1, 0, 6, 2); - break; - case 6: /* 0, 1, 3, 4, 5, 7, 2, 6 - 2h */ /* 2, 2, 2, 2, 6, 6, 6, 6 - 2h */ - RSP_VGE(0, 1, 3, 4, 5, 7, 2, 6, 5, 5, 5, 1, 1, 1, 5, 1, 7, 6, 4, 3, 2, 0, 5, 1); - break; - case 7: /* 0, 1, 2, 4, 5, 6, 3, 7 - 3h */ /* 3, 3, 3, 3, 7, 7, 7, 7 - 3h */ - RSP_VGE(0, 1, 2, 4, 5, 6, 3, 7, 4, 4, 4, 0, 0, 0, 4, 0, 7, 6, 5, 3, 2, 1, 4, 0); - break; - case 8: /* 1, 2, 3, 4, 5, 6, 7, 0 - 0 */ /* 0, 0, 0, 0, 0, 0, 0, 0 - 0 */ - RSP_VGE(1, 2, 3, 4, 5, 6, 7, 0, 7, 7, 7, 7, 7, 7, 7, 7, 6, 5, 4, 3, 2, 1, 0, 7); - break; - case 9: /* 0, 2, 3, 4, 5, 6, 7, 1 - 1 */ /* 1, 1, 1, 1, 1, 1, 1, 1 - 0 */ - RSP_VGE(0, 2, 3, 4, 5, 6, 7, 1, 6, 6, 6, 6, 6, 6, 6, 6, 7, 5, 4, 3, 2, 1, 0, 6); - break; - case 10: /* 0, 1, 3, 4, 5, 6, 7, 2 - 2 */ /* 2, 2, 2, 2, 2, 2, 2, 2 - 0 */ - RSP_VGE(0, 1, 3, 4, 5, 6, 7, 2, 5, 5, 5, 5, 5, 5, 5, 5, 7, 6, 4, 3, 2, 1, 0, 5); - break; - case 11: /* 0, 1, 2, 4, 5, 6, 7, 3 - 3 */ /* 3, 3, 3, 3, 3, 3, 3, 3 - 0 */ - RSP_VGE(0, 1, 2, 4, 5, 6, 7, 3, 4, 4, 4, 4, 4, 4, 4, 4, 7, 6, 5, 3, 2, 1, 0, 4); - break; - case 12: /* 0, 1, 2, 3, 5, 6, 7, 4 - 4 */ /* 4, 4, 4, 4, 4, 4, 4, 4 - 0 */ - RSP_VGE(0, 1, 2, 3, 5, 6, 7, 4, 3, 3, 3, 3, 3, 3, 3, 3, 7, 6, 5, 4, 2, 1, 0, 3); - break; - case 13: /* 0, 1, 2, 3, 4, 6, 7, 5 - 5 */ /* 5, 5, 5, 5, 5, 5, 5, 5 - 0 */ - RSP_VGE(0, 1, 2, 3, 4, 6, 7, 5, 2, 2, 2, 2, 2, 2, 2, 2, 7, 6, 5, 4, 3, 1, 0, 2); - break; - case 14: /* 0, 1, 2, 3, 4, 5, 7, 6 - 6 */ /* 6, 6, 6, 6, 6, 6, 6, 6 - 0 */ - RSP_VGE(0, 1, 2, 3, 4, 5, 7, 6, 1, 1, 1, 1, 1, 1, 1, 1, 7, 6, 5, 4, 3, 2, 0, 1); - break; - case 15: /* 0, 1, 2, 3, 4, 5, 6, 7 - 7 */ /* 7, 7, 7, 7, 7, 7, 7, 7 - 0 */ - RSP_VGE(0, 1, 2, 3, 4, 5, 6, 7, 0, 0, 0, 0, 0, 0, 0, 0, 7, 6, 5, 4, 3, 2, 1, 0); - break; + case 0: /* 0, 1, 2, 3, 4, 5, 6, 7 - none */ /* 0, 1, 2, 3, 4, 5, 6, 7 - none */ + RSP_VGE(0, 1, 2, 3, 4, 5, 6, 7, 7, 6, 5, 4, 3, 2, 1, 0, 7, 6, 5, 4, 3, 2, 1, 0); + break; + case 1: /* 0, 1, 2, 3, 4, 5, 6, 7 - ??? */ /* 0, 1, 2, 3, 4, 5, 6, 7 - ??? */ + RSP_VGE(0, 1, 2, 3, 4, 5, 6, 7, 7, 6, 5, 4, 3, 2, 1, 0, 7, 6, 5, 4, 3, 2, 1, 0); + break; + case 2: /* 1, 3, 5, 7, 0, 2, 4, 6 - 0q */ /* 0, 0, 2, 2, 4, 4, 6, 6 - 0q */ + RSP_VGE(1, 3, 5, 7, 0, 2, 4, 6, 7, 5, 3, 1, 7, 5, 3, 1, 6, 4, 2, 0, 7, 5, 3, 1); + break; + case 3: /* 0, 2, 4, 6, 1, 3, 5, 7 - 1q */ /* 1, 1, 3, 3, 5, 5, 7, 7 - 1q */ + RSP_VGE(0, 2, 4, 6, 1, 3, 5, 7, 6, 4, 2, 0, 6, 4, 2, 0, 7, 5, 3, 1, 6, 4, 2, 0); + break; + case 4: /* 1, 2, 3, 5, 6, 7, 0, 4 - 0h */ /* 0, 0, 0, 0, 4, 4, 4, 4 - 0h */ + RSP_VGE(1, 2, 3, 5, 6, 7, 0, 4, 7, 7, 7, 3, 3, 3, 7, 3, 6, 5, 4, 2, 1, 0, 7, 3); + break; + case 5: /* 0, 2, 3, 4, 6, 7, 1, 5 - 1h */ /* 1, 1, 1, 1, 5, 5, 5, 5 - 1h */ + RSP_VGE(0, 2, 3, 4, 6, 7, 1, 5, 6, 6, 6, 2, 2, 2, 6, 2, 7, 5, 4, 3, 1, 0, 6, 2); + break; + case 6: /* 0, 1, 3, 4, 5, 7, 2, 6 - 2h */ /* 2, 2, 2, 2, 6, 6, 6, 6 - 2h */ + RSP_VGE(0, 1, 3, 4, 5, 7, 2, 6, 5, 5, 5, 1, 1, 1, 5, 1, 7, 6, 4, 3, 2, 0, 5, 1); + break; + case 7: /* 0, 1, 2, 4, 5, 6, 3, 7 - 3h */ /* 3, 3, 3, 3, 7, 7, 7, 7 - 3h */ + RSP_VGE(0, 1, 2, 4, 5, 6, 3, 7, 4, 4, 4, 0, 0, 0, 4, 0, 7, 6, 5, 3, 2, 1, 4, 0); + break; + case 8: /* 1, 2, 3, 4, 5, 6, 7, 0 - 0 */ /* 0, 0, 0, 0, 0, 0, 0, 0 - 0 */ + RSP_VGE(1, 2, 3, 4, 5, 6, 7, 0, 7, 7, 7, 7, 7, 7, 7, 7, 6, 5, 4, 3, 2, 1, 0, 7); + break; + case 9: /* 0, 2, 3, 4, 5, 6, 7, 1 - 1 */ /* 1, 1, 1, 1, 1, 1, 1, 1 - 0 */ + RSP_VGE(0, 2, 3, 4, 5, 6, 7, 1, 6, 6, 6, 6, 6, 6, 6, 6, 7, 5, 4, 3, 2, 1, 0, 6); + break; + case 10: /* 0, 1, 3, 4, 5, 6, 7, 2 - 2 */ /* 2, 2, 2, 2, 2, 2, 2, 2 - 0 */ + RSP_VGE(0, 1, 3, 4, 5, 6, 7, 2, 5, 5, 5, 5, 5, 5, 5, 5, 7, 6, 4, 3, 2, 1, 0, 5); + break; + case 11: /* 0, 1, 2, 4, 5, 6, 7, 3 - 3 */ /* 3, 3, 3, 3, 3, 3, 3, 3 - 0 */ + RSP_VGE(0, 1, 2, 4, 5, 6, 7, 3, 4, 4, 4, 4, 4, 4, 4, 4, 7, 6, 5, 3, 2, 1, 0, 4); + break; + case 12: /* 0, 1, 2, 3, 5, 6, 7, 4 - 4 */ /* 4, 4, 4, 4, 4, 4, 4, 4 - 0 */ + RSP_VGE(0, 1, 2, 3, 5, 6, 7, 4, 3, 3, 3, 3, 3, 3, 3, 3, 7, 6, 5, 4, 2, 1, 0, 3); + break; + case 13: /* 0, 1, 2, 3, 4, 6, 7, 5 - 5 */ /* 5, 5, 5, 5, 5, 5, 5, 5 - 0 */ + RSP_VGE(0, 1, 2, 3, 4, 6, 7, 5, 2, 2, 2, 2, 2, 2, 2, 2, 7, 6, 5, 4, 3, 1, 0, 2); + break; + case 14: /* 0, 1, 2, 3, 4, 5, 7, 6 - 6 */ /* 6, 6, 6, 6, 6, 6, 6, 6 - 0 */ + RSP_VGE(0, 1, 2, 3, 4, 5, 7, 6, 1, 1, 1, 1, 1, 1, 1, 1, 7, 6, 5, 4, 3, 2, 0, 1); + break; + case 15: /* 0, 1, 2, 3, 4, 5, 6, 7 - 7 */ /* 7, 7, 7, 7, 7, 7, 7, 7 - 0 */ + RSP_VGE(0, 1, 2, 3, 4, 5, 6, 7, 0, 0, 0, 0, 0, 0, 0, 0, 7, 6, 5, 4, 3, 2, 1, 0); + break; } #else rsp->flag[1] = 0; @@ -5441,58 +5441,58 @@ INLINE void cfunc_rsp_vmrg(void *param) // // Merges two vectors according to compare flags - switch(EL) - { - case 0: /* 0, 1, 2, 3, 4, 5, 6, 7 - none */ /* 0, 1, 2, 3, 4, 5, 6, 7 - none */ - RSP_VMRG(0, 1, 2, 3, 4, 5, 6, 7, 0, 1, 2, 3, 4, 5, 6, 7); - break; - case 1: /* 0, 1, 2, 3, 4, 5, 6, 7 - ??? */ /* 0, 1, 2, 3, 4, 5, 6, 7 - ??? */ - RSP_VMRG(0, 1, 2, 3, 4, 5, 6, 7, 0, 1, 2, 3, 4, 5, 6, 7); - break; - case 2: /* 1, 3, 5, 7, 0, 2, 4, 6 - 0q */ /* 0, 0, 2, 2, 4, 4, 6, 6 - 0q */ - RSP_VMRG(1, 3, 5, 7, 0, 2, 4, 6, 0, 2, 4, 6, 0, 2, 4, 6); - break; - case 3: /* 0, 2, 4, 6, 1, 3, 5, 7 - 1q */ /* 1, 1, 3, 3, 5, 5, 7, 7 - 1q */ - RSP_VMRG(0, 2, 4, 6, 1, 3, 5, 7, 1, 3, 5, 7, 1, 3, 5, 7); - break; - case 4: /* 1, 2, 3, 5, 6, 7, 0, 4 - 0h */ /* 0, 0, 0, 0, 4, 4, 4, 4 - 0h */ - RSP_VMRG(1, 2, 3, 5, 6, 7, 0, 4, 0, 0, 0, 4, 4, 4, 0, 4); - break; - case 5: /* 0, 2, 3, 4, 6, 7, 1, 5 - 1h */ /* 1, 1, 1, 1, 5, 5, 5, 5 - 1h */ - RSP_VMRG(0, 2, 3, 4, 6, 7, 1, 5, 1, 1, 1, 5, 5, 5, 1, 5); - break; - case 6: /* 0, 1, 3, 4, 5, 7, 2, 6 - 2h */ /* 2, 2, 2, 2, 6, 6, 6, 6 - 2h */ - RSP_VMRG(0, 1, 3, 4, 5, 7, 2, 6, 2, 2, 2, 6, 6, 6, 2, 6); - break; - case 7: /* 0, 1, 2, 4, 5, 6, 3, 7 - 3h */ /* 3, 3, 3, 3, 7, 7, 7, 7 - 3h */ - RSP_VMRG(0, 1, 2, 4, 5, 6, 3, 7, 3, 3, 3, 7, 7, 7, 3, 7); - break; - case 8: /* 1, 2, 3, 4, 5, 6, 7, 0 - 0 */ /* 0, 0, 0, 0, 0, 0, 0, 0 - 0 */ - RSP_VMRG(1, 2, 3, 4, 5, 6, 7, 0, 0, 0, 0, 0, 0, 0, 0, 0); - break; - case 9: /* 0, 2, 3, 4, 5, 6, 7, 1 - 1 */ /* 1, 1, 1, 1, 1, 1, 1, 1 - 0 */ - RSP_VMRG(0, 2, 3, 4, 5, 6, 7, 1, 1, 1, 1, 1, 1, 1, 1, 1); - break; - case 10:/* 0, 1, 3, 4, 5, 6, 7, 2 - 2 */ /* 2, 2, 2, 2, 2, 2, 2, 2 - 0 */ - RSP_VMRG(0, 1, 3, 4, 5, 6, 7, 2, 2, 2, 2, 2, 2, 2, 2, 2); - break; - case 11:/* 0, 1, 2, 4, 5, 6, 7, 3 - 3 */ /* 3, 3, 3, 3, 3, 3, 3, 3 - 0 */ - RSP_VMRG(0, 1, 2, 4, 5, 6, 7, 3, 3, 3, 3, 3, 3, 3, 3, 3); - break; - case 12:/* 0, 1, 2, 3, 5, 6, 7, 4 - 4 */ /* 4, 4, 4, 4, 4, 4, 4, 4 - 0 */ - RSP_VMRG(0, 1, 2, 3, 5, 6, 7, 4, 4, 4, 4, 4, 4, 4, 4, 4); - break; - case 13:/* 0, 1, 2, 3, 4, 6, 7, 5 - 5 */ /* 5, 5, 5, 5, 5, 5, 5, 5 - 0 */ - RSP_VMRG(0, 1, 2, 3, 4, 6, 7, 5, 5, 5, 5, 5, 5, 5, 5, 5); - break; - case 14:/* 0, 1, 2, 3, 4, 5, 7, 6 - 6 */ /* 6, 6, 6, 6, 6, 6, 6, 6 - 0 */ - RSP_VMRG(0, 1, 2, 3, 4, 5, 7, 6, 6, 6, 6, 6, 6, 6, 6, 6); - break; - case 15:/* 0, 1, 2, 3, 4, 5, 6, 7 - 7 */ /* 7, 7, 7, 7, 7, 7, 7, 7 - 0 */ - RSP_VMRG(0, 1, 2, 3, 4, 5, 6, 7, 7, 7, 7, 7, 7, 7, 7, 7); - break; - } - WRITEBACK_RESULT(); + switch(EL) + { + case 0: /* 0, 1, 2, 3, 4, 5, 6, 7 - none */ /* 0, 1, 2, 3, 4, 5, 6, 7 - none */ + RSP_VMRG(0, 1, 2, 3, 4, 5, 6, 7, 0, 1, 2, 3, 4, 5, 6, 7); + break; + case 1: /* 0, 1, 2, 3, 4, 5, 6, 7 - ??? */ /* 0, 1, 2, 3, 4, 5, 6, 7 - ??? */ + RSP_VMRG(0, 1, 2, 3, 4, 5, 6, 7, 0, 1, 2, 3, 4, 5, 6, 7); + break; + case 2: /* 1, 3, 5, 7, 0, 2, 4, 6 - 0q */ /* 0, 0, 2, 2, 4, 4, 6, 6 - 0q */ + RSP_VMRG(1, 3, 5, 7, 0, 2, 4, 6, 0, 2, 4, 6, 0, 2, 4, 6); + break; + case 3: /* 0, 2, 4, 6, 1, 3, 5, 7 - 1q */ /* 1, 1, 3, 3, 5, 5, 7, 7 - 1q */ + RSP_VMRG(0, 2, 4, 6, 1, 3, 5, 7, 1, 3, 5, 7, 1, 3, 5, 7); + break; + case 4: /* 1, 2, 3, 5, 6, 7, 0, 4 - 0h */ /* 0, 0, 0, 0, 4, 4, 4, 4 - 0h */ + RSP_VMRG(1, 2, 3, 5, 6, 7, 0, 4, 0, 0, 0, 4, 4, 4, 0, 4); + break; + case 5: /* 0, 2, 3, 4, 6, 7, 1, 5 - 1h */ /* 1, 1, 1, 1, 5, 5, 5, 5 - 1h */ + RSP_VMRG(0, 2, 3, 4, 6, 7, 1, 5, 1, 1, 1, 5, 5, 5, 1, 5); + break; + case 6: /* 0, 1, 3, 4, 5, 7, 2, 6 - 2h */ /* 2, 2, 2, 2, 6, 6, 6, 6 - 2h */ + RSP_VMRG(0, 1, 3, 4, 5, 7, 2, 6, 2, 2, 2, 6, 6, 6, 2, 6); + break; + case 7: /* 0, 1, 2, 4, 5, 6, 3, 7 - 3h */ /* 3, 3, 3, 3, 7, 7, 7, 7 - 3h */ + RSP_VMRG(0, 1, 2, 4, 5, 6, 3, 7, 3, 3, 3, 7, 7, 7, 3, 7); + break; + case 8: /* 1, 2, 3, 4, 5, 6, 7, 0 - 0 */ /* 0, 0, 0, 0, 0, 0, 0, 0 - 0 */ + RSP_VMRG(1, 2, 3, 4, 5, 6, 7, 0, 0, 0, 0, 0, 0, 0, 0, 0); + break; + case 9: /* 0, 2, 3, 4, 5, 6, 7, 1 - 1 */ /* 1, 1, 1, 1, 1, 1, 1, 1 - 0 */ + RSP_VMRG(0, 2, 3, 4, 5, 6, 7, 1, 1, 1, 1, 1, 1, 1, 1, 1); + break; + case 10:/* 0, 1, 3, 4, 5, 6, 7, 2 - 2 */ /* 2, 2, 2, 2, 2, 2, 2, 2 - 0 */ + RSP_VMRG(0, 1, 3, 4, 5, 6, 7, 2, 2, 2, 2, 2, 2, 2, 2, 2); + break; + case 11:/* 0, 1, 2, 4, 5, 6, 7, 3 - 3 */ /* 3, 3, 3, 3, 3, 3, 3, 3 - 0 */ + RSP_VMRG(0, 1, 2, 4, 5, 6, 7, 3, 3, 3, 3, 3, 3, 3, 3, 3); + break; + case 12:/* 0, 1, 2, 3, 5, 6, 7, 4 - 4 */ /* 4, 4, 4, 4, 4, 4, 4, 4 - 0 */ + RSP_VMRG(0, 1, 2, 3, 5, 6, 7, 4, 4, 4, 4, 4, 4, 4, 4, 4); + break; + case 13:/* 0, 1, 2, 3, 4, 6, 7, 5 - 5 */ /* 5, 5, 5, 5, 5, 5, 5, 5 - 0 */ + RSP_VMRG(0, 1, 2, 3, 4, 6, 7, 5, 5, 5, 5, 5, 5, 5, 5, 5); + break; + case 14:/* 0, 1, 2, 3, 4, 5, 7, 6 - 6 */ /* 6, 6, 6, 6, 6, 6, 6, 6 - 0 */ + RSP_VMRG(0, 1, 2, 3, 4, 5, 7, 6, 6, 6, 6, 6, 6, 6, 6, 6); + break; + case 15:/* 0, 1, 2, 3, 4, 5, 6, 7 - 7 */ /* 7, 7, 7, 7, 7, 7, 7, 7 - 0 */ + RSP_VMRG(0, 1, 2, 3, 4, 5, 6, 7, 7, 7, 7, 7, 7, 7, 7, 7); + break; + } + WRITEBACK_RESULT(); } #if (DRC_VAND) @@ -5567,59 +5567,59 @@ static int generate_vand(rsp_state *rsp, drcuml_block *block, compiler_state *co // // Bitwise AND of two vector registers - switch(EL) - { - case 0: /* 0, 1, 2, 3, 4, 5, 6, 7 - none */ /* 0, 1, 2, 3, 4, 5, 6, 7 - none */ - RSP_VAND_DRC(0, 1, 2, 3, 4, 5, 6, 7, 7, 6, 5, 4, 3, 2, 1, 0, 7, 6, 5, 4, 3, 2, 1, 0); - return TRUE; - case 1: /* 0, 1, 2, 3, 4, 5, 6, 7 - ??? */ /* 0, 1, 2, 3, 4, 5, 6, 7 - ??? */ - RSP_VAND_DRC(0, 1, 2, 3, 4, 5, 6, 7, 7, 6, 5, 4, 3, 2, 1, 0, 7, 6, 5, 4, 3, 2, 1, 0); - return TRUE; - case 2: /* 1, 3, 5, 7, 0, 2, 4, 6 - 0q */ /* 0, 0, 2, 2, 4, 4, 6, 6 - 0q */ - RSP_VAND_DRC(1, 3, 5, 7, 0, 2, 4, 6, 7, 5, 3, 1, 7, 5, 3, 1, 6, 4, 2, 0, 7, 5, 3, 1); - return TRUE; - case 3: /* 0, 2, 4, 6, 1, 3, 5, 7 - 1q */ /* 1, 1, 3, 3, 5, 5, 7, 7 - 1q */ - RSP_VAND_DRC(0, 2, 4, 6, 1, 3, 5, 7, 6, 4, 2, 0, 6, 4, 2, 0, 7, 5, 3, 1, 6, 4, 2, 0); - return TRUE; - case 4: /* 1, 2, 3, 5, 6, 7, 0, 4 - 0h */ /* 0, 0, 0, 0, 4, 4, 4, 4 - 0h */ - RSP_VAND_DRC(1, 2, 3, 5, 6, 7, 0, 4, 7, 7, 7, 3, 3, 3, 7, 3, 6, 5, 4, 2, 1, 0, 7, 3); - return TRUE; - case 5: /* 0, 2, 3, 4, 6, 7, 1, 5 - 1h */ /* 1, 1, 1, 1, 5, 5, 5, 5 - 1h */ - RSP_VAND_DRC(0, 2, 3, 4, 6, 7, 1, 5, 6, 6, 6, 2, 2, 2, 6, 2, 7, 5, 4, 3, 1, 0, 6, 2); - return TRUE; - case 6: /* 0, 1, 3, 4, 5, 7, 2, 6 - 2h */ /* 2, 2, 2, 2, 6, 6, 6, 6 - 2h */ - RSP_VAND_DRC(0, 1, 3, 4, 5, 7, 2, 6, 5, 5, 5, 1, 1, 1, 5, 1, 7, 6, 4, 3, 2, 0, 5, 1); - return TRUE; - case 7: /* 0, 1, 2, 4, 5, 6, 3, 7 - 3h */ /* 3, 3, 3, 3, 7, 7, 7, 7 - 3h */ - RSP_VAND_DRC(0, 1, 2, 4, 5, 6, 3, 7, 4, 4, 4, 0, 0, 0, 4, 0, 7, 6, 5, 3, 2, 1, 4, 0); - return TRUE; - case 8: /* 1, 2, 3, 4, 5, 6, 7, 0 - 0 */ /* 0, 0, 0, 0, 0, 0, 0, 0 - 0 */ - RSP_VAND_DRC(1, 2, 3, 4, 5, 6, 7, 0, 7, 7, 7, 7, 7, 7, 7, 7, 6, 5, 4, 3, 2, 1, 0, 7); - return TRUE; - case 9: /* 0, 2, 3, 4, 5, 6, 7, 1 - 1 */ /* 1, 1, 1, 1, 1, 1, 1, 1 - 0 */ - RSP_VAND_DRC(0, 2, 3, 4, 5, 6, 7, 1, 6, 6, 6, 6, 6, 6, 6, 6, 7, 5, 4, 3, 2, 1, 0, 6); - return TRUE; - case 10: /* 0, 1, 3, 4, 5, 6, 7, 2 - 2 */ /* 2, 2, 2, 2, 2, 2, 2, 2 - 0 */ - RSP_VAND_DRC(0, 1, 3, 4, 5, 6, 7, 2, 5, 5, 5, 5, 5, 5, 5, 5, 7, 6, 4, 3, 2, 1, 0, 5); - return TRUE; - case 11: /* 0, 1, 2, 4, 5, 6, 7, 3 - 3 */ /* 3, 3, 3, 3, 3, 3, 3, 3 - 0 */ - RSP_VAND_DRC(0, 1, 2, 4, 5, 6, 7, 3, 4, 4, 4, 4, 4, 4, 4, 4, 7, 6, 5, 3, 2, 1, 0, 4); - return TRUE; - case 12: /* 0, 1, 2, 3, 5, 6, 7, 4 - 4 */ /* 4, 4, 4, 4, 4, 4, 4, 4 - 0 */ - RSP_VAND_DRC(0, 1, 2, 3, 5, 6, 7, 4, 3, 3, 3, 3, 3, 3, 3, 3, 7, 6, 5, 4, 2, 1, 0, 3); - return TRUE; - case 13: /* 0, 1, 2, 3, 4, 6, 7, 5 - 5 */ /* 5, 5, 5, 5, 5, 5, 5, 5 - 0 */ - RSP_VAND_DRC(0, 1, 2, 3, 4, 6, 7, 5, 2, 2, 2, 2, 2, 2, 2, 2, 7, 6, 5, 4, 3, 1, 0, 2); - return TRUE; - case 14: /* 0, 1, 2, 3, 4, 5, 7, 6 - 6 */ /* 6, 6, 6, 6, 6, 6, 6, 6 - 0 */ - RSP_VAND_DRC(0, 1, 2, 3, 4, 5, 7, 6, 1, 1, 1, 1, 1, 1, 1, 1, 7, 6, 5, 4, 3, 2, 0, 1); - return TRUE; - case 15: /* 0, 1, 2, 3, 4, 5, 6, 7 - 7 */ /* 7, 7, 7, 7, 7, 7, 7, 7 - 0 */ - RSP_VAND_DRC(0, 1, 2, 3, 4, 5, 6, 7, 0, 0, 0, 0, 0, 0, 0, 0, 7, 6, 5, 4, 3, 2, 1, 0); - return TRUE; - } - - return TRUE; + switch(EL) + { + case 0: /* 0, 1, 2, 3, 4, 5, 6, 7 - none */ /* 0, 1, 2, 3, 4, 5, 6, 7 - none */ + RSP_VAND_DRC(0, 1, 2, 3, 4, 5, 6, 7, 7, 6, 5, 4, 3, 2, 1, 0, 7, 6, 5, 4, 3, 2, 1, 0); + return TRUE; + case 1: /* 0, 1, 2, 3, 4, 5, 6, 7 - ??? */ /* 0, 1, 2, 3, 4, 5, 6, 7 - ??? */ + RSP_VAND_DRC(0, 1, 2, 3, 4, 5, 6, 7, 7, 6, 5, 4, 3, 2, 1, 0, 7, 6, 5, 4, 3, 2, 1, 0); + return TRUE; + case 2: /* 1, 3, 5, 7, 0, 2, 4, 6 - 0q */ /* 0, 0, 2, 2, 4, 4, 6, 6 - 0q */ + RSP_VAND_DRC(1, 3, 5, 7, 0, 2, 4, 6, 7, 5, 3, 1, 7, 5, 3, 1, 6, 4, 2, 0, 7, 5, 3, 1); + return TRUE; + case 3: /* 0, 2, 4, 6, 1, 3, 5, 7 - 1q */ /* 1, 1, 3, 3, 5, 5, 7, 7 - 1q */ + RSP_VAND_DRC(0, 2, 4, 6, 1, 3, 5, 7, 6, 4, 2, 0, 6, 4, 2, 0, 7, 5, 3, 1, 6, 4, 2, 0); + return TRUE; + case 4: /* 1, 2, 3, 5, 6, 7, 0, 4 - 0h */ /* 0, 0, 0, 0, 4, 4, 4, 4 - 0h */ + RSP_VAND_DRC(1, 2, 3, 5, 6, 7, 0, 4, 7, 7, 7, 3, 3, 3, 7, 3, 6, 5, 4, 2, 1, 0, 7, 3); + return TRUE; + case 5: /* 0, 2, 3, 4, 6, 7, 1, 5 - 1h */ /* 1, 1, 1, 1, 5, 5, 5, 5 - 1h */ + RSP_VAND_DRC(0, 2, 3, 4, 6, 7, 1, 5, 6, 6, 6, 2, 2, 2, 6, 2, 7, 5, 4, 3, 1, 0, 6, 2); + return TRUE; + case 6: /* 0, 1, 3, 4, 5, 7, 2, 6 - 2h */ /* 2, 2, 2, 2, 6, 6, 6, 6 - 2h */ + RSP_VAND_DRC(0, 1, 3, 4, 5, 7, 2, 6, 5, 5, 5, 1, 1, 1, 5, 1, 7, 6, 4, 3, 2, 0, 5, 1); + return TRUE; + case 7: /* 0, 1, 2, 4, 5, 6, 3, 7 - 3h */ /* 3, 3, 3, 3, 7, 7, 7, 7 - 3h */ + RSP_VAND_DRC(0, 1, 2, 4, 5, 6, 3, 7, 4, 4, 4, 0, 0, 0, 4, 0, 7, 6, 5, 3, 2, 1, 4, 0); + return TRUE; + case 8: /* 1, 2, 3, 4, 5, 6, 7, 0 - 0 */ /* 0, 0, 0, 0, 0, 0, 0, 0 - 0 */ + RSP_VAND_DRC(1, 2, 3, 4, 5, 6, 7, 0, 7, 7, 7, 7, 7, 7, 7, 7, 6, 5, 4, 3, 2, 1, 0, 7); + return TRUE; + case 9: /* 0, 2, 3, 4, 5, 6, 7, 1 - 1 */ /* 1, 1, 1, 1, 1, 1, 1, 1 - 0 */ + RSP_VAND_DRC(0, 2, 3, 4, 5, 6, 7, 1, 6, 6, 6, 6, 6, 6, 6, 6, 7, 5, 4, 3, 2, 1, 0, 6); + return TRUE; + case 10: /* 0, 1, 3, 4, 5, 6, 7, 2 - 2 */ /* 2, 2, 2, 2, 2, 2, 2, 2 - 0 */ + RSP_VAND_DRC(0, 1, 3, 4, 5, 6, 7, 2, 5, 5, 5, 5, 5, 5, 5, 5, 7, 6, 4, 3, 2, 1, 0, 5); + return TRUE; + case 11: /* 0, 1, 2, 4, 5, 6, 7, 3 - 3 */ /* 3, 3, 3, 3, 3, 3, 3, 3 - 0 */ + RSP_VAND_DRC(0, 1, 2, 4, 5, 6, 7, 3, 4, 4, 4, 4, 4, 4, 4, 4, 7, 6, 5, 3, 2, 1, 0, 4); + return TRUE; + case 12: /* 0, 1, 2, 3, 5, 6, 7, 4 - 4 */ /* 4, 4, 4, 4, 4, 4, 4, 4 - 0 */ + RSP_VAND_DRC(0, 1, 2, 3, 5, 6, 7, 4, 3, 3, 3, 3, 3, 3, 3, 3, 7, 6, 5, 4, 2, 1, 0, 3); + return TRUE; + case 13: /* 0, 1, 2, 3, 4, 6, 7, 5 - 5 */ /* 5, 5, 5, 5, 5, 5, 5, 5 - 0 */ + RSP_VAND_DRC(0, 1, 2, 3, 4, 6, 7, 5, 2, 2, 2, 2, 2, 2, 2, 2, 7, 6, 5, 4, 3, 1, 0, 2); + return TRUE; + case 14: /* 0, 1, 2, 3, 4, 5, 7, 6 - 6 */ /* 6, 6, 6, 6, 6, 6, 6, 6 - 0 */ + RSP_VAND_DRC(0, 1, 2, 3, 4, 5, 7, 6, 1, 1, 1, 1, 1, 1, 1, 1, 7, 6, 5, 4, 3, 2, 0, 1); + return TRUE; + case 15: /* 0, 1, 2, 3, 4, 5, 6, 7 - 7 */ /* 7, 7, 7, 7, 7, 7, 7, 7 - 0 */ + RSP_VAND_DRC(0, 1, 2, 3, 4, 5, 6, 7, 0, 0, 0, 0, 0, 0, 0, 0, 7, 6, 5, 4, 3, 2, 1, 0); + return TRUE; + } + + return TRUE; } #else #define RSP_VAND(E10, E11, E12, E13, E14, E15, E16, E17, E20, E21, E22, E23, E24, E25, E26, E27) \ @@ -5652,58 +5652,58 @@ INLINE void cfunc_rsp_vand(void *param) // // Bitwise AND of two vector registers - switch(EL) - { - case 0: /* 0, 1, 2, 3, 4, 5, 6, 7 - none */ /* 0, 1, 2, 3, 4, 5, 6, 7 - none */ - RSP_VAND(0, 1, 2, 3, 4, 5, 6, 7, 0, 1, 2, 3, 4, 5, 6, 7); - break; - case 1: /* 0, 1, 2, 3, 4, 5, 6, 7 - ??? */ /* 0, 1, 2, 3, 4, 5, 6, 7 - ??? */ - RSP_VAND(0, 1, 2, 3, 4, 5, 6, 7, 0, 1, 2, 3, 4, 5, 6, 7); - break; - case 2: /* 1, 3, 5, 7, 0, 2, 4, 6 - 0q */ /* 0, 0, 2, 2, 4, 4, 6, 6 - 0q */ - RSP_VAND(1, 3, 5, 7, 0, 2, 4, 6, 0, 2, 4, 6, 0, 2, 4, 6); - break; - case 3: /* 0, 2, 4, 6, 1, 3, 5, 7 - 1q */ /* 1, 1, 3, 3, 5, 5, 7, 7 - 1q */ - RSP_VAND(0, 2, 4, 6, 1, 3, 5, 7, 1, 3, 5, 7, 1, 3, 5, 7); - break; - case 4: /* 1, 2, 3, 5, 6, 7, 0, 4 - 0h */ /* 0, 0, 0, 0, 4, 4, 4, 4 - 0h */ - RSP_VAND(1, 2, 3, 5, 6, 7, 0, 4, 0, 0, 0, 4, 4, 4, 0, 4); - break; - case 5: /* 0, 2, 3, 4, 6, 7, 1, 5 - 1h */ /* 1, 1, 1, 1, 5, 5, 5, 5 - 1h */ - RSP_VAND(0, 2, 3, 4, 6, 7, 1, 5, 1, 1, 1, 5, 5, 5, 1, 5); - break; - case 6: /* 0, 1, 3, 4, 5, 7, 2, 6 - 2h */ /* 2, 2, 2, 2, 6, 6, 6, 6 - 2h */ - RSP_VAND(0, 1, 3, 4, 5, 7, 2, 6, 2, 2, 2, 6, 6, 6, 2, 6); - break; - case 7: /* 0, 1, 2, 4, 5, 6, 3, 7 - 3h */ /* 3, 3, 3, 3, 7, 7, 7, 7 - 3h */ - RSP_VAND(0, 1, 2, 4, 5, 6, 3, 7, 3, 3, 3, 7, 7, 7, 3, 7); - break; - case 8: /* 1, 2, 3, 4, 5, 6, 7, 0 - 0 */ /* 0, 0, 0, 0, 0, 0, 0, 0 - 0 */ - RSP_VAND(1, 2, 3, 4, 5, 6, 7, 0, 0, 0, 0, 0, 0, 0, 0, 0); - break; - case 9: /* 0, 2, 3, 4, 5, 6, 7, 1 - 1 */ /* 1, 1, 1, 1, 1, 1, 1, 1 - 0 */ - RSP_VAND(0, 2, 3, 4, 5, 6, 7, 1, 1, 1, 1, 1, 1, 1, 1, 1); - break; - case 10:/* 0, 1, 3, 4, 5, 6, 7, 2 - 2 */ /* 2, 2, 2, 2, 2, 2, 2, 2 - 0 */ - RSP_VAND(0, 1, 3, 4, 5, 6, 7, 2, 2, 2, 2, 2, 2, 2, 2, 2); - break; - case 11:/* 0, 1, 2, 4, 5, 6, 7, 3 - 3 */ /* 3, 3, 3, 3, 3, 3, 3, 3 - 0 */ - RSP_VAND(0, 1, 2, 4, 5, 6, 7, 3, 3, 3, 3, 3, 3, 3, 3, 3); - break; - case 12:/* 0, 1, 2, 3, 5, 6, 7, 4 - 4 */ /* 4, 4, 4, 4, 4, 4, 4, 4 - 0 */ - RSP_VAND(0, 1, 2, 3, 5, 6, 7, 4, 4, 4, 4, 4, 4, 4, 4, 4); - break; - case 13:/* 0, 1, 2, 3, 4, 6, 7, 5 - 5 */ /* 5, 5, 5, 5, 5, 5, 5, 5 - 0 */ - RSP_VAND(0, 1, 2, 3, 4, 6, 7, 5, 5, 5, 5, 5, 5, 5, 5, 5); - break; - case 14:/* 0, 1, 2, 3, 4, 5, 7, 6 - 6 */ /* 6, 6, 6, 6, 6, 6, 6, 6 - 0 */ - RSP_VAND(0, 1, 2, 3, 4, 5, 7, 6, 6, 6, 6, 6, 6, 6, 6, 6); - break; - case 15:/* 0, 1, 2, 3, 4, 5, 6, 7 - 7 */ /* 7, 7, 7, 7, 7, 7, 7, 7 - 0 */ - RSP_VAND(0, 1, 2, 3, 4, 5, 6, 7, 7, 7, 7, 7, 7, 7, 7, 7); - break; - } - WRITEBACK_RESULT(); + switch(EL) + { + case 0: /* 0, 1, 2, 3, 4, 5, 6, 7 - none */ /* 0, 1, 2, 3, 4, 5, 6, 7 - none */ + RSP_VAND(0, 1, 2, 3, 4, 5, 6, 7, 0, 1, 2, 3, 4, 5, 6, 7); + break; + case 1: /* 0, 1, 2, 3, 4, 5, 6, 7 - ??? */ /* 0, 1, 2, 3, 4, 5, 6, 7 - ??? */ + RSP_VAND(0, 1, 2, 3, 4, 5, 6, 7, 0, 1, 2, 3, 4, 5, 6, 7); + break; + case 2: /* 1, 3, 5, 7, 0, 2, 4, 6 - 0q */ /* 0, 0, 2, 2, 4, 4, 6, 6 - 0q */ + RSP_VAND(1, 3, 5, 7, 0, 2, 4, 6, 0, 2, 4, 6, 0, 2, 4, 6); + break; + case 3: /* 0, 2, 4, 6, 1, 3, 5, 7 - 1q */ /* 1, 1, 3, 3, 5, 5, 7, 7 - 1q */ + RSP_VAND(0, 2, 4, 6, 1, 3, 5, 7, 1, 3, 5, 7, 1, 3, 5, 7); + break; + case 4: /* 1, 2, 3, 5, 6, 7, 0, 4 - 0h */ /* 0, 0, 0, 0, 4, 4, 4, 4 - 0h */ + RSP_VAND(1, 2, 3, 5, 6, 7, 0, 4, 0, 0, 0, 4, 4, 4, 0, 4); + break; + case 5: /* 0, 2, 3, 4, 6, 7, 1, 5 - 1h */ /* 1, 1, 1, 1, 5, 5, 5, 5 - 1h */ + RSP_VAND(0, 2, 3, 4, 6, 7, 1, 5, 1, 1, 1, 5, 5, 5, 1, 5); + break; + case 6: /* 0, 1, 3, 4, 5, 7, 2, 6 - 2h */ /* 2, 2, 2, 2, 6, 6, 6, 6 - 2h */ + RSP_VAND(0, 1, 3, 4, 5, 7, 2, 6, 2, 2, 2, 6, 6, 6, 2, 6); + break; + case 7: /* 0, 1, 2, 4, 5, 6, 3, 7 - 3h */ /* 3, 3, 3, 3, 7, 7, 7, 7 - 3h */ + RSP_VAND(0, 1, 2, 4, 5, 6, 3, 7, 3, 3, 3, 7, 7, 7, 3, 7); + break; + case 8: /* 1, 2, 3, 4, 5, 6, 7, 0 - 0 */ /* 0, 0, 0, 0, 0, 0, 0, 0 - 0 */ + RSP_VAND(1, 2, 3, 4, 5, 6, 7, 0, 0, 0, 0, 0, 0, 0, 0, 0); + break; + case 9: /* 0, 2, 3, 4, 5, 6, 7, 1 - 1 */ /* 1, 1, 1, 1, 1, 1, 1, 1 - 0 */ + RSP_VAND(0, 2, 3, 4, 5, 6, 7, 1, 1, 1, 1, 1, 1, 1, 1, 1); + break; + case 10:/* 0, 1, 3, 4, 5, 6, 7, 2 - 2 */ /* 2, 2, 2, 2, 2, 2, 2, 2 - 0 */ + RSP_VAND(0, 1, 3, 4, 5, 6, 7, 2, 2, 2, 2, 2, 2, 2, 2, 2); + break; + case 11:/* 0, 1, 2, 4, 5, 6, 7, 3 - 3 */ /* 3, 3, 3, 3, 3, 3, 3, 3 - 0 */ + RSP_VAND(0, 1, 2, 4, 5, 6, 7, 3, 3, 3, 3, 3, 3, 3, 3, 3); + break; + case 12:/* 0, 1, 2, 3, 5, 6, 7, 4 - 4 */ /* 4, 4, 4, 4, 4, 4, 4, 4 - 0 */ + RSP_VAND(0, 1, 2, 3, 5, 6, 7, 4, 4, 4, 4, 4, 4, 4, 4, 4); + break; + case 13:/* 0, 1, 2, 3, 4, 6, 7, 5 - 5 */ /* 5, 5, 5, 5, 5, 5, 5, 5 - 0 */ + RSP_VAND(0, 1, 2, 3, 4, 6, 7, 5, 5, 5, 5, 5, 5, 5, 5, 5); + break; + case 14:/* 0, 1, 2, 3, 4, 5, 7, 6 - 6 */ /* 6, 6, 6, 6, 6, 6, 6, 6 - 0 */ + RSP_VAND(0, 1, 2, 3, 4, 5, 7, 6, 6, 6, 6, 6, 6, 6, 6, 6); + break; + case 15:/* 0, 1, 2, 3, 4, 5, 6, 7 - 7 */ /* 7, 7, 7, 7, 7, 7, 7, 7 - 0 */ + RSP_VAND(0, 1, 2, 3, 4, 5, 6, 7, 7, 7, 7, 7, 7, 7, 7, 7); + break; + } + WRITEBACK_RESULT(); } #endif @@ -5787,59 +5787,59 @@ static int generate_vnand(rsp_state *rsp, drcuml_block *block, compiler_state *c // // Bitwise NOT AND of two vector registers - switch(EL) - { - case 0: /* 0, 1, 2, 3, 4, 5, 6, 7 - none */ /* 0, 1, 2, 3, 4, 5, 6, 7 - none */ - RSP_VNAND_DRC(0, 1, 2, 3, 4, 5, 6, 7, 7, 6, 5, 4, 3, 2, 1, 0, 7, 6, 5, 4, 3, 2, 1, 0); - return TRUE; - case 1: /* 0, 1, 2, 3, 4, 5, 6, 7 - ??? */ /* 0, 1, 2, 3, 4, 5, 6, 7 - ??? */ - RSP_VNAND_DRC(0, 1, 2, 3, 4, 5, 6, 7, 7, 6, 5, 4, 3, 2, 1, 0, 7, 6, 5, 4, 3, 2, 1, 0); - return TRUE; - case 2: /* 1, 3, 5, 7, 0, 2, 4, 6 - 0q */ /* 0, 0, 2, 2, 4, 4, 6, 6 - 0q */ - RSP_VNAND_DRC(1, 3, 5, 7, 0, 2, 4, 6, 7, 5, 3, 1, 7, 5, 3, 1, 6, 4, 2, 0, 7, 5, 3, 1); - return TRUE; - case 3: /* 0, 2, 4, 6, 1, 3, 5, 7 - 1q */ /* 1, 1, 3, 3, 5, 5, 7, 7 - 1q */ - RSP_VNAND_DRC(0, 2, 4, 6, 1, 3, 5, 7, 6, 4, 2, 0, 6, 4, 2, 0, 7, 5, 3, 1, 6, 4, 2, 0); - return TRUE; - case 4: /* 1, 2, 3, 5, 6, 7, 0, 4 - 0h */ /* 0, 0, 0, 0, 4, 4, 4, 4 - 0h */ - RSP_VNAND_DRC(1, 2, 3, 5, 6, 7, 0, 4, 7, 7, 7, 3, 3, 3, 7, 3, 6, 5, 4, 2, 1, 0, 7, 3); - return TRUE; - case 5: /* 0, 2, 3, 4, 6, 7, 1, 5 - 1h */ /* 1, 1, 1, 1, 5, 5, 5, 5 - 1h */ - RSP_VNAND_DRC(0, 2, 3, 4, 6, 7, 1, 5, 6, 6, 6, 2, 2, 2, 6, 2, 7, 5, 4, 3, 1, 0, 6, 2); - return TRUE; - case 6: /* 0, 1, 3, 4, 5, 7, 2, 6 - 2h */ /* 2, 2, 2, 2, 6, 6, 6, 6 - 2h */ - RSP_VNAND_DRC(0, 1, 3, 4, 5, 7, 2, 6, 5, 5, 5, 1, 1, 1, 5, 1, 7, 6, 4, 3, 2, 0, 5, 1); - return TRUE; - case 7: /* 0, 1, 2, 4, 5, 6, 3, 7 - 3h */ /* 3, 3, 3, 3, 7, 7, 7, 7 - 3h */ - RSP_VNAND_DRC(0, 1, 2, 4, 5, 6, 3, 7, 4, 4, 4, 0, 0, 0, 4, 0, 7, 6, 5, 3, 2, 1, 4, 0); - return TRUE; - case 8: /* 1, 2, 3, 4, 5, 6, 7, 0 - 0 */ /* 0, 0, 0, 0, 0, 0, 0, 0 - 0 */ - RSP_VNAND_DRC(1, 2, 3, 4, 5, 6, 7, 0, 7, 7, 7, 7, 7, 7, 7, 7, 6, 5, 4, 3, 2, 1, 0, 7); - return TRUE; - case 9: /* 0, 2, 3, 4, 5, 6, 7, 1 - 1 */ /* 1, 1, 1, 1, 1, 1, 1, 1 - 0 */ - RSP_VNAND_DRC(0, 2, 3, 4, 5, 6, 7, 1, 6, 6, 6, 6, 6, 6, 6, 6, 7, 5, 4, 3, 2, 1, 0, 6); - return TRUE; - case 10: /* 0, 1, 3, 4, 5, 6, 7, 2 - 2 */ /* 2, 2, 2, 2, 2, 2, 2, 2 - 0 */ - RSP_VNAND_DRC(0, 1, 3, 4, 5, 6, 7, 2, 5, 5, 5, 5, 5, 5, 5, 5, 7, 6, 4, 3, 2, 1, 0, 5); - return TRUE; - case 11: /* 0, 1, 2, 4, 5, 6, 7, 3 - 3 */ /* 3, 3, 3, 3, 3, 3, 3, 3 - 0 */ - RSP_VNAND_DRC(0, 1, 2, 4, 5, 6, 7, 3, 4, 4, 4, 4, 4, 4, 4, 4, 7, 6, 5, 3, 2, 1, 0, 4); - return TRUE; - case 12: /* 0, 1, 2, 3, 5, 6, 7, 4 - 4 */ /* 4, 4, 4, 4, 4, 4, 4, 4 - 0 */ - RSP_VNAND_DRC(0, 1, 2, 3, 5, 6, 7, 4, 3, 3, 3, 3, 3, 3, 3, 3, 7, 6, 5, 4, 2, 1, 0, 3); - return TRUE; - case 13: /* 0, 1, 2, 3, 4, 6, 7, 5 - 5 */ /* 5, 5, 5, 5, 5, 5, 5, 5 - 0 */ - RSP_VNAND_DRC(0, 1, 2, 3, 4, 6, 7, 5, 2, 2, 2, 2, 2, 2, 2, 2, 7, 6, 5, 4, 3, 1, 0, 2); - return TRUE; - case 14: /* 0, 1, 2, 3, 4, 5, 7, 6 - 6 */ /* 6, 6, 6, 6, 6, 6, 6, 6 - 0 */ - RSP_VNAND_DRC(0, 1, 2, 3, 4, 5, 7, 6, 1, 1, 1, 1, 1, 1, 1, 1, 7, 6, 5, 4, 3, 2, 0, 1); - return TRUE; - case 15: /* 0, 1, 2, 3, 4, 5, 6, 7 - 7 */ /* 7, 7, 7, 7, 7, 7, 7, 7 - 0 */ - RSP_VNAND_DRC(0, 1, 2, 3, 4, 5, 6, 7, 0, 0, 0, 0, 0, 0, 0, 0, 7, 6, 5, 4, 3, 2, 1, 0); - return TRUE; - } - - return TRUE; + switch(EL) + { + case 0: /* 0, 1, 2, 3, 4, 5, 6, 7 - none */ /* 0, 1, 2, 3, 4, 5, 6, 7 - none */ + RSP_VNAND_DRC(0, 1, 2, 3, 4, 5, 6, 7, 7, 6, 5, 4, 3, 2, 1, 0, 7, 6, 5, 4, 3, 2, 1, 0); + return TRUE; + case 1: /* 0, 1, 2, 3, 4, 5, 6, 7 - ??? */ /* 0, 1, 2, 3, 4, 5, 6, 7 - ??? */ + RSP_VNAND_DRC(0, 1, 2, 3, 4, 5, 6, 7, 7, 6, 5, 4, 3, 2, 1, 0, 7, 6, 5, 4, 3, 2, 1, 0); + return TRUE; + case 2: /* 1, 3, 5, 7, 0, 2, 4, 6 - 0q */ /* 0, 0, 2, 2, 4, 4, 6, 6 - 0q */ + RSP_VNAND_DRC(1, 3, 5, 7, 0, 2, 4, 6, 7, 5, 3, 1, 7, 5, 3, 1, 6, 4, 2, 0, 7, 5, 3, 1); + return TRUE; + case 3: /* 0, 2, 4, 6, 1, 3, 5, 7 - 1q */ /* 1, 1, 3, 3, 5, 5, 7, 7 - 1q */ + RSP_VNAND_DRC(0, 2, 4, 6, 1, 3, 5, 7, 6, 4, 2, 0, 6, 4, 2, 0, 7, 5, 3, 1, 6, 4, 2, 0); + return TRUE; + case 4: /* 1, 2, 3, 5, 6, 7, 0, 4 - 0h */ /* 0, 0, 0, 0, 4, 4, 4, 4 - 0h */ + RSP_VNAND_DRC(1, 2, 3, 5, 6, 7, 0, 4, 7, 7, 7, 3, 3, 3, 7, 3, 6, 5, 4, 2, 1, 0, 7, 3); + return TRUE; + case 5: /* 0, 2, 3, 4, 6, 7, 1, 5 - 1h */ /* 1, 1, 1, 1, 5, 5, 5, 5 - 1h */ + RSP_VNAND_DRC(0, 2, 3, 4, 6, 7, 1, 5, 6, 6, 6, 2, 2, 2, 6, 2, 7, 5, 4, 3, 1, 0, 6, 2); + return TRUE; + case 6: /* 0, 1, 3, 4, 5, 7, 2, 6 - 2h */ /* 2, 2, 2, 2, 6, 6, 6, 6 - 2h */ + RSP_VNAND_DRC(0, 1, 3, 4, 5, 7, 2, 6, 5, 5, 5, 1, 1, 1, 5, 1, 7, 6, 4, 3, 2, 0, 5, 1); + return TRUE; + case 7: /* 0, 1, 2, 4, 5, 6, 3, 7 - 3h */ /* 3, 3, 3, 3, 7, 7, 7, 7 - 3h */ + RSP_VNAND_DRC(0, 1, 2, 4, 5, 6, 3, 7, 4, 4, 4, 0, 0, 0, 4, 0, 7, 6, 5, 3, 2, 1, 4, 0); + return TRUE; + case 8: /* 1, 2, 3, 4, 5, 6, 7, 0 - 0 */ /* 0, 0, 0, 0, 0, 0, 0, 0 - 0 */ + RSP_VNAND_DRC(1, 2, 3, 4, 5, 6, 7, 0, 7, 7, 7, 7, 7, 7, 7, 7, 6, 5, 4, 3, 2, 1, 0, 7); + return TRUE; + case 9: /* 0, 2, 3, 4, 5, 6, 7, 1 - 1 */ /* 1, 1, 1, 1, 1, 1, 1, 1 - 0 */ + RSP_VNAND_DRC(0, 2, 3, 4, 5, 6, 7, 1, 6, 6, 6, 6, 6, 6, 6, 6, 7, 5, 4, 3, 2, 1, 0, 6); + return TRUE; + case 10: /* 0, 1, 3, 4, 5, 6, 7, 2 - 2 */ /* 2, 2, 2, 2, 2, 2, 2, 2 - 0 */ + RSP_VNAND_DRC(0, 1, 3, 4, 5, 6, 7, 2, 5, 5, 5, 5, 5, 5, 5, 5, 7, 6, 4, 3, 2, 1, 0, 5); + return TRUE; + case 11: /* 0, 1, 2, 4, 5, 6, 7, 3 - 3 */ /* 3, 3, 3, 3, 3, 3, 3, 3 - 0 */ + RSP_VNAND_DRC(0, 1, 2, 4, 5, 6, 7, 3, 4, 4, 4, 4, 4, 4, 4, 4, 7, 6, 5, 3, 2, 1, 0, 4); + return TRUE; + case 12: /* 0, 1, 2, 3, 5, 6, 7, 4 - 4 */ /* 4, 4, 4, 4, 4, 4, 4, 4 - 0 */ + RSP_VNAND_DRC(0, 1, 2, 3, 5, 6, 7, 4, 3, 3, 3, 3, 3, 3, 3, 3, 7, 6, 5, 4, 2, 1, 0, 3); + return TRUE; + case 13: /* 0, 1, 2, 3, 4, 6, 7, 5 - 5 */ /* 5, 5, 5, 5, 5, 5, 5, 5 - 0 */ + RSP_VNAND_DRC(0, 1, 2, 3, 4, 6, 7, 5, 2, 2, 2, 2, 2, 2, 2, 2, 7, 6, 5, 4, 3, 1, 0, 2); + return TRUE; + case 14: /* 0, 1, 2, 3, 4, 5, 7, 6 - 6 */ /* 6, 6, 6, 6, 6, 6, 6, 6 - 0 */ + RSP_VNAND_DRC(0, 1, 2, 3, 4, 5, 7, 6, 1, 1, 1, 1, 1, 1, 1, 1, 7, 6, 5, 4, 3, 2, 0, 1); + return TRUE; + case 15: /* 0, 1, 2, 3, 4, 5, 6, 7 - 7 */ /* 7, 7, 7, 7, 7, 7, 7, 7 - 0 */ + RSP_VNAND_DRC(0, 1, 2, 3, 4, 5, 6, 7, 0, 0, 0, 0, 0, 0, 0, 0, 7, 6, 5, 4, 3, 2, 1, 0); + return TRUE; + } + + return TRUE; } #else #define RSP_VNAND(E10, E11, E12, E13, E14, E15, E16, E17, E20, E21, E22, E23, E24, E25, E26, E27) \ @@ -5872,58 +5872,58 @@ INLINE void cfunc_rsp_vnand(void *param) // // Bitwise NOT AND of two vector registers - switch(EL) - { - case 0: /* 0, 1, 2, 3, 4, 5, 6, 7 - none */ /* 0, 1, 2, 3, 4, 5, 6, 7 - none */ - RSP_VNAND(0, 1, 2, 3, 4, 5, 6, 7, 0, 1, 2, 3, 4, 5, 6, 7); - break; - case 1: /* 0, 1, 2, 3, 4, 5, 6, 7 - ??? */ /* 0, 1, 2, 3, 4, 5, 6, 7 - ??? */ - RSP_VNAND(0, 1, 2, 3, 4, 5, 6, 7, 0, 1, 2, 3, 4, 5, 6, 7); - break; - case 2: /* 1, 3, 5, 7, 0, 2, 4, 6 - 0q */ /* 0, 0, 2, 2, 4, 4, 6, 6 - 0q */ - RSP_VNAND(1, 3, 5, 7, 0, 2, 4, 6, 0, 2, 4, 6, 0, 2, 4, 6); - break; - case 3: /* 0, 2, 4, 6, 1, 3, 5, 7 - 1q */ /* 1, 1, 3, 3, 5, 5, 7, 7 - 1q */ - RSP_VNAND(0, 2, 4, 6, 1, 3, 5, 7, 1, 3, 5, 7, 1, 3, 5, 7); - break; - case 4: /* 1, 2, 3, 5, 6, 7, 0, 4 - 0h */ /* 0, 0, 0, 0, 4, 4, 4, 4 - 0h */ - RSP_VNAND(1, 2, 3, 5, 6, 7, 0, 4, 0, 0, 0, 4, 4, 4, 0, 4); - break; - case 5: /* 0, 2, 3, 4, 6, 7, 1, 5 - 1h */ /* 1, 1, 1, 1, 5, 5, 5, 5 - 1h */ - RSP_VNAND(0, 2, 3, 4, 6, 7, 1, 5, 1, 1, 1, 5, 5, 5, 1, 5); - break; - case 6: /* 0, 1, 3, 4, 5, 7, 2, 6 - 2h */ /* 2, 2, 2, 2, 6, 6, 6, 6 - 2h */ - RSP_VNAND(0, 1, 3, 4, 5, 7, 2, 6, 2, 2, 2, 6, 6, 6, 2, 6); - break; - case 7: /* 0, 1, 2, 4, 5, 6, 3, 7 - 3h */ /* 3, 3, 3, 3, 7, 7, 7, 7 - 3h */ - RSP_VNAND(0, 1, 2, 4, 5, 6, 3, 7, 3, 3, 3, 7, 7, 7, 3, 7); - break; - case 8: /* 1, 2, 3, 4, 5, 6, 7, 0 - 0 */ /* 0, 0, 0, 0, 0, 0, 0, 0 - 0 */ - RSP_VNAND(1, 2, 3, 4, 5, 6, 7, 0, 0, 0, 0, 0, 0, 0, 0, 0); - break; - case 9: /* 0, 2, 3, 4, 5, 6, 7, 1 - 1 */ /* 1, 1, 1, 1, 1, 1, 1, 1 - 0 */ - RSP_VNAND(0, 2, 3, 4, 5, 6, 7, 1, 1, 1, 1, 1, 1, 1, 1, 1); - break; - case 10:/* 0, 1, 3, 4, 5, 6, 7, 2 - 2 */ /* 2, 2, 2, 2, 2, 2, 2, 2 - 0 */ - RSP_VNAND(0, 1, 3, 4, 5, 6, 7, 2, 2, 2, 2, 2, 2, 2, 2, 2); - break; - case 11:/* 0, 1, 2, 4, 5, 6, 7, 3 - 3 */ /* 3, 3, 3, 3, 3, 3, 3, 3 - 0 */ - RSP_VNAND(0, 1, 2, 4, 5, 6, 7, 3, 3, 3, 3, 3, 3, 3, 3, 3); - break; - case 12:/* 0, 1, 2, 3, 5, 6, 7, 4 - 4 */ /* 4, 4, 4, 4, 4, 4, 4, 4 - 0 */ - RSP_VNAND(0, 1, 2, 3, 5, 6, 7, 4, 4, 4, 4, 4, 4, 4, 4, 4); - break; - case 13:/* 0, 1, 2, 3, 4, 6, 7, 5 - 5 */ /* 5, 5, 5, 5, 5, 5, 5, 5 - 0 */ - RSP_VNAND(0, 1, 2, 3, 4, 6, 7, 5, 5, 5, 5, 5, 5, 5, 5, 5); - break; - case 14:/* 0, 1, 2, 3, 4, 5, 7, 6 - 6 */ /* 6, 6, 6, 6, 6, 6, 6, 6 - 0 */ - RSP_VNAND(0, 1, 2, 3, 4, 5, 7, 6, 6, 6, 6, 6, 6, 6, 6, 6); - break; - case 15:/* 0, 1, 2, 3, 4, 5, 6, 7 - 7 */ /* 7, 7, 7, 7, 7, 7, 7, 7 - 0 */ - RSP_VNAND(0, 1, 2, 3, 4, 5, 6, 7, 7, 7, 7, 7, 7, 7, 7, 7); - break; - } - WRITEBACK_RESULT(); + switch(EL) + { + case 0: /* 0, 1, 2, 3, 4, 5, 6, 7 - none */ /* 0, 1, 2, 3, 4, 5, 6, 7 - none */ + RSP_VNAND(0, 1, 2, 3, 4, 5, 6, 7, 0, 1, 2, 3, 4, 5, 6, 7); + break; + case 1: /* 0, 1, 2, 3, 4, 5, 6, 7 - ??? */ /* 0, 1, 2, 3, 4, 5, 6, 7 - ??? */ + RSP_VNAND(0, 1, 2, 3, 4, 5, 6, 7, 0, 1, 2, 3, 4, 5, 6, 7); + break; + case 2: /* 1, 3, 5, 7, 0, 2, 4, 6 - 0q */ /* 0, 0, 2, 2, 4, 4, 6, 6 - 0q */ + RSP_VNAND(1, 3, 5, 7, 0, 2, 4, 6, 0, 2, 4, 6, 0, 2, 4, 6); + break; + case 3: /* 0, 2, 4, 6, 1, 3, 5, 7 - 1q */ /* 1, 1, 3, 3, 5, 5, 7, 7 - 1q */ + RSP_VNAND(0, 2, 4, 6, 1, 3, 5, 7, 1, 3, 5, 7, 1, 3, 5, 7); + break; + case 4: /* 1, 2, 3, 5, 6, 7, 0, 4 - 0h */ /* 0, 0, 0, 0, 4, 4, 4, 4 - 0h */ + RSP_VNAND(1, 2, 3, 5, 6, 7, 0, 4, 0, 0, 0, 4, 4, 4, 0, 4); + break; + case 5: /* 0, 2, 3, 4, 6, 7, 1, 5 - 1h */ /* 1, 1, 1, 1, 5, 5, 5, 5 - 1h */ + RSP_VNAND(0, 2, 3, 4, 6, 7, 1, 5, 1, 1, 1, 5, 5, 5, 1, 5); + break; + case 6: /* 0, 1, 3, 4, 5, 7, 2, 6 - 2h */ /* 2, 2, 2, 2, 6, 6, 6, 6 - 2h */ + RSP_VNAND(0, 1, 3, 4, 5, 7, 2, 6, 2, 2, 2, 6, 6, 6, 2, 6); + break; + case 7: /* 0, 1, 2, 4, 5, 6, 3, 7 - 3h */ /* 3, 3, 3, 3, 7, 7, 7, 7 - 3h */ + RSP_VNAND(0, 1, 2, 4, 5, 6, 3, 7, 3, 3, 3, 7, 7, 7, 3, 7); + break; + case 8: /* 1, 2, 3, 4, 5, 6, 7, 0 - 0 */ /* 0, 0, 0, 0, 0, 0, 0, 0 - 0 */ + RSP_VNAND(1, 2, 3, 4, 5, 6, 7, 0, 0, 0, 0, 0, 0, 0, 0, 0); + break; + case 9: /* 0, 2, 3, 4, 5, 6, 7, 1 - 1 */ /* 1, 1, 1, 1, 1, 1, 1, 1 - 0 */ + RSP_VNAND(0, 2, 3, 4, 5, 6, 7, 1, 1, 1, 1, 1, 1, 1, 1, 1); + break; + case 10:/* 0, 1, 3, 4, 5, 6, 7, 2 - 2 */ /* 2, 2, 2, 2, 2, 2, 2, 2 - 0 */ + RSP_VNAND(0, 1, 3, 4, 5, 6, 7, 2, 2, 2, 2, 2, 2, 2, 2, 2); + break; + case 11:/* 0, 1, 2, 4, 5, 6, 7, 3 - 3 */ /* 3, 3, 3, 3, 3, 3, 3, 3 - 0 */ + RSP_VNAND(0, 1, 2, 4, 5, 6, 7, 3, 3, 3, 3, 3, 3, 3, 3, 3); + break; + case 12:/* 0, 1, 2, 3, 5, 6, 7, 4 - 4 */ /* 4, 4, 4, 4, 4, 4, 4, 4 - 0 */ + RSP_VNAND(0, 1, 2, 3, 5, 6, 7, 4, 4, 4, 4, 4, 4, 4, 4, 4); + break; + case 13:/* 0, 1, 2, 3, 4, 6, 7, 5 - 5 */ /* 5, 5, 5, 5, 5, 5, 5, 5 - 0 */ + RSP_VNAND(0, 1, 2, 3, 4, 6, 7, 5, 5, 5, 5, 5, 5, 5, 5, 5); + break; + case 14:/* 0, 1, 2, 3, 4, 5, 7, 6 - 6 */ /* 6, 6, 6, 6, 6, 6, 6, 6 - 0 */ + RSP_VNAND(0, 1, 2, 3, 4, 5, 7, 6, 6, 6, 6, 6, 6, 6, 6, 6); + break; + case 15:/* 0, 1, 2, 3, 4, 5, 6, 7 - 7 */ /* 7, 7, 7, 7, 7, 7, 7, 7 - 0 */ + RSP_VNAND(0, 1, 2, 3, 4, 5, 6, 7, 7, 7, 7, 7, 7, 7, 7, 7); + break; + } + WRITEBACK_RESULT(); } #endif @@ -5999,59 +5999,59 @@ static int generate_vor(rsp_state *rsp, drcuml_block *block, compiler_state *com // // Bitwise OR of two vector registers - switch(EL) - { - case 0: /* 0, 1, 2, 3, 4, 5, 6, 7 - none */ /* 0, 1, 2, 3, 4, 5, 6, 7 - none */ - RSP_VOR_DRC(0, 1, 2, 3, 4, 5, 6, 7, 7, 6, 5, 4, 3, 2, 1, 0, 7, 6, 5, 4, 3, 2, 1, 0); - return TRUE; - case 1: /* 0, 1, 2, 3, 4, 5, 6, 7 - ??? */ /* 0, 1, 2, 3, 4, 5, 6, 7 - ??? */ - RSP_VOR_DRC(0, 1, 2, 3, 4, 5, 6, 7, 7, 6, 5, 4, 3, 2, 1, 0, 7, 6, 5, 4, 3, 2, 1, 0); - return TRUE; - case 2: /* 1, 3, 5, 7, 0, 2, 4, 6 - 0q */ /* 0, 0, 2, 2, 4, 4, 6, 6 - 0q */ - RSP_VOR_DRC(1, 3, 5, 7, 0, 2, 4, 6, 7, 5, 3, 1, 7, 5, 3, 1, 6, 4, 2, 0, 7, 5, 3, 1); - return TRUE; - case 3: /* 0, 2, 4, 6, 1, 3, 5, 7 - 1q */ /* 1, 1, 3, 3, 5, 5, 7, 7 - 1q */ - RSP_VOR_DRC(0, 2, 4, 6, 1, 3, 5, 7, 6, 4, 2, 0, 6, 4, 2, 0, 7, 5, 3, 1, 6, 4, 2, 0); - return TRUE; - case 4: /* 1, 2, 3, 5, 6, 7, 0, 4 - 0h */ /* 0, 0, 0, 0, 4, 4, 4, 4 - 0h */ - RSP_VOR_DRC(1, 2, 3, 5, 6, 7, 0, 4, 7, 7, 7, 3, 3, 3, 7, 3, 6, 5, 4, 2, 1, 0, 7, 3); - return TRUE; - case 5: /* 0, 2, 3, 4, 6, 7, 1, 5 - 1h */ /* 1, 1, 1, 1, 5, 5, 5, 5 - 1h */ - RSP_VOR_DRC(0, 2, 3, 4, 6, 7, 1, 5, 6, 6, 6, 2, 2, 2, 6, 2, 7, 5, 4, 3, 1, 0, 6, 2); - return TRUE; - case 6: /* 0, 1, 3, 4, 5, 7, 2, 6 - 2h */ /* 2, 2, 2, 2, 6, 6, 6, 6 - 2h */ - RSP_VOR_DRC(0, 1, 3, 4, 5, 7, 2, 6, 5, 5, 5, 1, 1, 1, 5, 1, 7, 6, 4, 3, 2, 0, 5, 1); - return TRUE; - case 7: /* 0, 1, 2, 4, 5, 6, 3, 7 - 3h */ /* 3, 3, 3, 3, 7, 7, 7, 7 - 3h */ - RSP_VOR_DRC(0, 1, 2, 4, 5, 6, 3, 7, 4, 4, 4, 0, 0, 0, 4, 0, 7, 6, 5, 3, 2, 1, 4, 0); - return TRUE; - case 8: /* 1, 2, 3, 4, 5, 6, 7, 0 - 0 */ /* 0, 0, 0, 0, 0, 0, 0, 0 - 0 */ - RSP_VOR_DRC(1, 2, 3, 4, 5, 6, 7, 0, 7, 7, 7, 7, 7, 7, 7, 7, 6, 5, 4, 3, 2, 1, 0, 7); - return TRUE; - case 9: /* 0, 2, 3, 4, 5, 6, 7, 1 - 1 */ /* 1, 1, 1, 1, 1, 1, 1, 1 - 0 */ - RSP_VOR_DRC(0, 2, 3, 4, 5, 6, 7, 1, 6, 6, 6, 6, 6, 6, 6, 6, 7, 5, 4, 3, 2, 1, 0, 6); - return TRUE; - case 10: /* 0, 1, 3, 4, 5, 6, 7, 2 - 2 */ /* 2, 2, 2, 2, 2, 2, 2, 2 - 0 */ - RSP_VOR_DRC(0, 1, 3, 4, 5, 6, 7, 2, 5, 5, 5, 5, 5, 5, 5, 5, 7, 6, 4, 3, 2, 1, 0, 5); - return TRUE; - case 11: /* 0, 1, 2, 4, 5, 6, 7, 3 - 3 */ /* 3, 3, 3, 3, 3, 3, 3, 3 - 0 */ - RSP_VOR_DRC(0, 1, 2, 4, 5, 6, 7, 3, 4, 4, 4, 4, 4, 4, 4, 4, 7, 6, 5, 3, 2, 1, 0, 4); - return TRUE; - case 12: /* 0, 1, 2, 3, 5, 6, 7, 4 - 4 */ /* 4, 4, 4, 4, 4, 4, 4, 4 - 0 */ - RSP_VOR_DRC(0, 1, 2, 3, 5, 6, 7, 4, 3, 3, 3, 3, 3, 3, 3, 3, 7, 6, 5, 4, 2, 1, 0, 3); - return TRUE; - case 13: /* 0, 1, 2, 3, 4, 6, 7, 5 - 5 */ /* 5, 5, 5, 5, 5, 5, 5, 5 - 0 */ - RSP_VOR_DRC(0, 1, 2, 3, 4, 6, 7, 5, 2, 2, 2, 2, 2, 2, 2, 2, 7, 6, 5, 4, 3, 1, 0, 2); - return TRUE; - case 14: /* 0, 1, 2, 3, 4, 5, 7, 6 - 6 */ /* 6, 6, 6, 6, 6, 6, 6, 6 - 0 */ - RSP_VOR_DRC(0, 1, 2, 3, 4, 5, 7, 6, 1, 1, 1, 1, 1, 1, 1, 1, 7, 6, 5, 4, 3, 2, 0, 1); - return TRUE; - case 15: /* 0, 1, 2, 3, 4, 5, 6, 7 - 7 */ /* 7, 7, 7, 7, 7, 7, 7, 7 - 0 */ - RSP_VOR_DRC(0, 1, 2, 3, 4, 5, 6, 7, 0, 0, 0, 0, 0, 0, 0, 0, 7, 6, 5, 4, 3, 2, 1, 0); - return TRUE; - } - - return TRUE; + switch(EL) + { + case 0: /* 0, 1, 2, 3, 4, 5, 6, 7 - none */ /* 0, 1, 2, 3, 4, 5, 6, 7 - none */ + RSP_VOR_DRC(0, 1, 2, 3, 4, 5, 6, 7, 7, 6, 5, 4, 3, 2, 1, 0, 7, 6, 5, 4, 3, 2, 1, 0); + return TRUE; + case 1: /* 0, 1, 2, 3, 4, 5, 6, 7 - ??? */ /* 0, 1, 2, 3, 4, 5, 6, 7 - ??? */ + RSP_VOR_DRC(0, 1, 2, 3, 4, 5, 6, 7, 7, 6, 5, 4, 3, 2, 1, 0, 7, 6, 5, 4, 3, 2, 1, 0); + return TRUE; + case 2: /* 1, 3, 5, 7, 0, 2, 4, 6 - 0q */ /* 0, 0, 2, 2, 4, 4, 6, 6 - 0q */ + RSP_VOR_DRC(1, 3, 5, 7, 0, 2, 4, 6, 7, 5, 3, 1, 7, 5, 3, 1, 6, 4, 2, 0, 7, 5, 3, 1); + return TRUE; + case 3: /* 0, 2, 4, 6, 1, 3, 5, 7 - 1q */ /* 1, 1, 3, 3, 5, 5, 7, 7 - 1q */ + RSP_VOR_DRC(0, 2, 4, 6, 1, 3, 5, 7, 6, 4, 2, 0, 6, 4, 2, 0, 7, 5, 3, 1, 6, 4, 2, 0); + return TRUE; + case 4: /* 1, 2, 3, 5, 6, 7, 0, 4 - 0h */ /* 0, 0, 0, 0, 4, 4, 4, 4 - 0h */ + RSP_VOR_DRC(1, 2, 3, 5, 6, 7, 0, 4, 7, 7, 7, 3, 3, 3, 7, 3, 6, 5, 4, 2, 1, 0, 7, 3); + return TRUE; + case 5: /* 0, 2, 3, 4, 6, 7, 1, 5 - 1h */ /* 1, 1, 1, 1, 5, 5, 5, 5 - 1h */ + RSP_VOR_DRC(0, 2, 3, 4, 6, 7, 1, 5, 6, 6, 6, 2, 2, 2, 6, 2, 7, 5, 4, 3, 1, 0, 6, 2); + return TRUE; + case 6: /* 0, 1, 3, 4, 5, 7, 2, 6 - 2h */ /* 2, 2, 2, 2, 6, 6, 6, 6 - 2h */ + RSP_VOR_DRC(0, 1, 3, 4, 5, 7, 2, 6, 5, 5, 5, 1, 1, 1, 5, 1, 7, 6, 4, 3, 2, 0, 5, 1); + return TRUE; + case 7: /* 0, 1, 2, 4, 5, 6, 3, 7 - 3h */ /* 3, 3, 3, 3, 7, 7, 7, 7 - 3h */ + RSP_VOR_DRC(0, 1, 2, 4, 5, 6, 3, 7, 4, 4, 4, 0, 0, 0, 4, 0, 7, 6, 5, 3, 2, 1, 4, 0); + return TRUE; + case 8: /* 1, 2, 3, 4, 5, 6, 7, 0 - 0 */ /* 0, 0, 0, 0, 0, 0, 0, 0 - 0 */ + RSP_VOR_DRC(1, 2, 3, 4, 5, 6, 7, 0, 7, 7, 7, 7, 7, 7, 7, 7, 6, 5, 4, 3, 2, 1, 0, 7); + return TRUE; + case 9: /* 0, 2, 3, 4, 5, 6, 7, 1 - 1 */ /* 1, 1, 1, 1, 1, 1, 1, 1 - 0 */ + RSP_VOR_DRC(0, 2, 3, 4, 5, 6, 7, 1, 6, 6, 6, 6, 6, 6, 6, 6, 7, 5, 4, 3, 2, 1, 0, 6); + return TRUE; + case 10: /* 0, 1, 3, 4, 5, 6, 7, 2 - 2 */ /* 2, 2, 2, 2, 2, 2, 2, 2 - 0 */ + RSP_VOR_DRC(0, 1, 3, 4, 5, 6, 7, 2, 5, 5, 5, 5, 5, 5, 5, 5, 7, 6, 4, 3, 2, 1, 0, 5); + return TRUE; + case 11: /* 0, 1, 2, 4, 5, 6, 7, 3 - 3 */ /* 3, 3, 3, 3, 3, 3, 3, 3 - 0 */ + RSP_VOR_DRC(0, 1, 2, 4, 5, 6, 7, 3, 4, 4, 4, 4, 4, 4, 4, 4, 7, 6, 5, 3, 2, 1, 0, 4); + return TRUE; + case 12: /* 0, 1, 2, 3, 5, 6, 7, 4 - 4 */ /* 4, 4, 4, 4, 4, 4, 4, 4 - 0 */ + RSP_VOR_DRC(0, 1, 2, 3, 5, 6, 7, 4, 3, 3, 3, 3, 3, 3, 3, 3, 7, 6, 5, 4, 2, 1, 0, 3); + return TRUE; + case 13: /* 0, 1, 2, 3, 4, 6, 7, 5 - 5 */ /* 5, 5, 5, 5, 5, 5, 5, 5 - 0 */ + RSP_VOR_DRC(0, 1, 2, 3, 4, 6, 7, 5, 2, 2, 2, 2, 2, 2, 2, 2, 7, 6, 5, 4, 3, 1, 0, 2); + return TRUE; + case 14: /* 0, 1, 2, 3, 4, 5, 7, 6 - 6 */ /* 6, 6, 6, 6, 6, 6, 6, 6 - 0 */ + RSP_VOR_DRC(0, 1, 2, 3, 4, 5, 7, 6, 1, 1, 1, 1, 1, 1, 1, 1, 7, 6, 5, 4, 3, 2, 0, 1); + return TRUE; + case 15: /* 0, 1, 2, 3, 4, 5, 6, 7 - 7 */ /* 7, 7, 7, 7, 7, 7, 7, 7 - 0 */ + RSP_VOR_DRC(0, 1, 2, 3, 4, 5, 6, 7, 0, 0, 0, 0, 0, 0, 0, 0, 7, 6, 5, 4, 3, 2, 1, 0); + return TRUE; + } + + return TRUE; } #else #define RSP_VOR(E10, E11, E12, E13, E14, E15, E16, E17, E20, E21, E22, E23, E24, E25, E26, E27) \ @@ -6084,58 +6084,58 @@ INLINE void cfunc_rsp_vor(void *param) // // Bitwise OR of two vector registers - switch(EL) - { - case 0: /* 0, 1, 2, 3, 4, 5, 6, 7 - none */ /* 0, 1, 2, 3, 4, 5, 6, 7 - none */ - RSP_VOR(0, 1, 2, 3, 4, 5, 6, 7, 0, 1, 2, 3, 4, 5, 6, 7); - break; - case 1: /* 0, 1, 2, 3, 4, 5, 6, 7 - ??? */ /* 0, 1, 2, 3, 4, 5, 6, 7 - ??? */ - RSP_VOR(0, 1, 2, 3, 4, 5, 6, 7, 0, 1, 2, 3, 4, 5, 6, 7); - break; - case 2: /* 1, 3, 5, 7, 0, 2, 4, 6 - 0q */ /* 0, 0, 2, 2, 4, 4, 6, 6 - 0q */ - RSP_VOR(1, 3, 5, 7, 0, 2, 4, 6, 0, 2, 4, 6, 0, 2, 4, 6); - break; - case 3: /* 0, 2, 4, 6, 1, 3, 5, 7 - 1q */ /* 1, 1, 3, 3, 5, 5, 7, 7 - 1q */ - RSP_VOR(0, 2, 4, 6, 1, 3, 5, 7, 1, 3, 5, 7, 1, 3, 5, 7); - break; - case 4: /* 1, 2, 3, 5, 6, 7, 0, 4 - 0h */ /* 0, 0, 0, 0, 4, 4, 4, 4 - 0h */ - RSP_VOR(1, 2, 3, 5, 6, 7, 0, 4, 0, 0, 0, 4, 4, 4, 0, 4); - break; - case 5: /* 0, 2, 3, 4, 6, 7, 1, 5 - 1h */ /* 1, 1, 1, 1, 5, 5, 5, 5 - 1h */ - RSP_VOR(0, 2, 3, 4, 6, 7, 1, 5, 1, 1, 1, 5, 5, 5, 1, 5); - break; - case 6: /* 0, 1, 3, 4, 5, 7, 2, 6 - 2h */ /* 2, 2, 2, 2, 6, 6, 6, 6 - 2h */ - RSP_VOR(0, 1, 3, 4, 5, 7, 2, 6, 2, 2, 2, 6, 6, 6, 2, 6); - break; - case 7: /* 0, 1, 2, 4, 5, 6, 3, 7 - 3h */ /* 3, 3, 3, 3, 7, 7, 7, 7 - 3h */ - RSP_VOR(0, 1, 2, 4, 5, 6, 3, 7, 3, 3, 3, 7, 7, 7, 3, 7); - break; - case 8: /* 1, 2, 3, 4, 5, 6, 7, 0 - 0 */ /* 0, 0, 0, 0, 0, 0, 0, 0 - 0 */ - RSP_VOR(1, 2, 3, 4, 5, 6, 7, 0, 0, 0, 0, 0, 0, 0, 0, 0); - break; - case 9: /* 0, 2, 3, 4, 5, 6, 7, 1 - 1 */ /* 1, 1, 1, 1, 1, 1, 1, 1 - 0 */ - RSP_VOR(0, 2, 3, 4, 5, 6, 7, 1, 1, 1, 1, 1, 1, 1, 1, 1); - break; - case 10:/* 0, 1, 3, 4, 5, 6, 7, 2 - 2 */ /* 2, 2, 2, 2, 2, 2, 2, 2 - 0 */ - RSP_VOR(0, 1, 3, 4, 5, 6, 7, 2, 2, 2, 2, 2, 2, 2, 2, 2); - break; - case 11:/* 0, 1, 2, 4, 5, 6, 7, 3 - 3 */ /* 3, 3, 3, 3, 3, 3, 3, 3 - 0 */ - RSP_VOR(0, 1, 2, 4, 5, 6, 7, 3, 3, 3, 3, 3, 3, 3, 3, 3); - break; - case 12:/* 0, 1, 2, 3, 5, 6, 7, 4 - 4 */ /* 4, 4, 4, 4, 4, 4, 4, 4 - 0 */ - RSP_VOR(0, 1, 2, 3, 5, 6, 7, 4, 4, 4, 4, 4, 4, 4, 4, 4); - break; - case 13:/* 0, 1, 2, 3, 4, 6, 7, 5 - 5 */ /* 5, 5, 5, 5, 5, 5, 5, 5 - 0 */ - RSP_VOR(0, 1, 2, 3, 4, 6, 7, 5, 5, 5, 5, 5, 5, 5, 5, 5); - break; - case 14:/* 0, 1, 2, 3, 4, 5, 7, 6 - 6 */ /* 6, 6, 6, 6, 6, 6, 6, 6 - 0 */ - RSP_VOR(0, 1, 2, 3, 4, 5, 7, 6, 6, 6, 6, 6, 6, 6, 6, 6); - break; - case 15:/* 0, 1, 2, 3, 4, 5, 6, 7 - 7 */ /* 7, 7, 7, 7, 7, 7, 7, 7 - 0 */ - RSP_VOR(0, 1, 2, 3, 4, 5, 6, 7, 7, 7, 7, 7, 7, 7, 7, 7); - break; - } - WRITEBACK_RESULT(); + switch(EL) + { + case 0: /* 0, 1, 2, 3, 4, 5, 6, 7 - none */ /* 0, 1, 2, 3, 4, 5, 6, 7 - none */ + RSP_VOR(0, 1, 2, 3, 4, 5, 6, 7, 0, 1, 2, 3, 4, 5, 6, 7); + break; + case 1: /* 0, 1, 2, 3, 4, 5, 6, 7 - ??? */ /* 0, 1, 2, 3, 4, 5, 6, 7 - ??? */ + RSP_VOR(0, 1, 2, 3, 4, 5, 6, 7, 0, 1, 2, 3, 4, 5, 6, 7); + break; + case 2: /* 1, 3, 5, 7, 0, 2, 4, 6 - 0q */ /* 0, 0, 2, 2, 4, 4, 6, 6 - 0q */ + RSP_VOR(1, 3, 5, 7, 0, 2, 4, 6, 0, 2, 4, 6, 0, 2, 4, 6); + break; + case 3: /* 0, 2, 4, 6, 1, 3, 5, 7 - 1q */ /* 1, 1, 3, 3, 5, 5, 7, 7 - 1q */ + RSP_VOR(0, 2, 4, 6, 1, 3, 5, 7, 1, 3, 5, 7, 1, 3, 5, 7); + break; + case 4: /* 1, 2, 3, 5, 6, 7, 0, 4 - 0h */ /* 0, 0, 0, 0, 4, 4, 4, 4 - 0h */ + RSP_VOR(1, 2, 3, 5, 6, 7, 0, 4, 0, 0, 0, 4, 4, 4, 0, 4); + break; + case 5: /* 0, 2, 3, 4, 6, 7, 1, 5 - 1h */ /* 1, 1, 1, 1, 5, 5, 5, 5 - 1h */ + RSP_VOR(0, 2, 3, 4, 6, 7, 1, 5, 1, 1, 1, 5, 5, 5, 1, 5); + break; + case 6: /* 0, 1, 3, 4, 5, 7, 2, 6 - 2h */ /* 2, 2, 2, 2, 6, 6, 6, 6 - 2h */ + RSP_VOR(0, 1, 3, 4, 5, 7, 2, 6, 2, 2, 2, 6, 6, 6, 2, 6); + break; + case 7: /* 0, 1, 2, 4, 5, 6, 3, 7 - 3h */ /* 3, 3, 3, 3, 7, 7, 7, 7 - 3h */ + RSP_VOR(0, 1, 2, 4, 5, 6, 3, 7, 3, 3, 3, 7, 7, 7, 3, 7); + break; + case 8: /* 1, 2, 3, 4, 5, 6, 7, 0 - 0 */ /* 0, 0, 0, 0, 0, 0, 0, 0 - 0 */ + RSP_VOR(1, 2, 3, 4, 5, 6, 7, 0, 0, 0, 0, 0, 0, 0, 0, 0); + break; + case 9: /* 0, 2, 3, 4, 5, 6, 7, 1 - 1 */ /* 1, 1, 1, 1, 1, 1, 1, 1 - 0 */ + RSP_VOR(0, 2, 3, 4, 5, 6, 7, 1, 1, 1, 1, 1, 1, 1, 1, 1); + break; + case 10:/* 0, 1, 3, 4, 5, 6, 7, 2 - 2 */ /* 2, 2, 2, 2, 2, 2, 2, 2 - 0 */ + RSP_VOR(0, 1, 3, 4, 5, 6, 7, 2, 2, 2, 2, 2, 2, 2, 2, 2); + break; + case 11:/* 0, 1, 2, 4, 5, 6, 7, 3 - 3 */ /* 3, 3, 3, 3, 3, 3, 3, 3 - 0 */ + RSP_VOR(0, 1, 2, 4, 5, 6, 7, 3, 3, 3, 3, 3, 3, 3, 3, 3); + break; + case 12:/* 0, 1, 2, 3, 5, 6, 7, 4 - 4 */ /* 4, 4, 4, 4, 4, 4, 4, 4 - 0 */ + RSP_VOR(0, 1, 2, 3, 5, 6, 7, 4, 4, 4, 4, 4, 4, 4, 4, 4); + break; + case 13:/* 0, 1, 2, 3, 4, 6, 7, 5 - 5 */ /* 5, 5, 5, 5, 5, 5, 5, 5 - 0 */ + RSP_VOR(0, 1, 2, 3, 4, 6, 7, 5, 5, 5, 5, 5, 5, 5, 5, 5); + break; + case 14:/* 0, 1, 2, 3, 4, 5, 7, 6 - 6 */ /* 6, 6, 6, 6, 6, 6, 6, 6 - 0 */ + RSP_VOR(0, 1, 2, 3, 4, 5, 7, 6, 6, 6, 6, 6, 6, 6, 6, 6); + break; + case 15:/* 0, 1, 2, 3, 4, 5, 6, 7 - 7 */ /* 7, 7, 7, 7, 7, 7, 7, 7 - 0 */ + RSP_VOR(0, 1, 2, 3, 4, 5, 6, 7, 7, 7, 7, 7, 7, 7, 7, 7); + break; + } + WRITEBACK_RESULT(); } #endif @@ -6219,59 +6219,59 @@ static int generate_vnor(rsp_state *rsp, drcuml_block *block, compiler_state *co // // Bitwise NOT OR of two vector registers - switch(EL) - { - case 0: /* 0, 1, 2, 3, 4, 5, 6, 7 - none */ /* 0, 1, 2, 3, 4, 5, 6, 7 - none */ - RSP_VNOR_DRC(0, 1, 2, 3, 4, 5, 6, 7, 7, 6, 5, 4, 3, 2, 1, 0, 7, 6, 5, 4, 3, 2, 1, 0); - return TRUE; - case 1: /* 0, 1, 2, 3, 4, 5, 6, 7 - ??? */ /* 0, 1, 2, 3, 4, 5, 6, 7 - ??? */ - RSP_VNOR_DRC(0, 1, 2, 3, 4, 5, 6, 7, 7, 6, 5, 4, 3, 2, 1, 0, 7, 6, 5, 4, 3, 2, 1, 0); - return TRUE; - case 2: /* 1, 3, 5, 7, 0, 2, 4, 6 - 0q */ /* 0, 0, 2, 2, 4, 4, 6, 6 - 0q */ - RSP_VNOR_DRC(1, 3, 5, 7, 0, 2, 4, 6, 7, 5, 3, 1, 7, 5, 3, 1, 6, 4, 2, 0, 7, 5, 3, 1); - return TRUE; - case 3: /* 0, 2, 4, 6, 1, 3, 5, 7 - 1q */ /* 1, 1, 3, 3, 5, 5, 7, 7 - 1q */ - RSP_VNOR_DRC(0, 2, 4, 6, 1, 3, 5, 7, 6, 4, 2, 0, 6, 4, 2, 0, 7, 5, 3, 1, 6, 4, 2, 0); - return TRUE; - case 4: /* 1, 2, 3, 5, 6, 7, 0, 4 - 0h */ /* 0, 0, 0, 0, 4, 4, 4, 4 - 0h */ - RSP_VNOR_DRC(1, 2, 3, 5, 6, 7, 0, 4, 7, 7, 7, 3, 3, 3, 7, 3, 6, 5, 4, 2, 1, 0, 7, 3); - return TRUE; - case 5: /* 0, 2, 3, 4, 6, 7, 1, 5 - 1h */ /* 1, 1, 1, 1, 5, 5, 5, 5 - 1h */ - RSP_VNOR_DRC(0, 2, 3, 4, 6, 7, 1, 5, 6, 6, 6, 2, 2, 2, 6, 2, 7, 5, 4, 3, 1, 0, 6, 2); - return TRUE; - case 6: /* 0, 1, 3, 4, 5, 7, 2, 6 - 2h */ /* 2, 2, 2, 2, 6, 6, 6, 6 - 2h */ - RSP_VNOR_DRC(0, 1, 3, 4, 5, 7, 2, 6, 5, 5, 5, 1, 1, 1, 5, 1, 7, 6, 4, 3, 2, 0, 5, 1); - return TRUE; - case 7: /* 0, 1, 2, 4, 5, 6, 3, 7 - 3h */ /* 3, 3, 3, 3, 7, 7, 7, 7 - 3h */ - RSP_VNOR_DRC(0, 1, 2, 4, 5, 6, 3, 7, 4, 4, 4, 0, 0, 0, 4, 0, 7, 6, 5, 3, 2, 1, 4, 0); - return TRUE; - case 8: /* 1, 2, 3, 4, 5, 6, 7, 0 - 0 */ /* 0, 0, 0, 0, 0, 0, 0, 0 - 0 */ - RSP_VNOR_DRC(1, 2, 3, 4, 5, 6, 7, 0, 7, 7, 7, 7, 7, 7, 7, 7, 6, 5, 4, 3, 2, 1, 0, 7); - return TRUE; - case 9: /* 0, 2, 3, 4, 5, 6, 7, 1 - 1 */ /* 1, 1, 1, 1, 1, 1, 1, 1 - 0 */ - RSP_VNOR_DRC(0, 2, 3, 4, 5, 6, 7, 1, 6, 6, 6, 6, 6, 6, 6, 6, 7, 5, 4, 3, 2, 1, 0, 6); - return TRUE; - case 10: /* 0, 1, 3, 4, 5, 6, 7, 2 - 2 */ /* 2, 2, 2, 2, 2, 2, 2, 2 - 0 */ - RSP_VNOR_DRC(0, 1, 3, 4, 5, 6, 7, 2, 5, 5, 5, 5, 5, 5, 5, 5, 7, 6, 4, 3, 2, 1, 0, 5); - return TRUE; - case 11: /* 0, 1, 2, 4, 5, 6, 7, 3 - 3 */ /* 3, 3, 3, 3, 3, 3, 3, 3 - 0 */ - RSP_VNOR_DRC(0, 1, 2, 4, 5, 6, 7, 3, 4, 4, 4, 4, 4, 4, 4, 4, 7, 6, 5, 3, 2, 1, 0, 4); - return TRUE; - case 12: /* 0, 1, 2, 3, 5, 6, 7, 4 - 4 */ /* 4, 4, 4, 4, 4, 4, 4, 4 - 0 */ - RSP_VNOR_DRC(0, 1, 2, 3, 5, 6, 7, 4, 3, 3, 3, 3, 3, 3, 3, 3, 7, 6, 5, 4, 2, 1, 0, 3); - return TRUE; - case 13: /* 0, 1, 2, 3, 4, 6, 7, 5 - 5 */ /* 5, 5, 5, 5, 5, 5, 5, 5 - 0 */ - RSP_VNOR_DRC(0, 1, 2, 3, 4, 6, 7, 5, 2, 2, 2, 2, 2, 2, 2, 2, 7, 6, 5, 4, 3, 1, 0, 2); - return TRUE; - case 14: /* 0, 1, 2, 3, 4, 5, 7, 6 - 6 */ /* 6, 6, 6, 6, 6, 6, 6, 6 - 0 */ - RSP_VNOR_DRC(0, 1, 2, 3, 4, 5, 7, 6, 1, 1, 1, 1, 1, 1, 1, 1, 7, 6, 5, 4, 3, 2, 0, 1); - return TRUE; - case 15: /* 0, 1, 2, 3, 4, 5, 6, 7 - 7 */ /* 7, 7, 7, 7, 7, 7, 7, 7 - 0 */ - RSP_VNOR_DRC(0, 1, 2, 3, 4, 5, 6, 7, 0, 0, 0, 0, 0, 0, 0, 0, 7, 6, 5, 4, 3, 2, 1, 0); - return TRUE; - } - - return TRUE; + switch(EL) + { + case 0: /* 0, 1, 2, 3, 4, 5, 6, 7 - none */ /* 0, 1, 2, 3, 4, 5, 6, 7 - none */ + RSP_VNOR_DRC(0, 1, 2, 3, 4, 5, 6, 7, 7, 6, 5, 4, 3, 2, 1, 0, 7, 6, 5, 4, 3, 2, 1, 0); + return TRUE; + case 1: /* 0, 1, 2, 3, 4, 5, 6, 7 - ??? */ /* 0, 1, 2, 3, 4, 5, 6, 7 - ??? */ + RSP_VNOR_DRC(0, 1, 2, 3, 4, 5, 6, 7, 7, 6, 5, 4, 3, 2, 1, 0, 7, 6, 5, 4, 3, 2, 1, 0); + return TRUE; + case 2: /* 1, 3, 5, 7, 0, 2, 4, 6 - 0q */ /* 0, 0, 2, 2, 4, 4, 6, 6 - 0q */ + RSP_VNOR_DRC(1, 3, 5, 7, 0, 2, 4, 6, 7, 5, 3, 1, 7, 5, 3, 1, 6, 4, 2, 0, 7, 5, 3, 1); + return TRUE; + case 3: /* 0, 2, 4, 6, 1, 3, 5, 7 - 1q */ /* 1, 1, 3, 3, 5, 5, 7, 7 - 1q */ + RSP_VNOR_DRC(0, 2, 4, 6, 1, 3, 5, 7, 6, 4, 2, 0, 6, 4, 2, 0, 7, 5, 3, 1, 6, 4, 2, 0); + return TRUE; + case 4: /* 1, 2, 3, 5, 6, 7, 0, 4 - 0h */ /* 0, 0, 0, 0, 4, 4, 4, 4 - 0h */ + RSP_VNOR_DRC(1, 2, 3, 5, 6, 7, 0, 4, 7, 7, 7, 3, 3, 3, 7, 3, 6, 5, 4, 2, 1, 0, 7, 3); + return TRUE; + case 5: /* 0, 2, 3, 4, 6, 7, 1, 5 - 1h */ /* 1, 1, 1, 1, 5, 5, 5, 5 - 1h */ + RSP_VNOR_DRC(0, 2, 3, 4, 6, 7, 1, 5, 6, 6, 6, 2, 2, 2, 6, 2, 7, 5, 4, 3, 1, 0, 6, 2); + return TRUE; + case 6: /* 0, 1, 3, 4, 5, 7, 2, 6 - 2h */ /* 2, 2, 2, 2, 6, 6, 6, 6 - 2h */ + RSP_VNOR_DRC(0, 1, 3, 4, 5, 7, 2, 6, 5, 5, 5, 1, 1, 1, 5, 1, 7, 6, 4, 3, 2, 0, 5, 1); + return TRUE; + case 7: /* 0, 1, 2, 4, 5, 6, 3, 7 - 3h */ /* 3, 3, 3, 3, 7, 7, 7, 7 - 3h */ + RSP_VNOR_DRC(0, 1, 2, 4, 5, 6, 3, 7, 4, 4, 4, 0, 0, 0, 4, 0, 7, 6, 5, 3, 2, 1, 4, 0); + return TRUE; + case 8: /* 1, 2, 3, 4, 5, 6, 7, 0 - 0 */ /* 0, 0, 0, 0, 0, 0, 0, 0 - 0 */ + RSP_VNOR_DRC(1, 2, 3, 4, 5, 6, 7, 0, 7, 7, 7, 7, 7, 7, 7, 7, 6, 5, 4, 3, 2, 1, 0, 7); + return TRUE; + case 9: /* 0, 2, 3, 4, 5, 6, 7, 1 - 1 */ /* 1, 1, 1, 1, 1, 1, 1, 1 - 0 */ + RSP_VNOR_DRC(0, 2, 3, 4, 5, 6, 7, 1, 6, 6, 6, 6, 6, 6, 6, 6, 7, 5, 4, 3, 2, 1, 0, 6); + return TRUE; + case 10: /* 0, 1, 3, 4, 5, 6, 7, 2 - 2 */ /* 2, 2, 2, 2, 2, 2, 2, 2 - 0 */ + RSP_VNOR_DRC(0, 1, 3, 4, 5, 6, 7, 2, 5, 5, 5, 5, 5, 5, 5, 5, 7, 6, 4, 3, 2, 1, 0, 5); + return TRUE; + case 11: /* 0, 1, 2, 4, 5, 6, 7, 3 - 3 */ /* 3, 3, 3, 3, 3, 3, 3, 3 - 0 */ + RSP_VNOR_DRC(0, 1, 2, 4, 5, 6, 7, 3, 4, 4, 4, 4, 4, 4, 4, 4, 7, 6, 5, 3, 2, 1, 0, 4); + return TRUE; + case 12: /* 0, 1, 2, 3, 5, 6, 7, 4 - 4 */ /* 4, 4, 4, 4, 4, 4, 4, 4 - 0 */ + RSP_VNOR_DRC(0, 1, 2, 3, 5, 6, 7, 4, 3, 3, 3, 3, 3, 3, 3, 3, 7, 6, 5, 4, 2, 1, 0, 3); + return TRUE; + case 13: /* 0, 1, 2, 3, 4, 6, 7, 5 - 5 */ /* 5, 5, 5, 5, 5, 5, 5, 5 - 0 */ + RSP_VNOR_DRC(0, 1, 2, 3, 4, 6, 7, 5, 2, 2, 2, 2, 2, 2, 2, 2, 7, 6, 5, 4, 3, 1, 0, 2); + return TRUE; + case 14: /* 0, 1, 2, 3, 4, 5, 7, 6 - 6 */ /* 6, 6, 6, 6, 6, 6, 6, 6 - 0 */ + RSP_VNOR_DRC(0, 1, 2, 3, 4, 5, 7, 6, 1, 1, 1, 1, 1, 1, 1, 1, 7, 6, 5, 4, 3, 2, 0, 1); + return TRUE; + case 15: /* 0, 1, 2, 3, 4, 5, 6, 7 - 7 */ /* 7, 7, 7, 7, 7, 7, 7, 7 - 0 */ + RSP_VNOR_DRC(0, 1, 2, 3, 4, 5, 6, 7, 0, 0, 0, 0, 0, 0, 0, 0, 7, 6, 5, 4, 3, 2, 1, 0); + return TRUE; + } + + return TRUE; } #else #define RSP_VNOR(E10, E11, E12, E13, E14, E15, E16, E17, E20, E21, E22, E23, E24, E25, E26, E27) \ @@ -6304,58 +6304,58 @@ INLINE void cfunc_rsp_vnor(void *param) // // Bitwise NOT OR of two vector registers - switch(EL) - { - case 0: /* 0, 1, 2, 3, 4, 5, 6, 7 - none */ /* 0, 1, 2, 3, 4, 5, 6, 7 - none */ - RSP_VNOR(0, 1, 2, 3, 4, 5, 6, 7, 0, 1, 2, 3, 4, 5, 6, 7); - break; - case 1: /* 0, 1, 2, 3, 4, 5, 6, 7 - ??? */ /* 0, 1, 2, 3, 4, 5, 6, 7 - ??? */ - RSP_VNOR(0, 1, 2, 3, 4, 5, 6, 7, 0, 1, 2, 3, 4, 5, 6, 7); - break; - case 2: /* 1, 3, 5, 7, 0, 2, 4, 6 - 0q */ /* 0, 0, 2, 2, 4, 4, 6, 6 - 0q */ - RSP_VNOR(1, 3, 5, 7, 0, 2, 4, 6, 0, 2, 4, 6, 0, 2, 4, 6); - break; - case 3: /* 0, 2, 4, 6, 1, 3, 5, 7 - 1q */ /* 1, 1, 3, 3, 5, 5, 7, 7 - 1q */ - RSP_VNOR(0, 2, 4, 6, 1, 3, 5, 7, 1, 3, 5, 7, 1, 3, 5, 7); - break; - case 4: /* 1, 2, 3, 5, 6, 7, 0, 4 - 0h */ /* 0, 0, 0, 0, 4, 4, 4, 4 - 0h */ - RSP_VNOR(1, 2, 3, 5, 6, 7, 0, 4, 0, 0, 0, 4, 4, 4, 0, 4); - break; - case 5: /* 0, 2, 3, 4, 6, 7, 1, 5 - 1h */ /* 1, 1, 1, 1, 5, 5, 5, 5 - 1h */ - RSP_VNOR(0, 2, 3, 4, 6, 7, 1, 5, 1, 1, 1, 5, 5, 5, 1, 5); - break; - case 6: /* 0, 1, 3, 4, 5, 7, 2, 6 - 2h */ /* 2, 2, 2, 2, 6, 6, 6, 6 - 2h */ - RSP_VNOR(0, 1, 3, 4, 5, 7, 2, 6, 2, 2, 2, 6, 6, 6, 2, 6); - break; - case 7: /* 0, 1, 2, 4, 5, 6, 3, 7 - 3h */ /* 3, 3, 3, 3, 7, 7, 7, 7 - 3h */ - RSP_VNOR(0, 1, 2, 4, 5, 6, 3, 7, 3, 3, 3, 7, 7, 7, 3, 7); - break; - case 8: /* 1, 2, 3, 4, 5, 6, 7, 0 - 0 */ /* 0, 0, 0, 0, 0, 0, 0, 0 - 0 */ - RSP_VNOR(1, 2, 3, 4, 5, 6, 7, 0, 0, 0, 0, 0, 0, 0, 0, 0); - break; - case 9: /* 0, 2, 3, 4, 5, 6, 7, 1 - 1 */ /* 1, 1, 1, 1, 1, 1, 1, 1 - 0 */ - RSP_VNOR(0, 2, 3, 4, 5, 6, 7, 1, 1, 1, 1, 1, 1, 1, 1, 1); - break; - case 10:/* 0, 1, 3, 4, 5, 6, 7, 2 - 2 */ /* 2, 2, 2, 2, 2, 2, 2, 2 - 0 */ - RSP_VNOR(0, 1, 3, 4, 5, 6, 7, 2, 2, 2, 2, 2, 2, 2, 2, 2); - break; - case 11:/* 0, 1, 2, 4, 5, 6, 7, 3 - 3 */ /* 3, 3, 3, 3, 3, 3, 3, 3 - 0 */ - RSP_VNOR(0, 1, 2, 4, 5, 6, 7, 3, 3, 3, 3, 3, 3, 3, 3, 3); - break; - case 12:/* 0, 1, 2, 3, 5, 6, 7, 4 - 4 */ /* 4, 4, 4, 4, 4, 4, 4, 4 - 0 */ - RSP_VNOR(0, 1, 2, 3, 5, 6, 7, 4, 4, 4, 4, 4, 4, 4, 4, 4); - break; - case 13:/* 0, 1, 2, 3, 4, 6, 7, 5 - 5 */ /* 5, 5, 5, 5, 5, 5, 5, 5 - 0 */ - RSP_VNOR(0, 1, 2, 3, 4, 6, 7, 5, 5, 5, 5, 5, 5, 5, 5, 5); - break; - case 14:/* 0, 1, 2, 3, 4, 5, 7, 6 - 6 */ /* 6, 6, 6, 6, 6, 6, 6, 6 - 0 */ - RSP_VNOR(0, 1, 2, 3, 4, 5, 7, 6, 6, 6, 6, 6, 6, 6, 6, 6); - break; - case 15:/* 0, 1, 2, 3, 4, 5, 6, 7 - 7 */ /* 7, 7, 7, 7, 7, 7, 7, 7 - 0 */ - RSP_VNOR(0, 1, 2, 3, 4, 5, 6, 7, 7, 7, 7, 7, 7, 7, 7, 7); - break; - } - WRITEBACK_RESULT(); + switch(EL) + { + case 0: /* 0, 1, 2, 3, 4, 5, 6, 7 - none */ /* 0, 1, 2, 3, 4, 5, 6, 7 - none */ + RSP_VNOR(0, 1, 2, 3, 4, 5, 6, 7, 0, 1, 2, 3, 4, 5, 6, 7); + break; + case 1: /* 0, 1, 2, 3, 4, 5, 6, 7 - ??? */ /* 0, 1, 2, 3, 4, 5, 6, 7 - ??? */ + RSP_VNOR(0, 1, 2, 3, 4, 5, 6, 7, 0, 1, 2, 3, 4, 5, 6, 7); + break; + case 2: /* 1, 3, 5, 7, 0, 2, 4, 6 - 0q */ /* 0, 0, 2, 2, 4, 4, 6, 6 - 0q */ + RSP_VNOR(1, 3, 5, 7, 0, 2, 4, 6, 0, 2, 4, 6, 0, 2, 4, 6); + break; + case 3: /* 0, 2, 4, 6, 1, 3, 5, 7 - 1q */ /* 1, 1, 3, 3, 5, 5, 7, 7 - 1q */ + RSP_VNOR(0, 2, 4, 6, 1, 3, 5, 7, 1, 3, 5, 7, 1, 3, 5, 7); + break; + case 4: /* 1, 2, 3, 5, 6, 7, 0, 4 - 0h */ /* 0, 0, 0, 0, 4, 4, 4, 4 - 0h */ + RSP_VNOR(1, 2, 3, 5, 6, 7, 0, 4, 0, 0, 0, 4, 4, 4, 0, 4); + break; + case 5: /* 0, 2, 3, 4, 6, 7, 1, 5 - 1h */ /* 1, 1, 1, 1, 5, 5, 5, 5 - 1h */ + RSP_VNOR(0, 2, 3, 4, 6, 7, 1, 5, 1, 1, 1, 5, 5, 5, 1, 5); + break; + case 6: /* 0, 1, 3, 4, 5, 7, 2, 6 - 2h */ /* 2, 2, 2, 2, 6, 6, 6, 6 - 2h */ + RSP_VNOR(0, 1, 3, 4, 5, 7, 2, 6, 2, 2, 2, 6, 6, 6, 2, 6); + break; + case 7: /* 0, 1, 2, 4, 5, 6, 3, 7 - 3h */ /* 3, 3, 3, 3, 7, 7, 7, 7 - 3h */ + RSP_VNOR(0, 1, 2, 4, 5, 6, 3, 7, 3, 3, 3, 7, 7, 7, 3, 7); + break; + case 8: /* 1, 2, 3, 4, 5, 6, 7, 0 - 0 */ /* 0, 0, 0, 0, 0, 0, 0, 0 - 0 */ + RSP_VNOR(1, 2, 3, 4, 5, 6, 7, 0, 0, 0, 0, 0, 0, 0, 0, 0); + break; + case 9: /* 0, 2, 3, 4, 5, 6, 7, 1 - 1 */ /* 1, 1, 1, 1, 1, 1, 1, 1 - 0 */ + RSP_VNOR(0, 2, 3, 4, 5, 6, 7, 1, 1, 1, 1, 1, 1, 1, 1, 1); + break; + case 10:/* 0, 1, 3, 4, 5, 6, 7, 2 - 2 */ /* 2, 2, 2, 2, 2, 2, 2, 2 - 0 */ + RSP_VNOR(0, 1, 3, 4, 5, 6, 7, 2, 2, 2, 2, 2, 2, 2, 2, 2); + break; + case 11:/* 0, 1, 2, 4, 5, 6, 7, 3 - 3 */ /* 3, 3, 3, 3, 3, 3, 3, 3 - 0 */ + RSP_VNOR(0, 1, 2, 4, 5, 6, 7, 3, 3, 3, 3, 3, 3, 3, 3, 3); + break; + case 12:/* 0, 1, 2, 3, 5, 6, 7, 4 - 4 */ /* 4, 4, 4, 4, 4, 4, 4, 4 - 0 */ + RSP_VNOR(0, 1, 2, 3, 5, 6, 7, 4, 4, 4, 4, 4, 4, 4, 4, 4); + break; + case 13:/* 0, 1, 2, 3, 4, 6, 7, 5 - 5 */ /* 5, 5, 5, 5, 5, 5, 5, 5 - 0 */ + RSP_VNOR(0, 1, 2, 3, 4, 6, 7, 5, 5, 5, 5, 5, 5, 5, 5, 5); + break; + case 14:/* 0, 1, 2, 3, 4, 5, 7, 6 - 6 */ /* 6, 6, 6, 6, 6, 6, 6, 6 - 0 */ + RSP_VNOR(0, 1, 2, 3, 4, 5, 7, 6, 6, 6, 6, 6, 6, 6, 6, 6); + break; + case 15:/* 0, 1, 2, 3, 4, 5, 6, 7 - 7 */ /* 7, 7, 7, 7, 7, 7, 7, 7 - 0 */ + RSP_VNOR(0, 1, 2, 3, 4, 5, 6, 7, 7, 7, 7, 7, 7, 7, 7, 7); + break; + } + WRITEBACK_RESULT(); } #endif @@ -6431,59 +6431,59 @@ static int generate_vxor(rsp_state *rsp, drcuml_block *block, compiler_state *co // // Bitwise XOR of two vector registers - switch(EL) - { - case 0: /* 0, 1, 2, 3, 4, 5, 6, 7 - none */ /* 0, 1, 2, 3, 4, 5, 6, 7 - none */ - RSP_VXOR_DRC(0, 1, 2, 3, 4, 5, 6, 7, 7, 6, 5, 4, 3, 2, 1, 0, 7, 6, 5, 4, 3, 2, 1, 0); - return TRUE; - case 1: /* 0, 1, 2, 3, 4, 5, 6, 7 - ??? */ /* 0, 1, 2, 3, 4, 5, 6, 7 - ??? */ - RSP_VXOR_DRC(0, 1, 2, 3, 4, 5, 6, 7, 7, 6, 5, 4, 3, 2, 1, 0, 7, 6, 5, 4, 3, 2, 1, 0); - return TRUE; - case 2: /* 1, 3, 5, 7, 0, 2, 4, 6 - 0q */ /* 0, 0, 2, 2, 4, 4, 6, 6 - 0q */ - RSP_VXOR_DRC(1, 3, 5, 7, 0, 2, 4, 6, 7, 5, 3, 1, 7, 5, 3, 1, 6, 4, 2, 0, 7, 5, 3, 1); - return TRUE; - case 3: /* 0, 2, 4, 6, 1, 3, 5, 7 - 1q */ /* 1, 1, 3, 3, 5, 5, 7, 7 - 1q */ - RSP_VXOR_DRC(0, 2, 4, 6, 1, 3, 5, 7, 6, 4, 2, 0, 6, 4, 2, 0, 7, 5, 3, 1, 6, 4, 2, 0); - return TRUE; - case 4: /* 1, 2, 3, 5, 6, 7, 0, 4 - 0h */ /* 0, 0, 0, 0, 4, 4, 4, 4 - 0h */ - RSP_VXOR_DRC(1, 2, 3, 5, 6, 7, 0, 4, 7, 7, 7, 3, 3, 3, 7, 3, 6, 5, 4, 2, 1, 0, 7, 3); - return TRUE; - case 5: /* 0, 2, 3, 4, 6, 7, 1, 5 - 1h */ /* 1, 1, 1, 1, 5, 5, 5, 5 - 1h */ - RSP_VXOR_DRC(0, 2, 3, 4, 6, 7, 1, 5, 6, 6, 6, 2, 2, 2, 6, 2, 7, 5, 4, 3, 1, 0, 6, 2); - return TRUE; - case 6: /* 0, 1, 3, 4, 5, 7, 2, 6 - 2h */ /* 2, 2, 2, 2, 6, 6, 6, 6 - 2h */ - RSP_VXOR_DRC(0, 1, 3, 4, 5, 7, 2, 6, 5, 5, 5, 1, 1, 1, 5, 1, 7, 6, 4, 3, 2, 0, 5, 1); - return TRUE; - case 7: /* 0, 1, 2, 4, 5, 6, 3, 7 - 3h */ /* 3, 3, 3, 3, 7, 7, 7, 7 - 3h */ - RSP_VXOR_DRC(0, 1, 2, 4, 5, 6, 3, 7, 4, 4, 4, 0, 0, 0, 4, 0, 7, 6, 5, 3, 2, 1, 4, 0); - return TRUE; - case 8: /* 1, 2, 3, 4, 5, 6, 7, 0 - 0 */ /* 0, 0, 0, 0, 0, 0, 0, 0 - 0 */ - RSP_VXOR_DRC(1, 2, 3, 4, 5, 6, 7, 0, 7, 7, 7, 7, 7, 7, 7, 7, 6, 5, 4, 3, 2, 1, 0, 7); - return TRUE; - case 9: /* 0, 2, 3, 4, 5, 6, 7, 1 - 1 */ /* 1, 1, 1, 1, 1, 1, 1, 1 - 0 */ - RSP_VXOR_DRC(0, 2, 3, 4, 5, 6, 7, 1, 6, 6, 6, 6, 6, 6, 6, 6, 7, 5, 4, 3, 2, 1, 0, 6); - return TRUE; - case 10: /* 0, 1, 3, 4, 5, 6, 7, 2 - 2 */ /* 2, 2, 2, 2, 2, 2, 2, 2 - 0 */ - RSP_VXOR_DRC(0, 1, 3, 4, 5, 6, 7, 2, 5, 5, 5, 5, 5, 5, 5, 5, 7, 6, 4, 3, 2, 1, 0, 5); - return TRUE; - case 11: /* 0, 1, 2, 4, 5, 6, 7, 3 - 3 */ /* 3, 3, 3, 3, 3, 3, 3, 3 - 0 */ - RSP_VXOR_DRC(0, 1, 2, 4, 5, 6, 7, 3, 4, 4, 4, 4, 4, 4, 4, 4, 7, 6, 5, 3, 2, 1, 0, 4); - return TRUE; - case 12: /* 0, 1, 2, 3, 5, 6, 7, 4 - 4 */ /* 4, 4, 4, 4, 4, 4, 4, 4 - 0 */ - RSP_VXOR_DRC(0, 1, 2, 3, 5, 6, 7, 4, 3, 3, 3, 3, 3, 3, 3, 3, 7, 6, 5, 4, 2, 1, 0, 3); - return TRUE; - case 13: /* 0, 1, 2, 3, 4, 6, 7, 5 - 5 */ /* 5, 5, 5, 5, 5, 5, 5, 5 - 0 */ - RSP_VXOR_DRC(0, 1, 2, 3, 4, 6, 7, 5, 2, 2, 2, 2, 2, 2, 2, 2, 7, 6, 5, 4, 3, 1, 0, 2); - return TRUE; - case 14: /* 0, 1, 2, 3, 4, 5, 7, 6 - 6 */ /* 6, 6, 6, 6, 6, 6, 6, 6 - 0 */ - RSP_VXOR_DRC(0, 1, 2, 3, 4, 5, 7, 6, 1, 1, 1, 1, 1, 1, 1, 1, 7, 6, 5, 4, 3, 2, 0, 1); - return TRUE; - case 15: /* 0, 1, 2, 3, 4, 5, 6, 7 - 7 */ /* 7, 7, 7, 7, 7, 7, 7, 7 - 0 */ - RSP_VXOR_DRC(0, 1, 2, 3, 4, 5, 6, 7, 0, 0, 0, 0, 0, 0, 0, 0, 7, 6, 5, 4, 3, 2, 1, 0); - return TRUE; - } - - return TRUE; + switch(EL) + { + case 0: /* 0, 1, 2, 3, 4, 5, 6, 7 - none */ /* 0, 1, 2, 3, 4, 5, 6, 7 - none */ + RSP_VXOR_DRC(0, 1, 2, 3, 4, 5, 6, 7, 7, 6, 5, 4, 3, 2, 1, 0, 7, 6, 5, 4, 3, 2, 1, 0); + return TRUE; + case 1: /* 0, 1, 2, 3, 4, 5, 6, 7 - ??? */ /* 0, 1, 2, 3, 4, 5, 6, 7 - ??? */ + RSP_VXOR_DRC(0, 1, 2, 3, 4, 5, 6, 7, 7, 6, 5, 4, 3, 2, 1, 0, 7, 6, 5, 4, 3, 2, 1, 0); + return TRUE; + case 2: /* 1, 3, 5, 7, 0, 2, 4, 6 - 0q */ /* 0, 0, 2, 2, 4, 4, 6, 6 - 0q */ + RSP_VXOR_DRC(1, 3, 5, 7, 0, 2, 4, 6, 7, 5, 3, 1, 7, 5, 3, 1, 6, 4, 2, 0, 7, 5, 3, 1); + return TRUE; + case 3: /* 0, 2, 4, 6, 1, 3, 5, 7 - 1q */ /* 1, 1, 3, 3, 5, 5, 7, 7 - 1q */ + RSP_VXOR_DRC(0, 2, 4, 6, 1, 3, 5, 7, 6, 4, 2, 0, 6, 4, 2, 0, 7, 5, 3, 1, 6, 4, 2, 0); + return TRUE; + case 4: /* 1, 2, 3, 5, 6, 7, 0, 4 - 0h */ /* 0, 0, 0, 0, 4, 4, 4, 4 - 0h */ + RSP_VXOR_DRC(1, 2, 3, 5, 6, 7, 0, 4, 7, 7, 7, 3, 3, 3, 7, 3, 6, 5, 4, 2, 1, 0, 7, 3); + return TRUE; + case 5: /* 0, 2, 3, 4, 6, 7, 1, 5 - 1h */ /* 1, 1, 1, 1, 5, 5, 5, 5 - 1h */ + RSP_VXOR_DRC(0, 2, 3, 4, 6, 7, 1, 5, 6, 6, 6, 2, 2, 2, 6, 2, 7, 5, 4, 3, 1, 0, 6, 2); + return TRUE; + case 6: /* 0, 1, 3, 4, 5, 7, 2, 6 - 2h */ /* 2, 2, 2, 2, 6, 6, 6, 6 - 2h */ + RSP_VXOR_DRC(0, 1, 3, 4, 5, 7, 2, 6, 5, 5, 5, 1, 1, 1, 5, 1, 7, 6, 4, 3, 2, 0, 5, 1); + return TRUE; + case 7: /* 0, 1, 2, 4, 5, 6, 3, 7 - 3h */ /* 3, 3, 3, 3, 7, 7, 7, 7 - 3h */ + RSP_VXOR_DRC(0, 1, 2, 4, 5, 6, 3, 7, 4, 4, 4, 0, 0, 0, 4, 0, 7, 6, 5, 3, 2, 1, 4, 0); + return TRUE; + case 8: /* 1, 2, 3, 4, 5, 6, 7, 0 - 0 */ /* 0, 0, 0, 0, 0, 0, 0, 0 - 0 */ + RSP_VXOR_DRC(1, 2, 3, 4, 5, 6, 7, 0, 7, 7, 7, 7, 7, 7, 7, 7, 6, 5, 4, 3, 2, 1, 0, 7); + return TRUE; + case 9: /* 0, 2, 3, 4, 5, 6, 7, 1 - 1 */ /* 1, 1, 1, 1, 1, 1, 1, 1 - 0 */ + RSP_VXOR_DRC(0, 2, 3, 4, 5, 6, 7, 1, 6, 6, 6, 6, 6, 6, 6, 6, 7, 5, 4, 3, 2, 1, 0, 6); + return TRUE; + case 10: /* 0, 1, 3, 4, 5, 6, 7, 2 - 2 */ /* 2, 2, 2, 2, 2, 2, 2, 2 - 0 */ + RSP_VXOR_DRC(0, 1, 3, 4, 5, 6, 7, 2, 5, 5, 5, 5, 5, 5, 5, 5, 7, 6, 4, 3, 2, 1, 0, 5); + return TRUE; + case 11: /* 0, 1, 2, 4, 5, 6, 7, 3 - 3 */ /* 3, 3, 3, 3, 3, 3, 3, 3 - 0 */ + RSP_VXOR_DRC(0, 1, 2, 4, 5, 6, 7, 3, 4, 4, 4, 4, 4, 4, 4, 4, 7, 6, 5, 3, 2, 1, 0, 4); + return TRUE; + case 12: /* 0, 1, 2, 3, 5, 6, 7, 4 - 4 */ /* 4, 4, 4, 4, 4, 4, 4, 4 - 0 */ + RSP_VXOR_DRC(0, 1, 2, 3, 5, 6, 7, 4, 3, 3, 3, 3, 3, 3, 3, 3, 7, 6, 5, 4, 2, 1, 0, 3); + return TRUE; + case 13: /* 0, 1, 2, 3, 4, 6, 7, 5 - 5 */ /* 5, 5, 5, 5, 5, 5, 5, 5 - 0 */ + RSP_VXOR_DRC(0, 1, 2, 3, 4, 6, 7, 5, 2, 2, 2, 2, 2, 2, 2, 2, 7, 6, 5, 4, 3, 1, 0, 2); + return TRUE; + case 14: /* 0, 1, 2, 3, 4, 5, 7, 6 - 6 */ /* 6, 6, 6, 6, 6, 6, 6, 6 - 0 */ + RSP_VXOR_DRC(0, 1, 2, 3, 4, 5, 7, 6, 1, 1, 1, 1, 1, 1, 1, 1, 7, 6, 5, 4, 3, 2, 0, 1); + return TRUE; + case 15: /* 0, 1, 2, 3, 4, 5, 6, 7 - 7 */ /* 7, 7, 7, 7, 7, 7, 7, 7 - 0 */ + RSP_VXOR_DRC(0, 1, 2, 3, 4, 5, 6, 7, 0, 0, 0, 0, 0, 0, 0, 0, 7, 6, 5, 4, 3, 2, 1, 0); + return TRUE; + } + + return TRUE; } #else #define RSP_VXOR(E10, E11, E12, E13, E14, E15, E16, E17, E20, E21, E22, E23, E24, E25, E26, E27) \ @@ -6516,58 +6516,58 @@ INLINE void cfunc_rsp_vxor(void *param) // // Bitwise XOR of two vector registers - switch(EL) - { - case 0: /* 0, 1, 2, 3, 4, 5, 6, 7 - none */ /* 0, 1, 2, 3, 4, 5, 6, 7 - none */ - RSP_VXOR(0, 1, 2, 3, 4, 5, 6, 7, 0, 1, 2, 3, 4, 5, 6, 7); - break; - case 1: /* 0, 1, 2, 3, 4, 5, 6, 7 - ??? */ /* 0, 1, 2, 3, 4, 5, 6, 7 - ??? */ - RSP_VXOR(0, 1, 2, 3, 4, 5, 6, 7, 0, 1, 2, 3, 4, 5, 6, 7); - break; - case 2: /* 1, 3, 5, 7, 0, 2, 4, 6 - 0q */ /* 0, 0, 2, 2, 4, 4, 6, 6 - 0q */ - RSP_VXOR(1, 3, 5, 7, 0, 2, 4, 6, 0, 2, 4, 6, 0, 2, 4, 6); - break; - case 3: /* 0, 2, 4, 6, 1, 3, 5, 7 - 1q */ /* 1, 1, 3, 3, 5, 5, 7, 7 - 1q */ - RSP_VXOR(0, 2, 4, 6, 1, 3, 5, 7, 1, 3, 5, 7, 1, 3, 5, 7); - break; - case 4: /* 1, 2, 3, 5, 6, 7, 0, 4 - 0h */ /* 0, 0, 0, 0, 4, 4, 4, 4 - 0h */ - RSP_VXOR(1, 2, 3, 5, 6, 7, 0, 4, 0, 0, 0, 4, 4, 4, 0, 4); - break; - case 5: /* 0, 2, 3, 4, 6, 7, 1, 5 - 1h */ /* 1, 1, 1, 1, 5, 5, 5, 5 - 1h */ - RSP_VXOR(0, 2, 3, 4, 6, 7, 1, 5, 1, 1, 1, 5, 5, 5, 1, 5); - break; - case 6: /* 0, 1, 3, 4, 5, 7, 2, 6 - 2h */ /* 2, 2, 2, 2, 6, 6, 6, 6 - 2h */ - RSP_VXOR(0, 1, 3, 4, 5, 7, 2, 6, 2, 2, 2, 6, 6, 6, 2, 6); - break; - case 7: /* 0, 1, 2, 4, 5, 6, 3, 7 - 3h */ /* 3, 3, 3, 3, 7, 7, 7, 7 - 3h */ - RSP_VXOR(0, 1, 2, 4, 5, 6, 3, 7, 3, 3, 3, 7, 7, 7, 3, 7); - break; - case 8: /* 1, 2, 3, 4, 5, 6, 7, 0 - 0 */ /* 0, 0, 0, 0, 0, 0, 0, 0 - 0 */ - RSP_VXOR(1, 2, 3, 4, 5, 6, 7, 0, 0, 0, 0, 0, 0, 0, 0, 0); - break; - case 9: /* 0, 2, 3, 4, 5, 6, 7, 1 - 1 */ /* 1, 1, 1, 1, 1, 1, 1, 1 - 0 */ - RSP_VXOR(0, 2, 3, 4, 5, 6, 7, 1, 1, 1, 1, 1, 1, 1, 1, 1); - break; - case 10:/* 0, 1, 3, 4, 5, 6, 7, 2 - 2 */ /* 2, 2, 2, 2, 2, 2, 2, 2 - 0 */ - RSP_VXOR(0, 1, 3, 4, 5, 6, 7, 2, 2, 2, 2, 2, 2, 2, 2, 2); - break; - case 11:/* 0, 1, 2, 4, 5, 6, 7, 3 - 3 */ /* 3, 3, 3, 3, 3, 3, 3, 3 - 0 */ - RSP_VXOR(0, 1, 2, 4, 5, 6, 7, 3, 3, 3, 3, 3, 3, 3, 3, 3); - break; - case 12:/* 0, 1, 2, 3, 5, 6, 7, 4 - 4 */ /* 4, 4, 4, 4, 4, 4, 4, 4 - 0 */ - RSP_VXOR(0, 1, 2, 3, 5, 6, 7, 4, 4, 4, 4, 4, 4, 4, 4, 4); - break; - case 13:/* 0, 1, 2, 3, 4, 6, 7, 5 - 5 */ /* 5, 5, 5, 5, 5, 5, 5, 5 - 0 */ - RSP_VXOR(0, 1, 2, 3, 4, 6, 7, 5, 5, 5, 5, 5, 5, 5, 5, 5); - break; - case 14:/* 0, 1, 2, 3, 4, 5, 7, 6 - 6 */ /* 6, 6, 6, 6, 6, 6, 6, 6 - 0 */ - RSP_VXOR(0, 1, 2, 3, 4, 5, 7, 6, 6, 6, 6, 6, 6, 6, 6, 6); - break; - case 15:/* 0, 1, 2, 3, 4, 5, 6, 7 - 7 */ /* 7, 7, 7, 7, 7, 7, 7, 7 - 0 */ - RSP_VXOR(0, 1, 2, 3, 4, 5, 6, 7, 7, 7, 7, 7, 7, 7, 7, 7); - break; - } - WRITEBACK_RESULT(); + switch(EL) + { + case 0: /* 0, 1, 2, 3, 4, 5, 6, 7 - none */ /* 0, 1, 2, 3, 4, 5, 6, 7 - none */ + RSP_VXOR(0, 1, 2, 3, 4, 5, 6, 7, 0, 1, 2, 3, 4, 5, 6, 7); + break; + case 1: /* 0, 1, 2, 3, 4, 5, 6, 7 - ??? */ /* 0, 1, 2, 3, 4, 5, 6, 7 - ??? */ + RSP_VXOR(0, 1, 2, 3, 4, 5, 6, 7, 0, 1, 2, 3, 4, 5, 6, 7); + break; + case 2: /* 1, 3, 5, 7, 0, 2, 4, 6 - 0q */ /* 0, 0, 2, 2, 4, 4, 6, 6 - 0q */ + RSP_VXOR(1, 3, 5, 7, 0, 2, 4, 6, 0, 2, 4, 6, 0, 2, 4, 6); + break; + case 3: /* 0, 2, 4, 6, 1, 3, 5, 7 - 1q */ /* 1, 1, 3, 3, 5, 5, 7, 7 - 1q */ + RSP_VXOR(0, 2, 4, 6, 1, 3, 5, 7, 1, 3, 5, 7, 1, 3, 5, 7); + break; + case 4: /* 1, 2, 3, 5, 6, 7, 0, 4 - 0h */ /* 0, 0, 0, 0, 4, 4, 4, 4 - 0h */ + RSP_VXOR(1, 2, 3, 5, 6, 7, 0, 4, 0, 0, 0, 4, 4, 4, 0, 4); + break; + case 5: /* 0, 2, 3, 4, 6, 7, 1, 5 - 1h */ /* 1, 1, 1, 1, 5, 5, 5, 5 - 1h */ + RSP_VXOR(0, 2, 3, 4, 6, 7, 1, 5, 1, 1, 1, 5, 5, 5, 1, 5); + break; + case 6: /* 0, 1, 3, 4, 5, 7, 2, 6 - 2h */ /* 2, 2, 2, 2, 6, 6, 6, 6 - 2h */ + RSP_VXOR(0, 1, 3, 4, 5, 7, 2, 6, 2, 2, 2, 6, 6, 6, 2, 6); + break; + case 7: /* 0, 1, 2, 4, 5, 6, 3, 7 - 3h */ /* 3, 3, 3, 3, 7, 7, 7, 7 - 3h */ + RSP_VXOR(0, 1, 2, 4, 5, 6, 3, 7, 3, 3, 3, 7, 7, 7, 3, 7); + break; + case 8: /* 1, 2, 3, 4, 5, 6, 7, 0 - 0 */ /* 0, 0, 0, 0, 0, 0, 0, 0 - 0 */ + RSP_VXOR(1, 2, 3, 4, 5, 6, 7, 0, 0, 0, 0, 0, 0, 0, 0, 0); + break; + case 9: /* 0, 2, 3, 4, 5, 6, 7, 1 - 1 */ /* 1, 1, 1, 1, 1, 1, 1, 1 - 0 */ + RSP_VXOR(0, 2, 3, 4, 5, 6, 7, 1, 1, 1, 1, 1, 1, 1, 1, 1); + break; + case 10:/* 0, 1, 3, 4, 5, 6, 7, 2 - 2 */ /* 2, 2, 2, 2, 2, 2, 2, 2 - 0 */ + RSP_VXOR(0, 1, 3, 4, 5, 6, 7, 2, 2, 2, 2, 2, 2, 2, 2, 2); + break; + case 11:/* 0, 1, 2, 4, 5, 6, 7, 3 - 3 */ /* 3, 3, 3, 3, 3, 3, 3, 3 - 0 */ + RSP_VXOR(0, 1, 2, 4, 5, 6, 7, 3, 3, 3, 3, 3, 3, 3, 3, 3); + break; + case 12:/* 0, 1, 2, 3, 5, 6, 7, 4 - 4 */ /* 4, 4, 4, 4, 4, 4, 4, 4 - 0 */ + RSP_VXOR(0, 1, 2, 3, 5, 6, 7, 4, 4, 4, 4, 4, 4, 4, 4, 4); + break; + case 13:/* 0, 1, 2, 3, 4, 6, 7, 5 - 5 */ /* 5, 5, 5, 5, 5, 5, 5, 5 - 0 */ + RSP_VXOR(0, 1, 2, 3, 4, 6, 7, 5, 5, 5, 5, 5, 5, 5, 5, 5); + break; + case 14:/* 0, 1, 2, 3, 4, 5, 7, 6 - 6 */ /* 6, 6, 6, 6, 6, 6, 6, 6 - 0 */ + RSP_VXOR(0, 1, 2, 3, 4, 5, 7, 6, 6, 6, 6, 6, 6, 6, 6, 6); + break; + case 15:/* 0, 1, 2, 3, 4, 5, 6, 7 - 7 */ /* 7, 7, 7, 7, 7, 7, 7, 7 - 0 */ + RSP_VXOR(0, 1, 2, 3, 4, 5, 6, 7, 7, 7, 7, 7, 7, 7, 7, 7); + break; + } + WRITEBACK_RESULT(); } #endif @@ -6651,59 +6651,59 @@ static int generate_vnxor(rsp_state *rsp, drcuml_block *block, compiler_state *c // // Bitwise NOT XOR of two vector registers - switch(EL) - { - case 0: /* 0, 1, 2, 3, 4, 5, 6, 7 - none */ /* 0, 1, 2, 3, 4, 5, 6, 7 - none */ - RSP_VNXOR_DRC(0, 1, 2, 3, 4, 5, 6, 7, 7, 6, 5, 4, 3, 2, 1, 0, 7, 6, 5, 4, 3, 2, 1, 0); - return TRUE; - case 1: /* 0, 1, 2, 3, 4, 5, 6, 7 - ??? */ /* 0, 1, 2, 3, 4, 5, 6, 7 - ??? */ - RSP_VNXOR_DRC(0, 1, 2, 3, 4, 5, 6, 7, 7, 6, 5, 4, 3, 2, 1, 0, 7, 6, 5, 4, 3, 2, 1, 0); - return TRUE; - case 2: /* 1, 3, 5, 7, 0, 2, 4, 6 - 0q */ /* 0, 0, 2, 2, 4, 4, 6, 6 - 0q */ - RSP_VNXOR_DRC(1, 3, 5, 7, 0, 2, 4, 6, 7, 5, 3, 1, 7, 5, 3, 1, 6, 4, 2, 0, 7, 5, 3, 1); - return TRUE; - case 3: /* 0, 2, 4, 6, 1, 3, 5, 7 - 1q */ /* 1, 1, 3, 3, 5, 5, 7, 7 - 1q */ - RSP_VNXOR_DRC(0, 2, 4, 6, 1, 3, 5, 7, 6, 4, 2, 0, 6, 4, 2, 0, 7, 5, 3, 1, 6, 4, 2, 0); - return TRUE; - case 4: /* 1, 2, 3, 5, 6, 7, 0, 4 - 0h */ /* 0, 0, 0, 0, 4, 4, 4, 4 - 0h */ - RSP_VNXOR_DRC(1, 2, 3, 5, 6, 7, 0, 4, 7, 7, 7, 3, 3, 3, 7, 3, 6, 5, 4, 2, 1, 0, 7, 3); - return TRUE; - case 5: /* 0, 2, 3, 4, 6, 7, 1, 5 - 1h */ /* 1, 1, 1, 1, 5, 5, 5, 5 - 1h */ - RSP_VNXOR_DRC(0, 2, 3, 4, 6, 7, 1, 5, 6, 6, 6, 2, 2, 2, 6, 2, 7, 5, 4, 3, 1, 0, 6, 2); - return TRUE; - case 6: /* 0, 1, 3, 4, 5, 7, 2, 6 - 2h */ /* 2, 2, 2, 2, 6, 6, 6, 6 - 2h */ - RSP_VNXOR_DRC(0, 1, 3, 4, 5, 7, 2, 6, 5, 5, 5, 1, 1, 1, 5, 1, 7, 6, 4, 3, 2, 0, 5, 1); - return TRUE; - case 7: /* 0, 1, 2, 4, 5, 6, 3, 7 - 3h */ /* 3, 3, 3, 3, 7, 7, 7, 7 - 3h */ - RSP_VNXOR_DRC(0, 1, 2, 4, 5, 6, 3, 7, 4, 4, 4, 0, 0, 0, 4, 0, 7, 6, 5, 3, 2, 1, 4, 0); - return TRUE; - case 8: /* 1, 2, 3, 4, 5, 6, 7, 0 - 0 */ /* 0, 0, 0, 0, 0, 0, 0, 0 - 0 */ - RSP_VNXOR_DRC(1, 2, 3, 4, 5, 6, 7, 0, 7, 7, 7, 7, 7, 7, 7, 7, 6, 5, 4, 3, 2, 1, 0, 7); - return TRUE; - case 9: /* 0, 2, 3, 4, 5, 6, 7, 1 - 1 */ /* 1, 1, 1, 1, 1, 1, 1, 1 - 0 */ - RSP_VNXOR_DRC(0, 2, 3, 4, 5, 6, 7, 1, 6, 6, 6, 6, 6, 6, 6, 6, 7, 5, 4, 3, 2, 1, 0, 6); - return TRUE; - case 10: /* 0, 1, 3, 4, 5, 6, 7, 2 - 2 */ /* 2, 2, 2, 2, 2, 2, 2, 2 - 0 */ - RSP_VNXOR_DRC(0, 1, 3, 4, 5, 6, 7, 2, 5, 5, 5, 5, 5, 5, 5, 5, 7, 6, 4, 3, 2, 1, 0, 5); - return TRUE; - case 11: /* 0, 1, 2, 4, 5, 6, 7, 3 - 3 */ /* 3, 3, 3, 3, 3, 3, 3, 3 - 0 */ - RSP_VNXOR_DRC(0, 1, 2, 4, 5, 6, 7, 3, 4, 4, 4, 4, 4, 4, 4, 4, 7, 6, 5, 3, 2, 1, 0, 4); - return TRUE; - case 12: /* 0, 1, 2, 3, 5, 6, 7, 4 - 4 */ /* 4, 4, 4, 4, 4, 4, 4, 4 - 0 */ - RSP_VNXOR_DRC(0, 1, 2, 3, 5, 6, 7, 4, 3, 3, 3, 3, 3, 3, 3, 3, 7, 6, 5, 4, 2, 1, 0, 3); - return TRUE; - case 13: /* 0, 1, 2, 3, 4, 6, 7, 5 - 5 */ /* 5, 5, 5, 5, 5, 5, 5, 5 - 0 */ - RSP_VNXOR_DRC(0, 1, 2, 3, 4, 6, 7, 5, 2, 2, 2, 2, 2, 2, 2, 2, 7, 6, 5, 4, 3, 1, 0, 2); - return TRUE; - case 14: /* 0, 1, 2, 3, 4, 5, 7, 6 - 6 */ /* 6, 6, 6, 6, 6, 6, 6, 6 - 0 */ - RSP_VNXOR_DRC(0, 1, 2, 3, 4, 5, 7, 6, 1, 1, 1, 1, 1, 1, 1, 1, 7, 6, 5, 4, 3, 2, 0, 1); - return TRUE; - case 15: /* 0, 1, 2, 3, 4, 5, 6, 7 - 7 */ /* 7, 7, 7, 7, 7, 7, 7, 7 - 0 */ - RSP_VNOR_DRC(0, 1, 2, 3, 4, 5, 6, 7, 0, 0, 0, 0, 0, 0, 0, 0, 7, 6, 5, 4, 3, 2, 1, 0); - return TRUE; - } - - return TRUE; + switch(EL) + { + case 0: /* 0, 1, 2, 3, 4, 5, 6, 7 - none */ /* 0, 1, 2, 3, 4, 5, 6, 7 - none */ + RSP_VNXOR_DRC(0, 1, 2, 3, 4, 5, 6, 7, 7, 6, 5, 4, 3, 2, 1, 0, 7, 6, 5, 4, 3, 2, 1, 0); + return TRUE; + case 1: /* 0, 1, 2, 3, 4, 5, 6, 7 - ??? */ /* 0, 1, 2, 3, 4, 5, 6, 7 - ??? */ + RSP_VNXOR_DRC(0, 1, 2, 3, 4, 5, 6, 7, 7, 6, 5, 4, 3, 2, 1, 0, 7, 6, 5, 4, 3, 2, 1, 0); + return TRUE; + case 2: /* 1, 3, 5, 7, 0, 2, 4, 6 - 0q */ /* 0, 0, 2, 2, 4, 4, 6, 6 - 0q */ + RSP_VNXOR_DRC(1, 3, 5, 7, 0, 2, 4, 6, 7, 5, 3, 1, 7, 5, 3, 1, 6, 4, 2, 0, 7, 5, 3, 1); + return TRUE; + case 3: /* 0, 2, 4, 6, 1, 3, 5, 7 - 1q */ /* 1, 1, 3, 3, 5, 5, 7, 7 - 1q */ + RSP_VNXOR_DRC(0, 2, 4, 6, 1, 3, 5, 7, 6, 4, 2, 0, 6, 4, 2, 0, 7, 5, 3, 1, 6, 4, 2, 0); + return TRUE; + case 4: /* 1, 2, 3, 5, 6, 7, 0, 4 - 0h */ /* 0, 0, 0, 0, 4, 4, 4, 4 - 0h */ + RSP_VNXOR_DRC(1, 2, 3, 5, 6, 7, 0, 4, 7, 7, 7, 3, 3, 3, 7, 3, 6, 5, 4, 2, 1, 0, 7, 3); + return TRUE; + case 5: /* 0, 2, 3, 4, 6, 7, 1, 5 - 1h */ /* 1, 1, 1, 1, 5, 5, 5, 5 - 1h */ + RSP_VNXOR_DRC(0, 2, 3, 4, 6, 7, 1, 5, 6, 6, 6, 2, 2, 2, 6, 2, 7, 5, 4, 3, 1, 0, 6, 2); + return TRUE; + case 6: /* 0, 1, 3, 4, 5, 7, 2, 6 - 2h */ /* 2, 2, 2, 2, 6, 6, 6, 6 - 2h */ + RSP_VNXOR_DRC(0, 1, 3, 4, 5, 7, 2, 6, 5, 5, 5, 1, 1, 1, 5, 1, 7, 6, 4, 3, 2, 0, 5, 1); + return TRUE; + case 7: /* 0, 1, 2, 4, 5, 6, 3, 7 - 3h */ /* 3, 3, 3, 3, 7, 7, 7, 7 - 3h */ + RSP_VNXOR_DRC(0, 1, 2, 4, 5, 6, 3, 7, 4, 4, 4, 0, 0, 0, 4, 0, 7, 6, 5, 3, 2, 1, 4, 0); + return TRUE; + case 8: /* 1, 2, 3, 4, 5, 6, 7, 0 - 0 */ /* 0, 0, 0, 0, 0, 0, 0, 0 - 0 */ + RSP_VNXOR_DRC(1, 2, 3, 4, 5, 6, 7, 0, 7, 7, 7, 7, 7, 7, 7, 7, 6, 5, 4, 3, 2, 1, 0, 7); + return TRUE; + case 9: /* 0, 2, 3, 4, 5, 6, 7, 1 - 1 */ /* 1, 1, 1, 1, 1, 1, 1, 1 - 0 */ + RSP_VNXOR_DRC(0, 2, 3, 4, 5, 6, 7, 1, 6, 6, 6, 6, 6, 6, 6, 6, 7, 5, 4, 3, 2, 1, 0, 6); + return TRUE; + case 10: /* 0, 1, 3, 4, 5, 6, 7, 2 - 2 */ /* 2, 2, 2, 2, 2, 2, 2, 2 - 0 */ + RSP_VNXOR_DRC(0, 1, 3, 4, 5, 6, 7, 2, 5, 5, 5, 5, 5, 5, 5, 5, 7, 6, 4, 3, 2, 1, 0, 5); + return TRUE; + case 11: /* 0, 1, 2, 4, 5, 6, 7, 3 - 3 */ /* 3, 3, 3, 3, 3, 3, 3, 3 - 0 */ + RSP_VNXOR_DRC(0, 1, 2, 4, 5, 6, 7, 3, 4, 4, 4, 4, 4, 4, 4, 4, 7, 6, 5, 3, 2, 1, 0, 4); + return TRUE; + case 12: /* 0, 1, 2, 3, 5, 6, 7, 4 - 4 */ /* 4, 4, 4, 4, 4, 4, 4, 4 - 0 */ + RSP_VNXOR_DRC(0, 1, 2, 3, 5, 6, 7, 4, 3, 3, 3, 3, 3, 3, 3, 3, 7, 6, 5, 4, 2, 1, 0, 3); + return TRUE; + case 13: /* 0, 1, 2, 3, 4, 6, 7, 5 - 5 */ /* 5, 5, 5, 5, 5, 5, 5, 5 - 0 */ + RSP_VNXOR_DRC(0, 1, 2, 3, 4, 6, 7, 5, 2, 2, 2, 2, 2, 2, 2, 2, 7, 6, 5, 4, 3, 1, 0, 2); + return TRUE; + case 14: /* 0, 1, 2, 3, 4, 5, 7, 6 - 6 */ /* 6, 6, 6, 6, 6, 6, 6, 6 - 0 */ + RSP_VNXOR_DRC(0, 1, 2, 3, 4, 5, 7, 6, 1, 1, 1, 1, 1, 1, 1, 1, 7, 6, 5, 4, 3, 2, 0, 1); + return TRUE; + case 15: /* 0, 1, 2, 3, 4, 5, 6, 7 - 7 */ /* 7, 7, 7, 7, 7, 7, 7, 7 - 0 */ + RSP_VNOR_DRC(0, 1, 2, 3, 4, 5, 6, 7, 0, 0, 0, 0, 0, 0, 0, 0, 7, 6, 5, 4, 3, 2, 1, 0); + return TRUE; + } + + return TRUE; } #else #define RSP_VNXOR(E10, E11, E12, E13, E14, E15, E16, E17, E20, E21, E22, E23, E24, E25, E26, E27) \ @@ -6736,58 +6736,58 @@ INLINE void cfunc_rsp_vnxor(void *param) // // Bitwise NOT XOR of two vector registers - switch(EL) - { - case 0: /* 0, 1, 2, 3, 4, 5, 6, 7 - none */ /* 0, 1, 2, 3, 4, 5, 6, 7 - none */ - RSP_VNXOR(0, 1, 2, 3, 4, 5, 6, 7, 0, 1, 2, 3, 4, 5, 6, 7); - break; - case 1: /* 0, 1, 2, 3, 4, 5, 6, 7 - ??? */ /* 0, 1, 2, 3, 4, 5, 6, 7 - ??? */ - RSP_VNXOR(0, 1, 2, 3, 4, 5, 6, 7, 0, 1, 2, 3, 4, 5, 6, 7); - break; - case 2: /* 1, 3, 5, 7, 0, 2, 4, 6 - 0q */ /* 0, 0, 2, 2, 4, 4, 6, 6 - 0q */ - RSP_VNXOR(1, 3, 5, 7, 0, 2, 4, 6, 0, 2, 4, 6, 0, 2, 4, 6); - break; - case 3: /* 0, 2, 4, 6, 1, 3, 5, 7 - 1q */ /* 1, 1, 3, 3, 5, 5, 7, 7 - 1q */ - RSP_VNXOR(0, 2, 4, 6, 1, 3, 5, 7, 1, 3, 5, 7, 1, 3, 5, 7); - break; - case 4: /* 1, 2, 3, 5, 6, 7, 0, 4 - 0h */ /* 0, 0, 0, 0, 4, 4, 4, 4 - 0h */ - RSP_VNXOR(1, 2, 3, 5, 6, 7, 0, 4, 0, 0, 0, 4, 4, 4, 0, 4); - break; - case 5: /* 0, 2, 3, 4, 6, 7, 1, 5 - 1h */ /* 1, 1, 1, 1, 5, 5, 5, 5 - 1h */ - RSP_VNXOR(0, 2, 3, 4, 6, 7, 1, 5, 1, 1, 1, 5, 5, 5, 1, 5); - break; - case 6: /* 0, 1, 3, 4, 5, 7, 2, 6 - 2h */ /* 2, 2, 2, 2, 6, 6, 6, 6 - 2h */ - RSP_VNXOR(0, 1, 3, 4, 5, 7, 2, 6, 2, 2, 2, 6, 6, 6, 2, 6); - break; - case 7: /* 0, 1, 2, 4, 5, 6, 3, 7 - 3h */ /* 3, 3, 3, 3, 7, 7, 7, 7 - 3h */ - RSP_VNXOR(0, 1, 2, 4, 5, 6, 3, 7, 3, 3, 3, 7, 7, 7, 3, 7); - break; - case 8: /* 1, 2, 3, 4, 5, 6, 7, 0 - 0 */ /* 0, 0, 0, 0, 0, 0, 0, 0 - 0 */ - RSP_VNXOR(1, 2, 3, 4, 5, 6, 7, 0, 0, 0, 0, 0, 0, 0, 0, 0); - break; - case 9: /* 0, 2, 3, 4, 5, 6, 7, 1 - 1 */ /* 1, 1, 1, 1, 1, 1, 1, 1 - 0 */ - RSP_VNXOR(0, 2, 3, 4, 5, 6, 7, 1, 1, 1, 1, 1, 1, 1, 1, 1); - break; - case 10:/* 0, 1, 3, 4, 5, 6, 7, 2 - 2 */ /* 2, 2, 2, 2, 2, 2, 2, 2 - 0 */ - RSP_VNXOR(0, 1, 3, 4, 5, 6, 7, 2, 2, 2, 2, 2, 2, 2, 2, 2); - break; - case 11:/* 0, 1, 2, 4, 5, 6, 7, 3 - 3 */ /* 3, 3, 3, 3, 3, 3, 3, 3 - 0 */ - RSP_VNXOR(0, 1, 2, 4, 5, 6, 7, 3, 3, 3, 3, 3, 3, 3, 3, 3); - break; - case 12:/* 0, 1, 2, 3, 5, 6, 7, 4 - 4 */ /* 4, 4, 4, 4, 4, 4, 4, 4 - 0 */ - RSP_VNXOR(0, 1, 2, 3, 5, 6, 7, 4, 4, 4, 4, 4, 4, 4, 4, 4); - break; - case 13:/* 0, 1, 2, 3, 4, 6, 7, 5 - 5 */ /* 5, 5, 5, 5, 5, 5, 5, 5 - 0 */ - RSP_VNXOR(0, 1, 2, 3, 4, 6, 7, 5, 5, 5, 5, 5, 5, 5, 5, 5); - break; - case 14:/* 0, 1, 2, 3, 4, 5, 7, 6 - 6 */ /* 6, 6, 6, 6, 6, 6, 6, 6 - 0 */ - RSP_VNXOR(0, 1, 2, 3, 4, 5, 7, 6, 6, 6, 6, 6, 6, 6, 6, 6); - break; - case 15:/* 0, 1, 2, 3, 4, 5, 6, 7 - 7 */ /* 7, 7, 7, 7, 7, 7, 7, 7 - 0 */ - RSP_VNXOR(0, 1, 2, 3, 4, 5, 6, 7, 7, 7, 7, 7, 7, 7, 7, 7); - break; - } - WRITEBACK_RESULT(); + switch(EL) + { + case 0: /* 0, 1, 2, 3, 4, 5, 6, 7 - none */ /* 0, 1, 2, 3, 4, 5, 6, 7 - none */ + RSP_VNXOR(0, 1, 2, 3, 4, 5, 6, 7, 0, 1, 2, 3, 4, 5, 6, 7); + break; + case 1: /* 0, 1, 2, 3, 4, 5, 6, 7 - ??? */ /* 0, 1, 2, 3, 4, 5, 6, 7 - ??? */ + RSP_VNXOR(0, 1, 2, 3, 4, 5, 6, 7, 0, 1, 2, 3, 4, 5, 6, 7); + break; + case 2: /* 1, 3, 5, 7, 0, 2, 4, 6 - 0q */ /* 0, 0, 2, 2, 4, 4, 6, 6 - 0q */ + RSP_VNXOR(1, 3, 5, 7, 0, 2, 4, 6, 0, 2, 4, 6, 0, 2, 4, 6); + break; + case 3: /* 0, 2, 4, 6, 1, 3, 5, 7 - 1q */ /* 1, 1, 3, 3, 5, 5, 7, 7 - 1q */ + RSP_VNXOR(0, 2, 4, 6, 1, 3, 5, 7, 1, 3, 5, 7, 1, 3, 5, 7); + break; + case 4: /* 1, 2, 3, 5, 6, 7, 0, 4 - 0h */ /* 0, 0, 0, 0, 4, 4, 4, 4 - 0h */ + RSP_VNXOR(1, 2, 3, 5, 6, 7, 0, 4, 0, 0, 0, 4, 4, 4, 0, 4); + break; + case 5: /* 0, 2, 3, 4, 6, 7, 1, 5 - 1h */ /* 1, 1, 1, 1, 5, 5, 5, 5 - 1h */ + RSP_VNXOR(0, 2, 3, 4, 6, 7, 1, 5, 1, 1, 1, 5, 5, 5, 1, 5); + break; + case 6: /* 0, 1, 3, 4, 5, 7, 2, 6 - 2h */ /* 2, 2, 2, 2, 6, 6, 6, 6 - 2h */ + RSP_VNXOR(0, 1, 3, 4, 5, 7, 2, 6, 2, 2, 2, 6, 6, 6, 2, 6); + break; + case 7: /* 0, 1, 2, 4, 5, 6, 3, 7 - 3h */ /* 3, 3, 3, 3, 7, 7, 7, 7 - 3h */ + RSP_VNXOR(0, 1, 2, 4, 5, 6, 3, 7, 3, 3, 3, 7, 7, 7, 3, 7); + break; + case 8: /* 1, 2, 3, 4, 5, 6, 7, 0 - 0 */ /* 0, 0, 0, 0, 0, 0, 0, 0 - 0 */ + RSP_VNXOR(1, 2, 3, 4, 5, 6, 7, 0, 0, 0, 0, 0, 0, 0, 0, 0); + break; + case 9: /* 0, 2, 3, 4, 5, 6, 7, 1 - 1 */ /* 1, 1, 1, 1, 1, 1, 1, 1 - 0 */ + RSP_VNXOR(0, 2, 3, 4, 5, 6, 7, 1, 1, 1, 1, 1, 1, 1, 1, 1); + break; + case 10:/* 0, 1, 3, 4, 5, 6, 7, 2 - 2 */ /* 2, 2, 2, 2, 2, 2, 2, 2 - 0 */ + RSP_VNXOR(0, 1, 3, 4, 5, 6, 7, 2, 2, 2, 2, 2, 2, 2, 2, 2); + break; + case 11:/* 0, 1, 2, 4, 5, 6, 7, 3 - 3 */ /* 3, 3, 3, 3, 3, 3, 3, 3 - 0 */ + RSP_VNXOR(0, 1, 2, 4, 5, 6, 7, 3, 3, 3, 3, 3, 3, 3, 3, 3); + break; + case 12:/* 0, 1, 2, 3, 5, 6, 7, 4 - 4 */ /* 4, 4, 4, 4, 4, 4, 4, 4 - 0 */ + RSP_VNXOR(0, 1, 2, 3, 5, 6, 7, 4, 4, 4, 4, 4, 4, 4, 4, 4); + break; + case 13:/* 0, 1, 2, 3, 4, 6, 7, 5 - 5 */ /* 5, 5, 5, 5, 5, 5, 5, 5 - 0 */ + RSP_VNXOR(0, 1, 2, 3, 4, 6, 7, 5, 5, 5, 5, 5, 5, 5, 5, 5); + break; + case 14:/* 0, 1, 2, 3, 4, 5, 7, 6 - 6 */ /* 6, 6, 6, 6, 6, 6, 6, 6 - 0 */ + RSP_VNXOR(0, 1, 2, 3, 4, 5, 7, 6, 6, 6, 6, 6, 6, 6, 6, 6); + break; + case 15:/* 0, 1, 2, 3, 4, 5, 6, 7 - 7 */ /* 7, 7, 7, 7, 7, 7, 7, 7 - 0 */ + RSP_VNXOR(0, 1, 2, 3, 4, 5, 6, 7, 7, 7, 7, 7, 7, 7, 7, 7); + break; + } + WRITEBACK_RESULT(); } #endif @@ -7472,11 +7472,11 @@ static void static_generate_memory_accessor(rsp_state *rsp, int size, int iswrit UML_AND(block, IREG(2), IREG(0), IMM(3)); // and i2,i0,3 UML_AND(block, IREG(0), IREG(0), IMM(0xffc)); // and i0,i0,0xffc UML_SHL(block, IREG(2), IREG(2), IMM(3)); // shl i2,i2,3 - UML_DLOAD(block, IREG(3), rsp->impstate->dmem, IREG(0), QWORD_x1); // dload i3,dmem,i0,qword_x1 + UML_DLOAD(block, IREG(3), rsp->impstate->dmem, IREG(0), QWORD_x1); // dload i3,dmem,i0,qword_x1 UML_ADD(block, IREG(2), IREG(2), IMM(48)); // add i2,i2,48 UML_DROL(block, IREG(3), IREG(3), IREG(2)); // drol i3,i3,i2 UML_DAND(block, IREG(1), IREG(1), IMM(0xffff)); // dand i1,i1,0xffff - UML_DAND(block, IREG(3), IREG(3), IMM(U64(0xffffffffffff0000))); // dand i3,i3,~0xffff + UML_DAND(block, IREG(3), IREG(3), IMM(U64(0xffffffffffff0000))); // dand i3,i3,~0xffff UML_DOR(block, IREG(1), IREG(1), IREG(3)); // dor i1,i1,i3 UML_DROR(block, IREG(1), IREG(1), IREG(2)); // dror i1,i1,i2 UML_DSTORE(block, rsp->impstate->dmem, IREG(0), IREG(1), QWORD_x1); // dstore dmem,i0,i1,qword_x1 @@ -7496,11 +7496,11 @@ static void static_generate_memory_accessor(rsp_state *rsp, int size, int iswrit UML_AND(block, IREG(2), IREG(0), IMM(3)); // and i2,i0,3 UML_AND(block, IREG(0), IREG(0), IMM(0xffc)); // and i0,i0,0xffc UML_SHL(block, IREG(2), IREG(2), IMM(3)); // shl i2,i2,3 - UML_DLOAD(block, IREG(3), rsp->impstate->dmem, IREG(0), QWORD_x1); // dload i3,dmem,i0,qword_x1 + UML_DLOAD(block, IREG(3), rsp->impstate->dmem, IREG(0), QWORD_x1); // dload i3,dmem,i0,qword_x1 UML_ADD(block, IREG(2), IREG(2), IMM(48)); // add i2,i2,48 UML_DROL(block, IREG(3), IREG(3), IREG(2)); // drol i3,i3,i2 UML_DAND(block, IREG(1), IREG(1), IMM(0xffffffff)); // dand i1,i1,0xffffffff - UML_DAND(block, IREG(3), IREG(3), IMM(U64(0xffffffff00000000))); // dand i3,i3,~0xffffffff + UML_DAND(block, IREG(3), IREG(3), IMM(U64(0xffffffff00000000))); // dand i3,i3,~0xffffffff UML_DOR(block, IREG(1), IREG(1), IREG(3)); // dor i1,i1,i3 UML_DROR(block, IREG(1), IREG(1), IREG(2)); // dror i1,i1,i2 UML_DSTORE(block, rsp->impstate->dmem, IREG(0), IREG(1), QWORD_x1); // dstore dmem,i0,i1,qword_x1 @@ -7515,7 +7515,7 @@ static void static_generate_memory_accessor(rsp_state *rsp, int size, int iswrit UML_XOR(block, IREG(0), IREG(0), IMM(3)); // xor i0,i0,3 #endif UML_AND(block, IREG(0), IREG(0), IMM(0x00000fff)); // and i0,i0,0xfff - UML_LOAD(block, IREG(0), rsp->impstate->dmem, IREG(0), BYTE); // load i0,dmem,i0,byte + UML_LOAD(block, IREG(0), rsp->impstate->dmem, IREG(0), BYTE); // load i0,dmem,i0,byte } else if (size == 2) { @@ -7532,7 +7532,7 @@ static void static_generate_memory_accessor(rsp_state *rsp, int size, int iswrit UML_AND(block, IREG(1), IREG(0), IMM(3)); // and i1,i0,3 UML_AND(block, IREG(0), IREG(0), IMM(0xffc)); // and i0,i0,0xffc UML_SHL(block, IREG(1), IREG(1), IMM(3)); // shl i1,i1,3 - UML_DLOAD(block, IREG(0), rsp->impstate->dmem, IREG(0), QWORD_x1); // dload i0,dmem,i0,qword_x1 + UML_DLOAD(block, IREG(0), rsp->impstate->dmem, IREG(0), QWORD_x1); // dload i0,dmem,i0,qword_x1 UML_ADD(block, IREG(1), IREG(1), IMM(48)); // add i1,i1,48 UML_DROL(block, IREG(0), IREG(0), IREG(1)); // drol i0,i0,i1 UML_AND(block, IREG(0), IREG(0), IMM(0xffff)); // and i0,i0,0xffff @@ -7541,7 +7541,7 @@ static void static_generate_memory_accessor(rsp_state *rsp, int size, int iswrit else if (size == 4) { #ifdef LSB_FIRST - UML_TEST(block, IREG(0), IMM(3)); // test i0,3 + UML_TEST(block, IREG(0), IMM(3)); // test i0,3 UML_JMPc(block, IF_NZ, unaligned_case); // jnz <unaligned_case> #endif UML_AND(block, IREG(0), IREG(0), IMM(0x00000fff)); // and i0,i0,0xfff @@ -7552,7 +7552,7 @@ static void static_generate_memory_accessor(rsp_state *rsp, int size, int iswrit UML_AND(block, IREG(1), IREG(0), IMM(3)); // and i1,i0,3 UML_AND(block, IREG(0), IREG(0), IMM(0xffc)); // and i0,i0,0xffc UML_SHL(block, IREG(1), IREG(1), IMM(3)); // shl i1,i1,3 - UML_DLOAD(block, IREG(0), rsp->impstate->dmem, IREG(0), QWORD_x1); // dload i0,dmem,i0,qword_x1 + UML_DLOAD(block, IREG(0), rsp->impstate->dmem, IREG(0), QWORD_x1); // dload i0,dmem,i0,qword_x1 UML_ADD(block, IREG(1), IREG(1), IMM(48)); // add i1,i1,48 UML_DROL(block, IREG(0), IREG(0), IREG(1)); // drol i0,i0,i1 #endif @@ -7665,9 +7665,9 @@ static void generate_sequence_instruction(rsp_state *rsp, drcuml_block *block, c /* if we hit an unmapped address, fatal error */ //if (desc->flags & OPFLAG_COMPILER_UNMAPPED) //{ - // UML_MOV(block, MEM(&rsp->pc), IMM(desc->pc)); // mov [pc],desc->pc - // save_fast_iregs(rsp, block); - // UML_EXIT(block, IMM(EXECUTE_UNMAPPED_CODE)); // exit EXECUTE_UNMAPPED_CODE + // UML_MOV(block, MEM(&rsp->pc), IMM(desc->pc)); // mov [pc],desc->pc + // save_fast_iregs(rsp, block); + // UML_EXIT(block, IMM(EXECUTE_UNMAPPED_CODE)); // exit EXECUTE_UNMAPPED_CODE //} /* otherwise, unless this is a virtual no-op, it's a regular instruction */ @@ -8188,8 +8188,8 @@ static int generate_opcode(rsp_state *rsp, drcuml_block *block, compiler_state * case 0x3a: /* SWC2 - MIPS I */ return generate_swc2(rsp, block, compiler, desc); - //UML_MOV(block, MEM(&rsp->impstate->arg0), IMM(desc->opptr.l[0])); // mov [arg0],desc->opptr.l - //UML_CALLC(block, cfunc_swc2, rsp); // callc cfunc_mfc2 + //UML_MOV(block, MEM(&rsp->impstate->arg0), IMM(desc->opptr.l[0])); // mov [arg0],desc->opptr.l + //UML_CALLC(block, cfunc_swc2, rsp); // callc cfunc_mfc2 //return TRUE; /* ----- coprocessor instructions ----- */ @@ -8424,7 +8424,7 @@ static int generate_cop2(rsp_state *rsp, drcuml_block *block, compiler_state *co { UML_MOV(block, MEM(&rsp->impstate->arg0), IMM(desc->opptr.l[0])); // mov [arg0],desc->opptr.l UML_CALLC(block, cfunc_mfc2, rsp); // callc cfunc_mfc2 - //UML_SEXT(block, R32(RTREG), IREG(0), DWORD); // dsext <rtreg>,i0,dword + //UML_SEXT(block, R32(RTREG), IREG(0), DWORD); // dsext <rtreg>,i0,dword } return TRUE; @@ -8433,7 +8433,7 @@ static int generate_cop2(rsp_state *rsp, drcuml_block *block, compiler_state *co { UML_MOV(block, MEM(&rsp->impstate->arg0), IMM(desc->opptr.l[0])); // mov [arg0],desc->opptr.l UML_CALLC(block, cfunc_cfc2, rsp); // callc cfunc_cfc2 - //UML_SEXT(block, R32(RTREG), IREG(0), DWORD); // dsext <rtreg>,i0,dword + //UML_SEXT(block, R32(RTREG), IREG(0), DWORD); // dsext <rtreg>,i0,dword } return TRUE; @@ -8618,11 +8618,11 @@ CPU_GET_INFO( rsp ) case CPUINFO_INT_ADDRBUS_WIDTH_PROGRAM: info->i = 32; break; case CPUINFO_INT_ADDRBUS_SHIFT_PROGRAM: info->i = 0; break; case CPUINFO_INT_DATABUS_WIDTH_DATA: info->i = 0; break; - case CPUINFO_INT_ADDRBUS_WIDTH_DATA: info->i = 0; break; - case CPUINFO_INT_ADDRBUS_SHIFT_DATA: info->i = 0; break; + case CPUINFO_INT_ADDRBUS_WIDTH_DATA: info->i = 0; break; + case CPUINFO_INT_ADDRBUS_SHIFT_DATA: info->i = 0; break; case CPUINFO_INT_DATABUS_WIDTH_IO: info->i = 0; break; - case CPUINFO_INT_ADDRBUS_WIDTH_IO: info->i = 0; break; - case CPUINFO_INT_ADDRBUS_SHIFT_IO: info->i = 0; break; + case CPUINFO_INT_ADDRBUS_WIDTH_IO: info->i = 0; break; + case CPUINFO_INT_ADDRBUS_SHIFT_IO: info->i = 0; break; case CPUINFO_INT_INPUT_STATE: info->i = CLEAR_LINE; break; diff --git a/src/mame/drivers/arkanoid.c b/src/mame/drivers/arkanoid.c index 012a710a862..1c3b843689d 100644 --- a/src/mame/drivers/arkanoid.c +++ b/src/mame/drivers/arkanoid.c @@ -1390,7 +1390,7 @@ GAME( 1986, arkangc2, arkanoid, bootleg, arkangc2, arkangc2, ROT90, "bootleg" GAME( 1986, arkblock, arkanoid, bootleg, arkangc, arkblock, ROT90, "bootleg", "Block (Game Corporation bootleg, set 1)", GAME_SUPPORTS_SAVE ) GAME( 1986, arkbloc2, arkanoid, bootleg, arkangc, arkbloc2, ROT90, "bootleg", "Block (Game Corporation bootleg, set 2)", GAME_SUPPORTS_SAVE ) GAME( 1986, arkbloc3, arkanoid, bootleg, block2, block2, ROT90, "bootleg", "Block (Game Corporation bootleg, set 3)", GAME_SUPPORTS_SAVE )// Both these sets have an extra unknown rom -GAME( 1986, block2, arkanoid, bootleg, block2, block2, ROT90, "bootleg", "Block 2 (S.P.A. CO. bootleg)", GAME_SUPPORTS_SAVE ) // and scrambled gfx roms with 'space invader' themed gfx +GAME( 1986, block2, arkanoid, bootleg, block2, block2, ROT90, "bootleg", "Block 2 (S.P.A. CO. bootleg)", GAME_SUPPORTS_SAVE ) // and scrambled gfx roms with 'space invader' themed gfx GAME( 1986, arkgcbl, arkanoid, bootleg, arkgcbl, arkgcbl, ROT90, "bootleg", "Arkanoid (bootleg on Block hardware, set 1)", GAME_SUPPORTS_SAVE ) GAME( 1986, arkgcbla, arkanoid, bootleg, arkgcbl, arkgcbl, ROT90, "bootleg", "Arkanoid (bootleg on Block hardware, set 2)", GAME_SUPPORTS_SAVE ) GAME( 1988, paddle2, arkanoid, bootleg, paddle2, paddle2, ROT90, "bootleg", "Paddle 2 (bootleg on Block hardware)", GAME_SUPPORTS_SAVE ) diff --git a/src/mame/drivers/cb2001.c b/src/mame/drivers/cb2001.c index 5d166432e08..6197cabf7ad 100644 --- a/src/mame/drivers/cb2001.c +++ b/src/mame/drivers/cb2001.c @@ -94,7 +94,7 @@ e0093 78 03 bc e0098 probably "aa" is an undocumented opcode 1) aa 1e ## ## -> bb mov bw,#### -_ 1e ## ## -> 89 mov +_ 1e ## ## -> 89 mov 2) aa 26 ## ## -> bc mov sp,#### _ 26 ## -> b5 mov ch,## diff --git a/src/mame/drivers/darius.c b/src/mame/drivers/darius.c index ef9f75ede7a..6a4a9857b27 100644 --- a/src/mame/drivers/darius.c +++ b/src/mame/drivers/darius.c @@ -809,8 +809,8 @@ static const ym2203_interface ym2203_interface_2 = static const pc080sn_interface darius_pc080sn_intf = { - 1, /* gfxnum */ - -16, 8, 0, 1 /* x_offset, y_offset, y_invert, dblwidth */ + 1, /* gfxnum */ + -16, 8, 0, 1 /* x_offset, y_offset, y_invert, dblwidth */ }; static MACHINE_DRIVER_START( darius ) diff --git a/src/mame/drivers/deco32.c b/src/mame/drivers/deco32.c index f2f72b5fa58..37e64ea6260 100644 --- a/src/mame/drivers/deco32.c +++ b/src/mame/drivers/deco32.c @@ -774,14 +774,14 @@ static ADDRESS_MAP_START( dragngun_map, ADDRESS_SPACE_PROGRAM, 32 ) AM_RANGE(0x138000, 0x138003) AM_NOP /* Palette dma complete in bit 0x8? ack? return 0 else tight loop */ AM_RANGE(0x138008, 0x13800b) AM_WRITE(deco32_palette_dma_w) -// AM_RANGE(0x180000, 0x18001f) AM_RAM_WRITE(deco32_pf12_control_w) AM_BASE(&deco32_pf12_control) +// AM_RANGE(0x180000, 0x18001f) AM_RAM_WRITE(deco32_pf12_control_w) AM_BASE(&deco32_pf12_control) AM_RANGE(0x180000, 0x18001f) AM_RAM AM_BASE(&deco32_pf12_control) AM_RANGE(0x190000, 0x191fff) AM_RAM_WRITE(deco32_pf1_data_w) AM_BASE(&deco32_pf1_data) AM_RANGE(0x194000, 0x195fff) AM_RAM_WRITE(deco32_pf2_data_w) AM_BASE(&deco32_pf2_data) AM_RANGE(0x1a0000, 0x1a0fff) AM_RAM AM_BASE(&deco32_pf1_rowscroll) AM_RANGE(0x1a4000, 0x1a4fff) AM_RAM AM_BASE(&deco32_pf2_rowscroll) -// AM_RANGE(0x1c0000, 0x1c001f) AM_RAM_WRITE(deco32_pf34_control_w) AM_BASE(&deco32_pf34_control) +// AM_RANGE(0x1c0000, 0x1c001f) AM_RAM_WRITE(deco32_pf34_control_w) AM_BASE(&deco32_pf34_control) AM_RANGE(0x1c0000, 0x1c001f) AM_RAM AM_BASE(&deco32_pf34_control) AM_RANGE(0x1d0000, 0x1d1fff) AM_RAM_WRITE(deco32_pf3_data_w) AM_BASE(&deco32_pf3_data) AM_RANGE(0x1d4000, 0x1d5fff) AM_RAM_WRITE(deco32_pf4_data_w) AM_BASE(&deco32_pf4_data) @@ -827,14 +827,14 @@ static ADDRESS_MAP_START( lockload_map, ADDRESS_SPACE_PROGRAM, 32 ) AM_RANGE(0x170000, 0x170007) AM_READ(lockload_gun_mirror_r) /* Not on Dragongun */ AM_RANGE(0x178008, 0x17800f) AM_WRITENOP /* Gun read ACK's */ -// AM_RANGE(0x180000, 0x18001f) AM_RAM_WRITE(deco32_pf12_control_w) AM_BASE(&deco32_pf12_control) +// AM_RANGE(0x180000, 0x18001f) AM_RAM_WRITE(deco32_pf12_control_w) AM_BASE(&deco32_pf12_control) AM_RANGE(0x180000, 0x18001f) AM_RAM AM_BASE(&deco32_pf12_control) AM_RANGE(0x190000, 0x191fff) AM_RAM_WRITE(deco32_pf1_data_w) AM_BASE(&deco32_pf1_data) AM_RANGE(0x194000, 0x195fff) AM_RAM_WRITE(deco32_pf2_data_w) AM_BASE(&deco32_pf2_data) AM_RANGE(0x1a0000, 0x1a0fff) AM_RAM AM_BASE(&deco32_pf1_rowscroll) AM_RANGE(0x1a4000, 0x1a4fff) AM_RAM AM_BASE(&deco32_pf2_rowscroll) -// AM_RANGE(0x1c0000, 0x1c001f) AM_RAM_WRITE(deco32_pf34_control_w) AM_BASE(&deco32_pf34_control) +// AM_RANGE(0x1c0000, 0x1c001f) AM_RAM_WRITE(deco32_pf34_control_w) AM_BASE(&deco32_pf34_control) AM_RANGE(0x1c0000, 0x1c001f) AM_RAM AM_BASE(&deco32_pf34_control) AM_RANGE(0x1d0000, 0x1d1fff) AM_RAM_WRITE(deco32_pf3_data_w) AM_BASE(&deco32_pf3_data) AM_RANGE(0x1d4000, 0x1d5fff) AM_RAM_WRITE(deco32_pf4_data_w) AM_BASE(&deco32_pf4_data) diff --git a/src/mame/drivers/galastrm.c b/src/mame/drivers/galastrm.c index 7653b8bf331..e1b1134cf38 100644 --- a/src/mame/drivers/galastrm.c +++ b/src/mame/drivers/galastrm.c @@ -310,7 +310,7 @@ static const tc0100scn_interface galastrm_tc0100scn_intf = static const tc0480scp_interface galastrm_tc0480scp_intf = { 1, 3, /* gfxnum, txnum */ - 0, /* pixels */ + 0, /* pixels */ -40, -3, /* x_offset, y_offset */ 0, 0, /* text_xoff, text_yoff */ 0, 0, /* flip_xoff, flip_yoff */ diff --git a/src/mame/drivers/goldstar.c b/src/mame/drivers/goldstar.c index 82c5b18087f..dc575ea5326 100644 --- a/src/mame/drivers/goldstar.c +++ b/src/mame/drivers/goldstar.c @@ -5969,7 +5969,7 @@ there is extra hardware which causes it to run a different game contained in tha the extra rom contains -MEGA DOUBLE POKER TM COPYRIGHT 1991 +MEGA DOUBLE POKER TM COPYRIGHT 1991 as well as various @@ -6016,7 +6016,7 @@ ROM_START( cmasterbv ) ROM_CONTINUE(0x5000,0x1000) ROM_REGION( 0x20000, "extra", 0 ) // how do we use this?!! - ROM_LOAD( "mgraise.bin", 0x0000, 0x20000, CRC(019f37d4) SHA1(ab71fe0b41ff4415896a23f28b27a0e64950c68c) ) + ROM_LOAD( "mgraise.bin", 0x0000, 0x20000, CRC(019f37d4) SHA1(ab71fe0b41ff4415896a23f28b27a0e64950c68c) ) ROM_REGION( 0x18000, "gfx1", 0 ) @@ -8638,7 +8638,7 @@ GAME( 1991, cmasterf, cmaster, cm, cmasterb, cmv4, ROT0, "Dyna", GAME( 1991, cmast91, 0, cmast91, cmast91, cmast91, ROT0, "Dyna", "Cherry Master '91 (ver.1.30)", 0 ) -GAME( 1992, cmast92, 0, cmast91, cmast91, cmast91, ROT0, "Dyna", "Cherry Master '92", GAME_NOT_WORKING ) // no gfx roms are dumped +GAME( 1992, cmast92, 0, cmast91, cmast91, cmast91, ROT0, "Dyna", "Cherry Master '92", GAME_NOT_WORKING ) // no gfx roms are dumped GAME( 1989, lucky8, 0, lucky8, lucky8, 0, ROT0, "Wing Co.Ltd / GEI", "New Lucky 8 Lines (set 1)", 0 ) diff --git a/src/mame/drivers/groundfx.c b/src/mame/drivers/groundfx.c index 9f0497124f6..6b7b8ac3538 100644 --- a/src/mame/drivers/groundfx.c +++ b/src/mame/drivers/groundfx.c @@ -354,7 +354,7 @@ static const tc0100scn_interface groundfx_tc0100scn_intf = static const tc0480scp_interface groundfx_tc0480scp_intf = { 1, 4, /* gfxnum, txnum */ - 0, /* pixels */ + 0, /* pixels */ 0x24, 0, /* x_offset, y_offset */ -1, 0, /* text_xoff, text_yoff */ 0, 0, /* flip_xoff, flip_yoff */ diff --git a/src/mame/drivers/gunbustr.c b/src/mame/drivers/gunbustr.c index f651c2df4fb..65a555f31a9 100644 --- a/src/mame/drivers/gunbustr.c +++ b/src/mame/drivers/gunbustr.c @@ -317,7 +317,7 @@ static const eeprom_interface gunbustr_eeprom_interface = static const tc0480scp_interface gunbustr_tc0480scp_intf = { 1, 2, /* gfxnum, txnum */ - 0, /* pixels */ + 0, /* pixels */ 0x20, 0x07, /* x_offset, y_offset */ -1, -1, /* text_xoff, text_yoff */ -1, 0, /* flip_xoff, flip_yoff */ diff --git a/src/mame/drivers/namcond1.c b/src/mame/drivers/namcond1.c index ad5afb08ca7..1793c34f3a1 100644 --- a/src/mame/drivers/namcond1.c +++ b/src/mame/drivers/namcond1.c @@ -287,7 +287,7 @@ static MACHINE_DRIVER_START( namcond1 ) MDRV_CPU_ADD("maincpu", M68000, 12288000) MDRV_CPU_PROGRAM_MAP(namcond1_map) MDRV_CPU_VBLANK_INT("screen", irq1_line_hold) - + // I've disabled this for now, I don't think it's correct, it breaks ncv2 'game options' in test // mode (and could also be responsible for the random resets?) // also, if you log the timing of it and the scanlines on which the interrupt fires, it doesn't diff --git a/src/mame/drivers/opwolf.c b/src/mame/drivers/opwolf.c index 326867f944e..215aee5bf67 100644 --- a/src/mame/drivers/opwolf.c +++ b/src/mame/drivers/opwolf.c @@ -710,8 +710,8 @@ static const msm5205_interface msm5205_config = static const pc080sn_interface opwolf_pc080sn_intf = { - 1, /* gfxnum */ - 0, 0, 0, 0 /* x_offset, y_offset, y_invert, dblwidth */ + 1, /* gfxnum */ + 0, 0, 0, 0 /* x_offset, y_offset, y_invert, dblwidth */ }; static const pc090oj_interface opwolf_pc090oj_intf = diff --git a/src/mame/drivers/rainbow.c b/src/mame/drivers/rainbow.c index b372eba553b..26beb419ce8 100644 --- a/src/mame/drivers/rainbow.c +++ b/src/mame/drivers/rainbow.c @@ -649,14 +649,14 @@ static const ym2151_interface ym2151_config = static const pc080sn_interface rainbow_pc080sn_intf = { - 1, /* gfxnum */ - 0, 0, 0, 0 /* x_offset, y_offset, y_invert, dblwidth */ + 1, /* gfxnum */ + 0, 0, 0, 0 /* x_offset, y_offset, y_invert, dblwidth */ }; static const pc080sn_interface jumping_pc080sn_intf = { - 1, /* gfxnum */ - 0, 0, 1, 0 /* x_offset, y_offset, y_invert, dblwidth */ + 1, /* gfxnum */ + 0, 0, 1, 0 /* x_offset, y_offset, y_invert, dblwidth */ }; static const pc090oj_interface rainbow_pc090oj_intf = diff --git a/src/mame/drivers/rastan.c b/src/mame/drivers/rastan.c index eefffa561e2..3f119ec1898 100644 --- a/src/mame/drivers/rastan.c +++ b/src/mame/drivers/rastan.c @@ -382,8 +382,8 @@ static MACHINE_RESET( rastan ) static const pc080sn_interface rastan_pc080sn_intf = { - 0, /* gfxnum */ - 0, 0, 0, 0 /* x_offset, y_offset, y_invert, dblwidth */ + 0, /* gfxnum */ + 0, 0, 0, 0 /* x_offset, y_offset, y_invert, dblwidth */ }; static const pc090oj_interface rastan_pc090oj_intf = diff --git a/src/mame/drivers/slapshot.c b/src/mame/drivers/slapshot.c index c357ea2495c..d6bdf72f921 100644 --- a/src/mame/drivers/slapshot.c +++ b/src/mame/drivers/slapshot.c @@ -498,7 +498,7 @@ static const ym2610_interface ym2610_config = static const tc0480scp_interface slapshot_tc0480scp_intf = { 1, 2, /* gfxnum, txnum */ - 3, /* pixels */ + 3, /* pixels */ 30, 9, /* x_offset, y_offset */ -1, 1, /* text_xoff, text_yoff */ 0, 2, /* flip_xoff, flip_yoff */ diff --git a/src/mame/drivers/superchs.c b/src/mame/drivers/superchs.c index 15c48ad8e0a..86e09e93dc1 100644 --- a/src/mame/drivers/superchs.c +++ b/src/mame/drivers/superchs.c @@ -363,7 +363,7 @@ static const eeprom_interface superchs_eeprom_interface = static const tc0480scp_interface superchs_tc0480scp_intf = { 1, 2, /* gfxnum, txnum */ - 0, /* pixels */ + 0, /* pixels */ 0x20, 0x08, /* x_offset, y_offset */ -1, 0, /* text_xoff, text_yoff */ 0, 0, /* flip_xoff, flip_yoff */ diff --git a/src/mame/drivers/taito_f2.c b/src/mame/drivers/taito_f2.c index af725699a9d..a8f4cb2bf4d 100644 --- a/src/mame/drivers/taito_f2.c +++ b/src/mame/drivers/taito_f2.c @@ -3265,7 +3265,7 @@ static const tc0100scn_interface thundfox_tc0100scn_intf_2 = static const tc0480scp_interface footchmp_tc0480scp_intf = { 1, 2, /* gfxnum, txnum */ - 3, /* pixels */ + 3, /* pixels */ 0x1d, 0x08, /* x_offset, y_offset */ -1, 0, /* text_xoff, text_yoff */ -1, 0, /* flip_xoff, flip_yoff */ @@ -3275,7 +3275,7 @@ static const tc0480scp_interface footchmp_tc0480scp_intf = static const tc0480scp_interface hthero_tc0480scp_intf = { 1, 2, /* gfxnum, txnum */ - 3, /* pixels */ + 3, /* pixels */ 0x33, -0x04, /* x_offset, y_offset */ -1, 0, /* text_xoff, text_yoff */ -1, 0, /* flip_xoff, flip_yoff */ @@ -3285,7 +3285,7 @@ static const tc0480scp_interface hthero_tc0480scp_intf = static const tc0480scp_interface deadconx_tc0480scp_intf = { 1, 2, /* gfxnum, txnum */ - 3, /* pixels */ + 3, /* pixels */ 0x1e, 0x08, /* x_offset, y_offset */ -1, 0, /* text_xoff, text_yoff */ -1, 0, /* flip_xoff, flip_yoff */ @@ -3295,7 +3295,7 @@ static const tc0480scp_interface deadconx_tc0480scp_intf = static const tc0480scp_interface deadconxj_tc0480scp_intf = { 1, 2, /* gfxnum, txnum */ - 3, /* pixels */ + 3, /* pixels */ 0x34, -0x05, /* x_offset, y_offset */ -1, 0, /* text_xoff, text_yoff */ -1, 0, /* flip_xoff, flip_yoff */ @@ -3305,7 +3305,7 @@ static const tc0480scp_interface deadconxj_tc0480scp_intf = static const tc0480scp_interface metalb_tc0480scp_intf = { 1, 2, /* gfxnum, txnum */ - 3, /* pixels */ + 3, /* pixels */ 0x32, -0x04, /* x_offset, y_offset */ 1, 0, /* text_xoff, text_yoff */ -1, 0, /* flip_xoff, flip_yoff */ diff --git a/src/mame/drivers/taito_z.c b/src/mame/drivers/taito_z.c index af1c5bccb9b..b1a024bd951 100644 --- a/src/mame/drivers/taito_z.c +++ b/src/mame/drivers/taito_z.c @@ -2902,7 +2902,7 @@ static const tc0100scn_interface spacegun_tc0100scn_intf = static const tc0480scp_interface taitoz_tc0480scp_intf = { 1, 2, /* gfxnum, txnum */ - 0, /* pixels */ + 0, /* pixels */ 0x21, 0x08, /* x_offset, y_offset */ 4, 0, /* text_xoff, text_yoff */ 0, 0, /* flip_xoff, flip_yoff */ diff --git a/src/mame/drivers/topspeed.c b/src/mame/drivers/topspeed.c index dd03a7f7e18..7341263aaff 100644 --- a/src/mame/drivers/topspeed.c +++ b/src/mame/drivers/topspeed.c @@ -672,8 +672,8 @@ static MACHINE_RESET( topspeed ) static const pc080sn_interface topspeed_pc080sn_intf = { - 1, /* gfxnum */ - 0, 8, 0, 0 /* x_offset, y_offset, y_invert, dblwidth */ + 1, /* gfxnum */ + 0, 8, 0, 0 /* x_offset, y_offset, y_invert, dblwidth */ }; static const tc0220ioc_interface topspeed_io_intf = diff --git a/src/mame/drivers/undrfire.c b/src/mame/drivers/undrfire.c index e022fded9a6..6af5b3948b7 100644 --- a/src/mame/drivers/undrfire.c +++ b/src/mame/drivers/undrfire.c @@ -712,7 +712,7 @@ static const tc0100scn_interface undrfire_tc0100scn_intf = static const tc0480scp_interface undrfire_tc0480scp_intf = { 1, 4, /* gfxnum, txnum */ - 0, /* pixels */ + 0, /* pixels */ 0x24, 0, /* x_offset, y_offset */ -1, 0, /* text_xoff, text_yoff */ 0, 0, /* flip_xoff, flip_yoff */ diff --git a/src/mame/machine/nmk112.c b/src/mame/machine/nmk112.c index 9f7115356ea..8c06274093d 100644 --- a/src/mame/machine/nmk112.c +++ b/src/mame/machine/nmk112.c @@ -61,7 +61,7 @@ WRITE8_DEVICE_HANDLER( nmk112_okibank_w ) int size = chip ? nmk112->size1 : nmk112->size0; int bankaddr = (data * BANKSIZE) % size; - if (nmk112->current_bank[offset] == data) + if (nmk112->current_bank[offset] == data) return; nmk112->current_bank[offset] = data; @@ -99,7 +99,7 @@ static STATE_POSTLOAD( nmk112_postload_bankswitch ) { int banknum = nmk112->last_bank[i]; int paged = (nmk112->page_mask & (1 << i)); - + UINT8 *rom = i ? nmk112->rom1 : nmk112->rom0; int size = i ? nmk112->size1 : nmk112->size0; int bankaddr = (nmk112->current_bank[nmk112->last_bank[i] + i * 4] * BANKSIZE) % size; diff --git a/src/mame/machine/snes.c b/src/mame/machine/snes.c index bfc3a15bb4f..09e2484310a 100644 --- a/src/mame/machine/snes.c +++ b/src/mame/machine/snes.c @@ -178,7 +178,7 @@ static TIMER_CALLBACK( snes_scanline_tick ) timer_adjust_oneshot(snes_hirq_timer, video_screen_get_time_until_pos(machine->primary_screen, snes_ppu.beam.current_vert, pixel*snes_htmult), 0); } } - } + } /* Start of VBlank */ if( snes_ppu.beam.current_vert == snes_ppu.beam.last_visible_line ) diff --git a/src/mame/machine/tait8741.c b/src/mame/machine/tait8741.c index e7dc9eaf592..3203eace616 100644 --- a/src/mame/machine/tait8741.c +++ b/src/mame/machine/tait8741.c @@ -604,7 +604,7 @@ static INT8 cyclemb_8741_r(const address_space *space,int num,int offset) if(cyclemb_mcu.rst) { /* FIXME: mame rands are supposedly parity checks or signals that the i8741 sends to the main z80 for telling him what kind of input - this specific packet contains. DSW3 surely contains something else too... */ + this specific packet contains. DSW3 surely contains something else too... */ /* FIXME: remove cpu_get_pc hack */ switch(cpu_get_pc(space->cpu)) { diff --git a/src/mame/video/cninja.c b/src/mame/video/cninja.c index 8c26ed7c324..c6177a09ed4 100644 --- a/src/mame/video/cninja.c +++ b/src/mame/video/cninja.c @@ -200,7 +200,7 @@ static void cninjabl_draw_sprites(running_machine *machine, bitmap_t *bitmap, co y = buffered_spriteram16[offs+1]; // changed on bootleg! if (!sprite) continue; - + x = buffered_spriteram16[offs+2]; /* Sprite/playfield priority */ @@ -223,7 +223,7 @@ static void cninjabl_draw_sprites(running_machine *machine, bitmap_t *bitmap, co fy = y & 0x4000; multi = (1 << ((y & 0x0600) >> 9)) - 1; /* 1x, 2x, 4x, 8x height */ - + y -= multi*16; // changed on bootleg! y += 4; diff --git a/src/mame/video/groundfx.c b/src/mame/video/groundfx.c index 079df043be9..f53948a466c 100644 --- a/src/mame/video/groundfx.c +++ b/src/mame/video/groundfx.c @@ -257,7 +257,7 @@ VIDEO_UPDATE( groundfx ) it's contents the usual way. */ - if (tc0100scn_long_r(tc0100scn, 0x4090 / 4, 0xffffffff) || + if (tc0100scn_long_r(tc0100scn, 0x4090 / 4, 0xffffffff) || tc0480scp_long_r(tc0480scp, 0x20 / 4, 0xffffffff) == 0x240866) /* Anything in text layer - really stupid hack */ { tc0480scp_tilemap_draw(tc0480scp, bitmap, cliprect, layer[1], 0, 2); @@ -269,8 +269,8 @@ VIDEO_UPDATE( groundfx ) if (tc0480scp_long_r(tc0480scp, 0x20 / 4, 0xffffffff) != 0x240866) /* Stupid hack for start of race */ tc0480scp_tilemap_draw(tc0480scp, bitmap, &hack_cliprect, layer[0], 0, 0); draw_sprites(screen->machine, bitmap, cliprect, 1, 44, -574); - } - else + } + else { tc0480scp_tilemap_draw(tc0480scp, bitmap, cliprect, layer[0], 0, 1); tc0480scp_tilemap_draw(tc0480scp, bitmap, cliprect, layer[1], 0, 2); diff --git a/src/mame/video/hng64.c b/src/mame/video/hng64.c index 273cfbc55af..efb9aa20277 100644 --- a/src/mame/video/hng64.c +++ b/src/mame/video/hng64.c @@ -2103,7 +2103,7 @@ void recoverPolygonBlock(running_machine* machine, const UINT16* packet, struct // 24 word chunk, 3 vertices, per-vertex UVs case 0x04: // 0000 0100 case 0x0e: // 0000 1110 - case 0x24: // 0010 0100 - TODO: I'm missing a lot of geo in the driving game intros + case 0x24: // 0010 0100 - TODO: I'm missing a lot of geo in the driving game intros case 0x2e: // 0010 1110 for (m = 0; m < 3; m++) { @@ -2182,7 +2182,7 @@ void recoverPolygonBlock(running_machine* machine, const UINT16* packet, struct // 12 word chunk, 1 vertex, per-vertex UVs case 0x86: // 1000 0110 case 0x96: // 1001 0110 - case 0xb6: // 1011 0110 - TODO: I'm missing a lot of geo in the driving game intros. + case 0xb6: // 1011 0110 - TODO: I'm missing a lot of geo in the driving game intros. case 0xc6: // 1100 0110 case 0xd6: // 1101 0110 // Copy over the proper vertices from the previous triangle... @@ -2219,15 +2219,15 @@ void recoverPolygonBlock(running_machine* machine, const UINT16* packet, struct // TODO: I'm not reading 3 necessary words here (maybe face normal) !!! - /* DEBUG - printf("0x?6 : %08x (%d/%d)\n", address[k]*3*2, l, size[k]-1); - for (m = 0; m < 13; m++) - printf("%04x ", threeDPointer[m]); - printf("\n"); - for (m = 0; m < 13; m++) - printf("%3.4f ", uToF(threeDPointer[m])); - printf("\n\n"); - */ + /* DEBUG + printf("0x?6 : %08x (%d/%d)\n", address[k]*3*2, l, size[k]-1); + for (m = 0; m < 13; m++) + printf("%04x ", threeDPointer[m]); + printf("\n"); + for (m = 0; m < 13; m++) + printf("%3.4f ", uToF(threeDPointer[m])); + printf("\n\n"); + */ chunkLength = 12; break; diff --git a/src/mame/video/n64.c b/src/mame/video/n64.c index 847a969a684..4e977579d14 100644 --- a/src/mame/video/n64.c +++ b/src/mame/video/n64.c @@ -10,7 +10,7 @@ #include "driver.h" #include "includes/n64.h" -#define LOG_RDP_EXECUTION 0 +#define LOG_RDP_EXECUTION 0 static FILE *rdp_exec; @@ -1703,26 +1703,26 @@ INLINE void video_max(UINT32* Pixels, UINT8* max, UINT32* enb) /* INLINE void video_max(UINT32* Pixels, UINT8* max, UINT32* enb) { - int i; - int pos = 0; - *enb = 0; - for(i = 0; i < 7; i++) - { - if (Pixels[i] > Pixels[pos]) - { - *enb += (1 << i); - pos = i; - } - else if (Pixels[i] < Pixels[pos]) - { - *enb += (1 << i); - } - else - { - pos = i; - } - } - *max = Pixels[pos]; + int i; + int pos = 0; + *enb = 0; + for(i = 0; i < 7; i++) + { + if (Pixels[i] > Pixels[pos]) + { + *enb += (1 << i); + pos = i; + } + else if (Pixels[i] < Pixels[pos]) + { + *enb += (1 << i); + } + else + { + pos = i; + } + } + *max = Pixels[pos]; } */ @@ -2519,7 +2519,7 @@ static void render_spans_32(int start, int end, TILE* tex_tile, int shade, int t { COLOR_COMBINER2_C0(c1); COLOR_COMBINER2_C1(c2); - } + } if ((zbuffer || other_modes.z_source_sel) && other_modes.z_compare_en) { @@ -3588,7 +3588,7 @@ static RDP_COMMAND( rdp_set_other_modes ) int index; other_modes.cycle_type = (w1 >> 20) & 0x3; - other_modes.persp_tex_en = (w1 & 0x80000) ? 1 : 0; + other_modes.persp_tex_en = (w1 & 0x80000) ? 1 : 0; other_modes.detail_tex_en = (w1 & 0x40000) ? 1 : 0; other_modes.sharpen_tex_en = (w1 & 0x20000) ? 1 : 0; other_modes.tex_lod_en = (w1 & 0x10000) ? 1 : 0; @@ -4092,19 +4092,19 @@ static RDP_COMMAND( rdp_set_combine ) SET_SUB_ALPHA_INPUT(&combiner_alphaadd[1], combine.add_a1); /* - if(combiner_rgbsub_a_r[1] == &noise_color.i.r) - { - COLOR_COMBINER1 = COLOR_COMBINER1_NOISE; - COLOR_COMBINER2_C0 = COLOR_COMBINER2_C0_NOISE; - COLOR_COMBINER2_C1 = COLOR_COMBINER2_C1_NOISE; - } - else - { - COLOR_COMBINER1 = COLOR_COMBINER1_NNOISE; - COLOR_COMBINER2_C0 = COLOR_COMBINER2_C0_NNOISE; - COLOR_COMBINER2_C1 = COLOR_COMBINER2_C1_NNOISE; - } - */ + if(combiner_rgbsub_a_r[1] == &noise_color.i.r) + { + COLOR_COMBINER1 = COLOR_COMBINER1_NOISE; + COLOR_COMBINER2_C0 = COLOR_COMBINER2_C0_NOISE; + COLOR_COMBINER2_C1 = COLOR_COMBINER2_C1_NOISE; + } + else + { + COLOR_COMBINER1 = COLOR_COMBINER1_NNOISE; + COLOR_COMBINER2_C0 = COLOR_COMBINER2_C0_NNOISE; + COLOR_COMBINER2_C1 = COLOR_COMBINER2_C1_NNOISE; + } + */ } static RDP_COMMAND( rdp_set_texture_image ) @@ -4122,7 +4122,7 @@ static RDP_COMMAND( rdp_set_mask_image ) static RDP_COMMAND( rdp_set_color_image ) { - fb_format = (w1 >> 21) & 0x7; + fb_format = (w1 >> 21) & 0x7; fb_size = (w1 >> 19) & 0x3; fb_width = (w1 & 0x3ff) + 1; fb_address = w2 & 0x01ffffff; @@ -4238,23 +4238,23 @@ void rdp_process_list(running_machine *machine) //*out = cc_lut2[(cc_lut1[(*A << 16) | (*B << 8) | *C] << 8) | *D]; /* - The slow, branchy version + The slow, branchy version - INT32 color = (((*A-*B)* *C) + (*D << 8) + 0x80); - color >>= 8; - if (color > 255) - { - *out = 255; - } - else if (color < 0) - { - *out = 0; - } - else - { - *out = (UINT8)color; - } - */ + INT32 color = (((*A-*B)* *C) + (*D << 8) + 0x80); + color >>= 8; + if (color > 255) + { + *out = 255; + } + else if (color < 0) + { + *out = 0; + } + else + { + *out = (UINT8)color; + } + */ //} INLINE void BLENDER_EQUATION0_FORCE(INT32* r, INT32* g, INT32* b, int bsel_special) diff --git a/src/mame/video/ninjaw.c b/src/mame/video/ninjaw.c index eee4ae8187f..6cdcf427521 100644 --- a/src/mame/video/ninjaw.c +++ b/src/mame/video/ninjaw.c @@ -156,7 +156,7 @@ VIDEO_UPDATE( ninjaw ) nodraw = tc0100scn_tilemap_draw(tc0100scn, bitmap, cliprect, layer[0], TILEMAP_DRAW_OPAQUE, 0); /* left */ /* Ensure screen blanked even when bottom layers not drawn due to disable bit */ - if (nodraw) + if (nodraw) bitmap_fill(bitmap, cliprect, get_black_pen(screen->machine)); /* Sprites can be under/over the layer below text layer */ diff --git a/src/mame/video/rdpblend.h b/src/mame/video/rdpblend.h index a777342c9f9..73116288ab5 100644 --- a/src/mame/video/rdpblend.h +++ b/src/mame/video/rdpblend.h @@ -113,47 +113,47 @@ INLINE int BLENDER2_16_NIMR_NZC_AC_ND_NFORCE(UINT16 *fb, UINT8* hb, COLOR c1, CO static int (*rdp_blender1_16_dith_func[32])(UINT16 *, UINT8 *, COLOR, int) = { BLENDER1_16_NIMR_NZC_NDITH_NAC_NFORCE, BLENDER1_16_NIMR_NZC_NDITH_AC_NFORCE, BLENDER1_16_NIMR_NZC_DITH_NAC_NFORCE, BLENDER1_16_NIMR_NZC_DITH_AC_NFORCE, - BLENDER1_16_NIMR_ZC_NDITH_NAC_NFORCE, BLENDER1_16_NIMR_ZC_NDITH_AC_NFORCE, BLENDER1_16_NIMR_ZC_DITH_NAC_NFORCE, BLENDER1_16_NIMR_ZC_DITH_AC_NFORCE, - BLENDER1_16_IMR_NZC_NDITH_NAC_NFORCE, BLENDER1_16_IMR_NZC_NDITH_AC_NFORCE, BLENDER1_16_IMR_NZC_DITH_NAC_NFORCE, BLENDER1_16_IMR_NZC_DITH_AC_NFORCE, - BLENDER1_16_IMR_ZC_NDITH_NAC_NFORCE, BLENDER1_16_IMR_ZC_NDITH_AC_NFORCE, BLENDER1_16_IMR_ZC_DITH_NAC_NFORCE, BLENDER1_16_IMR_ZC_DITH_AC_NFORCE, + BLENDER1_16_NIMR_ZC_NDITH_NAC_NFORCE, BLENDER1_16_NIMR_ZC_NDITH_AC_NFORCE, BLENDER1_16_NIMR_ZC_DITH_NAC_NFORCE, BLENDER1_16_NIMR_ZC_DITH_AC_NFORCE, + BLENDER1_16_IMR_NZC_NDITH_NAC_NFORCE, BLENDER1_16_IMR_NZC_NDITH_AC_NFORCE, BLENDER1_16_IMR_NZC_DITH_NAC_NFORCE, BLENDER1_16_IMR_NZC_DITH_AC_NFORCE, + BLENDER1_16_IMR_ZC_NDITH_NAC_NFORCE, BLENDER1_16_IMR_ZC_NDITH_AC_NFORCE, BLENDER1_16_IMR_ZC_DITH_NAC_NFORCE, BLENDER1_16_IMR_ZC_DITH_AC_NFORCE, BLENDER1_16_NIMR_NZC_NDITH_NAC_FORCE, BLENDER1_16_NIMR_NZC_NDITH_AC_FORCE, BLENDER1_16_NIMR_NZC_DITH_NAC_FORCE, BLENDER1_16_NIMR_NZC_DITH_AC_FORCE, - BLENDER1_16_NIMR_ZC_NDITH_NAC_FORCE, BLENDER1_16_NIMR_ZC_NDITH_AC_FORCE, BLENDER1_16_NIMR_ZC_DITH_NAC_FORCE, BLENDER1_16_NIMR_ZC_DITH_AC_FORCE, - BLENDER1_16_IMR_NZC_NDITH_NAC_FORCE, BLENDER1_16_IMR_NZC_NDITH_AC_FORCE, BLENDER1_16_IMR_NZC_DITH_NAC_FORCE, BLENDER1_16_IMR_NZC_DITH_AC_FORCE, - BLENDER1_16_IMR_ZC_NDITH_NAC_FORCE, BLENDER1_16_IMR_ZC_NDITH_AC_FORCE, BLENDER1_16_IMR_ZC_DITH_NAC_FORCE, BLENDER1_16_IMR_ZC_DITH_AC_FORCE, + BLENDER1_16_NIMR_ZC_NDITH_NAC_FORCE, BLENDER1_16_NIMR_ZC_NDITH_AC_FORCE, BLENDER1_16_NIMR_ZC_DITH_NAC_FORCE, BLENDER1_16_NIMR_ZC_DITH_AC_FORCE, + BLENDER1_16_IMR_NZC_NDITH_NAC_FORCE, BLENDER1_16_IMR_NZC_NDITH_AC_FORCE, BLENDER1_16_IMR_NZC_DITH_NAC_FORCE, BLENDER1_16_IMR_NZC_DITH_AC_FORCE, + BLENDER1_16_IMR_ZC_NDITH_NAC_FORCE, BLENDER1_16_IMR_ZC_NDITH_AC_FORCE, BLENDER1_16_IMR_ZC_DITH_NAC_FORCE, BLENDER1_16_IMR_ZC_DITH_AC_FORCE, }; static int (*rdp_blender2_16_dith_func[32])(UINT16 *, UINT8 *, COLOR, COLOR, int) = { BLENDER2_16_NIMR_NZC_NDITH_NAC_NFORCE, BLENDER2_16_NIMR_NZC_NDITH_AC_NFORCE, BLENDER2_16_NIMR_NZC_DITH_NAC_NFORCE, BLENDER2_16_NIMR_NZC_DITH_AC_NFORCE, - BLENDER2_16_NIMR_ZC_NDITH_NAC_NFORCE, BLENDER2_16_NIMR_ZC_NDITH_AC_NFORCE, BLENDER2_16_NIMR_ZC_DITH_NAC_NFORCE, BLENDER2_16_NIMR_ZC_DITH_AC_NFORCE, - BLENDER2_16_IMR_NZC_NDITH_NAC_NFORCE, BLENDER2_16_IMR_NZC_NDITH_AC_NFORCE, BLENDER2_16_IMR_NZC_DITH_NAC_NFORCE, BLENDER2_16_IMR_NZC_DITH_AC_NFORCE, - BLENDER2_16_IMR_ZC_NDITH_NAC_NFORCE, BLENDER2_16_IMR_ZC_NDITH_AC_NFORCE, BLENDER2_16_IMR_ZC_DITH_NAC_NFORCE, BLENDER2_16_IMR_ZC_DITH_AC_NFORCE, + BLENDER2_16_NIMR_ZC_NDITH_NAC_NFORCE, BLENDER2_16_NIMR_ZC_NDITH_AC_NFORCE, BLENDER2_16_NIMR_ZC_DITH_NAC_NFORCE, BLENDER2_16_NIMR_ZC_DITH_AC_NFORCE, + BLENDER2_16_IMR_NZC_NDITH_NAC_NFORCE, BLENDER2_16_IMR_NZC_NDITH_AC_NFORCE, BLENDER2_16_IMR_NZC_DITH_NAC_NFORCE, BLENDER2_16_IMR_NZC_DITH_AC_NFORCE, + BLENDER2_16_IMR_ZC_NDITH_NAC_NFORCE, BLENDER2_16_IMR_ZC_NDITH_AC_NFORCE, BLENDER2_16_IMR_ZC_DITH_NAC_NFORCE, BLENDER2_16_IMR_ZC_DITH_AC_NFORCE, BLENDER2_16_NIMR_NZC_NDITH_NAC_FORCE, BLENDER2_16_NIMR_NZC_NDITH_AC_FORCE, BLENDER2_16_NIMR_NZC_DITH_NAC_FORCE, BLENDER2_16_NIMR_NZC_DITH_AC_FORCE, - BLENDER2_16_NIMR_ZC_NDITH_NAC_FORCE, BLENDER2_16_NIMR_ZC_NDITH_AC_FORCE, BLENDER2_16_NIMR_ZC_DITH_NAC_FORCE, BLENDER2_16_NIMR_ZC_DITH_AC_FORCE, - BLENDER2_16_IMR_NZC_NDITH_NAC_FORCE, BLENDER2_16_IMR_NZC_NDITH_AC_FORCE, BLENDER2_16_IMR_NZC_DITH_NAC_FORCE, BLENDER2_16_IMR_NZC_DITH_AC_FORCE, - BLENDER2_16_IMR_ZC_NDITH_NAC_FORCE, BLENDER2_16_IMR_ZC_NDITH_AC_FORCE, BLENDER2_16_IMR_ZC_DITH_NAC_FORCE, BLENDER2_16_IMR_ZC_DITH_AC_FORCE, + BLENDER2_16_NIMR_ZC_NDITH_NAC_FORCE, BLENDER2_16_NIMR_ZC_NDITH_AC_FORCE, BLENDER2_16_NIMR_ZC_DITH_NAC_FORCE, BLENDER2_16_NIMR_ZC_DITH_AC_FORCE, + BLENDER2_16_IMR_NZC_NDITH_NAC_FORCE, BLENDER2_16_IMR_NZC_NDITH_AC_FORCE, BLENDER2_16_IMR_NZC_DITH_NAC_FORCE, BLENDER2_16_IMR_NZC_DITH_AC_FORCE, + BLENDER2_16_IMR_ZC_NDITH_NAC_FORCE, BLENDER2_16_IMR_ZC_NDITH_AC_FORCE, BLENDER2_16_IMR_ZC_DITH_NAC_FORCE, BLENDER2_16_IMR_ZC_DITH_AC_FORCE, }; static int (*rdp_blender1_16_ndith_func[16])(UINT16 *, UINT8 *, COLOR) = { BLENDER1_16_NIMR_NZC_NAC_ND_NFORCE, BLENDER1_16_NIMR_NZC_AC_ND_NFORCE, - BLENDER1_16_NIMR_ZC_NAC_ND_NFORCE, BLENDER1_16_NIMR_ZC_AC_ND_NFORCE, - BLENDER1_16_IMR_NZC_NAC_ND_NFORCE, BLENDER1_16_IMR_NZC_AC_ND_NFORCE, - BLENDER1_16_IMR_ZC_NAC_ND_NFORCE, BLENDER1_16_IMR_ZC_AC_ND_NFORCE, + BLENDER1_16_NIMR_ZC_NAC_ND_NFORCE, BLENDER1_16_NIMR_ZC_AC_ND_NFORCE, + BLENDER1_16_IMR_NZC_NAC_ND_NFORCE, BLENDER1_16_IMR_NZC_AC_ND_NFORCE, + BLENDER1_16_IMR_ZC_NAC_ND_NFORCE, BLENDER1_16_IMR_ZC_AC_ND_NFORCE, BLENDER1_16_NIMR_NZC_NAC_ND_FORCE, BLENDER1_16_NIMR_NZC_AC_ND_FORCE, - BLENDER1_16_NIMR_ZC_NAC_ND_FORCE, BLENDER1_16_NIMR_ZC_AC_ND_FORCE, - BLENDER1_16_IMR_NZC_NAC_ND_FORCE, BLENDER1_16_IMR_NZC_AC_ND_FORCE, - BLENDER1_16_IMR_ZC_NAC_ND_FORCE, BLENDER1_16_IMR_ZC_AC_ND_FORCE, + BLENDER1_16_NIMR_ZC_NAC_ND_FORCE, BLENDER1_16_NIMR_ZC_AC_ND_FORCE, + BLENDER1_16_IMR_NZC_NAC_ND_FORCE, BLENDER1_16_IMR_NZC_AC_ND_FORCE, + BLENDER1_16_IMR_ZC_NAC_ND_FORCE, BLENDER1_16_IMR_ZC_AC_ND_FORCE, }; static int (*rdp_blender2_16_ndith_func[16])(UINT16 *, UINT8 *, COLOR, COLOR) = { BLENDER2_16_NIMR_NZC_NAC_ND_NFORCE, BLENDER2_16_NIMR_NZC_AC_ND_NFORCE, - BLENDER2_16_NIMR_ZC_NAC_ND_NFORCE, BLENDER2_16_NIMR_ZC_AC_ND_NFORCE, - BLENDER2_16_IMR_NZC_NAC_ND_NFORCE, BLENDER2_16_IMR_NZC_AC_ND_NFORCE, - BLENDER2_16_IMR_ZC_NAC_ND_NFORCE, BLENDER2_16_IMR_ZC_AC_ND_NFORCE, + BLENDER2_16_NIMR_ZC_NAC_ND_NFORCE, BLENDER2_16_NIMR_ZC_AC_ND_NFORCE, + BLENDER2_16_IMR_NZC_NAC_ND_NFORCE, BLENDER2_16_IMR_NZC_AC_ND_NFORCE, + BLENDER2_16_IMR_ZC_NAC_ND_NFORCE, BLENDER2_16_IMR_ZC_AC_ND_NFORCE, BLENDER2_16_NIMR_NZC_NAC_ND_FORCE, BLENDER2_16_NIMR_NZC_AC_ND_FORCE, - BLENDER2_16_NIMR_ZC_NAC_ND_FORCE, BLENDER2_16_NIMR_ZC_AC_ND_FORCE, - BLENDER2_16_IMR_NZC_NAC_ND_FORCE, BLENDER2_16_IMR_NZC_AC_ND_FORCE, - BLENDER2_16_IMR_ZC_NAC_ND_FORCE, BLENDER2_16_IMR_ZC_AC_ND_FORCE, + BLENDER2_16_NIMR_ZC_NAC_ND_FORCE, BLENDER2_16_NIMR_ZC_AC_ND_FORCE, + BLENDER2_16_IMR_NZC_NAC_ND_FORCE, BLENDER2_16_IMR_NZC_AC_ND_FORCE, + BLENDER2_16_IMR_ZC_NAC_ND_FORCE, BLENDER2_16_IMR_ZC_AC_ND_FORCE, }; diff --git a/src/mame/video/rdpcc.c b/src/mame/video/rdpcc.c index 828cf0dfea0..585cd88f462 100644 --- a/src/mame/video/rdpcc.c +++ b/src/mame/video/rdpcc.c @@ -1,14 +1,14 @@ /* #if defined(NOISE) - #define COLOR_COMBINER1_NOISE(color) - noise_color.i.r = rdp_rand(); - noise_color.i.g = rdp_rand(); - noise_color.i.b = rdp_rand(); - color.i.r = COMBINER_EQUATION(*combiner_rgbsub_a_r[1],*combiner_rgbsub_b_r[1],*combiner_rgbmul_r[1],*combiner_rgbadd_r[1]); - color.i.g = COMBINER_EQUATION(*combiner_rgbsub_a_g[1],*combiner_rgbsub_b_g[1],*combiner_rgbmul_g[1],*combiner_rgbadd_g[1]); - color.i.b = COMBINER_EQUATION(*combiner_rgbsub_a_b[1],*combiner_rgbsub_b_b[1],*combiner_rgbmul_b[1],*combiner_rgbadd_b[1]); - color.i.a = COMBINER_EQUATION(*combiner_alphasub_a[1],*combiner_alphasub_b[1],*combiner_alphamul[1],*combiner_alphaadd[1]); - alpha_cvg_get(&color.i.a); + #define COLOR_COMBINER1_NOISE(color) + noise_color.i.r = rdp_rand(); + noise_color.i.g = rdp_rand(); + noise_color.i.b = rdp_rand(); + color.i.r = COMBINER_EQUATION(*combiner_rgbsub_a_r[1],*combiner_rgbsub_b_r[1],*combiner_rgbmul_r[1],*combiner_rgbadd_r[1]); + color.i.g = COMBINER_EQUATION(*combiner_rgbsub_a_g[1],*combiner_rgbsub_b_g[1],*combiner_rgbmul_g[1],*combiner_rgbadd_g[1]); + color.i.b = COMBINER_EQUATION(*combiner_rgbsub_a_b[1],*combiner_rgbsub_b_b[1],*combiner_rgbmul_b[1],*combiner_rgbadd_b[1]); + color.i.a = COMBINER_EQUATION(*combiner_alphasub_a[1],*combiner_alphasub_b[1],*combiner_alphamul[1],*combiner_alphaadd[1]); + alpha_cvg_get(&color.i.a); #else*/ #define COLOR_COMBINER1(color) \ color.i.r = COMBINER_EQUATION(*combiner_rgbsub_a_r[1],*combiner_rgbsub_b_r[1],*combiner_rgbmul_r[1],*combiner_rgbadd_r[1]); \ @@ -20,15 +20,15 @@ /* #if defined(NOISE) - #define COLOR_COMBINER2_C0_NOISE(color) - noise_color.i.r = rdp_rand(); - noise_color.i.g = rdp_rand(); - noise_color.i.b = rdp_rand(); - color.i.r = COMBINER_EQUATION(*combiner_rgbsub_a_r[0],*combiner_rgbsub_b_r[0],*combiner_rgbmul_r[0],*combiner_rgbadd_r[0]); - color.i.g = COMBINER_EQUATION(*combiner_rgbsub_a_g[0],*combiner_rgbsub_b_g[0],*combiner_rgbmul_g[0],*combiner_rgbadd_g[0]); - color.i.b = COMBINER_EQUATION(*combiner_rgbsub_a_b[0],*combiner_rgbsub_b_b[0],*combiner_rgbmul_b[0],*combiner_rgbadd_b[0]); - color.i.a = COMBINER_EQUATION(*combiner_alphasub_a[0],*combiner_alphasub_b[0],*combiner_alphamul[0],*combiner_alphaadd[0]); - combined_color.c = color.c; + #define COLOR_COMBINER2_C0_NOISE(color) + noise_color.i.r = rdp_rand(); + noise_color.i.g = rdp_rand(); + noise_color.i.b = rdp_rand(); + color.i.r = COMBINER_EQUATION(*combiner_rgbsub_a_r[0],*combiner_rgbsub_b_r[0],*combiner_rgbmul_r[0],*combiner_rgbadd_r[0]); + color.i.g = COMBINER_EQUATION(*combiner_rgbsub_a_g[0],*combiner_rgbsub_b_g[0],*combiner_rgbmul_g[0],*combiner_rgbadd_g[0]); + color.i.b = COMBINER_EQUATION(*combiner_rgbsub_a_b[0],*combiner_rgbsub_b_b[0],*combiner_rgbmul_b[0],*combiner_rgbadd_b[0]); + color.i.a = COMBINER_EQUATION(*combiner_alphasub_a[0],*combiner_alphasub_b[0],*combiner_alphamul[0],*combiner_alphaadd[0]); + combined_color.c = color.c; #else*/ #define COLOR_COMBINER2_C0(color) \ color.i.r = COMBINER_EQUATION(*combiner_rgbsub_a_r[0],*combiner_rgbsub_b_r[0],*combiner_rgbmul_r[0],*combiner_rgbadd_r[0]); \ @@ -40,18 +40,18 @@ /*#if defined(NOISE) - #define COLOR_COMBINER2_C1_NOISE(color) - color.c = texel0_color.c; - texel0_color.c = texel1_color.c; - texel1_color.c = color.c; - noise_color.i.r = rdp_rand(); - noise_color.i.g = rdp_rand(); - noise_color.i.b = rdp_rand(); - color.i.r = COMBINER_EQUATION(*combiner_rgbsub_a_r[1],*combiner_rgbsub_b_r[1],*combiner_rgbmul_r[1],*combiner_rgbadd_r[1]); - color.i.g = COMBINER_EQUATION(*combiner_rgbsub_a_g[1],*combiner_rgbsub_b_g[1],*combiner_rgbmul_g[1],*combiner_rgbadd_g[1]); - color.i.b = COMBINER_EQUATION(*combiner_rgbsub_a_b[1],*combiner_rgbsub_b_b[1],*combiner_rgbmul_b[1],*combiner_rgbadd_b[1]); - color.i.a = COMBINER_EQUATION(*combiner_alphasub_a[1],*combiner_alphasub_b[1],*combiner_alphamul[1],*combiner_alphaadd[1]); - alpha_cvg_get(&color.i.a); + #define COLOR_COMBINER2_C1_NOISE(color) + color.c = texel0_color.c; + texel0_color.c = texel1_color.c; + texel1_color.c = color.c; + noise_color.i.r = rdp_rand(); + noise_color.i.g = rdp_rand(); + noise_color.i.b = rdp_rand(); + color.i.r = COMBINER_EQUATION(*combiner_rgbsub_a_r[1],*combiner_rgbsub_b_r[1],*combiner_rgbmul_r[1],*combiner_rgbadd_r[1]); + color.i.g = COMBINER_EQUATION(*combiner_rgbsub_a_g[1],*combiner_rgbsub_b_g[1],*combiner_rgbmul_g[1],*combiner_rgbadd_g[1]); + color.i.b = COMBINER_EQUATION(*combiner_rgbsub_a_b[1],*combiner_rgbsub_b_b[1],*combiner_rgbmul_b[1],*combiner_rgbadd_b[1]); + color.i.a = COMBINER_EQUATION(*combiner_alphasub_a[1],*combiner_alphasub_b[1],*combiner_alphamul[1],*combiner_alphaadd[1]); + alpha_cvg_get(&color.i.a); #else*/ #define COLOR_COMBINER2_C1(color) \ color.c = texel0_color.c; \ diff --git a/src/mame/video/rdpclamp.h b/src/mame/video/rdpclamp.h index 77339731fa4..dfd277a36eb 100644 --- a/src/mame/video/rdpclamp.h +++ b/src/mame/video/rdpclamp.h @@ -19,18 +19,18 @@ INLINE void CLAMP_QUICK_C(INT32* S, INT32* T, INT32 maxs, INT32 maxt, int num); static void (*rdp_clamp_func[8])(INT32*, INT32*, INT32*, INT32*, INT32, INT32, TILE*) = { - CLAMP_NC_NDOS_NDOT, CLAMP_NC_NDOS_DOT, CLAMP_NC_DOS_NDOT, CLAMP_NC_DOS_DOT, + CLAMP_NC_NDOS_NDOT, CLAMP_NC_NDOS_DOT, CLAMP_NC_DOS_NDOT, CLAMP_NC_DOS_DOT, CLAMP_C, CLAMP_C, CLAMP_C, CLAMP_C, }; static void (*rdp_clamp_light_func[8])(INT32*, INT32*, INT32, INT32, TILE*) = { - CLAMP_LIGHT_NC_NDOS_NDOT, CLAMP_LIGHT_NC_NDOS_DOT, CLAMP_LIGHT_NC_DOS_NDOT, CLAMP_LIGHT_NC_DOS_DOT, + CLAMP_LIGHT_NC_NDOS_NDOT, CLAMP_LIGHT_NC_NDOS_DOT, CLAMP_LIGHT_NC_DOS_NDOT, CLAMP_LIGHT_NC_DOS_DOT, CLAMP_LIGHT_C, CLAMP_LIGHT_C, CLAMP_LIGHT_C, CLAMP_LIGHT_C, }; static void (*rdp_clamp_quick_func[8])(INT32*, INT32*, INT32, INT32, int) = { - CLAMP_QUICK_NC_NDOS_NDOT, CLAMP_QUICK_NC_NDOS_DOT, CLAMP_QUICK_NC_DOS_NDOT, CLAMP_QUICK_NC_DOS_DOT, + CLAMP_QUICK_NC_NDOS_NDOT, CLAMP_QUICK_NC_NDOS_DOT, CLAMP_QUICK_NC_DOS_NDOT, CLAMP_QUICK_NC_DOS_DOT, CLAMP_QUICK_C, CLAMP_QUICK_C, CLAMP_QUICK_C, CLAMP_QUICK_C, }; diff --git a/src/mame/video/rdpfetch.h b/src/mame/video/rdpfetch.h index 60f3a756a8f..56c54fbd641 100644 --- a/src/mame/video/rdpfetch.h +++ b/src/mame/video/rdpfetch.h @@ -41,41 +41,41 @@ static UINT32 (*rdp_fetch_texel_func[128])(UINT32, UINT32) = { // 4-bit accessors FETCH_TEXEL_RGBA4_TLUT_NEN, FETCH_TEXEL_RGBA4_TLUT_NEN, FETCH_TEXEL_RGBA4_TLUT_EN0, FETCH_TEXEL_RGBA4_TLUT_EN1, - FETCH_TEXEL_INVALID, FETCH_TEXEL_INVALID, FETCH_TEXEL_INVALID, FETCH_TEXEL_INVALID, - FETCH_TEXEL_CI4_TLUT_NEN, FETCH_TEXEL_CI4_TLUT_NEN, FETCH_TEXEL_CI4_TLUT_EN0, FETCH_TEXEL_CI4_TLUT_EN1, + FETCH_TEXEL_INVALID, FETCH_TEXEL_INVALID, FETCH_TEXEL_INVALID, FETCH_TEXEL_INVALID, + FETCH_TEXEL_CI4_TLUT_NEN, FETCH_TEXEL_CI4_TLUT_NEN, FETCH_TEXEL_CI4_TLUT_EN0, FETCH_TEXEL_CI4_TLUT_EN1, FETCH_TEXEL_IA4_TLUT_NEN, FETCH_TEXEL_IA4_TLUT_NEN, FETCH_TEXEL_IA4_TLUT_EN0, FETCH_TEXEL_IA4_TLUT_EN1, FETCH_TEXEL_I4_TLUT_NEN, FETCH_TEXEL_I4_TLUT_NEN, FETCH_TEXEL_I4_TLUT_EN0, FETCH_TEXEL_I4_TLUT_EN1, - FETCH_TEXEL_INVALID, FETCH_TEXEL_INVALID, FETCH_TEXEL_INVALID, FETCH_TEXEL_INVALID, - FETCH_TEXEL_INVALID, FETCH_TEXEL_INVALID, FETCH_TEXEL_INVALID, FETCH_TEXEL_INVALID, - FETCH_TEXEL_INVALID, FETCH_TEXEL_INVALID, FETCH_TEXEL_INVALID, FETCH_TEXEL_INVALID, + FETCH_TEXEL_INVALID, FETCH_TEXEL_INVALID, FETCH_TEXEL_INVALID, FETCH_TEXEL_INVALID, + FETCH_TEXEL_INVALID, FETCH_TEXEL_INVALID, FETCH_TEXEL_INVALID, FETCH_TEXEL_INVALID, + FETCH_TEXEL_INVALID, FETCH_TEXEL_INVALID, FETCH_TEXEL_INVALID, FETCH_TEXEL_INVALID, // 8-bit accessors FETCH_TEXEL_RGBA8_TLUT_NEN, FETCH_TEXEL_RGBA8_TLUT_NEN, FETCH_TEXEL_RGBA8_TLUT_EN0, FETCH_TEXEL_RGBA8_TLUT_EN1, - FETCH_TEXEL_INVALID, FETCH_TEXEL_INVALID, FETCH_TEXEL_INVALID, FETCH_TEXEL_INVALID, - FETCH_TEXEL_CI8_TLUT_NEN, FETCH_TEXEL_CI8_TLUT_NEN, FETCH_TEXEL_CI8_TLUT_EN0, FETCH_TEXEL_CI8_TLUT_EN1, + FETCH_TEXEL_INVALID, FETCH_TEXEL_INVALID, FETCH_TEXEL_INVALID, FETCH_TEXEL_INVALID, + FETCH_TEXEL_CI8_TLUT_NEN, FETCH_TEXEL_CI8_TLUT_NEN, FETCH_TEXEL_CI8_TLUT_EN0, FETCH_TEXEL_CI8_TLUT_EN1, FETCH_TEXEL_IA8_TLUT_NEN, FETCH_TEXEL_IA8_TLUT_NEN, FETCH_TEXEL_IA8_TLUT_EN0, FETCH_TEXEL_IA8_TLUT_EN1, FETCH_TEXEL_I8_TLUT_NEN, FETCH_TEXEL_I8_TLUT_NEN, FETCH_TEXEL_I8_TLUT_EN0, FETCH_TEXEL_I8_TLUT_EN1, - FETCH_TEXEL_INVALID, FETCH_TEXEL_INVALID, FETCH_TEXEL_INVALID, FETCH_TEXEL_INVALID, - FETCH_TEXEL_INVALID, FETCH_TEXEL_INVALID, FETCH_TEXEL_INVALID, FETCH_TEXEL_INVALID, - FETCH_TEXEL_INVALID, FETCH_TEXEL_INVALID, FETCH_TEXEL_INVALID, FETCH_TEXEL_INVALID, + FETCH_TEXEL_INVALID, FETCH_TEXEL_INVALID, FETCH_TEXEL_INVALID, FETCH_TEXEL_INVALID, + FETCH_TEXEL_INVALID, FETCH_TEXEL_INVALID, FETCH_TEXEL_INVALID, FETCH_TEXEL_INVALID, + FETCH_TEXEL_INVALID, FETCH_TEXEL_INVALID, FETCH_TEXEL_INVALID, FETCH_TEXEL_INVALID, // 16-bit accessors FETCH_TEXEL_RGBA16_TLUT_NEN,FETCH_TEXEL_RGBA16_TLUT_NEN,FETCH_TEXEL_RGBA16_TLUT_EN0,FETCH_TEXEL_RGBA16_TLUT_EN1, - FETCH_TEXEL_YUV16, FETCH_TEXEL_YUV16, FETCH_TEXEL_YUV16, FETCH_TEXEL_YUV16, - FETCH_TEXEL_CI16_TLUT_NEN, FETCH_TEXEL_CI16_TLUT_NEN, FETCH_TEXEL_CI16_TLUT_EN0, FETCH_TEXEL_CI16_TLUT_EN1, + FETCH_TEXEL_YUV16, FETCH_TEXEL_YUV16, FETCH_TEXEL_YUV16, FETCH_TEXEL_YUV16, + FETCH_TEXEL_CI16_TLUT_NEN, FETCH_TEXEL_CI16_TLUT_NEN, FETCH_TEXEL_CI16_TLUT_EN0, FETCH_TEXEL_CI16_TLUT_EN1, FETCH_TEXEL_IA16_TLUT_NEN, FETCH_TEXEL_IA16_TLUT_NEN, FETCH_TEXEL_IA16_TLUT_EN0, FETCH_TEXEL_IA16_TLUT_EN1, FETCH_TEXEL_INVALID, FETCH_TEXEL_INVALID, FETCH_TEXEL_INVALID, FETCH_TEXEL_INVALID, - FETCH_TEXEL_INVALID, FETCH_TEXEL_INVALID, FETCH_TEXEL_INVALID, FETCH_TEXEL_INVALID, - FETCH_TEXEL_INVALID, FETCH_TEXEL_INVALID, FETCH_TEXEL_INVALID, FETCH_TEXEL_INVALID, - FETCH_TEXEL_INVALID, FETCH_TEXEL_INVALID, FETCH_TEXEL_INVALID, FETCH_TEXEL_INVALID, + FETCH_TEXEL_INVALID, FETCH_TEXEL_INVALID, FETCH_TEXEL_INVALID, FETCH_TEXEL_INVALID, + FETCH_TEXEL_INVALID, FETCH_TEXEL_INVALID, FETCH_TEXEL_INVALID, FETCH_TEXEL_INVALID, + FETCH_TEXEL_INVALID, FETCH_TEXEL_INVALID, FETCH_TEXEL_INVALID, FETCH_TEXEL_INVALID, // 32-bit accessors FETCH_TEXEL_RGBA32_TLUT_NEN,FETCH_TEXEL_RGBA32_TLUT_NEN,FETCH_TEXEL_RGBA32_TLUT_EN0,FETCH_TEXEL_RGBA32_TLUT_EN1, - FETCH_TEXEL_INVALID, FETCH_TEXEL_INVALID, FETCH_TEXEL_INVALID, FETCH_TEXEL_INVALID, - FETCH_TEXEL_INVALID, FETCH_TEXEL_INVALID, FETCH_TEXEL_INVALID, FETCH_TEXEL_INVALID, FETCH_TEXEL_INVALID, FETCH_TEXEL_INVALID, FETCH_TEXEL_INVALID, FETCH_TEXEL_INVALID, FETCH_TEXEL_INVALID, FETCH_TEXEL_INVALID, FETCH_TEXEL_INVALID, FETCH_TEXEL_INVALID, - FETCH_TEXEL_INVALID, FETCH_TEXEL_INVALID, FETCH_TEXEL_INVALID, FETCH_TEXEL_INVALID, - FETCH_TEXEL_INVALID, FETCH_TEXEL_INVALID, FETCH_TEXEL_INVALID, FETCH_TEXEL_INVALID, - FETCH_TEXEL_INVALID, FETCH_TEXEL_INVALID, FETCH_TEXEL_INVALID, FETCH_TEXEL_INVALID, + FETCH_TEXEL_INVALID, FETCH_TEXEL_INVALID, FETCH_TEXEL_INVALID, FETCH_TEXEL_INVALID, + FETCH_TEXEL_INVALID, FETCH_TEXEL_INVALID, FETCH_TEXEL_INVALID, FETCH_TEXEL_INVALID, + FETCH_TEXEL_INVALID, FETCH_TEXEL_INVALID, FETCH_TEXEL_INVALID, FETCH_TEXEL_INVALID, + FETCH_TEXEL_INVALID, FETCH_TEXEL_INVALID, FETCH_TEXEL_INVALID, FETCH_TEXEL_INVALID, + FETCH_TEXEL_INVALID, FETCH_TEXEL_INVALID, FETCH_TEXEL_INVALID, FETCH_TEXEL_INVALID, }; diff --git a/src/mame/video/rdpfrect.h b/src/mame/video/rdpfrect.h index 469edb9f81c..ef197e51388 100644 --- a/src/mame/video/rdpfrect.h +++ b/src/mame/video/rdpfrect.h @@ -11,6 +11,6 @@ static void (*rdp_fill_rectangle_16bit_func[16])(RECTANGLE *) = { fill_rectangle_16bit_c1_dm, fill_rectangle_16bit_c1_db, fill_rectangle_16bit_c1_dn, fill_rectangle_16bit_c1_dn, fill_rectangle_16bit_c2_dm, fill_rectangle_16bit_c2_db, fill_rectangle_16bit_c2_dn, fill_rectangle_16bit_c2_dn, - fill_rectangle_16bit_cc, fill_rectangle_16bit_cc, fill_rectangle_16bit_cc, fill_rectangle_16bit_cc, - fill_rectangle_16bit_cf, fill_rectangle_16bit_cf, fill_rectangle_16bit_cf, fill_rectangle_16bit_cf, + fill_rectangle_16bit_cc, fill_rectangle_16bit_cc, fill_rectangle_16bit_cc, fill_rectangle_16bit_cc, + fill_rectangle_16bit_cf, fill_rectangle_16bit_cf, fill_rectangle_16bit_cf, fill_rectangle_16bit_cf, }; diff --git a/src/mame/video/rdpspn16.h b/src/mame/video/rdpspn16.h index 239bf0eabe9..2f4734a93b3 100644 --- a/src/mame/video/rdpspn16.h +++ b/src/mame/video/rdpspn16.h @@ -396,275 +396,275 @@ static void render_spans_16_c2_s_t_z_f_zc_zu_dn(int start, int end, TILE* tex_ti static void (*rdp_render_spans_16_func[512])(int, int, TILE*) = { - render_spans_16_c1_ns_nt_nz_nf_nzc_dm, render_spans_16_c2_ns_nt_nz_nf_nzc_dm, - render_spans_16_c1_ns_nt_z_nf_nzc_dm, render_spans_16_c2_ns_nt_z_nf_nzc_dm, - render_spans_16_c1_ns_t_nz_nf_nzc_dm, render_spans_16_c2_ns_t_nz_nf_nzc_dm, - render_spans_16_c1_ns_t_z_nf_nzc_dm, render_spans_16_c2_ns_t_z_nf_nzc_dm, - render_spans_16_c1_s_nt_nz_nf_nzc_dm, render_spans_16_c2_s_nt_nz_nf_nzc_dm, - render_spans_16_c1_s_nt_z_nf_nzc_dm, render_spans_16_c2_s_nt_z_nf_nzc_dm, - render_spans_16_c1_s_t_nz_nf_nzc_dm, render_spans_16_c2_s_t_nz_nf_nzc_dm, + render_spans_16_c1_ns_nt_nz_nf_nzc_dm, render_spans_16_c2_ns_nt_nz_nf_nzc_dm, + render_spans_16_c1_ns_nt_z_nf_nzc_dm, render_spans_16_c2_ns_nt_z_nf_nzc_dm, + render_spans_16_c1_ns_t_nz_nf_nzc_dm, render_spans_16_c2_ns_t_nz_nf_nzc_dm, + render_spans_16_c1_ns_t_z_nf_nzc_dm, render_spans_16_c2_ns_t_z_nf_nzc_dm, + render_spans_16_c1_s_nt_nz_nf_nzc_dm, render_spans_16_c2_s_nt_nz_nf_nzc_dm, + render_spans_16_c1_s_nt_z_nf_nzc_dm, render_spans_16_c2_s_nt_z_nf_nzc_dm, + render_spans_16_c1_s_t_nz_nf_nzc_dm, render_spans_16_c2_s_t_nz_nf_nzc_dm, render_spans_16_c1_s_t_z_nf_nzc_dm, render_spans_16_c2_s_t_z_nf_nzc_dm, - render_spans_16_c1_ns_nt_nz_f_nzc_dm, render_spans_16_c2_ns_nt_nz_f_nzc_dm, - render_spans_16_c1_ns_nt_z_f_nzc_dm, render_spans_16_c2_ns_nt_z_f_nzc_dm, - render_spans_16_c1_ns_t_nz_f_nzc_dm, render_spans_16_c2_ns_t_nz_f_nzc_dm, + render_spans_16_c1_ns_nt_nz_f_nzc_dm, render_spans_16_c2_ns_nt_nz_f_nzc_dm, + render_spans_16_c1_ns_nt_z_f_nzc_dm, render_spans_16_c2_ns_nt_z_f_nzc_dm, + render_spans_16_c1_ns_t_nz_f_nzc_dm, render_spans_16_c2_ns_t_nz_f_nzc_dm, render_spans_16_c1_ns_t_z_f_nzc_dm, render_spans_16_c2_ns_t_z_f_nzc_dm, - render_spans_16_c1_s_nt_nz_f_nzc_dm, render_spans_16_c2_s_nt_nz_f_nzc_dm, + render_spans_16_c1_s_nt_nz_f_nzc_dm, render_spans_16_c2_s_nt_nz_f_nzc_dm, render_spans_16_c1_s_nt_z_f_nzc_dm, render_spans_16_c2_s_nt_z_f_nzc_dm, render_spans_16_c1_s_t_nz_f_nzc_dm, render_spans_16_c2_s_t_nz_f_nzc_dm, - render_spans_16_c1_s_t_z_f_nzc_dm, render_spans_16_c2_s_t_z_f_nzc_dm, + render_spans_16_c1_s_t_z_f_nzc_dm, render_spans_16_c2_s_t_z_f_nzc_dm, render_spans_16_c1_ns_nt_nz_nf_zc_dm, render_spans_16_c2_ns_nt_nz_nf_zc_dm, - render_spans_16_c1_ns_nt_z_nf_zc_dm, render_spans_16_c2_ns_nt_z_nf_zc_dm, - render_spans_16_c1_ns_t_nz_nf_zc_dm, render_spans_16_c2_ns_t_nz_nf_zc_dm, + render_spans_16_c1_ns_nt_z_nf_zc_dm, render_spans_16_c2_ns_nt_z_nf_zc_dm, + render_spans_16_c1_ns_t_nz_nf_zc_dm, render_spans_16_c2_ns_t_nz_nf_zc_dm, render_spans_16_c1_ns_t_z_nf_zc_dm, render_spans_16_c2_ns_t_z_nf_zc_dm, - render_spans_16_c1_s_nt_nz_nf_zc_dm, render_spans_16_c2_s_nt_nz_nf_zc_dm, + render_spans_16_c1_s_nt_nz_nf_zc_dm, render_spans_16_c2_s_nt_nz_nf_zc_dm, render_spans_16_c1_s_nt_z_nf_zc_dm, render_spans_16_c2_s_nt_z_nf_zc_dm, render_spans_16_c1_s_t_nz_nf_zc_dm, render_spans_16_c2_s_t_nz_nf_zc_dm, - render_spans_16_c1_s_t_z_nf_zc_dm, render_spans_16_c2_s_t_z_nf_zc_dm, - render_spans_16_c1_ns_nt_nz_f_zc_dm, render_spans_16_c2_ns_nt_nz_f_zc_dm, + render_spans_16_c1_s_t_z_nf_zc_dm, render_spans_16_c2_s_t_z_nf_zc_dm, + render_spans_16_c1_ns_nt_nz_f_zc_dm, render_spans_16_c2_ns_nt_nz_f_zc_dm, render_spans_16_c1_ns_nt_z_f_zc_dm, render_spans_16_c2_ns_nt_z_f_zc_dm, render_spans_16_c1_ns_t_nz_f_zc_dm, render_spans_16_c2_ns_t_nz_f_zc_dm, - render_spans_16_c1_ns_t_z_f_zc_dm, render_spans_16_c2_ns_t_z_f_zc_dm, + render_spans_16_c1_ns_t_z_f_zc_dm, render_spans_16_c2_ns_t_z_f_zc_dm, render_spans_16_c1_s_nt_nz_f_zc_dm, render_spans_16_c2_s_nt_nz_f_zc_dm, - render_spans_16_c1_s_nt_z_f_zc_dm, render_spans_16_c2_s_nt_z_f_zc_dm, - render_spans_16_c1_s_t_nz_f_zc_dm, render_spans_16_c2_s_t_nz_f_zc_dm, - render_spans_16_c1_s_t_z_f_zc_dm, render_spans_16_c2_s_t_z_f_zc_dm, + render_spans_16_c1_s_nt_z_f_zc_dm, render_spans_16_c2_s_nt_z_f_zc_dm, + render_spans_16_c1_s_t_nz_f_zc_dm, render_spans_16_c2_s_t_nz_f_zc_dm, + render_spans_16_c1_s_t_z_f_zc_dm, render_spans_16_c2_s_t_z_f_zc_dm, - render_spans_16_c1_ns_nt_nz_nf_nzc_zu_dm, render_spans_16_c2_ns_nt_nz_nf_nzc_zu_dm, - render_spans_16_c1_ns_nt_z_nf_nzc_zu_dm, render_spans_16_c2_ns_nt_z_nf_nzc_zu_dm, - render_spans_16_c1_ns_t_nz_nf_nzc_zu_dm, render_spans_16_c2_ns_t_nz_nf_nzc_zu_dm, + render_spans_16_c1_ns_nt_nz_nf_nzc_zu_dm, render_spans_16_c2_ns_nt_nz_nf_nzc_zu_dm, + render_spans_16_c1_ns_nt_z_nf_nzc_zu_dm, render_spans_16_c2_ns_nt_z_nf_nzc_zu_dm, + render_spans_16_c1_ns_t_nz_nf_nzc_zu_dm, render_spans_16_c2_ns_t_nz_nf_nzc_zu_dm, render_spans_16_c1_ns_t_z_nf_nzc_zu_dm, render_spans_16_c2_ns_t_z_nf_nzc_zu_dm, - render_spans_16_c1_s_nt_nz_nf_nzc_zu_dm, render_spans_16_c2_s_nt_nz_nf_nzc_zu_dm, + render_spans_16_c1_s_nt_nz_nf_nzc_zu_dm, render_spans_16_c2_s_nt_nz_nf_nzc_zu_dm, render_spans_16_c1_s_nt_z_nf_nzc_zu_dm, render_spans_16_c2_s_nt_z_nf_nzc_zu_dm, render_spans_16_c1_s_t_nz_nf_nzc_zu_dm, render_spans_16_c2_s_t_nz_nf_nzc_zu_dm, - render_spans_16_c1_s_t_z_nf_nzc_zu_dm, render_spans_16_c2_s_t_z_nf_nzc_zu_dm, - render_spans_16_c1_ns_nt_nz_f_nzc_zu_dm, render_spans_16_c2_ns_nt_nz_f_nzc_zu_dm, + render_spans_16_c1_s_t_z_nf_nzc_zu_dm, render_spans_16_c2_s_t_z_nf_nzc_zu_dm, + render_spans_16_c1_ns_nt_nz_f_nzc_zu_dm, render_spans_16_c2_ns_nt_nz_f_nzc_zu_dm, render_spans_16_c1_ns_nt_z_f_nzc_zu_dm, render_spans_16_c2_ns_nt_z_f_nzc_zu_dm, render_spans_16_c1_ns_t_nz_f_nzc_zu_dm, render_spans_16_c2_ns_t_nz_f_nzc_zu_dm, - render_spans_16_c1_ns_t_z_f_nzc_zu_dm, render_spans_16_c2_ns_t_z_f_nzc_zu_dm, + render_spans_16_c1_ns_t_z_f_nzc_zu_dm, render_spans_16_c2_ns_t_z_f_nzc_zu_dm, render_spans_16_c1_s_nt_nz_f_nzc_zu_dm, render_spans_16_c2_s_nt_nz_f_nzc_zu_dm, - render_spans_16_c1_s_nt_z_f_nzc_zu_dm, render_spans_16_c2_s_nt_z_f_nzc_zu_dm, - render_spans_16_c1_s_t_nz_f_nzc_zu_dm, render_spans_16_c2_s_t_nz_f_nzc_zu_dm, - render_spans_16_c1_s_t_z_f_nzc_zu_dm, render_spans_16_c2_s_t_z_f_nzc_zu_dm, + render_spans_16_c1_s_nt_z_f_nzc_zu_dm, render_spans_16_c2_s_nt_z_f_nzc_zu_dm, + render_spans_16_c1_s_t_nz_f_nzc_zu_dm, render_spans_16_c2_s_t_nz_f_nzc_zu_dm, + render_spans_16_c1_s_t_z_f_nzc_zu_dm, render_spans_16_c2_s_t_z_f_nzc_zu_dm, render_spans_16_c1_ns_nt_nz_nf_zc_zu_dm, render_spans_16_c2_ns_nt_nz_nf_zc_zu_dm, render_spans_16_c1_ns_nt_z_nf_zc_zu_dm, render_spans_16_c2_ns_nt_z_nf_zc_zu_dm, render_spans_16_c1_ns_t_nz_nf_zc_zu_dm, render_spans_16_c2_ns_t_nz_nf_zc_zu_dm, - render_spans_16_c1_ns_t_z_nf_zc_zu_dm, render_spans_16_c2_ns_t_z_nf_zc_zu_dm, + render_spans_16_c1_ns_t_z_nf_zc_zu_dm, render_spans_16_c2_ns_t_z_nf_zc_zu_dm, render_spans_16_c1_s_nt_nz_nf_zc_zu_dm, render_spans_16_c2_s_nt_nz_nf_zc_zu_dm, - render_spans_16_c1_s_nt_z_nf_zc_zu_dm, render_spans_16_c2_s_nt_z_nf_zc_zu_dm, - render_spans_16_c1_s_t_nz_nf_zc_zu_dm, render_spans_16_c2_s_t_nz_nf_zc_zu_dm, - render_spans_16_c1_s_t_z_nf_zc_zu_dm, render_spans_16_c2_s_t_z_nf_zc_zu_dm, + render_spans_16_c1_s_nt_z_nf_zc_zu_dm, render_spans_16_c2_s_nt_z_nf_zc_zu_dm, + render_spans_16_c1_s_t_nz_nf_zc_zu_dm, render_spans_16_c2_s_t_nz_nf_zc_zu_dm, + render_spans_16_c1_s_t_z_nf_zc_zu_dm, render_spans_16_c2_s_t_z_nf_zc_zu_dm, render_spans_16_c1_ns_nt_nz_f_zc_zu_dm, render_spans_16_c2_ns_nt_nz_f_zc_zu_dm, - render_spans_16_c1_ns_nt_z_f_zc_zu_dm, render_spans_16_c2_ns_nt_z_f_zc_zu_dm, - render_spans_16_c1_ns_t_nz_f_zc_zu_dm, render_spans_16_c2_ns_t_nz_f_zc_zu_dm, - render_spans_16_c1_ns_t_z_f_zc_zu_dm, render_spans_16_c2_ns_t_z_f_zc_zu_dm, - render_spans_16_c1_s_nt_nz_f_zc_zu_dm, render_spans_16_c2_s_nt_nz_f_zc_zu_dm, - render_spans_16_c1_s_nt_z_f_zc_zu_dm, render_spans_16_c2_s_nt_z_f_zc_zu_dm, - render_spans_16_c1_s_t_nz_f_zc_zu_dm, render_spans_16_c2_s_t_nz_f_zc_zu_dm, - render_spans_16_c1_s_t_z_f_zc_zu_dm, render_spans_16_c2_s_t_z_f_zc_zu_dm, + render_spans_16_c1_ns_nt_z_f_zc_zu_dm, render_spans_16_c2_ns_nt_z_f_zc_zu_dm, + render_spans_16_c1_ns_t_nz_f_zc_zu_dm, render_spans_16_c2_ns_t_nz_f_zc_zu_dm, + render_spans_16_c1_ns_t_z_f_zc_zu_dm, render_spans_16_c2_ns_t_z_f_zc_zu_dm, + render_spans_16_c1_s_nt_nz_f_zc_zu_dm, render_spans_16_c2_s_nt_nz_f_zc_zu_dm, + render_spans_16_c1_s_nt_z_f_zc_zu_dm, render_spans_16_c2_s_nt_z_f_zc_zu_dm, + render_spans_16_c1_s_t_nz_f_zc_zu_dm, render_spans_16_c2_s_t_nz_f_zc_zu_dm, + render_spans_16_c1_s_t_z_f_zc_zu_dm, render_spans_16_c2_s_t_z_f_zc_zu_dm, render_spans_16_c1_ns_nt_nz_nf_nzc_db, render_spans_16_c2_ns_nt_nz_nf_nzc_db, - render_spans_16_c1_ns_nt_z_nf_nzc_db, render_spans_16_c2_ns_nt_z_nf_nzc_db, - render_spans_16_c1_ns_t_nz_nf_nzc_db, render_spans_16_c2_ns_t_nz_nf_nzc_db, - render_spans_16_c1_ns_t_z_nf_nzc_db, render_spans_16_c2_ns_t_z_nf_nzc_db, - render_spans_16_c1_s_nt_nz_nf_nzc_db, render_spans_16_c2_s_nt_nz_nf_nzc_db, - render_spans_16_c1_s_nt_z_nf_nzc_db, render_spans_16_c2_s_nt_z_nf_nzc_db, - render_spans_16_c1_s_t_nz_nf_nzc_db, render_spans_16_c2_s_t_nz_nf_nzc_db, + render_spans_16_c1_ns_nt_z_nf_nzc_db, render_spans_16_c2_ns_nt_z_nf_nzc_db, + render_spans_16_c1_ns_t_nz_nf_nzc_db, render_spans_16_c2_ns_t_nz_nf_nzc_db, + render_spans_16_c1_ns_t_z_nf_nzc_db, render_spans_16_c2_ns_t_z_nf_nzc_db, + render_spans_16_c1_s_nt_nz_nf_nzc_db, render_spans_16_c2_s_nt_nz_nf_nzc_db, + render_spans_16_c1_s_nt_z_nf_nzc_db, render_spans_16_c2_s_nt_z_nf_nzc_db, + render_spans_16_c1_s_t_nz_nf_nzc_db, render_spans_16_c2_s_t_nz_nf_nzc_db, render_spans_16_c1_s_t_z_nf_nzc_db, render_spans_16_c2_s_t_z_nf_nzc_db, - render_spans_16_c1_ns_nt_nz_f_nzc_db, render_spans_16_c2_ns_nt_nz_f_nzc_db, - render_spans_16_c1_ns_nt_z_f_nzc_db, render_spans_16_c2_ns_nt_z_f_nzc_db, - render_spans_16_c1_ns_t_nz_f_nzc_db, render_spans_16_c2_ns_t_nz_f_nzc_db, + render_spans_16_c1_ns_nt_nz_f_nzc_db, render_spans_16_c2_ns_nt_nz_f_nzc_db, + render_spans_16_c1_ns_nt_z_f_nzc_db, render_spans_16_c2_ns_nt_z_f_nzc_db, + render_spans_16_c1_ns_t_nz_f_nzc_db, render_spans_16_c2_ns_t_nz_f_nzc_db, render_spans_16_c1_ns_t_z_f_nzc_db, render_spans_16_c2_ns_t_z_f_nzc_db, - render_spans_16_c1_s_nt_nz_f_nzc_db, render_spans_16_c2_s_nt_nz_f_nzc_db, + render_spans_16_c1_s_nt_nz_f_nzc_db, render_spans_16_c2_s_nt_nz_f_nzc_db, render_spans_16_c1_s_nt_z_f_nzc_db, render_spans_16_c2_s_nt_z_f_nzc_db, render_spans_16_c1_s_t_nz_f_nzc_db, render_spans_16_c2_s_t_nz_f_nzc_db, - render_spans_16_c1_s_t_z_f_nzc_db, render_spans_16_c2_s_t_z_f_nzc_db, + render_spans_16_c1_s_t_z_f_nzc_db, render_spans_16_c2_s_t_z_f_nzc_db, render_spans_16_c1_ns_nt_nz_nf_zc_db, render_spans_16_c2_ns_nt_nz_nf_zc_db, - render_spans_16_c1_ns_nt_z_nf_zc_db, render_spans_16_c2_ns_nt_z_nf_zc_db, - render_spans_16_c1_ns_t_nz_nf_zc_db, render_spans_16_c2_ns_t_nz_nf_zc_db, + render_spans_16_c1_ns_nt_z_nf_zc_db, render_spans_16_c2_ns_nt_z_nf_zc_db, + render_spans_16_c1_ns_t_nz_nf_zc_db, render_spans_16_c2_ns_t_nz_nf_zc_db, render_spans_16_c1_ns_t_z_nf_zc_db, render_spans_16_c2_ns_t_z_nf_zc_db, - render_spans_16_c1_s_nt_nz_nf_zc_db, render_spans_16_c2_s_nt_nz_nf_zc_db, + render_spans_16_c1_s_nt_nz_nf_zc_db, render_spans_16_c2_s_nt_nz_nf_zc_db, render_spans_16_c1_s_nt_z_nf_zc_db, render_spans_16_c2_s_nt_z_nf_zc_db, render_spans_16_c1_s_t_nz_nf_zc_db, render_spans_16_c2_s_t_nz_nf_zc_db, - render_spans_16_c1_s_t_z_nf_zc_db, render_spans_16_c2_s_t_z_nf_zc_db, - render_spans_16_c1_ns_nt_nz_f_zc_db, render_spans_16_c2_ns_nt_nz_f_zc_db, + render_spans_16_c1_s_t_z_nf_zc_db, render_spans_16_c2_s_t_z_nf_zc_db, + render_spans_16_c1_ns_nt_nz_f_zc_db, render_spans_16_c2_ns_nt_nz_f_zc_db, render_spans_16_c1_ns_nt_z_f_zc_db, render_spans_16_c2_ns_nt_z_f_zc_db, render_spans_16_c1_ns_t_nz_f_zc_db, render_spans_16_c2_ns_t_nz_f_zc_db, - render_spans_16_c1_ns_t_z_f_zc_db, render_spans_16_c2_ns_t_z_f_zc_db, + render_spans_16_c1_ns_t_z_f_zc_db, render_spans_16_c2_ns_t_z_f_zc_db, render_spans_16_c1_s_nt_nz_f_zc_db, render_spans_16_c2_s_nt_nz_f_zc_db, - render_spans_16_c1_s_nt_z_f_zc_db, render_spans_16_c2_s_nt_z_f_zc_db, - render_spans_16_c1_s_t_nz_f_zc_db, render_spans_16_c2_s_t_nz_f_zc_db, - render_spans_16_c1_s_t_z_f_zc_db, render_spans_16_c2_s_t_z_f_zc_db, + render_spans_16_c1_s_nt_z_f_zc_db, render_spans_16_c2_s_nt_z_f_zc_db, + render_spans_16_c1_s_t_nz_f_zc_db, render_spans_16_c2_s_t_nz_f_zc_db, + render_spans_16_c1_s_t_z_f_zc_db, render_spans_16_c2_s_t_z_f_zc_db, - render_spans_16_c1_ns_nt_nz_nf_nzc_zu_db, render_spans_16_c2_ns_nt_nz_nf_nzc_zu_db, - render_spans_16_c1_ns_nt_z_nf_nzc_zu_db, render_spans_16_c2_ns_nt_z_nf_nzc_zu_db, - render_spans_16_c1_ns_t_nz_nf_nzc_zu_db, render_spans_16_c2_ns_t_nz_nf_nzc_zu_db, + render_spans_16_c1_ns_nt_nz_nf_nzc_zu_db, render_spans_16_c2_ns_nt_nz_nf_nzc_zu_db, + render_spans_16_c1_ns_nt_z_nf_nzc_zu_db, render_spans_16_c2_ns_nt_z_nf_nzc_zu_db, + render_spans_16_c1_ns_t_nz_nf_nzc_zu_db, render_spans_16_c2_ns_t_nz_nf_nzc_zu_db, render_spans_16_c1_ns_t_z_nf_nzc_zu_db, render_spans_16_c2_ns_t_z_nf_nzc_zu_db, - render_spans_16_c1_s_nt_nz_nf_nzc_zu_db, render_spans_16_c2_s_nt_nz_nf_nzc_zu_db, + render_spans_16_c1_s_nt_nz_nf_nzc_zu_db, render_spans_16_c2_s_nt_nz_nf_nzc_zu_db, render_spans_16_c1_s_nt_z_nf_nzc_zu_db, render_spans_16_c2_s_nt_z_nf_nzc_zu_db, render_spans_16_c1_s_t_nz_nf_nzc_zu_db, render_spans_16_c2_s_t_nz_nf_nzc_zu_db, - render_spans_16_c1_s_t_z_nf_nzc_zu_db, render_spans_16_c2_s_t_z_nf_nzc_zu_db, - render_spans_16_c1_ns_nt_nz_f_nzc_zu_db, render_spans_16_c2_ns_nt_nz_f_nzc_zu_db, + render_spans_16_c1_s_t_z_nf_nzc_zu_db, render_spans_16_c2_s_t_z_nf_nzc_zu_db, + render_spans_16_c1_ns_nt_nz_f_nzc_zu_db, render_spans_16_c2_ns_nt_nz_f_nzc_zu_db, render_spans_16_c1_ns_nt_z_f_nzc_zu_db, render_spans_16_c2_ns_nt_z_f_nzc_zu_db, render_spans_16_c1_ns_t_nz_f_nzc_zu_db, render_spans_16_c2_ns_t_nz_f_nzc_zu_db, - render_spans_16_c1_ns_t_z_f_nzc_zu_db, render_spans_16_c2_ns_t_z_f_nzc_zu_db, + render_spans_16_c1_ns_t_z_f_nzc_zu_db, render_spans_16_c2_ns_t_z_f_nzc_zu_db, render_spans_16_c1_s_nt_nz_f_nzc_zu_db, render_spans_16_c2_s_nt_nz_f_nzc_zu_db, - render_spans_16_c1_s_nt_z_f_nzc_zu_db, render_spans_16_c2_s_nt_z_f_nzc_zu_db, - render_spans_16_c1_s_t_nz_f_nzc_zu_db, render_spans_16_c2_s_t_nz_f_nzc_zu_db, - render_spans_16_c1_s_t_z_f_nzc_zu_db, render_spans_16_c2_s_t_z_f_nzc_zu_db, + render_spans_16_c1_s_nt_z_f_nzc_zu_db, render_spans_16_c2_s_nt_z_f_nzc_zu_db, + render_spans_16_c1_s_t_nz_f_nzc_zu_db, render_spans_16_c2_s_t_nz_f_nzc_zu_db, + render_spans_16_c1_s_t_z_f_nzc_zu_db, render_spans_16_c2_s_t_z_f_nzc_zu_db, render_spans_16_c1_ns_nt_nz_nf_zc_zu_db, render_spans_16_c2_ns_nt_nz_nf_zc_zu_db, render_spans_16_c1_ns_nt_z_nf_zc_zu_db, render_spans_16_c2_ns_nt_z_nf_zc_zu_db, render_spans_16_c1_ns_t_nz_nf_zc_zu_db, render_spans_16_c2_ns_t_nz_nf_zc_zu_db, - render_spans_16_c1_ns_t_z_nf_zc_zu_db, render_spans_16_c2_ns_t_z_nf_zc_zu_db, + render_spans_16_c1_ns_t_z_nf_zc_zu_db, render_spans_16_c2_ns_t_z_nf_zc_zu_db, render_spans_16_c1_s_nt_nz_nf_zc_zu_db, render_spans_16_c2_s_nt_nz_nf_zc_zu_db, - render_spans_16_c1_s_nt_z_nf_zc_zu_db, render_spans_16_c2_s_nt_z_nf_zc_zu_db, - render_spans_16_c1_s_t_nz_nf_zc_zu_db, render_spans_16_c2_s_t_nz_nf_zc_zu_db, - render_spans_16_c1_s_t_z_nf_zc_zu_db, render_spans_16_c2_s_t_z_nf_zc_zu_db, + render_spans_16_c1_s_nt_z_nf_zc_zu_db, render_spans_16_c2_s_nt_z_nf_zc_zu_db, + render_spans_16_c1_s_t_nz_nf_zc_zu_db, render_spans_16_c2_s_t_nz_nf_zc_zu_db, + render_spans_16_c1_s_t_z_nf_zc_zu_db, render_spans_16_c2_s_t_z_nf_zc_zu_db, render_spans_16_c1_ns_nt_nz_f_zc_zu_db, render_spans_16_c2_ns_nt_nz_f_zc_zu_db, - render_spans_16_c1_ns_nt_z_f_zc_zu_db, render_spans_16_c2_ns_nt_z_f_zc_zu_db, - render_spans_16_c1_ns_t_nz_f_zc_zu_db, render_spans_16_c2_ns_t_nz_f_zc_zu_db, - render_spans_16_c1_ns_t_z_f_zc_zu_db, render_spans_16_c2_ns_t_z_f_zc_zu_db, - render_spans_16_c1_s_nt_nz_f_zc_zu_db, render_spans_16_c2_s_nt_nz_f_zc_zu_db, - render_spans_16_c1_s_nt_z_f_zc_zu_db, render_spans_16_c2_s_nt_z_f_zc_zu_db, - render_spans_16_c1_s_t_nz_f_zc_zu_db, render_spans_16_c2_s_t_nz_f_zc_zu_db, - render_spans_16_c1_s_t_z_f_zc_zu_db, render_spans_16_c2_s_t_z_f_zc_zu_db, + render_spans_16_c1_ns_nt_z_f_zc_zu_db, render_spans_16_c2_ns_nt_z_f_zc_zu_db, + render_spans_16_c1_ns_t_nz_f_zc_zu_db, render_spans_16_c2_ns_t_nz_f_zc_zu_db, + render_spans_16_c1_ns_t_z_f_zc_zu_db, render_spans_16_c2_ns_t_z_f_zc_zu_db, + render_spans_16_c1_s_nt_nz_f_zc_zu_db, render_spans_16_c2_s_nt_nz_f_zc_zu_db, + render_spans_16_c1_s_nt_z_f_zc_zu_db, render_spans_16_c2_s_nt_z_f_zc_zu_db, + render_spans_16_c1_s_t_nz_f_zc_zu_db, render_spans_16_c2_s_t_nz_f_zc_zu_db, + render_spans_16_c1_s_t_z_f_zc_zu_db, render_spans_16_c2_s_t_z_f_zc_zu_db, render_spans_16_c1_ns_nt_nz_nf_nzc_dn, render_spans_16_c2_ns_nt_nz_nf_nzc_dn, - render_spans_16_c1_ns_nt_z_nf_nzc_dn, render_spans_16_c2_ns_nt_z_nf_nzc_dn, - render_spans_16_c1_ns_t_nz_nf_nzc_dn, render_spans_16_c2_ns_t_nz_nf_nzc_dn, - render_spans_16_c1_ns_t_z_nf_nzc_dn, render_spans_16_c2_ns_t_z_nf_nzc_dn, - render_spans_16_c1_s_nt_nz_nf_nzc_dn, render_spans_16_c2_s_nt_nz_nf_nzc_dn, - render_spans_16_c1_s_nt_z_nf_nzc_dn, render_spans_16_c2_s_nt_z_nf_nzc_dn, - render_spans_16_c1_s_t_nz_nf_nzc_dn, render_spans_16_c2_s_t_nz_nf_nzc_dn, + render_spans_16_c1_ns_nt_z_nf_nzc_dn, render_spans_16_c2_ns_nt_z_nf_nzc_dn, + render_spans_16_c1_ns_t_nz_nf_nzc_dn, render_spans_16_c2_ns_t_nz_nf_nzc_dn, + render_spans_16_c1_ns_t_z_nf_nzc_dn, render_spans_16_c2_ns_t_z_nf_nzc_dn, + render_spans_16_c1_s_nt_nz_nf_nzc_dn, render_spans_16_c2_s_nt_nz_nf_nzc_dn, + render_spans_16_c1_s_nt_z_nf_nzc_dn, render_spans_16_c2_s_nt_z_nf_nzc_dn, + render_spans_16_c1_s_t_nz_nf_nzc_dn, render_spans_16_c2_s_t_nz_nf_nzc_dn, render_spans_16_c1_s_t_z_nf_nzc_dn, render_spans_16_c2_s_t_z_nf_nzc_dn, - render_spans_16_c1_ns_nt_nz_f_nzc_dn, render_spans_16_c2_ns_nt_nz_f_nzc_dn, - render_spans_16_c1_ns_nt_z_f_nzc_dn, render_spans_16_c2_ns_nt_z_f_nzc_dn, - render_spans_16_c1_ns_t_nz_f_nzc_dn, render_spans_16_c2_ns_t_nz_f_nzc_dn, + render_spans_16_c1_ns_nt_nz_f_nzc_dn, render_spans_16_c2_ns_nt_nz_f_nzc_dn, + render_spans_16_c1_ns_nt_z_f_nzc_dn, render_spans_16_c2_ns_nt_z_f_nzc_dn, + render_spans_16_c1_ns_t_nz_f_nzc_dn, render_spans_16_c2_ns_t_nz_f_nzc_dn, render_spans_16_c1_ns_t_z_f_nzc_dn, render_spans_16_c2_ns_t_z_f_nzc_dn, - render_spans_16_c1_s_nt_nz_f_nzc_dn, render_spans_16_c2_s_nt_nz_f_nzc_dn, + render_spans_16_c1_s_nt_nz_f_nzc_dn, render_spans_16_c2_s_nt_nz_f_nzc_dn, render_spans_16_c1_s_nt_z_f_nzc_dn, render_spans_16_c2_s_nt_z_f_nzc_dn, render_spans_16_c1_s_t_nz_f_nzc_dn, render_spans_16_c2_s_t_nz_f_nzc_dn, - render_spans_16_c1_s_t_z_f_nzc_dn, render_spans_16_c2_s_t_z_f_nzc_dn, + render_spans_16_c1_s_t_z_f_nzc_dn, render_spans_16_c2_s_t_z_f_nzc_dn, render_spans_16_c1_ns_nt_nz_nf_zc_dn, render_spans_16_c2_ns_nt_nz_nf_zc_dn, - render_spans_16_c1_ns_nt_z_nf_zc_dn, render_spans_16_c2_ns_nt_z_nf_zc_dn, - render_spans_16_c1_ns_t_nz_nf_zc_dn, render_spans_16_c2_ns_t_nz_nf_zc_dn, + render_spans_16_c1_ns_nt_z_nf_zc_dn, render_spans_16_c2_ns_nt_z_nf_zc_dn, + render_spans_16_c1_ns_t_nz_nf_zc_dn, render_spans_16_c2_ns_t_nz_nf_zc_dn, render_spans_16_c1_ns_t_z_nf_zc_dn, render_spans_16_c2_ns_t_z_nf_zc_dn, - render_spans_16_c1_s_nt_nz_nf_zc_dn, render_spans_16_c2_s_nt_nz_nf_zc_dn, + render_spans_16_c1_s_nt_nz_nf_zc_dn, render_spans_16_c2_s_nt_nz_nf_zc_dn, render_spans_16_c1_s_nt_z_nf_zc_dn, render_spans_16_c2_s_nt_z_nf_zc_dn, render_spans_16_c1_s_t_nz_nf_zc_dn, render_spans_16_c2_s_t_nz_nf_zc_dn, - render_spans_16_c1_s_t_z_nf_zc_dn, render_spans_16_c2_s_t_z_nf_zc_dn, - render_spans_16_c1_ns_nt_nz_f_zc_dn, render_spans_16_c2_ns_nt_nz_f_zc_dn, + render_spans_16_c1_s_t_z_nf_zc_dn, render_spans_16_c2_s_t_z_nf_zc_dn, + render_spans_16_c1_ns_nt_nz_f_zc_dn, render_spans_16_c2_ns_nt_nz_f_zc_dn, render_spans_16_c1_ns_nt_z_f_zc_dn, render_spans_16_c2_ns_nt_z_f_zc_dn, render_spans_16_c1_ns_t_nz_f_zc_dn, render_spans_16_c2_ns_t_nz_f_zc_dn, - render_spans_16_c1_ns_t_z_f_zc_dn, render_spans_16_c2_ns_t_z_f_zc_dn, + render_spans_16_c1_ns_t_z_f_zc_dn, render_spans_16_c2_ns_t_z_f_zc_dn, render_spans_16_c1_s_nt_nz_f_zc_dn, render_spans_16_c2_s_nt_nz_f_zc_dn, - render_spans_16_c1_s_nt_z_f_zc_dn, render_spans_16_c2_s_nt_z_f_zc_dn, - render_spans_16_c1_s_t_nz_f_zc_dn, render_spans_16_c2_s_t_nz_f_zc_dn, - render_spans_16_c1_s_t_z_f_zc_dn, render_spans_16_c2_s_t_z_f_zc_dn, + render_spans_16_c1_s_nt_z_f_zc_dn, render_spans_16_c2_s_nt_z_f_zc_dn, + render_spans_16_c1_s_t_nz_f_zc_dn, render_spans_16_c2_s_t_nz_f_zc_dn, + render_spans_16_c1_s_t_z_f_zc_dn, render_spans_16_c2_s_t_z_f_zc_dn, - render_spans_16_c1_ns_nt_nz_nf_nzc_zu_dn, render_spans_16_c2_ns_nt_nz_nf_nzc_zu_dn, - render_spans_16_c1_ns_nt_z_nf_nzc_zu_dn, render_spans_16_c2_ns_nt_z_nf_nzc_zu_dn, - render_spans_16_c1_ns_t_nz_nf_nzc_zu_dn, render_spans_16_c2_ns_t_nz_nf_nzc_zu_dn, + render_spans_16_c1_ns_nt_nz_nf_nzc_zu_dn, render_spans_16_c2_ns_nt_nz_nf_nzc_zu_dn, + render_spans_16_c1_ns_nt_z_nf_nzc_zu_dn, render_spans_16_c2_ns_nt_z_nf_nzc_zu_dn, + render_spans_16_c1_ns_t_nz_nf_nzc_zu_dn, render_spans_16_c2_ns_t_nz_nf_nzc_zu_dn, render_spans_16_c1_ns_t_z_nf_nzc_zu_dn, render_spans_16_c2_ns_t_z_nf_nzc_zu_dn, - render_spans_16_c1_s_nt_nz_nf_nzc_zu_dn, render_spans_16_c2_s_nt_nz_nf_nzc_zu_dn, + render_spans_16_c1_s_nt_nz_nf_nzc_zu_dn, render_spans_16_c2_s_nt_nz_nf_nzc_zu_dn, render_spans_16_c1_s_nt_z_nf_nzc_zu_dn, render_spans_16_c2_s_nt_z_nf_nzc_zu_dn, render_spans_16_c1_s_t_nz_nf_nzc_zu_dn, render_spans_16_c2_s_t_nz_nf_nzc_zu_dn, - render_spans_16_c1_s_t_z_nf_nzc_zu_dn, render_spans_16_c2_s_t_z_nf_nzc_zu_dn, - render_spans_16_c1_ns_nt_nz_f_nzc_zu_dn, render_spans_16_c2_ns_nt_nz_f_nzc_zu_dn, + render_spans_16_c1_s_t_z_nf_nzc_zu_dn, render_spans_16_c2_s_t_z_nf_nzc_zu_dn, + render_spans_16_c1_ns_nt_nz_f_nzc_zu_dn, render_spans_16_c2_ns_nt_nz_f_nzc_zu_dn, render_spans_16_c1_ns_nt_z_f_nzc_zu_dn, render_spans_16_c2_ns_nt_z_f_nzc_zu_dn, render_spans_16_c1_ns_t_nz_f_nzc_zu_dn, render_spans_16_c2_ns_t_nz_f_nzc_zu_dn, - render_spans_16_c1_ns_t_z_f_nzc_zu_dn, render_spans_16_c2_ns_t_z_f_nzc_zu_dn, + render_spans_16_c1_ns_t_z_f_nzc_zu_dn, render_spans_16_c2_ns_t_z_f_nzc_zu_dn, render_spans_16_c1_s_nt_nz_f_nzc_zu_dn, render_spans_16_c2_s_nt_nz_f_nzc_zu_dn, - render_spans_16_c1_s_nt_z_f_nzc_zu_dn, render_spans_16_c2_s_nt_z_f_nzc_zu_dn, - render_spans_16_c1_s_t_nz_f_nzc_zu_dn, render_spans_16_c2_s_t_nz_f_nzc_zu_dn, - render_spans_16_c1_s_t_z_f_nzc_zu_dn, render_spans_16_c2_s_t_z_f_nzc_zu_dn, + render_spans_16_c1_s_nt_z_f_nzc_zu_dn, render_spans_16_c2_s_nt_z_f_nzc_zu_dn, + render_spans_16_c1_s_t_nz_f_nzc_zu_dn, render_spans_16_c2_s_t_nz_f_nzc_zu_dn, + render_spans_16_c1_s_t_z_f_nzc_zu_dn, render_spans_16_c2_s_t_z_f_nzc_zu_dn, render_spans_16_c1_ns_nt_nz_nf_zc_zu_dn, render_spans_16_c2_ns_nt_nz_nf_zc_zu_dn, render_spans_16_c1_ns_nt_z_nf_zc_zu_dn, render_spans_16_c2_ns_nt_z_nf_zc_zu_dn, render_spans_16_c1_ns_t_nz_nf_zc_zu_dn, render_spans_16_c2_ns_t_nz_nf_zc_zu_dn, - render_spans_16_c1_ns_t_z_nf_zc_zu_dn, render_spans_16_c2_ns_t_z_nf_zc_zu_dn, + render_spans_16_c1_ns_t_z_nf_zc_zu_dn, render_spans_16_c2_ns_t_z_nf_zc_zu_dn, render_spans_16_c1_s_nt_nz_nf_zc_zu_dn, render_spans_16_c2_s_nt_nz_nf_zc_zu_dn, - render_spans_16_c1_s_nt_z_nf_zc_zu_dn, render_spans_16_c2_s_nt_z_nf_zc_zu_dn, - render_spans_16_c1_s_t_nz_nf_zc_zu_dn, render_spans_16_c2_s_t_nz_nf_zc_zu_dn, - render_spans_16_c1_s_t_z_nf_zc_zu_dn, render_spans_16_c2_s_t_z_nf_zc_zu_dn, + render_spans_16_c1_s_nt_z_nf_zc_zu_dn, render_spans_16_c2_s_nt_z_nf_zc_zu_dn, + render_spans_16_c1_s_t_nz_nf_zc_zu_dn, render_spans_16_c2_s_t_nz_nf_zc_zu_dn, + render_spans_16_c1_s_t_z_nf_zc_zu_dn, render_spans_16_c2_s_t_z_nf_zc_zu_dn, render_spans_16_c1_ns_nt_nz_f_zc_zu_dn, render_spans_16_c2_ns_nt_nz_f_zc_zu_dn, - render_spans_16_c1_ns_nt_z_f_zc_zu_dn, render_spans_16_c2_ns_nt_z_f_zc_zu_dn, - render_spans_16_c1_ns_t_nz_f_zc_zu_dn, render_spans_16_c2_ns_t_nz_f_zc_zu_dn, - render_spans_16_c1_ns_t_z_f_zc_zu_dn, render_spans_16_c2_ns_t_z_f_zc_zu_dn, - render_spans_16_c1_s_nt_nz_f_zc_zu_dn, render_spans_16_c2_s_nt_nz_f_zc_zu_dn, - render_spans_16_c1_s_nt_z_f_zc_zu_dn, render_spans_16_c2_s_nt_z_f_zc_zu_dn, - render_spans_16_c1_s_t_nz_f_zc_zu_dn, render_spans_16_c2_s_t_nz_f_zc_zu_dn, - render_spans_16_c1_s_t_z_f_zc_zu_dn, render_spans_16_c2_s_t_z_f_zc_zu_dn, + render_spans_16_c1_ns_nt_z_f_zc_zu_dn, render_spans_16_c2_ns_nt_z_f_zc_zu_dn, + render_spans_16_c1_ns_t_nz_f_zc_zu_dn, render_spans_16_c2_ns_t_nz_f_zc_zu_dn, + render_spans_16_c1_ns_t_z_f_zc_zu_dn, render_spans_16_c2_ns_t_z_f_zc_zu_dn, + render_spans_16_c1_s_nt_nz_f_zc_zu_dn, render_spans_16_c2_s_nt_nz_f_zc_zu_dn, + render_spans_16_c1_s_nt_z_f_zc_zu_dn, render_spans_16_c2_s_nt_z_f_zc_zu_dn, + render_spans_16_c1_s_t_nz_f_zc_zu_dn, render_spans_16_c2_s_t_nz_f_zc_zu_dn, + render_spans_16_c1_s_t_z_f_zc_zu_dn, render_spans_16_c2_s_t_z_f_zc_zu_dn, render_spans_16_c1_ns_nt_nz_nf_nzc_dn, render_spans_16_c2_ns_nt_nz_nf_nzc_dn, - render_spans_16_c1_ns_nt_z_nf_nzc_dn, render_spans_16_c2_ns_nt_z_nf_nzc_dn, - render_spans_16_c1_ns_t_nz_nf_nzc_dn, render_spans_16_c2_ns_t_nz_nf_nzc_dn, - render_spans_16_c1_ns_t_z_nf_nzc_dn, render_spans_16_c2_ns_t_z_nf_nzc_dn, - render_spans_16_c1_s_nt_nz_nf_nzc_dn, render_spans_16_c2_s_nt_nz_nf_nzc_dn, - render_spans_16_c1_s_nt_z_nf_nzc_dn, render_spans_16_c2_s_nt_z_nf_nzc_dn, - render_spans_16_c1_s_t_nz_nf_nzc_dn, render_spans_16_c2_s_t_nz_nf_nzc_dn, + render_spans_16_c1_ns_nt_z_nf_nzc_dn, render_spans_16_c2_ns_nt_z_nf_nzc_dn, + render_spans_16_c1_ns_t_nz_nf_nzc_dn, render_spans_16_c2_ns_t_nz_nf_nzc_dn, + render_spans_16_c1_ns_t_z_nf_nzc_dn, render_spans_16_c2_ns_t_z_nf_nzc_dn, + render_spans_16_c1_s_nt_nz_nf_nzc_dn, render_spans_16_c2_s_nt_nz_nf_nzc_dn, + render_spans_16_c1_s_nt_z_nf_nzc_dn, render_spans_16_c2_s_nt_z_nf_nzc_dn, + render_spans_16_c1_s_t_nz_nf_nzc_dn, render_spans_16_c2_s_t_nz_nf_nzc_dn, render_spans_16_c1_s_t_z_nf_nzc_dn, render_spans_16_c2_s_t_z_nf_nzc_dn, - render_spans_16_c1_ns_nt_nz_f_nzc_dn, render_spans_16_c2_ns_nt_nz_f_nzc_dn, - render_spans_16_c1_ns_nt_z_f_nzc_dn, render_spans_16_c2_ns_nt_z_f_nzc_dn, - render_spans_16_c1_ns_t_nz_f_nzc_dn, render_spans_16_c2_ns_t_nz_f_nzc_dn, + render_spans_16_c1_ns_nt_nz_f_nzc_dn, render_spans_16_c2_ns_nt_nz_f_nzc_dn, + render_spans_16_c1_ns_nt_z_f_nzc_dn, render_spans_16_c2_ns_nt_z_f_nzc_dn, + render_spans_16_c1_ns_t_nz_f_nzc_dn, render_spans_16_c2_ns_t_nz_f_nzc_dn, render_spans_16_c1_ns_t_z_f_nzc_dn, render_spans_16_c2_ns_t_z_f_nzc_dn, - render_spans_16_c1_s_nt_nz_f_nzc_dn, render_spans_16_c2_s_nt_nz_f_nzc_dn, + render_spans_16_c1_s_nt_nz_f_nzc_dn, render_spans_16_c2_s_nt_nz_f_nzc_dn, render_spans_16_c1_s_nt_z_f_nzc_dn, render_spans_16_c2_s_nt_z_f_nzc_dn, render_spans_16_c1_s_t_nz_f_nzc_dn, render_spans_16_c2_s_t_nz_f_nzc_dn, - render_spans_16_c1_s_t_z_f_nzc_dn, render_spans_16_c2_s_t_z_f_nzc_dn, + render_spans_16_c1_s_t_z_f_nzc_dn, render_spans_16_c2_s_t_z_f_nzc_dn, render_spans_16_c1_ns_nt_nz_nf_zc_dn, render_spans_16_c2_ns_nt_nz_nf_zc_dn, - render_spans_16_c1_ns_nt_z_nf_zc_dn, render_spans_16_c2_ns_nt_z_nf_zc_dn, - render_spans_16_c1_ns_t_nz_nf_zc_dn, render_spans_16_c2_ns_t_nz_nf_zc_dn, + render_spans_16_c1_ns_nt_z_nf_zc_dn, render_spans_16_c2_ns_nt_z_nf_zc_dn, + render_spans_16_c1_ns_t_nz_nf_zc_dn, render_spans_16_c2_ns_t_nz_nf_zc_dn, render_spans_16_c1_ns_t_z_nf_zc_dn, render_spans_16_c2_ns_t_z_nf_zc_dn, - render_spans_16_c1_s_nt_nz_nf_zc_dn, render_spans_16_c2_s_nt_nz_nf_zc_dn, + render_spans_16_c1_s_nt_nz_nf_zc_dn, render_spans_16_c2_s_nt_nz_nf_zc_dn, render_spans_16_c1_s_nt_z_nf_zc_dn, render_spans_16_c2_s_nt_z_nf_zc_dn, render_spans_16_c1_s_t_nz_nf_zc_dn, render_spans_16_c2_s_t_nz_nf_zc_dn, - render_spans_16_c1_s_t_z_nf_zc_dn, render_spans_16_c2_s_t_z_nf_zc_dn, - render_spans_16_c1_ns_nt_nz_f_zc_dn, render_spans_16_c2_ns_nt_nz_f_zc_dn, + render_spans_16_c1_s_t_z_nf_zc_dn, render_spans_16_c2_s_t_z_nf_zc_dn, + render_spans_16_c1_ns_nt_nz_f_zc_dn, render_spans_16_c2_ns_nt_nz_f_zc_dn, render_spans_16_c1_ns_nt_z_f_zc_dn, render_spans_16_c2_ns_nt_z_f_zc_dn, render_spans_16_c1_ns_t_nz_f_zc_dn, render_spans_16_c2_ns_t_nz_f_zc_dn, - render_spans_16_c1_ns_t_z_f_zc_dn, render_spans_16_c2_ns_t_z_f_zc_dn, + render_spans_16_c1_ns_t_z_f_zc_dn, render_spans_16_c2_ns_t_z_f_zc_dn, render_spans_16_c1_s_nt_nz_f_zc_dn, render_spans_16_c2_s_nt_nz_f_zc_dn, - render_spans_16_c1_s_nt_z_f_zc_dn, render_spans_16_c2_s_nt_z_f_zc_dn, - render_spans_16_c1_s_t_nz_f_zc_dn, render_spans_16_c2_s_t_nz_f_zc_dn, - render_spans_16_c1_s_t_z_f_zc_dn, render_spans_16_c2_s_t_z_f_zc_dn, + render_spans_16_c1_s_nt_z_f_zc_dn, render_spans_16_c2_s_nt_z_f_zc_dn, + render_spans_16_c1_s_t_nz_f_zc_dn, render_spans_16_c2_s_t_nz_f_zc_dn, + render_spans_16_c1_s_t_z_f_zc_dn, render_spans_16_c2_s_t_z_f_zc_dn, - render_spans_16_c1_ns_nt_nz_nf_nzc_zu_dn, render_spans_16_c2_ns_nt_nz_nf_nzc_zu_dn, - render_spans_16_c1_ns_nt_z_nf_nzc_zu_dn, render_spans_16_c2_ns_nt_z_nf_nzc_zu_dn, - render_spans_16_c1_ns_t_nz_nf_nzc_zu_dn, render_spans_16_c2_ns_t_nz_nf_nzc_zu_dn, + render_spans_16_c1_ns_nt_nz_nf_nzc_zu_dn, render_spans_16_c2_ns_nt_nz_nf_nzc_zu_dn, + render_spans_16_c1_ns_nt_z_nf_nzc_zu_dn, render_spans_16_c2_ns_nt_z_nf_nzc_zu_dn, + render_spans_16_c1_ns_t_nz_nf_nzc_zu_dn, render_spans_16_c2_ns_t_nz_nf_nzc_zu_dn, render_spans_16_c1_ns_t_z_nf_nzc_zu_dn, render_spans_16_c2_ns_t_z_nf_nzc_zu_dn, - render_spans_16_c1_s_nt_nz_nf_nzc_zu_dn, render_spans_16_c2_s_nt_nz_nf_nzc_zu_dn, + render_spans_16_c1_s_nt_nz_nf_nzc_zu_dn, render_spans_16_c2_s_nt_nz_nf_nzc_zu_dn, render_spans_16_c1_s_nt_z_nf_nzc_zu_dn, render_spans_16_c2_s_nt_z_nf_nzc_zu_dn, render_spans_16_c1_s_t_nz_nf_nzc_zu_dn, render_spans_16_c2_s_t_nz_nf_nzc_zu_dn, - render_spans_16_c1_s_t_z_nf_nzc_zu_dn, render_spans_16_c2_s_t_z_nf_nzc_zu_dn, - render_spans_16_c1_ns_nt_nz_f_nzc_zu_dn, render_spans_16_c2_ns_nt_nz_f_nzc_zu_dn, + render_spans_16_c1_s_t_z_nf_nzc_zu_dn, render_spans_16_c2_s_t_z_nf_nzc_zu_dn, + render_spans_16_c1_ns_nt_nz_f_nzc_zu_dn, render_spans_16_c2_ns_nt_nz_f_nzc_zu_dn, render_spans_16_c1_ns_nt_z_f_nzc_zu_dn, render_spans_16_c2_ns_nt_z_f_nzc_zu_dn, render_spans_16_c1_ns_t_nz_f_nzc_zu_dn, render_spans_16_c2_ns_t_nz_f_nzc_zu_dn, - render_spans_16_c1_ns_t_z_f_nzc_zu_dn, render_spans_16_c2_ns_t_z_f_nzc_zu_dn, + render_spans_16_c1_ns_t_z_f_nzc_zu_dn, render_spans_16_c2_ns_t_z_f_nzc_zu_dn, render_spans_16_c1_s_nt_nz_f_nzc_zu_dn, render_spans_16_c2_s_nt_nz_f_nzc_zu_dn, - render_spans_16_c1_s_nt_z_f_nzc_zu_dn, render_spans_16_c2_s_nt_z_f_nzc_zu_dn, - render_spans_16_c1_s_t_nz_f_nzc_zu_dn, render_spans_16_c2_s_t_nz_f_nzc_zu_dn, - render_spans_16_c1_s_t_z_f_nzc_zu_dn, render_spans_16_c2_s_t_z_f_nzc_zu_dn, + render_spans_16_c1_s_nt_z_f_nzc_zu_dn, render_spans_16_c2_s_nt_z_f_nzc_zu_dn, + render_spans_16_c1_s_t_nz_f_nzc_zu_dn, render_spans_16_c2_s_t_nz_f_nzc_zu_dn, + render_spans_16_c1_s_t_z_f_nzc_zu_dn, render_spans_16_c2_s_t_z_f_nzc_zu_dn, render_spans_16_c1_ns_nt_nz_nf_zc_zu_dn, render_spans_16_c2_ns_nt_nz_nf_zc_zu_dn, render_spans_16_c1_ns_nt_z_nf_zc_zu_dn, render_spans_16_c2_ns_nt_z_nf_zc_zu_dn, render_spans_16_c1_ns_t_nz_nf_zc_zu_dn, render_spans_16_c2_ns_t_nz_nf_zc_zu_dn, - render_spans_16_c1_ns_t_z_nf_zc_zu_dn, render_spans_16_c2_ns_t_z_nf_zc_zu_dn, + render_spans_16_c1_ns_t_z_nf_zc_zu_dn, render_spans_16_c2_ns_t_z_nf_zc_zu_dn, render_spans_16_c1_s_nt_nz_nf_zc_zu_dn, render_spans_16_c2_s_nt_nz_nf_zc_zu_dn, - render_spans_16_c1_s_nt_z_nf_zc_zu_dn, render_spans_16_c2_s_nt_z_nf_zc_zu_dn, - render_spans_16_c1_s_t_nz_nf_zc_zu_dn, render_spans_16_c2_s_t_nz_nf_zc_zu_dn, - render_spans_16_c1_s_t_z_nf_zc_zu_dn, render_spans_16_c2_s_t_z_nf_zc_zu_dn, + render_spans_16_c1_s_nt_z_nf_zc_zu_dn, render_spans_16_c2_s_nt_z_nf_zc_zu_dn, + render_spans_16_c1_s_t_nz_nf_zc_zu_dn, render_spans_16_c2_s_t_nz_nf_zc_zu_dn, + render_spans_16_c1_s_t_z_nf_zc_zu_dn, render_spans_16_c2_s_t_z_nf_zc_zu_dn, render_spans_16_c1_ns_nt_nz_f_zc_zu_dn, render_spans_16_c2_ns_nt_nz_f_zc_zu_dn, - render_spans_16_c1_ns_nt_z_f_zc_zu_dn, render_spans_16_c2_ns_nt_z_f_zc_zu_dn, - render_spans_16_c1_ns_t_nz_f_zc_zu_dn, render_spans_16_c2_ns_t_nz_f_zc_zu_dn, - render_spans_16_c1_ns_t_z_f_zc_zu_dn, render_spans_16_c2_ns_t_z_f_zc_zu_dn, - render_spans_16_c1_s_nt_nz_f_zc_zu_dn, render_spans_16_c2_s_nt_nz_f_zc_zu_dn, - render_spans_16_c1_s_nt_z_f_zc_zu_dn, render_spans_16_c2_s_nt_z_f_zc_zu_dn, - render_spans_16_c1_s_t_nz_f_zc_zu_dn, render_spans_16_c2_s_t_nz_f_zc_zu_dn, - render_spans_16_c1_s_t_z_f_zc_zu_dn, render_spans_16_c2_s_t_z_f_zc_zu_dn, + render_spans_16_c1_ns_nt_z_f_zc_zu_dn, render_spans_16_c2_ns_nt_z_f_zc_zu_dn, + render_spans_16_c1_ns_t_nz_f_zc_zu_dn, render_spans_16_c2_ns_t_nz_f_zc_zu_dn, + render_spans_16_c1_ns_t_z_f_zc_zu_dn, render_spans_16_c2_ns_t_z_f_zc_zu_dn, + render_spans_16_c1_s_nt_nz_f_zc_zu_dn, render_spans_16_c2_s_nt_nz_f_zc_zu_dn, + render_spans_16_c1_s_nt_z_f_zc_zu_dn, render_spans_16_c2_s_nt_z_f_zc_zu_dn, + render_spans_16_c1_s_t_nz_f_zc_zu_dn, render_spans_16_c2_s_t_nz_f_zc_zu_dn, + render_spans_16_c1_s_t_z_f_zc_zu_dn, render_spans_16_c2_s_t_z_f_zc_zu_dn, }; diff --git a/src/mame/video/rdptpipe.c b/src/mame/video/rdptpipe.c index 8bf300f1349..24b23b919c2 100644 --- a/src/mame/video/rdptpipe.c +++ b/src/mame/video/rdptpipe.c @@ -1,4 +1,4 @@ -#define RELATIVE(x, y) (((((x) >> 3) - (y)) << 3) | (x & 7)) +#define RELATIVE(x, y) (((((x) >> 3) - (y)) << 3) | (x & 7)) #if defined(COPY) #define CLAMP(SSS, SST, maxs, maxt) \ diff --git a/src/mame/video/rdpzcomp.h b/src/mame/video/rdpzcomp.h index 2ed3d314170..23e23878998 100644 --- a/src/mame/video/rdpzcomp.h +++ b/src/mame/video/rdpzcomp.h @@ -17,8 +17,8 @@ INLINE UINT32 z_compare_NIMR_NAA_Z3(void* fb, UINT8* hb, UINT16* zb, UINT8* zhb, static UINT32 (*rdp_z_compare_func[16])(void*, UINT8*, UINT16*, UINT8*, UINT32, UINT16) = { - z_compare_IMR_AA_Z0, z_compare_NIMR_AA_Z0, z_compare_IMR_NAA_Z0, z_compare_NIMR_NAA_Z0, - z_compare_IMR_AA_Z1, z_compare_NIMR_AA_Z1, z_compare_IMR_NAA_Z1, z_compare_NIMR_NAA_Z1, - z_compare_IMR_AA_Z2, z_compare_NIMR_AA_Z2, z_compare_IMR_NAA_Z2, z_compare_NIMR_NAA_Z2, - z_compare_IMR_AA_Z3, z_compare_NIMR_AA_Z3, z_compare_IMR_NAA_Z3, z_compare_NIMR_NAA_Z3 + z_compare_IMR_AA_Z0, z_compare_NIMR_AA_Z0, z_compare_IMR_NAA_Z0, z_compare_NIMR_NAA_Z0, + z_compare_IMR_AA_Z1, z_compare_NIMR_AA_Z1, z_compare_IMR_NAA_Z1, z_compare_NIMR_NAA_Z1, + z_compare_IMR_AA_Z2, z_compare_NIMR_AA_Z2, z_compare_IMR_NAA_Z2, z_compare_NIMR_NAA_Z2, + z_compare_IMR_AA_Z3, z_compare_NIMR_AA_Z3, z_compare_IMR_NAA_Z3, z_compare_NIMR_NAA_Z3 }; diff --git a/src/mame/video/taito_b.c b/src/mame/video/taito_b.c index 27dad1dd5ad..5e1adec2adf 100644 --- a/src/mame/video/taito_b.c +++ b/src/mame/video/taito_b.c @@ -62,8 +62,8 @@ VIDEO_START( taitob_color_order0 ) /*this is the basic layout used in: Nastar, Ashura Blaster, Hit the Ice, Rambo3, Tetris*/ /*Note that in both this and color order 1 - * pixel_color_base/color_granularity is equal to sprites color base. - * Pure coincidence ?*/ + * pixel_color_base/color_granularity is equal to sprites color base. + * Pure coincidence ?*/ b_sp_color_base = 0x40 * 16; /*sprites */ @@ -394,7 +394,7 @@ VIDEO_UPDATE( taitob ) VIDEO_EOF( taitob ) { - const device_config *tc0180vcu = devtag_get_device(machine, "tc0180vcu"); + const device_config *tc0180vcu = devtag_get_device(machine, "tc0180vcu"); UINT8 video_control = tc0180vcu_get_videoctrl(tc0180vcu, 0); UINT8 framebuffer_page = tc0180vcu_get_fb_page(tc0180vcu, 0); diff --git a/src/mame/video/taitoair.c b/src/mame/video/taitoair.c index 40d6db3938b..0ad16362b84 100644 --- a/src/mame/video/taitoair.c +++ b/src/mame/video/taitoair.c @@ -369,7 +369,7 @@ VIDEO_UPDATE( taitoair ) tc0080vco_tilemap_draw(tc0080vco, bitmap, cliprect, 2, 0, 0); - if (taitoair_line_ram[0x3fff]) + if (taitoair_line_ram[0x3fff]) { int adr = 0x3fff; struct poly q; @@ -378,10 +378,10 @@ VIDEO_UPDATE( taitoair ) view.x2 = cliprect->max_x; view.y2 = cliprect->max_y; - while(adr>=0 && taitoair_line_ram[adr] && taitoair_line_ram[adr] != 0x4000) + while(adr>=0 && taitoair_line_ram[adr] && taitoair_line_ram[adr] != 0x4000) { int pcount; - if(!(taitoair_line_ram[adr] & 0x8000) || adr < 10) + if(!(taitoair_line_ram[adr] & 0x8000) || adr < 10) { logerror("quad: unknown value %04x at %04x\n", taitoair_line_ram[adr], adr); break; @@ -389,7 +389,7 @@ VIDEO_UPDATE( taitoair ) q.col = (taitoair_line_ram[adr] & 0x7fff) + 0x300; adr--; pcount = 0; - while(pcount < POLY_MAX_PT && adr>=1 && !(taitoair_line_ram[adr] & 0xc000)) + while(pcount < POLY_MAX_PT && adr>=1 && !(taitoair_line_ram[adr] & 0xc000)) { q.p[pcount].y = taitoair_line_ram[adr]+3*16; q.p[pcount].x = taitoair_line_ram[adr-1]; diff --git a/src/mame/video/taitoic.c b/src/mame/video/taitoic.c index 7eec2dca8b7..41b06c8408f 100644 --- a/src/mame/video/taitoic.c +++ b/src/mame/video/taitoic.c @@ -1800,7 +1800,7 @@ void tc0080vco_tilemap_draw( const device_config *device, bitmap_t *bitmap, cons } } -/* FIXME: maybe it would be better to provide pointers to these RAM regions +/* FIXME: maybe it would be better to provide pointers to these RAM regions which can be accessed directly by the drivers... */ READ16_DEVICE_HANDLER( tc0080vco_cram_0_r ) { @@ -2504,7 +2504,7 @@ static DEVICE_START( tc0100scn ) tc0100scn_set_layer_ptrs(tc0100scn); - tc0100scn_set_colbanks(device, 0, 0, 0); /* standard values, only Wgp & multiscreen games change them */ + tc0100scn_set_colbanks(device, 0, 0, 0); /* standard values, only Wgp & multiscreen games change them */ /* we call this here, so that they can be modified at VIDEO_START*/ /* create the char set (gfx will then be updated dynamically from RAM) */ diff --git a/src/mame/video/warriorb.c b/src/mame/video/warriorb.c index 6af5587cc92..04be5b0feec 100644 --- a/src/mame/video/warriorb.c +++ b/src/mame/video/warriorb.c @@ -116,7 +116,7 @@ VIDEO_UPDATE( warriorb ) nodraw = tc0100scn_tilemap_draw(tc0100scn, bitmap, cliprect, layer[0], TILEMAP_DRAW_OPAQUE, 0); /* left */ /* Ensure screen blanked even when bottom layers not drawn due to disable bit */ - if (nodraw) + if (nodraw) bitmap_fill(bitmap, cliprect, get_black_pen(screen->machine)); // draw middle layer diff --git a/src/mame/video/wgp.c b/src/mame/video/wgp.c index 2c6a7a696a0..19f47f56386 100644 --- a/src/mame/video/wgp.c +++ b/src/mame/video/wgp.c @@ -51,7 +51,7 @@ static void wgp_core_vh_start(running_machine *machine, int piv_xoffs, int piv_y wgp_piv_tilemap[0] = tilemap_create(machine, get_piv0_tile_info, tilemap_scan_rows, 16, 16, 64, 64); wgp_piv_tilemap[1] = tilemap_create(machine, get_piv1_tile_info, tilemap_scan_rows, 16, 16, 64, 64); - wgp_piv_tilemap[2] = tilemap_create(machine, get_piv2_tile_info, tilemap_scan_rows, 16, 16, 64, 64); + wgp_piv_tilemap[2] = tilemap_create(machine, get_piv2_tile_info, tilemap_scan_rows, 16, 16, 64, 64); wgp_piv_xoffs = piv_xoffs; wgp_piv_yoffs = piv_yoffs; diff --git a/src/version.c b/src/version.c index 3f0f91a8282..af1c135da00 100644 --- a/src/version.c +++ b/src/version.c @@ -10,4 +10,4 @@ ***************************************************************************/ extern const char build_version[]; -const char build_version[] = "0.135u4 ("__DATE__")"; +const char build_version[] = "0.136 ("__DATE__")"; |