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author Aaron Giles <aaron@aarongiles.com>2008-05-29 07:18:35 +0000
committer Aaron Giles <aaron@aarongiles.com>2008-05-29 07:18:35 +0000
commiteeb821032e7556896ad4c4d26c79bddd9882a022 (patch)
tree7158cb382e055d636a685b8cbe5b2eb01d718c9e
parent9438e76f1fb759f0b4bbcae22231c3e75296179f (diff)
Several miscellaneous changes:
1. In the MIPS core: - renamed struct mips3_config -> mips3_config - updated all drivers to the new names - removed MIPS3DRC_STRICT_COP0 flag, which is no longer used - a few minor cleanups 2. In the CPU interface: - added new 'intention' parameter to the translate callback to indicate read/write/fetch access, user/supervisor mode, and a flag for debugging - updated all call sites to pass an appropriate value - updated all CPU cores to the new prototype 3. In the UML: - added new opcode SETC to set the carry flag from a source bit - added new opcode BSWAP to swap bytes within a value - updated C, x86, x64 back-ends to support the new opcodes - updated disassembler to support the new opcodes 4. In the DRC frontend: - fixed bug in handling edge case with the PC near the 0 or ~0
-rw-r--r--src/emu/cpu/drcbec.c29
-rw-r--r--src/emu/cpu/drcbex64.c124
-rw-r--r--src/emu/cpu/drcbex86.c132
-rw-r--r--src/emu/cpu/drcfe.c19
-rw-r--r--src/emu/cpu/drcuml.c8
-rw-r--r--src/emu/cpu/drcuml.h2
-rw-r--r--src/emu/cpu/drcumld.c2
-rw-r--r--src/emu/cpu/drcumlsh.h6
-rw-r--r--src/emu/cpu/h6280/h6280.c4
-rw-r--r--src/emu/cpu/i386/i386.c2
-rw-r--r--src/emu/cpu/m6502/m4510.c4
-rw-r--r--src/emu/cpu/mips/mips3.c4
-rw-r--r--src/emu/cpu/mips/mips3.h14
-rw-r--r--src/emu/cpu/mips/mips3com.c4
-rw-r--r--src/emu/cpu/mips/mips3com.h4
-rw-r--r--src/emu/cpu/mips/mips3drc.c135
-rw-r--r--src/emu/cpu/powerpc/ppc_mem.c2
-rw-r--r--src/emu/cpu/x86emit.h2
-rw-r--r--src/emu/cpu/z180/z180.c4
-rw-r--r--src/emu/cpuintrf.c4
-rw-r--r--src/emu/cpuintrf.h20
-rw-r--r--src/emu/debug/debugcmd.c16
-rw-r--r--src/emu/debug/debugcpu.c26
-rw-r--r--src/emu/debug/debugcpu.h8
-rw-r--r--src/emu/debug/debugvw.c20
-rw-r--r--src/emu/memory.h12
-rw-r--r--src/mame/drivers/aleck64.c2
-rw-r--r--src/mame/drivers/hng64.c2
-rw-r--r--src/mame/drivers/kinst.c2
-rw-r--r--src/mame/drivers/namcos23.c2
-rw-r--r--src/mame/drivers/seattle.c2
-rw-r--r--src/mame/drivers/vegas.c2
32 files changed, 466 insertions, 153 deletions
diff --git a/src/emu/cpu/drcbec.c b/src/emu/cpu/drcbec.c
index ff415ccf3e1..a0edfd84c06 100644
--- a/src/emu/cpu/drcbec.c
+++ b/src/emu/cpu/drcbec.c
@@ -720,6 +720,10 @@ static int drcbec_execute(drcbe_state *drcbe, drcuml_codehandle *entry)
PARAM0 = (PARAM0 & ~PARAM1) | (inst[2].puint32[flags & 0x1f] & PARAM1);
break;
+ case MAKE_OPCODE_SHORT(DRCUML_OP_SETC, 4, 0): /* SETC src,bitnum */
+ flags = (flags & ~DRCUML_FLAG_C) | ((PARAM0 >> (PARAM1 & 31)) & DRCUML_FLAG_C);
+ break;
+
case MAKE_OPCODE_SHORT(DRCUML_OP_MOV, 4, 1): /* MOV dst,src[,c] */
if (OPCODE_FAIL_CONDITION(opcode, flags))
break;
@@ -905,14 +909,13 @@ static int drcbec_execute(drcbe_state *drcbe, drcuml_codehandle *entry)
PARAM0 = temp32;
break;
- case MAKE_OPCODE_SHORT(DRCUML_OP_LZCNT, 4, 0): /* LZCNT dst,src[,f] */
+ case MAKE_OPCODE_SHORT(DRCUML_OP_LZCNT, 4, 0): /* LZCNT dst,src */
PARAM0 = count_leading_zeros(PARAM1);
break;
- case MAKE_OPCODE_SHORT(DRCUML_OP_LZCNT, 4, 1):
- temp32 = count_leading_zeros(PARAM1);
- flags = (temp32 == 0) ? DRCUML_FLAG_Z : 0;
- PARAM0 = temp32;
+ case MAKE_OPCODE_SHORT(DRCUML_OP_BSWAP, 4, 0): /* BSWAP dst,src */
+ temp32 = PARAM1;
+ PARAM0 = FLIPENDIAN_INT32(temp32);
break;
case MAKE_OPCODE_SHORT(DRCUML_OP_SHL, 4, 0): /* SHL dst,src,count[,f] */
@@ -1138,6 +1141,10 @@ static int drcbec_execute(drcbe_state *drcbe, drcuml_codehandle *entry)
DPARAM0 = (DPARAM0 & ~DPARAM1) | (inst[2].puint64[flags & 0x0f] & DPARAM1);
break;
+ case MAKE_OPCODE_SHORT(DRCUML_OP_SETC, 8, 0): /* DSETC src,bitnum */
+ flags = (flags & ~DRCUML_FLAG_C) | ((DPARAM0 >> (DPARAM1 & 63)) & DRCUML_FLAG_C);
+ break;
+
case MAKE_OPCODE_SHORT(DRCUML_OP_MOV, 8, 1): /* DMOV dst,src[,c] */
if (OPCODE_FAIL_CONDITION(opcode, flags))
break;
@@ -1321,20 +1328,16 @@ static int drcbec_execute(drcbe_state *drcbe, drcuml_codehandle *entry)
DPARAM0 = temp64;
break;
- case MAKE_OPCODE_SHORT(DRCUML_OP_LZCNT, 8, 0): /* DLZCNT dst,src[,f] */
+ case MAKE_OPCODE_SHORT(DRCUML_OP_LZCNT, 8, 0): /* DLZCNT dst,src */
if ((UINT32)(DPARAM1 >> 32) != 0)
DPARAM0 = count_leading_zeros(DPARAM1 >> 32);
else
DPARAM0 = 32 + count_leading_zeros(DPARAM1);
break;
- case MAKE_OPCODE_SHORT(DRCUML_OP_LZCNT, 8, 1):
- if ((UINT32)(DPARAM1 >> 32) != 0)
- temp32 = count_leading_zeros(DPARAM1 >> 32);
- else
- temp32 = 32 + count_leading_zeros(DPARAM1);
- flags = (temp32 == 0) ? DRCUML_FLAG_Z : 0;
- DPARAM0 = temp32;
+ case MAKE_OPCODE_SHORT(DRCUML_OP_BSWAP, 8, 0): /* DBSWAP dst,src */
+ temp64 = DPARAM1;
+ DPARAM0 = FLIPENDIAN_INT64(temp64);
break;
case MAKE_OPCODE_SHORT(DRCUML_OP_SHL, 8, 0): /* DSHL dst,src,count[,f] */
diff --git a/src/emu/cpu/drcbex64.c b/src/emu/cpu/drcbex64.c
index 211a5861836..7889a3e1fe4 100644
--- a/src/emu/cpu/drcbex64.c
+++ b/src/emu/cpu/drcbex64.c
@@ -428,6 +428,7 @@ static x86code *op_writ4m(drcbe_state *drcbe, x86code *dst, const drcuml_instruc
static x86code *op_write8(drcbe_state *drcbe, x86code *dst, const drcuml_instruction *inst);
static x86code *op_writ8m(drcbe_state *drcbe, x86code *dst, const drcuml_instruction *inst);
static x86code *op_flags(drcbe_state *drcbe, x86code *dst, const drcuml_instruction *inst);
+static x86code *op_setc(drcbe_state *drcbe, x86code *dst, const drcuml_instruction *inst);
static x86code *op_mov(drcbe_state *drcbe, x86code *dst, const drcuml_instruction *inst);
static x86code *op_zext1(drcbe_state *drcbe, x86code *dst, const drcuml_instruction *inst);
static x86code *op_zext2(drcbe_state *drcbe, x86code *dst, const drcuml_instruction *inst);
@@ -451,6 +452,7 @@ static x86code *op_test(drcbe_state *drcbe, x86code *dst, const drcuml_instructi
static x86code *op_or(drcbe_state *drcbe, x86code *dst, const drcuml_instruction *inst);
static x86code *op_xor(drcbe_state *drcbe, x86code *dst, const drcuml_instruction *inst);
static x86code *op_lzcnt(drcbe_state *drcbe, x86code *dst, const drcuml_instruction *inst);
+static x86code *op_bswap(drcbe_state *drcbe, x86code *dst, const drcuml_instruction *inst);
static x86code *op_shl(drcbe_state *drcbe, x86code *dst, const drcuml_instruction *inst);
static x86code *op_shr(drcbe_state *drcbe, x86code *dst, const drcuml_instruction *inst);
static x86code *op_sar(drcbe_state *drcbe, x86code *dst, const drcuml_instruction *inst);
@@ -546,6 +548,7 @@ static const opcode_table_entry opcode_table_source[] =
{ DRCUML_OP_WRITE8, op_write8 }, /* WRITE8 space,dst,src1 */
{ DRCUML_OP_WRIT8M, op_writ8m }, /* WRIT8M space,dst,mask,src1 */
{ DRCUML_OP_FLAGS, op_flags }, /* FLAGS dst,mask,table */
+ { DRCUML_OP_SETC, op_setc }, /* FLAGS src,bitnum */
{ DRCUML_OP_MOV, op_mov }, /* MOV dst,src[,c] */
{ DRCUML_OP_ZEXT1, op_zext1 }, /* ZEXT1 dst,src */
{ DRCUML_OP_ZEXT2, op_zext2 }, /* ZEXT2 dst,src */
@@ -569,6 +572,7 @@ static const opcode_table_entry opcode_table_source[] =
{ DRCUML_OP_OR, op_or }, /* OR dst,src1,src2[,f] */
{ DRCUML_OP_XOR, op_xor }, /* XOR dst,src1,src2[,f] */
{ DRCUML_OP_LZCNT, op_lzcnt }, /* LZCNT dst,src[,f] */
+ { DRCUML_OP_BSWAP, op_bswap }, /* BSWAP dst,src */
{ DRCUML_OP_SHL, op_shl }, /* SHL dst,src,count[,f] */
{ DRCUML_OP_SHR, op_shr }, /* SHR dst,src,count[,f] */
{ DRCUML_OP_SAR, op_sar }, /* SAR dst,src,count[,f] */
@@ -4818,6 +4822,79 @@ static x86code *op_flags(drcbe_state *drcbe, x86code *dst, const drcuml_instruct
/*-------------------------------------------------
+ op_setc - process a SETC opcode
+-------------------------------------------------*/
+
+static x86code *op_setc(drcbe_state *drcbe, x86code *dst, const drcuml_instruction *inst)
+{
+ drcuml_parameter srcp, bitp;
+
+ /* validate instruction */
+ assert(inst->size == 4 || inst->size == 8);
+ assert(inst->condflags == DRCUML_COND_ALWAYS);
+
+ /* normalize parameters */
+ param_normalize_2(drcbe, inst, &srcp, PTYPE_MRI, &bitp, PTYPE_MRI);
+
+ /* degenerate case: source is immediate */
+ if (srcp.type == DRCUML_PTYPE_IMMEDIATE && bitp.type == DRCUML_PTYPE_IMMEDIATE)
+ {
+ if (srcp.value & ((UINT64)1 << bitp.value))
+ emit_stc(&dst);
+ else
+ emit_clc(&dst);
+ return dst;
+ }
+
+ /* load non-immediate bit numbers into a register */
+ if (bitp.type != DRCUML_PTYPE_IMMEDIATE)
+ {
+ emit_mov_r32_p32(drcbe, &dst, REG_ECX, &bitp);
+ emit_and_r32_imm(&dst, REG_ECX, inst->size * 8 - 1);
+ }
+
+ /* 32-bit form */
+ if (inst->size == 4)
+ {
+ if (bitp.type == DRCUML_PTYPE_IMMEDIATE)
+ {
+ if (srcp.type == DRCUML_PTYPE_MEMORY)
+ emit_bt_m32_imm(&dst, MABS(srcp.value), bitp.value); // bt [srcp],bitp
+ else if (srcp.type == DRCUML_PTYPE_INT_REGISTER)
+ emit_bt_r32_imm(&dst, srcp.value, bitp.value); // bt srcp,bitp
+ }
+ else
+ {
+ if (srcp.type == DRCUML_PTYPE_MEMORY)
+ emit_bt_m32_r32(&dst, MABS(srcp.value), REG_ECX); // bt [srcp],ecx
+ else if (srcp.type == DRCUML_PTYPE_INT_REGISTER)
+ emit_bt_r32_r32(&dst, srcp.value, REG_ECX); // bt srcp,ecx
+ }
+ }
+
+ /* 64-bit form */
+ else
+ {
+ if (bitp.type == DRCUML_PTYPE_IMMEDIATE)
+ {
+ if (srcp.type == DRCUML_PTYPE_MEMORY)
+ emit_bt_m64_imm(&dst, MABS(srcp.value), bitp.value); // bt [srcp],bitp
+ else if (srcp.type == DRCUML_PTYPE_INT_REGISTER)
+ emit_bt_r64_imm(&dst, srcp.value, bitp.value); // bt srcp,bitp
+ }
+ else
+ {
+ if (srcp.type == DRCUML_PTYPE_MEMORY)
+ emit_bt_m64_r64(&dst, MABS(srcp.value), REG_ECX); // bt [srcp],ecx
+ else if (srcp.type == DRCUML_PTYPE_INT_REGISTER)
+ emit_bt_r64_r64(&dst, srcp.value, REG_ECX); // bt srcp,ecx
+ }
+ }
+ return dst;
+}
+
+
+/*-------------------------------------------------
op_mov - process a MOV opcode
-------------------------------------------------*/
@@ -6271,6 +6348,53 @@ static x86code *op_lzcnt(drcbe_state *drcbe, x86code *dst, const drcuml_instruct
/*-------------------------------------------------
+ op_bswap - process a BSWAP opcode
+-------------------------------------------------*/
+
+static x86code *op_bswap(drcbe_state *drcbe, x86code *dst, const drcuml_instruction *inst)
+{
+ drcuml_parameter dstp, srcp;
+ int dstreg;
+
+ /* validate instruction */
+ assert(inst->size == 4 || inst->size == 8);
+ assert(inst->condflags == 0);
+
+ /* normalize parameters */
+ param_normalize_2(drcbe, inst, &dstp, PTYPE_MR, &srcp, PTYPE_MRI);
+
+ /* degenerate cases -- convert to a move */
+ if (srcp.type == DRCUML_PTYPE_IMMEDIATE && inst->condflags == 0)
+ {
+ if (inst->size == 4)
+ return convert_to_mov_imm(drcbe, dst, inst, &dstp, FLIPENDIAN_INT32(srcp.value));
+ else if (inst->size == 8)
+ return convert_to_mov_imm(drcbe, dst, inst, &dstp, FLIPENDIAN_INT64(srcp.value));
+ }
+
+ /* pick a target register for the general case */
+ dstreg = param_select_register(REG_RAX, &dstp, &srcp);
+
+ /* 32-bit form */
+ if (inst->size == 4)
+ {
+ emit_mov_r32_p32(drcbe, &dst, dstreg, &srcp); // mov dstreg,src1p
+ emit_bswap_r32(&dst, dstreg); // bswap dstreg
+ emit_mov_p32_r32(drcbe, &dst, &dstp, dstreg); // mov dstp,dstreg
+ }
+
+ /* 64-bit form */
+ else if (inst->size == 8)
+ {
+ emit_mov_r64_p64(drcbe, &dst, dstreg, &srcp); // mov dstreg,src1p
+ emit_bswap_r64(&dst, dstreg); // bswap dstreg
+ emit_mov_p64_r64(drcbe, &dst, &dstp, dstreg); // mov dstp,dstreg
+ }
+ return dst;
+}
+
+
+/*-------------------------------------------------
op_shl - process a SHL opcode
-------------------------------------------------*/
diff --git a/src/emu/cpu/drcbex86.c b/src/emu/cpu/drcbex86.c
index 5e5373ad255..f31907451e9 100644
--- a/src/emu/cpu/drcbex86.c
+++ b/src/emu/cpu/drcbex86.c
@@ -314,6 +314,7 @@ static x86code *op_writ4m(drcbe_state *drcbe, x86code *dst, const drcuml_instruc
static x86code *op_write8(drcbe_state *drcbe, x86code *dst, const drcuml_instruction *inst);
static x86code *op_writ8m(drcbe_state *drcbe, x86code *dst, const drcuml_instruction *inst);
static x86code *op_flags(drcbe_state *drcbe, x86code *dst, const drcuml_instruction *inst);
+static x86code *op_setc(drcbe_state *drcbe, x86code *dst, const drcuml_instruction *inst);
static x86code *op_mov(drcbe_state *drcbe, x86code *dst, const drcuml_instruction *inst);
static x86code *op_zext1(drcbe_state *drcbe, x86code *dst, const drcuml_instruction *inst);
static x86code *op_zext2(drcbe_state *drcbe, x86code *dst, const drcuml_instruction *inst);
@@ -337,6 +338,7 @@ static x86code *op_test(drcbe_state *drcbe, x86code *dst, const drcuml_instructi
static x86code *op_or(drcbe_state *drcbe, x86code *dst, const drcuml_instruction *inst);
static x86code *op_xor(drcbe_state *drcbe, x86code *dst, const drcuml_instruction *inst);
static x86code *op_lzcnt(drcbe_state *drcbe, x86code *dst, const drcuml_instruction *inst);
+static x86code *op_bswap(drcbe_state *drcbe, x86code *dst, const drcuml_instruction *inst);
static x86code *op_shl(drcbe_state *drcbe, x86code *dst, const drcuml_instruction *inst);
static x86code *op_shr(drcbe_state *drcbe, x86code *dst, const drcuml_instruction *inst);
static x86code *op_sar(drcbe_state *drcbe, x86code *dst, const drcuml_instruction *inst);
@@ -432,6 +434,7 @@ static const opcode_table_entry opcode_table_source[] =
{ DRCUML_OP_WRITE8, op_write8 }, /* WRITE8 space,dst,src1 */
{ DRCUML_OP_WRIT8M, op_writ8m }, /* WRIT8M space,dst,mask,src1 */
{ DRCUML_OP_FLAGS, op_flags }, /* FLAGS dst,mask,table */
+ { DRCUML_OP_SETC, op_setc }, /* FLAGS src,bitnum */
{ DRCUML_OP_MOV, op_mov }, /* MOV dst,src[,c] */
{ DRCUML_OP_ZEXT1, op_zext1 }, /* ZEXT1 dst,src */
{ DRCUML_OP_ZEXT2, op_zext2 }, /* ZEXT2 dst,src */
@@ -455,6 +458,7 @@ static const opcode_table_entry opcode_table_source[] =
{ DRCUML_OP_OR, op_or }, /* OR dst,src1,src2[,f] */
{ DRCUML_OP_XOR, op_xor }, /* XOR dst,src1,src2[,f] */
{ DRCUML_OP_LZCNT, op_lzcnt }, /* LZCNT dst,src */
+ { DRCUML_OP_BSWAP, op_bswap }, /* BSWAP dst,src */
{ DRCUML_OP_SHL, op_shl }, /* SHL dst,src,count[,f] */
{ DRCUML_OP_SHR, op_shr }, /* SHR dst,src,count[,f] */
{ DRCUML_OP_SAR, op_sar }, /* SAR dst,src,count[,f] */
@@ -4879,6 +4883,84 @@ static x86code *op_flags(drcbe_state *drcbe, x86code *dst, const drcuml_instruct
/*-------------------------------------------------
+ op_setc - process a SETC opcode
+-------------------------------------------------*/
+
+static x86code *op_setc(drcbe_state *drcbe, x86code *dst, const drcuml_instruction *inst)
+{
+ drcuml_parameter srcp, bitp;
+
+ /* validate instruction */
+ assert(inst->size == 4 || inst->size == 8);
+ assert(inst->condflags == DRCUML_COND_ALWAYS);
+
+ /* normalize parameters */
+ param_normalize_2(drcbe, inst, &srcp, PTYPE_MRI, &bitp, PTYPE_MRI);
+
+ /* degenerate case: source is immediate */
+ if (srcp.type == DRCUML_PTYPE_IMMEDIATE && bitp.type == DRCUML_PTYPE_IMMEDIATE)
+ {
+ if (srcp.value & ((UINT64)1 << bitp.value))
+ emit_stc(&dst);
+ else
+ emit_clc(&dst);
+ return dst;
+ }
+
+ /* load non-immediate bit numbers into a register */
+ if (bitp.type != DRCUML_PTYPE_IMMEDIATE)
+ {
+ emit_mov_r32_p32(drcbe, &dst, REG_ECX, &bitp);
+ emit_and_r32_imm(&dst, REG_ECX, inst->size * 8 - 1);
+ }
+
+ /* 32-bit form */
+ if (inst->size == 4)
+ {
+ if (bitp.type == DRCUML_PTYPE_IMMEDIATE)
+ {
+ if (srcp.type == DRCUML_PTYPE_MEMORY)
+ emit_bt_m32_imm(&dst, MABS(srcp.value), bitp.value); // bt [srcp],bitp
+ else if (srcp.type == DRCUML_PTYPE_INT_REGISTER)
+ emit_bt_r32_imm(&dst, srcp.value, bitp.value); // bt srcp,bitp
+ }
+ else
+ {
+ if (srcp.type == DRCUML_PTYPE_MEMORY)
+ emit_bt_m32_r32(&dst, MABS(srcp.value), REG_ECX); // bt [srcp],ecx
+ else if (srcp.type == DRCUML_PTYPE_INT_REGISTER)
+ emit_bt_r32_r32(&dst, srcp.value, REG_ECX); // bt [srcp],ecx
+ }
+ }
+
+ /* 64-bit form */
+ else
+ {
+ if (bitp.type == DRCUML_PTYPE_IMMEDIATE)
+ {
+ if (srcp.type == DRCUML_PTYPE_MEMORY)
+ emit_bt_m32_imm(&dst, MABS(srcp.value), bitp.value); // bt [srcp],bitp
+ else if (srcp.type == DRCUML_PTYPE_INT_REGISTER && bitp.value < 32)
+ emit_bt_r32_imm(&dst, srcp.value, bitp.value); // bt srcp,bitp
+ else if (srcp.type == DRCUML_PTYPE_INT_REGISTER && bitp.value >= 32)
+ emit_bt_m32_imm(&dst, MABS(drcbe->reghi[srcp.value]), bitp.value - 32); // bt [srcp.hi],bitp
+ }
+ else
+ {
+ if (srcp.type == DRCUML_PTYPE_MEMORY)
+ emit_bt_m32_r32(&dst, MABS(srcp.value), REG_ECX); // bt [srcp],ecx
+ else if (srcp.type == DRCUML_PTYPE_INT_REGISTER)
+ {
+ emit_mov_m32_r32(&dst, MABS(drcbe->reglo[srcp.value]), srcp.value); // mov [srcp.lo],srcp
+ emit_bt_m32_r32(&dst, MABS(drcbe->reglo[srcp.value]), REG_ECX); // bt [srcp],ecx
+ }
+ }
+ }
+ return dst;
+}
+
+
+/*-------------------------------------------------
op_mov - process a MOV opcode
-------------------------------------------------*/
@@ -6398,7 +6480,7 @@ static x86code *op_lzcnt(drcbe_state *drcbe, x86code *dst, const drcuml_instruct
param_normalize_2(drcbe, inst, &dstp, PTYPE_MR, &srcp, PTYPE_MRI);
/* degenerate cases -- convert to a move */
- if (srcp.type == DRCUML_PTYPE_IMMEDIATE && inst->condflags == 0)
+ if (srcp.type == DRCUML_PTYPE_IMMEDIATE && inst->condflags == 0 && inst->size == 4)
return convert_to_mov_imm(drcbe, dst, inst, &dstp, count_leading_zeros(srcp.value));
/* pick a target register for the general case */
@@ -6435,6 +6517,54 @@ static x86code *op_lzcnt(drcbe_state *drcbe, x86code *dst, const drcuml_instruct
/*-------------------------------------------------
+ op_bswap - process a BSWAP opcode
+-------------------------------------------------*/
+
+static x86code *op_bswap(drcbe_state *drcbe, x86code *dst, const drcuml_instruction *inst)
+{
+ drcuml_parameter dstp, srcp;
+ int dstreg;
+
+ /* validate instruction */
+ assert(inst->size == 4 || inst->size == 8);
+ assert(inst->condflags == 0);
+
+ /* normalize parameters */
+ param_normalize_2(drcbe, inst, &dstp, PTYPE_MR, &srcp, PTYPE_MRI);
+
+ /* degenerate cases -- convert to a move */
+ if (srcp.type == DRCUML_PTYPE_IMMEDIATE && inst->condflags == 0)
+ {
+ if (inst->size == 4)
+ return convert_to_mov_imm(drcbe, dst, inst, &dstp, FLIPENDIAN_INT32(srcp.value));
+ else if (inst->size == 8)
+ return convert_to_mov_imm(drcbe, dst, inst, &dstp, FLIPENDIAN_INT64(srcp.value));
+ }
+
+ /* pick a target register for the general case */
+ dstreg = param_select_register(REG_EAX, &dstp, &srcp);
+
+ /* 32-bit form */
+ if (inst->size == 4)
+ {
+ emit_mov_r32_p32(drcbe, &dst, dstreg, &srcp); // mov dstreg,src1p
+ emit_bswap_r32(&dst, dstreg); // bswap dstreg
+ emit_mov_p32_r32(drcbe, &dst, &dstp, dstreg); // mov dstp,dstreg
+ }
+
+ /* 64-bit form */
+ else if (inst->size == 8)
+ {
+ emit_mov_r64_p64(drcbe, &dst, REG_EDX, dstreg, &srcp); // mov dstreg:edx,srcp
+ emit_bswap_r32(&dst, dstreg); // bswap dstreg
+ emit_bswap_r32(&dst, REG_EDX); // bswap edx
+ emit_mov_p64_r64(drcbe, &dst, &dstp, REG_EDX, dstreg); // mov dstp,dstreg:edx
+ }
+ return dst;
+}
+
+
+/*-------------------------------------------------
op_shl - process a SHL opcode
-------------------------------------------------*/
diff --git a/src/emu/cpu/drcfe.c b/src/emu/cpu/drcfe.c
index 45815cef256..012f4b4cff8 100644
--- a/src/emu/cpu/drcfe.c
+++ b/src/emu/cpu/drcfe.c
@@ -8,6 +8,19 @@
Released for general non-commercial use under the MAME license
Visit http://mamedev.org for licensing and usage restrictions.
+****************************************************************************
+
+ Future improvements/changes:
+
+ * change from detecting live to detecting unnecessary
+ - at the end of sequence: mustupdate.all = TRUE;
+ - scan backwards:
+ inst.mustupdate = inst.update & mustupdate;
+ if (inst.modified.reg) mustupdate.reg = FALSE;
+ if (inst.used.reg) mustupdate.reg = TRUE;
+
+ * rename UINT64 gpr, fpr to UINT32 reg[4]
+
***************************************************************************/
#include <stddef.h>
@@ -175,8 +188,8 @@ void drcfe_exit(drcfe_state *drcfe)
const opcode_desc *drcfe_describe_code(drcfe_state *drcfe, offs_t startpc)
{
- offs_t minpc = startpc - drcfe->window_start;
- offs_t maxpc = startpc + drcfe->window_end;
+ offs_t minpc = startpc - MIN(drcfe->window_start, startpc);
+ offs_t maxpc = startpc + MIN(drcfe->window_end, 0xffffffff - startpc);
pc_stack_entry pcstack[MAX_STACK_DEPTH];
pc_stack_entry *pcstackptr = &pcstack[0];
opcode_desc **tailptr;
@@ -274,7 +287,7 @@ static opcode_desc *describe_one(drcfe_state *drcfe, offs_t curpc)
desc->targetpc = BRANCH_TARGET_DYNAMIC;
/* compute the physical PC */
- if (drcfe->translate != NULL && !(*drcfe->translate)(ADDRESS_SPACE_PROGRAM, &desc->physpc))
+ if (drcfe->translate != NULL && !(*drcfe->translate)(ADDRESS_SPACE_PROGRAM, TRANSLATE_FETCH, &desc->physpc))
{
/* uh-oh: a page fault; leave the description empty and just if this is the first instruction, leave it empty and */
/* mark as needing to validate; otherwise, just end the sequence here */
diff --git a/src/emu/cpu/drcuml.c b/src/emu/cpu/drcuml.c
index de97a317e8a..a86ca7dd555 100644
--- a/src/emu/cpu/drcuml.c
+++ b/src/emu/cpu/drcuml.c
@@ -21,6 +21,12 @@
* Support for FPU exceptions
* New instructions?
+ - FDRNDS dst,src
+ round to single-precision
+
+ - FCOPYI, ICOPYF
+ copy raw between float and integer registers
+
- VALID opcode_desc,handle,param
checksum/compare code referenced by opcode_desc; if not
matching, generate exception with handle,param
@@ -228,6 +234,7 @@ static const drcuml_opcode_valid opcode_valid_list[] =
OPVALID_ENTRY_3(WRITE8, 8, NONE, IMV4, IANY4, IANY)
OPVALID_ENTRY_4(WRIT8M, 8, NONE, IMV4, IANY4, IANY, IANY)
OPVALID_ENTRY_3(FLAGS, 4|8, NONE, IRM, IMV, MEM)
+ OPVALID_ENTRY_2(SETC, 4|8, NONE, IANY, IANY)
OPVALID_ENTRY_2(MOV, 4|8, COND, IRM, IANY)
OPVALID_ENTRY_2(ZEXT1, 4|8, NONE, IRM, IANY4)
OPVALID_ENTRY_2(ZEXT2, 4|8, NONE, IRM, IANY4)
@@ -251,6 +258,7 @@ static const drcuml_opcode_valid opcode_valid_list[] =
OPVALID_ENTRY_3(OR, 4|8, SZ, IRM, IANY, IANY)
OPVALID_ENTRY_3(XOR, 4|8, SZ, IRM, IANY, IANY)
OPVALID_ENTRY_2(LZCNT, 4|8, NONE, IRM, IANY)
+ OPVALID_ENTRY_2(BSWAP, 4|8, NONE, IRM, IANY)
OPVALID_ENTRY_3(SHL, 4|8, SZC, IRM, IANY, IANY)
OPVALID_ENTRY_3(SHR, 4|8, SZC, IRM, IANY, IANY)
OPVALID_ENTRY_3(SAR, 4|8, SZC, IRM, IANY, IANY)
diff --git a/src/emu/cpu/drcuml.h b/src/emu/cpu/drcuml.h
index df3d4a5c7fb..c3200150ff0 100644
--- a/src/emu/cpu/drcuml.h
+++ b/src/emu/cpu/drcuml.h
@@ -208,6 +208,7 @@ enum _drcuml_opcode
DRCUML_OP_WRIT4M, /* WRIT4M space,dst,mask,src1 */
DRCUML_OP_WRITE8, /* WRITE8 space,dst,src1 */
DRCUML_OP_WRIT8M, /* WRIT8M space,dst,mask,src1 */
+ DRCUML_OP_SETC, /* SETC src,bitnum */
DRCUML_OP_FLAGS, /* FLAGS dst,mask,table */
DRCUML_OP_MOV, /* MOV dst,src[,c] */
DRCUML_OP_ZEXT1, /* ZEXT1 dst,src */
@@ -232,6 +233,7 @@ enum _drcuml_opcode
DRCUML_OP_OR, /* OR dst,src1,src2[,f] */
DRCUML_OP_XOR, /* XOR dst,src1,src2[,f] */
DRCUML_OP_LZCNT, /* LZCNT dst,src */
+ DRCUML_OP_BSWAP, /* BSWAP dst,src */
DRCUML_OP_SHL, /* SHL dst,src,count[,f] */
DRCUML_OP_SHR, /* SHR dst,src,count[,f] */
DRCUML_OP_SAR, /* SAR dst,src,count[,f] */
diff --git a/src/emu/cpu/drcumld.c b/src/emu/cpu/drcumld.c
index 8d68cd7702f..127b3d8bcea 100644
--- a/src/emu/cpu/drcumld.c
+++ b/src/emu/cpu/drcumld.c
@@ -122,6 +122,7 @@ static const drcuml_opdesc opcode_source_table[] =
{ DRCUML_OP_WRITE8, "!write8", { output_param_space, output_param, output_param } },
{ DRCUML_OP_WRIT8M, "!writ8m", { output_param_space, output_param, output_param, output_param } },
{ DRCUML_OP_FLAGS, "!flags", { output_param, output_param, output_param } },
+ { DRCUML_OP_SETC, "!setc", { output_param, output_param } },
{ DRCUML_OP_MOV, "!mov", { output_param, output_param, output_cond } },
{ DRCUML_OP_ZEXT1, "!zext1", { output_param, output_param } },
{ DRCUML_OP_ZEXT2, "!zext2", { output_param, output_param } },
@@ -145,6 +146,7 @@ static const drcuml_opdesc opcode_source_table[] =
{ DRCUML_OP_OR, "!or", { output_param, output_param, output_param, output_flags } },
{ DRCUML_OP_XOR, "!xor", { output_param, output_param, output_param, output_flags } },
{ DRCUML_OP_LZCNT, "!lzcnt", { output_param, output_param } },
+ { DRCUML_OP_BSWAP, "!bswap", { output_param, output_param } },
{ DRCUML_OP_SHL, "!shl", { output_param, output_param, output_param, output_flags } },
{ DRCUML_OP_SHR, "!shr", { output_param, output_param, output_param, output_flags } },
{ DRCUML_OP_SAR, "!sar", { output_param, output_param, output_param, output_flags } },
diff --git a/src/emu/cpu/drcumlsh.h b/src/emu/cpu/drcumlsh.h
index 02dcc637fcc..a3543aaee7e 100644
--- a/src/emu/cpu/drcumlsh.h
+++ b/src/emu/cpu/drcumlsh.h
@@ -151,15 +151,18 @@
#define UML_READ1S(block, dst, space, src1) do { drcuml_block_append_3(block, DRCUML_OP_READ1S, 4, IF_ALWAYS, dst, IMM(ADDRESS_SPACE_##space), src1); } while (0)
#define UML_READ2U(block, dst, space, src1) do { drcuml_block_append_3(block, DRCUML_OP_READ2U, 4, IF_ALWAYS, dst, IMM(ADDRESS_SPACE_##space), src1); } while (0)
#define UML_READ2S(block, dst, space, src1) do { drcuml_block_append_3(block, DRCUML_OP_READ2S, 4, IF_ALWAYS, dst, IMM(ADDRESS_SPACE_##space), src1); } while (0)
+#define UML_READ2M(block, dst, space, src1, mask) do { drcuml_block_append_4(block, DRCUML_OP_READ2M, 4, IF_ALWAYS, dst, IMM(ADDRESS_SPACE_##space), src1, mask); } while (0)
#define UML_READ4(block, dst, space, src1) do { drcuml_block_append_3(block, DRCUML_OP_READ4U, 4, IF_ALWAYS, dst, IMM(ADDRESS_SPACE_##space), src1); } while (0)
#define UML_READ4M(block, dst, space, src1, mask) do { drcuml_block_append_4(block, DRCUML_OP_READ4M, 4, IF_ALWAYS, dst, IMM(ADDRESS_SPACE_##space), src1, mask); } while (0)
#define UML_WRITE1(block, space, dst, src1) do { drcuml_block_append_3(block, DRCUML_OP_WRITE1, 4, IF_ALWAYS, IMM(ADDRESS_SPACE_##space), dst, src1); } while (0)
#define UML_WRITE2(block, space, dst, src1) do { drcuml_block_append_3(block, DRCUML_OP_WRITE2, 4, IF_ALWAYS, IMM(ADDRESS_SPACE_##space), dst, src1); } while (0)
+#define UML_WRIT2M(block, space, dst, mask, src1) do { drcuml_block_append_4(block, DRCUML_OP_WRIT2M, 4, IF_ALWAYS, IMM(ADDRESS_SPACE_##space), dst, mask, src1); } while (0)
#define UML_WRITE4(block, space, dst, src1) do { drcuml_block_append_3(block, DRCUML_OP_WRITE4, 4, IF_ALWAYS, IMM(ADDRESS_SPACE_##space), dst, src1); } while (0)
#define UML_WRIT4M(block, space, dst, mask, src1) do { drcuml_block_append_4(block, DRCUML_OP_WRIT4M, 4, IF_ALWAYS, IMM(ADDRESS_SPACE_##space), dst, mask, src1); } while (0)
#define UML_FLAGS(block, dst, mask, table) do { drcuml_block_append_3(block, DRCUML_OP_FLAGS, 4, IF_ALWAYS, dst, IMM(mask), MEM(table)); } while (0)
+#define UML_SETC(block, src, bitnum) do { drcuml_block_append_2(block, DRCUML_OP_SETC, 4, IF_ALWAYS, src, bitnum); } while (0)
#define UML_MOV(block, dst, src1) do { drcuml_block_append_2(block, DRCUML_OP_MOV, 4, IF_ALWAYS, dst, src1); } while (0)
#define UML_MOVc(block, cond, dst, src1) do { drcuml_block_append_2(block, DRCUML_OP_MOV, 4, cond, dst, src1); } while (0)
@@ -211,6 +214,9 @@
#define UML_XOR(block, dst, src1, src2) do { drcuml_block_append_3(block, DRCUML_OP_XOR, 4, FLAGS_NONE, dst, src1, src2); } while (0)
#define UML_XORf(block, dst, src1, src2, flags) do { drcuml_block_append_3(block, DRCUML_OP_XOR, 4, flags, dst, src1, src2); } while (0)
+#define UML_LZCNT(block, dst, src) do { drcuml_block_append_2(block, DRCUML_OP_LZCNT, 4, FLAGS_NONE, dst, src); } while (0)
+#define UML_BSWAP(block, dst, src) do { drcuml_block_append_2(block, DRCUML_OP_BSWAP, 4, FLAGS_NONE, dst, src); } while (0)
+
#define UML_SHL(block, dst, src, count) do { drcuml_block_append_3(block, DRCUML_OP_SHL, 4, FLAGS_NONE, dst, src, count); } while (0)
#define UML_SHLf(block, dst, src, count, flags) do { drcuml_block_append_3(block, DRCUML_OP_SHL, 4, flags, dst, src, count); } while (0)
diff --git a/src/emu/cpu/h6280/h6280.c b/src/emu/cpu/h6280/h6280.c
index a7b8a8568a6..2c898b4f661 100644
--- a/src/emu/cpu/h6280/h6280.c
+++ b/src/emu/cpu/h6280/h6280.c
@@ -379,11 +379,11 @@ WRITE8_HANDLER( H6280_timer_w )
}
}
-static int h6280_translate(int space, offs_t *addr)
+static int h6280_translate(int space, int intention, offs_t *addr)
{
if (space == ADDRESS_SPACE_PROGRAM)
*addr = TRANSLATED(*addr);
- return 1;
+ return TRUE;
}
UINT8 h6280io_get_buffer()
diff --git a/src/emu/cpu/i386/i386.c b/src/emu/cpu/i386/i386.c
index 01fab039571..6182137d941 100644
--- a/src/emu/cpu/i386/i386.c
+++ b/src/emu/cpu/i386/i386.c
@@ -729,7 +729,7 @@ static int i386_execute(int num_cycles)
/*************************************************************************/
-static int translate_address_cb(int space, offs_t *addr)
+static int translate_address_cb(int space, int intention, offs_t *addr)
{
int result = 1;
if (space == ADDRESS_SPACE_PROGRAM)
diff --git a/src/emu/cpu/m6502/m4510.c b/src/emu/cpu/m6502/m4510.c
index 4986bfcf411..42d77a4f874 100644
--- a/src/emu/cpu/m6502/m4510.c
+++ b/src/emu/cpu/m6502/m4510.c
@@ -371,11 +371,11 @@ static ADDRESS_MAP_START(m4510_mem, ADDRESS_SPACE_PROGRAM, 8)
AM_RANGE(0x0000, 0x0001) AM_READWRITE(m4510_read_0000, m4510_write_0000)
ADDRESS_MAP_END
-static int m4510_translate(int space, offs_t *addr)
+static int m4510_translate(int space, int intention, offs_t *addr)
{
if (space == ADDRESS_SPACE_PROGRAM)
*addr = M4510_MEM(*addr);
- return 1;
+ return TRUE;
}
/**************************************************************************
diff --git a/src/emu/cpu/mips/mips3.c b/src/emu/cpu/mips/mips3.c
index fa7e9c92e8a..78d7a097813 100644
--- a/src/emu/cpu/mips/mips3.c
+++ b/src/emu/cpu/mips/mips3.c
@@ -290,10 +290,10 @@ static void mips3_reset(void)
}
-static int mips3_translate(int space, offs_t *address)
+static int mips3_translate(int space, int intention, offs_t *address)
{
/* common translate */
- return mips3com_translate_address(&mips3.core, space, address);
+ return mips3com_translate_address(&mips3.core, space, intention, address);
}
diff --git a/src/emu/cpu/mips/mips3.h b/src/emu/cpu/mips/mips3.h
index 3ab8ec82ec8..e92d9edbffb 100644
--- a/src/emu/cpu/mips/mips3.h
+++ b/src/emu/cpu/mips/mips3.h
@@ -204,7 +204,8 @@ enum
STRUCTURES
***************************************************************************/
-struct mips3_config
+typedef struct _mips3_config mips3_config;
+struct _mips3_config
{
size_t icache; /* code cache size */
size_t dcache; /* data cache size */
@@ -250,13 +251,12 @@ void rm7000le_get_info(UINT32 state, cpuinfo *info);
/* fix me -- how do we make this work?? */
#define MIPS3DRC_STRICT_VERIFY 0x0001 /* verify all instructions */
-#define MIPS3DRC_STRICT_COP0 0x0002 /* validate all COP0 instructions */
-#define MIPS3DRC_STRICT_COP1 0x0004 /* validate all COP1 instructions */
-#define MIPS3DRC_STRICT_COP2 0x0008 /* validate all COP2 instructions */
-#define MIPS3DRC_FLUSH_PC 0x0020 /* flush the PC value before each memory access */
-#define MIPS3DRC_CHECK_OVERFLOWS 0x0040 /* actually check overflows on add/sub instructions */
+#define MIPS3DRC_STRICT_COP1 0x0002 /* validate all COP1 instructions */
+#define MIPS3DRC_STRICT_COP2 0x0004 /* validate all COP2 instructions */
+#define MIPS3DRC_FLUSH_PC 0x0008 /* flush the PC value before each memory access */
+#define MIPS3DRC_CHECK_OVERFLOWS 0x0010 /* actually check overflows on add/sub instructions */
-#define MIPS3DRC_COMPATIBLE_OPTIONS (MIPS3DRC_STRICT_VERIFY | MIPS3DRC_STRICT_COP0 | MIPS3DRC_STRICT_COP1 | MIPS3DRC_STRICT_COP2 | MIPS3DRC_FLUSH_PC)
+#define MIPS3DRC_COMPATIBLE_OPTIONS (MIPS3DRC_STRICT_VERIFY | MIPS3DRC_STRICT_COP1 | MIPS3DRC_STRICT_COP2 | MIPS3DRC_FLUSH_PC)
#define MIPS3DRC_FASTEST_OPTIONS (0)
diff --git a/src/emu/cpu/mips/mips3com.c b/src/emu/cpu/mips/mips3com.c
index 806cee03880..6bbd9e3ff35 100644
--- a/src/emu/cpu/mips/mips3com.c
+++ b/src/emu/cpu/mips/mips3com.c
@@ -40,7 +40,7 @@ static void tlb_entry_log_half(mips3_tlb_entry *tlbent, int index, int which);
structure based on the configured type
-------------------------------------------------*/
-size_t mips3com_init(mips3_state *mips, mips3_flavor flavor, int bigendian, int index, int clock, const struct mips3_config *config, int (*irqcallback)(int), void *memory)
+size_t mips3com_init(mips3_state *mips, mips3_flavor flavor, int bigendian, int index, int clock, const mips3_config *config, int (*irqcallback)(int), void *memory)
{
int tlbindex;
@@ -257,7 +257,7 @@ void mips3com_recompute_tlb_table(mips3_state *mips)
from logical to physical
-------------------------------------------------*/
-int mips3com_translate_address(mips3_state *mips, int space, offs_t *address)
+int mips3com_translate_address(mips3_state *mips, int space, int intention, offs_t *address)
{
/* only applies to the program address space */
if (space == ADDRESS_SPACE_PROGRAM)
diff --git a/src/emu/cpu/mips/mips3com.h b/src/emu/cpu/mips/mips3com.h
index a132db47615..d01ca3d1d6f 100644
--- a/src/emu/cpu/mips/mips3com.h
+++ b/src/emu/cpu/mips/mips3com.h
@@ -213,7 +213,7 @@ struct _mips3_state
FUNCTION PROTOTYPES
***************************************************************************/
-size_t mips3com_init(mips3_state *mips, mips3_flavor flavor, int bigendian, int index, int clock, const struct mips3_config *config, int (*irqcallback)(int), void *memory);
+size_t mips3com_init(mips3_state *mips, mips3_flavor flavor, int bigendian, int index, int clock, const mips3_config *config, int (*irqcallback)(int), void *memory);
void mips3com_reset(mips3_state *mips);
#ifdef ENABLE_DEBUGGER
offs_t mips3com_dasm(mips3_state *mips, char *buffer, offs_t pc, const UINT8 *oprom, const UINT8 *opram);
@@ -223,7 +223,7 @@ void mips3com_update_cycle_counting(mips3_state *mips);
void mips3com_map_tlb_entries(mips3_state *mips);
void mips3com_unmap_tlb_entries(mips3_state *mips);
void mips3com_recompute_tlb_table(mips3_state *mips);
-int mips3com_translate_address(mips3_state *mips, int space, offs_t *address);
+int mips3com_translate_address(mips3_state *mips, int space, int intention, offs_t *address);
void mips3com_tlbr(mips3_state *mips);
void mips3com_tlbwi(mips3_state *mips);
void mips3com_tlbwr(mips3_state *mips);
diff --git a/src/emu/cpu/mips/mips3drc.c b/src/emu/cpu/mips/mips3drc.c
index 12edc091528..ddad017e528 100644
--- a/src/emu/cpu/mips/mips3drc.c
+++ b/src/emu/cpu/mips/mips3drc.c
@@ -11,6 +11,8 @@
****************************************************************************
Future improvements/changes:
+
+ * Move context to a pointer to reduce context switch times
* Add DRC option to flush PC before calling memory handlers
@@ -691,7 +693,7 @@ INLINE void save_fast_iregs(drcuml_block *block)
mips3_init - initialize the processor
-------------------------------------------------*/
-static void mips3_init(mips3_flavor flavor, int bigendian, int index, int clock, const struct mips3_config *config, int (*irqcallback)(int))
+static void mips3_init(mips3_flavor flavor, int bigendian, int index, int clock, const mips3_config *config, int (*irqcallback)(int))
{
drcfe_config feconfig =
{
@@ -878,9 +880,9 @@ static void mips3_set_context(void *src)
address translation
-------------------------------------------------*/
-static int mips3_translate(int space, offs_t *address)
+static int mips3_translate(int space, int intention, offs_t *address)
{
- return mips3com_translate_address(mips3.core, space, address);
+ return mips3com_translate_address(mips3.core, space, intention, address);
}
@@ -897,6 +899,72 @@ static offs_t mips3_dasm(char *buffer, offs_t pc, const UINT8 *oprom, const UINT
+/*-------------------------------------------------
+ mips3_set_info - set information about a given
+ CPU instance
+-------------------------------------------------*/
+
+static void mips3_set_info(UINT32 state, cpuinfo *info)
+{
+ switch (state)
+ {
+ /* --- the following bits of info are set as 64-bit signed integers --- */
+ case CPUINFO_INT_MIPS3_DRC_OPTIONS: mips3.drcoptions = info->i; break;
+
+ case CPUINFO_INT_MIPS3_FASTRAM_SELECT: if (info->i >= 0 && info->i < MIPS3_MAX_FASTRAM) mips3.fastram_select = info->i; mips3.cache_dirty = TRUE; break;
+ case CPUINFO_INT_MIPS3_FASTRAM_START: mips3.fastram[mips3.fastram_select].start = info->i; mips3.cache_dirty = TRUE; break;
+ case CPUINFO_INT_MIPS3_FASTRAM_END: mips3.fastram[mips3.fastram_select].end = info->i; mips3.cache_dirty = TRUE; break;
+ case CPUINFO_INT_MIPS3_FASTRAM_READONLY: mips3.fastram[mips3.fastram_select].readonly = info->i; mips3.cache_dirty = TRUE; break;
+
+ case CPUINFO_INT_MIPS3_HOTSPOT_SELECT: if (info->i >= 0 && info->i < MIPS3_MAX_HOTSPOTS) mips3.hotspot_select = info->i; mips3.cache_dirty = TRUE; break;
+ case CPUINFO_INT_MIPS3_HOTSPOT_PC: mips3.hotspot[mips3.hotspot_select].pc = info->i; mips3.cache_dirty = TRUE; break;
+ case CPUINFO_INT_MIPS3_HOTSPOT_OPCODE: mips3.hotspot[mips3.hotspot_select].opcode = info->i; mips3.cache_dirty = TRUE; break;
+ case CPUINFO_INT_MIPS3_HOTSPOT_CYCLES: mips3.hotspot[mips3.hotspot_select].cycles = info->i; mips3.cache_dirty = TRUE; break;
+
+ /* --- the following bits of info are set as pointers to data or functions --- */
+ case CPUINFO_PTR_MIPS3_FASTRAM_BASE: mips3.fastram[mips3.fastram_select].base = info->p; break;
+
+ /* --- everything else is handled generically --- */
+ default: mips3com_set_info(mips3.core, state, info); break;
+ }
+}
+
+
+/*-------------------------------------------------
+ mips3_get_info - return information about a
+ given CPU instance
+-------------------------------------------------*/
+
+static void mips3_get_info(UINT32 state, cpuinfo *info)
+{
+ switch (state)
+ {
+ /* --- the following bits of info are returned as 64-bit signed integers --- */
+ case CPUINFO_INT_CONTEXT_SIZE: info->i = sizeof(mips3); break;
+ case CPUINFO_INT_PREVIOUSPC: /* not implemented */ break;
+
+ /* --- the following bits of info are returned as pointers to data or functions --- */
+ case CPUINFO_PTR_SET_INFO: info->setinfo = mips3_set_info; break;
+ case CPUINFO_PTR_GET_CONTEXT: info->getcontext = mips3_get_context; break;
+ case CPUINFO_PTR_SET_CONTEXT: info->setcontext = mips3_set_context; break;
+ case CPUINFO_PTR_INIT: /* provided per-CPU */ break;
+ case CPUINFO_PTR_RESET: info->reset = mips3_reset; break;
+ case CPUINFO_PTR_EXIT: info->exit = mips3_exit; break;
+ case CPUINFO_PTR_EXECUTE: info->execute = mips3_execute; break;
+#ifdef ENABLE_DEBUGGER
+ case CPUINFO_PTR_DISASSEMBLE: info->disassemble = mips3_dasm; break;
+#endif /* ENABLE_DEBUGGER */
+ case CPUINFO_PTR_TRANSLATE: info->translate = mips3_translate; break;
+
+ /* --- the following bits of info are returned as NULL-terminated strings --- */
+ case CPUINFO_STR_CORE_FILE: strcpy(info->s, __FILE__); break;
+
+ /* --- everything else is handled generically --- */
+ default: mips3com_get_info(mips3.core, state, info); break;
+ }
+}
+
+
/***************************************************************************
CACHE MANAGEMENT
@@ -3755,67 +3823,6 @@ static void log_opcode_desc(drcuml_state *drcuml, const opcode_desc *desclist, i
/***************************************************************************
- GENERIC GET/SET INFO
-***************************************************************************/
-
-static void mips3_set_info(UINT32 state, cpuinfo *info)
-{
- switch (state)
- {
- /* --- the following bits of info are set as 64-bit signed integers --- */
- case CPUINFO_INT_MIPS3_DRC_OPTIONS: mips3.drcoptions = info->i; break;
-
- case CPUINFO_INT_MIPS3_FASTRAM_SELECT: if (info->i >= 0 && info->i < MIPS3_MAX_FASTRAM) mips3.fastram_select = info->i; mips3.cache_dirty = TRUE; break;
- case CPUINFO_INT_MIPS3_FASTRAM_START: mips3.fastram[mips3.fastram_select].start = info->i; mips3.cache_dirty = TRUE; break;
- case CPUINFO_INT_MIPS3_FASTRAM_END: mips3.fastram[mips3.fastram_select].end = info->i; mips3.cache_dirty = TRUE; break;
- case CPUINFO_INT_MIPS3_FASTRAM_READONLY: mips3.fastram[mips3.fastram_select].readonly = info->i; mips3.cache_dirty = TRUE; break;
-
- case CPUINFO_INT_MIPS3_HOTSPOT_SELECT: if (info->i >= 0 && info->i < MIPS3_MAX_HOTSPOTS) mips3.hotspot_select = info->i; mips3.cache_dirty = TRUE; break;
- case CPUINFO_INT_MIPS3_HOTSPOT_PC: mips3.hotspot[mips3.hotspot_select].pc = info->i; mips3.cache_dirty = TRUE; break;
- case CPUINFO_INT_MIPS3_HOTSPOT_OPCODE: mips3.hotspot[mips3.hotspot_select].opcode = info->i; mips3.cache_dirty = TRUE; break;
- case CPUINFO_INT_MIPS3_HOTSPOT_CYCLES: mips3.hotspot[mips3.hotspot_select].cycles = info->i; mips3.cache_dirty = TRUE; break;
-
- /* --- the following bits of info are set as pointers to data or functions --- */
- case CPUINFO_PTR_MIPS3_FASTRAM_BASE: mips3.fastram[mips3.fastram_select].base = info->p; break;
-
- /* --- everything else is handled generically --- */
- default: mips3com_set_info(mips3.core, state, info); break;
- }
-}
-
-
-static void mips3_get_info(UINT32 state, cpuinfo *info)
-{
- switch (state)
- {
- /* --- the following bits of info are returned as 64-bit signed integers --- */
- case CPUINFO_INT_CONTEXT_SIZE: info->i = sizeof(mips3); break;
- case CPUINFO_INT_PREVIOUSPC: /* not implemented */ break;
-
- /* --- the following bits of info are returned as pointers to data or functions --- */
- case CPUINFO_PTR_SET_INFO: info->setinfo = mips3_set_info; break;
- case CPUINFO_PTR_GET_CONTEXT: info->getcontext = mips3_get_context; break;
- case CPUINFO_PTR_SET_CONTEXT: info->setcontext = mips3_set_context; break;
- case CPUINFO_PTR_INIT: /* provided per-CPU */ break;
- case CPUINFO_PTR_RESET: info->reset = mips3_reset; break;
- case CPUINFO_PTR_EXIT: info->exit = mips3_exit; break;
- case CPUINFO_PTR_EXECUTE: info->execute = mips3_execute; break;
-#ifdef ENABLE_DEBUGGER
- case CPUINFO_PTR_DISASSEMBLE: info->disassemble = mips3_dasm; break;
-#endif /* ENABLE_DEBUGGER */
- case CPUINFO_PTR_TRANSLATE: info->translate = mips3_translate; break;
-
- /* --- the following bits of info are returned as NULL-terminated strings --- */
- case CPUINFO_STR_CORE_FILE: strcpy(info->s, __FILE__); break;
-
- /* --- everything else is handled generically --- */
- default: mips3com_get_info(mips3.core, state, info); break;
- }
-}
-
-
-
-/***************************************************************************
R4600 VARIANTS
***************************************************************************/
diff --git a/src/emu/cpu/powerpc/ppc_mem.c b/src/emu/cpu/powerpc/ppc_mem.c
index c96002751ab..47f9b2f17f2 100644
--- a/src/emu/cpu/powerpc/ppc_mem.c
+++ b/src/emu/cpu/powerpc/ppc_mem.c
@@ -297,7 +297,7 @@ exception:
}
#if (HAS_PPC602||HAS_PPC603)
-static int ppc_translate_address_cb(int space, offs_t *addr)
+static int ppc_translate_address_cb(int space, int intention, offs_t *addr)
{
int success = 1;
diff --git a/src/emu/cpu/x86emit.h b/src/emu/cpu/x86emit.h
index f55d8a448a4..a9cae927839 100644
--- a/src/emu/cpu/x86emit.h
+++ b/src/emu/cpu/x86emit.h
@@ -1568,6 +1568,8 @@ INLINE void emit_nop(x86code **emitptr) { emit_op_simple(emitptr, OP_NOP, OP_
INLINE void emit_int_3(x86code **emitptr) { emit_op_simple(emitptr, OP_INT_3, OP_32BIT); }
INLINE void emit_ret(x86code **emitptr) { emit_op_simple(emitptr, OP_RETN, OP_32BIT); }
INLINE void emit_cdq(x86code **emitptr) { emit_op_simple(emitptr, OP_CDQ, OP_32BIT); }
+INLINE void emit_clc(x86code **emitptr) { emit_op_simple(emitptr, OP_CLC, OP_32BIT); }
+INLINE void emit_stc(x86code **emitptr) { emit_op_simple(emitptr, OP_STC, OP_32BIT); }
INLINE void emit_cmc(x86code **emitptr) { emit_op_simple(emitptr, OP_CMC, OP_32BIT); }
INLINE void emit_pushf(x86code **emitptr) { emit_op_simple(emitptr, OP_PUSHF_Fv, OP_32BIT); }
INLINE void emit_popf(x86code **emitptr) { emit_op_simple(emitptr, OP_POPF_Fv, OP_32BIT); }
diff --git a/src/emu/cpu/z180/z180.c b/src/emu/cpu/z180/z180.c
index 7f730e0d0b9..c86332cfc9c 100644
--- a/src/emu/cpu/z180/z180.c
+++ b/src/emu/cpu/z180/z180.c
@@ -2338,13 +2338,13 @@ static void set_irq_line(int irqline, int state)
}
/* logical to physical address translation */
-static int z180_translate(int space, offs_t *addr)
+static int z180_translate(int space, int intention, offs_t *addr)
{
if (space == ADDRESS_SPACE_PROGRAM)
{
*addr = MMU_REMAP_ADDR(*addr);
}
- return 1;
+ return TRUE;
}
/**************************************************************************
diff --git a/src/emu/cpuintrf.c b/src/emu/cpuintrf.c
index 01e0bf1c6ad..6eb80089ed6 100644
--- a/src/emu/cpuintrf.c
+++ b/src/emu/cpuintrf.c
@@ -1269,7 +1269,7 @@ offs_t activecpu_get_physical_pc_byte(void)
else
pc >>= shift;
if (cpu[activecpu].intf.translate)
- (*cpu[activecpu].intf.translate)(ADDRESS_SPACE_PROGRAM, &pc);
+ (*cpu[activecpu].intf.translate)(ADDRESS_SPACE_PROGRAM, TRANSLATE_FETCH, &pc);
return pc;
}
@@ -1526,7 +1526,7 @@ offs_t cpunum_get_physical_pc_byte(int cpunum)
else
pc >>= shift;
if (cpu[activecpu].intf.translate)
- (*cpu[activecpu].intf.translate)(ADDRESS_SPACE_PROGRAM, &pc);
+ (*cpu[activecpu].intf.translate)(ADDRESS_SPACE_PROGRAM, TRANSLATE_FETCH, &pc);
cpuintrf_pop_context();
return pc;
}
diff --git a/src/emu/cpuintrf.h b/src/emu/cpuintrf.h
index 76769aca0df..2301297a501 100644
--- a/src/emu/cpuintrf.h
+++ b/src/emu/cpuintrf.h
@@ -124,7 +124,7 @@ enum
CPUINFO_PTR_EXECUTE, /* R/O: int (*execute)(int cycles) */
CPUINFO_PTR_BURN, /* R/O: void (*burn)(int cycles) */
CPUINFO_PTR_DISASSEMBLE, /* R/O: offs_t (*disassemble)(char *buffer, offs_t pc, const UINT8 *oprom, const UINT8 *opram) */
- CPUINFO_PTR_TRANSLATE, /* R/O: int (*translate)(int space, offs_t *address) */
+ CPUINFO_PTR_TRANSLATE, /* R/O: int (*translate)(int space, int intention, offs_t *address) */
CPUINFO_PTR_READ, /* R/O: int (*read)(int space, UINT32 offset, int size, UINT64 *value) */
CPUINFO_PTR_WRITE, /* R/O: int (*write)(int space, UINT32 offset, int size, UINT64 value) */
CPUINFO_PTR_READOP, /* R/O: int (*readop)(UINT32 offset, int size, UINT64 *value) */
@@ -178,6 +178,22 @@ enum
};
+/* Translation intentions */
+#define TRANSLATE_TYPE_MASK 0x03 /* read write or fetch */
+#define TRANSLATE_USER_MASK 0x04 /* user mode or fully privileged */
+#define TRANSLATE_DEBUG_MASK 0x08 /* debug mode (no side effects) */
+
+#define TRANSLATE_READ 0 /* translate for read */
+#define TRANSLATE_WRITE 1 /* translate for write */
+#define TRANSLATE_FETCH 2 /* translate for instruction fetch */
+#define TRANSLATE_READ_USER (TRANSLATE_READ | TRANSLATE_USER_MASK)
+#define TRANSLATE_WRITE_USER (TRANSLATE_WRITE | TRANSLATE_USER_MASK)
+#define TRANSLATE_FETCH_USER (TRANSLATE_FETCH | TRANSLATE_USER_MASK)
+#define TRANSLATE_READ_DEBUG (TRANSLATE_READ | TRANSLATE_DEBUG_MASK)
+#define TRANSLATE_WRITE_DEBUG (TRANSLATE_WRITE | TRANSLATE_DEBUG_MASK)
+#define TRANSLATE_FETCH_DEBUG (TRANSLATE_FETCH | TRANSLATE_DEBUG_MASK)
+
+
/* Disassembler constants */
#define DASMFLAG_SUPPORTED 0x80000000 /* are disassembly flags supported? */
#define DASMFLAG_STEP_OUT 0x40000000 /* this instruction should be the end of a step out sequence */
@@ -208,7 +224,7 @@ typedef void (*cpu_exit_func)(void);
typedef int (*cpu_execute_func)(int cycles);
typedef void (*cpu_burn_func)(int cycles);
typedef offs_t (*cpu_disassemble_func)(char *buffer, offs_t pc, const UINT8 *oprom, const UINT8 *opram);
-typedef int (*cpu_translate_func)(int space, offs_t *address);
+typedef int (*cpu_translate_func)(int space, int intention, offs_t *address);
typedef int (*cpu_read_func)(int space, UINT32 offset, int size, UINT64 *value);
typedef int (*cpu_write_func)(int space, UINT32 offset, int size, UINT64 value);
typedef int (*cpu_readop_func)(UINT32 offset, int size, UINT64 *value);
diff --git a/src/emu/debug/debugcmd.c b/src/emu/debug/debugcmd.c
index 7fee281f50a..5a035d1607c 100644
--- a/src/emu/debug/debugcmd.c
+++ b/src/emu/debug/debugcmd.c
@@ -1490,7 +1490,7 @@ static void execute_dump(int ref, int params, const char *param[])
if (i + j <= endoffset)
{
offs_t curaddr = i + j;
- if (!info->translate || (*info->translate)(spacenum, &curaddr))
+ if (info->translate == NULL || (*info->translate)(spacenum, TRANSLATE_READ, &curaddr))
{
UINT8 byte = debug_read_byte(ref, i + j, TRUE);
outdex += sprintf(&output[outdex], " %02X", byte);
@@ -1509,7 +1509,7 @@ static void execute_dump(int ref, int params, const char *param[])
if (i + j <= endoffset)
{
offs_t curaddr = i + j;
- if (!info->translate || (*info->translate)(spacenum, &curaddr))
+ if (info->translate == NULL || (*info->translate)(spacenum, TRANSLATE_READ_DEBUG, &curaddr))
{
UINT16 word = debug_read_word(ref, i + j, TRUE);
outdex += sprintf(&output[outdex], " %04X", word);
@@ -1528,7 +1528,7 @@ static void execute_dump(int ref, int params, const char *param[])
if (i + j <= endoffset)
{
offs_t curaddr = i + j;
- if (!info->translate || (*info->translate)(spacenum, &curaddr))
+ if (info->translate == NULL || (*info->translate)(spacenum, TRANSLATE_READ_DEBUG, &curaddr))
{
UINT32 dword = debug_read_dword(ref, i + j, TRUE);
outdex += sprintf(&output[outdex], " %08X", dword);
@@ -1547,7 +1547,7 @@ static void execute_dump(int ref, int params, const char *param[])
if (i + j <= endoffset)
{
offs_t curaddr = i + j;
- if (!info->translate || (*info->translate)(spacenum, &curaddr))
+ if (info->translate == NULL || (*info->translate)(spacenum, TRANSLATE_READ_DEBUG, &curaddr))
{
UINT64 qword = debug_read_qword(ref, i + j, TRUE);
outdex += sprintf(&output[outdex], " %08X%08X", (UINT32)(qword >> 32), (UINT32)qword);
@@ -1568,7 +1568,7 @@ static void execute_dump(int ref, int params, const char *param[])
for (j = 0; j < 16 && (i + j) <= endoffset; j++)
{
offs_t curaddr = i + j;
- if (!info->translate || (*info->translate)(spacenum, &curaddr))
+ if (info->translate == NULL || (*info->translate)(spacenum, TRANSLATE_READ_DEBUG, &curaddr))
{
UINT8 byte = debug_read_byte(ref, i + j, TRUE);
outdex += sprintf(&output[outdex], "%c", (byte >= 32 && byte < 128) ? byte : '.');
@@ -1759,7 +1759,7 @@ static void execute_dasm(int ref, int params, const char *param[])
/* make sure we can translate the address */
tempaddr = pcbyte;
- if (!info->translate || (*info->translate)(ADDRESS_SPACE_PROGRAM, &tempaddr))
+ if (info->translate == NULL || (*info->translate)(ADDRESS_SPACE_PROGRAM, TRANSLATE_FETCH_DEBUG, &tempaddr))
{
UINT8 opbuf[64], argbuf[64];
@@ -2063,9 +2063,9 @@ static void execute_map(int ref, int params, const char *param[])
/* do the translation first */
taddress = ADDR2BYTE_MASKED(address, info, spacenum);
- if (info->translate)
+ if (info->translate != NULL)
{
- if ((*info->translate)(spacenum, &taddress))
+ if ((*info->translate)(spacenum, TRANSLATE_READ_DEBUG, &taddress))
debug_console_printf("%08X logical -> %08X physical\n", (UINT32)address, BYTE2ADDR(taddress, info, spacenum));
else
{
diff --git a/src/emu/debug/debugcpu.c b/src/emu/debug/debugcpu.c
index 9fad76f48a3..d0ad7d3e977 100644
--- a/src/emu/debug/debugcpu.c
+++ b/src/emu/debug/debugcpu.c
@@ -223,10 +223,10 @@ void debug_cpu_init(running_machine *machine)
debug_cpuinfo[cpunum].temp_breakpoint_pc = ~0;
/* fetch the memory accessors */
- debug_cpuinfo[cpunum].translate = (int (*)(int, offs_t *))cpunum_get_info_fct(cpunum, CPUINFO_PTR_TRANSLATE);
- debug_cpuinfo[cpunum].read = (int (*)(int, UINT32, int, UINT64 *))cpunum_get_info_fct(cpunum, CPUINFO_PTR_READ);
- debug_cpuinfo[cpunum].write = (int (*)(int, UINT32, int, UINT64))cpunum_get_info_fct(cpunum, CPUINFO_PTR_WRITE);
- debug_cpuinfo[cpunum].readop = (int (*)(UINT32, int, UINT64 *))cpunum_get_info_fct(cpunum, CPUINFO_PTR_READOP);
+ debug_cpuinfo[cpunum].translate = (cpu_translate_func)cpunum_get_info_fct(cpunum, CPUINFO_PTR_TRANSLATE);
+ debug_cpuinfo[cpunum].read = (cpu_read_func)cpunum_get_info_fct(cpunum, CPUINFO_PTR_READ);
+ debug_cpuinfo[cpunum].write = (cpu_write_func)cpunum_get_info_fct(cpunum, CPUINFO_PTR_WRITE);
+ debug_cpuinfo[cpunum].readop = (cpu_readop_func)cpunum_get_info_fct(cpunum, CPUINFO_PTR_READOP);
/* allocate a symbol table */
debug_cpuinfo[cpunum].symtable = symtable_alloc(global_symtable);
@@ -1637,7 +1637,7 @@ UINT8 debug_read_byte(int spacenum, offs_t address, int apply_translation)
memory_set_debugger_access(1);
/* translate if necessary; if not mapped, return 0xff */
- if (apply_translation && info->translate != NULL && !(*info->translate)(spacenum, &address))
+ if (apply_translation && info->translate != NULL && !(*info->translate)(spacenum, TRANSLATE_READ_DEBUG, &address))
result = 0xff;
/* if there is a custom read handler, and it returns TRUE, use that value */
@@ -1688,7 +1688,7 @@ UINT16 debug_read_word(int spacenum, offs_t address, int apply_translation)
memory_set_debugger_access(1);
/* translate if necessary; if not mapped, return 0xffff */
- if (apply_translation && info->translate != NULL && !(*info->translate)(spacenum, &address))
+ if (apply_translation && info->translate != NULL && !(*info->translate)(spacenum, TRANSLATE_READ_DEBUG, &address))
result = 0xffff;
/* if there is a custom read handler, and it returns TRUE, use that value */
@@ -1741,7 +1741,7 @@ UINT32 debug_read_dword(int spacenum, offs_t address, int apply_translation)
memory_set_debugger_access(1);
/* translate if necessary; if not mapped, return 0xffffffff */
- if (apply_translation && info->translate != NULL && !(*info->translate)(spacenum, &address))
+ if (apply_translation && info->translate != NULL && !(*info->translate)(spacenum, TRANSLATE_READ_DEBUG, &address))
result = 0xffffffff;
/* if there is a custom read handler, and it returns TRUE, use that value */
@@ -1794,7 +1794,7 @@ UINT64 debug_read_qword(int spacenum, offs_t address, int apply_translation)
memory_set_debugger_access(1);
/* translate if necessary; if not mapped, return 0xffffffffffffffff */
- if (apply_translation && info->translate != NULL && !(*info->translate)(spacenum, &address))
+ if (apply_translation && info->translate != NULL && !(*info->translate)(spacenum, TRANSLATE_READ_DEBUG, &address))
result = ~(UINT64)0;
/* if there is a custom read handler, and it returns TRUE, use that value */
@@ -1829,7 +1829,7 @@ void debug_write_byte(int spacenum, offs_t address, UINT8 data, int apply_transl
memory_set_debugger_access(1);
/* translate if necessary; if not mapped, we're done */
- if (apply_translation && info->translate != NULL && !(*info->translate)(spacenum, &address))
+ if (apply_translation && info->translate != NULL && !(*info->translate)(spacenum, TRANSLATE_WRITE_DEBUG, &address))
;
/* if there is a custom write handler, and it returns TRUE, use that */
@@ -1880,7 +1880,7 @@ void debug_write_word(int spacenum, offs_t address, UINT16 data, int apply_trans
memory_set_debugger_access(1);
/* translate if necessary; if not mapped, we're done */
- if (apply_translation && info->translate && !(*info->translate)(spacenum, &address))
+ if (apply_translation && info->translate && !(*info->translate)(spacenum, TRANSLATE_WRITE_DEBUG, &address))
;
/* if there is a custom write handler, and it returns TRUE, use that */
@@ -1932,7 +1932,7 @@ void debug_write_dword(int spacenum, offs_t address, UINT32 data, int apply_tran
memory_set_debugger_access(1);
/* translate if necessary; if not mapped, we're done */
- if (apply_translation && info->translate && !(*info->translate)(spacenum, &address))
+ if (apply_translation && info->translate && !(*info->translate)(spacenum, TRANSLATE_WRITE_DEBUG, &address))
;
/* if there is a custom write handler, and it returns TRUE, use that */
@@ -1983,7 +1983,7 @@ void debug_write_qword(int spacenum, offs_t address, UINT64 data, int apply_tran
memory_set_debugger_access(1);
/* translate if necessary; if not mapped, we're done */
- if (apply_translation && info->translate && !(*info->translate)(spacenum, &address))
+ if (apply_translation && info->translate && !(*info->translate)(spacenum, TRANSLATE_WRITE_DEBUG, &address))
;
/* if there is a custom write handler, and it returns TRUE, use that */
@@ -2037,7 +2037,7 @@ UINT64 debug_read_opcode(offs_t address, int size, int arg)
}
/* translate to physical first */
- if (info->translate && !(*info->translate)(ADDRESS_SPACE_PROGRAM, &address))
+ if (info->translate && !(*info->translate)(ADDRESS_SPACE_PROGRAM, TRANSLATE_FETCH_DEBUG, &address))
return ~(UINT64)0 & (~(UINT64)0 >> (64 - 8*size));
/* keep in physical range */
diff --git a/src/emu/debug/debugcpu.h b/src/emu/debug/debugcpu.h
index 8f52c75b2fa..91b8f1e03d7 100644
--- a/src/emu/debug/debugcpu.h
+++ b/src/emu/debug/debugcpu.h
@@ -122,10 +122,10 @@ struct _debug_cpu_info
UINT32 pc_history_index; /* current history index */
int hotspot_count; /* number of hotspots */
int hotspot_threshhold; /* threshhold for the number of hits to print */
- int (*translate)(int space, offs_t *address);/* address translation routine */
- int (*read)(int space, UINT32 offset, int size, UINT64 *value); /* memory read routine */
- int (*write)(int space, UINT32 offset, int size, UINT64 value); /* memory write routine */
- int (*readop)(UINT32 offset, int size, UINT64 *value); /* opcode read routine */
+ cpu_translate_func translate; /* address translation routine */
+ cpu_read_func read; /* memory read routine */
+ cpu_write_func write; /* memory write routine */
+ cpu_readop_func readop; /* opcode read routine */
int (*instrhook)(offs_t pc); /* per-instruction callback hook */
};
diff --git a/src/emu/debug/debugvw.c b/src/emu/debug/debugvw.c
index ac40410a96a..11935897d80 100644
--- a/src/emu/debug/debugvw.c
+++ b/src/emu/debug/debugvw.c
@@ -1359,7 +1359,7 @@ static offs_t disasm_back_up(int cpunum, const debug_cpu_info *cpuinfo, offs_t s
/* get the disassembly, but only if mapped */
instlen = 1;
- if (!cpuinfo->translate || (*cpuinfo->translate)(ADDRESS_SPACE_PROGRAM, &pcbyte))
+ if (cpuinfo->translate == NULL || (*cpuinfo->translate)(ADDRESS_SPACE_PROGRAM, TRANSLATE_FETCH_DEBUG, &pcbyte))
instlen = activecpu_dasm(dasmbuffer, testpc & addrmask, &opbuf[1000 + testpc - startpc], &argbuf[1000 + testpc - startpc]) & DASMFLAG_LENGTHMASK;
/* count this one */
@@ -1537,7 +1537,7 @@ static int disasm_recompute(debug_view *view, offs_t pc, int startline, int line
/* make sure we can translate the address */
tempaddr = pcbyte;
- if (!cpuinfo->translate || (*cpuinfo->translate)(ADDRESS_SPACE_PROGRAM, &tempaddr))
+ if (cpuinfo->translate == NULL || (*cpuinfo->translate)(ADDRESS_SPACE_PROGRAM, TRANSLATE_FETCH_DEBUG, &tempaddr))
{
UINT8 opbuf[64], argbuf[64];
@@ -2770,7 +2770,7 @@ static void memory_update(debug_view *view)
if (curaddr > maxaddr)
len += sprintf(&data[len], " ");
else if (memdata->raw_base != NULL || memdata->no_translation ||
- cpuinfo->translate == NULL || (*cpuinfo->translate)(memdata->spacenum, &curaddr))
+ cpuinfo->translate == NULL || (*cpuinfo->translate)(memdata->spacenum, TRANSLATE_READ_DEBUG, &curaddr))
len += sprintf(&data[len], "%02X ", memory_read_byte(memdata, addrbyte + i, !memdata->no_translation));
else
len += sprintf(&data[len], "** ");
@@ -2784,7 +2784,7 @@ static void memory_update(debug_view *view)
if (curaddr > maxaddr)
len += sprintf(&data[len], " ");
else if (memdata->raw_base != NULL || memdata->no_translation ||
- cpuinfo->translate == NULL || (*cpuinfo->translate)(memdata->spacenum, &curaddr))
+ cpuinfo->translate == NULL || (*cpuinfo->translate)(memdata->spacenum, TRANSLATE_READ_DEBUG, &curaddr))
len += sprintf(&data[len], " %04X ", memory_read_word(memdata, addrbyte + 2 * i, !memdata->no_translation));
else
len += sprintf(&data[len], " **** ");
@@ -2798,7 +2798,7 @@ static void memory_update(debug_view *view)
if (curaddr > maxaddr)
len += sprintf(&data[len], " ");
else if (memdata->raw_base != NULL || memdata->no_translation ||
- cpuinfo->translate == NULL || (*cpuinfo->translate)(memdata->spacenum, &curaddr))
+ cpuinfo->translate == NULL || (*cpuinfo->translate)(memdata->spacenum, TRANSLATE_READ_DEBUG, &curaddr))
len += sprintf(&data[len], " %08X ", memory_read_dword(memdata, addrbyte + 4 * i, !memdata->no_translation));
else
len += sprintf(&data[len], " ******** ");
@@ -2812,7 +2812,7 @@ static void memory_update(debug_view *view)
if (curaddr > maxaddr)
len += sprintf(&data[len], " ");
else if (memdata->raw_base != NULL || memdata->no_translation ||
- cpuinfo->translate == NULL || (*cpuinfo->translate)(memdata->spacenum, &curaddr))
+ cpuinfo->translate == NULL || (*cpuinfo->translate)(memdata->spacenum, TRANSLATE_READ_DEBUG, &curaddr))
{
UINT64 qword = memory_read_qword(memdata, addrbyte + 8 * i, !memdata->no_translation);
len += sprintf(&data[len], " %08X%08X ", (UINT32)(qword >> 32), (UINT32)qword);
@@ -2866,7 +2866,7 @@ static void memory_update(debug_view *view)
if (curaddr > maxaddr)
len += sprintf(&data[len], " ");
else if (memdata->raw_base != NULL || memdata->no_translation ||
- cpuinfo->translate == NULL || (*cpuinfo->translate)(memdata->spacenum, &curaddr))
+ cpuinfo->translate == NULL || (*cpuinfo->translate)(memdata->spacenum, TRANSLATE_READ_DEBUG, &curaddr))
len += sprintf(&data[len], "%02X ", memory_read_byte(memdata, addrbyte + i, !memdata->no_translation));
else
len += sprintf(&data[len], "** ");
@@ -2880,7 +2880,7 @@ static void memory_update(debug_view *view)
if (curaddr > maxaddr)
len += sprintf(&data[len], " ");
else if (memdata->raw_base != NULL || memdata->no_translation ||
- cpuinfo->translate == NULL || (*cpuinfo->translate)(memdata->spacenum, &curaddr))
+ cpuinfo->translate == NULL || (*cpuinfo->translate)(memdata->spacenum, TRANSLATE_READ_DEBUG, &curaddr))
len += sprintf(&data[len], " %04X ", memory_read_word(memdata, addrbyte + 2 * i, !memdata->no_translation));
else
len += sprintf(&data[len], " **** ");
@@ -2894,7 +2894,7 @@ static void memory_update(debug_view *view)
if (curaddr > maxaddr)
len += sprintf(&data[len], " ");
else if (memdata->raw_base != NULL || memdata->no_translation ||
- cpuinfo->translate == NULL || (*cpuinfo->translate)(memdata->spacenum, &curaddr))
+ cpuinfo->translate == NULL || (*cpuinfo->translate)(memdata->spacenum, TRANSLATE_READ_DEBUG, &curaddr))
len += sprintf(&data[len], " %08X ", memory_read_dword(memdata, addrbyte + 4 * i, !memdata->no_translation));
else
len += sprintf(&data[len], " ******** ");
@@ -2908,7 +2908,7 @@ static void memory_update(debug_view *view)
if (curaddr > maxaddr)
len += sprintf(&data[len], " ");
else if (memdata->raw_base != NULL || memdata->no_translation ||
- cpuinfo->translate == NULL || (*cpuinfo->translate)(memdata->spacenum, &curaddr))
+ cpuinfo->translate == NULL || (*cpuinfo->translate)(memdata->spacenum, TRANSLATE_READ_DEBUG, &curaddr))
{
UINT64 qword = memory_read_qword(memdata, addrbyte + 8 * i, !memdata->no_translation);
len += sprintf(&data[len], " %08X%08X ", (UINT32)(qword >> 32), (UINT32)qword);
diff --git a/src/emu/memory.h b/src/emu/memory.h
index 75c739ba39f..9c44edf815e 100644
--- a/src/emu/memory.h
+++ b/src/emu/memory.h
@@ -786,14 +786,14 @@ union _addrmap64_token
/* common shortcuts */
#define AM_READWRITE(_read,_write) AM_READ(_read) AM_WRITE(_write)
-#define AM_READWRITE8(_read,_write,_shift) AM_READ8(_read,_shift) AM_WRITE8(_write,_shift)
-#define AM_READWRITE16(_read,_write,_shift) AM_READ16(_read,_shift) AM_WRITE16(_write,_shift)
-#define AM_READWRITE32(_read,_write,_shift) AM_READ32(_read,_shift) AM_WRITE32(_write,_shift)
+#define AM_READWRITE8(_read,_write,_mask) AM_READ8(_read,_mask) AM_WRITE8(_write,_mask)
+#define AM_READWRITE16(_read,_write,_mask) AM_READ16(_read,_mask) AM_WRITE16(_write,_mask)
+#define AM_READWRITE32(_read,_write,_mask) AM_READ32(_read,_mask) AM_WRITE32(_write,_mask)
#define AM_DEVREADWRITE(_type,_tag,_read,_write) AM_DEVREAD(_type,_tag,_read) AM_DEVWRITE(_type,_tag,_write)
-#define AM_DEVREADWRITE8(_type,_tag,_read,_write,_shift) AM_DEVREAD8(_type,_tag,_read,_shift) AM_DEVWRITE8(_type,_tag,_write,_shift)
-#define AM_DEVREADWRITE16(_type,_tag,_read,_write,_shift) AM_DEVREAD16(_type,_tag,_read,_shift) AM_DEVWRITE16(_type,_tag,_write,_shift)
-#define AM_DEVREADWRITE32(_type,_tag,_read,_write,_shift) AM_DEVREAD32(_type,_tag,_read,_shift) AM_DEVWRITE32(_type,_tag,_write,_shift)
+#define AM_DEVREADWRITE8(_type,_tag,_read,_write,_mask) AM_DEVREAD8(_type,_tag,_read,_mask) AM_DEVWRITE8(_type,_tag,_write,_mask)
+#define AM_DEVREADWRITE16(_type,_tag,_read,_write,_mask) AM_DEVREAD16(_type,_tag,_read,_mask) AM_DEVWRITE16(_type,_tag,_write,_mask)
+#define AM_DEVREADWRITE32(_type,_tag,_read,_write,_mask) AM_DEVREAD32(_type,_tag,_read,_mask) AM_DEVWRITE32(_type,_tag,_write,_mask)
#define AM_ROM AM_READ(SMH_ROM)
#define AM_ROMBANK(_bank) AM_READ(SMH_BANK(_bank))
diff --git a/src/mame/drivers/aleck64.c b/src/mame/drivers/aleck64.c
index b0df9708ef8..b1149b0a6b3 100644
--- a/src/mame/drivers/aleck64.c
+++ b/src/mame/drivers/aleck64.c
@@ -408,7 +408,7 @@ static INPUT_PORTS_START( starsldr )
INPUT_PORTS_END
/* ?? */
-static const struct mips3_config config =
+static const mips3_config config =
{
16384, /* code cache size */
8192, /* data cache size */
diff --git a/src/mame/drivers/hng64.c b/src/mame/drivers/hng64.c
index 7c5001717cf..75a770231dd 100644
--- a/src/mame/drivers/hng64.c
+++ b/src/mame/drivers/hng64.c
@@ -1422,7 +1422,7 @@ static DRIVER_INIT(hng64_race)
/* ?? */
-static const struct mips3_config config =
+static const mips3_config config =
{
16384, /* code cache size */
16384 /* data cache size */
diff --git a/src/mame/drivers/kinst.c b/src/mame/drivers/kinst.c
index 97979a33a96..3558b830ed2 100644
--- a/src/mame/drivers/kinst.c
+++ b/src/mame/drivers/kinst.c
@@ -667,7 +667,7 @@ INPUT_PORTS_END
*
*************************************/
-static const struct mips3_config config =
+static const mips3_config config =
{
16384, /* code cache size */
16384 /* data cache size */
diff --git a/src/mame/drivers/namcos23.c b/src/mame/drivers/namcos23.c
index 703ab7b1b67..fbd9edffb65 100644
--- a/src/mame/drivers/namcos23.c
+++ b/src/mame/drivers/namcos23.c
@@ -1012,7 +1012,7 @@ static GFXDECODE_START( namcos23 )
GFXDECODE_ENTRY( 0, 0, namcos23_cg_layout, 0, 0x80 )
GFXDECODE_END
-static const struct mips3_config config =
+static const mips3_config config =
{
8192, /* code cache size - VERIFIED */
8192 /* data cache size - VERIFIED */
diff --git a/src/mame/drivers/seattle.c b/src/mame/drivers/seattle.c
index ae3d413871d..71a6616750e 100644
--- a/src/mame/drivers/seattle.c
+++ b/src/mame/drivers/seattle.c
@@ -2442,7 +2442,7 @@ INPUT_PORTS_END
*
*************************************/
-static const struct mips3_config config =
+static const mips3_config config =
{
16384, /* code cache size */
16384, /* data cache size */
diff --git a/src/mame/drivers/vegas.c b/src/mame/drivers/vegas.c
index 7978e47b7c7..6d974529f87 100644
--- a/src/mame/drivers/vegas.c
+++ b/src/mame/drivers/vegas.c
@@ -2217,7 +2217,7 @@ INPUT_PORTS_END
*
*************************************/
-static const struct mips3_config config =
+static const mips3_config config =
{
16384, /* code cache size */
16384, /* data cache size */