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author Aaron Giles <aaron@aarongiles.com>2008-05-25 22:09:21 +0000
committer Aaron Giles <aaron@aarongiles.com>2008-05-25 22:09:21 +0000
commit40dea6049e2b9d93f5c1427a38e52509833b270f (patch)
tree18c4b831bb7bb7b623400fbf11a7b52fc311b5f5
parent238dc3aada9a1526f0af17d1a5114db61c184d13 (diff)
Added new front-end flag to tag privileged instructions.
Minor tweaks/cleanups to the MIPS3 drc.
-rw-r--r--src/emu/cpu/drcfe.h21
-rw-r--r--src/emu/cpu/drcuml.c2
-rw-r--r--src/emu/cpu/mips/mips3com.c45
-rw-r--r--src/emu/cpu/mips/mips3com.h24
-rw-r--r--src/emu/cpu/mips/mips3drc.c13
5 files changed, 23 insertions, 82 deletions
diff --git a/src/emu/cpu/drcfe.h b/src/emu/cpu/drcfe.h
index 6cd069d0ee4..d5f8873095d 100644
--- a/src/emu/cpu/drcfe.h
+++ b/src/emu/cpu/drcfe.h
@@ -56,22 +56,23 @@
#define OPFLAG_CAN_EXPOSE_EXTERNAL_INT 0x00000040 /* instruction can expose an external interrupt */
#define OPFLAG_CAN_CAUSE_EXCEPTION 0x00000080 /* instruction may generate exception */
#define OPFLAG_WILL_CAUSE_EXCEPTION 0x00000100 /* instruction will generate exception */
+#define OPFLAG_PRIVILEGED 0x00000200 /* instruction is privileged */
/* opcode virtual->physical translation flags */
-#define OPFLAG_VALIDATE_TLB 0x00000200 /* instruction must validate TLB before execution */
-#define OPFLAG_MODIFIES_TRANSLATION 0x00000400 /* instruction modifies the TLB */
-#define OPFLAG_COMPILER_PAGE_FAULT 0x00000800 /* compiler hit a page fault when parsing */
-#define OPFLAG_COMPILER_UNMAPPED 0x00001000 /* compiler hit unmapped memory when parsing */
+#define OPFLAG_VALIDATE_TLB 0x00000400 /* instruction must validate TLB before execution */
+#define OPFLAG_MODIFIES_TRANSLATION 0x00000800 /* instruction modifies the TLB */
+#define OPFLAG_COMPILER_PAGE_FAULT 0x00001000 /* compiler hit a page fault when parsing */
+#define OPFLAG_COMPILER_UNMAPPED 0x00002000 /* compiler hit unmapped memory when parsing */
/* opcode flags */
-#define OPFLAG_INVALID_OPCODE 0x00002000 /* instruction is invalid */
-#define OPFLAG_VIRTUAL_NOOP 0x00004000 /* instruction is a virtual no-op */
+#define OPFLAG_INVALID_OPCODE 0x00004000 /* instruction is invalid */
+#define OPFLAG_VIRTUAL_NOOP 0x00008000 /* instruction is a virtual no-op */
/* opcode sequence flow flags */
-#define OPFLAG_REDISPATCH 0x00008000 /* instruction must redispatch after completion */
-#define OPFLAG_RETURN_TO_START 0x00010000 /* instruction must jump back to the beginning after completion */
-#define OPFLAG_END_SEQUENCE 0x00020000 /* this is the last instruction in a sequence */
-#define OPFLAG_CAN_CHANGE_MODES 0x00040000 /* instruction can change modes */
+#define OPFLAG_REDISPATCH 0x00010000 /* instruction must redispatch after completion */
+#define OPFLAG_RETURN_TO_START 0x00020000 /* instruction must jump back to the beginning after completion */
+#define OPFLAG_END_SEQUENCE 0x00040000 /* this is the last instruction in a sequence */
+#define OPFLAG_CAN_CHANGE_MODES 0x00080000 /* instruction can change modes */
/* execution semantics */
#define OPFLAG_READS_MEMORY 0x00080000 /* instruction reads memory */
diff --git a/src/emu/cpu/drcuml.c b/src/emu/cpu/drcuml.c
index 2ce0a5303d0..de97a317e8a 100644
--- a/src/emu/cpu/drcuml.c
+++ b/src/emu/cpu/drcuml.c
@@ -17,6 +17,8 @@
- checks behavior of all opcodes
* Extend registers to 16? Depends on if PPC can use them
+
+ * Support for FPU exceptions
* New instructions?
- VALID opcode_desc,handle,param
diff --git a/src/emu/cpu/mips/mips3com.c b/src/emu/cpu/mips/mips3com.c
index 31a67ef835d..806cee03880 100644
--- a/src/emu/cpu/mips/mips3com.c
+++ b/src/emu/cpu/mips/mips3com.c
@@ -32,46 +32,6 @@ static void tlb_entry_log_half(mips3_tlb_entry *tlbent, int index, int which);
/***************************************************************************
- PRIVATE GLOBAL VARIABLES
-***************************************************************************/
-
-static const memory_accessors be_memory =
-{
- program_read_byte_32be,
- program_read_word_32be,
- program_read_dword_32be,
- program_read_dword_masked_32be,
- program_read_qword_32be,
- program_read_qword_masked_32be,
-
- program_write_byte_32be,
- program_write_word_32be,
- program_write_dword_32be,
- program_write_dword_masked_32be,
- program_write_qword_32be,
- program_write_qword_masked_32be
-};
-
-static const memory_accessors le_memory =
-{
- program_read_byte_32le,
- program_read_word_32le,
- program_read_dword_32le,
- program_read_dword_masked_32le,
- program_read_qword_32le,
- program_read_qword_masked_32le,
-
- program_write_byte_32le,
- program_write_word_32le,
- program_write_dword_32le,
- program_write_dword_masked_32le,
- program_write_qword_32le,
- program_write_qword_masked_32le
-};
-
-
-
-/***************************************************************************
INITIALIZATION AND SHUTDOWN
***************************************************************************/
@@ -99,10 +59,7 @@ size_t mips3com_init(mips3_state *mips, mips3_flavor flavor, int bigendian, int
mips->system_clock = config->system_clock;
/* set up the endianness */
- if (mips->bigendian)
- mips->memory = be_memory;
- else
- mips->memory = le_memory;
+ mips->memory = *memory_get_accessors(ADDRESS_SPACE_PROGRAM, 32, mips->bigendian ? CPU_IS_BE : CPU_IS_LE);
/* allocate memory */
mips->icache = memory;
diff --git a/src/emu/cpu/mips/mips3com.h b/src/emu/cpu/mips/mips3com.h
index 335f87efbd3..a132db47615 100644
--- a/src/emu/cpu/mips/mips3com.h
+++ b/src/emu/cpu/mips/mips3com.h
@@ -22,6 +22,7 @@
#define MIPS3_MIN_PAGE_SIZE (1 << MIPS3_MIN_PAGE_SHIFT)
#define MIPS3_MIN_PAGE_MASK (MIPS3_MIN_PAGE_SIZE - 1)
#define MIPS3_MAX_PADDR_SHIFT 32
+#define MIPS3_TLB_ENTRIES 48
/* cycle parameters */
#define MIPS3_COUNT_READ_CYCLES 250
@@ -159,25 +160,6 @@ typedef enum _mips3_flavor mips3_flavor;
STRUCTURES & TYPEDEFS
***************************************************************************/
-/* memory access function table */
-typedef struct _memory_accessors memory_accessors;
-struct _memory_accessors
-{
- UINT8 (*readbyte)(offs_t);
- UINT16 (*readhalf)(offs_t);
- UINT32 (*readword)(offs_t);
- UINT32 (*readword_masked)(offs_t, UINT32);
- UINT64 (*readdouble)(offs_t);
- UINT64 (*readdouble_masked)(offs_t, UINT64);
- void (*writebyte)(offs_t, UINT8);
- void (*writehalf)(offs_t, UINT16);
- void (*writeword)(offs_t, UINT32);
- void (*writeword_masked)(offs_t, UINT32, UINT32);
- void (*writedouble)(offs_t, UINT64);
- void (*writedouble_masked)(offs_t, UINT64, UINT64);
-};
-
-
/* MIPS3 TLB entry */
typedef struct _mips3_tlb_entry mips3_tlb_entry;
struct _mips3_tlb_entry
@@ -212,7 +194,7 @@ struct _mips3_state
/* memory accesses */
UINT8 bigendian;
- memory_accessors memory;
+ data_accessors memory;
/* cache memory */
UINT32 * icache;
@@ -221,7 +203,7 @@ struct _mips3_state
size_t dcache_size;
/* MMU */
- mips3_tlb_entry tlb[48];
+ mips3_tlb_entry tlb[MIPS3_TLB_ENTRIES];
UINT32 * tlb_table;
};
diff --git a/src/emu/cpu/mips/mips3drc.c b/src/emu/cpu/mips/mips3drc.c
index 3d26e157405..12edc091528 100644
--- a/src/emu/cpu/mips/mips3drc.c
+++ b/src/emu/cpu/mips/mips3drc.c
@@ -3025,15 +3025,14 @@ static int generate_cop0(drcuml_block *block, compiler_state *compiler, const op
{
UINT32 op = *desc->opptr.l;
UINT8 opswitch = RSREG;
- drcuml_codelabel okay;
int skip;
- /* generate an exception if COP0 is disabled or we are not in kernel mode */
- UML_TEST(block, CPR032(COP0_Status), IMM(SR_KSU_MASK)); // test [Status],SR_KSU_MASK
- UML_JMPc(block, IF_Z, okay = compiler->labelnum++); // jmp okay,Z
- UML_TEST(block, CPR032(COP0_Status), IMM(SR_COP0)); // test [Status],SR_COP0
- UML_EXHc(block, IF_Z, mips3.exception[EXCEPTION_BADCOP], IMM(0)); // exh cop,0,Z
- UML_LABEL(block, okay); // okay:
+ /* generate an exception if COP0 is disabled unless we are in kernel mode */
+ if ((mips3.cstate->mode >> 1) != MODE_KERNEL)
+ {
+ UML_TEST(block, CPR032(COP0_Status), IMM(SR_COP0)); // test [Status],SR_COP0
+ UML_EXHc(block, IF_Z, mips3.exception[EXCEPTION_BADCOP], IMM(0)); // exh cop,0,Z
+ }
switch (opswitch)
{