summaryrefslogtreecommitdiffstatshomepage
diff options
context:
space:
mode:
author Patrick Mackinlay <pmackinlay@hotmail.com>2023-07-21 14:45:44 +0700
committer Patrick Mackinlay <pmackinlay@hotmail.com>2023-07-21 14:46:04 +0700
commit0d0992525bab762d33d284e6e5c0a6d68540f6a7 (patch)
tree9af306698a4b882ea7c01ce12f6d35e196bfeadc
parent627d839a9c7a09e9f4317efa3b8f3e60fbd8b575 (diff)
mips1: fix swl/swr cache logic
-rw-r--r--src/devices/cpu/mips/mips1.cpp5
1 files changed, 2 insertions, 3 deletions
diff --git a/src/devices/cpu/mips/mips1.cpp b/src/devices/cpu/mips/mips1.cpp
index 2d9894731e5..8dd77b3a0bd 100644
--- a/src/devices/cpu/mips/mips1.cpp
+++ b/src/devices/cpu/mips/mips1.cpp
@@ -8,7 +8,6 @@
*
* TODO:
* - multi-word cache line sizes
- * - verify lwl/lwr and swl/swr cache logic
* - R3041 features
*
*/
@@ -1397,7 +1396,7 @@ template <typename T, bool Aligned> void mips1core_device_base::store(u32 addres
l.update(u32(data) << shift, u32(mem_mask) << shift);
}
- else if constexpr (sizeof(T) == 4)
+ else if constexpr (Aligned && sizeof(T) == 4)
// only full word stores update the cache after a miss
l.update(data, mem_mask);
}
@@ -1416,7 +1415,7 @@ template <typename T, bool Aligned> void mips1core_device_base::store(u32 addres
// stores invalidate the cache line
auto [l, miss] = cache_lookup(address, true);
- if constexpr (sizeof(T) == 4)
+ if constexpr (Aligned && sizeof(T) == 4)
l.update(data, mem_mask);
else
l.invalidate();