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author Patrick Mackinlay <pmackinlay@hotmail.com>2022-02-11 17:16:46 +0700
committer Patrick Mackinlay <pmackinlay@hotmail.com>2022-02-11 17:16:46 +0700
commitaaecd78f65a5cd77982f152a60cd95cf2c619654 (patch)
treeb11a523003b0ad4222d1738a5b2210b63282fb13
parent02cd26d37ee11191f3e311e19e805d872cb1e3a4 (diff)
asmjit: sync with upstream
-rw-r--r--3rdparty/asmjit/.gitignore6
-rw-r--r--3rdparty/asmjit/.travis.yml343
-rw-r--r--3rdparty/asmjit/CMakeLists.txt248
-rw-r--r--3rdparty/asmjit/README.md21
-rw-r--r--3rdparty/asmjit/src/asmjit.natvis166
-rw-r--r--3rdparty/asmjit/src/asmjit/a64.h62
-rw-r--r--3rdparty/asmjit/src/asmjit/arm.h62
-rw-r--r--3rdparty/asmjit/src/asmjit/arm/a64archtraits_p.h81
-rw-r--r--3rdparty/asmjit/src/asmjit/arm/a64assembler.cpp5115
-rw-r--r--3rdparty/asmjit/src/asmjit/arm/a64assembler.h72
-rw-r--r--3rdparty/asmjit/src/asmjit/arm/a64builder.cpp51
-rw-r--r--3rdparty/asmjit/src/asmjit/arm/a64builder.h57
-rw-r--r--3rdparty/asmjit/src/asmjit/arm/a64compiler.cpp60
-rw-r--r--3rdparty/asmjit/src/asmjit/arm/a64compiler.h235
-rw-r--r--3rdparty/asmjit/src/asmjit/arm/a64emithelper.cpp464
-rw-r--r--3rdparty/asmjit/src/asmjit/arm/a64emithelper_p.h50
-rw-r--r--3rdparty/asmjit/src/asmjit/arm/a64emitter.h1228
-rw-r--r--3rdparty/asmjit/src/asmjit/arm/a64formatter.cpp298
-rw-r--r--3rdparty/asmjit/src/asmjit/arm/a64formatter_p.h59
-rw-r--r--3rdparty/asmjit/src/asmjit/arm/a64func.cpp189
-rw-r--r--3rdparty/asmjit/src/asmjit/arm/a64func_p.h33
-rw-r--r--3rdparty/asmjit/src/asmjit/arm/a64globals.h1894
-rw-r--r--3rdparty/asmjit/src/asmjit/arm/a64instapi.cpp278
-rw-r--r--3rdparty/asmjit/src/asmjit/arm/a64instapi_p.h41
-rw-r--r--3rdparty/asmjit/src/asmjit/arm/a64instdb.cpp1957
-rw-r--r--3rdparty/asmjit/src/asmjit/arm/a64instdb.h74
-rw-r--r--3rdparty/asmjit/src/asmjit/arm/a64instdb_p.h876
-rw-r--r--3rdparty/asmjit/src/asmjit/arm/a64operand.cpp85
-rw-r--r--3rdparty/asmjit/src/asmjit/arm/a64operand.h312
-rw-r--r--3rdparty/asmjit/src/asmjit/arm/a64rapass.cpp806
-rw-r--r--3rdparty/asmjit/src/asmjit/arm/a64rapass_p.h105
-rw-r--r--3rdparty/asmjit/src/asmjit/arm/a64utils.h179
-rw-r--r--3rdparty/asmjit/src/asmjit/arm/armformatter.cpp143
-rw-r--r--3rdparty/asmjit/src/asmjit/arm/armformatter_p.h44
-rw-r--r--3rdparty/asmjit/src/asmjit/arm/armglobals.h21
-rw-r--r--3rdparty/asmjit/src/asmjit/arm/armoperand.h596
-rw-r--r--3rdparty/asmjit/src/asmjit/asmjit-scope-begin.h17
-rw-r--r--3rdparty/asmjit/src/asmjit/asmjit-scope-end.h9
-rw-r--r--3rdparty/asmjit/src/asmjit/asmjit.h14
-rw-r--r--3rdparty/asmjit/src/asmjit/core.h1418
-rw-r--r--3rdparty/asmjit/src/asmjit/core/api-build_p.h28
-rw-r--r--3rdparty/asmjit/src/asmjit/core/api-config.h385
-rw-r--r--3rdparty/asmjit/src/asmjit/core/arch.cpp59
-rw-r--r--3rdparty/asmjit/src/asmjit/core/arch.h64
-rw-r--r--3rdparty/asmjit/src/asmjit/core/archcommons.h229
-rw-r--r--3rdparty/asmjit/src/asmjit/core/archtraits.cpp160
-rw-r--r--3rdparty/asmjit/src/asmjit/core/archtraits.h290
-rw-r--r--3rdparty/asmjit/src/asmjit/core/assembler.cpp230
-rw-r--r--3rdparty/asmjit/src/asmjit/core/assembler.h45
-rw-r--r--3rdparty/asmjit/src/asmjit/core/builder.cpp218
-rw-r--r--3rdparty/asmjit/src/asmjit/core/builder.h792
-rw-r--r--3rdparty/asmjit/src/asmjit/core/callconv.cpp59
-rw-r--r--3rdparty/asmjit/src/asmjit/core/callconv.h374
-rw-r--r--3rdparty/asmjit/src/asmjit/core/codebuffer.h61
-rw-r--r--3rdparty/asmjit/src/asmjit/core/codeholder.cpp381
-rw-r--r--3rdparty/asmjit/src/asmjit/core/codeholder.h920
-rw-r--r--3rdparty/asmjit/src/asmjit/core/codewriter.cpp175
-rw-r--r--3rdparty/asmjit/src/asmjit/core/codewriter_p.h (renamed from 3rdparty/asmjit/src/asmjit/core/codebufferwriter_p.h)84
-rw-r--r--3rdparty/asmjit/src/asmjit/core/compiler.cpp325
-rw-r--r--3rdparty/asmjit/src/asmjit/core/compiler.h639
-rw-r--r--3rdparty/asmjit/src/asmjit/core/compilerdefs.h173
-rw-r--r--3rdparty/asmjit/src/asmjit/core/constpool.cpp102
-rw-r--r--3rdparty/asmjit/src/asmjit/core/constpool.h74
-rw-r--r--3rdparty/asmjit/src/asmjit/core/cpuinfo.cpp1147
-rw-r--r--3rdparty/asmjit/src/asmjit/core/cpuinfo.h757
-rw-r--r--3rdparty/asmjit/src/asmjit/core/datatypes.h1071
-rw-r--r--3rdparty/asmjit/src/asmjit/core/emithelper.cpp323
-rw-r--r--3rdparty/asmjit/src/asmjit/core/emithelper_p.h58
-rw-r--r--3rdparty/asmjit/src/asmjit/core/emitter.cpp265
-rw-r--r--3rdparty/asmjit/src/asmjit/core/emitter.h721
-rw-r--r--3rdparty/asmjit/src/asmjit/core/emitterutils.cpp83
-rw-r--r--3rdparty/asmjit/src/asmjit/core/emitterutils_p.h58
-rw-r--r--3rdparty/asmjit/src/asmjit/core/environment.cpp24
-rw-r--r--3rdparty/asmjit/src/asmjit/core/environment.h737
-rw-r--r--3rdparty/asmjit/src/asmjit/core/errorhandler.cpp29
-rw-r--r--3rdparty/asmjit/src/asmjit/core/errorhandler.h129
-rw-r--r--3rdparty/asmjit/src/asmjit/core/features.h186
-rw-r--r--3rdparty/asmjit/src/asmjit/core/formatter.cpp435
-rw-r--r--3rdparty/asmjit/src/asmjit/core/formatter.h267
-rw-r--r--3rdparty/asmjit/src/asmjit/core/formatter_p.h34
-rw-r--r--3rdparty/asmjit/src/asmjit/core/func.cpp311
-rw-r--r--3rdparty/asmjit/src/asmjit/core/func.h1123
-rw-r--r--3rdparty/asmjit/src/asmjit/core/funcargscontext.cpp293
-rw-r--r--3rdparty/asmjit/src/asmjit/core/funcargscontext_p.h199
-rw-r--r--3rdparty/asmjit/src/asmjit/core/globals.cpp47
-rw-r--r--3rdparty/asmjit/src/asmjit/core/globals.h246
-rw-r--r--3rdparty/asmjit/src/asmjit/core/inst.cpp106
-rw-r--r--3rdparty/asmjit/src/asmjit/core/inst.h745
-rw-r--r--3rdparty/asmjit/src/asmjit/core/jitallocator.cpp978
-rw-r--r--3rdparty/asmjit/src/asmjit/core/jitallocator.h197
-rw-r--r--3rdparty/asmjit/src/asmjit/core/jitruntime.cpp96
-rw-r--r--3rdparty/asmjit/src/asmjit/core/jitruntime.h53
-rw-r--r--3rdparty/asmjit/src/asmjit/core/logger.cpp73
-rw-r--r--3rdparty/asmjit/src/asmjit/core/logger.h110
-rw-r--r--3rdparty/asmjit/src/asmjit/core/misc_p.h28
-rw-r--r--3rdparty/asmjit/src/asmjit/core/operand.cpp62
-rw-r--r--3rdparty/asmjit/src/asmjit/core/operand.h1681
-rw-r--r--3rdparty/asmjit/src/asmjit/core/osutils.cpp28
-rw-r--r--3rdparty/asmjit/src/asmjit/core/osutils.h40
-rw-r--r--3rdparty/asmjit/src/asmjit/core/osutils_p.h58
-rw-r--r--3rdparty/asmjit/src/asmjit/core/raassignment_p.h185
-rw-r--r--3rdparty/asmjit/src/asmjit/core/rabuilders_p.h269
-rw-r--r--3rdparty/asmjit/src/asmjit/core/radefs_p.h943
-rw-r--r--3rdparty/asmjit/src/asmjit/core/ralocal.cpp544
-rw-r--r--3rdparty/asmjit/src/asmjit/core/ralocal_p.h100
-rw-r--r--3rdparty/asmjit/src/asmjit/core/rapass.cpp819
-rw-r--r--3rdparty/asmjit/src/asmjit/core/rapass_p.h615
-rw-r--r--3rdparty/asmjit/src/asmjit/core/rastack.cpp56
-rw-r--r--3rdparty/asmjit/src/asmjit/core/rastack_p.h48
-rw-r--r--3rdparty/asmjit/src/asmjit/core/string.cpp168
-rw-r--r--3rdparty/asmjit/src/asmjit/core/string.h192
-rw-r--r--3rdparty/asmjit/src/asmjit/core/support.cpp39
-rw-r--r--3rdparty/asmjit/src/asmjit/core/support.h1225
-rw-r--r--3rdparty/asmjit/src/asmjit/core/target.cpp31
-rw-r--r--3rdparty/asmjit/src/asmjit/core/target.h140
-rw-r--r--3rdparty/asmjit/src/asmjit/core/type.cpp118
-rw-r--r--3rdparty/asmjit/src/asmjit/core/type.h592
-rw-r--r--3rdparty/asmjit/src/asmjit/core/virtmem.cpp639
-rw-r--r--3rdparty/asmjit/src/asmjit/core/virtmem.h283
-rw-r--r--3rdparty/asmjit/src/asmjit/core/zone.cpp93
-rw-r--r--3rdparty/asmjit/src/asmjit/core/zone.h212
-rw-r--r--3rdparty/asmjit/src/asmjit/core/zonehash.cpp44
-rw-r--r--3rdparty/asmjit/src/asmjit/core/zonehash.h48
-rw-r--r--3rdparty/asmjit/src/asmjit/core/zonelist.cpp29
-rw-r--r--3rdparty/asmjit/src/asmjit/core/zonelist.h128
-rw-r--r--3rdparty/asmjit/src/asmjit/core/zonestack.cpp53
-rw-r--r--3rdparty/asmjit/src/asmjit/core/zonestack.h117
-rw-r--r--3rdparty/asmjit/src/asmjit/core/zonestring.h65
-rw-r--r--3rdparty/asmjit/src/asmjit/core/zonetree.cpp29
-rw-r--r--3rdparty/asmjit/src/asmjit/core/zonetree.h103
-rw-r--r--3rdparty/asmjit/src/asmjit/core/zonevector.cpp45
-rw-r--r--3rdparty/asmjit/src/asmjit/core/zonevector.h198
-rw-r--r--3rdparty/asmjit/src/asmjit/x86.h101
-rw-r--r--3rdparty/asmjit/src/asmjit/x86/x86archdata.cpp137
-rw-r--r--3rdparty/asmjit/src/asmjit/x86/x86archdata_p.h51
-rw-r--r--3rdparty/asmjit/src/asmjit/x86/x86archtraits_p.h148
-rw-r--r--3rdparty/asmjit/src/asmjit/x86/x86assembler.cpp1638
-rw-r--r--3rdparty/asmjit/src/asmjit/x86/x86assembler.h270
-rw-r--r--3rdparty/asmjit/src/asmjit/x86/x86builder.cpp73
-rw-r--r--3rdparty/asmjit/src/asmjit/x86/x86builder.h130
-rw-r--r--3rdparty/asmjit/src/asmjit/x86/x86callconv.cpp238
-rw-r--r--3rdparty/asmjit/src/asmjit/x86/x86callconv_p.h52
-rw-r--r--3rdparty/asmjit/src/asmjit/x86/x86compiler.cpp79
-rw-r--r--3rdparty/asmjit/src/asmjit/x86/x86compiler.h328
-rw-r--r--3rdparty/asmjit/src/asmjit/x86/x86emithelper.cpp619
-rw-r--r--3rdparty/asmjit/src/asmjit/x86/x86emithelper_p.h60
-rw-r--r--3rdparty/asmjit/src/asmjit/x86/x86emitter.h2584
-rw-r--r--3rdparty/asmjit/src/asmjit/x86/x86features.cpp398
-rw-r--r--3rdparty/asmjit/src/asmjit/x86/x86features.h290
-rw-r--r--3rdparty/asmjit/src/asmjit/x86/x86formatter.cpp465
-rw-r--r--3rdparty/asmjit/src/asmjit/x86/x86formatter_p.h50
-rw-r--r--3rdparty/asmjit/src/asmjit/x86/x86func.cpp503
-rw-r--r--3rdparty/asmjit/src/asmjit/x86/x86func_p.h33
-rw-r--r--3rdparty/asmjit/src/asmjit/x86/x86globals.h1188
-rw-r--r--3rdparty/asmjit/src/asmjit/x86/x86instapi.cpp895
-rw-r--r--3rdparty/asmjit/src/asmjit/x86/x86instapi_p.h34
-rw-r--r--3rdparty/asmjit/src/asmjit/x86/x86instdb.cpp7543
-rw-r--r--3rdparty/asmjit/src/asmjit/x86/x86instdb.h690
-rw-r--r--3rdparty/asmjit/src/asmjit/x86/x86instdb_p.h102
-rw-r--r--3rdparty/asmjit/src/asmjit/x86/x86internal.cpp1733
-rw-r--r--3rdparty/asmjit/src/asmjit/x86/x86internal_p.h87
-rw-r--r--3rdparty/asmjit/src/asmjit/x86/x86opcode_p.h358
-rw-r--r--3rdparty/asmjit/src/asmjit/x86/x86operand.cpp92
-rw-r--r--3rdparty/asmjit/src/asmjit/x86/x86operand.h915
-rw-r--r--3rdparty/asmjit/src/asmjit/x86/x86rapass.cpp1018
-rw-r--r--3rdparty/asmjit/src/asmjit/x86/x86rapass_p.h99
-rw-r--r--3rdparty/asmjit/test/asmjit_bench_x86.cpp172
-rw-r--r--3rdparty/asmjit/test/asmjit_test_assembler.cpp84
-rw-r--r--3rdparty/asmjit/test/asmjit_test_assembler.h85
-rw-r--r--3rdparty/asmjit/test/asmjit_test_assembler_a64.cpp4006
-rw-r--r--3rdparty/asmjit/test/asmjit_test_assembler_x64.cpp17833
-rw-r--r--3rdparty/asmjit/test/asmjit_test_assembler_x86.cpp8300
-rw-r--r--3rdparty/asmjit/test/asmjit_test_compiler.cpp253
-rw-r--r--3rdparty/asmjit/test/asmjit_test_compiler.h73
-rw-r--r--3rdparty/asmjit/test/asmjit_test_compiler_a64.cpp690
-rw-r--r--3rdparty/asmjit/test/asmjit_test_compiler_x86.cpp (renamed from 3rdparty/asmjit/test/asmjit_test_x86_cc.cpp)1765
-rw-r--r--3rdparty/asmjit/test/asmjit_test_emitters.cpp (renamed from 3rdparty/asmjit/test/asmjit_test_x86_asm.cpp)91
-rw-r--r--3rdparty/asmjit/test/asmjit_test_instinfo.cpp181
-rw-r--r--3rdparty/asmjit/test/asmjit_test_misc.h203
-rw-r--r--3rdparty/asmjit/test/asmjit_test_opcode.cpp110
-rw-r--r--3rdparty/asmjit/test/asmjit_test_opcode.h6059
-rw-r--r--3rdparty/asmjit/test/asmjit_test_perf.cpp62
-rw-r--r--3rdparty/asmjit/test/asmjit_test_perf.h61
-rw-r--r--3rdparty/asmjit/test/asmjit_test_perf_a64.cpp699
-rw-r--r--3rdparty/asmjit/test/asmjit_test_perf_x86.cpp5032
-rw-r--r--3rdparty/asmjit/test/asmjit_test_unit.cpp90
-rw-r--r--3rdparty/asmjit/test/asmjit_test_x86_instinfo.cpp128
-rw-r--r--3rdparty/asmjit/test/asmjit_test_x86_sections.cpp65
-rw-r--r--3rdparty/asmjit/test/asmjitutils.h38
-rw-r--r--3rdparty/asmjit/test/cmdline.h61
-rw-r--r--3rdparty/asmjit/test/performancetimer.h41
-rw-r--r--3rdparty/asmjit/tools/configure-makefiles.sh20
-rw-r--r--3rdparty/asmjit/tools/configure-ninja.sh22
-rw-r--r--3rdparty/asmjit/tools/configure-sanitizers.sh20
-rw-r--r--3rdparty/asmjit/tools/configure-vs-x64.bat9
-rw-r--r--3rdparty/asmjit/tools/configure-vs-x86.bat9
-rw-r--r--3rdparty/asmjit/tools/configure-vs2019-x64.bat2
-rw-r--r--3rdparty/asmjit/tools/configure-vs2019-x86.bat2
-rw-r--r--3rdparty/asmjit/tools/configure-vs2022-x64.bat2
-rw-r--r--3rdparty/asmjit/tools/configure-vs2022-x86.bat2
-rw-r--r--3rdparty/asmjit/tools/configure-xcode.sh11
-rw-r--r--3rdparty/asmjit/tools/tablegen-arm.js365
-rw-r--r--3rdparty/asmjit/tools/tablegen-arm.sh3
-rw-r--r--3rdparty/asmjit/tools/tablegen-x86.js1318
-rw-r--r--3rdparty/asmjit/tools/tablegen-x86.sh3
-rw-r--r--3rdparty/asmjit/tools/tablegen.js69
-rw-r--r--3rdparty/asmjit/tools/tablegen.sh1
207 files changed, 82319 insertions, 33326 deletions
diff --git a/3rdparty/asmjit/.gitignore b/3rdparty/asmjit/.gitignore
index 34bbad2b75f..75d36d09cd0 100644
--- a/3rdparty/asmjit/.gitignore
+++ b/3rdparty/asmjit/.gitignore
@@ -1,6 +1,6 @@
+/build
+/build_*
+/tools/asmdb
.vscode
.kdev4
*.kdev4
-build
-build_*
-tools/asmdb
diff --git a/3rdparty/asmjit/.travis.yml b/3rdparty/asmjit/.travis.yml
deleted file mode 100644
index 0d541e6c10d..00000000000
--- a/3rdparty/asmjit/.travis.yml
+++ /dev/null
@@ -1,343 +0,0 @@
-language: cpp
-
-git:
- depth: false
-
-env:
- global:
- - BUILD_TOOLCHAIN="Unix Makefiles"
- - MAKEFLAGS="-j2"
-
-dist: bionic
-
-matrix:
- include:
- - name: "Source Code Check"
- env: BUILD_MATRIX="SOURCE_CODE_CHECK=1"
- os: linux
- language: node_js
- node_js:
- - node
-
- - name: "Linux Clang Default [64-bit] [DBG]"
- env: BUILD_MATRIX="BUILD_TYPE=Debug && CC=clang-9 && CXX=clang++-9"
- os: linux
- addons:
- apt:
- sources:
- - sourceline: "ppa:ubuntu-toolchain-r/test"
- packages: [clang++-9]
-
- - name: "Linux Clang Default [64-bit] [REL]"
- env: BUILD_MATRIX="BUILD_TYPE=Release && CC=clang-9 && CXX=clang++-9"
- os: linux
- addons:
- apt:
- sources:
- - sourceline: "ppa:ubuntu-toolchain-r/test"
- packages: [clang++-9]
-
- - name: "Linux Clang Default [64-bit] [REL] [Valgrind]"
- env: BUILD_MATRIX="BUILD_TYPE=Release && CC=clang-9 && CXX=clang++-9" USE_VALGRIND=1
- os: linux
- addons:
- apt:
- sources:
- - sourceline: "ppa:ubuntu-toolchain-r/test"
- packages: [clang++-9, valgrind]
-
- - name: "Linux Clang Default [64-bit] [REL] [Sanitize=Address]"
- env: BUILD_MATRIX="BUILD_TYPE=Release && CC=clang-9 && CXX=clang++-9" EXTRA_OPTIONS="-DASMJIT_SANITIZE=address"
- os: linux
- addons:
- apt:
- sources:
- - sourceline: "ppa:ubuntu-toolchain-r/test"
- packages: [clang++-9]
-
- - name: "Linux Clang Default [64-bit] [REL] [Sanitize=Undefined]"
- env: BUILD_MATRIX="BUILD_TYPE=Release && CC=clang-9 && CXX=clang++-9" EXTRA_OPTIONS="-DASMJIT_SANITIZE=undefined"
- os: linux
- addons:
- apt:
- sources:
- - sourceline: "ppa:ubuntu-toolchain-r/test"
- packages: [clang++-9]
-
- - name: "Linux Clang Default [64-bit] [REL] [NoDeprecated]"
- env: BUILD_MATRIX="BUILD_TYPE=Release && CC=clang-9 && CXX=clang++-9" EXTRA_OPTIONS="-DASMJIT_NO_DEPRECATED=1"
- os: linux
- addons:
- apt:
- sources:
- - sourceline: "ppa:ubuntu-toolchain-r/test"
- packages: [clang++-9]
-
- - name: "Linux Clang Default [64-bit] [REL] [NoIntrinsics]"
- env: BUILD_MATRIX="BUILD_TYPE=Release && CC=clang-9 && CXX=clang++-9" EXTRA_OPTIONS="-DASMJIT_NO_INTRINSICS=1"
- os: linux
- addons:
- apt:
- sources:
- - sourceline: "ppa:ubuntu-toolchain-r/test"
- packages: [clang++-9]
-
- - name: "Linux Clang Default [64-bit] [REL] [NoLogging]"
- env: BUILD_MATRIX="BUILD_TYPE=Release && CC=clang-9 && CXX=clang++-9" EXTRA_OPTIONS="-DASMJIT_NO_LOGGING=1"
- os: linux
- addons:
- apt:
- sources:
- - sourceline: "ppa:ubuntu-toolchain-r/test"
- packages: [clang++-9]
-
- - name: "Linux Clang Default [64-bit] [REL] [NoBuilder]"
- env: BUILD_MATRIX="BUILD_TYPE=Release && CC=clang-9 && CXX=clang++-9" EXTRA_OPTIONS="-DASMJIT_NO_BUILDER=1"
- os: linux
- addons:
- apt:
- sources:
- - sourceline: "ppa:ubuntu-toolchain-r/test"
- packages: [clang++-9]
-
- - name: "Linux Clang Default [64-bit] [REL] [NoCompiler]"
- env: BUILD_MATRIX="BUILD_TYPE=Release && CC=clang-9 && CXX=clang++-9" EXTRA_OPTIONS="-DASMJIT_NO_COMPILER=1"
- os: linux
- addons:
- apt:
- sources:
- - sourceline: "ppa:ubuntu-toolchain-r/test"
- packages: [clang++-9]
-
- - name: "Linux GCC 4.8 [32-bit] [DBG]"
- env: BUILD_MATRIX="BUILD_TYPE=Debug && CC=gcc-4.8 && CXX=g++-4.8" CXXFLAGS=-m32 LDFLAGS=-m32
- os: linux
- addons:
- apt:
- packages: [g++-4.8, g++-4.8-multilib, "linux-libc-dev:i386"]
-
- - name: "Linux GCC 4.8 [64-bit] [DBG]"
- env: BUILD_MATRIX="BUILD_TYPE=Debug && CC=gcc-4.8 && CXX=g++-4.8"
- os: linux
- addons:
- apt:
- packages: [g++-4.8]
-
- - name: "Linux GCC 5 [32-bit] [DBG]"
- env: BUILD_MATRIX="BUILD_TYPE=Debug && CC=gcc-5 && CXX=g++-5" CXXFLAGS=-m32 LDFLAGS=-m32
- os: linux
- addons:
- apt:
- packages: [g++-5, g++-5-multilib, "linux-libc-dev:i386"]
-
- - name: "Linux GCC 5 [64-bit] [DBG]"
- env: BUILD_MATRIX="BUILD_TYPE=Debug && CC=gcc-5 && CXX=g++-5"
- os: linux
- addons:
- apt:
- packages: [g++-5]
-
- - name: "Linux GCC 6 [32-bit] [DBG]"
- env: BUILD_MATRIX="BUILD_TYPE=Debug && CC=gcc-6 && CXX=g++-6" CXXFLAGS=-m32 LDFLAGS=-m32
- os: linux
- addons:
- apt:
- packages: [g++-6, g++-6-multilib, "linux-libc-dev:i386"]
-
- - name: "Linux GCC 6 [64-bit] [DBG]"
- env: BUILD_MATRIX="BUILD_TYPE=Debug && CC=gcc-6 && CXX=g++-6"
- os: linux
- addons:
- apt:
- packages: [g++-6]
-
- - name: "Linux GCC 7 [32-bit] [DBG]"
- env: BUILD_MATRIX="BUILD_TYPE=Debug && CC=gcc-7 && CXX=g++-7" CXXFLAGS=-m32 LDFLAGS=-m32
- os: linux
- addons:
- apt:
- packages: [g++-7, g++-7-multilib, "linux-libc-dev:i386"]
-
- - name: "Linux GCC 7 [64-bit] [DBG]"
- env: BUILD_MATRIX="BUILD_TYPE=Debug && CC=gcc-7 && CXX=g++-7"
- os: linux
- addons:
- apt:
- packages: [g++-7]
-
- - name: "Linux GCC 8 [32-bit] [DBG]"
- env: BUILD_MATRIX="BUILD_TYPE=Debug && CC=gcc-8 && CXX=g++-8" CXXFLAGS=-m32 LDFLAGS=-m32
- os: linux
- addons:
- apt:
- packages: [g++-8, g++-8-multilib, "linux-libc-dev:i386"]
-
- - name: "Linux GCC 8 [64-bit] [DBG]"
- env: BUILD_MATRIX="BUILD_TYPE=Debug && CC=gcc-8 && CXX=g++-8"
- os: linux
- addons:
- apt:
- packages: [g++-8]
-
- - name: "Linux GCC 9 [32-bit] [DBG]"
- env: BUILD_MATRIX="BUILD_TYPE=Debug && CC=gcc-9 && CXX=g++-9" CXXFLAGS=-m32 LDFLAGS=-m32
- os: linux
- addons:
- apt:
- sources:
- - sourceline: "ppa:ubuntu-toolchain-r/test"
- packages: [g++-9, g++-9-multilib, "linux-libc-dev:i386"]
-
- - name: "Linux GCC 9 [64-bit] [DBG]"
- env: BUILD_MATRIX="BUILD_TYPE=Debug && CC=gcc-9 && CXX=g++-9"
- os: linux
- addons:
- apt:
- sources:
- - sourceline: "ppa:ubuntu-toolchain-r/test"
- packages: [g++-9]
-
- - name: "Linux GCC 10 [32-bit] [DBG]"
- env: BUILD_MATRIX="BUILD_TYPE=Debug && CC=gcc-10 && CXX=g++-10" CXXFLAGS=-m32 LDFLAGS=-m32
- os: linux
- addons:
- apt:
- sources:
- - sourceline: "ppa:ubuntu-toolchain-r/test"
- packages: [g++-10, g++-10-multilib, "linux-libc-dev:i386"]
-
- - name: "Linux GCC 10 [32-bit] [REL]"
- env: BUILD_MATRIX="BUILD_TYPE=Release && CC=gcc-10 && CXX=g++-10" CXXFLAGS=-m32 LDFLAGS=-m32
- os: linux
- addons:
- apt:
- sources:
- - sourceline: "ppa:ubuntu-toolchain-r/test"
- packages: [g++-10, g++-10-multilib, "linux-libc-dev:i386"]
-
- - name: "Linux GCC 10 [64-bit] [DBG]"
- env: BUILD_MATRIX="BUILD_TYPE=Debug && CC=gcc-10 && CXX=g++-10"
- os: linux
- addons:
- apt:
- sources:
- - sourceline: "ppa:ubuntu-toolchain-r/test"
- packages: [g++-10]
-
- - name: "Linux GCC 10 [64-bit] [REL]"
- env: BUILD_MATRIX="BUILD_TYPE=Release && CC=gcc-10 && CXX=g++-10"
- os: linux
- addons:
- apt:
- sources:
- - sourceline: "ppa:ubuntu-toolchain-r/test"
- packages: [g++-10]
-
- - name: "OSX Clang XCode 9.4 [32-bit] [DBG]"
- env: BUILD_MATRIX="BUILD_TYPE=Debug" CXXFLAGS=-m32 LDFLAGS=-m32
- os: osx
- osx_image: xcode9.4
-
- - name: "OSX Clang XCode 9.4 [32-bit] [REL]"
- env: BUILD_MATRIX="BUILD_TYPE=Release" CXXFLAGS=-m32 LDFLAGS=-m32
- os: osx
- osx_image: xcode9.4
-
- - name: "OSX Clang XCode 9.4 [64-bit] [DBG]"
- env: BUILD_MATRIX="BUILD_TYPE=Debug"
- os: osx
- osx_image: xcode9.4
-
- - name: "OSX Clang XCode 9.4 [64-bit] [REL]"
- env: BUILD_MATRIX="BUILD_TYPE=Release"
- os: osx
- osx_image: xcode9.4
-
- - name: "OSX Clang XCode 10.2 [64-bit] [DBG]"
- env: BUILD_MATRIX="BUILD_TYPE=Debug"
- os: osx
- osx_image: xcode10.2
-
- - name: "OSX Clang XCode 10.2 [64-bit] [REL]"
- env: BUILD_MATRIX="BUILD_TYPE=Release"
- os: osx
- osx_image: xcode10.2
-
- - name: "OSX Clang XCode 11 [64-bit] [DBG]"
- env: BUILD_MATRIX="BUILD_TYPE=Debug"
- os: osx
- osx_image: xcode11
-
- - name: "OSX Clang XCode 11 [64-bit] [REL]"
- env: BUILD_MATRIX="BUILD_TYPE=Release"
- os: osx
- osx_image: xcode11
-
- - name: "Windows VS2017 [32-bit] [DBG]"
- env: BUILD_MATRIX="BUILD_TYPE=Debug" BUILD_TOOLCHAIN="Visual Studio 15 2017"
- os: windows
-
- - name: "Windows VS2017 [32-bit] [REL]"
- env: BUILD_MATRIX="BUILD_TYPE=Release" BUILD_TOOLCHAIN="Visual Studio 15 2017"
- os: windows
-
- - name: "Windows VS2017 [64-bit] [DBG]"
- env: BUILD_MATRIX="BUILD_TYPE=Debug" BUILD_TOOLCHAIN="Visual Studio 15 2017 Win64"
- os: windows
-
- - name: "Windows VS2017 [64-bit] [REL]"
- env: BUILD_MATRIX="BUILD_TYPE=Release" BUILD_TOOLCHAIN="Visual Studio 15 2017 Win64"
- os: windows
-
-before_install:
- - eval "$BUILD_MATRIX"
-
-before_script:
- - |
- if [ -z $SOURCE_CODE_CHECK ]; then
- mkdir build
- cd build
- if [[ "$BUILD_TOOLCHAIN" =~ ^Visual\ Studio ]]; then
- cmake .. -G"${BUILD_TOOLCHAIN}" -DASMJIT_TEST=1 ${EXTRA_OPTIONS}
- else
- cmake .. -G"${BUILD_TOOLCHAIN}" -DASMJIT_TEST=1 ${EXTRA_OPTIONS} -DCMAKE_PREFIX_PATH="${MINGW_PATH}" -DCMAKE_BUILD_TYPE="${BUILD_TYPE}"
- fi
- cd ..
- fi
-
-script:
- - |
- if [ -z $SOURCE_CODE_CHECK ]; then
- cd build
- if [[ "$BUILD_TOOLCHAIN" =~ ^Visual\ Studio ]]; then
- cmake --build . --config ${BUILD_TYPE} -- -nologo -v:minimal || exit 1
- cd ${BUILD_TYPE}
- else
- cmake --build . || exit 1
- fi
- echo ""
- echo "=== Starting Tests ==="
- echo ""
- if [ "$USE_VALGRIND" = "1" ]; then
- RUN_CMD="valgrind --leak-check=full --show-reachable=yes --track-origins=yes"
- fi
- eval "$RUN_CMD ./asmjit_test_unit --quick" || exit 1
- echo ""
- eval "$RUN_CMD ./asmjit_test_opcode > /dev/null" || exit 1
- echo ""
- eval "$RUN_CMD ./asmjit_test_x86_asm" || exit 1
- echo ""
- eval "$RUN_CMD ./asmjit_test_x86_sections" || exit 1
- if [ -f ./asmjit_test_x86_instinfo ]; then
- echo ""
- eval "$RUN_CMD ./asmjit_test_x86_instinfo" || exit 1
- fi
- if [ -f ./asmjit_test_x86_cc ]; then
- echo ""
- eval "$RUN_CMD ./asmjit_test_x86_cc" || exit 1
- fi
- else
- cd tools
- ./enumgen.sh --verify || exit 1
- cd ..
- fi
diff --git a/3rdparty/asmjit/CMakeLists.txt b/3rdparty/asmjit/CMakeLists.txt
index e033c3ff663..50c9bcc198c 100644
--- a/3rdparty/asmjit/CMakeLists.txt
+++ b/3rdparty/asmjit/CMakeLists.txt
@@ -10,17 +10,17 @@ if(POLICY CMP0092)
cmake_policy(SET CMP0092 NEW) # Don't add -W3 warning level by default.
endif()
-include(CheckCXXCompilerFlag)
-
# Don't create a project if it was already created by another CMakeLists.txt.
# This allows one library to embed another library without making a collision.
if (NOT CMAKE_PROJECT_NAME OR "${CMAKE_PROJECT_NAME}" STREQUAL "asmjit")
project(asmjit CXX)
endif()
-# =============================================================================
-# [AsmJit - Deprecated]
-# =============================================================================
+include(CheckCXXCompilerFlag)
+include(GNUInstallDirs)
+
+# AsmJit - Deprecated
+# ===================
if (DEFINED ASMJIT_BUILD_EMBED)
message(DEPRECATION "ASMJIT_BUILD_EMBED is deprecated, use ASMJIT_EMBED")
@@ -32,9 +32,12 @@ if (DEFINED ASMJIT_BUILD_STATIC)
set(ASMJIT_STATIC "${ASMJIT_BUILD_STATIC}")
endif()
-# =============================================================================
-# [AsmJit - Configuration]
-# =============================================================================
+# AsmJit - Configuration
+# ======================
+
+if (NOT DEFINED ASMJIT_TEST)
+ set(ASMJIT_TEST FALSE)
+endif()
if (NOT DEFINED ASMJIT_EMBED)
set(ASMJIT_EMBED FALSE)
@@ -44,38 +47,53 @@ if (NOT DEFINED ASMJIT_STATIC)
set(ASMJIT_STATIC ${ASMJIT_EMBED})
endif()
-if (NOT DEFINED ASMJIT_BUILD_ARM)
- set(ASMJIT_BUILD_ARM FALSE)
+if (NOT DEFINED ASMJIT_SANITIZE)
+ set(ASMJIT_SANITIZE FALSE)
endif()
-if (NOT DEFINED ASMJIT_BUILD_X86)
- set(ASMJIT_BUILD_X86 FALSE)
+if (NOT DEFINED ASMJIT_NO_X86)
+ set(ASMJIT_NO_X86 FALSE)
endif()
-if (NOT DEFINED ASMJIT_TEST)
- set(ASMJIT_TEST FALSE)
+if (NOT DEFINED ASMJIT_NO_AARCH32)
+ set(ASMJIT_NO_AARCH32 FALSE)
+endif()
+
+if (NOT DEFINED ASMJIT_NO_AARCH64)
+ set(ASMJIT_NO_AARCH64 FALSE)
+endif()
+
+if (NOT DEFINED ASMJIT_NO_FOREIGN)
+ set(ASMJIT_NO_FOREIGN FALSE)
endif()
if (NOT DEFINED ASMJIT_NO_NATVIS)
set(ASMJIT_NO_NATVIS FALSE)
endif()
+if (NOT DEFINED ASMJIT_NO_CUSTOM_FLAGS)
+ set(ASMJIT_NO_CUSTOM_FLAGS FALSE)
+endif()
+
# EMBED implies STATIC.
if (ASMJIT_EMBED AND NOT ASMJIT_STATIC)
set(ASMJIT_STATIC TRUE)
endif()
-set(ASMJIT_DIR "${CMAKE_CURRENT_LIST_DIR}" CACHE PATH "Location of 'asmjit'")
-set(ASMJIT_TEST ${ASMJIT_TEST} CACHE BOOL "Build 'asmjit' test applications")
-set(ASMJIT_EMBED ${ASMJIT_EMBED} CACHE BOOL "Embed 'asmjit' library (no targets)")
-set(ASMJIT_STATIC ${ASMJIT_STATIC} CACHE BOOL "Build 'asmjit' library as static")
-set(ASMJIT_SANITIZE ${ASMJIT_SANITIZE} CACHE STRING "Build with sanitizers: 'address', 'undefined', etc...")
-set(ASMJIT_BUILD_X86 ${ASMJIT_BUILD_X86} CACHE BOOL "Build X86 backends (X86 and X86_64)")
-set(ASMJIT_BUILD_ARM ${ASMJIT_BUILD_ARM} CACHE BOOL "Build ARM backends (ARM/Trumb and AArch64")
-
-# =============================================================================
-# [AsmJit - Project]
-# =============================================================================
+set(ASMJIT_DIR "${CMAKE_CURRENT_LIST_DIR}" CACHE PATH "Location of 'asmjit'")
+set(ASMJIT_TEST "${ASMJIT_TEST}" CACHE BOOL "Build 'asmjit' test applications")
+set(ASMJIT_EMBED "${ASMJIT_EMBED}" CACHE BOOL "Embed 'asmjit' library (no targets)")
+set(ASMJIT_STATIC "${ASMJIT_STATIC}" CACHE BOOL "Build 'asmjit' library as static")
+set(ASMJIT_SANITIZE "${ASMJIT_SANITIZE}" CACHE STRING "Build with sanitizers: 'address', 'undefined', etc...")
+set(ASMJIT_NO_X86 "${ASMJIT_NO_X86}" CACHE BOOL "Disable X86/X64 backend")
+set(ASMJIT_NO_AARCH32 "${ASMJIT_NO_AARCH32}" CACHE BOOL "Disable AArch32 backend (ARM and THUMB)")
+set(ASMJIT_NO_AARCH64 "${ASMJIT_NO_AARCH64}" CACHE BOOL "Disable AArch64 backend")
+set(ASMJIT_NO_FOREIGN "${ASMJIT_NO_FOREIGN}" CACHE BOOL "Disable all foreign architectures (enables only a native architecture)")
+set(ASMJIT_NO_NATVIS "${ASMJIT_NO_NATVIS}" CACHE BOOL "Disable natvis support (embedding asmjit.natvis in PDB)")
+set(ASMJIT_NO_CUSTOM_FLAGS "${ASMJIT_NO_CUSTOM_FLAGS}" CACHE BOOL "Disable extra compilation flags added by AsmJit to its targets")
+
+# AsmJit - Project
+# ================
set(ASMJIT_INCLUDE_DIRS "${ASMJIT_DIR}/src") # Include directory is the same as source dir.
set(ASMJIT_DEPS "") # AsmJit dependencies (libraries) for the linker.
@@ -87,9 +105,8 @@ set(ASMJIT_PRIVATE_CFLAGS_REL "") # Private compiler flags used b
set(ASMJIT_SANITIZE_CFLAGS "") # Compiler flags required by currently enabled sanitizers.
set(ASMJIT_SANITIZE_LFLAGS "") # Linker flags required by currently enabled sanitizers.
-# =============================================================================
-# [AsmJit - Utilities]
-# =============================================================================
+# AsmJit - Utilities
+# ==================
function(asmjit_detect_cflags out)
set(out_array ${${out}})
@@ -139,6 +156,7 @@ function(asmjit_add_target target target_type)
add_library(${target} ${target_type} ${X_SOURCES})
endif()
+ set_target_properties(${target} PROPERTIES DEFINE_SYMBOL "")
target_link_libraries(${target} PRIVATE ${X_LIBRARIES})
# target_link_options was added in cmake v3.13, don't use it for now...
@@ -160,9 +178,8 @@ function(asmjit_add_target target target_type)
endif()
endfunction()
-# =============================================================================
-# [AsmJit - Compiler Support]
-# =============================================================================
+# AsmJit - Compiler Support
+# =========================
set(ASMJIT_INCLUDE_DIRS "${ASMJIT_DIR}/src") # Include directory is the same as source dir.
set(ASMJIT_DEPS "") # AsmJit dependencies (libraries) for the linker.
@@ -182,6 +199,7 @@ if (NOT ASMJIT_NO_CUSTOM_FLAGS)
list(APPEND ASMJIT_PRIVATE_CFLAGS
-MP # [+] Multi-Process Compilation.
-GF # [+] Eliminate duplicate strings.
+ -Zc:__cplusplus # [+] Conforming __cplusplus definition.
-Zc:inline # [+] Remove unreferenced COMDAT.
-Zc:strictStrings # [+] Strict const qualification of string literals.
-Zc:threadSafeInit- # [-] Thread-safe statics.
@@ -235,7 +253,7 @@ if (NOT WIN32)
list(APPEND ASMJIT_DEPS pthread)
endif()
-if ("${CMAKE_SYSTEM_NAME}" MATCHES "Linux")
+if ("${CMAKE_SYSTEM_NAME}" MATCHES "Linux" OR "${CMAKE_SYSTEM_NAME}" MATCHES "NetBSD")
list(APPEND ASMJIT_DEPS rt)
endif()
@@ -253,9 +271,12 @@ else()
endif()
foreach(build_option ASMJIT_STATIC
- ASMJIT_BUILD_X86
- #ASMJIT_BUILD_ARM
- ASMJIT_BUILD_A64
+ # AsmJit backends selection.
+ ASMJIT_NO_X86
+ ASMJIT_NO_AARCH32
+ ASMJIT_NO_AARCH64
+ ASMJIT_NO_FOREIGN
+ # AsmJit features selection.
ASMJIT_NO_DEPRECATED
ASMJIT_NO_JIT
ASMJIT_NO_LOGGING
@@ -270,9 +291,8 @@ foreach(build_option ASMJIT_STATIC
endif()
endforeach()
-# =============================================================================
-# [AsmJit - Linker Support]
-# =============================================================================
+# AsmJit - Linker Support
+# =======================
if (WIN32)
if(CMAKE_LINKER MATCHES "link\\.exe" OR CMAKE_LINKER MATCHES "lld-link\\.exe")
@@ -280,35 +300,38 @@ if (WIN32)
endif()
endif()
-# =============================================================================
-# [AsmJit - Source]
-# =============================================================================
+# AsmJit - Source
+# ===============
set(ASMJIT_SRC_LIST
asmjit/asmjit.h
+ asmjit/asmjit-scope-begin.h
+ asmjit/asmjit-scope-end.h
asmjit/core.h
asmjit/core/api-build_p.h
asmjit/core/api-config.h
- asmjit/core/arch.cpp
- asmjit/core/arch.h
+ asmjit/core/archtraits.cpp
+ asmjit/core/archtraits.h
+ asmjit/core/archcommons.h
asmjit/core/assembler.cpp
asmjit/core/assembler.h
asmjit/core/builder.cpp
asmjit/core/builder.h
- asmjit/core/callconv.cpp
- asmjit/core/callconv.h
asmjit/core/codebuffer.h
- asmjit/core/codebufferwriter_p.h
asmjit/core/codeholder.cpp
asmjit/core/codeholder.h
+ asmjit/core/codewriter.cpp
+ asmjit/core/codewriter_p.h
asmjit/core/compiler.cpp
asmjit/core/compiler.h
+ asmjit/core/compilerdefs.h
asmjit/core/constpool.cpp
asmjit/core/constpool.h
asmjit/core/cpuinfo.cpp
asmjit/core/cpuinfo.h
- asmjit/core/datatypes.h
+ asmjit/core/emithelper.cpp
+ asmjit/core/emithelper_p.h
asmjit/core/emitter.cpp
asmjit/core/emitter.h
asmjit/core/emitterutils.cpp
@@ -317,11 +340,12 @@ set(ASMJIT_SRC_LIST
asmjit/core/environment.h
asmjit/core/errorhandler.cpp
asmjit/core/errorhandler.h
- asmjit/core/features.h
asmjit/core/formatter.cpp
asmjit/core/formatter.h
asmjit/core/func.cpp
asmjit/core/func.h
+ asmjit/core/funcargscontext.cpp
+ asmjit/core/funcargscontext_p.h
asmjit/core/globals.cpp
asmjit/core/globals.h
asmjit/core/inst.cpp
@@ -370,25 +394,52 @@ set(ASMJIT_SRC_LIST
asmjit/core/zonevector.cpp
asmjit/core/zonevector.h
+ asmjit/arm.h
+ asmjit/arm/armformatter.cpp
+ asmjit/arm/armformatter_p.h
+ asmjit/arm/armglobals.h
+ asmjit/arm/armoperand.h
+ asmjit/arm/a64archtraits_p.h
+ asmjit/arm/a64assembler.cpp
+ asmjit/arm/a64assembler.h
+ asmjit/arm/a64builder.cpp
+ asmjit/arm/a64builder.h
+ asmjit/arm/a64compiler.cpp
+ asmjit/arm/a64compiler.h
+ asmjit/arm/a64emithelper.cpp
+ asmjit/arm/a64emithelper_p.h
+ asmjit/arm/a64emitter.h
+ asmjit/arm/a64formatter.cpp
+ asmjit/arm/a64formatter_p.h
+ asmjit/arm/a64func.cpp
+ asmjit/arm/a64func_p.h
+ asmjit/arm/a64globals.h
+ asmjit/arm/a64instapi.cpp
+ asmjit/arm/a64instapi_p.h
+ asmjit/arm/a64instdb.cpp
+ asmjit/arm/a64instdb.h
+ asmjit/arm/a64operand.cpp
+ asmjit/arm/a64operand.h
+ asmjit/arm/a64rapass.cpp
+ asmjit/arm/a64rapass_p.h
+ asmjit/arm/a64utils.h
+
asmjit/x86.h
- asmjit/x86/x86archdata.cpp
- asmjit/x86/x86archdata_p.h
+ asmjit/x86/x86archtraits_p.h
asmjit/x86/x86assembler.cpp
asmjit/x86/x86assembler.h
asmjit/x86/x86builder.cpp
asmjit/x86/x86builder.h
- asmjit/x86/x86callconv.cpp
- asmjit/x86/x86callconv_p.h
asmjit/x86/x86compiler.cpp
asmjit/x86/x86compiler.h
+ asmjit/x86/x86emithelper.cpp
+ asmjit/x86/x86emithelper_p.h
asmjit/x86/x86emitter.h
- asmjit/x86/x86features.cpp
- asmjit/x86/x86features.h
asmjit/x86/x86formatter.cpp
asmjit/x86/x86formatter_p.h
+ asmjit/x86/x86func.cpp
+ asmjit/x86/x86func_p.h
asmjit/x86/x86globals.h
- asmjit/x86/x86internal.cpp
- asmjit/x86/x86internal_p.h
asmjit/x86/x86instdb.cpp
asmjit/x86/x86instdb.h
asmjit/x86/x86instdb_p.h
@@ -420,9 +471,8 @@ if (NOT ${CMAKE_VERSION} VERSION_LESS "3.8.0")
source_group(TREE "${ASMJIT_DIR}" FILES ${ASMJIT_SRC})
endif()
-# =============================================================================
-# [AsmJit - Summary]
-# =============================================================================
+# AsmJit - Summary
+# ================
message("** AsmJit Summary **")
message(" ASMJIT_DIR=${ASMJIT_DIR}")
@@ -435,9 +485,8 @@ message(" ASMJIT_PRIVATE_CFLAGS=${ASMJIT_PRIVATE_CFLAGS}")
message(" ASMJIT_PRIVATE_CFLAGS_DBG=${ASMJIT_PRIVATE_CFLAGS_DBG}")
message(" ASMJIT_PRIVATE_CFLAGS_REL=${ASMJIT_PRIVATE_CFLAGS_REL}")
-# =============================================================================
-# [AsmJit - Targets]
-# =============================================================================
+# AsmJit - Targets
+# ================
if (NOT ASMJIT_EMBED)
# Add AsmJit target.
@@ -447,19 +496,33 @@ if (NOT ASMJIT_EMBED)
CFLAGS ${ASMJIT_PRIVATE_CFLAGS}
CFLAGS_DBG ${ASMJIT_PRIVATE_CFLAGS_DBG}
CFLAGS_REL ${ASMJIT_PRIVATE_CFLAGS_REL})
- target_include_directories(asmjit BEFORE INTERFACE ${ASMJIT_INCLUDE_DIRS})
+
target_compile_options(asmjit INTERFACE ${ASMJIT_CFLAGS})
+ target_include_directories(asmjit BEFORE INTERFACE
+ $<BUILD_INTERFACE:${ASMJIT_INCLUDE_DIRS}>
+ $<INSTALL_INTERFACE:${CMAKE_INSTALL_INCLUDEDIR}>)
+
+ # Add blend2d::blend2d alias.
+ add_library(asmjit::asmjit ALIAS asmjit)
+ # TODO: [CMAKE] Deprecated alias - we use projectname::libraryname convention now.
add_library(AsmJit::AsmJit ALIAS asmjit)
# Add AsmJit install instructions (library and public headers).
if (NOT ASMJIT_NO_INSTALL)
- install(TARGETS asmjit RUNTIME DESTINATION "bin"
- LIBRARY DESTINATION "lib${LIB_SUFFIX}"
- ARCHIVE DESTINATION "lib${LIB_SUFFIX}")
+ install(TARGETS asmjit
+ EXPORT asmjit-config
+ RUNTIME DESTINATION "${CMAKE_INSTALL_BINDIR}"
+ ARCHIVE DESTINATION "${CMAKE_INSTALL_LIBDIR}"
+ LIBRARY DESTINATION "${CMAKE_INSTALL_LIBDIR}"
+ INCLUDES DESTINATION "${CMAKE_INSTALL_INCLUDEDIR}")
+ install(EXPORT asmjit-config
+ NAMESPACE asmjit::
+ DESTINATION "${CMAKE_INSTALL_LIBDIR}/cmake/asmjit")
+
foreach(_src_file ${ASMJIT_SRC_LIST})
if ("${_src_file}" MATCHES "\\.h$" AND NOT "${_src_file}" MATCHES "_p\\.h$")
get_filename_component(_src_dir ${_src_file} PATH)
- install(FILES "${ASMJIT_DIR}/src/${_src_file}" DESTINATION "include/${_src_dir}")
+ install(FILES "${ASMJIT_DIR}/src/${_src_file}" DESTINATION "${CMAKE_INSTALL_INCLUDEDIR}/${_src_dir}")
endif()
endforeach()
endif()
@@ -482,50 +545,65 @@ if (NOT ASMJIT_EMBED)
CFLAGS_REL ${ASMJIT_PRIVATE_CFLAGS_REL})
target_include_directories(asmjit_test_unit BEFORE PRIVATE ${ASMJIT_INCLUDE_DIRS})
- foreach(_target asmjit_test_opcode
- asmjit_test_x86_asm
+ asmjit_add_target(asmjit_test_assembler TEST
+ SOURCES test/asmjit_test_assembler.cpp
+ test/asmjit_test_assembler.h
+ test/asmjit_test_assembler_a64.cpp
+ test/asmjit_test_assembler_x64.cpp
+ test/asmjit_test_assembler_x86.cpp
+ LIBRARIES asmjit::asmjit
+ CFLAGS ${ASMJIT_PRIVATE_CFLAGS}
+ CFLAGS_DBG ${ASMJIT_PRIVATE_CFLAGS_DBG}
+ CFLAGS_REL ${ASMJIT_PRIVATE_CFLAGS_REL})
+
+ asmjit_add_target(asmjit_test_perf EXECUTABLE
+ SOURCES test/asmjit_test_perf.cpp
+ test/asmjit_test_perf_a64.cpp
+ test/asmjit_test_perf_x86.cpp
+ SOURCES test/asmjit_test_perf.h
+ LIBRARIES asmjit::asmjit
+ CFLAGS ${ASMJIT_PRIVATE_CFLAGS}
+ CFLAGS_DBG ${ASMJIT_PRIVATE_CFLAGS_DBG}
+ CFLAGS_REL ${ASMJIT_PRIVATE_CFLAGS_REL})
+
+ foreach(_target asmjit_test_emitters
asmjit_test_x86_sections)
asmjit_add_target(${_target} TEST
SOURCES test/${_target}.cpp
- LIBRARIES AsmJit::AsmJit
+ LIBRARIES asmjit::asmjit
CFLAGS ${ASMJIT_PRIVATE_CFLAGS}
CFLAGS_DBG ${ASMJIT_PRIVATE_CFLAGS_DBG}
CFLAGS_REL ${ASMJIT_PRIVATE_CFLAGS_REL})
endforeach()
if (NOT ASMJIT_NO_INTROSPECTION)
- asmjit_add_target(asmjit_test_x86_instinfo TEST
- SOURCES test/asmjit_test_x86_instinfo.cpp
- LIBRARIES AsmJit::AsmJit
+ asmjit_add_target(asmjit_test_instinfo TEST
+ SOURCES test/asmjit_test_instinfo.cpp
+ LIBRARIES asmjit::asmjit
CFLAGS ${ASMJIT_PRIVATE_CFLAGS}
CFLAGS_DBG ${ASMJIT_PRIVATE_CFLAGS_DBG}
CFLAGS_REL ${ASMJIT_PRIVATE_CFLAGS_REL})
endif()
if (NOT (ASMJIT_NO_BUILDER OR ASMJIT_NO_COMPILER))
- # Vectorcall tests and XMM tests require at least SSE2 (required in 32-bit mode).
+ # Vectorcall tests and XMM tests require at least SSE2 in 32-bit mode (in 64-bit mode it's implicit).
set(sse2_flags "")
if ("${CMAKE_CXX_COMPILER_ID}" STREQUAL "MSVC" OR "x${CMAKE_CXX_SIMULATE_ID}" STREQUAL "xMSVC")
asmjit_detect_cflags(sse2_flags "-arch:SSE2")
else()
asmjit_detect_cflags(sse2_flags "-msse2")
endif()
- asmjit_add_target(asmjit_test_x86_cc TEST
- SOURCES test/asmjit_test_x86_cc.cpp
- LIBRARIES AsmJit::AsmJit
+ asmjit_add_target(asmjit_test_compiler TEST
+ SOURCES test/asmjit_test_compiler.cpp
+ test/asmjit_test_compiler.h
+ test/asmjit_test_compiler_a64.cpp
+ test/asmjit_test_compiler_x86.cpp
+ LIBRARIES asmjit::asmjit
CFLAGS ${ASMJIT_PRIVATE_CFLAGS} ${sse2_flags}
CFLAGS_DBG ${ASMJIT_PRIVATE_CFLAGS_DBG}
CFLAGS_REL ${ASMJIT_PRIVATE_CFLAGS_REL})
endif()
- foreach(_target asmjit_bench_x86)
- asmjit_add_target(${_target} EXECUTABLE
- SOURCES test/${_target}.cpp
- LIBRARIES AsmJit::AsmJit
- CFLAGS ${ASMJIT_PRIVATE_CFLAGS}
- CFLAGS_DBG ${ASMJIT_PRIVATE_CFLAGS_DBG}
- CFLAGS_REL ${ASMJIT_PRIVATE_CFLAGS_REL})
- endforeach()
endif()
endif()
diff --git a/3rdparty/asmjit/README.md b/3rdparty/asmjit/README.md
index abe51bb2169..c683989c656 100644
--- a/3rdparty/asmjit/README.md
+++ b/3rdparty/asmjit/README.md
@@ -23,8 +23,10 @@ Breaking the API is sometimes inevitable, what to do?
* See [Breaking Changes Guide](https://asmjit.com/doc/group__asmjit__breaking__changes.html), which is now part of AsmJit documentation.
* See asmjit tests, they always compile and provide implementation of many use-cases:
- * [asmjit_test_x86_asm.cpp](./test/asmjit_test_x86_asm.cpp) - Tests that demonstrate the purpose of emitters.
- * [asmjit_test_x86_cc.cpp](./test/asmjit_test_x86_cc.cpp) - A lot of tests targeting Compiler infrastructure.
+ * [asmjit_test_emitters.cpp](./test/asmjit_test_emitters.cpp) - Tests that demonstrate the purpose of emitters.
+ * [asmjit_test_assembler_x86.cpp](./test/asmjit_test_assembler_x86.cpp) - Tests targeting AsmJit's Assembler (x86/x64).
+ * [asmjit_test_compiler_x86.cpp](./test/asmjit_test_compiler_x86.cpp) - Tests targeting AsmJit's Compiler (x86/x64).
+ * [asmjit_test_instinfo.cpp](./test/asmjit_test_instinfo.cpp) - Tests that query instruction information.
* [asmjit_test_x86_sections.cpp](./test/asmjit_test_x86_sections.cpp) - Multiple sections test.
* Visit our [Official Chat](https://gitter.im/asmjit/asmjit) if you need a quick help.
@@ -44,12 +46,19 @@ TODO
----
* [ ] Core:
- * [ ] Add support for user external buffers in CodeHolder.
+ * [ ] Add support for user external buffers in CodeBuffer / CodeHolder.
* [ ] Ports:
- * [ ] ARM/Thumb/AArch64 support.
+ * [ ] 32-bit ARM/Thumb port.
+ * [ ] 64-bit ARM (AArch64) port.
+ * [ ] RISC-V port.
-Donors
-------
+Support
+-------
+
+ * AsmJit project has both community and commercial support, see [AsmJit's Support Page](https://asmjit.com/support.html)
+ * You can help the development and maintenance through Petr Kobalicek's [GitHub sponsors Profile](https://github.com/sponsors/kobalicek)
+
+Notable Donors List:
* [ZehMatt](https://github.com/ZehMatt)
diff --git a/3rdparty/asmjit/src/asmjit.natvis b/3rdparty/asmjit/src/asmjit.natvis
index b73d8487276..68012e0d15a 100644
--- a/3rdparty/asmjit/src/asmjit.natvis
+++ b/3rdparty/asmjit/src/asmjit.natvis
@@ -34,50 +34,94 @@
</Expand>
</Type>
- <Type Name="asmjit::Operand_">
- <Intrinsic Name="opType" Expression="(unsigned int)(_signature &amp; 0x7)" />
- <Intrinsic Name="opSize" Expression="(_signature &gt;&gt; 24) &amp; 0xFF" />
-
- <Intrinsic Name="regType" Expression="(_signature &gt;&gt; 3) &amp; 0x1F" />
- <Intrinsic Name="regGroup" Expression="(_signature &gt;&gt; 8) &amp; 0xF" />
-
- <Intrinsic Name="memBaseType" Expression="(_signature &gt;&gt; 3) &amp; 0x1F" />
- <Intrinsic Name="memIndexType" Expression="(_signature &gt;&gt; 8) &amp; 0x1F" />
- <Intrinsic Name="memAddrType" Expression="(_signature &gt;&gt; 13) &amp; 0x3" />
- <Intrinsic Name="memRegHome" Expression="(_signature &gt;&gt; 15) &amp; 0x1" />
+ <Type Name="asmjit::OperandSignature">
+ <Intrinsic Name="opType" Expression="(asmjit::OperandType)(_bits &amp; 0x7)" />
+ <Intrinsic Name="opSize" Expression="(_bits &gt;&gt; 24) &amp; 0xFF" />
+ <Intrinsic Name="regType" Expression="(asmjit::RegType)((_bits &gt;&gt; 3) &amp; 0x1F)" />
+ <Intrinsic Name="regGroup" Expression="(asmjit::RegGroup)((_bits &gt;&gt; 8) &amp; 0xF)" />
+ <Intrinsic Name="memBaseType" Expression="(asmjit::RegType)((_bits &gt;&gt; 3) &amp; 0x1F)" />
+ <Intrinsic Name="memIndexType" Expression="(asmjit::RegType)((_bits &gt;&gt; 8) &amp; 0x1F)" />
+ <Intrinsic Name="memRegHome" Expression="(bool)((_bits &gt;&gt; 13) &amp; 0x1)" />
+ <Intrinsic Name="memX86Segment" Expression="(asmjit::x86::SReg::Id)((_bits &gt;&gt; 18) &amp; 0x7)" />
+ <Intrinsic Name="memX86AddrType" Expression="(asmjit::x86::Mem::AddrType)((_bits &gt;&gt; 14) &amp; 0x3)" />
+ <Intrinsic Name="memX86ShiftValue" Expression="((_bits &gt;&gt; 16) &amp; 0x3)" />
+ <Intrinsic Name="memX86Broadcast" Expression="(asmjit::x86::Mem::Broadcast)((_bits &gt;&gt; 21) &amp; 0x7)" />
+ <Intrinsic Name="immType" Expression="(asmjit::ImmType)((_bits &gt;&gt; 3) &amp; 0x1)" />
+
+ <DisplayString Condition="opType() == asmjit::OperandType::kNone">[None]</DisplayString>
+ <DisplayString Condition="opType() == asmjit::OperandType::kReg">[Reg] {{ type={regType()} group={regGroup()} size={opSize(), d} }}</DisplayString>
+ <DisplayString Condition="opType() == asmjit::OperandType::kMem">[Mem] {{ base={memBaseType()} index={memIndexType()} }}</DisplayString>
+ <DisplayString Condition="opType() == asmjit::OperandType::kImm">[Imm] {{ type={immType()} }}</DisplayString>
+ <DisplayString Condition="opType() == asmjit::OperandType::kLabel">[Label]</DisplayString>
+ <DisplayString Condition="opType() &gt; asmjit::OperandType::kMaxValue">[Unknown]</DisplayString>
+ <Expand HideRawView="true">
+ <Item Name="bits">_bits, X</Item>
+ <Item Name="op.type">opType()</Item>
+ <Item Name="reg.type" Condition="opType() == asmjit::OperandType::kReg">regType()</Item>
+ <Item Name="reg.group" Condition="opType() == asmjit::OperandType::kReg">regGroup()</Item>
+ <Item Name="reg.size" Condition="opType() == asmjit::OperandType::kReg">opSize(), d</Item>
+ <Item Name="mem.baseType" Condition="opType() == asmjit::OperandType::kMem">memBaseType()</Item>
+ <Item Name="mem.indexType" Condition="opType() == asmjit::OperandType::kMem">memIndexType()</Item>
+ <Item Name="mem.regHome" Condition="opType() == asmjit::OperandType::kMem">memRegHome()</Item>
+ <Item Name="mem.size" Condition="opType() == asmjit::OperandType::kMem">opSize(), d</Item>
+ <Item Name="mem.x86.segment" Condition="opType() == asmjit::OperandType::kMem">memX86Segment()</Item>
+ <Item Name="mem.x86.addrType" Condition="opType() == asmjit::OperandType::kMem">memX86AddrType()</Item>
+ <Item Name="mem.x86.shift" Condition="opType() == asmjit::OperandType::kMem">memX86ShiftValue()</Item>
+ <Item Name="mem.x86.broadcast" Condition="opType() == asmjit::OperandType::kMem">memX86Broadcast()</Item>
+ <Item Name="imm.type" Condition="opType() == asmjit::OperandType::kImm">immType()</Item>
+ </Expand>
+ </Type>
+
+ <Type Name="asmjit::Operand_">
+ <Intrinsic Name="opType" Expression="(asmjit::OperandType)(_signature._bits &amp; 0x7)" />
+ <Intrinsic Name="opSize" Expression="(_signature._bits &gt;&gt; 24) &amp; 0xFF" />
+ <Intrinsic Name="regType" Expression="(asmjit::RegType)((_signature._bits &gt;&gt; 3) &amp; 0x1F)" />
+ <Intrinsic Name="regGroup" Expression="(asmjit::RegGroup)((_signature._bits &gt;&gt; 8) &amp; 0xF)" />
+ <Intrinsic Name="memBaseType" Expression="(asmjit::RegType)((_signature._bits &gt;&gt; 3) &amp; 0x1F)" />
+ <Intrinsic Name="memIndexType" Expression="(asmjit::RegType)((_signature._bits &gt;&gt; 8) &amp; 0x1F)" />
+ <Intrinsic Name="memRegHome" Expression="(bool)((_signature._bits &gt;&gt; 13) &amp; 0x1)" />
+ <Intrinsic Name="memX86Segment" Expression="(asmjit::x86::SReg::Id)((_signature._bits &gt;&gt; 18) &amp; 0x7)" />
+ <Intrinsic Name="memX86AddrType" Expression="(asmjit::x86::Mem::AddrType)((_signature._bits &gt;&gt; 14) &amp; 0x3)" />
+ <Intrinsic Name="memX86ShiftValue" Expression="((_signature._bits &gt;&gt; 16) &amp; 0x3)" />
+ <Intrinsic Name="memX86Broadcast" Expression="(asmjit::x86::Mem::Broadcast)((_signature._bits &gt;&gt; 21) &amp; 0x7)" />
<Intrinsic Name="memBaseId" Expression="_baseId" />
<Intrinsic Name="memIndexId" Expression="_data[0]" />
-
<Intrinsic Name="memOffset32b" Expression="(__int64)int(_data[1])" />
<Intrinsic Name="memOffset64b" Expression="(__int64) ((unsigned __int64)_baseId &lt;&lt; 32) | ((unsigned __int64)_data[1])" />
- <Intrinsic Name="memOffset" Expression="memBaseType() != 0 ? memOffset32b() : memOffset64b()" />
-
+ <Intrinsic Name="memOffset" Expression="memBaseType() != asmjit::RegType::kNone ? memOffset32b() : memOffset64b()" />
+ <Intrinsic Name="immType" Expression="(asmjit::ImmType)((_signature._bits &gt;&gt; 3) &amp; 0x1)" />
<Intrinsic Name="immValue" Expression="((__int64)_data[1] &lt;&lt; 32) | (__int64)_data[0]" />
- <DisplayString Condition="opType() == 0">[None]</DisplayString>
- <DisplayString Condition="opType() == 1">[Reg] {{ id={_baseId, d} group={regGroup(), d} type={regType(), d} size={opSize(), d} }}</DisplayString>
- <DisplayString Condition="opType() == 2">[Mem] {{ baseId={memBaseId(), d} indexId={memIndexId(), d} offset={(__int64)memOffset(), d} }}</DisplayString>
- <DisplayString Condition="opType() == 3">[Imm] {{ val={immValue(), d} hex={immValue(), X} }}</DisplayString>
- <DisplayString Condition="opType() == 4">[Label] {{ id={_baseId} }}</DisplayString>
+ <DisplayString Condition="opType() == asmjit::OperandType::kNone">[None]</DisplayString>
+ <DisplayString Condition="opType() == asmjit::OperandType::kReg">[Reg] {{ id={_baseId, d} group={regGroup(), d} type={regType(), d} size={opSize(), d} }}</DisplayString>
+ <DisplayString Condition="opType() == asmjit::OperandType::kMem">[Mem] {{ baseId={memBaseId(), d} indexId={memIndexId(), d} offset={(__int64)memOffset(), d} }}</DisplayString>
+ <DisplayString Condition="opType() == asmjit::OperandType::kImm">[Imm] {{ val={immValue(), d} hex={immValue(), X} }}</DisplayString>
+ <DisplayString Condition="opType() == asmjit::OperandType::kLabel">[Label] {{ id={_baseId} }}</DisplayString>
<DisplayString Condition="opType() &gt; 4">[Unknown]</DisplayString>
<Expand HideRawView="true">
- <Item Name="_signature">_signature, X</Item>
- <Item Name="_signature.any.type">(asmjit::Operand_::OpType)opType()</Item>
- <Item Name="_signature.any.size">opSize(), d</Item>
- <Item Name="_signature.reg.type" Condition="opType() == 1">(asmjit::BaseReg::RegType)regType()</Item>
- <Item Name="_signature.reg.group" Condition="opType() == 1">(asmjit::BaseReg::RegGroup)regGroup()</Item>
- <Item Name="_signature.mem.baseType" Condition="opType() == 2">(asmjit::BaseReg::RegType)memBaseType()</Item>
- <Item Name="_signature.mem.indexType" Condition="opType() == 2">(asmjit::BaseReg::RegType)memIndexType()</Item>
- <Item Name="_signature.mem.addrType" Condition="opType() == 2">(asmjit::BaseMem::AddrType)memAddrType()</Item>
- <Item Name="_signature.mem.regHome" Condition="opType() == 2">(bool)memRegHome()</Item>
- <Item Name="_baseId">_baseId</Item>
- <Item Name="_data[0]" Condition="opType() != 2 &amp;&amp; opType() != 3">_data[0]</Item>
- <Item Name="_data[1]" Condition="opType() != 2 &amp;&amp; opType() != 3">_data[1]</Item>
- <Item Name="_data[IndexId]" Condition="opType() == 2">_data[0]</Item>
- <Item Name="_data[OffsetLo]" Condition="opType() == 2">_data[1]</Item>
- <Item Name="_data[ImmHi]" Condition="opType() == 3">_data[0]</Item>
- <Item Name="_data[ImmLo]" Condition="opType() == 3">_data[1]</Item>
+ <Item Name="_signature">_signature._bits, X</Item>
+ <Item Name="op.type">opType()</Item>
+ <Item Name="op.size">opSize(), d</Item>
+ <Item Name="reg.type" Condition="opType() == asmjit::OperandType::kReg">regType()</Item>
+ <Item Name="reg.group" Condition="opType() == asmjit::OperandType::kReg">regGroup()</Item>
+ <Item Name="reg.id" Condition="opType() == asmjit::OperandType::kReg">_baseId, d</Item>
+ <Item Name="mem.baseType" Condition="opType() == asmjit::OperandType::kMem">memBaseType()</Item>
+ <Item Name="mem.baseId" Condition="opType() == asmjit::OperandType::kMem &amp;&amp; memBaseType() != asmjit::RegType::kNone">memBaseId()</Item>
+ <Item Name="mem.indexType" Condition="opType() == asmjit::OperandType::kMem">memIndexType()</Item>
+ <Item Name="mem.indexId" Condition="opType() == asmjit::OperandType::kMem &amp;&amp; memIndexType() != asmjit::RegType::kNone">memIndexId()</Item>
+ <Item Name="mem.regHome" Condition="opType() == asmjit::OperandType::kMem">memRegHome()</Item>
+ <Item Name="mem.offset" Condition="opType() == asmjit::OperandType::kMem">memOffset(), d</Item>
+ <Item Name="mem.x86.segment" Condition="opType() == asmjit::OperandType::kMem">memX86Segment()</Item>
+ <Item Name="mem.x86.addrType" Condition="opType() == asmjit::OperandType::kMem">memX86AddrType()</Item>
+ <Item Name="mem.x86.shift" Condition="opType() == asmjit::OperandType::kMem">memX86ShiftValue()</Item>
+ <Item Name="mem.x86.broadcast" Condition="opType() == asmjit::OperandType::kMem">memX86Broadcast()</Item>
+ <Item Name="imm.type" Condition="opType() == asmjit::OperandType::kImm">immType()</Item>
+ <Item Name="imm.value" Condition="opType() == asmjit::OperandType::kImm">immValue(), X</Item>
+ <Item Name="label.id" Condition="opType() == asmjit::OperandType::kLabel">_baseId, d</Item>
+ <Item Name="raw.baseId">_baseId</Item>
+ <Item Name="raw.data[0]">_data[0]</Item>
+ <Item Name="raw.data[1]">_data[1]</Item>
</Expand>
</Type>
@@ -98,7 +142,7 @@
<Expand HideRawView="true">
<Item Name="data">_data</Item>
- <Item Name="typeId">(asmjit::Type::Id)(typeId())</Item>
+ <Item Name="typeId">(asmjit::TypeId)(typeId())</Item>
<Item Name="regType" Condition="isReg()">(asmjit::BaseReg::RegType)regType()</Item>
<Item Name="regId" Condition="isReg()">regId()</Item>
<Item Name="stackOffset" Condition="isStack()">stackOffset()</Item>
@@ -108,26 +152,26 @@
<Type Name="asmjit::BaseNode">
<Intrinsic Name="nodeType" Expression="_any._nodeType" />
- <Intrinsic Name="isInst" Expression="nodeType() == asmjit::BaseNode::kNodeInst"></Intrinsic>
- <Intrinsic Name="isSection" Expression="nodeType() == asmjit::BaseNode::kNodeSection"></Intrinsic>
- <Intrinsic Name="isLabel" Expression="nodeType() == asmjit::BaseNode::kNodeLabel"></Intrinsic>
- <Intrinsic Name="isAlign" Expression="nodeType() == asmjit::BaseNode::kNodeAlign"></Intrinsic>
- <Intrinsic Name="isEmbedData" Expression="nodeType() == asmjit::BaseNode::kNodeEmbedData"></Intrinsic>
- <Intrinsic Name="isEmbedLabel" Expression="nodeType() == asmjit::BaseNode::kNodeEmbedLabel"></Intrinsic>
- <Intrinsic Name="isEmbedLabelDelta" Expression="nodeType() == asmjit::BaseNode::kNodeEmbedLabelDelta"></Intrinsic>
- <Intrinsic Name="isConstPool" Expression="nodeType() == asmjit::BaseNode::kNodeConstPool"></Intrinsic>
- <Intrinsic Name="isComment" Expression="nodeType() == asmjit::BaseNode::kNodeComment"></Intrinsic>
- <Intrinsic Name="isSentinel" Expression="nodeType() == asmjit::BaseNode::kNodeSentinel"></Intrinsic>
- <Intrinsic Name="isJump" Expression="nodeType() == asmjit::BaseNode::kNodeJump"></Intrinsic>
- <Intrinsic Name="isFunc" Expression="nodeType() == asmjit::BaseNode::kNodeFunc"></Intrinsic>
- <Intrinsic Name="isFuncRet" Expression="nodeType() == asmjit::BaseNode::kNodeFuncRet"></Intrinsic>
- <Intrinsic Name="isInvoke" Expression="nodeType() == asmjit::BaseNode::kNodeInvoke"></Intrinsic>
+ <Intrinsic Name="isInst" Expression="nodeType() == asmjit::NodeType::kInst"></Intrinsic>
+ <Intrinsic Name="isSection" Expression="nodeType() == asmjit::NodeType::kSection"></Intrinsic>
+ <Intrinsic Name="isLabel" Expression="nodeType() == asmjit::NodeType::kLabel"></Intrinsic>
+ <Intrinsic Name="isAlign" Expression="nodeType() == asmjit::NodeType::kAlign"></Intrinsic>
+ <Intrinsic Name="isEmbedData" Expression="nodeType() == asmjit::NodeType::kEmbedData"></Intrinsic>
+ <Intrinsic Name="isEmbedLabel" Expression="nodeType() == asmjit::NodeType::kEmbedLabel"></Intrinsic>
+ <Intrinsic Name="isEmbedLabelDelta" Expression="nodeType() == asmjit::NodeType::kEmbedLabelDelta"></Intrinsic>
+ <Intrinsic Name="isConstPool" Expression="nodeType() == asmjit::NodeType::kConstPool"></Intrinsic>
+ <Intrinsic Name="isComment" Expression="nodeType() == asmjit::NodeType::kComment"></Intrinsic>
+ <Intrinsic Name="isSentinel" Expression="nodeType() == asmjit::NodeType::kSentinel"></Intrinsic>
+ <Intrinsic Name="isJump" Expression="nodeType() == asmjit::NodeType::kJump"></Intrinsic>
+ <Intrinsic Name="isFunc" Expression="nodeType() == asmjit::NodeType::kFunc"></Intrinsic>
+ <Intrinsic Name="isFuncRet" Expression="nodeType() == asmjit::NodeType::kFuncRet"></Intrinsic>
+ <Intrinsic Name="isInvoke" Expression="nodeType() == asmjit::NodeType::kInvoke"></Intrinsic>
<Intrinsic Name="actsAsInst" Expression="isInst() || isJump() || isFunc() || isFuncRet() || isInvoke()" />
<Intrinsic Name="actsAsLabel" Expression="isLabel() || isFunc()" />
<DisplayString Condition="isInst()">[InstNode]</DisplayString>
- <DisplayString Condition="isSentinel()">[SectionNode]</DisplayString>
+ <DisplayString Condition="isSection()">[SectionNode]</DisplayString>
<DisplayString Condition="isLabel()">[LabelNode]</DisplayString>
<DisplayString Condition="isAlign()">[AlignNode]</DisplayString>
<DisplayString Condition="isEmbedData()">[EmbedDataNode]</DisplayString>
@@ -140,14 +184,14 @@
<DisplayString Condition="isFunc()">[FuncNode]</DisplayString>
<DisplayString Condition="isFuncRet()">[FuncRetNode]</DisplayString>
<DisplayString Condition="isInvoke()">[InvokeNode]</DisplayString>
- <DisplayString Condition="nodeType() == 0 || nodeType() &gt; 18">[UnknownNode {nodeType(), d}]</DisplayString>
+ <DisplayString Condition="nodeType() == asmjit::NodeType::kNone || nodeType() &gt; 18">[UnknownNode {nodeType(), d}]</DisplayString>
<Expand HideRawView="true">
<Item Name="prev">_prev</Item>
<Item Name="next">_next</Item>
- <Item Name="nodeType">(asmjit::BaseNode::NodeType)_any._nodeType</Item>
- <Item Name="nodeFlags">(asmjit::BaseNode::Flags)_any._nodeFlags</Item>
+ <Item Name="nodeType">_any._nodeType</Item>
+ <Item Name="nodeFlags">_any._nodeFlags</Item>
<Item Name="position">_position</Item>
<Item Name="userData.u64">_userDataU64</Item>
@@ -163,9 +207,9 @@
<Item Name="sectionId" Condition="isSection()">((asmjit::SectionNode*)this)-&gt;_id</Item>
<Item Name="nextSection" Condition="isSection()">((asmjit::SectionNode*)this)-&gt;_nextSection</Item>
- <Item Name="labelId" Condition="isLabel()">((asmjit::LabelNode*)this)-&gt;_id</Item>
+ <Item Name="labelId" Condition="isLabel()">((asmjit::LabelNode*)this)-&gt;_labelId</Item>
- <Item Name="alignMode" Condition="isAlign()">((asmjit::AlignNode*)this)-&gt;_alignMode</Item>
+ <Item Name="alignMode" Condition="isAlign()">((asmjit::AlignNode*)this)-&gt;_alignData._alignMode</Item>
<Item Name="alignment" Condition="isAlign()">((asmjit::AlignNode*)this)-&gt;_alignment</Item>
<Item Name="typeId" Condition="isEmbedData()">_embed._typeId, d</Item>
@@ -175,15 +219,15 @@
<Item Name="inlineData" Condition="isEmbedData()">((asmjit::EmbedDataNode*)this)-&gt;_inlineData</Item>
<Item Name="externalData" Condition="isEmbedData()">((asmjit::EmbedDataNode*)this)-&gt;_externalData</Item>
- <Item Name="labelId" Condition="isEmbedLabel()">((asmjit::EmbedLabelNode*)this)-&gt;_id</Item>
+ <Item Name="labelId" Condition="isEmbedLabel()">((asmjit::EmbedLabelNode*)this)-&gt;_labelId</Item>
- <Item Name="labelId" Condition="isEmbedLabelDelta()">((asmjit::EmbedLabelDeltaNode*)this)-&gt;_id</Item>
- <Item Name="baseId" Condition="isEmbedLabelDelta()">((asmjit::EmbedLabelDeltaNode*)this)-&gt;_baseId</Item>
+ <Item Name="labelId" Condition="isEmbedLabelDelta()">((asmjit::EmbedLabelDeltaNode*)this)-&gt;_labelId</Item>
+ <Item Name="baseLabelId" Condition="isEmbedLabelDelta()">((asmjit::EmbedLabelDeltaNode*)this)-&gt;_baseLabelId</Item>
<Item Name="dataSize" Condition="isEmbedLabelDelta()">((asmjit::EmbedLabelDeltaNode*)this)-&gt;_dataSize</Item>
<Item Name="constPool" Condition="isConstPool()">((asmjit::ConstPoolNode*)this)-&gt;_constPool</Item>
- <Item Name="sentinel.sentinelType" Condition="isSentinel()">(asmjit::SentinelNode::SentinelType)_sentinel._sentinelType</Item>
+ <Item Name="sentinel.sentinelType" Condition="isSentinel()">_sentinel._sentinelType</Item>
<Item Name="annotation" Condition="isJump()">((asmjit::JumpNode*)this)-&gt;_annotation</Item>
@@ -194,7 +238,7 @@
<Item Name="args" Condition="isFunc()">((asmjit::FuncNode*)this)-&gt;_args, [((asmjit::FuncNode*)this)-&gt;_funcDetail._argCount]</Item>
<Item Name="funcDetail" Condition="isInvoke()">((asmjit::InvokeNode*)this)-&gt;_funcDetail</Item>
- <Item Name="rets" Condition="isInvoke()">((asmjit::InvokeNode*)this)-&gt;_rets, [((asmjit::InvokeNode*)this)-&gt;_funcDetail._retCount]</Item>
+ <Item Name="rets" Condition="isInvoke()">((asmjit::InvokeNode*)this)-&gt;_rets</Item>
<Item Name="args" Condition="isInvoke()">((asmjit::InvokeNode*)this)-&gt;_args, [((asmjit::InvokeNode*)this)-&gt;_funcDetail._argCount]</Item>
</Expand>
</Type>
diff --git a/3rdparty/asmjit/src/asmjit/a64.h b/3rdparty/asmjit/src/asmjit/a64.h
new file mode 100644
index 00000000000..ea4d304f058
--- /dev/null
+++ b/3rdparty/asmjit/src/asmjit/a64.h
@@ -0,0 +1,62 @@
+// This file is part of AsmJit project <https://asmjit.com>
+//
+// See asmjit.h or LICENSE.md for license and copyright information
+// SPDX-License-Identifier: Zlib
+
+#ifndef ASMJIT_A64_H_INCLUDED
+#define ASMJIT_A64_H_INCLUDED
+
+//! \addtogroup asmjit_a64
+//!
+//! ### Emitters
+//!
+//! - \ref a64::Assembler - AArch64 assembler (must read, provides examples).
+//! - \ref a64::Builder - AArch64 builder.
+//! - \ref a64::Compiler - AArch64 compiler.
+//! - \ref a64::Emitter - AArch64 emitter (abstract).
+//!
+//! ### Supported Instructions
+//!
+//! - Emitters:
+//! - \ref a64::EmitterExplicitT - Provides all instructions that use explicit
+//! operands, provides also utility functions. The member functions provided
+//! are part of all ARM/AArch64 emitters.
+//!
+//! - Instruction representation:
+//! - \ref a64::Inst::Id - instruction identifiers.
+//!
+//! ### Register Operands
+//!
+//! - \ref arm::Reg - Base class for any AArch32/AArch64 register.
+//! - \ref arm::Gp - General purpose register:
+//! - \ref arm::GpW - 32-bit register.
+//! - \ref arm::GpX - 64-bit register.
+//! - \ref arm::Vec - Vector (SIMD) register:
+//! - \ref arm::VecB - 8-bit SIMD register (AArch64 only).
+//! - \ref arm::VecH - 16-bit SIMD register (AArch64 only).
+//! - \ref arm::VecS - 32-bit SIMD register.
+//! - \ref arm::VecD - 64-bit SIMD register.
+//! - \ref arm::VecV - 128-bit SIMD register.
+//!
+//! ### Memory Operands
+//!
+//! - \ref arm::Mem - AArch32/AArch64 memory operand that provides support for all ARM addressing features
+//! including base, index, pre/post increment, and ARM-specific shift addressing and index extending.
+//!
+//! ### Other
+//!
+//! - \ref arm::Shift - Shift operation and value.
+//! - \ref a64::Utils - Utilities that can help during code generation for AArch64.
+
+#include "./arm.h"
+#include "./arm/a64assembler.h"
+#include "./arm/a64builder.h"
+#include "./arm/a64compiler.h"
+#include "./arm/a64emitter.h"
+#include "./arm/a64globals.h"
+#include "./arm/a64instdb.h"
+#include "./arm/a64operand.h"
+#include "./arm/a64utils.h"
+
+#endif // ASMJIT_A64_H_INCLUDED
+
diff --git a/3rdparty/asmjit/src/asmjit/arm.h b/3rdparty/asmjit/src/asmjit/arm.h
new file mode 100644
index 00000000000..57ffa815b8c
--- /dev/null
+++ b/3rdparty/asmjit/src/asmjit/arm.h
@@ -0,0 +1,62 @@
+// This file is part of AsmJit project <https://asmjit.com>
+//
+// See asmjit.h or LICENSE.md for license and copyright information
+// SPDX-License-Identifier: Zlib
+
+#ifndef ASMJIT_ARM_H_INCLUDED
+#define ASMJIT_ARM_H_INCLUDED
+
+//! \addtogroup asmjit_arm
+//!
+//! ### Namespaces
+//!
+//! - \ref arm - arm namespace provides common functionality for both AArch32 and AArch64 backends.
+//! - \ref a64 - a64 namespace provides support for AArch64 architecture. In addition it includes
+//! \ref arm namespace, so you can only use a single namespace when targeting AArch64 architecture.
+//!
+//! ### Emitters
+//!
+//! - AArch64
+//! - \ref a64::Assembler - AArch64 assembler (must read, provides examples).
+//! - \ref a64::Builder - AArch64 builder.
+//! - \ref a64::Compiler - AArch64 compiler.
+//! - \ref a64::Emitter - AArch64 emitter (abstract).
+//!
+//! ### Supported Instructions
+//!
+//! - AArch64:
+//! - Emitters:
+//! - \ref a64::EmitterExplicitT - Provides all instructions that use explicit operands, provides also
+//! utility functions. The member functions provided are part of all AArch64 emitters.
+//! - Instruction representation:
+//! - \ref a64::Inst::Id - instruction identifiers.
+//!
+//! ### Register Operands
+//!
+//! - \ref arm::Reg - Base class for any AArch32/AArch64 register.
+//! - \ref arm::Gp - General purpose register:
+//! - \ref arm::GpW - 32-bit register.
+//! - \ref arm::GpX - 64-bit register.
+//! - \ref arm::Vec - Vector (SIMD) register:
+//! - \ref arm::VecB - 8-bit SIMD register (AArch64 only).
+//! - \ref arm::VecH - 16-bit SIMD register (AArch64 only).
+//! - \ref arm::VecS - 32-bit SIMD register.
+//! - \ref arm::VecD - 64-bit SIMD register.
+//! - \ref arm::VecV - 128-bit SIMD register.
+//!
+//! ### Memory Operands
+//!
+//! - \ref arm::Mem - AArch32/AArch64 memory operand that provides support for all ARM addressing features
+//! including base, index, pre/post increment, and ARM-specific shift addressing and index extending.
+//!
+//! ### Other
+//!
+//! - \ref arm::Shift - Shift operation and value (both AArch32 and AArch64).
+//! - \ref arm::DataType - Data type that is part of an instruction in AArch32 mode.
+//! - \ref a64::Utils - Utilities that can help during code generation for AArch64.
+
+#include "./core.h"
+#include "./arm/armglobals.h"
+#include "./arm/armoperand.h"
+
+#endif // ASMJIT_ARM_H_INCLUDED
diff --git a/3rdparty/asmjit/src/asmjit/arm/a64archtraits_p.h b/3rdparty/asmjit/src/asmjit/arm/a64archtraits_p.h
new file mode 100644
index 00000000000..87559c71d5a
--- /dev/null
+++ b/3rdparty/asmjit/src/asmjit/arm/a64archtraits_p.h
@@ -0,0 +1,81 @@
+// This file is part of AsmJit project <https://asmjit.com>
+//
+// See asmjit.h or LICENSE.md for license and copyright information
+// SPDX-License-Identifier: Zlib
+
+#ifndef ASMJIT_ARM_A64ARCHTRAITS_P_H_INCLUDED
+#define ASMJIT_ARM_A64ARCHTRAITS_P_H_INCLUDED
+
+#include "../core/archtraits.h"
+#include "../core/misc_p.h"
+#include "../core/type.h"
+#include "../arm/a64operand.h"
+
+ASMJIT_BEGIN_SUB_NAMESPACE(a64)
+
+//! \cond INTERNAL
+//! \addtogroup asmjit_a64
+//! \{
+
+static const constexpr ArchTraits a64ArchTraits = {
+ // SP/FP/LR/PC.
+ Gp::kIdSp, Gp::kIdFp, Gp::kIdLr, 0xFF,
+
+ // Reserved.
+ { 0, 0, 0 },
+
+ // HW stack alignment (AArch64 requires stack aligned to 64 bytes).
+ 16,
+
+ // Min/max stack offset - byte addressing is the worst, VecQ addressing the best.
+ 4095, 65520,
+
+ // Instruction hints [Gp, Vec, ExtraVirt2, ExtraVirt3].
+ {{
+ InstHints::kPushPop,
+ InstHints::kPushPop,
+ InstHints::kNoHints,
+ InstHints::kNoHints
+ }},
+
+ // RegInfo.
+ #define V(index) OperandSignature{arm::RegTraits<RegType(index)>::kSignature}
+ {{ ASMJIT_LOOKUP_TABLE_32(V, 0) }},
+ #undef V
+
+ // RegTypeToTypeId.
+ #define V(index) TypeId(arm::RegTraits<RegType(index)>::kTypeId)
+ {{ ASMJIT_LOOKUP_TABLE_32(V, 0) }},
+ #undef V
+
+ // TypeIdToRegType.
+ #define V(index) (index + uint32_t(TypeId::_kBaseStart) == uint32_t(TypeId::kInt8) ? RegType::kARM_GpW : \
+ index + uint32_t(TypeId::_kBaseStart) == uint32_t(TypeId::kUInt8) ? RegType::kARM_GpW : \
+ index + uint32_t(TypeId::_kBaseStart) == uint32_t(TypeId::kInt16) ? RegType::kARM_GpW : \
+ index + uint32_t(TypeId::_kBaseStart) == uint32_t(TypeId::kUInt16) ? RegType::kARM_GpW : \
+ index + uint32_t(TypeId::_kBaseStart) == uint32_t(TypeId::kInt32) ? RegType::kARM_GpW : \
+ index + uint32_t(TypeId::_kBaseStart) == uint32_t(TypeId::kUInt32) ? RegType::kARM_GpW : \
+ index + uint32_t(TypeId::_kBaseStart) == uint32_t(TypeId::kInt64) ? RegType::kARM_GpX : \
+ index + uint32_t(TypeId::_kBaseStart) == uint32_t(TypeId::kUInt64) ? RegType::kARM_GpX : \
+ index + uint32_t(TypeId::_kBaseStart) == uint32_t(TypeId::kIntPtr) ? RegType::kARM_GpX : \
+ index + uint32_t(TypeId::_kBaseStart) == uint32_t(TypeId::kUIntPtr) ? RegType::kARM_GpX : \
+ index + uint32_t(TypeId::_kBaseStart) == uint32_t(TypeId::kFloat32) ? RegType::kARM_VecS : \
+ index + uint32_t(TypeId::_kBaseStart) == uint32_t(TypeId::kFloat64) ? RegType::kARM_VecD : RegType::kNone)
+ {{ ASMJIT_LOOKUP_TABLE_32(V, 0) }},
+ #undef V
+
+ // Word names of 8-bit, 16-bit, 32-bit, and 64-bit quantities.
+ {
+ ArchTypeNameId::kByte,
+ ArchTypeNameId::kHWord,
+ ArchTypeNameId::kWord,
+ ArchTypeNameId::kXWord
+ }
+};
+
+//! \}
+//! \endcond
+
+ASMJIT_END_SUB_NAMESPACE
+
+#endif // ASMJIT_ARM_A64ARCHTRAITS_P_H_INCLUDED
diff --git a/3rdparty/asmjit/src/asmjit/arm/a64assembler.cpp b/3rdparty/asmjit/src/asmjit/arm/a64assembler.cpp
new file mode 100644
index 00000000000..9f8c9b1a9f2
--- /dev/null
+++ b/3rdparty/asmjit/src/asmjit/arm/a64assembler.cpp
@@ -0,0 +1,5115 @@
+// This file is part of AsmJit project <https://asmjit.com>
+//
+// See asmjit.h or LICENSE.md for license and copyright information
+// SPDX-License-Identifier: Zlib
+
+#include "../core/api-build_p.h"
+#if !defined(ASMJIT_NO_AARCH64)
+
+#include "../core/codewriter_p.h"
+#include "../core/cpuinfo.h"
+#include "../core/emitterutils_p.h"
+#include "../core/formatter.h"
+#include "../core/logger.h"
+#include "../core/misc_p.h"
+#include "../core/support.h"
+#include "../arm/armformatter_p.h"
+#include "../arm/a64assembler.h"
+#include "../arm/a64emithelper_p.h"
+#include "../arm/a64instdb_p.h"
+#include "../arm/a64utils.h"
+
+ASMJIT_BEGIN_SUB_NAMESPACE(a64)
+
+// a64::Assembler - Cond
+// =====================
+
+static inline uint32_t condCodeToOpcodeCond(uint32_t cond) noexcept {
+ return (uint32_t(cond) - 2u) & 0xFu;
+}
+
+// a64::Assembler - Bits
+// =====================
+
+template<typename T>
+static inline constexpr uint32_t B(const T& index) noexcept { return uint32_t(1u) << uint32_t(index); }
+
+static constexpr uint32_t kSP = Gp::kIdSp;
+static constexpr uint32_t kZR = Gp::kIdZr;
+static constexpr uint32_t kWX = InstDB::kWX;
+
+// a64::Assembler - ShiftOpToLdStOptMap
+// ====================================
+
+// Table that maps ShiftOp to OPT part in LD/ST (register) opcode.
+#define VALUE(index) index == uint32_t(ShiftOp::kUXTW) ? 2u : \
+ index == uint32_t(ShiftOp::kLSL) ? 3u : \
+ index == uint32_t(ShiftOp::kSXTW) ? 6u : \
+ index == uint32_t(ShiftOp::kSXTX) ? 7u : 0xFF
+static const uint8_t armShiftOpToLdStOptMap[] = { ASMJIT_LOOKUP_TABLE_16(VALUE, 0) };
+#undef VALUE
+
+static inline constexpr uint32_t diff(RegType a, RegType b) noexcept {
+ return uint32_t(a) - uint32_t(b);
+}
+
+// asmjit::a64::Assembler - SizeOp
+// ===============================
+
+//! Struct that contains Size (2 bits), Q flag, and S (scalar) flag. These values
+//! are used to encode Q, Size, and Scalar fields in an opcode.
+struct SizeOp {
+ enum : uint8_t {
+ k128BitShift = 0,
+ kScalarShift = 1,
+ kSizeShift = 2,
+
+ kQ = uint8_t(1u << k128BitShift),
+ kS = uint8_t(1u << kScalarShift),
+
+ k00 = uint8_t(0 << kSizeShift),
+ k01 = uint8_t(1 << kSizeShift),
+ k10 = uint8_t(2 << kSizeShift),
+ k11 = uint8_t(3 << kSizeShift),
+
+ k00Q = k00 | kQ,
+ k01Q = k01 | kQ,
+ k10Q = k10 | kQ,
+ k11Q = k11 | kQ,
+
+ k00S = k00 | kS,
+ k01S = k01 | kS,
+ k10S = k10 | kS,
+ k11S = k11 | kS,
+
+ kInvalid = 0xFFu,
+
+ // Masks used by SizeOpMap.
+ kSzQ = (0x3u << kSizeShift) | kQ,
+ kSzS = (0x3u << kSizeShift) | kS,
+ kSzQS = (0x3u << kSizeShift) | kQ | kS
+ };
+
+ uint8_t value;
+
+ inline bool isValid() const noexcept { return value != kInvalid; }
+ inline void makeInvalid() noexcept { value = kInvalid; }
+
+ inline uint32_t q() const noexcept { return (value >> k128BitShift) & 0x1u; }
+ inline uint32_t qs() const noexcept { return ((value >> k128BitShift) | (value >> kScalarShift)) & 0x1u; }
+ inline uint32_t scalar() const noexcept { return (value >> kScalarShift) & 0x1u; }
+ inline uint32_t size() const noexcept { return (value >> kSizeShift) & 0x3u; }
+
+ inline void decrementSize() noexcept {
+ ASMJIT_ASSERT(size() > 0);
+ value = uint8_t(value - (1u << kSizeShift));
+ }
+};
+
+struct SizeOpTable {
+ enum TableId : uint8_t {
+ kTableBin = 0,
+ kTableAny,
+ kCount
+ };
+
+ // 40 elements for each combination.
+ SizeOp array[(uint32_t(RegType::kARM_VecV) - uint32_t(RegType::kARM_VecB) + 1) * 8];
+};
+
+#define VALUE_BIN(x) { \
+ x == (((uint32_t(RegType::kARM_VecD) - uint32_t(RegType::kARM_VecB)) << 3) | (Vec::kElementTypeNone)) ? SizeOp::k00 : \
+ x == (((uint32_t(RegType::kARM_VecV) - uint32_t(RegType::kARM_VecB)) << 3) | (Vec::kElementTypeNone)) ? SizeOp::k00Q : \
+ x == (((uint32_t(RegType::kARM_VecD) - uint32_t(RegType::kARM_VecB)) << 3) | (Vec::kElementTypeB )) ? SizeOp::k00 : \
+ x == (((uint32_t(RegType::kARM_VecV) - uint32_t(RegType::kARM_VecB)) << 3) | (Vec::kElementTypeB )) ? SizeOp::k00Q : SizeOp::kInvalid \
+}
+
+#define VALUE_ANY(x) { \
+ x == (((uint32_t(RegType::kARM_VecB) - uint32_t(RegType::kARM_VecB)) << 3) | (Vec::kElementTypeNone)) ? SizeOp::k00S : \
+ x == (((uint32_t(RegType::kARM_VecH) - uint32_t(RegType::kARM_VecB)) << 3) | (Vec::kElementTypeNone)) ? SizeOp::k01S : \
+ x == (((uint32_t(RegType::kARM_VecS) - uint32_t(RegType::kARM_VecB)) << 3) | (Vec::kElementTypeNone)) ? SizeOp::k10S : \
+ x == (((uint32_t(RegType::kARM_VecD) - uint32_t(RegType::kARM_VecB)) << 3) | (Vec::kElementTypeNone)) ? SizeOp::k11S : \
+ x == (((uint32_t(RegType::kARM_VecD) - uint32_t(RegType::kARM_VecB)) << 3) | (Vec::kElementTypeB )) ? SizeOp::k00 : \
+ x == (((uint32_t(RegType::kARM_VecV) - uint32_t(RegType::kARM_VecB)) << 3) | (Vec::kElementTypeB )) ? SizeOp::k00Q : \
+ x == (((uint32_t(RegType::kARM_VecD) - uint32_t(RegType::kARM_VecB)) << 3) | (Vec::kElementTypeH )) ? SizeOp::k01 : \
+ x == (((uint32_t(RegType::kARM_VecV) - uint32_t(RegType::kARM_VecB)) << 3) | (Vec::kElementTypeH )) ? SizeOp::k01Q : \
+ x == (((uint32_t(RegType::kARM_VecD) - uint32_t(RegType::kARM_VecB)) << 3) | (Vec::kElementTypeS )) ? SizeOp::k10 : \
+ x == (((uint32_t(RegType::kARM_VecV) - uint32_t(RegType::kARM_VecB)) << 3) | (Vec::kElementTypeS )) ? SizeOp::k10Q : \
+ x == (((uint32_t(RegType::kARM_VecD) - uint32_t(RegType::kARM_VecB)) << 3) | (Vec::kElementTypeD )) ? SizeOp::k11S : \
+ x == (((uint32_t(RegType::kARM_VecV) - uint32_t(RegType::kARM_VecB)) << 3) | (Vec::kElementTypeD )) ? SizeOp::k11Q : SizeOp::kInvalid \
+}
+
+static const SizeOpTable sizeOpTable[SizeOpTable::kCount] = {
+ {{ ASMJIT_LOOKUP_TABLE_40(VALUE_BIN, 0) }},
+ {{ ASMJIT_LOOKUP_TABLE_40(VALUE_ANY, 0) }}
+};
+
+#undef VALUE_ANY
+#undef VALUE_BIN
+
+struct SizeOpMap {
+ uint8_t tableId;
+ uint8_t sizeOpMask;
+ uint16_t acceptMask;
+};
+
+static const constexpr SizeOpMap sizeOpMap[InstDB::kVO_Count] = {
+ { // kVO_V_B:
+ SizeOpTable::kTableBin, SizeOp::kQ , uint16_t(B(SizeOp::k00) | B(SizeOp::k00Q))
+ },
+
+ { // kVO_V_BH:
+ SizeOpTable::kTableAny, SizeOp::kSzQS, uint16_t(B(SizeOp::k00) | B(SizeOp::k00Q) | B(SizeOp::k01) | B(SizeOp::k01Q))
+ },
+
+ { // kVO_V_BH_4S:
+ SizeOpTable::kTableAny, SizeOp::kSzQS, uint16_t(B(SizeOp::k00) | B(SizeOp::k00Q) | B(SizeOp::k01) | B(SizeOp::k01Q) | B(SizeOp::k10Q))
+ },
+
+ { // kVO_V_BHS:
+ SizeOpTable::kTableAny, SizeOp::kSzQS, uint16_t(B(SizeOp::k00) | B(SizeOp::k00Q) | B(SizeOp::k01) | B(SizeOp::k01Q) | B(SizeOp::k10) | B(SizeOp::k10Q))
+ },
+
+ { // kVO_V_BHS_D2:
+ SizeOpTable::kTableAny, SizeOp::kSzQS, uint16_t(B(SizeOp::k00) | B(SizeOp::k00Q) | B(SizeOp::k01) | B(SizeOp::k01Q) | B(SizeOp::k10) | B(SizeOp::k10Q) | B(SizeOp::k11Q))
+ },
+
+ { // kVO_V_HS:
+ SizeOpTable::kTableAny, SizeOp::kSzQS, uint16_t(B(SizeOp::k01) | B(SizeOp::k01Q) | B(SizeOp::k10) | B(SizeOp::k10Q))
+ },
+
+ { // kVO_V_S:
+ SizeOpTable::kTableAny, SizeOp::kQ , uint16_t(B(SizeOp::k10) | B(SizeOp::k10Q))
+ },
+
+ { // kVO_V_B8H4:
+ SizeOpTable::kTableAny, SizeOp::kSzQS, uint16_t(B(SizeOp::k00) | B(SizeOp::k01))
+ },
+
+ { // kVO_V_B8H4S2:
+ SizeOpTable::kTableAny, SizeOp::kSzQS, uint16_t(B(SizeOp::k00) | B(SizeOp::k01) | B(SizeOp::k10))
+ },
+
+ { // kVO_V_B8D1:
+ SizeOpTable::kTableAny, SizeOp::kSzQ , uint16_t(B(SizeOp::k00) | B(SizeOp::k11S))
+ },
+
+ { // kVO_V_H4S2:
+ SizeOpTable::kTableAny, SizeOp::kSzQS, uint16_t(B(SizeOp::k01) | B(SizeOp::k10))
+ },
+
+ { // kVO_V_B16:
+ SizeOpTable::kTableBin, SizeOp::kQ , uint16_t(B(SizeOp::k00Q))
+ },
+
+ { // kVO_V_B16H8:
+ SizeOpTable::kTableAny, SizeOp::kSzQS, uint16_t(B(SizeOp::k00Q) | B(SizeOp::k01Q))
+ },
+
+ { // kVO_V_B16H8S4:
+ SizeOpTable::kTableAny, SizeOp::kSzQS, uint16_t(B(SizeOp::k00Q) | B(SizeOp::k01Q) | B(SizeOp::k10Q))
+ },
+
+ { // kVO_V_B16D2:
+ SizeOpTable::kTableAny, SizeOp::kSzQS, uint16_t(B(SizeOp::k00Q) | B(SizeOp::k11Q))
+ },
+
+ { // kVO_V_H8S4:
+ SizeOpTable::kTableAny, SizeOp::kSzQS, uint16_t(B(SizeOp::k01Q) | B(SizeOp::k10Q))
+ },
+
+ { // kVO_V_S4:
+ SizeOpTable::kTableAny, 0 , uint16_t(B(SizeOp::k10Q))
+ },
+
+ { // kVO_V_D2:
+ SizeOpTable::kTableAny, 0 , uint16_t(B(SizeOp::k11Q))
+ },
+
+ { // kVO_SV_BHS:
+ SizeOpTable::kTableAny, SizeOp::kSzQS, uint16_t(B(SizeOp::k00) | B(SizeOp::k00Q) | B(SizeOp::k00S) | B(SizeOp::k01) | B(SizeOp::k01Q) | B(SizeOp::k01S) | B(SizeOp::k10) | B(SizeOp::k10Q) | B(SizeOp::k10S))
+ },
+
+ { // kVO_SV_B8H4S2:
+ SizeOpTable::kTableAny, SizeOp::kSzQS, uint16_t(B(SizeOp::k00) | B(SizeOp::k00S) | B(SizeOp::k01) | B(SizeOp::k01S) | B(SizeOp::k10) | B(SizeOp::k10S))
+ },
+
+ { // kVO_SV_HS:
+ SizeOpTable::kTableAny, SizeOp::kSzQS, uint16_t(B(SizeOp::k01) | B(SizeOp::k01Q) | B(SizeOp::k01S) | B(SizeOp::k10) | B(SizeOp::k10Q) | B(SizeOp::k10S))
+ },
+
+ { // kVO_V_Any:
+ SizeOpTable::kTableAny, SizeOp::kSzQS, uint16_t(B(SizeOp::k00) | B(SizeOp::k00Q) | B(SizeOp::k01) | B(SizeOp::k01Q) | B(SizeOp::k10) | B(SizeOp::k10Q) | B(SizeOp::k11S) | B(SizeOp::k11Q))
+ },
+
+ { // kVO_SV_Any:
+ SizeOpTable::kTableAny, SizeOp::kSzQS, uint16_t(B(SizeOp::k00) | B(SizeOp::k00Q) | B(SizeOp::k00S) |
+ B(SizeOp::k01) | B(SizeOp::k01Q) | B(SizeOp::k01S) |
+ B(SizeOp::k10) | B(SizeOp::k10Q) | B(SizeOp::k10S) |
+ B(SizeOp::k11) | B(SizeOp::k11Q) | B(SizeOp::k11S))
+ }
+};
+
+static const Operand_& significantSimdOp(const Operand_& o0, const Operand_& o1, uint32_t instFlags) noexcept {
+ return !(instFlags & InstDB::kInstFlagLong) ? o0 : o1;
+}
+
+static inline SizeOp armElementTypeToSizeOp(uint32_t vecOpType, RegType regType, uint32_t elementType) noexcept {
+ // Instruction data or Assembler is wrong if this triggers an assertion failure.
+ ASMJIT_ASSERT(vecOpType < InstDB::kVO_Count);
+ // ElementType uses 3 bits in the operand signature, it should never overflow.
+ ASMJIT_ASSERT(elementType <= 0x7u);
+
+ const SizeOpMap& map = sizeOpMap[vecOpType];
+ const SizeOpTable& table = sizeOpTable[map.tableId];
+
+ size_t index = (Support::min<uint32_t>(diff(regType, RegType::kARM_VecB), diff(RegType::kARM_VecV, RegType::kARM_VecB) + 1) << 3) | elementType;
+ SizeOp op = table.array[index];
+ SizeOp modifiedOp { uint8_t(op.value & map.sizeOpMask) };
+
+ if (!Support::bitTest(map.acceptMask, op.value))
+ modifiedOp.makeInvalid();
+
+ return modifiedOp;
+}
+
+// a64::Assembler - Immediate Encoding Utilities (Integral)
+// ========================================================
+
+using Utils::LogicalImm;
+
+struct HalfWordImm {
+ uint32_t hw;
+ uint32_t inv;
+ uint32_t imm;
+};
+
+struct LMHImm {
+ uint32_t lm;
+ uint32_t h;
+ uint32_t maxRmId;
+};
+
+static inline uint32_t countZeroHalfWords64(uint64_t imm) noexcept {
+ return uint32_t((imm & 0x000000000000FFFFu) == 0) +
+ uint32_t((imm & 0x00000000FFFF0000u) == 0) +
+ uint32_t((imm & 0x0000FFFF00000000u) == 0) +
+ uint32_t((imm & 0xFFFF000000000000u) == 0) ;
+}
+
+static uint32_t encodeMovSequence32(uint32_t out[2], uint32_t imm, uint32_t rd, uint32_t x) noexcept {
+ ASMJIT_ASSERT(rd <= 31);
+
+ uint32_t kMovZ = 0b01010010100000000000000000000000 | (x << 31);
+ uint32_t kMovN = 0b00010010100000000000000000000000;
+ uint32_t kMovK = 0b01110010100000000000000000000000;
+
+ if ((imm & 0xFFFF0000u) == 0x00000000u) {
+ out[0] = kMovZ | (0 << 21) | ((imm & 0xFFFFu) << 5) | rd;
+ return 1;
+ }
+
+ if ((imm & 0xFFFF0000u) == 0xFFFF0000u) {
+ out[0] = kMovN | (0 << 21) | ((~imm & 0xFFFFu) << 5) | rd;
+ return 1;
+ }
+
+ if ((imm & 0x0000FFFFu) == 0x00000000u) {
+ out[0] = kMovZ | (1 << 21) | ((imm >> 16) << 5) | rd;
+ return 1;
+ }
+
+ if ((imm & 0x0000FFFFu) == 0x0000FFFFu) {
+ out[0] = kMovN | (1 << 21) | ((~imm >> 16) << 5) | rd;
+ return 1;
+ }
+
+ out[0] = kMovZ | (0 << 21) | ((imm & 0xFFFFu) << 5) | rd;
+ out[1] = kMovK | (1 << 21) | ((imm >> 16) << 5) | rd;
+ return 2;
+}
+
+static uint32_t encodeMovSequence64(uint32_t out[4], uint64_t imm, uint32_t rd, uint32_t x) noexcept {
+ ASMJIT_ASSERT(rd <= 31);
+
+ uint32_t kMovZ = 0b11010010100000000000000000000000;
+ uint32_t kMovN = 0b10010010100000000000000000000000;
+ uint32_t kMovK = 0b11110010100000000000000000000000;
+
+ if (imm <= 0xFFFFFFFFu)
+ return encodeMovSequence32(out, uint32_t(imm), rd, x);
+
+ uint32_t zhw = countZeroHalfWords64( imm);
+ uint32_t ohw = countZeroHalfWords64(~imm);
+
+ if (zhw >= ohw) {
+ uint32_t op = kMovZ;
+ uint32_t count = 0;
+
+ for (uint32_t hwIndex = 0; hwIndex < 4; hwIndex++, imm >>= 16) {
+ uint32_t hwImm = uint32_t(imm & 0xFFFFu);
+ if (hwImm == 0)
+ continue;
+
+ out[count++] = op | (hwIndex << 21) | (hwImm << 5) | rd;
+ op = kMovK;
+ }
+
+ // This should not happen - zero should be handled by encodeMovSequence32().
+ ASMJIT_ASSERT(count > 0);
+
+ return count;
+ }
+ else {
+ uint32_t op = kMovN;
+ uint32_t count = 0;
+ uint32_t negMask = 0xFFFFu;
+
+ for (uint32_t hwIndex = 0; hwIndex < 4; hwIndex++, imm >>= 16) {
+ uint32_t hwImm = uint32_t(imm & 0xFFFFu);
+ if (hwImm == 0xFFFFu)
+ continue;
+
+ out[count++] = op | (hwIndex << 21) | ((hwImm ^ negMask) << 5) | rd;
+ op = kMovK;
+ negMask = 0;
+ }
+
+ if (count == 0) {
+ out[count++] = kMovN | ((0xFFFF ^ negMask) << 5) | rd;
+ }
+
+ return count;
+ }
+}
+
+static inline bool encodeLMH(uint32_t sizeField, uint32_t elementIndex, LMHImm* out) noexcept {
+ if (sizeField != 1 && sizeField != 2)
+ return false;
+
+ uint32_t hShift = 3u - sizeField;
+ uint32_t lmShift = sizeField - 1u;
+ uint32_t maxElementIndex = 15u >> sizeField;
+
+ out->h = elementIndex >> hShift;
+ out->lm = (elementIndex << lmShift) & 0x3u;
+ out->maxRmId = (8u << sizeField) - 1;
+
+ return elementIndex <= maxElementIndex;
+}
+
+// [.......A|B.......|.......C|D.......|.......E|F.......|.......G|H.......]
+static inline uint32_t encodeImm64ByteMaskToImm8(uint64_t imm) noexcept {
+ return uint32_t(((imm >> (7 - 0)) & 0b00000011) | // [.......G|H.......]
+ ((imm >> (23 - 2)) & 0b00001100) | // [.......E|F.......]
+ ((imm >> (39 - 4)) & 0b00110000) | // [.......C|D.......]
+ ((imm >> (55 - 6)) & 0b11000000)); // [.......A|B.......]
+}
+
+// a64::Assembler - Opcode
+// =======================
+
+//! Helper class to store and manipulate ARM opcode.
+struct Opcode {
+ uint32_t v;
+
+ enum Bits : uint32_t {
+ kN = (1u << 22),
+ kQ = (1u << 30),
+ kX = (1u << 31)
+ };
+
+ // --------------------------------------------------------------------------
+ // [Opcode Builder]
+ // --------------------------------------------------------------------------
+
+ inline uint32_t get() const noexcept { return v; }
+ inline void reset(uint32_t value) noexcept { v = value; }
+
+ inline bool hasQ() const noexcept { return (v & kQ) != 0; }
+ inline bool hasX() const noexcept { return (v & kX) != 0; }
+
+ template<typename T>
+ inline Opcode& addImm(T value, uint32_t bitIndex) noexcept { return operator|=(uint32_t(value) << bitIndex); }
+
+ template<typename T>
+ inline Opcode& xorImm(T value, uint32_t bitIndex) noexcept { return operator^=(uint32_t(value) << bitIndex); }
+
+ template<typename T, typename Condition>
+ inline Opcode& addIf(T value, const Condition& condition) noexcept { return operator|=(condition ? uint32_t(value) : uint32_t(0)); }
+
+ inline Opcode& addLogicalImm(const LogicalImm& logicalImm) noexcept {
+ addImm(logicalImm.n, 22);
+ addImm(logicalImm.r, 16);
+ addImm(logicalImm.s, 10);
+ return *this;
+ }
+
+ inline Opcode& addReg(uint32_t id, uint32_t bitIndex) noexcept { return operator|=((id & 31u) << bitIndex); }
+ inline Opcode& addReg(const Operand_& op, uint32_t bitIndex) noexcept { return addReg(op.id(), bitIndex); }
+
+ inline Opcode& operator=(uint32_t x) noexcept { v = x; return *this; }
+ inline Opcode& operator&=(uint32_t x) noexcept { v &= x; return *this; }
+ inline Opcode& operator|=(uint32_t x) noexcept { v |= x; return *this; }
+ inline Opcode& operator^=(uint32_t x) noexcept { v ^= x; return *this; }
+
+ inline uint32_t operator&(uint32_t x) const noexcept { return v & x; }
+ inline uint32_t operator|(uint32_t x) const noexcept { return v | x; }
+ inline uint32_t operator^(uint32_t x) const noexcept { return v ^ x; }
+};
+
+// a64::Assembler - Signature Utilities
+// ====================================
+
+// TODO: [ARM] Deprecate matchSignature.
+static inline bool matchSignature(const Operand_& o0, const Operand_& o1, uint32_t instFlags) noexcept {
+ if (!(instFlags & (InstDB::kInstFlagLong | InstDB::kInstFlagNarrow)))
+ return o0.signature() == o1.signature();
+
+ // TODO: [ARM] Something smart to validate this.
+ return true;
+}
+
+static inline bool matchSignature(const Operand_& o0, const Operand_& o1, const Operand_& o2, uint32_t instFlags) noexcept {
+ return matchSignature(o0, o1, instFlags) && o1.signature() == o2.signature();
+}
+
+static inline bool matchSignature(const Operand_& o0, const Operand_& o1, const Operand_& o2, const Operand_& o3, uint32_t instFlags) noexcept {
+ return matchSignature(o0, o1, instFlags) && o1.signature() == o2.signature() && o2.signature() == o3.signature();;
+}
+
+// Memory must be either:
+// 1. Absolute address, which will be converted to relative.
+// 2. Relative displacement (Label).
+// 3. Base register + either offset or index.
+static inline bool armCheckMemBaseIndexRel(const Mem& mem) noexcept {
+ // Allowed base types (Nothing, Label, and GpX).
+ constexpr uint32_t kBaseMask = B(0) |
+ B(RegType::kLabelTag) |
+ B(RegType::kARM_GpX);
+
+ // Allowed index types (Nothing, GpW, and GpX).
+ constexpr uint32_t kIndexMask = B(0) |
+ B(RegType::kARM_GpW) |
+ B(RegType::kARM_GpX) ;
+
+ RegType baseType = mem.baseType();
+ RegType indexType = mem.indexType();
+
+ if (!Support::bitTest(kBaseMask, baseType))
+ return false;
+
+ if (baseType > RegType::kLabelTag) {
+ // Index allows either GpW or GpX.
+ if (!Support::bitTest(kIndexMask, indexType))
+ return false;
+
+ if (indexType == RegType::kNone)
+ return true;
+ else
+ return !mem.hasOffset();
+ }
+ else {
+ // No index register allowed if this is a PC relative address (literal).
+ return indexType == RegType::kNone;
+ }
+}
+
+struct EncodeFpOpcodeBits {
+ uint32_t sizeMask;
+ uint32_t mask[3];
+};
+
+static inline bool pickFpOpcode(const Vec& reg, uint32_t sOp, uint32_t sHf, uint32_t vOp, uint32_t vHf, Opcode* opcode, uint32_t* szOut) noexcept {
+ static constexpr uint32_t kQBitIndex = 30;
+
+ static const EncodeFpOpcodeBits szBits[InstDB::kHF_Count] = {
+ { B(2) | B(1) , { 0u , 0u, B(22) } },
+ { B(2) | B(1) | B(0), { 0u , 0u, 0u } },
+ { B(2) | B(1) | B(0), { B(23) | B(22) , 0u, B(22) } },
+ { B(2) | B(1) | B(0), { B(22) | B(20) | B(19) , 0u, B(22) } },
+ { B(2) | B(1) | B(0), { B(22) | B(21) | B(15) | B(14), 0u, B(22) } },
+ { B(2) | B(1) | B(0), { B(23) , 0u, B(22) } }
+ };
+
+ if (!reg.hasElementType()) {
+ // Scalar operation [HSD].
+ uint32_t sz = diff(reg.type(), RegType::kARM_VecH);
+ if (sz > 2u || !Support::bitTest(szBits[sHf].sizeMask, sz))
+ return false;
+
+ opcode->reset(szBits[sHf].mask[sz] ^ sOp);
+ *szOut = sz;
+ return sOp != 0;
+ }
+ else {
+ // Vector operation [HSD].
+ uint32_t q = diff(reg.type(), RegType::kARM_VecD);
+ uint32_t sz = reg.elementType() - Vec::kElementTypeH;
+
+ if (q > 1u || sz > 2u || !Support::bitTest(szBits[vHf].sizeMask, sz))
+ return false;
+
+ opcode->reset(szBits[vHf].mask[sz] ^ (vOp | (q << kQBitIndex)));
+ *szOut = sz;
+ return vOp != 0;
+ }
+}
+
+static inline bool pickFpOpcode(const Vec& reg, uint32_t sOp, uint32_t sHf, uint32_t vOp, uint32_t vHf, Opcode* opcode) noexcept {
+ uint32_t sz;
+ return pickFpOpcode(reg, sOp, sHf, vOp, vHf, opcode, &sz);
+}
+
+// a64::Assembler - Operand Checks
+// ===============================
+
+// Checks whether all operands have the same signature.
+static inline bool checkSignature(const Operand_& o0, const Operand_& o1) noexcept {
+ return o0.signature() == o1.signature();
+}
+
+static inline bool checkSignature(const Operand_& o0, const Operand_& o1, const Operand_& o2) noexcept {
+ return o0.signature() == o1.signature() &&
+ o1.signature() == o2.signature();
+}
+
+static inline bool checkSignature(const Operand_& o0, const Operand_& o1, const Operand_& o2, const Operand_& o3) noexcept {
+ return o0.signature() == o1.signature() &&
+ o1.signature() == o2.signature() &&
+ o2.signature() == o3.signature();
+}
+
+// Checks whether the register is GP register of the allowed types.
+//
+// Allowed is a 2-bit mask, where the first bits allows GpW and the second bit
+// allows GpX. These bits are usually stored within the instruction, but could
+// be also hardcoded in the assembler for instructions where GP types are not
+// selectable.
+static inline bool checkGpType(const Operand_& op, uint32_t allowed) noexcept {
+ RegType type = op.as<Reg>().type();
+ return Support::bitTest(allowed << uint32_t(RegType::kARM_GpW), type);
+}
+
+static inline bool checkGpType(const Operand_& op, uint32_t allowed, uint32_t* x) noexcept {
+ // NOTE: We set 'x' to one only when GpW is allowed, otherwise the X is part
+ // of the opcode and we cannot set it. This is why this works without requiring
+ // additional logic.
+ RegType type = op.as<Reg>().type();
+ *x = diff(type, RegType::kARM_GpW) & allowed;
+ return Support::bitTest(allowed << uint32_t(RegType::kARM_GpW), type);
+}
+
+static inline bool checkGpType(const Operand_& o0, const Operand_& o1, uint32_t allowed, uint32_t* x) noexcept {
+ return checkGpType(o0, allowed, x) && checkSignature(o0, o1);
+}
+
+static inline bool checkGpType(const Operand_& o0, const Operand_& o1, const Operand_& o2, uint32_t allowed, uint32_t* x) noexcept {
+ return checkGpType(o0, allowed, x) && checkSignature(o0, o1, o2);
+}
+
+static inline bool checkGpId(const Operand_& op, uint32_t hiId = kZR) noexcept {
+ uint32_t id = op.as<Reg>().id();
+ return id < 31u || id == hiId;
+}
+
+static inline bool checkGpId(const Operand_& o0, const Operand_& o1, uint32_t hiId = kZR) noexcept {
+ uint32_t id0 = o0.as<Reg>().id();
+ uint32_t id1 = o1.as<Reg>().id();
+
+ return (id0 < 31u || id0 == hiId) && (id1 < 31u || id1 == hiId);
+}
+
+static inline bool checkGpId(const Operand_& o0, const Operand_& o1, const Operand_& o2, uint32_t hiId = kZR) noexcept {
+ uint32_t id0 = o0.as<Reg>().id();
+ uint32_t id1 = o1.as<Reg>().id();
+ uint32_t id2 = o2.as<Reg>().id();
+
+ return (id0 < 31u || id0 == hiId) && (id1 < 31u || id1 == hiId) && (id2 < 31u || id2 == hiId);
+}
+
+static inline bool checkVecId(const Operand_& op) noexcept {
+ uint32_t id = op.as<Reg>().id();
+ return id <= 31u;
+}
+
+static inline bool checkVecId(const Operand_& o0, const Operand_& o1) noexcept {
+ uint32_t id0 = o0.as<Reg>().id();
+ uint32_t id1 = o1.as<Reg>().id();
+
+ return (id0 | id1) <= 31u;
+}
+
+/* Unused at the moment.
+static inline bool checkVecId(const Operand_& o0, const Operand_& o1, const Operand_& o2) noexcept {
+ uint32_t id0 = o0.as<Reg>().id();
+ uint32_t id1 = o1.as<Reg>().id();
+ uint32_t id2 = o2.as<Reg>().id();
+
+ return (id0 | id1 | id2) <= 31u;
+}
+
+static inline bool checkVecId(const Operand_& o0, const Operand_& o1, const Operand_& o2, const Operand_& o3) noexcept {
+ uint32_t id0 = o0.as<Reg>().id();
+ uint32_t id1 = o1.as<Reg>().id();
+ uint32_t id2 = o2.as<Reg>().id();
+ uint32_t id3 = o3.as<Reg>().id();
+
+ return (id0 | id1 | id2 | id3) <= 31u;
+}
+*/
+
+static inline bool checkMemBase(const Mem& mem) noexcept {
+ return mem.baseType() == RegType::kARM_GpX && mem.baseId() <= 31;
+}
+
+static inline bool checkEven(const Operand_& o0, const Operand_& o1) noexcept {
+ return ((o0.id() | o1.id()) & 1) == 0;
+}
+
+static inline bool checkConsecutive(const Operand_& o0, const Operand_& o1) noexcept {
+ return ((o0.id() + 1u) & 0x1Fu) == o1.id();
+}
+
+static inline bool checkConsecutive(const Operand_& o0, const Operand_& o1, const Operand_& o2) noexcept {
+ return ((o0.id() + 1u) & 0x1Fu) == o1.id() &&
+ ((o0.id() + 2u) & 0x1Fu) == o2.id();
+}
+
+static inline bool checkConsecutive(const Operand_& o0, const Operand_& o1, const Operand_& o2, const Operand_& o3) noexcept {
+ return ((o0.id() + 1u) & 0x1Fu) == o1.id() &&
+ ((o0.id() + 2u) & 0x1Fu) == o2.id() &&
+ ((o0.id() + 3u) & 0x1Fu) == o3.id();
+}
+
+// a64::Assembler - CheckReg
+// =========================
+
+#define V(index) (index == uint32_t(RegType::kARM_GpW) ? Gp::kIdZr : \
+ index == uint32_t(RegType::kARM_GpX) ? Gp::kIdZr : \
+ index == uint32_t(RegType::kARM_VecB) ? 31u : \
+ index == uint32_t(RegType::kARM_VecH) ? 31u : \
+ index == uint32_t(RegType::kARM_VecS) ? 31u : \
+ index == uint32_t(RegType::kARM_VecD) ? 31u : \
+ index == uint32_t(RegType::kARM_VecV) ? 31u : 0)
+static const Support::Array<uint8_t, 32> commonHiRegIdOfType = {{
+ ASMJIT_LOOKUP_TABLE_32(V, 0)
+}};
+#undef V
+
+static inline bool checkValidRegs(const Operand_& o0) noexcept {
+ return ((o0.id() < 31) | (o0.id() == commonHiRegIdOfType[o0.as<Reg>().type()]));
+}
+
+static inline bool checkValidRegs(const Operand_& o0, const Operand_& o1) noexcept {
+ return ((o0.id() < 31) | (o0.id() == commonHiRegIdOfType[o0.as<Reg>().type()])) &
+ ((o1.id() < 31) | (o1.id() == commonHiRegIdOfType[o1.as<Reg>().type()])) ;
+}
+
+static inline bool checkValidRegs(const Operand_& o0, const Operand_& o1, const Operand_& o2) noexcept {
+ return ((o0.id() < 31) | (o0.id() == commonHiRegIdOfType[o0.as<Reg>().type()])) &
+ ((o1.id() < 31) | (o1.id() == commonHiRegIdOfType[o1.as<Reg>().type()])) &
+ ((o2.id() < 31) | (o2.id() == commonHiRegIdOfType[o2.as<Reg>().type()])) ;
+}
+
+static inline bool checkValidRegs(const Operand_& o0, const Operand_& o1, const Operand_& o2, const Operand_& o3) noexcept {
+ return ((o0.id() < 31) | (o0.id() == commonHiRegIdOfType[o0.as<Reg>().type()])) &
+ ((o1.id() < 31) | (o1.id() == commonHiRegIdOfType[o1.as<Reg>().type()])) &
+ ((o2.id() < 31) | (o2.id() == commonHiRegIdOfType[o2.as<Reg>().type()])) &
+ ((o3.id() < 31) | (o3.id() == commonHiRegIdOfType[o3.as<Reg>().type()])) ;
+}
+
+// a64::Assembler - Construction & Destruction
+// ===========================================
+
+Assembler::Assembler(CodeHolder* code) noexcept : BaseAssembler() {
+ _archMask = uint64_t(1) << uint32_t(Arch::kAArch64);
+ assignEmitterFuncs(this);
+
+ if (code)
+ code->attach(this);
+}
+
+Assembler::~Assembler() noexcept {}
+
+// a64::Assembler - Emit
+// =====================
+
+#define ENC_OPS1(OP0) \
+ (uint32_t(OperandType::k##OP0))
+
+#define ENC_OPS2(OP0, OP1) \
+ (uint32_t(OperandType::k##OP0) + \
+ (uint32_t(OperandType::k##OP1) << 3))
+
+#define ENC_OPS3(OP0, OP1, OP2) \
+ (uint32_t(OperandType::k##OP0) + \
+ (uint32_t(OperandType::k##OP1) << 3) + \
+ (uint32_t(OperandType::k##OP2) << 6))
+
+#define ENC_OPS4(OP0, OP1, OP2, OP3) \
+ (uint32_t(OperandType::k##OP0) + \
+ (uint32_t(OperandType::k##OP1) << 3) + \
+ (uint32_t(OperandType::k##OP2) << 6) + \
+ (uint32_t(OperandType::k##OP3) << 9))
+
+Error Assembler::_emit(InstId instId, const Operand_& o0, const Operand_& o1, const Operand_& o2, const Operand_* opExt) {
+ // Logging/Validation/Error.
+ constexpr InstOptions kRequiresSpecialHandling = InstOptions::kReserved;
+
+ Error err;
+ CodeWriter writer(this);
+
+ // Combine all instruction options and also check whether the instruction
+ // is valid. All options that require special handling (including invalid
+ // instruction) are handled by the next branch.
+ InstOptions options = InstOptions(instId - 1 >= Inst::_kIdCount - 1) | InstOptions((size_t)(_bufferEnd - writer.cursor()) < 4) | instOptions() | forcedInstOptions();
+
+ CondCode instCC = BaseInst::extractARMCondCode(instId);
+ instId = instId & uint32_t(InstIdParts::kRealId);
+
+ if (instId >= Inst::_kIdCount)
+ instId = 0;
+
+ const InstDB::InstInfo* instInfo = &InstDB::_instInfoTable[instId];
+ uint32_t encodingIndex = instInfo->_encodingDataIndex;
+
+ Opcode opcode;
+ uint32_t isign4;
+ uint32_t instFlags;
+
+ const Operand_& o3 = opExt[EmitterUtils::kOp3];
+ const Operand_* rmRel = nullptr;
+
+ uint32_t multipleOpData[4];
+ uint32_t multipleOpCount;
+
+ // These are only used when instruction uses a relative displacement.
+ OffsetFormat offsetFormat; // Offset format.
+ uint64_t offsetValue; // Offset value (if known).
+
+ if (ASMJIT_UNLIKELY(Support::test(options, kRequiresSpecialHandling))) {
+ if (ASMJIT_UNLIKELY(!_code))
+ return reportError(DebugUtils::errored(kErrorNotInitialized));
+
+ // Unknown instruction.
+ if (ASMJIT_UNLIKELY(instId == 0))
+ goto InvalidInstruction;
+
+ // Condition code can only be used with 'B' instruction.
+ if (ASMJIT_UNLIKELY(instCC != CondCode::kAL && instId != Inst::kIdB))
+ goto InvalidInstruction;
+
+ // Grow request, happens rarely.
+ err = writer.ensureSpace(this, 4);
+ if (ASMJIT_UNLIKELY(err))
+ goto Failed;
+
+#ifndef ASMJIT_NO_VALIDATION
+ // Strict validation.
+ if (hasDiagnosticOption(DiagnosticOptions::kValidateAssembler)) {
+ Operand_ opArray[Globals::kMaxOpCount];
+ EmitterUtils::opArrayFromEmitArgs(opArray, o0, o1, o2, opExt);
+
+ err = _funcs.validate(arch(), BaseInst(instId, options, _extraReg), opArray, Globals::kMaxOpCount, ValidationFlags::kNone);
+ if (ASMJIT_UNLIKELY(err))
+ goto Failed;
+ }
+#endif
+ }
+
+ // Signature of the first 4 operands.
+ isign4 = (uint32_t(o0.opType()) ) +
+ (uint32_t(o1.opType()) << 3) +
+ (uint32_t(o2.opType()) << 6) +
+ (uint32_t(o3.opType()) << 9);
+ instFlags = instInfo->flags();
+
+ switch (instInfo->_encoding) {
+ // ------------------------------------------------------------------------
+ // [Base - Universal]
+ // ------------------------------------------------------------------------
+
+ case InstDB::kEncodingBaseOp: {
+ const InstDB::EncodingData::BaseOp& opData = InstDB::EncodingData::baseOp[encodingIndex];
+
+ if (isign4 == 0) {
+ opcode.reset(opData.opcode);
+ goto EmitOp;
+ }
+
+ break;
+ }
+
+ case InstDB::kEncodingBaseOpImm: {
+ const InstDB::EncodingData::BaseOpImm& opData = InstDB::EncodingData::baseOpImm[encodingIndex];
+
+ if (isign4 == ENC_OPS1(Imm)) {
+ uint64_t imm = o0.as<Imm>().valueAs<uint64_t>();
+ uint32_t immMax = 1u << opData.immBits;
+
+ if (imm >= immMax)
+ goto InvalidImmediate;
+
+ opcode.reset(opData.opcode);
+ opcode.addImm(imm, opData.immOffset);
+ goto EmitOp;
+ }
+
+ break;
+ }
+
+ case InstDB::kEncodingBaseR: {
+ const InstDB::EncodingData::BaseR& opData = InstDB::EncodingData::baseR[encodingIndex];
+
+ if (isign4 == ENC_OPS1(Reg)) {
+ if (!checkGpType(o0, opData.rType))
+ goto InvalidInstruction;
+
+ if (!checkGpId(o0, opData.rHiId))
+ goto InvalidPhysId;
+
+ opcode.reset(opData.opcode);
+ opcode.addReg(o0, opData.rShift);
+ goto EmitOp;
+ }
+
+ break;
+ }
+
+ case InstDB::kEncodingBaseRR: {
+ const InstDB::EncodingData::BaseRR& opData = InstDB::EncodingData::baseRR[encodingIndex];
+
+ if (isign4 == ENC_OPS2(Reg, Reg)) {
+ uint32_t x;
+ if (!checkGpType(o0, opData.aType, &x))
+ goto InvalidInstruction;
+
+ if (!checkGpType(o1, opData.bType))
+ goto InvalidInstruction;
+
+ if (opData.uniform && !checkSignature(o0, o1))
+ goto InvalidInstruction;
+
+ if (!checkGpId(o0, opData.aHiId))
+ goto InvalidPhysId;
+
+ if (!checkGpId(o1, opData.bHiId))
+ goto InvalidPhysId;
+
+ opcode.reset(opData.opcode);
+ opcode.addImm(x, 31);
+ opcode.addReg(o1, opData.bShift);
+ opcode.addReg(o0, opData.aShift);
+ goto EmitOp;
+ }
+
+ break;
+ }
+
+ case InstDB::kEncodingBaseRRR: {
+ const InstDB::EncodingData::BaseRRR& opData = InstDB::EncodingData::baseRRR[encodingIndex];
+
+ if (isign4 == ENC_OPS3(Reg, Reg, Reg)) {
+ uint32_t x;
+ if (!checkGpType(o0, opData.aType, &x))
+ goto InvalidInstruction;
+
+ if (!checkGpType(o1, opData.bType))
+ goto InvalidInstruction;
+
+ if (!checkGpType(o2, opData.cType))
+ goto InvalidInstruction;
+
+ if (opData.uniform && !checkSignature(o0, o1, o2))
+ goto InvalidInstruction;
+
+ if (!checkGpId(o0, opData.aHiId))
+ goto InvalidPhysId;
+
+ if (!checkGpId(o1, opData.bHiId))
+ goto InvalidPhysId;
+
+ if (!checkGpId(o2, opData.cHiId))
+ goto InvalidPhysId;
+
+ opcode.reset(opData.opcode());
+ opcode.addImm(x, 31);
+ opcode.addReg(o2, 16);
+ opcode.addReg(o1, 5);
+ opcode.addReg(o0, 0);
+ goto EmitOp;
+ }
+
+ break;
+ }
+
+ case InstDB::kEncodingBaseRRRR: {
+ const InstDB::EncodingData::BaseRRRR& opData = InstDB::EncodingData::baseRRRR[encodingIndex];
+
+ if (isign4 == ENC_OPS4(Reg, Reg, Reg, Reg)) {
+ uint32_t x;
+ if (!checkGpType(o0, opData.aType, &x))
+ goto InvalidInstruction;
+
+ if (!checkGpType(o1, opData.bType))
+ goto InvalidInstruction;
+
+ if (!checkGpType(o2, opData.cType))
+ goto InvalidInstruction;
+
+ if (!checkGpType(o3, opData.dType))
+ goto InvalidInstruction;
+
+ if (opData.uniform && !checkSignature(o0, o1, o2, o3))
+ goto InvalidInstruction;
+
+ if (!checkGpId(o0, opData.aHiId))
+ goto InvalidPhysId;
+
+ if (!checkGpId(o1, opData.bHiId))
+ goto InvalidPhysId;
+
+ if (!checkGpId(o2, opData.cHiId))
+ goto InvalidPhysId;
+
+ if (!checkGpId(o3, opData.dHiId))
+ goto InvalidPhysId;
+
+ opcode.reset(opData.opcode());
+ opcode.addImm(x, 31);
+ opcode.addReg(o2, 16);
+ opcode.addReg(o3, 10);
+ opcode.addReg(o1, 5);
+ opcode.addReg(o0, 0);
+ goto EmitOp;
+ }
+
+ break;
+ }
+
+ case InstDB::kEncodingBaseRRII: {
+ const InstDB::EncodingData::BaseRRII& opData = InstDB::EncodingData::baseRRII[encodingIndex];
+
+ if (isign4 == ENC_OPS4(Reg, Reg, Imm, Imm)) {
+ if (!checkGpType(o0, opData.aType))
+ goto InvalidInstruction;
+
+ if (!checkGpType(o1, opData.bType))
+ goto InvalidInstruction;
+
+ if (!checkGpId(o0, opData.aHiId))
+ goto InvalidPhysId;
+
+ if (!checkGpId(o1, opData.bHiId))
+ goto InvalidPhysId;
+
+ if (o2.as<Imm>().valueAs<uint64_t>() >= Support::bitMask(opData.aImmSize + opData.aImmDiscardLsb) ||
+ o3.as<Imm>().valueAs<uint64_t>() >= Support::bitMask(opData.bImmSize + opData.bImmDiscardLsb))
+ goto InvalidImmediate;
+
+ uint32_t aImm = o2.as<Imm>().valueAs<uint32_t>() >> opData.aImmDiscardLsb;
+ uint32_t bImm = o3.as<Imm>().valueAs<uint32_t>() >> opData.bImmDiscardLsb;
+
+ if ((aImm << opData.aImmDiscardLsb) != o2.as<Imm>().valueAs<uint32_t>() ||
+ (bImm << opData.bImmDiscardLsb) != o3.as<Imm>().valueAs<uint32_t>())
+ goto InvalidImmediate;
+
+ opcode.reset(opData.opcode());
+ opcode.addImm(aImm, opData.aImmOffset);
+ opcode.addImm(bImm, opData.bImmOffset);
+ opcode.addReg(o1, 5);
+ opcode.addReg(o0, 0);
+ goto EmitOp;
+ }
+
+ break;
+ }
+
+ // ------------------------------------------------------------------------
+ // [Base - Mov]
+ // ------------------------------------------------------------------------
+
+ case InstDB::kEncodingBaseMov: {
+ // MOV is a pseudo instruction that uses various instructions depending on its signature.
+ uint32_t x = diff(o0.as<Reg>().type(), RegType::kARM_GpW);
+ if (x > 1)
+ goto InvalidInstruction;
+
+ if (isign4 == ENC_OPS2(Reg, Reg)) {
+ if (!o0.as<Reg>().isGp())
+ goto InvalidInstruction;
+
+ if (!checkSignature(o0, o1))
+ goto InvalidInstruction;
+
+ bool hasSP = o0.as<Gp>().isSP() || o1.as<Gp>().isSP();
+ if (hasSP) {
+ // Cannot be combined with ZR.
+ if (!checkGpId(o0, o1, kSP))
+ goto InvalidPhysId;
+
+ // MOV Rd, Rm -> ADD Rd, Rn, #0.
+ opcode.reset(0b00010001000000000000000000000000);
+ opcode.addImm(x, 31);
+ opcode.addReg(o1, 5);
+ opcode.addReg(o0, 0);
+ goto EmitOp;
+ }
+ else {
+ if (!checkGpId(o0, o1, kZR))
+ goto InvalidPhysId;
+
+ // MOV Rd, Rm -> ORR Rd, <ZR>, Rm.
+ opcode.reset(0b00101010000000000000001111100000);
+ opcode.addImm(x, 31);
+ opcode.addReg(o1, 16);
+ opcode.addReg(o0, 0);
+ goto EmitOp;
+ }
+ }
+
+ if (isign4 == ENC_OPS2(Reg, Imm)) {
+ if (!o0.as<Reg>().isGp())
+ goto InvalidInstruction;
+
+ uint64_t immValue = o1.as<Imm>().valueAs<uint64_t>();
+ if (!x)
+ immValue &= 0xFFFFFFFFu;
+
+ // Prefer a single MOVN/MOVZ instruction over a logical instruction.
+ multipleOpCount = encodeMovSequence64(multipleOpData, immValue, o0.id() & 31, x);
+ if (multipleOpCount == 1 && !o0.as<Gp>().isSP()) {
+ opcode.reset(multipleOpData[0]);
+ goto EmitOp;
+ }
+
+ // Logical instructions use 13-bit immediate pattern encoded as N:ImmR:ImmS.
+ LogicalImm logicalImm;
+ if (!o0.as<Gp>().isZR()) {
+ if (Utils::encodeLogicalImm(immValue, x ? 64 : 32, &logicalImm)) {
+ if (!checkGpId(o0, kSP))
+ goto InvalidPhysId;
+
+ opcode.reset(0b00110010000000000000001111100000);
+ opcode.addImm(x, 31);
+ opcode.addLogicalImm(logicalImm);
+ opcode.addReg(o0, 0);
+ goto EmitOp;
+ }
+ }
+
+ if (!checkGpId(o0, kZR))
+ goto InvalidPhysId;
+
+ goto EmitOp_Multiple;
+ }
+
+ break;
+ }
+
+ case InstDB::kEncodingBaseMovKNZ: {
+ const InstDB::EncodingData::BaseMovKNZ& opData = InstDB::EncodingData::baseMovKNZ[encodingIndex];
+
+ uint32_t x = diff(o0.as<Reg>().type(), RegType::kARM_GpW);
+ if (x > 1)
+ goto InvalidInstruction;
+
+ if (!checkGpId(o0, kZR))
+ goto InvalidPhysId;
+
+ opcode.reset(opData.opcode);
+ opcode.addImm(x, 31);
+
+ if (isign4 == ENC_OPS2(Reg, Imm)) {
+ uint64_t imm16 = o1.as<Imm>().valueAs<uint64_t>();
+ if (imm16 > 0xFFFFu)
+ goto InvalidImmediate;
+
+ opcode.addImm(imm16, 5);
+ opcode.addReg(o0, 0);
+ goto EmitOp;
+ }
+
+ if (isign4 == ENC_OPS3(Reg, Imm, Imm)) {
+ uint64_t imm16 = o1.as<Imm>().valueAs<uint64_t>();
+ uint32_t shiftType = o2.as<Imm>().predicate();
+ uint64_t shiftValue = o2.as<Imm>().valueAs<uint64_t>();
+
+ if (imm16 > 0xFFFFu || shiftValue > 48 || shiftType != uint32_t(ShiftOp::kLSL))
+ goto InvalidImmediate;
+
+ // Convert shift value to 'hw' field.
+ uint32_t hw = uint32_t(shiftValue) >> 4;
+ if ((hw << 4) != uint32_t(shiftValue))
+ goto InvalidImmediate;
+
+ opcode.addImm(hw, 21);
+ opcode.addImm(imm16, 5);
+ opcode.addReg(o0, 0);
+
+ if (!x && hw > 1u)
+ goto InvalidImmediate;
+
+ goto EmitOp;
+ }
+
+ break;
+ }
+
+ // ------------------------------------------------------------------------
+ // [Base - Adr]
+ // ------------------------------------------------------------------------
+
+ case InstDB::kEncodingBaseAdr: {
+ const InstDB::EncodingData::BaseAdr& opData = InstDB::EncodingData::baseAdr[encodingIndex];
+
+ if (isign4 == ENC_OPS2(Reg, Label) || isign4 == ENC_OPS2(Reg, Imm)) {
+ if (!o0.as<Reg>().isGpX())
+ goto InvalidInstruction;
+
+ if (!checkGpId(o0, kZR))
+ goto InvalidPhysId;
+
+ opcode.reset(opData.opcode());
+ opcode.addReg(o0, 0);
+ offsetFormat.resetToImmValue(opData.offsetType, 4, 5, 21, 0);
+
+ if (instId == Inst::kIdAdrp)
+ offsetFormat._immDiscardLsb = 12;
+
+ rmRel = &o1;
+ goto EmitOp_Rel;
+ }
+
+ break;
+ }
+
+ // ------------------------------------------------------------------------
+ // [Base - Arithmetic and Logical]
+ // ------------------------------------------------------------------------
+
+ case InstDB::kEncodingBaseAddSub: {
+ const InstDB::EncodingData::BaseAddSub& opData = InstDB::EncodingData::baseAddSub[encodingIndex];
+
+ uint32_t x;
+ if (!checkGpType(o0, o1, kWX, &x))
+ goto InvalidInstruction;
+
+ if (isign4 == ENC_OPS3(Reg, Reg, Imm) || isign4 == ENC_OPS4(Reg, Reg, Imm, Imm)) {
+ opcode.reset(uint32_t(opData.immediateOp) << 24);
+
+ // ADD | SUB (immediate) - ZR is not allowed.
+ // ADDS|SUBS (immediate) - ZR allowed in Rd, SP allowed in Rn.
+ uint32_t aHiId = opcode.get() & B(29) ? kZR : kSP;
+ uint32_t bHiId = kSP;
+
+ if (!checkGpId(o0, aHiId) || !checkGpId(o1, bHiId))
+ goto InvalidPhysId;
+
+ // ADD|SUB (immediate) use 12-bit immediate optionally shifted by 'LSL #12'.
+ uint64_t imm = o2.as<Imm>().valueAs<uint64_t>();
+ uint32_t shift = 0;
+
+ if (isign4 == ENC_OPS4(Reg, Reg, Imm, Imm)) {
+ if (o3.as<Imm>().predicate() != uint32_t(ShiftOp::kLSL))
+ goto InvalidImmediate;
+
+ if (o3.as<Imm>().value() != 0 && o3.as<Imm>().value() != 12)
+ goto InvalidImmediate;
+
+ shift = uint32_t(o3.as<Imm>().value() != 0);
+ }
+
+ // Accept immediate value of '0x00XXX000' by setting 'shift' to 12.
+ if (imm > 0xFFFu) {
+ if (shift || (imm & ~uint64_t(0xFFFu << 12)) != 0)
+ goto InvalidImmediate;
+ shift = 1;
+ imm >>= 12;
+ }
+
+ opcode.addImm(x, 31);
+ opcode.addImm(shift, 22);
+ opcode.addImm(imm, 10);
+ opcode.addReg(o1, 5);
+ opcode.addReg(o0, 0);
+ goto EmitOp;
+ }
+
+ if (isign4 == ENC_OPS3(Reg, Reg, Reg) || isign4 == ENC_OPS4(Reg, Reg, Reg, Imm)) {
+ if (!checkSignature(o1, o2))
+ goto InvalidInstruction;
+
+ uint32_t opSize = x ? 64 : 32;
+ uint64_t shift = 0;
+ uint32_t sType = uint32_t(ShiftOp::kLSL);
+
+ if (isign4 == ENC_OPS4(Reg, Reg, Reg, Imm)) {
+ sType = o3.as<Imm>().predicate();
+ shift = o3.as<Imm>().valueAs<uint64_t>();
+ }
+
+ if (!checkGpId(o2, kZR))
+ goto InvalidPhysId;
+
+ // Shift operation - LSL, LSR, ASR.
+ if (sType <= uint32_t(ShiftOp::kASR)) {
+ bool hasSP = o0.as<Gp>().isSP() || o1.as<Gp>().isSP();
+ if (!hasSP) {
+ if (!checkGpId(o0, o1, kZR))
+ goto InvalidPhysId;
+
+ if (shift >= opSize)
+ goto InvalidImmediate;
+
+ opcode.reset(uint32_t(opData.shiftedOp) << 21);
+ opcode.addImm(x, 31);
+ opcode.addImm(sType, 22);
+ opcode.addReg(o2, 16);
+ opcode.addImm(shift, 10);
+ opcode.addReg(o1, 5);
+ opcode.addReg(o0, 0);
+ goto EmitOp;
+ }
+
+ // SP register can only be used with LSL or Extend.
+ if (sType != uint32_t(ShiftOp::kLSL))
+ goto InvalidImmediate;
+ sType = x ? uint32_t(ShiftOp::kUXTX) : uint32_t(ShiftOp::kUXTW);
+ }
+
+ // Extend operation - UXTB, UXTH, UXTW, UXTX, SXTB, SXTH, SXTW, SXTX.
+ opcode.reset(uint32_t(opData.extendedOp) << 21);
+ sType -= uint32_t(ShiftOp::kUXTB);
+
+ if (sType > 7 || shift > 4)
+ goto InvalidImmediate;
+
+ if (!(opcode.get() & B(29))) {
+ // ADD|SUB (extend) - ZR is not allowed.
+ if (!checkGpId(o0, o1, kSP))
+ goto InvalidPhysId;
+ }
+ else {
+ // ADDS|SUBS (extend) - ZR allowed in Rd, SP allowed in Rn.
+ if (!checkGpId(o0, kZR) || !checkGpId(o1, kSP))
+ goto InvalidPhysId;
+ }
+
+ opcode.addImm(x, 31);
+ opcode.addReg(o2, 16);
+ opcode.addImm(sType, 13);
+ opcode.addImm(shift, 10);
+ opcode.addReg(o1, 5);
+ opcode.addReg(o0, 0);
+ goto EmitOp;
+ }
+
+ break;
+ }
+
+ case InstDB::kEncodingBaseLogical: {
+ const InstDB::EncodingData::BaseLogical& opData = InstDB::EncodingData::baseLogical[encodingIndex];
+
+ uint32_t x;
+ if (!checkGpType(o0, o1, kWX, &x))
+ goto InvalidInstruction;
+
+ if (!checkSignature(o0, o1))
+ goto InvalidInstruction;
+
+ uint32_t opSize = x ? 64 : 32;
+
+ if (isign4 == ENC_OPS3(Reg, Reg, Imm) && opData.immediateOp != 0) {
+ opcode.reset(uint32_t(opData.immediateOp) << 23);
+
+ // AND|ANDS|BIC|BICS|ORR|EOR (immediate) uses a LogicalImm format described by N:R:S values.
+ uint64_t immMask = Support::lsbMask<uint64_t>(opSize);
+ uint64_t immValue = o2.as<Imm>().valueAs<uint64_t>();
+
+ if (opData.negateImm)
+ immValue ^= immMask;
+
+ // Logical instructions use 13-bit immediate pattern encoded as N:ImmS:ImmR.
+ LogicalImm logicalImm;
+ if (!Utils::encodeLogicalImm(immValue & immMask, opSize, &logicalImm))
+ goto InvalidImmediate;
+
+ // AND|BIC|ORR|EOR (immediate) can have SP on destination, but ANDS|BICS (immediate) cannot.
+ uint32_t kOpANDS = 0x3 << 29;
+ bool isANDS = (opcode.get() & kOpANDS) == kOpANDS;
+
+ if (!checkGpId(o0, isANDS ? kZR : kSP) || !checkGpId(o1, kZR))
+ goto InvalidPhysId;
+
+ opcode.addImm(x, 31);
+ opcode.addLogicalImm(logicalImm);
+ opcode.addReg(o1, 5);
+ opcode.addReg(o0, 0);
+ goto EmitOp;
+ }
+
+ if (!checkSignature(o1, o2))
+ goto InvalidInstruction;
+
+ if (isign4 == ENC_OPS3(Reg, Reg, Reg)) {
+ if (!checkGpId(o0, o1, o2, kZR))
+ goto InvalidPhysId;
+
+ opcode.reset(uint32_t(opData.shiftedOp) << 21);
+ opcode.addImm(x, 31);
+ opcode.addReg(o2, 16);
+ opcode.addReg(o1, 5);
+ opcode.addReg(o0, 0);
+ goto EmitOp;
+ }
+
+ if (isign4 == ENC_OPS4(Reg, Reg, Reg, Imm)) {
+ if (!checkGpId(o0, o1, o2, kZR))
+ goto InvalidPhysId;
+
+ uint32_t shiftType = o3.as<Imm>().predicate();
+ uint64_t opShift = o3.as<Imm>().valueAs<uint64_t>();
+
+ if (shiftType > 0x3 || opShift >= opSize)
+ goto InvalidImmediate;
+
+ opcode.reset(uint32_t(opData.shiftedOp) << 21);
+ opcode.addImm(x, 31);
+ opcode.addImm(shiftType, 22);
+ opcode.addReg(o2, 16);
+ opcode.addImm(opShift, 10);
+ opcode.addReg(o1, 5);
+ opcode.addReg(o0, 0);
+ goto EmitOp;
+ }
+
+ break;
+ }
+
+ case InstDB::kEncodingBaseCmpCmn: {
+ const InstDB::EncodingData::BaseCmpCmn& opData = InstDB::EncodingData::baseCmpCmn[encodingIndex];
+
+ uint32_t x;
+ if (!checkGpType(o0, kWX, &x))
+ goto InvalidInstruction;
+
+ if (isign4 == ENC_OPS2(Reg, Imm)) {
+ // CMN|CMP (immediate) - ZR is not allowed.
+ if (!checkGpId(o0, kSP))
+ goto InvalidPhysId;
+
+ // CMN|CMP (immediate) use 12-bit immediate optionally shifted by 'LSL #12'.
+ const Imm& imm12 = o1.as<Imm>();
+ uint32_t immShift = 0;
+ uint64_t immValue = imm12.valueAs<uint64_t>();
+
+ if (immValue > 0xFFFu) {
+ if ((immValue & ~uint64_t(0xFFFu << 12)) != 0)
+ goto InvalidImmediate;
+ immShift = 1;
+ immValue >>= 12;
+ }
+
+ opcode.reset(uint32_t(opData.immediateOp) << 24);
+ opcode.addImm(x, 31);
+ opcode.addImm(immShift, 22);
+ opcode.addImm(immValue, 10);
+ opcode.addReg(o0, 5);
+ opcode.addReg(Gp::kIdZr, 0);
+ goto EmitOp;
+ }
+
+ if (isign4 == ENC_OPS2(Reg, Reg) || isign4 == ENC_OPS3(Reg, Reg, Imm)) {
+ if (!checkSignature(o0, o1))
+ goto InvalidInstruction;
+
+ uint32_t opSize = x ? 64 : 32;
+ uint32_t sType = 0;
+ uint64_t shift = 0;
+
+ if (isign4 == ENC_OPS3(Reg, Reg, Imm)) {
+ sType = o2.as<Imm>().predicate();
+ shift = o2.as<Imm>().valueAs<uint64_t>();
+ }
+
+ bool hasSP = o0.as<Gp>().isSP() || o1.as<Gp>().isSP();
+
+ // Shift operation - LSL, LSR, ASR.
+ if (sType <= uint32_t(ShiftOp::kASR)) {
+ if (!hasSP) {
+ if (shift >= opSize)
+ goto InvalidImmediate;
+
+ opcode.reset(uint32_t(opData.shiftedOp) << 21);
+ opcode.addImm(x, 31);
+ opcode.addImm(sType, 22);
+ opcode.addReg(o1, 16);
+ opcode.addImm(shift, 10);
+ opcode.addReg(o0, 5);
+ opcode.addReg(Gp::kIdZr, 0);
+ goto EmitOp;
+ }
+
+ // SP register can only be used with LSL or Extend.
+ if (sType != uint32_t(ShiftOp::kLSL))
+ goto InvalidImmediate;
+
+ sType = x ? uint32_t(ShiftOp::kUXTX) : uint32_t(ShiftOp::kUXTW);
+ }
+
+ // Extend operation - UXTB, UXTH, UXTW, UXTX, SXTB, SXTH, SXTW, SXTX.
+ sType -= uint32_t(ShiftOp::kUXTB);
+ if (sType > 7 || shift > 4)
+ goto InvalidImmediate;
+
+ opcode.reset(uint32_t(opData.extendedOp) << 21);
+ opcode.addImm(x, 31);
+ opcode.addReg(o1, 16);
+ opcode.addImm(sType, 13);
+ opcode.addImm(shift, 10);
+ opcode.addReg(o0, 5);
+ opcode.addReg(Gp::kIdZr, 0);
+ goto EmitOp;
+ }
+
+ break;
+ }
+
+ case InstDB::kEncodingBaseMvnNeg: {
+ const InstDB::EncodingData::BaseMvnNeg& opData = InstDB::EncodingData::baseMvnNeg[encodingIndex];
+
+ uint32_t x;
+ if (!checkGpType(o0, o1, kWX, &x))
+ goto InvalidInstruction;
+
+ opcode.reset(opData.opcode);
+ opcode.addImm(x, 31);
+ opcode.addReg(o1, 16);
+ opcode.addReg(o0, 0);
+
+ if (isign4 == ENC_OPS2(Reg, Reg)) {
+ if (!checkGpId(o0, o1, kZR))
+ goto InvalidPhysId;
+
+ goto EmitOp;
+ }
+
+ if (isign4 == ENC_OPS3(Reg, Reg, Imm)) {
+ if (!checkGpId(o0, o1, kZR))
+ goto InvalidPhysId;
+
+ uint32_t opSize = x ? 64 : 32;
+ uint32_t shiftType = o2.as<Imm>().predicate();
+ uint64_t opShift = o2.as<Imm>().valueAs<uint64_t>();
+
+ if (shiftType > uint32_t(ShiftOp::kROR) || opShift >= opSize)
+ goto InvalidImmediate;
+
+ opcode.addImm(shiftType, 22);
+ opcode.addImm(opShift, 10);
+ goto EmitOp;
+ }
+
+ break;
+ }
+
+ case InstDB::kEncodingBaseTst: {
+ const InstDB::EncodingData::BaseTst& opData = InstDB::EncodingData::baseTst[encodingIndex];
+
+ uint32_t x;
+ if (!checkGpType(o0, kWX, &x))
+ goto InvalidInstruction;
+
+ uint32_t opSize = x ? 64 : 32;
+
+ if (isign4 == ENC_OPS2(Reg, Imm) && opData.immediateOp != 0) {
+ if (!checkGpId(o0, kZR))
+ goto InvalidPhysId;
+
+ // TST (immediate) uses a LogicalImm format described by N:R:S values.
+ uint64_t immMask = Support::lsbMask<uint64_t>(opSize);
+ uint64_t immValue = o1.as<Imm>().valueAs<uint64_t>();
+
+ // Logical instructions use 13-bit immediate pattern encoded as N:ImmS:ImmR.
+ LogicalImm logicalImm;
+ if (!Utils::encodeLogicalImm(immValue & immMask, opSize, &logicalImm))
+ goto InvalidImmediate;
+
+ opcode.reset(uint32_t(opData.immediateOp) << 22);
+ opcode.addLogicalImm(logicalImm);
+ opcode.addImm(x, 31);
+ opcode.addReg(o0, 5);
+ opcode.addReg(Gp::kIdZr, 0);
+ goto EmitOp;
+ }
+
+ opcode.reset(uint32_t(opData.shiftedOp) << 21);
+ opcode.addImm(x, 31);
+ opcode.addReg(o1, 16);
+ opcode.addReg(o0, 5);
+ opcode.addReg(Gp::kIdZr, 0);
+
+ if (isign4 == ENC_OPS2(Reg, Reg)) {
+ if (!checkGpId(o0, o1, kZR))
+ goto InvalidPhysId;
+
+ goto EmitOp;
+ }
+
+ if (isign4 == ENC_OPS3(Reg, Reg, Imm)) {
+ if (!checkGpId(o0, o1, kZR))
+ goto InvalidPhysId;
+
+ uint32_t shiftType = o2.as<Imm>().predicate();
+ uint64_t opShift = o2.as<Imm>().valueAs<uint64_t>();
+
+ if (shiftType > 0x3 || opShift >= opSize)
+ goto InvalidImmediate;
+
+ opcode.addImm(shiftType, 22);
+ opcode.addImm(opShift, 10);
+ goto EmitOp;
+ }
+
+ break;
+ }
+
+ // ------------------------------------------------------------------------
+ // [Base - Bit Manipulation]
+ // ------------------------------------------------------------------------
+
+ case InstDB::kEncodingBaseBfc: {
+ const InstDB::EncodingData::BaseBfc& opData = InstDB::EncodingData::baseBfc[encodingIndex];
+
+ if (isign4 == ENC_OPS3(Reg, Imm, Imm)) {
+ uint32_t x;
+ if (!checkGpType(o0, InstDB::kWX, &x))
+ goto InvalidInstruction;
+
+ if (!checkGpId(o0))
+ goto InvalidPhysId;
+
+ uint64_t lsb = o1.as<Imm>().valueAs<uint64_t>();
+ uint64_t width = o2.as<Imm>().valueAs<uint64_t>();
+ uint32_t opSize = x ? 64 : 32;
+
+ if (lsb >= opSize || width == 0 || width > opSize)
+ goto InvalidImmediate;
+
+ uint32_t lsb32 = Support::neg(uint32_t(lsb)) & (opSize - 1);
+ uint32_t width32 = uint32_t(width) - 1;
+
+ opcode.reset(opData.opcode);
+ opcode.addImm(x, 31);
+ opcode.addImm(x, 22);
+ opcode.addImm(lsb32, 16);
+ opcode.addImm(width32, 10);
+ opcode.addReg(o0, 0);
+ goto EmitOp;
+ }
+
+ break;
+ }
+
+ case InstDB::kEncodingBaseBfi: {
+ const InstDB::EncodingData::BaseBfi& opData = InstDB::EncodingData::baseBfi[encodingIndex];
+
+ if (isign4 == ENC_OPS4(Reg, Reg, Imm, Imm)) {
+ uint32_t x;
+ if (!checkGpType(o0, InstDB::kWX, &x))
+ goto InvalidInstruction;
+
+ if (!checkSignature(o0, o1))
+ goto InvalidInstruction;
+
+ if (!checkGpId(o0, o1))
+ goto InvalidPhysId;
+
+ uint64_t lsb = o2.as<Imm>().valueAs<uint64_t>();
+ uint64_t width = o3.as<Imm>().valueAs<uint64_t>();
+ uint32_t opSize = x ? 64 : 32;
+
+ if (lsb >= opSize || width == 0 || width > opSize)
+ goto InvalidImmediate;
+
+ uint32_t lImm = Support::neg(uint32_t(lsb)) & (opSize - 1);
+ uint32_t wImm = uint32_t(width) - 1;
+
+ opcode.reset(opData.opcode);
+ opcode.addImm(x, 31);
+ opcode.addImm(x, 22);
+ opcode.addImm(lImm, 16);
+ opcode.addImm(wImm, 10);
+ opcode.addReg(o1, 5);
+ opcode.addReg(o0, 0);
+ goto EmitOp;
+ }
+
+ break;
+ }
+
+ case InstDB::kEncodingBaseBfm: {
+ const InstDB::EncodingData::BaseBfm& opData = InstDB::EncodingData::baseBfm[encodingIndex];
+
+ if (isign4 == ENC_OPS4(Reg, Reg, Imm, Imm)) {
+ uint32_t x;
+ if (!checkGpType(o0, InstDB::kWX, &x))
+ goto InvalidInstruction;
+
+ if (!checkSignature(o0, o1))
+ goto InvalidInstruction;
+
+ if (!checkGpId(o0, o1))
+ goto InvalidPhysId;
+
+ uint64_t immR = o2.as<Imm>().valueAs<uint64_t>();
+ uint64_t immS = o3.as<Imm>().valueAs<uint64_t>();
+ uint32_t opSize = x ? 64 : 32;
+
+ if ((immR | immS) >= opSize)
+ goto InvalidImmediate;
+
+ opcode.reset(opData.opcode);
+ opcode.addImm(x, 31);
+ opcode.addImm(x, 22);
+ opcode.addImm(immR, 16);
+ opcode.addImm(immS, 10);
+ opcode.addReg(o1, 5);
+ opcode.addReg(o0, 0);
+ goto EmitOp;
+ }
+
+ break;
+ }
+
+ case InstDB::kEncodingBaseBfx: {
+ const InstDB::EncodingData::BaseBfx& opData = InstDB::EncodingData::baseBfx[encodingIndex];
+
+ if (isign4 == ENC_OPS4(Reg, Reg, Imm, Imm)) {
+ uint32_t x;
+ if (!checkGpType(o0, InstDB::kWX, &x))
+ goto InvalidInstruction;
+
+ if (!checkSignature(o0, o1))
+ goto InvalidInstruction;
+
+ if (!checkGpId(o0, o1))
+ goto InvalidPhysId;
+
+ uint64_t lsb = o2.as<Imm>().valueAs<uint64_t>();
+ uint64_t width = o3.as<Imm>().valueAs<uint64_t>();
+ uint32_t opSize = x ? 64 : 32;
+
+ if (lsb >= opSize || width == 0 || width > opSize)
+ goto InvalidImmediate;
+
+ uint32_t lsb32 = uint32_t(lsb);
+ uint32_t width32 = lsb32 + uint32_t(width) - 1u;
+
+ if (width32 >= opSize)
+ goto InvalidImmediate;
+
+ opcode.reset(opData.opcode);
+ opcode.addImm(x, 31);
+ opcode.addImm(x, 22);
+ opcode.addImm(lsb32, 16);
+ opcode.addImm(width32, 10);
+ opcode.addReg(o1, 5);
+ opcode.addReg(o0, 0);
+ goto EmitOp;
+ }
+
+ break;
+ }
+
+ case InstDB::kEncodingBaseExtend: {
+ const InstDB::EncodingData::BaseExtend& opData = InstDB::EncodingData::baseExtend[encodingIndex];
+
+ if (isign4 == ENC_OPS2(Reg, Reg)) {
+ uint32_t x;
+ if (!checkGpType(o0, opData.rType, &x))
+ goto InvalidInstruction;
+
+ if (!o1.as<Reg>().isGpW())
+ goto InvalidInstruction;
+
+ if (!checkGpId(o0, o1))
+ goto InvalidPhysId;
+
+ opcode.reset(opData.opcode());
+ opcode.addImm(x, 31);
+ opcode.addImm(x, 22);
+ opcode.addReg(o1, 5);
+ opcode.addReg(o0, 0);
+ goto EmitOp;
+ }
+
+ break;
+ }
+
+ case InstDB::kEncodingBaseExtract: {
+ const InstDB::EncodingData::BaseExtract& opData = InstDB::EncodingData::baseExtract[encodingIndex];
+
+ if (isign4 == ENC_OPS4(Reg, Reg, Reg, Imm)) {
+ uint32_t x;
+ if (!checkGpType(o0, kWX, &x))
+ goto InvalidInstruction;
+
+ if (!checkSignature(o0, o1, o2))
+ goto InvalidInstruction;
+
+ if (!checkGpId(o0, o1, o2))
+ goto InvalidPhysId;
+
+ uint64_t lsb = o3.as<Imm>().valueAs<uint64_t>();
+ uint32_t opSize = x ? 64 : 32;
+
+ if (lsb >= opSize)
+ goto InvalidImmediate;
+
+ opcode.reset(opData.opcode);
+ opcode.addImm(x, 31);
+ opcode.addImm(x, 22);
+ opcode.addReg(o2, 16);
+ opcode.addImm(lsb, 10);
+ opcode.addReg(o1, 5);
+ opcode.addReg(o0, 0);
+ goto EmitOp;
+ }
+
+ break;
+ }
+
+ case InstDB::kEncodingBaseRev: {
+ if (isign4 == ENC_OPS2(Reg, Reg)) {
+ uint32_t x;
+ if (!checkGpType(o0, InstDB::kWX, &x))
+ goto InvalidInstruction;
+
+ if (!checkSignature(o0, o1))
+ goto InvalidInstruction;
+
+ if (!checkGpId(o0, o1))
+ goto InvalidPhysId;
+
+ opcode.reset(0b01011010110000000000100000000000);
+ opcode.addImm(x, 31);
+ opcode.addImm(x, 10);
+ opcode.addReg(o1, 5);
+ opcode.addReg(o0, 0);
+ goto EmitOp;
+ }
+
+ break;
+ }
+
+ case InstDB::kEncodingBaseShift: {
+ const InstDB::EncodingData::BaseShift& opData = InstDB::EncodingData::baseShift[encodingIndex];
+
+ uint32_t x;
+ if (!checkGpType(o0, kWX, &x))
+ goto InvalidInstruction;
+
+ if (isign4 == ENC_OPS3(Reg, Reg, Reg)) {
+ if (!checkSignature(o0, o1, o2))
+ goto InvalidInstruction;
+
+ if (!checkGpId(o0, o1, o2, kZR))
+ goto InvalidPhysId;
+
+ opcode.reset(opData.registerOp());
+ opcode.addImm(x, 31);
+ opcode.addReg(o2, 16);
+ opcode.addReg(o1, 5);
+ opcode.addReg(o0, 0);
+ goto EmitOp;
+ }
+
+ if (isign4 == ENC_OPS3(Reg, Reg, Imm) && opData.immediateOp()) {
+ if (!checkSignature(o0, o1))
+ goto InvalidInstruction;
+
+ if (!checkGpId(o0, o1, kZR))
+ goto InvalidPhysId;
+
+ uint64_t immR = o2.as<Imm>().valueAs<uint64_t>();
+ uint32_t opSize = x ? 64 : 32;
+
+ if (immR >= opSize)
+ goto InvalidImmediate;
+
+ opcode.reset(opData.immediateOp());
+ opcode.addImm(x, 31);
+ opcode.addImm(x, 22);
+ opcode.addReg(o1, 5);
+ opcode.addReg(o0, 0);
+
+ if (opcode.get() & B(10)) {
+ // ASR and LSR (immediate) has the same logic.
+ opcode.addImm(x, 15);
+ opcode.addImm(immR, 16);
+ goto EmitOp;
+ }
+
+ if (opData.ror == 0) {
+ // LSL (immediate) is an alias to UBFM
+ uint32_t ubfmImmR = Support::neg(uint32_t(immR)) & (opSize - 1);
+ uint32_t ubfmImmS = opSize - 1 - uint32_t(immR);
+
+ opcode.addImm(ubfmImmR, 16);
+ opcode.addImm(ubfmImmS, 10);
+ goto EmitOp;
+ }
+ else {
+ // ROR (immediate) is an alias to EXTR.
+ opcode.addImm(immR, 10);
+ opcode.addReg(o1, 16);
+ goto EmitOp;
+ }
+ }
+
+ break;
+ }
+
+ // ------------------------------------------------------------------------
+ // [Base - Conditionals]
+ // ------------------------------------------------------------------------
+
+ case InstDB::kEncodingBaseCCmp: {
+ const InstDB::EncodingData::BaseCCmp& opData = InstDB::EncodingData::baseCCmp[encodingIndex];
+
+ if (isign4 == ENC_OPS4(Reg, Reg, Imm, Imm) || isign4 == ENC_OPS4(Reg, Imm, Imm, Imm)) {
+ uint32_t x;
+ if (!checkGpType(o0, InstDB::kWX, &x))
+ goto InvalidInstruction;
+
+ if (!checkGpId(o0, kZR))
+ goto InvalidPhysId;
+
+ uint64_t nzcv = o2.as<Imm>().valueAs<uint64_t>();
+ uint64_t cond = o3.as<Imm>().valueAs<uint64_t>();
+
+ if ((nzcv | cond) > 0xFu)
+ goto InvalidImmediate;
+
+ opcode.reset(opData.opcode);
+ opcode.addImm(x, 31);
+ opcode.addImm(condCodeToOpcodeCond(uint32_t(cond)), 12);
+ opcode.addImm(nzcv, 0);
+
+ if (isign4 == ENC_OPS4(Reg, Reg, Imm, Imm)) {
+ // CCMN|CCMP (register) form.
+ if (!checkSignature(o0, o1))
+ goto InvalidInstruction;
+
+ if (!checkGpId(o1, kZR))
+ goto InvalidPhysId;
+
+ opcode.addReg(o1, 16);
+ opcode.addReg(o0, 5);
+ goto EmitOp;
+ }
+ else {
+ // CCMN|CCMP (immediate) form.
+ uint64_t imm5 = o1.as<Imm>().valueAs<uint64_t>();
+ if (imm5 > 0x1F)
+ goto InvalidImmediate;
+
+ opcode.addImm(1, 11);
+ opcode.addImm(imm5, 16);
+ opcode.addReg(o0, 5);
+ goto EmitOp;
+ }
+ }
+
+ break;
+ }
+
+ case InstDB::kEncodingBaseCInc: {
+ const InstDB::EncodingData::BaseCInc& opData = InstDB::EncodingData::baseCInc[encodingIndex];
+
+ if (isign4 == ENC_OPS3(Reg, Reg, Imm)) {
+ uint32_t x;
+ if (!checkGpType(o0, o1, InstDB::kWX, &x))
+ goto InvalidInstruction;
+
+ if (!checkGpId(o0, o1, kZR))
+ goto InvalidPhysId;
+
+ uint64_t cond = o2.as<Imm>().valueAs<uint64_t>();
+ if (cond - 2u > 0xEu)
+ goto InvalidImmediate;
+
+ opcode.reset(opData.opcode);
+ opcode.addImm(x, 31);
+ opcode.addReg(o1, 16);
+ opcode.addImm(condCodeToOpcodeCond(uint32_t(cond)) ^ 1u, 12);
+ opcode.addReg(o1, 5);
+ opcode.addReg(o0, 0);
+ goto EmitOp;
+ }
+
+ break;
+ }
+
+ case InstDB::kEncodingBaseCSel: {
+ const InstDB::EncodingData::BaseCSel& opData = InstDB::EncodingData::baseCSel[encodingIndex];
+
+ if (isign4 == ENC_OPS4(Reg, Reg, Reg, Imm)) {
+ uint32_t x;
+ if (!checkGpType(o0, o1, o2, InstDB::kWX, &x))
+ goto InvalidInstruction;
+
+ if (!checkGpId(o0, o1, o2, kZR))
+ goto InvalidPhysId;
+
+ uint64_t cond = o3.as<Imm>().valueAs<uint64_t>();
+ if (cond > 0xFu)
+ goto InvalidImmediate;
+
+ opcode.reset(opData.opcode);
+ opcode.addImm(x, 31);
+ opcode.addReg(o2, 16);
+ opcode.addImm(condCodeToOpcodeCond(uint32_t(cond)), 12);
+ opcode.addReg(o1, 5);
+ opcode.addReg(o0, 0);
+ goto EmitOp;
+ }
+
+ break;
+ }
+
+ case InstDB::kEncodingBaseCSet: {
+ const InstDB::EncodingData::BaseCSet& opData = InstDB::EncodingData::baseCSet[encodingIndex];
+
+ if (isign4 == ENC_OPS2(Reg, Imm)) {
+ uint32_t x;
+ if (!checkGpType(o0, InstDB::kWX, &x))
+ goto InvalidInstruction;
+
+ if (!checkGpId(o0, kZR))
+ goto InvalidPhysId;
+
+ uint64_t cond = o1.as<Imm>().valueAs<uint64_t>();
+ if (cond - 2u >= 0xEu)
+ goto InvalidImmediate;
+
+ opcode.reset(opData.opcode);
+ opcode.addImm(x, 31);
+ opcode.addImm(condCodeToOpcodeCond(uint32_t(cond)) ^ 1u, 12);
+ opcode.addReg(o0, 0);
+ goto EmitOp;
+ }
+
+ break;
+ }
+
+ // ------------------------------------------------------------------------
+ // [Base - Special]
+ // ------------------------------------------------------------------------
+
+ case InstDB::kEncodingBaseAtDcIcTlbi: {
+ const InstDB::EncodingData::BaseAtDcIcTlbi& opData = InstDB::EncodingData::baseAtDcIcTlbi[encodingIndex];
+
+ if (isign4 == ENC_OPS1(Imm) || isign4 == ENC_OPS2(Imm, Reg)) {
+ if (opData.mandatoryReg && isign4 != ENC_OPS2(Imm, Reg))
+ goto InvalidInstruction;
+
+ if (o0.as<Imm>().valueAs<uint64_t>() > 0x7FFFu)
+ goto InvalidImmediate;
+
+ uint32_t imm = o0.as<Imm>().valueAs<uint32_t>();
+ if ((imm & opData.immVerifyMask) != opData.immVerifyData)
+ goto InvalidImmediate;
+
+ uint32_t rt = 31;
+ if (o1.isReg()) {
+ if (!o1.as<Reg>().isGpX())
+ goto InvalidInstruction;
+
+ if (!checkGpId(o1, kZR))
+ goto InvalidPhysId;
+
+ rt = o1.id() & 31;
+ }
+
+ opcode.reset(0b11010101000010000000000000000000);
+ opcode.addImm(imm, 5);
+ opcode.addReg(rt, 0);
+ goto EmitOp;
+ }
+ break;
+ }
+
+ case InstDB::kEncodingBaseMrs: {
+ if (isign4 == ENC_OPS2(Reg, Imm)) {
+ if (!o0.as<Reg>().isGpX())
+ goto InvalidInstruction;
+
+ if (!checkGpId(o0, kZR))
+ goto InvalidPhysId;
+
+ if (o1.as<Imm>().valueAs<uint64_t>() > 0xFFFFu)
+ goto InvalidImmediate;
+
+ uint32_t imm = o1.as<Imm>().valueAs<uint32_t>();
+ if (!(imm & B(15)))
+ goto InvalidImmediate;
+
+ opcode.reset(0b11010101001100000000000000000000);
+ opcode.addImm(imm, 5);
+ opcode.addReg(o0, 0);
+ goto EmitOp;
+ }
+
+ break;
+ }
+
+ case InstDB::kEncodingBaseMsr: {
+ if (isign4 == ENC_OPS2(Imm, Reg)) {
+ if (!o1.as<Reg>().isGpX())
+ goto InvalidInstruction;
+
+ if (o0.as<Imm>().valueAs<uint64_t>() > 0xFFFFu)
+ goto InvalidImmediate;
+
+ uint32_t imm = o0.as<Imm>().valueAs<uint32_t>();
+ if (!(imm & B(15)))
+ goto InvalidImmediate;
+
+ if (!checkGpId(o1, kZR))
+ goto InvalidPhysId;
+
+ opcode.reset(0b11010101000100000000000000000000);
+ opcode.addImm(imm, 5);
+ opcode.addReg(o1, 0);
+ goto EmitOp;
+ }
+
+ if (isign4 == ENC_OPS2(Imm, Imm)) {
+ if (o0.as<Imm>().valueAs<uint64_t>() > 0x1Fu)
+ goto InvalidImmediate;
+
+ if (o1.as<Imm>().valueAs<uint64_t>() > 0xFu)
+ goto InvalidImmediate;
+
+ uint32_t op = o0.as<Imm>().valueAs<uint32_t>();
+ uint32_t cRm = o1.as<Imm>().valueAs<uint32_t>();
+
+ uint32_t op1 = uint32_t(op) >> 3;
+ uint32_t op2 = uint32_t(op) & 0x7u;
+
+ opcode.reset(0b11010101000000000100000000011111);
+ opcode.addImm(op1, 16);
+ opcode.addImm(cRm, 8);
+ opcode.addImm(op2, 5);
+ goto EmitOp;
+ }
+
+ break;
+ }
+
+ case InstDB::kEncodingBaseSys: {
+ if (isign4 == ENC_OPS4(Imm, Imm, Imm, Imm)) {
+ if (o0.as<Imm>().valueAs<uint64_t>() > 0x7u ||
+ o1.as<Imm>().valueAs<uint64_t>() > 0xFu ||
+ o2.as<Imm>().valueAs<uint64_t>() > 0xFu ||
+ o3.as<Imm>().valueAs<uint64_t>() > 0x7u)
+ goto InvalidImmediate;
+
+ uint32_t op1 = o0.as<Imm>().valueAs<uint32_t>();
+ uint32_t cRn = o1.as<Imm>().valueAs<uint32_t>();
+ uint32_t cRm = o2.as<Imm>().valueAs<uint32_t>();
+ uint32_t op2 = o3.as<Imm>().valueAs<uint32_t>();
+ uint32_t rt = 31;
+
+ const Operand_& o4 = opExt[EmitterUtils::kOp4];
+ if (o4.isReg()) {
+ if (!o4.as<Reg>().isGpX())
+ goto InvalidInstruction;
+
+ if (!checkGpId(o4, kZR))
+ goto InvalidPhysId;
+
+ rt = o4.id() & 31;
+ }
+ else if (!o4.isNone()) {
+ goto InvalidInstruction;
+ }
+
+ opcode.reset(0b11010101000010000000000000000000);
+ opcode.addImm(op1, 16);
+ opcode.addImm(cRn, 12);
+ opcode.addImm(cRm, 8);
+ opcode.addImm(op2, 5);
+ opcode.addImm(rt, 0);
+ goto EmitOp;
+ }
+
+ break;
+ }
+
+ // ------------------------------------------------------------------------
+ // [Base - Branch]
+ // ------------------------------------------------------------------------
+
+ case InstDB::kEncodingBaseBranchReg: {
+ const InstDB::EncodingData::BaseBranchReg& opData = InstDB::EncodingData::baseBranchReg[encodingIndex];
+
+ if (isign4 == ENC_OPS1(Reg)) {
+ if (!o0.as<Reg>().isGpX())
+ goto InvalidInstruction;
+
+ if (!checkGpId(o0, kZR))
+ goto InvalidPhysId;
+
+ opcode.reset(opData.opcode);
+ opcode.addReg(o0, 5);
+ goto EmitOp;
+ }
+
+ break;
+ }
+
+ case InstDB::kEncodingBaseBranchRel: {
+ const InstDB::EncodingData::BaseBranchRel& opData = InstDB::EncodingData::baseBranchRel[encodingIndex];
+
+ if (isign4 == ENC_OPS1(Label) || isign4 == ENC_OPS1(Imm)) {
+ opcode.reset(opData.opcode);
+ rmRel = &o0;
+
+ if (instCC != CondCode::kAL) {
+ opcode |= B(30);
+ opcode.addImm(condCodeToOpcodeCond(uint32_t(instCC)), 0);
+ offsetFormat.resetToImmValue(OffsetType::kSignedOffset, 4, 5, 19, 2);
+ goto EmitOp_Rel;
+ }
+
+ offsetFormat.resetToImmValue(OffsetType::kSignedOffset, 4, 0, 26, 2);
+ goto EmitOp_Rel;
+ }
+
+ break;
+ }
+
+ case InstDB::kEncodingBaseBranchCmp: {
+ const InstDB::EncodingData::BaseBranchCmp& opData = InstDB::EncodingData::baseBranchCmp[encodingIndex];
+
+ if (isign4 == ENC_OPS2(Reg, Label) || isign4 == ENC_OPS2(Reg, Imm)) {
+ uint32_t x;
+ if (!checkGpType(o0, kWX, &x))
+ goto InvalidInstruction;
+
+ if (!checkGpId(o0, kZR))
+ goto InvalidPhysId;
+
+ opcode.reset(opData.opcode);
+ opcode.addImm(x, 31);
+ opcode.addReg(o0, 0);
+ offsetFormat.resetToImmValue(OffsetType::kSignedOffset, 4, 5, 19, 2);
+
+ rmRel = &o1;
+ goto EmitOp_Rel;
+ }
+
+ break;
+ }
+
+ case InstDB::kEncodingBaseBranchTst: {
+ const InstDB::EncodingData::BaseBranchTst& opData = InstDB::EncodingData::baseBranchTst[encodingIndex];
+
+ if (isign4 == ENC_OPS3(Reg, Imm, Label) || isign4 == ENC_OPS3(Reg, Imm, Imm)) {
+ uint32_t x;
+ if (!checkGpType(o0, kWX, &x))
+ goto InvalidInstruction;
+
+ if (!checkGpId(o0, kZR))
+ goto InvalidPhysId;
+
+ uint64_t imm = o1.as<Imm>().valueAs<uint64_t>();
+
+ opcode.reset(opData.opcode);
+ if (imm >= 32) {
+ if (!x)
+ goto InvalidImmediate;
+ opcode.addImm(x, 31);
+ imm &= 0x1F;
+ }
+
+ opcode.addReg(o0, 0);
+ opcode.addImm(imm, 19);
+ offsetFormat.resetToImmValue(OffsetType::kSignedOffset, 4, 5, 14, 2);
+
+ rmRel = &o2;
+ goto EmitOp_Rel;
+ }
+
+ break;
+ }
+
+ // ------------------------------------------------------------------------
+ // [Base - Load / Store]
+ // ------------------------------------------------------------------------
+
+ case InstDB::kEncodingBaseLdSt: {
+ const InstDB::EncodingData::BaseLdSt& opData = InstDB::EncodingData::baseLdSt[encodingIndex];
+
+ if (isign4 == ENC_OPS2(Reg, Mem)) {
+ const Mem& m = o1.as<Mem>();
+ rmRel = &m;
+
+ uint32_t x;
+ if (!checkGpType(o0, opData.rType, &x))
+ goto InvalidInstruction;
+
+ if (!checkGpId(o0, kZR))
+ goto InvalidPhysId;
+
+ // Instructions that work with either word or dword have the unsigned
+ // offset shift set to 2 (word), so we set it to 3 (dword) if this is
+ // X version of the instruction.
+ uint32_t xShiftMask = uint32_t(opData.uOffsetShift == 2);
+ uint32_t immShift = uint32_t(opData.uOffsetShift) + (x & xShiftMask);
+
+ if (!armCheckMemBaseIndexRel(m))
+ goto InvalidAddress;
+
+ int64_t offset = m.offset();
+ if (m.hasBaseReg()) {
+ // [Base {Offset | Index}]
+ if (m.hasIndex()) {
+ uint32_t opt = armShiftOpToLdStOptMap[m.predicate()];
+ if (opt == 0xFF)
+ goto InvalidAddress;
+
+ uint32_t shift = m.shift();
+ uint32_t s = shift != 0;
+
+ if (s && shift != immShift)
+ goto InvalidAddressScale;
+
+ opcode.reset(uint32_t(opData.registerOp) << 21);
+ opcode.xorImm(x, opData.xOffset);
+ opcode.addImm(opt, 13);
+ opcode.addImm(s, 12);
+ opcode |= B(11);
+ opcode.addReg(o0, 0);
+ goto EmitOp_MemBaseIndex_Rn5_Rm16;
+ }
+
+ // Makes it easier to work with the offset especially on 32-bit arch.
+ if (!Support::isInt32(offset))
+ goto InvalidDisplacement;
+ int32_t offset32 = int32_t(offset);
+
+ if (m.isPreOrPost()) {
+ if (!Support::isInt9(offset32))
+ goto InvalidDisplacement;
+
+ opcode.reset(uint32_t(opData.prePostOp) << 21);
+ opcode.xorImm(x, opData.xOffset);
+ opcode.addImm(offset32 & 0x1FF, 12);
+ opcode.addImm(m.isPreIndex(), 11);
+ opcode |= B(10);
+ opcode.addReg(o0, 0);
+ goto EmitOp_MemBase_Rn5;
+ }
+ else {
+ uint32_t imm12 = uint32_t(offset32) >> immShift;
+
+ // Alternative form of LDUR/STUR and related instructions as described by AArch64 reference manual:
+ //
+ // If this instruction is not encodable with scaled unsigned offset, try unscaled signed offset.
+ if (!Support::isUInt12(imm12) || (imm12 << immShift) != uint32_t(offset32)) {
+ instId = opData.uAltInstId;
+ instInfo = &InstDB::_instInfoTable[instId];
+ encodingIndex = instInfo->_encodingDataIndex;
+ goto Case_BaseLdurStur;
+ }
+
+ opcode.reset(uint32_t(opData.uOffsetOp) << 22);
+ opcode.xorImm(x, opData.xOffset);
+ opcode.addImm(imm12, 10);
+ opcode.addReg(o0, 0);
+ goto EmitOp_MemBase_Rn5;
+ }
+ }
+ else {
+ if (!opData.literalOp)
+ goto InvalidAddress;
+
+ opcode.reset(uint32_t(opData.literalOp) << 24);
+ opcode.xorImm(x, opData.xOffset);
+ opcode.addReg(o0, 0);
+ offsetFormat.resetToImmValue(OffsetType::kSignedOffset, 4, 5, 19, 2);
+ goto EmitOp_Rel;
+ }
+ }
+
+ break;
+ }
+
+ case InstDB::kEncodingBaseLdpStp: {
+ const InstDB::EncodingData::BaseLdpStp& opData = InstDB::EncodingData::baseLdpStp[encodingIndex];
+
+ if (isign4 == ENC_OPS3(Reg, Reg, Mem)) {
+ const Mem& m = o2.as<Mem>();
+ rmRel = &m;
+
+ uint32_t x;
+ if (!checkGpType(o0, o1, opData.rType, &x))
+ goto InvalidInstruction;
+
+ if (!checkGpId(o0, o1, kZR))
+ goto InvalidPhysId;
+
+ if (m.baseType() != RegType::kARM_GpX || m.hasIndex())
+ goto InvalidAddress;
+
+ if (m.isOffset64Bit())
+ goto InvalidDisplacement;
+
+ uint32_t offsetShift = opData.offsetShift + x;
+ int32_t offset32 = m.offsetLo32() >> offsetShift;
+
+ // Make sure we didn't lose bits by applying the mandatory offset shift.
+ if (uint32_t(offset32) << offsetShift != uint32_t(m.offsetLo32()))
+ goto InvalidDisplacement;
+
+ // Offset is encoded as 7-bit immediate.
+ if (!Support::isInt7(offset32))
+ goto InvalidDisplacement;
+
+ if (m.isPreOrPost() && offset32 != 0) {
+ if (!opData.prePostOp)
+ goto InvalidAddress;
+
+ opcode.reset(uint32_t(opData.prePostOp) << 22);
+ opcode.addImm(m.isPreIndex(), 24);
+ }
+ else {
+ opcode.reset(uint32_t(opData.offsetOp) << 22);
+ }
+
+ opcode.addImm(x, opData.xOffset);
+ opcode.addImm(offset32 & 0x7F, 15);
+ opcode.addReg(o1, 10);
+ opcode.addReg(o0, 0);
+ goto EmitOp_MemBase_Rn5;
+ }
+
+ break;
+ }
+
+ case InstDB::kEncodingBaseStx: {
+ const InstDB::EncodingData::BaseStx& opData = InstDB::EncodingData::baseStx[encodingIndex];
+
+ if (isign4 == ENC_OPS3(Reg, Reg, Mem)) {
+ const Mem& m = o2.as<Mem>();
+ uint32_t x;
+
+ if (!o0.as<Reg>().isGpW() || !checkGpType(o1, opData.rType, &x))
+ goto InvalidInstruction;
+
+ if (!checkGpId(o0, o1, kZR))
+ goto InvalidPhysId;
+
+ opcode.reset(opData.opcode());
+ opcode.addImm(x, opData.xOffset);
+ opcode.addReg(o0, 16);
+ opcode.addReg(o1, 0);
+
+ rmRel = &m;
+ goto EmitOp_MemBaseNoImm_Rn5;
+ }
+
+ break;
+ }
+
+ case InstDB::kEncodingBaseLdxp: {
+ const InstDB::EncodingData::BaseLdxp& opData = InstDB::EncodingData::baseLdxp[encodingIndex];
+
+ if (isign4 == ENC_OPS3(Reg, Reg, Mem)) {
+ const Mem& m = o2.as<Mem>();
+ uint32_t x;
+
+ if (!checkGpType(o0, opData.rType, &x) || !checkSignature(o0, o1))
+ goto InvalidInstruction;
+
+ if (!checkGpId(o0, o1, kZR))
+ goto InvalidPhysId;
+
+ opcode.reset(opData.opcode());
+ opcode.addImm(x, opData.xOffset);
+ opcode.addReg(o1, 10);
+ opcode.addReg(o0, 0);
+
+ rmRel = &m;
+ goto EmitOp_MemBaseNoImm_Rn5;
+ }
+
+ break;
+ }
+
+ case InstDB::kEncodingBaseStxp: {
+ const InstDB::EncodingData::BaseStxp& opData = InstDB::EncodingData::baseStxp[encodingIndex];
+
+ if (isign4 == ENC_OPS4(Reg, Reg, Reg, Mem)) {
+ const Mem& m = o3.as<Mem>();
+ uint32_t x;
+
+ if (!o0.as<Reg>().isGpW() || !checkGpType(o1, opData.rType, &x) || !checkSignature(o1, o2))
+ goto InvalidInstruction;
+
+ if (!checkGpId(o0, o1, o2, kZR))
+ goto InvalidPhysId;
+
+ opcode.reset(opData.opcode());
+ opcode.addImm(x, opData.xOffset);
+ opcode.addReg(o0, 16);
+ opcode.addReg(o2, 10);
+ opcode.addReg(o1, 0);
+
+ rmRel = &m;
+ goto EmitOp_MemBaseNoImm_Rn5;
+ }
+
+ break;
+ }
+
+ case InstDB::kEncodingBaseRM_NoImm: {
+ const InstDB::EncodingData::BaseRM_NoImm& opData = InstDB::EncodingData::baseRM_NoImm[encodingIndex];
+
+ if (isign4 == ENC_OPS2(Reg, Mem)) {
+ const Mem& m = o1.as<Mem>();
+ rmRel = &m;
+
+ uint32_t x;
+ if (!checkGpType(o0, opData.rType, &x))
+ goto InvalidInstruction;
+
+ if (!checkGpId(o0, opData.rHiId))
+ goto InvalidPhysId;
+
+ opcode.reset(opData.opcode());
+ opcode.addImm(x, opData.xOffset);
+ opcode.addReg(o0, 0);
+ goto EmitOp_MemBaseNoImm_Rn5;
+ }
+
+ break;
+ }
+
+ case InstDB::kEncodingBaseRM_SImm9: {
+Case_BaseLdurStur:
+ const InstDB::EncodingData::BaseRM_SImm9& opData = InstDB::EncodingData::baseRM_SImm9[encodingIndex];
+
+ if (isign4 == ENC_OPS2(Reg, Mem)) {
+ const Mem& m = o1.as<Mem>();
+ rmRel = &m;
+
+ uint32_t x;
+ if (!checkGpType(o0, opData.rType, &x))
+ goto InvalidInstruction;
+
+ if (!checkGpId(o0, opData.rHiId))
+ goto InvalidPhysId;
+
+ if (m.hasBaseReg() && !m.hasIndex()) {
+ if (m.isOffset64Bit())
+ goto InvalidDisplacement;
+
+ int32_t offset32 = m.offsetLo32() >> opData.immShift;
+ if (Support::shl(offset32, opData.immShift) != m.offsetLo32())
+ goto InvalidDisplacement;
+
+ if (!Support::isInt9(offset32))
+ goto InvalidDisplacement;
+
+ if (m.isFixedOffset()) {
+ opcode.reset(opData.offsetOp());
+ }
+ else {
+ if (!opData.prePostOp())
+ goto InvalidInstruction;
+
+ opcode.reset(opData.prePostOp());
+ opcode.xorImm(m.isPreIndex(), 11);
+ }
+
+ opcode.xorImm(x, opData.xOffset);
+ opcode.addImm(offset32 & 0x1FF, 12);
+ opcode.addReg(o0, 0);
+ goto EmitOp_MemBase_Rn5;
+ }
+
+ goto InvalidAddress;
+ }
+
+ break;
+ }
+
+ case InstDB::kEncodingBaseRM_SImm10: {
+ const InstDB::EncodingData::BaseRM_SImm10& opData = InstDB::EncodingData::baseRM_SImm10[encodingIndex];
+
+ if (isign4 == ENC_OPS2(Reg, Mem)) {
+ const Mem& m = o1.as<Mem>();
+ rmRel = &m;
+
+ uint32_t x;
+ if (!checkGpType(o0, opData.rType, &x))
+ goto InvalidInstruction;
+
+ if (!checkGpId(o0, opData.rHiId))
+ goto InvalidPhysId;
+
+ if (m.hasBaseReg() && !m.hasIndex()) {
+ if (m.isOffset64Bit())
+ goto InvalidDisplacement;
+
+ int32_t offset32 = m.offsetLo32() >> opData.immShift;
+ if (Support::shl(offset32, opData.immShift) != m.offsetLo32())
+ goto InvalidDisplacement;
+
+ if (!Support::isInt10(offset32))
+ goto InvalidDisplacement;
+
+ if (m.isPostIndex())
+ goto InvalidAddress;
+
+ // Offset has 10 bits, sign is stored in the 10th bit.
+ offset32 &= 0x3FF;
+
+ opcode.reset(opData.opcode());
+ opcode.xorImm(m.isPreIndex(), 11);
+ opcode.xorImm(x, opData.xOffset);
+ opcode.addImm(offset32 >> 9, 22);
+ opcode.addImm(offset32, 12);
+ opcode.addReg(o0, 0);
+ goto EmitOp_MemBase_Rn5;
+ }
+
+ goto InvalidAddress;
+ }
+
+ break;
+ }
+
+ case InstDB::kEncodingBaseAtomicOp: {
+ const InstDB::EncodingData::BaseAtomicOp& opData = InstDB::EncodingData::baseAtomicOp[encodingIndex];
+
+ if (isign4 == ENC_OPS3(Reg, Reg, Mem)) {
+ const Mem& m = o2.as<Mem>();
+ uint32_t x;
+
+ if (!checkGpType(o0, opData.rType, &x) || !checkSignature(o0, o1))
+ goto InvalidInstruction;
+
+ if (!checkGpId(o0, o1, kZR))
+ goto InvalidInstruction;
+
+ opcode.reset(opData.opcode());
+ opcode.addImm(x, opData.xOffset);
+ opcode.addReg(o0, 16);
+ opcode.addReg(o1, 0);
+
+ rmRel = &m;
+ goto EmitOp_MemBaseNoImm_Rn5;
+ }
+
+ break;
+ }
+
+ case InstDB::kEncodingBaseAtomicSt: {
+ const InstDB::EncodingData::BaseAtomicSt& opData = InstDB::EncodingData::baseAtomicSt[encodingIndex];
+
+ if (isign4 == ENC_OPS2(Reg, Mem)) {
+ const Mem& m = o1.as<Mem>();
+ uint32_t x;
+
+ if (!checkGpType(o0, opData.rType, &x))
+ goto InvalidInstruction;
+
+ if (!checkGpId(o0, kZR))
+ goto InvalidPhysId;
+
+ opcode.reset(opData.opcode());
+ opcode.addImm(x, opData.xOffset);
+ opcode.addReg(o0, 16);
+ opcode.addReg(Gp::kIdZr, 0);
+
+ rmRel = &m;
+ goto EmitOp_MemBaseNoImm_Rn5;
+ }
+
+ break;
+ }
+
+ case InstDB::kEncodingBaseAtomicCasp: {
+ const InstDB::EncodingData::BaseAtomicCasp& opData = InstDB::EncodingData::baseAtomicCasp[encodingIndex];
+ const Operand_& o4 = opExt[EmitterUtils::kOp4];
+
+ if (isign4 == ENC_OPS4(Reg, Reg, Reg, Reg) && o4.isMem()) {
+ const Mem& m = o4.as<Mem>();
+ uint32_t x;
+
+ if (!checkGpType(o0, opData.rType, &x))
+ goto InvalidInstruction;
+
+ if (!checkSignature(o0, o1, o2, o3))
+ goto InvalidInstruction;
+
+ if (!checkEven(o0, o2) || !checkGpId(o0, o2, kZR))
+ goto InvalidPhysId;
+
+ if (!checkConsecutive(o0, o1) || !checkConsecutive(o2, o3))
+ goto InvalidPhysId;
+
+ opcode.reset(opData.opcode());
+ opcode.addImm(x, opData.xOffset);
+ opcode.addReg(o0, 16);
+ opcode.addReg(o2, 0);
+
+ rmRel = &m;
+ goto EmitOp_MemBaseNoImm_Rn5;
+ }
+
+ break;
+ }
+
+ // ------------------------------------------------------------------------
+ // [FSimd - Instructions]
+ // ------------------------------------------------------------------------
+
+ case InstDB::kEncodingFSimdSV: {
+ const InstDB::EncodingData::FSimdSV& opData = InstDB::EncodingData::fSimdSV[encodingIndex];
+
+ if (isign4 == ENC_OPS2(Reg, Reg)) {
+ uint32_t q = diff(o1.as<Reg>().type(), RegType::kARM_VecD);
+ if (q > 1)
+ goto InvalidInstruction;
+
+ if (o0.as<Vec>().hasElementType())
+ goto InvalidInstruction;
+
+ // This operation is only defined for:
+ // hD, vS.{4|8}h (16-bit)
+ // sD, vS.4s (32-bit)
+ uint32_t sz = diff(o0.as<Reg>().type(), RegType::kARM_VecH);
+ uint32_t elementSz = o1.as<Vec>().elementType() - Vec::kElementTypeH;
+
+ // Size greater than 1 means 64-bit elements, not supported.
+ if ((sz | elementSz) > 1 || sz != elementSz)
+ goto InvalidInstruction;
+
+ // Size 1 (32-bit float) requires at least 4 elements.
+ if (sz && !q)
+ goto InvalidInstruction;
+
+ // Bit flipping according to sz.
+ static const uint32_t szBits[] = { B(29), 0 };
+
+ opcode.reset(opData.opcode << 10);
+ opcode ^= szBits[sz];
+ opcode.addImm(q, 30);
+ goto EmitOp_Rd0_Rn5;
+ }
+
+ break;
+ }
+
+ case InstDB::kEncodingFSimdVV: {
+ const InstDB::EncodingData::FSimdVV& opData = InstDB::EncodingData::fSimdVV[encodingIndex];
+
+ if (isign4 == ENC_OPS2(Reg, Reg)) {
+ if (!matchSignature(o0, o1, instFlags))
+ goto InvalidInstruction;
+
+ if (!pickFpOpcode(o0.as<Vec>(), opData.scalarOp(), opData.scalarHf(), opData.vectorOp(), opData.vectorHf(), &opcode))
+ goto InvalidInstruction;
+
+ goto EmitOp_Rd0_Rn5;
+ }
+
+ break;
+ }
+
+ case InstDB::kEncodingFSimdVVV: {
+ const InstDB::EncodingData::FSimdVVV& opData = InstDB::EncodingData::fSimdVVV[encodingIndex];
+
+ if (isign4 == ENC_OPS3(Reg, Reg, Reg)) {
+ if (!matchSignature(o0, o1, o2, instFlags))
+ goto InvalidInstruction;
+
+ if (!pickFpOpcode(o0.as<Vec>(), opData.scalarOp(), opData.scalarHf(), opData.vectorOp(), opData.vectorHf(), &opcode))
+ goto InvalidInstruction;
+
+ goto EmitOp_Rd0_Rn5_Rm16;
+ }
+
+ break;
+ }
+
+ case InstDB::kEncodingFSimdVVVe: {
+ const InstDB::EncodingData::FSimdVVVe& opData = InstDB::EncodingData::fSimdVVVe[encodingIndex];
+
+ if (isign4 == ENC_OPS3(Reg, Reg, Reg)) {
+ if (!o2.as<Vec>().hasElementIndex()) {
+ if (!matchSignature(o0, o1, o2, instFlags))
+ goto InvalidInstruction;
+
+ if (!pickFpOpcode(o0.as<Vec>(), opData.scalarOp(), opData.scalarHf(), opData.vectorOp(), opData.vectorHf(), &opcode))
+ goto InvalidInstruction;
+
+ goto EmitOp_Rd0_Rn5_Rm16;
+ }
+ else {
+ if (!matchSignature(o0, o1, instFlags))
+ goto InvalidInstruction;
+
+ uint32_t q = o1.as<Reg>().isVecQ();
+ uint32_t sz;
+
+ if (!pickFpOpcode(o0.as<Vec>(), opData.elementScalarOp(), InstDB::kHF_D, opData.elementVectorOp(), InstDB::kHF_D, &opcode, &sz))
+ goto InvalidInstruction;
+
+ if (sz == 0 && o2.as<Reg>().id() > 15)
+ goto InvalidPhysId;
+
+ uint32_t elementIndex = o2.as<Vec>().elementIndex();
+ if (elementIndex > (7u >> sz))
+ goto InvalidElementIndex;
+
+ uint32_t hlm = elementIndex << sz;
+ opcode.addImm(q, 30);
+ opcode.addImm(hlm & 3u, 20);
+ opcode.addImm(hlm >> 2, 11);
+ goto EmitOp_Rd0_Rn5_Rm16;
+ }
+ }
+
+ break;
+ }
+
+ case InstDB::kEncodingFSimdVVVV: {
+ const InstDB::EncodingData::FSimdVVVV& opData = InstDB::EncodingData::fSimdVVVV[encodingIndex];
+
+ if (isign4 == ENC_OPS4(Reg, Reg, Reg, Reg)) {
+ if (!matchSignature(o0, o1, o2, o3, instFlags))
+ goto InvalidInstruction;
+
+ if (!pickFpOpcode(o0.as<Vec>(), opData.scalarOp(), opData.scalarHf(), opData.vectorOp(), opData.vectorHf(), &opcode))
+ goto InvalidInstruction;
+
+ goto EmitOp_Rd0_Rn5_Rm16_Ra10;
+ }
+
+ break;
+ }
+
+ case InstDB::kEncodingSimdFcadd: {
+ const InstDB::EncodingData::SimdFcadd& opData = InstDB::EncodingData::simdFcadd[encodingIndex];
+
+ if (isign4 == ENC_OPS4(Reg, Reg, Reg, Imm)) {
+ if (!checkSignature(o0, o1, o2) || o0.as<Vec>().hasElementIndex())
+ goto InvalidInstruction;
+
+ uint32_t q = diff(o0.as<Reg>().type(), RegType::kARM_VecD);
+ if (q > 1)
+ goto InvalidInstruction;
+
+ uint32_t sz = o0.as<Vec>().elementType() - Vec::kElementTypeB;
+ if (sz == 0 || sz > 3)
+ goto InvalidInstruction;
+
+ // 0 <- 90deg.
+ // 1 <- 270deg.
+ uint32_t rot = 0;
+ if (o3.as<Imm>().value() == 270)
+ rot = 1;
+ else if (o3.as<Imm>().value() != 90)
+ goto InvalidImmediate;
+
+ opcode.reset(opData.opcode());
+ opcode.addImm(q, 30);
+ opcode.addImm(sz, 22);
+ opcode.addImm(rot, 12);
+ goto EmitOp_Rd0_Rn5_Rm16;
+ }
+
+ break;
+ }
+
+ case InstDB::kEncodingSimdFccmpFccmpe: {
+ const InstDB::EncodingData::SimdFccmpFccmpe& opData = InstDB::EncodingData::simdFccmpFccmpe[encodingIndex];
+
+ if (isign4 == ENC_OPS4(Reg, Reg, Imm, Imm)) {
+ uint32_t sz = diff(o0.as<Reg>().type(), RegType::kARM_VecH);
+ if (sz > 2)
+ goto InvalidInstruction;
+
+ if (!checkSignature(o0, o1) || o0.as<Vec>().hasElementType())
+ goto InvalidInstruction;
+
+ uint64_t nzcv = o2.as<Imm>().valueAs<uint64_t>();
+ uint64_t cond = o3.as<Imm>().valueAs<uint64_t>();
+
+ if ((nzcv | cond) > 0xFu)
+ goto InvalidImmediate;
+
+ uint32_t type = (sz - 1) & 0x3u;
+
+ opcode.reset(opData.opcode());
+ opcode.addImm(type, 22);
+ opcode.addImm(condCodeToOpcodeCond(uint32_t(cond)), 12);
+ opcode.addImm(nzcv, 0);
+
+ goto EmitOp_Rn5_Rm16;
+ }
+
+ break;
+ }
+
+ case InstDB::kEncodingSimdFcm: {
+ const InstDB::EncodingData::SimdFcm& opData = InstDB::EncodingData::simdFcm[encodingIndex];
+
+ if (isign4 == ENC_OPS3(Reg, Reg, Reg) && opData.hasRegisterOp()) {
+ if (!matchSignature(o0, o1, o2, instFlags))
+ goto InvalidInstruction;
+
+ if (!pickFpOpcode(o0.as<Vec>(), opData.registerScalarOp(), opData.registerScalarHf(), opData.registerVectorOp(), opData.registerVectorHf(), &opcode))
+ goto InvalidInstruction;
+
+ goto EmitOp_Rd0_Rn5_Rm16;
+ }
+
+ if (isign4 == ENC_OPS3(Reg, Reg, Imm) && opData.hasZeroOp()) {
+ if (!checkSignature(o0, o1))
+ goto InvalidInstruction;
+
+ if (o2.as<Imm>().value() != 0 || o2.as<Imm>().predicate() != 0)
+ goto InvalidImmediate;
+
+ if (!pickFpOpcode(o0.as<Vec>(), opData.zeroScalarOp(), InstDB::kHF_B, opData.zeroVectorOp(), InstDB::kHF_B, &opcode))
+ goto InvalidInstruction;
+
+ goto EmitOp_Rd0_Rn5;
+ }
+
+ break;
+ }
+
+ case InstDB::kEncodingSimdFcmla: {
+ const InstDB::EncodingData::SimdFcmla& opData = InstDB::EncodingData::simdFcmla[encodingIndex];
+
+ if (isign4 == ENC_OPS4(Reg, Reg, Reg, Imm)) {
+ if (!checkSignature(o0, o1))
+ goto InvalidInstruction;
+
+ uint32_t q = diff(o0.as<Reg>().type(), RegType::kARM_VecD);
+ if (q > 1)
+ goto InvalidInstruction;
+
+ uint32_t sz = o0.as<Vec>().elementType() - Vec::kElementTypeB;
+ if (sz == 0 || sz > 3)
+ goto InvalidInstruction;
+
+ uint32_t rot = 0;
+ switch (o3.as<Imm>().value()) {
+ case 0 : rot = 0; break;
+ case 90 : rot = 1; break;
+ case 180: rot = 2; break;
+ case 270: rot = 3; break;
+ default:
+ goto InvalidImmediate;
+ }
+
+ if (!o2.as<Vec>().hasElementIndex()) {
+ if (!checkSignature(o1, o2))
+ goto InvalidInstruction;
+
+ opcode.reset(opData.regularOp());
+ opcode.addImm(q, 30);
+ opcode.addImm(sz, 22);
+ opcode.addImm(rot, 11);
+ goto EmitOp_Rd0_Rn5_Rm16;
+ }
+ else {
+ if (o0.as<Vec>().elementType() != o2.as<Vec>().elementType())
+ goto InvalidInstruction;
+
+ // Only allowed vectors are: 4H, 8H, and 4S.
+ if (!(sz == 1 || (q == 1 && sz == 2)))
+ goto InvalidInstruction;
+
+ // Element index ranges:
+ // 4H - ElementIndex[0..1] (index 2..3 is UNDEFINED).
+ // 8H - ElementIndex[0..3].
+ // 4S - ElementIndex[0..1].
+ uint32_t elementIndex = o2.as<Vec>().elementIndex();
+ uint32_t hlFieldShift = sz == 1 ? 0u : 1u;
+ uint32_t maxElementIndex = q == 1 && sz == 1 ? 3u : 1u;
+
+ if (elementIndex > maxElementIndex)
+ goto InvalidElementIndex;
+
+ uint32_t hl = elementIndex << hlFieldShift;
+
+ opcode.reset(opData.elementOp());
+ opcode.addImm(q, 30);
+ opcode.addImm(sz, 22);
+ opcode.addImm(hl & 1u, 21); // L field.
+ opcode.addImm(hl >> 1, 11); // H field.
+ opcode.addImm(rot, 13);
+ goto EmitOp_Rd0_Rn5_Rm16;
+ }
+ }
+
+ break;
+ }
+
+ case InstDB::kEncodingSimdFcmpFcmpe: {
+ const InstDB::EncodingData::SimdFcmpFcmpe& opData = InstDB::EncodingData::simdFcmpFcmpe[encodingIndex];
+
+ uint32_t sz = diff(o0.as<Reg>().type(), RegType::kARM_VecH);
+ uint32_t type = (sz - 1) & 0x3u;
+
+ if (sz > 2)
+ goto InvalidInstruction;
+
+ if (o0.as<Vec>().hasElementType())
+ goto InvalidInstruction;
+
+ opcode.reset(opData.opcode());
+ opcode.addImm(type, 22);
+
+ if (isign4 == ENC_OPS2(Reg, Reg)) {
+ if (!checkSignature(o0, o1))
+ goto InvalidInstruction;
+
+ goto EmitOp_Rn5_Rm16;
+ }
+
+ if (isign4 == ENC_OPS2(Reg, Imm)) {
+ if (o1.as<Imm>().value() != 0 || o1.as<Imm>().predicate() != 0)
+ goto InvalidInstruction;
+
+ opcode |= B(3);
+ goto EmitOp_Rn5;
+ }
+
+ break;
+ }
+
+ case InstDB::kEncodingSimdFcsel: {
+ if (isign4 == ENC_OPS4(Reg, Reg, Reg, Imm)) {
+ if (!checkSignature(o0, o1, o2))
+ goto InvalidInstruction;
+
+ uint32_t sz = diff(o0.as<Reg>().type(), RegType::kARM_VecH);
+ uint32_t type = (sz - 1) & 0x3u;
+
+ if (sz > 2 || o0.as<Vec>().hasElementType())
+ goto InvalidInstruction;
+
+ uint64_t cond = o3.as<Imm>().valueAs<uint64_t>();
+ if (cond > 0xFu)
+ goto InvalidImmediate;
+
+ opcode.reset(0b00011110001000000000110000000000);
+ opcode.addImm(type, 22);
+ opcode.addImm(condCodeToOpcodeCond(uint32_t(cond)), 12);
+ goto EmitOp_Rd0_Rn5_Rm16;
+ }
+
+ break;
+ }
+
+ case InstDB::kEncodingSimdFcvt: {
+ if (isign4 == ENC_OPS2(Reg, Reg)) {
+ uint32_t dstSz = diff(o0.as<Reg>().type(), RegType::kARM_VecH);
+ uint32_t srcSz = diff(o1.as<Reg>().type(), RegType::kARM_VecH);
+
+ if ((dstSz | srcSz) > 3)
+ goto InvalidInstruction;
+
+ if (o0.as<Vec>().hasElementType() || o1.as<Vec>().hasElementType())
+ goto InvalidInstruction;
+
+ // Table that provides 'type' and 'opc' according to the dst/src combination.
+ static const uint8_t table[] = {
+ 0xFFu, // H <- H (Invalid).
+ 0x03u, // H <- S (type=00 opc=11).
+ 0x13u, // H <- D (type=01 opc=11).
+ 0xFFu, // H <- Q (Invalid).
+ 0x30u, // S <- H (type=11 opc=00).
+ 0xFFu, // S <- S (Invalid).
+ 0x10u, // S <- D (type=01 opc=00).
+ 0xFFu, // S <- Q (Invalid).
+ 0x31u, // D <- H (type=11 opc=01).
+ 0x01u, // D <- S (type=00 opc=01).
+ 0xFFu, // D <- D (Invalid).
+ 0xFFu, // D <- Q (Invalid).
+ 0xFFu, // Q <- H (Invalid).
+ 0xFFu, // Q <- S (Invalid).
+ 0xFFu, // Q <- D (Invalid).
+ 0xFFu // Q <- Q (Invalid).
+ };
+
+ uint32_t typeOpc = table[(dstSz << 2) | srcSz];
+ opcode.reset(0b0001111000100010010000 << 10);
+ opcode.addImm(typeOpc >> 4, 22);
+ opcode.addImm(typeOpc & 15, 15);
+ goto EmitOp_Rd0_Rn5;
+ }
+
+ break;
+ }
+
+ case InstDB::kEncodingSimdFcvtLN: {
+ const InstDB::EncodingData::SimdFcvtLN& opData = InstDB::EncodingData::simdFcvtLN[encodingIndex];
+
+ if (isign4 == ENC_OPS2(Reg, Reg)) {
+ // Scalar form - only FCVTXN.
+ if (o0.as<Vec>().isVecS() && o1.as<Vec>().isVecD()) {
+ if (!opData.hasScalar())
+ goto InvalidInstruction;
+
+ if (o0.as<Vec>().hasElementType() || o1.as<Vec>().hasElementType())
+ goto InvalidInstruction;
+
+ opcode.reset(opData.scalarOp());
+ opcode |= B(22); // sz bit must be 1, the only supported combination of FCVTXN.
+ goto EmitOp_Rd0_Rn5;
+ }
+
+ opcode.reset(opData.vectorOp());
+
+ const Vec& rL = (instFlags & InstDB::kInstFlagLong) ? o0.as<Vec>() : o1.as<Vec>();
+ const Vec& rN = (instFlags & InstDB::kInstFlagLong) ? o1.as<Vec>() : o0.as<Vec>();
+
+ uint32_t q = diff(rN.type(), RegType::kARM_VecD);
+ if (uint32_t(opcode.hasQ()) != q)
+ goto InvalidInstruction;
+
+ if (rL.isVecS4() && rN.elementType() == Vec::kElementTypeH && !opData.isCvtxn()) {
+ goto EmitOp_Rd0_Rn5;
+ }
+
+ if (rL.isVecD2() && rN.elementType() == Vec::kElementTypeS) {
+ opcode |= B(22);
+ goto EmitOp_Rd0_Rn5;
+ }
+ }
+
+ break;
+ }
+
+ case InstDB::kEncodingSimdFcvtSV: {
+ const InstDB::EncodingData::SimdFcvtSV& opData = InstDB::EncodingData::simdFcvtSV[encodingIndex];
+
+ // So we can support both IntToFloat and FloatToInt conversions.
+ const Operand_& oGp = opData.isFloatToInt() ? o0 : o1;
+ const Operand_& oVec = opData.isFloatToInt() ? o1 : o0;
+
+ if (isign4 == ENC_OPS2(Reg, Reg)) {
+ if (oGp.as<Reg>().isGp() && oVec.as<Reg>().isVec()) {
+ uint32_t x = oGp.as<Reg>().isGpX();
+ uint32_t type = diff(oVec.as<Reg>().type(), RegType::kARM_VecH);
+
+ if (type > 2u)
+ goto InvalidInstruction;
+
+ type = (type - 1u) & 0x3;
+ opcode.reset(opData.generalOp());
+ opcode.addImm(type, 22);
+ opcode.addImm(x, 31);
+ goto EmitOp_Rd0_Rn5;
+ }
+
+ if (o0.as<Reg>().isVec() && o1.as<Reg>().isVec()) {
+ if (!checkSignature(o0, o1))
+ goto InvalidInstruction;
+
+ if (!pickFpOpcode(o0.as<Vec>(), opData.scalarIntOp(), InstDB::kHF_B, opData.vectorIntOp(), InstDB::kHF_B, &opcode))
+ goto InvalidInstruction;
+
+ goto EmitOp_Rd0_Rn5;
+ }
+ }
+
+ if (isign4 == ENC_OPS3(Reg, Reg, Imm) && opData.isFixedPoint()) {
+ if (o2.as<Imm>().valueAs<uint64_t>() >= 64)
+ goto InvalidInstruction;
+
+ uint32_t scale = o2.as<Imm>().valueAs<uint32_t>();
+ if (scale == 0)
+ goto InvalidInstruction;
+
+ if (oGp.as<Reg>().isGp() && oVec.as<Reg>().isVec()) {
+ uint32_t x = oGp.as<Reg>().isGpX();
+ uint32_t type = diff(oVec.as<Reg>().type(), RegType::kARM_VecH);
+
+ uint32_t scaleLimit = 32u << x;
+ if (scale > scaleLimit)
+ goto InvalidInstruction;
+
+ type = (type - 1u) & 0x3;
+ opcode.reset(opData.generalOp() ^ B(21));
+ opcode.addImm(type, 22);
+ opcode.addImm(x, 31);
+ opcode.addImm(64u - scale, 10);
+ goto EmitOp_Rd0_Rn5;
+ }
+
+ if (o0.as<Reg>().isVec() && o1.as<Reg>().isVec()) {
+ if (!checkSignature(o0, o1))
+ goto InvalidInstruction;
+
+ uint32_t sz;
+ if (!pickFpOpcode(o0.as<Vec>(), opData.scalarFpOp(), InstDB::kHF_0, opData.vectorFpOp(), InstDB::kHF_0, &opcode, &sz))
+ goto InvalidInstruction;
+
+ uint32_t scaleLimit = 16u << sz;
+ if (scale > scaleLimit)
+ goto InvalidInstruction;
+
+ uint32_t imm = Support::neg(scale) & Support::lsbMask<uint32_t>(sz + 4 + 1);
+ opcode.addImm(imm, 16);
+ goto EmitOp_Rd0_Rn5;
+ }
+ }
+
+ break;
+ }
+
+ case InstDB::kEncodingSimdFmlal: {
+ const InstDB::EncodingData::SimdFmlal& opData = InstDB::EncodingData::simdFmlal[encodingIndex];
+
+ if (isign4 == ENC_OPS3(Reg, Reg, Reg)) {
+ uint32_t q = diff(o0.as<Reg>().type(), RegType::kARM_VecD);
+ uint32_t qIsOptional = opData.optionalQ();
+
+ if (qIsOptional) {
+ // This instruction works with either 64-bit or 128-bit registers,
+ // encoded by Q bit.
+ if (q > 1)
+ goto InvalidInstruction;
+ }
+ else {
+ // This instruction requires 128-bit vector registers.
+ if (q != 1)
+ goto InvalidInstruction;
+
+ // The instruction is ehtier B (bottom) or T (top), which is part of
+ // the opcode, which uses Q bit, so we have to clear it explicitly.
+ q = 0;
+ }
+
+ if (uint32_t(o0.as<Reg>().type()) != uint32_t(o1.as<Reg>().type()) + qIsOptional ||
+ o0.as<Vec>().elementType() != opData.tA ||
+ o1.as<Vec>().elementType() != opData.tB)
+ goto InvalidInstruction;
+
+ if (!o2.as<Vec>().hasElementIndex()) {
+ if (!checkSignature(o1, o2))
+ goto InvalidInstruction;
+
+ opcode.reset(opData.vectorOp());
+ opcode.addImm(q, 30);
+ goto EmitOp_Rd0_Rn5_Rm16;
+ }
+ else {
+ if (o2.as<Vec>().elementType() != opData.tElement)
+ goto InvalidInstruction;
+
+ if (o2.as<Reg>().id() > 15)
+ goto InvalidPhysId;
+
+ uint32_t elementIndex = o2.as<Vec>().elementIndex();
+ if (elementIndex > 7u)
+ goto InvalidElementIndex;
+
+ opcode.reset(opData.elementOp());
+ opcode.addImm(q, 30);
+ opcode.addImm(elementIndex & 3u, 20);
+ opcode.addImm(elementIndex >> 2, 11);
+ goto EmitOp_Rd0_Rn5_Rm16;
+ }
+ }
+
+ break;
+ }
+
+ case InstDB::kEncodingSimdFmov: {
+ if (isign4 == ENC_OPS2(Reg, Reg)) {
+ // FMOV Gp <-> Vec opcode:
+ opcode.reset(0b00011110001001100000000000000000);
+
+ if (o0.as<Reg>().isGp() && o1.as<Reg>().isVec()) {
+ // FMOV Wd, Hn (sf=0 type=11 rmode=00 op=110)
+ // FMOV Xd, Hn (sf=1 type=11 rmode=00 op=110)
+ // FMOV Wd, Sn (sf=0 type=00 rmode=00 op=110)
+ // FMOV Xd, Dn (sf=1 type=11 rmode=00 op=110)
+ // FMOV Xd, Vn.d[1] (sf=1 type=10 rmode=01 op=110)
+ uint32_t x = o0.as<Reg>().isGpX();
+ uint32_t sz = diff(o1.as<Reg>().type(), RegType::kARM_VecH);
+
+ uint32_t type = (sz - 1) & 0x3u;
+ uint32_t rModeOp = 0b00110;
+
+ if (o1.as<Vec>().hasElementIndex()) {
+ // Special case.
+ if (!x || !o1.as<Vec>().isVecD2() || o1.as<Vec>().elementIndex() != 1)
+ goto InvalidInstruction;
+ type = 0b10;
+ rModeOp = 0b01110;
+ }
+ else {
+ // Must be scalar.
+ if (sz > 2)
+ goto InvalidInstruction;
+
+ if (o1.as<Vec>().hasElementType())
+ goto InvalidInstruction;
+
+ if (o1.as<Vec>().isVecS() && x)
+ goto InvalidInstruction;
+
+ if (o1.as<Vec>().isVecD() && !x)
+ goto InvalidInstruction;
+ }
+
+ opcode.addImm(x, 31);
+ opcode.addImm(type, 22);
+ opcode.addImm(rModeOp, 16);
+ goto EmitOp_Rd0_Rn5;
+ }
+
+ if (o0.as<Reg>().isVec() && o1.as<Reg>().isGp()) {
+ // FMOV Hd, Wn (sf=0 type=11 rmode=00 op=111)
+ // FMOV Hd, Xn (sf=1 type=11 rmode=00 op=111)
+ // FMOV Sd, Wn (sf=0 type=00 rmode=00 op=111)
+ // FMOV Dd, Xn (sf=1 type=11 rmode=00 op=111)
+ // FMOV Vd.d[1], Xn (sf=1 type=10 rmode=01 op=111)
+ uint32_t x = o1.as<Reg>().isGpX();
+ uint32_t sz = diff(o0.as<Reg>().type(), RegType::kARM_VecH);
+
+ uint32_t type = (sz - 1) & 0x3u;
+ uint32_t rModeOp = 0b00111;
+
+ if (o0.as<Vec>().hasElementIndex()) {
+ // Special case.
+ if (!x || !o0.as<Vec>().isVecD2() || o0.as<Vec>().elementIndex() != 1)
+ goto InvalidInstruction;
+ type = 0b10;
+ rModeOp = 0b01111;
+ }
+ else {
+ // Must be scalar.
+ if (sz > 2)
+ goto InvalidInstruction;
+
+ if (o0.as<Vec>().hasElementType())
+ goto InvalidInstruction;
+
+ if (o0.as<Vec>().isVecS() && x)
+ goto InvalidInstruction;
+
+ if (o0.as<Vec>().isVecD() && !x)
+ goto InvalidInstruction;
+ }
+
+ opcode.addImm(x, 31);
+ opcode.addImm(type, 22);
+ opcode.addImm(rModeOp, 16);
+ goto EmitOp_Rd0_Rn5;
+ }
+
+ if (checkSignature(o0, o1)) {
+ uint32_t sz = diff(o0.as<Reg>().type(), RegType::kARM_VecH);
+ if (sz > 2)
+ goto InvalidInstruction;
+
+ if (o0.as<Vec>().hasElementType())
+ goto InvalidInstruction;
+
+ uint32_t type = (sz - 1) & 0x3;
+ opcode.reset(0b00011110001000000100000000000000);
+ opcode.addImm(type, 22);
+ goto EmitOp_Rd0_Rn5;
+ }
+ }
+
+ if (isign4 == ENC_OPS2(Reg, Imm)) {
+ if (o0.as<Reg>().isVec()) {
+ double fpValue;
+ if (o1.as<Imm>().isDouble())
+ fpValue = o1.as<Imm>().valueAs<double>();
+ else if (o1.as<Imm>().isInt32())
+ fpValue = o1.as<Imm>().valueAs<int32_t>();
+ else
+ goto InvalidImmediate;
+
+ if (!Utils::isFP64Imm8(fpValue))
+ goto InvalidImmediate;
+
+ uint32_t imm8 = Utils::encodeFP64ToImm8(fpValue);
+ if (!o0.as<Vec>().hasElementType()) {
+ // FMOV (scalar, immediate).
+ uint32_t sz = diff(o0.as<Reg>().type(), RegType::kARM_VecH);
+ uint32_t type = (sz - 1u) & 0x3u;
+
+ if (sz > 2)
+ goto InvalidInstruction;
+
+ opcode.reset(0b00011110001000000001000000000000);
+ opcode.addImm(type, 22);
+ opcode.addImm(imm8, 13);
+ goto EmitOp_Rd0;
+ }
+ else {
+ uint32_t q = diff(o0.as<Vec>().type(), RegType::kARM_VecD);
+ uint32_t sz = o0.as<Vec>().elementType() - Vec::kElementTypeH;
+
+ if (q > 1 || sz > 2)
+ goto InvalidInstruction;
+
+ static const uint32_t szBits[3] = { B(11), B(0), B(29) };
+ opcode.reset(0b00001111000000001111010000000000);
+ opcode ^= szBits[sz];
+ opcode.addImm(q, 30);
+ opcode.addImm(imm8 >> 5, 16);
+ opcode.addImm(imm8 & 31, 5);
+ goto EmitOp_Rd0;
+ }
+ }
+ }
+
+ break;
+ }
+
+ case InstDB::kEncodingFSimdPair: {
+ const InstDB::EncodingData::FSimdPair& opData = InstDB::EncodingData::fSimdPair[encodingIndex];
+
+ if (isign4 == ENC_OPS2(Reg, Reg)) {
+ // This operation is only defined for:
+ // hD, vS.2h (16-bit)
+ // sD, vS.2s (32-bit)
+ // dD, vS.2d (64-bit)
+ uint32_t sz = diff(o0.as<Reg>().type(), RegType::kARM_VecH);
+ if (sz > 2)
+ goto InvalidInstruction;
+
+ static const uint32_t szSignatures[3] = {
+ VecS::kSignature | (Vec::kSignatureElementH),
+ VecD::kSignature | (Vec::kSignatureElementS),
+ VecV::kSignature | (Vec::kSignatureElementD)
+ };
+
+ if (o1.signature() != szSignatures[sz])
+ goto InvalidInstruction;
+
+ static const uint32_t szBits[] = { B(29), 0, B(22) };
+ opcode.reset(opData.scalarOp());
+ opcode ^= szBits[sz];
+ goto EmitOp_Rd0_Rn5;
+ }
+
+ if (isign4 == ENC_OPS3(Reg, Reg, Reg)) {
+ if (!checkSignature(o0, o1, o2))
+ goto InvalidInstruction;
+
+ uint32_t q = diff(o0.as<Reg>().type(), RegType::kARM_VecD);
+ if (q > 1)
+ goto InvalidInstruction;
+
+ uint32_t sz = o0.as<Vec>().elementType() - Vec::kElementTypeH;
+ if (sz > 2)
+ goto InvalidInstruction;
+
+ static const uint32_t szBits[3] = { B(22) | B(21) | B(15) | B(14), 0, B(22) };
+ opcode.reset(opData.vectorOp());
+ opcode ^= szBits[sz];
+ opcode.addImm(q, 30);
+ goto EmitOp_Rd0_Rn5_Rm16;
+ }
+
+ break;
+ }
+
+ // ------------------------------------------------------------------------
+ // [ISimd - Instructions]
+ // ------------------------------------------------------------------------
+
+ case InstDB::kEncodingISimdSV: {
+ const InstDB::EncodingData::ISimdSV& opData = InstDB::EncodingData::iSimdSV[encodingIndex];
+
+ if (isign4 == ENC_OPS2(Reg, Reg)) {
+ // The first destination operand is scalar, which matches element-type of source vectors.
+ uint32_t L = (instFlags & InstDB::kInstFlagLong) != 0;
+ if (diff(o0.as<Vec>().type(), RegType::kARM_VecB) != o1.as<Vec>().elementType() - Vec::kElementTypeB + L)
+ goto InvalidInstruction;
+
+ SizeOp sizeOp = armElementTypeToSizeOp(opData.vecOpType, o1.as<Reg>().type(), o1.as<Vec>().elementType());
+ if (!sizeOp.isValid())
+ goto InvalidInstruction;
+
+ opcode.reset(opData.opcode());
+ opcode.addImm(sizeOp.q(), 30);
+ opcode.addImm(sizeOp.size(), 22);
+ goto EmitOp_Rd0_Rn5;
+ }
+
+ break;
+ }
+
+ case InstDB::kEncodingISimdVV: {
+ const InstDB::EncodingData::ISimdVV& opData = InstDB::EncodingData::iSimdVV[encodingIndex];
+
+ if (isign4 == ENC_OPS2(Reg, Reg)) {
+ const Operand_& sop = significantSimdOp(o0, o1, instFlags);
+ if (!matchSignature(o0, o1, instFlags))
+ goto InvalidInstruction;
+
+ SizeOp sizeOp = armElementTypeToSizeOp(opData.vecOpType, sop.as<Reg>().type(), sop.as<Vec>().elementType());
+ if (!sizeOp.isValid())
+ goto InvalidInstruction;
+
+ opcode.reset(opData.opcode());
+ opcode.addImm(sizeOp.qs(), 30);
+ opcode.addImm(sizeOp.scalar(), 28);
+ opcode.addImm(sizeOp.size(), 22);
+ goto EmitOp_Rd0_Rn5;
+ }
+
+ break;
+ }
+
+ case InstDB::kEncodingISimdVVx: {
+ const InstDB::EncodingData::ISimdVVx& opData = InstDB::EncodingData::iSimdVVx[encodingIndex];
+
+ if (isign4 == ENC_OPS2(Reg, Reg)) {
+ if (o0.signature() != opData.op0Signature ||
+ o1.signature() != opData.op1Signature)
+ goto InvalidInstruction;
+
+ opcode.reset(opData.opcode());
+ goto EmitOp_Rd0_Rn5;
+ }
+
+ break;
+ }
+
+ case InstDB::kEncodingISimdVVV: {
+ const InstDB::EncodingData::ISimdVVV& opData = InstDB::EncodingData::iSimdVVV[encodingIndex];
+
+ if (isign4 == ENC_OPS3(Reg, Reg, Reg)) {
+ const Operand_& sop = significantSimdOp(o0, o1, instFlags);
+ if (!matchSignature(o0, o1, o2, instFlags))
+ goto InvalidInstruction;
+
+ SizeOp sizeOp = armElementTypeToSizeOp(opData.vecOpType, sop.as<Reg>().type(), sop.as<Vec>().elementType());
+ if (!sizeOp.isValid())
+ goto InvalidInstruction;
+
+ opcode.reset(opData.opcode());
+ opcode.addImm(sizeOp.qs(), 30);
+ opcode.addImm(sizeOp.scalar(), 28);
+ opcode.addImm(sizeOp.size(), 22);
+ goto EmitOp_Rd0_Rn5_Rm16;
+ }
+
+ break;
+ }
+
+ case InstDB::kEncodingISimdVVVx: {
+ const InstDB::EncodingData::ISimdVVVx& opData = InstDB::EncodingData::iSimdVVVx[encodingIndex];
+
+ if (isign4 == ENC_OPS3(Reg, Reg, Reg)) {
+ if (o0.signature() != opData.op0Signature ||
+ o1.signature() != opData.op1Signature ||
+ o2.signature() != opData.op2Signature)
+ goto InvalidInstruction;
+
+ opcode.reset(opData.opcode());
+ goto EmitOp_Rd0_Rn5_Rm16;
+ }
+
+ break;
+ }
+
+ case InstDB::kEncodingISimdWWV: {
+ // Special case for wide add/sub [s|b][add|sub][w]{2}.
+ const InstDB::EncodingData::ISimdWWV& opData = InstDB::EncodingData::iSimdWWV[encodingIndex];
+
+ if (isign4 == ENC_OPS3(Reg, Reg, Reg)) {
+ SizeOp sizeOp = armElementTypeToSizeOp(opData.vecOpType, o2.as<Reg>().type(), o2.as<Vec>().elementType());
+ if (!sizeOp.isValid())
+ goto InvalidInstruction;
+
+ if (!checkSignature(o0, o1) || !o0.as<Reg>().isVecV() || o0.as<Vec>().elementType() != o2.as<Vec>().elementType() + 1)
+ goto InvalidInstruction;
+
+ opcode.reset(opData.opcode());
+ opcode.addImm(sizeOp.qs(), 30);
+ opcode.addImm(sizeOp.scalar(), 28);
+ opcode.addImm(sizeOp.size(), 22);
+ goto EmitOp_Rd0_Rn5_Rm16;
+ }
+
+ break;
+ }
+
+ case InstDB::kEncodingISimdVVVe: {
+ const InstDB::EncodingData::ISimdVVVe& opData = InstDB::EncodingData::iSimdVVVe[encodingIndex];
+
+ if (isign4 == ENC_OPS3(Reg, Reg, Reg)) {
+ const Operand_& sop = significantSimdOp(o0, o1, instFlags);
+ if (!matchSignature(o0, o1, instFlags))
+ goto InvalidInstruction;
+
+ if (!o2.as<Vec>().hasElementIndex()) {
+ SizeOp sizeOp = armElementTypeToSizeOp(opData.regularVecType, sop.as<Reg>().type(), sop.as<Vec>().elementType());
+ if (!sizeOp.isValid())
+ goto InvalidInstruction;
+
+ if (!checkSignature(o1, o2))
+ goto InvalidInstruction;
+
+ opcode.reset(uint32_t(opData.regularOp) << 10);
+ opcode.addImm(sizeOp.qs(), 30);
+ opcode.addImm(sizeOp.scalar(), 28);
+ opcode.addImm(sizeOp.size(), 22);
+ goto EmitOp_Rd0_Rn5_Rm16;
+ }
+ else {
+ SizeOp sizeOp = armElementTypeToSizeOp(opData.elementVecType, sop.as<Reg>().type(), sop.as<Vec>().elementType());
+ if (!sizeOp.isValid())
+ goto InvalidInstruction;
+
+ uint32_t elementIndex = o2.as<Vec>().elementIndex();
+ LMHImm lmh;
+
+ if (!encodeLMH(sizeOp.size(), elementIndex, &lmh))
+ goto InvalidElementIndex;
+
+ if (o2.as<Reg>().id() > lmh.maxRmId)
+ goto InvalidPhysId;
+
+ opcode.reset(uint32_t(opData.elementOp) << 10);
+ opcode.addImm(sizeOp.q(), 30);
+ opcode.addImm(sizeOp.size(), 22);
+ opcode.addImm(lmh.lm, 20);
+ opcode.addImm(lmh.h, 11);
+ goto EmitOp_Rd0_Rn5_Rm16;
+ }
+ }
+
+ break;
+ }
+
+ case InstDB::kEncodingISimdVVVI: {
+ const InstDB::EncodingData::ISimdVVVI& opData = InstDB::EncodingData::iSimdVVVI[encodingIndex];
+
+ if (isign4 == ENC_OPS4(Reg, Reg, Reg, Imm)) {
+ const Operand_& sop = significantSimdOp(o0, o1, instFlags);
+ if (!matchSignature(o0, o1, o2, instFlags))
+ goto InvalidInstruction;
+
+ SizeOp sizeOp = armElementTypeToSizeOp(opData.vecOpType, sop.as<Reg>().type(), sop.as<Vec>().elementType());
+ if (!sizeOp.isValid())
+ goto InvalidInstruction;
+
+ uint64_t immValue = o3.as<Imm>().valueAs<uint64_t>();
+ uint32_t immSize = opData.immSize;
+
+ if (opData.imm64HasOneBitLess && !sizeOp.q())
+ immSize--;
+
+ uint32_t immMax = 1u << immSize;
+ if (immValue >= immMax)
+ goto InvalidImmediate;
+
+ opcode.reset(opData.opcode());
+ opcode.addImm(sizeOp.qs(), 30);
+ opcode.addImm(sizeOp.scalar(), 28);
+ opcode.addImm(sizeOp.size(), 22);
+ opcode.addImm(immValue, opData.immShift);
+ goto EmitOp_Rd0_Rn5_Rm16;
+ }
+
+ break;
+ }
+
+ case InstDB::kEncodingISimdVVVV: {
+ const InstDB::EncodingData::ISimdVVVV& opData = InstDB::EncodingData::iSimdVVVV[encodingIndex];
+
+ if (isign4 == ENC_OPS4(Reg, Reg, Reg, Reg)) {
+ const Operand_& sop = significantSimdOp(o0, o1, instFlags);
+ if (!matchSignature(o0, o1, o2, o3, instFlags))
+ goto InvalidInstruction;
+
+ SizeOp sizeOp = armElementTypeToSizeOp(opData.vecOpType, sop.as<Reg>().type(), sop.as<Vec>().elementType());
+ if (!sizeOp.isValid())
+ goto InvalidInstruction;
+
+ opcode.reset(uint32_t(opData.opcode) << 10);
+ opcode.addImm(sizeOp.qs(), 30);
+ opcode.addImm(sizeOp.scalar(), 28);
+ opcode.addImm(sizeOp.size(), 22);
+ goto EmitOp_Rd0_Rn5_Rm16_Ra10;
+ }
+
+ break;
+ }
+
+ case InstDB::kEncodingISimdVVVVx: {
+ const InstDB::EncodingData::ISimdVVVVx& opData = InstDB::EncodingData::iSimdVVVVx[encodingIndex];
+
+ if (isign4 == ENC_OPS4(Reg, Reg, Reg, Reg)) {
+ if (o0.signature() != opData.op0Signature ||
+ o1.signature() != opData.op1Signature ||
+ o2.signature() != opData.op2Signature ||
+ o3.signature() != opData.op3Signature)
+ goto InvalidInstruction;
+
+ opcode.reset(uint32_t(opData.opcode) << 10);
+ goto EmitOp_Rd0_Rn5_Rm16_Ra10;
+ }
+
+ break;
+ }
+
+
+ case InstDB::kEncodingISimdPair: {
+ const InstDB::EncodingData::ISimdPair& opData = InstDB::EncodingData::iSimdPair[encodingIndex];
+
+ if (isign4 == ENC_OPS2(Reg, Reg) && opData.opcode2) {
+ if (o0.as<Vec>().isVecD1() && o1.as<Vec>().isVecD2()) {
+ opcode.reset(uint32_t(opData.opcode2) << 10);
+ opcode.addImm(0x3, 22); // size.
+ goto EmitOp_Rd0_Rn5;
+ }
+ }
+
+ if (isign4 == ENC_OPS3(Reg, Reg, Reg)) {
+ if (!matchSignature(o0, o1, o2, instFlags))
+ goto InvalidInstruction;
+
+ SizeOp sizeOp = armElementTypeToSizeOp(opData.opType3, o0.as<Reg>().type(), o0.as<Vec>().elementType());
+ if (!sizeOp.isValid())
+ goto InvalidInstruction;
+
+ opcode.reset(uint32_t(opData.opcode3) << 10);
+ opcode.addImm(sizeOp.qs(), 30);
+ opcode.addImm(sizeOp.scalar(), 28);
+ opcode.addImm(sizeOp.size(), 22);
+ goto EmitOp_Rd0_Rn5_Rm16;
+ }
+
+ break;
+ }
+
+ case InstDB::kEncodingSimdBicOrr: {
+ const InstDB::EncodingData::SimdBicOrr& opData = InstDB::EncodingData::simdBicOrr[encodingIndex];
+
+ if (isign4 == ENC_OPS3(Reg, Reg, Reg)) {
+ if (!matchSignature(o0, o1, o2, instFlags))
+ goto InvalidInstruction;
+
+ SizeOp sizeOp = armElementTypeToSizeOp(InstDB::kVO_V_B, o0.as<Reg>().type(), o0.as<Vec>().elementType());
+ if (!sizeOp.isValid())
+ goto InvalidInstruction;
+
+ opcode.reset(uint32_t(opData.registerOp) << 10);
+ opcode.addImm(sizeOp.q(), 30);
+ goto EmitOp_Rd0_Rn5_Rm16;
+ }
+
+ if (isign4 == ENC_OPS2(Reg, Imm) || isign4 == ENC_OPS3(Reg, Imm, Imm)) {
+ SizeOp sizeOp = armElementTypeToSizeOp(InstDB::kVO_V_HS, o0.as<Reg>().type(), o0.as<Vec>().elementType());
+ if (!sizeOp.isValid())
+ goto InvalidInstruction;
+
+ if (o1.as<Imm>().valueAs<uint64_t>() > 0xFFFFFFFFu)
+ goto InvalidImmediate;
+
+ uint32_t imm = o1.as<Imm>().valueAs<uint32_t>();
+ uint32_t shift = 0;
+ uint32_t maxShift = (8u << sizeOp.size()) - 8u;
+
+ if (o2.isImm()) {
+ if (o2.as<Imm>().predicate() != uint32_t(ShiftOp::kLSL))
+ goto InvalidImmediate;
+
+ if (imm > 0xFFu || o2.as<Imm>().valueAs<uint64_t>() > maxShift)
+ goto InvalidImmediate;
+
+ shift = o2.as<Imm>().valueAs<uint32_t>();
+ if ((shift & 0x7u) != 0u)
+ goto InvalidImmediate;
+ }
+ else if (imm) {
+ shift = Support::ctz(imm) & 0x7u;
+ imm >>= shift;
+
+ if (imm > 0xFFu || shift > maxShift)
+ goto InvalidImmediate;
+ }
+
+ uint32_t cmode = 0x1u | ((shift / 8u) << 1);
+ if (sizeOp.size() == 1)
+ cmode |= B(3);
+
+ // The immediate value is split into ABC and DEFGH parts.
+ uint32_t abc = (imm >> 5) & 0x7u;
+ uint32_t defgh = imm & 0x1Fu;
+
+ opcode.reset(uint32_t(opData.immediateOp) << 10);
+ opcode.addImm(sizeOp.q(), 30);
+ opcode.addImm(abc, 16);
+ opcode.addImm(cmode, 12);
+ opcode.addImm(defgh, 5);
+ goto EmitOp_Rd0;
+ }
+
+ break;
+ }
+
+ case InstDB::kEncodingSimdCmp: {
+ const InstDB::EncodingData::SimdCmp& opData = InstDB::EncodingData::simdCmp[encodingIndex];
+
+ if (isign4 == ENC_OPS3(Reg, Reg, Reg) && opData.regOp) {
+ if (!matchSignature(o0, o1, o2, instFlags))
+ goto InvalidInstruction;
+
+ SizeOp sizeOp = armElementTypeToSizeOp(opData.vecOpType, o0.as<Reg>().type(), o0.as<Vec>().elementType());
+ if (!sizeOp.isValid())
+ goto InvalidInstruction;
+
+ opcode.reset(uint32_t(opData.regOp) << 10);
+ opcode.addImm(sizeOp.qs(), 30);
+ opcode.addImm(sizeOp.scalar(), 28);
+ opcode.addImm(sizeOp.size(), 22);
+ goto EmitOp_Rd0_Rn5_Rm16;
+ }
+
+ if (isign4 == ENC_OPS3(Reg, Reg, Imm) && opData.zeroOp) {
+ if (!matchSignature(o0, o1, instFlags))
+ goto InvalidInstruction;
+
+ if (o2.as<Imm>().value() != 0)
+ goto InvalidImmediate;
+
+ SizeOp sizeOp = armElementTypeToSizeOp(opData.vecOpType, o0.as<Reg>().type(), o0.as<Vec>().elementType());
+ if (!sizeOp.isValid())
+ goto InvalidInstruction;
+
+ opcode.reset(uint32_t(opData.zeroOp) << 10);
+ opcode.addImm(sizeOp.qs(), 30);
+ opcode.addImm(sizeOp.scalar(), 28);
+ opcode.addImm(sizeOp.size(), 22);
+ goto EmitOp_Rd0_Rn5;
+ }
+
+ break;
+ }
+
+ case InstDB::kEncodingSimdDot: {
+ const InstDB::EncodingData::SimdDot& opData = InstDB::EncodingData::simdDot[encodingIndex];
+
+ if (isign4 == ENC_OPS3(Reg, Reg, Reg)) {
+ uint32_t q = diff(o0.as<Reg>().type(), RegType::kARM_VecD);
+ uint32_t size = 2;
+
+ if (q > 1u)
+ goto InvalidInstruction;
+
+ if (!o2.as<Vec>().hasElementIndex()) {
+ if (!opData.vectorOp)
+ goto InvalidInstruction;
+
+ if (o0.as<Reg>().type() != o1.as<Reg>().type() || o1.as<Reg>().type() != o2.as<Reg>().type())
+ goto InvalidInstruction;
+
+ if (o0.as<Vec>().elementType() != opData.tA ||
+ o1.as<Vec>().elementType() != opData.tB ||
+ o2.as<Vec>().elementType() != opData.tB)
+ goto InvalidInstruction;
+
+ opcode.reset(uint32_t(opData.vectorOp) << 10);
+ opcode.addImm(q, 30);
+ goto EmitOp_Rd0_Rn5_Rm16;
+ }
+ else {
+ if (!opData.elementOp)
+ goto InvalidInstruction;
+
+ if (o0.as<Reg>().type() != o1.as<Reg>().type() || !o2.as<Reg>().isVecV())
+ goto InvalidInstruction;
+
+ if (o0.as<Vec>().elementType() != opData.tA ||
+ o1.as<Vec>().elementType() != opData.tB ||
+ o2.as<Vec>().elementType() != opData.tElement)
+ goto InvalidInstruction;
+
+ uint32_t elementIndex = o2.as<Vec>().elementIndex();
+ LMHImm lmh;
+
+ if (!encodeLMH(size, elementIndex, &lmh))
+ goto InvalidElementIndex;
+
+ if (o2.as<Reg>().id() > lmh.maxRmId)
+ goto InvalidPhysId;
+
+ opcode.reset(uint32_t(opData.elementOp) << 10);
+ opcode.addImm(q, 30);
+ opcode.addImm(lmh.lm, 20);
+ opcode.addImm(lmh.h, 11);
+ goto EmitOp_Rd0_Rn5_Rm16;
+ }
+ }
+
+ break;
+ }
+
+ case InstDB::kEncodingSimdDup: SimdDup: {
+ if (isign4 == ENC_OPS2(Reg, Reg)) {
+ // Truth table of valid encodings of `Q:1|ElementType:3`
+ uint32_t kValidEncodings = B(Vec::kElementTypeB + 0) |
+ B(Vec::kElementTypeH + 0) |
+ B(Vec::kElementTypeS + 0) |
+ B(Vec::kElementTypeB + 8) |
+ B(Vec::kElementTypeH + 8) |
+ B(Vec::kElementTypeS + 8) |
+ B(Vec::kElementTypeD + 8) ;
+
+ uint32_t q = diff(o0.as<Reg>().type(), RegType::kARM_VecD);
+
+ if (o1.as<Reg>().isGp()) {
+ // DUP - Vec (scalar|vector) <- GP register.
+ //
+ // NOTE: This is only scalar for `dup d, x` case, otherwise the value
+ // would be duplicated across all vector elements (1, 2, 4, 8, or 16).
+ uint32_t elementType = o0.as<Vec>().elementType();
+ if (q > 1 || !Support::bitTest(kValidEncodings, (q << 3) | elementType))
+ goto InvalidInstruction;
+
+ uint32_t lsbIndex = elementType - 1u;
+ uint32_t imm5 = 1u << lsbIndex;
+
+ opcode.reset(0b0000111000000000000011 << 10);
+ opcode.addImm(q, 30);
+ opcode.addImm(imm5, 16);
+ goto EmitOp_Rd0_Rn5;
+ }
+
+ if (!o1.as<Reg>().isVec() || !o1.as<Vec>().hasElementIndex())
+ goto InvalidInstruction;
+
+ uint32_t dstIndex = o1.as<Vec>().elementIndex();
+ if (!o0.as<Vec>().hasElementType()) {
+ // DUP - Vec (scalar) <- Vec[N].
+ uint32_t lsbIndex = diff(o0.as<Reg>().type(), RegType::kARM_VecB);
+
+ if (lsbIndex != o1.as<Vec>().elementType() - Vec::kElementTypeB || lsbIndex > 3)
+ goto InvalidInstruction;
+
+ uint32_t imm5 = ((dstIndex << 1) | 1u) << lsbIndex;
+ if (imm5 > 31)
+ goto InvalidElementIndex;
+
+ opcode.reset(0b0101111000000000000001 << 10);
+ opcode.addImm(imm5, 16);
+ goto EmitOp_Rd0_Rn5;
+ }
+ else {
+ // DUP - Vec (all) <- Vec[N].
+ uint32_t elementType = o0.as<Vec>().elementType();
+ if (q > 1 || !Support::bitTest(kValidEncodings, (q << 3) | elementType))
+ goto InvalidInstruction;
+
+ uint32_t lsbIndex = elementType - 1u;
+ uint32_t imm5 = ((dstIndex << 1) | 1u) << lsbIndex;
+
+ if (imm5 > 31)
+ goto InvalidElementIndex;
+
+ opcode.reset(0b0000111000000000000001 << 10);
+ opcode.addImm(q, 30);
+ opcode.addImm(imm5, 16);
+ goto EmitOp_Rd0_Rn5;
+ }
+ }
+
+ break;
+ }
+
+ case InstDB::kEncodingSimdIns: SimdIns: {
+ if (isign4 == ENC_OPS2(Reg, Reg) && o0.as<Reg>().isVecV()) {
+ if (!o0.as<Vec>().hasElementIndex())
+ goto InvalidInstruction;
+
+ uint32_t elementType = o0.as<Vec>().elementType();
+ uint32_t dstIndex = o0.as<Vec>().elementIndex();
+ uint32_t lsbIndex = elementType - 1u;
+
+ uint32_t imm5 = ((dstIndex << 1) | 1u) << lsbIndex;
+ if (imm5 > 31)
+ goto InvalidElementIndex;
+
+ if (o1.as<Reg>().isGp()) {
+ // INS - Vec[N] <- GP register.
+ opcode.reset(0b0100111000000000000111 << 10);
+ opcode.addImm(imm5, 16);
+ goto EmitOp_Rd0_Rn5;
+ }
+ else if (o1.as<Reg>().isVecV() && o1.as<Vec>().hasElementIndex()) {
+ // INS - Vec[N] <- Vec[M].
+ if (o0.as<Vec>().elementType() != o1.as<Vec>().elementType())
+ goto InvalidInstruction;
+
+ uint32_t srcIndex = o1.as<Vec>().elementIndex();
+ if (o0.as<Reg>().type() != o1.as<Reg>().type())
+ goto InvalidInstruction;
+
+ uint32_t imm4 = srcIndex << lsbIndex;
+ if (imm4 > 15)
+ goto InvalidElementIndex;
+
+ opcode.reset(0b0110111000000000000001 << 10);
+ opcode.addImm(imm5, 16);
+ opcode.addImm(imm4, 11);
+ goto EmitOp_Rd0_Rn5;
+ }
+ }
+
+ break;
+ }
+
+ case InstDB::kEncodingSimdMov: {
+ if (isign4 == ENC_OPS2(Reg, Reg)) {
+ if (o0.as<Reg>().isVec() && o1.as<Reg>().isVec()) {
+ // INS v.x[index], v.x[index].
+ if (o0.as<Vec>().hasElementIndex() && o1.as<Vec>().hasElementIndex())
+ goto SimdIns;
+
+ // DUP {b|h|s|d}, v.{b|h|s|d}[index].
+ if (o1.as<Vec>().hasElementIndex())
+ goto SimdDup;
+
+ if (!checkSignature(o0, o1))
+ goto InvalidInstruction;
+
+ // ORR Vd, Vn, Vm
+ uint32_t q = diff(o0.as<Reg>().type(), RegType::kARM_VecD);
+ if (q > 1)
+ goto InvalidInstruction;
+
+ opcode.reset(0b0000111010100000000111 << 10);
+ opcode.addImm(q, 30);
+ opcode.addReg(o1, 16); // Vn == Vm.
+ goto EmitOp_Rd0_Rn5;
+ }
+
+ if (o0.as<Reg>().isVec() && o1.as<Reg>().isGp()) {
+ // INS v.x[index], Rn.
+ if (o0.as<Vec>().hasElementIndex())
+ goto SimdIns;
+
+ goto InvalidInstruction;
+ }
+
+ if (o0.as<Reg>().isGp() && o1.as<Reg>().isVec()) {
+ // UMOV Rd, V.{s|d}[index].
+ encodingIndex = 1;
+ goto SimdUmov;
+ }
+ }
+
+ break;
+ }
+
+ case InstDB::kEncodingSimdMoviMvni: {
+ const InstDB::EncodingData::SimdMoviMvni& opData = InstDB::EncodingData::simdMoviMvni[encodingIndex];
+
+ if (isign4 == ENC_OPS2(Reg, Imm) || isign4 == ENC_OPS3(Reg, Imm, Imm)) {
+ SizeOp sizeOp = armElementTypeToSizeOp(InstDB::kVO_V_Any, o0.as<Reg>().type(), o0.as<Vec>().elementType());
+ if (!sizeOp.isValid())
+ goto InvalidInstruction;
+
+ uint64_t imm64 = o1.as<Imm>().valueAs<uint64_t>();
+ uint32_t imm8 = 0;
+ uint32_t cmode = 0;
+ uint32_t inverted = opData.inverted;
+ uint32_t op = 0;
+ uint32_t shift = 0;
+ uint32_t shiftOp = uint32_t(ShiftOp::kLSL);
+
+ if (sizeOp.size() == 3u) {
+ // The second immediate should not be present, however, we accept
+ // an immediate value of zero as some user code may still pass it.
+ if (o2.isImm() && o0.as<Imm>().value() != 0)
+ goto InvalidImmediate;
+
+ if (Utils::isByteMaskImm8(imm64)) {
+ imm8 = encodeImm64ByteMaskToImm8(imm64);
+ }
+ else {
+ // Change from D to S and from 64-bit imm to 32-bit imm if this
+ // is not a byte-mask pattern.
+ if ((imm64 >> 32) == (imm64 & 0xFFFFFFFFu)) {
+ imm64 &= 0xFFFFFFFFu;
+ sizeOp.decrementSize();
+ }
+ else {
+ goto InvalidImmediate;
+ }
+ }
+ }
+
+ if (sizeOp.size() < 3u) {
+ if (imm64 > 0xFFFFFFFFu)
+ goto InvalidImmediate;
+ imm8 = uint32_t(imm64);
+
+ if (sizeOp.size() == 2) {
+ if ((imm8 >> 16) == (imm8 & 0xFFFFu)) {
+ imm8 >>= 16;
+ sizeOp.decrementSize();
+ }
+ }
+
+ if (sizeOp.size() == 1) {
+ if (imm8 > 0xFFFFu)
+ goto InvalidImmediate;
+
+ if ((imm8 >> 8) == (imm8 & 0xFFu)) {
+ imm8 >>= 8;
+ sizeOp.decrementSize();
+ }
+ }
+
+ uint32_t maxShift = (8u << sizeOp.size()) - 8u;
+ if (o2.isImm()) {
+ if (imm8 > 0xFFu || o2.as<Imm>().valueAs<uint64_t>() > maxShift)
+ goto InvalidImmediate;
+
+ shift = o2.as<Imm>().valueAs<uint32_t>();
+ shiftOp = o2.as<Imm>().predicate();
+ }
+ else if (imm8) {
+ shift = Support::ctz(imm8) & ~0x7u;
+ imm8 >>= shift;
+
+ if (imm8 > 0xFFu || shift > maxShift)
+ goto InvalidImmediate;
+ }
+
+ if ((shift & 0x7u) != 0u)
+ goto InvalidImmediate;
+ }
+
+ shift /= 8u;
+
+ switch (sizeOp.size()) {
+ case 0:
+ if (shiftOp != uint32_t(ShiftOp::kLSL))
+ goto InvalidImmediate;
+
+ if (inverted) {
+ imm8 = ~imm8 & 0xFFu;
+ inverted = 0;
+ }
+
+ cmode = B(3) | B(2) | B(1);
+ break;
+
+ case 1:
+ if (shiftOp != uint32_t(ShiftOp::kLSL))
+ goto InvalidImmediate;
+
+ cmode = B(3) | (shift << 1);
+ op = inverted;
+ break;
+
+ case 2:
+ if (shiftOp == uint32_t(ShiftOp::kLSL)) {
+ cmode = shift << 1;
+ }
+ else if (shiftOp == uint32_t(ShiftOp::kMSL)) {
+ if (shift == 0 || shift > 2)
+ goto InvalidImmediate;
+ cmode = B(3) | B(2) | (shift - 1u);
+ }
+ else {
+ goto InvalidImmediate;
+ }
+
+ op = inverted;
+ break;
+
+ case 3:
+ if (inverted) {
+ imm8 = ~imm8 & 0xFFu;
+ inverted = 0;
+ }
+
+ op = 1;
+ cmode = B(3) | B(2) | B(1);
+ break;
+ }
+
+ // The immediate value is split into ABC and DEFGH parts.
+ uint32_t abc = (imm8 >> 5) & 0x7u;
+ uint32_t defgh = imm8 & 0x1Fu;
+
+ opcode.reset(uint32_t(opData.opcode) << 10);
+ opcode.addImm(sizeOp.q(), 30);
+ opcode.addImm(op, 29);
+ opcode.addImm(abc, 16);
+ opcode.addImm(cmode, 12);
+ opcode.addImm(defgh, 5);
+ goto EmitOp_Rd0;
+ }
+
+ break;
+ }
+
+ case InstDB::kEncodingSimdShift: {
+ const InstDB::EncodingData::SimdShift& opData = InstDB::EncodingData::simdShift[encodingIndex];
+
+ const Operand_& sop = significantSimdOp(o0, o1, instFlags);
+ SizeOp sizeOp = armElementTypeToSizeOp(opData.vecOpType, sop.as<Reg>().type(), sop.as<Vec>().elementType());
+
+ if (!sizeOp.isValid())
+ goto InvalidInstruction;
+
+ if (isign4 == ENC_OPS3(Reg, Reg, Imm) && opData.immediateOp) {
+ if (!matchSignature(o0, o1, instFlags))
+ goto InvalidInstruction;
+
+ if (o2.as<Imm>().valueAs<uint64_t>() > 63)
+ goto InvalidImmediate;
+
+ uint32_t lsbShift = sizeOp.size() + 3u;
+ uint32_t lsbMask = (1u << lsbShift) - 1u;
+ uint32_t imm = o2.as<Imm>().valueAs<uint32_t>();
+
+ // Some instructions use IMM and some X - IMM, so negate if required.
+ if (opData.invertedImm) {
+ if (imm == 0 || imm > (1u << lsbShift))
+ goto InvalidImmediate;
+ imm = Support::neg(imm) & lsbMask;
+ }
+
+ if (imm > lsbMask)
+ goto InvalidImmediate;
+ imm |= (1u << lsbShift);
+
+ opcode.reset(uint32_t(opData.immediateOp) << 10);
+ opcode.addImm(sizeOp.qs(), 30);
+ opcode.addImm(sizeOp.scalar(), 28);
+ opcode.addImm(imm, 16);
+ goto EmitOp_Rd0_Rn5;
+ }
+
+ if (isign4 == ENC_OPS3(Reg, Reg, Reg) && opData.registerOp) {
+ if (!matchSignature(o0, o1, o2, instFlags))
+ goto InvalidInstruction;
+
+ opcode.reset(uint32_t(opData.registerOp) << 10);
+ opcode.addImm(sizeOp.qs(), 30);
+ opcode.addImm(sizeOp.scalar(), 28);
+ opcode.addImm(sizeOp.size(), 22);
+ goto EmitOp_Rd0_Rn5_Rm16;
+ }
+
+ break;
+ }
+
+ case InstDB::kEncodingSimdShiftES: {
+ const InstDB::EncodingData::SimdShiftES& opData = InstDB::EncodingData::simdShiftES[encodingIndex];
+
+ if (isign4 == ENC_OPS3(Reg, Reg, Imm)) {
+ SizeOp sizeOp = armElementTypeToSizeOp(opData.vecOpType, o1.as<Reg>().type(), o1.as<Vec>().elementType());
+ if (!sizeOp.isValid())
+ goto InvalidInstruction;
+
+ if (!matchSignature(o0, o1, instFlags))
+ goto InvalidInstruction;
+
+ // The immediate value must match the element size.
+ uint64_t shift = o2.as<Imm>().valueAs<uint64_t>();
+ uint32_t shiftOp = o2.as<Imm>().predicate();
+
+ if (shift != (8u << sizeOp.size()) || shiftOp != uint32_t(ShiftOp::kLSL))
+ goto InvalidImmediate;
+
+ opcode.reset(uint32_t(opData.opcode) << 10);
+ opcode.addImm(sizeOp.q(), 30);
+ opcode.addImm(sizeOp.size(), 22);
+ goto EmitOp_Rd0_Rn5;
+ }
+
+ break;
+ }
+
+ case InstDB::kEncodingSimdSm3tt: {
+ const InstDB::EncodingData::SimdSm3tt& opData = InstDB::EncodingData::simdSm3tt[encodingIndex];
+
+ if (isign4 == ENC_OPS3(Reg, Reg, Reg)) {
+ if (o0.as<Vec>().isVecS4() && o1.as<Vec>().isVecS4() && o2.as<Vec>().isVecS4() && o2.as<Vec>().hasElementIndex()) {
+ uint32_t imm2 = o2.as<Vec>().elementIndex();
+ if (imm2 > 3)
+ goto InvalidElementIndex;
+
+ opcode.reset(uint32_t(opData.opcode) << 10);
+ opcode.addImm(imm2, 12);
+ goto EmitOp_Rd0_Rn5_Rm16;
+ }
+ }
+
+ break;
+ }
+
+
+ case InstDB::kEncodingSimdSmovUmov: SimdUmov: {
+ const InstDB::EncodingData::SimdSmovUmov& opData = InstDB::EncodingData::simdSmovUmov[encodingIndex];
+
+ if (isign4 == ENC_OPS2(Reg, Reg) && o0.as<Reg>().isGp() && o1.as<Reg>().isVec()) {
+ SizeOp sizeOp = armElementTypeToSizeOp(opData.vecOpType, o1.as<Reg>().type(), o1.as<Vec>().elementType());
+ if (!sizeOp.isValid())
+ goto InvalidInstruction;
+
+ if (!o1.as<Vec>().hasElementIndex())
+ goto InvalidInstruction;
+
+ uint32_t x = o0.as<Gp>().isGpX();
+ uint32_t gpMustBeX = uint32_t(sizeOp.size() >= 3u - opData.isSigned);
+
+ if (opData.isSigned) {
+ if (gpMustBeX && !x)
+ goto InvalidInstruction;
+ }
+ else {
+ if (x != gpMustBeX)
+ goto InvalidInstruction;
+ }
+
+ uint32_t elementIndex = o1.as<Vec>().elementIndex();
+ uint32_t maxElementIndex = 15u >> sizeOp.size();
+
+ if (elementIndex > maxElementIndex)
+ goto InvalidElementIndex;
+
+ uint32_t imm5 = (1u | (elementIndex << 1)) << sizeOp.size();
+
+ opcode.reset(uint32_t(opData.opcode) << 10);
+ opcode.addImm(x, 30);
+ opcode.addImm(imm5, 16);
+ goto EmitOp_Rd0_Rn5;
+ }
+
+ break;
+ }
+
+ case InstDB::kEncodingSimdSxtlUxtl: {
+ const InstDB::EncodingData::SimdSxtlUxtl& opData = InstDB::EncodingData::simdSxtlUxtl[encodingIndex];
+
+ if (isign4 == ENC_OPS2(Reg, Reg)) {
+ SizeOp sizeOp = armElementTypeToSizeOp(opData.vecOpType, o1.as<Reg>().type(), o1.as<Vec>().elementType());
+ if (!sizeOp.isValid())
+ goto InvalidInstruction;
+
+ if (!matchSignature(o0, o1, instFlags))
+ goto InvalidInstruction;
+
+ opcode.reset(uint32_t(opData.opcode) << 10);
+ opcode.addImm(sizeOp.q(), 30);
+ opcode.addImm(1u, sizeOp.size() + 19);
+ goto EmitOp_Rd0_Rn5;
+ }
+
+ break;
+ }
+
+ case InstDB::kEncodingSimdTblTbx: {
+ const InstDB::EncodingData::SimdTblTbx& opData = InstDB::EncodingData::simdTblTbx[encodingIndex];
+
+ if (isign4 == ENC_OPS3(Reg, Reg, Reg) || isign4 == ENC_OPS4(Reg, Reg, Reg, Reg)) {
+ // TBL/TBX <Vd>.<Ta>, { <Vn>.16B }, <Vm>.<Ta>
+ // TBL/TBX <Vd>.<Ta>, { <Vn>.16B, <Vn+1>.16B }, <Vm>.<Ta>
+ // TBL/TBX <Vd>.<Ta>, { <Vn>.16B, <Vn+1>.16B, <Vn+2>.16B }, <Vm>.<Ta>
+ // TBL/TBX <Vd>.<Ta>, { <Vn>.16B, <Vn+1>.16B, <Vn+2>.16B, <Vn+3>.16B }, <Vm>.<Ta>
+ opcode.reset(uint32_t(opData.opcode) << 10);
+
+ const Operand_& o4 = opExt[EmitterUtils::kOp4];
+ const Operand_& o5 = opExt[EmitterUtils::kOp5];
+
+ uint32_t q = diff(o0.as<Reg>().type(), RegType::kARM_VecD);
+ if (q > 1 || o0.as<Vec>().hasElementIndex())
+ goto InvalidInstruction;
+
+ if (!o1.as<Vec>().isVecB16() || o1.as<Vec>().hasElementIndex())
+ goto InvalidInstruction;
+
+ uint32_t len = uint32_t(!o3.isNone()) + uint32_t(!o4.isNone()) + uint32_t(!o5.isNone());
+ opcode.addImm(q, 30);
+ opcode.addImm(len, 13);
+
+ switch (len) {
+ case 0:
+ if (!checkSignature(o0, o2))
+ goto InvalidInstruction;
+
+ if (o2.id() > 31)
+ goto InvalidPhysId;
+
+ opcode.addReg(o2, 16);
+ goto EmitOp_Rd0_Rn5;
+
+ case 1:
+ if (!checkSignature(o0, o3))
+ goto InvalidInstruction;
+
+ if (o3.id() > 31)
+ goto InvalidPhysId;
+
+ opcode.addReg(o3, 16);
+ goto EmitOp_Rd0_Rn5;
+
+ case 2:
+ if (!checkSignature(o0, o4))
+ goto InvalidInstruction;
+
+ if (o4.id() > 31)
+ goto InvalidPhysId;
+
+ opcode.addReg(o4, 16);
+ goto EmitOp_Rd0_Rn5;
+
+ case 3:
+ if (!checkSignature(o0, o5))
+ goto InvalidInstruction;
+
+ if (o5.id() > 31)
+ goto InvalidPhysId;
+
+ opcode.addReg(o5, 16);
+ goto EmitOp_Rd0_Rn5;
+
+ default:
+ // Should never happen.
+ goto InvalidInstruction;
+ }
+ }
+
+ break;
+ }
+
+ // ------------------------------------------------------------------------
+ // [Simd - Load / Store]
+ // ------------------------------------------------------------------------
+
+ case InstDB::kEncodingSimdLdSt: {
+ const InstDB::EncodingData::SimdLdSt& opData = InstDB::EncodingData::simdLdSt[encodingIndex];
+
+ if (isign4 == ENC_OPS2(Reg, Mem)) {
+ const Mem& m = o1.as<Mem>();
+ rmRel = &m;
+
+ // Width | SZ | XY | XSZ
+ // -------+----------+-----------+-----
+ // 8-bit | size==00 | opc == 01 | 000
+ // 16-bit | size==01 | opc == 01 | 001
+ // 32-bit | size==10 | opc == 01 | 010
+ // 64-bit | size==11 | opc == 01 | 011
+ // 128-bit| size==00 | opc == 11 | 100
+ uint32_t xsz = diff(o0.as<Reg>().type(), RegType::kARM_VecB);
+ if (xsz > 4u || o0.as<Vec>().hasElementIndex())
+ goto InvalidRegType;
+
+ if (!checkVecId(o0))
+ goto InvalidPhysId;
+
+ if (!armCheckMemBaseIndexRel(m))
+ goto InvalidAddress;
+
+ int64_t offset = m.offset();
+ if (m.hasBaseReg()) {
+ // [Base {Offset | Index}]
+ if (m.hasIndex()) {
+ uint32_t opt = armShiftOpToLdStOptMap[m.predicate()];
+ if (opt == 0xFFu)
+ goto InvalidAddress;
+
+ uint32_t shift = m.shift();
+ uint32_t s = (shift != 0);
+
+ if (s && shift != xsz)
+ goto InvalidAddressScale;
+
+ opcode.reset(uint32_t(opData.registerOp) << 21);
+ opcode.addImm(xsz & 3u, 30);
+ opcode.addImm(xsz >> 2, 23);
+ opcode.addImm(opt, 13);
+ opcode.addImm(s, 12);
+ opcode |= B(11);
+ opcode.addReg(o0, 0);
+ goto EmitOp_MemBaseIndex_Rn5_Rm16;
+ }
+
+ // Makes it easier to work with the offset especially on 32-bit arch.
+ if (!Support::isInt32(offset))
+ goto InvalidDisplacement;
+ int32_t offset32 = int32_t(offset);
+
+ if (m.isPreOrPost()) {
+ if (!Support::isInt9(offset32))
+ goto InvalidDisplacement;
+
+ opcode.reset(uint32_t(opData.prePostOp) << 21);
+ opcode.addImm(xsz & 3u, 30);
+ opcode.addImm(xsz >> 2, 23);
+ opcode.addImm(offset32 & 0x1FF, 12);
+ opcode.addImm(m.isPreIndex(), 11);
+ opcode |= B(10);
+ opcode.addReg(o0, 0);
+ goto EmitOp_MemBase_Rn5;
+ }
+ else {
+ uint32_t imm12 = uint32_t(offset32) >> xsz;
+
+ // If this instruction is not encodable with scaled unsigned offset, try unscaled signed offset.
+ if (!Support::isUInt12(imm12) || (imm12 << xsz) != uint32_t(offset32)) {
+ instId = opData.uAltInstId;
+ instInfo = &InstDB::_instInfoTable[instId];
+ encodingIndex = instInfo->_encodingDataIndex;
+ goto Case_SimdLdurStur;
+ }
+
+ opcode.reset(uint32_t(opData.uOffsetOp) << 22);
+ opcode.addImm(xsz & 3u, 30);
+ opcode.addImm(xsz >> 2, 23);
+ opcode.addImm(imm12, 10);
+ opcode.addReg(o0, 0);
+ goto EmitOp_MemBase_Rn5;
+ }
+ }
+ else {
+ if (!opData.literalOp)
+ goto InvalidAddress;
+
+ if (xsz < 2u)
+ goto InvalidRegType;
+
+ uint32_t opc = xsz - 2u;
+ opcode.reset(uint32_t(opData.literalOp) << 24);
+ opcode.addImm(opc, 30);
+ opcode.addReg(o0, 0);
+ offsetFormat.resetToImmValue(OffsetType::kSignedOffset, 4, 5, 19, 2);
+ goto EmitOp_Rel;
+ }
+ }
+
+ break;
+ }
+
+ case InstDB::kEncodingSimdLdpStp: {
+ const InstDB::EncodingData::SimdLdpStp& opData = InstDB::EncodingData::simdLdpStp[encodingIndex];
+
+ if (isign4 == ENC_OPS3(Reg, Reg, Mem)) {
+ const Mem& m = o2.as<Mem>();
+ rmRel = &m;
+
+ uint32_t opc = diff(o0.as<Reg>().type(), RegType::kARM_VecS);
+ if (opc > 2u || o0.as<Vec>().hasElementTypeOrIndex())
+ goto InvalidInstruction;
+
+ if (!checkSignature(o0, o1))
+ goto InvalidInstruction;
+
+ if (!checkVecId(o0, o1))
+ goto InvalidPhysId;
+
+ if (m.baseType() != RegType::kARM_GpX || m.hasIndex())
+ goto InvalidAddress;
+
+ if (m.isOffset64Bit())
+ goto InvalidDisplacement;
+
+ uint32_t offsetShift = 2u + opc;
+ int32_t offset32 = m.offsetLo32() >> offsetShift;
+
+ // Make sure we didn't lose bits by applying the mandatory offset shift.
+ if (Support::shl(offset32, offsetShift) != m.offsetLo32())
+ goto InvalidDisplacement;
+
+ // Offset is encoded as a 7-bit immediate.
+ if (!Support::isInt7(offset32))
+ goto InvalidDisplacement;
+
+ if (m.isPreOrPost() && offset32 != 0) {
+ if (!opData.prePostOp)
+ goto InvalidAddress;
+
+ opcode.reset(uint32_t(opData.prePostOp) << 22);
+ opcode.addImm(m.isPreIndex(), 24);
+ }
+ else {
+ opcode.reset(uint32_t(opData.offsetOp) << 22);
+ }
+
+ opcode.addImm(opc, 30);
+ opcode.addImm(offset32 & 0x7F, 15);
+ opcode.addReg(o1, 10);
+ opcode.addReg(o0, 0);
+ goto EmitOp_MemBase_Rn5;
+ }
+
+ break;
+ }
+
+ case InstDB::kEncodingSimdLdurStur: {
+Case_SimdLdurStur:
+ const InstDB::EncodingData::SimdLdurStur& opData = InstDB::EncodingData::simdLdurStur[encodingIndex];
+
+ if (isign4 == ENC_OPS2(Reg, Mem)) {
+ const Mem& m = o1.as<Mem>();
+ rmRel = &m;
+
+ uint32_t sz = diff(o0.as<Reg>().type(), RegType::kARM_VecB);
+ if (sz > 4 || o0.as<Vec>().hasElementTypeOrIndex())
+ goto InvalidInstruction;
+
+ if (!checkVecId(o0))
+ goto InvalidPhysId;
+
+ if (!armCheckMemBaseIndexRel(m))
+ goto InvalidAddress;
+
+ if (m.hasBaseReg() && !m.hasIndex() && !m.isPreOrPost()) {
+ if (m.isOffset64Bit())
+ goto InvalidDisplacement;
+
+ int32_t offset32 = m.offsetLo32();
+ if (!Support::isInt9(offset32))
+ goto InvalidDisplacement;
+
+ opcode.reset(uint32_t(opData.opcode) << 10);
+ opcode.addImm(sz & 3u, 30);
+ opcode.addImm(sz >> 2, 23);
+ opcode.addImm(offset32 & 0x1FF, 12);
+ opcode.addReg(o0, 0);
+ goto EmitOp_MemBase_Rn5;
+ }
+
+ goto InvalidAddress;
+ }
+
+ break;
+ }
+
+ case InstDB::kEncodingSimdLdNStN: {
+ const InstDB::EncodingData::SimdLdNStN& opData = InstDB::EncodingData::simdLdNStN[encodingIndex];
+ const Operand_& o4 = opExt[EmitterUtils::kOp4];
+
+ uint32_t n = 1;
+
+ if (isign4 == ENC_OPS2(Reg, Mem)) {
+ if (opData.n != 1)
+ goto InvalidInstruction;
+
+ rmRel = &o1;
+ }
+ else if (isign4 == ENC_OPS3(Reg, Reg, Mem)) {
+ if (opData.n != 1 && opData.n != 2)
+ goto InvalidInstruction;
+
+ if (!checkSignature(o0, o1) || !checkConsecutive(o0, o1))
+ goto InvalidInstruction;
+
+ n = 2;
+ rmRel = &o2;
+ }
+ else if (isign4 == ENC_OPS4(Reg, Reg, Reg, Mem) && o4.isNone()) {
+ if (opData.n != 1 && opData.n != 3)
+ goto InvalidInstruction;
+
+ if (!checkSignature(o0, o1, o2) || !checkConsecutive(o0, o1, o2))
+ goto InvalidInstruction;
+
+ n = 3;
+ rmRel = &o3;
+ }
+ else if (isign4 == ENC_OPS4(Reg, Reg, Reg, Reg) && o4.isMem()) {
+ if (opData.n != 1 && opData.n != 4)
+ goto InvalidInstruction;
+
+ if (!checkSignature(o0, o1, o2, o3) || !checkConsecutive(o0, o1, o2, o3))
+ goto InvalidInstruction;
+
+ n = 4;
+ rmRel = &o4;
+ }
+ else {
+ goto InvalidInstruction;
+ }
+
+ // We will use `v` and `m` from now as those are relevant for encoding.
+ const Vec& v = o0.as<Vec>();
+ const Mem& m = rmRel->as<Mem>();
+
+ uint32_t q = 0;
+ uint32_t rm = 0;
+ uint32_t rn = m.baseId();
+ uint32_t sz = v.elementType() - Vec::kElementTypeB;
+ uint32_t opcSsize = sz;
+ uint32_t offsetPossibility = 0;
+
+ if (sz > 3)
+ goto InvalidInstruction;
+
+ if (m.baseType() != RegType::kARM_GpX)
+ goto InvalidAddress;
+
+ // Rn cannot be ZR, but can be SP.
+ if (rn > 30 && rn != Gp::kIdSp)
+ goto InvalidAddress;
+
+ rn &= 31;
+
+ if (opData.replicate) {
+ if (n != opData.n)
+ goto InvalidInstruction;
+
+ // Replicates to the whole register, element index cannot be used.
+ if (v.hasElementIndex())
+ goto InvalidInstruction;
+
+ q = diff(v.type(), RegType::kARM_VecD);
+ if (q > 1)
+ goto InvalidInstruction;
+
+ opcode.reset(uint32_t(opData.singleOp) << 10);
+ offsetPossibility = (1u << sz) * n;
+ }
+ else if (v.hasElementIndex()) {
+ if (n != opData.n)
+ goto InvalidInstruction;
+
+ // LDx/STx (single structure).
+ static const uint8_t opcSsizeBySzS[] = { 0x0u << 3, 0x2u << 3, 0x4u << 3, (0x4u << 3) | 1u };
+
+ opcode.reset(uint32_t(opData.singleOp) << 10);
+ opcSsize = opcSsizeBySzS[sz];
+ offsetPossibility = (1u << sz) * opData.n;
+
+ uint32_t elementIndex = v.elementIndex();
+ uint32_t maxElementIndex = 15 >> sz;
+
+ if (elementIndex > maxElementIndex)
+ goto InvalidElementIndex;
+
+ elementIndex <<= sz;
+ q = elementIndex >> 3;
+ opcSsize |= elementIndex & 0x7u;
+ }
+ else {
+ // LDx/STx (multiple structures).
+ static const uint8_t opcSsizeByN[] = { 0u, 0x7u << 2, 0xAu << 2, 0x6u << 2, 0x2u << 2 };
+
+ q = diff(v.type(), RegType::kARM_VecD);
+ if (q > 1)
+ goto InvalidInstruction;
+
+ if (opData.n == 1)
+ opcSsize |= opcSsizeByN[n];
+
+ opcode.reset(uint32_t(opData.multipleOp) << 10);
+ offsetPossibility = (8u << q) * n;
+ }
+
+ if (m.hasIndex()) {
+ if (m.hasOffset() || !m.isPostIndex())
+ goto InvalidAddress;
+
+ rm = m.indexId();
+ if (rm > 30)
+ goto InvalidAddress;
+
+ // Bit 23 - PostIndex.
+ opcode |= B(23);
+ }
+ else {
+ if (m.hasOffset()) {
+ if (m.offset() != int32_t(offsetPossibility) || !m.isPostIndex())
+ goto InvalidAddress;
+ rm = 31;
+
+ // Bit 23 - PostIndex.
+ opcode |= B(23);
+ }
+ }
+
+ opcode.addImm(q, 30);
+ opcode.addImm(rm, 16);
+ opcode.addImm(opcSsize, 10);
+ opcode.addImm(rn, 5);
+ goto EmitOp_Rd0;
+ }
+
+ default:
+ break;
+ }
+
+ goto InvalidInstruction;
+
+ // --------------------------------------------------------------------------
+ // [EmitGp - Single]
+ // --------------------------------------------------------------------------
+
+EmitOp_Rd0:
+ if (!checkValidRegs(o0))
+ goto InvalidPhysId;
+
+ opcode.addReg(o0, 0);
+ goto EmitOp;
+
+EmitOp_Rn5:
+ if (!checkValidRegs(o0))
+ goto InvalidPhysId;
+
+ opcode.addReg(o0, 5);
+ goto EmitOp;
+
+EmitOp_Rn5_Rm16:
+ if (!checkValidRegs(o0, o1))
+ goto InvalidPhysId;
+
+ opcode.addReg(o0, 5);
+ opcode.addReg(o1, 16);
+ goto EmitOp;
+
+EmitOp_Rd0_Rn5:
+ if (!checkValidRegs(o0, o1))
+ goto InvalidPhysId;
+
+ opcode.addReg(o0, 0);
+ opcode.addReg(o1, 5);
+ goto EmitOp;
+
+EmitOp_Rd0_Rn5_Rm16_Ra10:
+ if (!checkValidRegs(o0, o1, o2, o3))
+ goto InvalidPhysId;
+
+ opcode.addReg(o0, 0);
+ opcode.addReg(o1, 5);
+ opcode.addReg(o2, 16);
+ opcode.addReg(o3, 10);
+ goto EmitOp;
+
+EmitOp_Rd0_Rn5_Rm16:
+ if (!checkValidRegs(o0, o1, o3))
+ goto InvalidPhysId;
+
+ opcode.addReg(o0, 0);
+ opcode.addReg(o1, 5);
+ opcode.addReg(o2, 16);
+ goto EmitOp;
+
+ // --------------------------------------------------------------------------
+ // [EmitGp - Multiple]
+ // --------------------------------------------------------------------------
+
+EmitOp_Multiple:
+ {
+ ASMJIT_ASSERT(multipleOpCount > 0);
+ err = writer.ensureSpace(this, multipleOpCount * 4u);
+ if (ASMJIT_UNLIKELY(err))
+ goto Failed;
+
+ for (uint32_t i = 0; i < multipleOpCount; i++)
+ writer.emit32uLE(multipleOpData[i]);
+
+ goto EmitDone;
+ }
+
+ // --------------------------------------------------------------------------
+ // [EmitGp - Memory]
+ // --------------------------------------------------------------------------
+
+EmitOp_MemBase_Rn5:
+ if (!checkMemBase(rmRel->as<Mem>()))
+ goto InvalidAddress;
+
+ opcode.addReg(rmRel->as<Mem>().baseId(), 5);
+ goto EmitOp;
+
+EmitOp_MemBaseNoImm_Rn5:
+ if (!checkMemBase(rmRel->as<Mem>()) || rmRel->as<Mem>().hasIndex())
+ goto InvalidAddress;
+
+ if (rmRel->as<Mem>().hasOffset())
+ goto InvalidDisplacement;
+
+ opcode.addReg(rmRel->as<Mem>().baseId(), 5);
+ goto EmitOp;
+
+EmitOp_MemBaseIndex_Rn5_Rm16:
+ if (!rmRel->as<Mem>().hasBaseReg())
+ goto InvalidAddress;
+
+ if (rmRel->as<Mem>().indexId() > 30 && rmRel->as<Mem>().indexId() != Gp::kIdZr)
+ goto InvalidPhysId;
+
+ opcode.addReg(rmRel->as<Mem>().indexId(), 16);
+ opcode.addReg(rmRel->as<Mem>().baseId(), 5);
+ goto EmitOp;
+
+ // --------------------------------------------------------------------------
+ // [EmitOp - PC Relative]
+ // --------------------------------------------------------------------------
+
+EmitOp_Rel:
+ {
+ if (rmRel->isLabel() || rmRel->isMem()) {
+ uint32_t labelId;
+ int64_t labelOffset = 0;
+
+ if (rmRel->isLabel()) {
+ labelId = rmRel->as<Label>().id();
+ }
+ else {
+ labelId = rmRel->as<Mem>().baseId();
+ labelOffset = rmRel->as<Mem>().offset();
+ }
+
+ LabelEntry* label = _code->labelEntry(labelId);
+ if (ASMJIT_UNLIKELY(!label))
+ goto InvalidLabel;
+
+ if (offsetFormat.type() == OffsetType::kAArch64_ADRP) {
+ // TODO: [ARM] Always create relocation entry.
+ }
+
+ if (label->isBoundTo(_section)) {
+ // Label bound to the current section.
+ offsetValue = label->offset() - uint64_t(offset()) + uint64_t(labelOffset);
+ goto EmitOp_DispImm;
+ }
+ else {
+ // Record non-bound label.
+ size_t codeOffset = writer.offsetFrom(_bufferData);
+ LabelLink* link = _code->newLabelLink(label, _section->id(), codeOffset, intptr_t(labelOffset), offsetFormat);
+
+ if (ASMJIT_UNLIKELY(!link))
+ goto OutOfMemory;
+
+ goto EmitOp;
+ }
+ }
+ }
+
+ if (rmRel->isImm()) {
+ uint64_t baseAddress = _code->baseAddress();
+ uint64_t targetOffset = rmRel->as<Imm>().valueAs<uint64_t>();
+
+ size_t codeOffset = writer.offsetFrom(_bufferData);
+
+ if (baseAddress == Globals::kNoBaseAddress || _section->id() != 0) {
+ // Create a new RelocEntry as we cannot calculate the offset right now.
+ RelocEntry* re;
+ err = _code->newRelocEntry(&re, RelocType::kAbsToRel);
+ if (err)
+ goto Failed;
+
+ re->_sourceSectionId = _section->id();
+ re->_sourceOffset = codeOffset;
+ re->_format = offsetFormat;
+ re->_payload = rmRel->as<Imm>().valueAs<uint64_t>() + 4u;
+ goto EmitOp;
+ }
+ else {
+ uint64_t pc = baseAddress + codeOffset;
+
+ if (offsetFormat.type() == OffsetType::kAArch64_ADRP)
+ pc &= ~uint64_t(4096 - 1);
+
+ offsetValue = targetOffset - pc;
+ goto EmitOp_DispImm;
+ }
+ }
+
+ goto InvalidInstruction;
+
+EmitOp_DispImm:
+ {
+ if ((offsetValue & Support::lsbMask<uint32_t>(offsetFormat.immDiscardLsb())) != 0)
+ goto InvalidDisplacement;
+
+ int64_t dispImm64 = int64_t(offsetValue) >> offsetFormat.immDiscardLsb();
+ if (!Support::isEncodableOffset64(dispImm64, offsetFormat.immBitCount()))
+ goto InvalidDisplacement;
+
+ uint32_t dispImm32 = uint32_t(dispImm64 & Support::lsbMask<uint32_t>(offsetFormat.immBitCount()));
+ switch (offsetFormat.type()) {
+ case OffsetType::kSignedOffset: {
+ opcode.addImm(dispImm32, offsetFormat.immBitShift());
+ goto EmitOp;
+ }
+
+ case OffsetType::kAArch64_ADR:
+ case OffsetType::kAArch64_ADRP: {
+ uint32_t immLo = dispImm32 & 0x3u;
+ uint32_t immHi = dispImm32 >> 2;
+ opcode.addImm(immLo, 29);
+ opcode.addImm(immHi, 5);
+ goto EmitOp;
+ }
+
+ default:
+ goto InvalidDisplacement;
+ }
+ }
+
+ // --------------------------------------------------------------------------
+ // [EmitOp - Opcode]
+ // --------------------------------------------------------------------------
+
+EmitOp:
+ writer.emit32uLE(opcode.get());
+ goto EmitDone;
+
+ // --------------------------------------------------------------------------
+ // [Done]
+ // --------------------------------------------------------------------------
+
+EmitDone:
+ if (Support::test(options, InstOptions::kReserved)) {
+#ifndef ASMJIT_NO_LOGGING
+ if (_logger)
+ EmitterUtils::logInstructionEmitted(this, instId, options, o0, o1, o2, opExt, 0, 0, writer.cursor());
+#endif
+ }
+
+ resetExtraReg();
+ resetInstOptions();
+ resetInlineComment();
+
+ writer.done(this);
+ return kErrorOk;
+
+ // --------------------------------------------------------------------------
+ // [Error Handler]
+ // --------------------------------------------------------------------------
+
+#define ERROR_HANDLER(ERR) ERR: err = DebugUtils::errored(kError##ERR); goto Failed;
+ ERROR_HANDLER(OutOfMemory)
+ ERROR_HANDLER(InvalidAddress)
+ ERROR_HANDLER(InvalidAddressScale)
+ ERROR_HANDLER(InvalidDisplacement)
+ ERROR_HANDLER(InvalidElementIndex)
+ ERROR_HANDLER(InvalidLabel)
+ ERROR_HANDLER(InvalidImmediate)
+ ERROR_HANDLER(InvalidInstruction)
+ ERROR_HANDLER(InvalidPhysId)
+ ERROR_HANDLER(InvalidRegType)
+#undef ERROR_HANDLER
+
+Failed:
+#ifndef ASMJIT_NO_LOGGING
+ return EmitterUtils::logInstructionFailed(this, err, instId, options, o0, o1, o2, opExt);
+#else
+ resetExtraReg();
+ resetInstOptions();
+ resetInlineComment();
+ return reportError(err);
+#endif
+}
+
+#undef ENC_OPS1
+#undef ENC_OPS2
+#undef ENC_OPS3
+#undef ENC_OPS4
+
+// a64::Assembler - Align
+// ======================
+
+Error Assembler::align(AlignMode alignMode, uint32_t alignment) {
+ constexpr uint32_t kNopA64 = 0xD503201Fu; // [11010101|00000011|00100000|00011111].
+
+ if (ASMJIT_UNLIKELY(!_code))
+ return reportError(DebugUtils::errored(kErrorNotInitialized));
+
+ if (ASMJIT_UNLIKELY(uint32_t(alignMode) > uint32_t(AlignMode::kMaxValue)))
+ return reportError(DebugUtils::errored(kErrorInvalidArgument));
+
+ if (alignment <= 1)
+ return kErrorOk;
+
+ if (ASMJIT_UNLIKELY(alignment > Globals::kMaxAlignment || !Support::isPowerOf2(alignment)))
+ return reportError(DebugUtils::errored(kErrorInvalidArgument));
+
+ uint32_t i = uint32_t(Support::alignUpDiff<size_t>(offset(), alignment));
+ if (i == 0)
+ return kErrorOk;
+
+ CodeWriter writer(this);
+ ASMJIT_PROPAGATE(writer.ensureSpace(this, i));
+
+ switch (alignMode) {
+ case AlignMode::kCode: {
+ uint32_t pattern = kNopA64;
+
+ if (ASMJIT_UNLIKELY(offset() & 0x3u))
+ return DebugUtils::errored(kErrorInvalidState);
+
+ while (i >= 4) {
+ writer.emit32uLE(pattern);
+ i -= 4;
+ }
+
+ ASMJIT_ASSERT(i == 0);
+ break;
+ }
+
+ case AlignMode::kData:
+ case AlignMode::kZero:
+ writer.emitZeros(i);
+ break;
+ }
+
+ writer.done(this);
+
+#ifndef ASMJIT_NO_LOGGING
+ if (_logger) {
+ StringTmp<128> sb;
+ sb.appendChars(' ', _logger->indentation(FormatIndentationGroup::kCode));
+ sb.appendFormat("align %u\n", alignment);
+ _logger->log(sb);
+ }
+#endif
+
+ return kErrorOk;
+}
+
+// a64::Assembler - Events
+// =======================
+
+Error Assembler::onAttach(CodeHolder* code) noexcept {
+ ASMJIT_PROPAGATE(Base::onAttach(code));
+ return kErrorOk;
+}
+
+Error Assembler::onDetach(CodeHolder* code) noexcept {
+ return Base::onDetach(code);
+}
+
+ASMJIT_END_SUB_NAMESPACE
+
+#endif // !ASMJIT_NO_AARCH64
diff --git a/3rdparty/asmjit/src/asmjit/arm/a64assembler.h b/3rdparty/asmjit/src/asmjit/arm/a64assembler.h
new file mode 100644
index 00000000000..f1ac72b8d56
--- /dev/null
+++ b/3rdparty/asmjit/src/asmjit/arm/a64assembler.h
@@ -0,0 +1,72 @@
+// This file is part of AsmJit project <https://asmjit.com>
+//
+// See asmjit.h or LICENSE.md for license and copyright information
+// SPDX-License-Identifier: Zlib
+
+#ifndef ASMJIT_ARM_A64ASSEMBLER_H_INCLUDED
+#define ASMJIT_ARM_A64ASSEMBLER_H_INCLUDED
+
+#include "../core/assembler.h"
+#include "../arm/a64emitter.h"
+#include "../arm/a64operand.h"
+
+ASMJIT_BEGIN_SUB_NAMESPACE(a64)
+
+//! \addtogroup asmjit_a64
+//! \{
+
+//! AArch64 assembler implementation.
+class ASMJIT_VIRTAPI Assembler
+ : public BaseAssembler,
+ public EmitterExplicitT<Assembler> {
+
+public:
+ typedef BaseAssembler Base;
+
+ //! \name Construction / Destruction
+ //! \{
+
+ ASMJIT_API Assembler(CodeHolder* code = nullptr) noexcept;
+ ASMJIT_API virtual ~Assembler() noexcept;
+
+ //! \}
+
+ //! \name Accessors
+ //! \{
+
+ //! Gets whether the current ARM mode is THUMB (alternative to 32-bit ARM encoding).
+ inline bool isInThumbMode() const noexcept { return _environment.isArchThumb(); }
+
+ //! Gets the current code alignment of the current mode (ARM vs THUMB).
+ inline uint32_t codeAlignment() const noexcept { return isInThumbMode() ? 2 : 4; }
+
+ //! \}
+
+ //! \name Emit
+ //! \{
+
+ ASMJIT_API Error _emit(InstId instId, const Operand_& o0, const Operand_& o1, const Operand_& o2, const Operand_* opExt) override;
+
+ //! \}
+
+ //! \name Align
+ //! \{
+
+ ASMJIT_API Error align(AlignMode alignMode, uint32_t alignment) override;
+
+ //! \}
+
+ //! \name Events
+ //! \{
+
+ ASMJIT_API Error onAttach(CodeHolder* code) noexcept override;
+ ASMJIT_API Error onDetach(CodeHolder* code) noexcept override;
+
+ //! \}
+};
+
+//! \}
+
+ASMJIT_END_SUB_NAMESPACE
+
+#endif // ASMJIT_ARM_A64ASSEMBLER_H_INCLUDED
diff --git a/3rdparty/asmjit/src/asmjit/arm/a64builder.cpp b/3rdparty/asmjit/src/asmjit/arm/a64builder.cpp
new file mode 100644
index 00000000000..3a52b2a578c
--- /dev/null
+++ b/3rdparty/asmjit/src/asmjit/arm/a64builder.cpp
@@ -0,0 +1,51 @@
+// This file is part of AsmJit project <https://asmjit.com>
+//
+// See asmjit.h or LICENSE.md for license and copyright information
+// SPDX-License-Identifier: Zlib
+
+#include "../core/api-build_p.h"
+#if !defined(ASMJIT_NO_AARCH64) && !defined(ASMJIT_NO_BUILDER)
+
+#include "../arm/a64assembler.h"
+#include "../arm/a64builder.h"
+#include "../arm/a64emithelper_p.h"
+
+ASMJIT_BEGIN_SUB_NAMESPACE(a64)
+
+// a64::Builder - Construction & Destruction
+// =========================================
+
+Builder::Builder(CodeHolder* code) noexcept : BaseBuilder() {
+ _archMask = uint64_t(1) << uint32_t(Arch::kAArch64);
+ assignEmitterFuncs(this);
+
+ if (code)
+ code->attach(this);
+}
+Builder::~Builder() noexcept {}
+
+// a64::Builder - Events
+// =====================
+
+Error Builder::onAttach(CodeHolder* code) noexcept {
+ return Base::onAttach(code);
+}
+
+Error Builder::onDetach(CodeHolder* code) noexcept {
+ return Base::onDetach(code);
+}
+
+// a64::Builder - Finalize
+// =======================
+
+Error Builder::finalize() {
+ ASMJIT_PROPAGATE(runPasses());
+ Assembler a(_code);
+ a.addEncodingOptions(encodingOptions());
+ a.addDiagnosticOptions(diagnosticOptions());
+ return serializeTo(&a);
+}
+
+ASMJIT_END_SUB_NAMESPACE
+
+#endif // !ASMJIT_NO_AARCH64 && !ASMJIT_NO_BUILDER
diff --git a/3rdparty/asmjit/src/asmjit/arm/a64builder.h b/3rdparty/asmjit/src/asmjit/arm/a64builder.h
new file mode 100644
index 00000000000..adc99aafc8c
--- /dev/null
+++ b/3rdparty/asmjit/src/asmjit/arm/a64builder.h
@@ -0,0 +1,57 @@
+// This file is part of AsmJit project <https://asmjit.com>
+//
+// See asmjit.h or LICENSE.md for license and copyright information
+// SPDX-License-Identifier: Zlib
+
+#ifndef ASMJIT_ARM_A64BUILDER_H_INCLUDED
+#define ASMJIT_ARM_A64BUILDER_H_INCLUDED
+
+#include "../core/api-config.h"
+#ifndef ASMJIT_NO_BUILDER
+
+#include "../core/builder.h"
+#include "../arm/a64emitter.h"
+
+ASMJIT_BEGIN_SUB_NAMESPACE(a64)
+
+//! \addtogroup asmjit_a64
+//! \{
+
+//! AArch64 builder implementation.
+class ASMJIT_VIRTAPI Builder
+ : public BaseBuilder,
+ public EmitterExplicitT<Builder> {
+public:
+ ASMJIT_NONCOPYABLE(Builder)
+ typedef BaseBuilder Base;
+
+ //! \name Construction & Destruction
+ //! \{
+
+ ASMJIT_API explicit Builder(CodeHolder* code = nullptr) noexcept;
+ ASMJIT_API virtual ~Builder() noexcept;
+
+ //! \}
+
+ //! \name Events
+ //! \{
+
+ ASMJIT_API Error onAttach(CodeHolder* code) noexcept override;
+ ASMJIT_API Error onDetach(CodeHolder* code) noexcept override;
+
+ //! \}
+
+ //! \name Finalize
+ //! \{
+
+ ASMJIT_API Error finalize() override;
+
+ //! \}
+};
+
+//! \}
+
+ASMJIT_END_SUB_NAMESPACE
+
+#endif // !ASMJIT_NO_BUILDER
+#endif // ASMJIT_ARM_A64BUILDER_H_INCLUDED
diff --git a/3rdparty/asmjit/src/asmjit/arm/a64compiler.cpp b/3rdparty/asmjit/src/asmjit/arm/a64compiler.cpp
new file mode 100644
index 00000000000..d6c4ed28ff2
--- /dev/null
+++ b/3rdparty/asmjit/src/asmjit/arm/a64compiler.cpp
@@ -0,0 +1,60 @@
+// This file is part of AsmJit project <https://asmjit.com>
+//
+// See asmjit.h or LICENSE.md for license and copyright information
+// SPDX-License-Identifier: Zlib
+
+#include "../core/api-build_p.h"
+#if !defined(ASMJIT_NO_AARCH64) && !defined(ASMJIT_NO_COMPILER)
+
+#include "../arm/a64assembler.h"
+#include "../arm/a64compiler.h"
+#include "../arm/a64emithelper_p.h"
+#include "../arm/a64rapass_p.h"
+
+ASMJIT_BEGIN_SUB_NAMESPACE(a64)
+
+// a64::Compiler - Construction & Destruction
+// ==========================================
+
+Compiler::Compiler(CodeHolder* code) noexcept : BaseCompiler() {
+ _archMask = uint64_t(1) << uint32_t(Arch::kAArch64);
+ assignEmitterFuncs(this);
+
+ if (code)
+ code->attach(this);
+}
+Compiler::~Compiler() noexcept {}
+
+// a64::Compiler - Events
+// ======================
+
+Error Compiler::onAttach(CodeHolder* code) noexcept {
+ ASMJIT_PROPAGATE(Base::onAttach(code));
+ Error err = addPassT<ARMRAPass>();
+
+ if (ASMJIT_UNLIKELY(err)) {
+ onDetach(code);
+ return err;
+ }
+
+ return kErrorOk;
+}
+
+Error Compiler::onDetach(CodeHolder* code) noexcept {
+ return Base::onDetach(code);
+}
+
+// a64::Compiler - Finalize
+// ========================
+
+Error Compiler::finalize() {
+ ASMJIT_PROPAGATE(runPasses());
+ Assembler a(_code);
+ a.addEncodingOptions(encodingOptions());
+ a.addDiagnosticOptions(diagnosticOptions());
+ return serializeTo(&a);
+}
+
+ASMJIT_END_SUB_NAMESPACE
+
+#endif // !ASMJIT_NO_AARCH64 && !ASMJIT_NO_COMPILER
diff --git a/3rdparty/asmjit/src/asmjit/arm/a64compiler.h b/3rdparty/asmjit/src/asmjit/arm/a64compiler.h
new file mode 100644
index 00000000000..ebed549581c
--- /dev/null
+++ b/3rdparty/asmjit/src/asmjit/arm/a64compiler.h
@@ -0,0 +1,235 @@
+// This file is part of AsmJit project <https://asmjit.com>
+//
+// See asmjit.h or LICENSE.md for license and copyright information
+// SPDX-License-Identifier: Zlib
+
+#ifndef ASMJIT_ARM_ARMCOMPILER_H_INCLUDED
+#define ASMJIT_ARM_ARMCOMPILER_H_INCLUDED
+
+#include "../core/api-config.h"
+#ifndef ASMJIT_NO_COMPILER
+
+#include "../core/compiler.h"
+#include "../core/type.h"
+#include "../arm/a64emitter.h"
+
+ASMJIT_BEGIN_SUB_NAMESPACE(a64)
+
+//! \addtogroup asmjit_a64
+//! \{
+
+//! AArch64 compiler implementation.
+class ASMJIT_VIRTAPI Compiler
+ : public BaseCompiler,
+ public EmitterExplicitT<Compiler> {
+public:
+ ASMJIT_NONCOPYABLE(Compiler)
+ typedef BaseCompiler Base;
+
+ //! \name Construction & Destruction
+ //! \{
+
+ ASMJIT_API explicit Compiler(CodeHolder* code = nullptr) noexcept;
+ ASMJIT_API virtual ~Compiler() noexcept;
+
+ //! \}
+
+ //! \name Virtual Registers
+ //! \{
+
+ //! \cond INTERNAL
+ template<typename RegT, typename Type>
+ inline RegT _newRegInternal(const Type& type) {
+ RegT reg(Globals::NoInit);
+ _newReg(&reg, type, nullptr);
+ return reg;
+ }
+
+ template<typename RegT, typename Type, typename... Args>
+ inline RegT _newRegInternal(const Type& type, const char* s, Args&&... args) {
+#ifndef ASMJIT_NO_LOGGING
+ RegT reg(Globals::NoInit);
+ if (sizeof...(Args) == 0)
+ _newReg(&reg, type, s);
+ else
+ _newRegFmt(&reg, type, s, std::forward<Args>(args)...);
+ return reg;
+#else
+ DebugUtils::unused(std::forward<Args>(args)...);
+ RegT reg(Globals::NoInit);
+ _newReg(&reg, type, nullptr);
+ return reg;
+#endif
+ }
+ //! \endcond
+
+ template<typename RegT, typename... Args>
+ inline RegT newSimilarReg(const RegT& ref, Args&&... args) {
+ return _newRegInternal<RegT>(ref, std::forward<Args>(args)...);
+ }
+
+ template<typename... Args>
+ inline Reg newReg(TypeId typeId, Args&&... args) { return _newRegInternal<Reg>(typeId, std::forward<Args>(args)...); }
+
+ template<typename... Args>
+ inline Gp newGp(TypeId typeId, Args&&... args) { return _newRegInternal<Gp>(typeId, std::forward<Args>(args)...); }
+
+ template<typename... Args>
+ inline Vec newVec(TypeId typeId, Args&&... args) { return _newRegInternal<Vec>(typeId, std::forward<Args>(args)...); }
+
+ template<typename... Args>
+ inline Gp newInt32(Args&&... args) { return _newRegInternal<Gp>(TypeId::kInt32, std::forward<Args>(args)...); }
+ template<typename... Args>
+ inline Gp newUInt32(Args&&... args) { return _newRegInternal<Gp>(TypeId::kUInt32, std::forward<Args>(args)...); }
+
+ template<typename... Args>
+ inline Gp newInt64(Args&&... args) { return _newRegInternal<Gp>(TypeId::kInt64, std::forward<Args>(args)...); }
+ template<typename... Args>
+ inline Gp newUInt64(Args&&... args) { return _newRegInternal<Gp>(TypeId::kUInt64, std::forward<Args>(args)...); }
+
+ template<typename... Args>
+ inline Gp newIntPtr(Args&&... args) { return _newRegInternal<Gp>(TypeId::kIntPtr, std::forward<Args>(args)...); }
+ template<typename... Args>
+ inline Gp newUIntPtr(Args&&... args) { return _newRegInternal<Gp>(TypeId::kUIntPtr, std::forward<Args>(args)...); }
+
+ template<typename... Args>
+ inline Gp newGpw(Args&&... args) { return _newRegInternal<Gp>(TypeId::kUInt32, std::forward<Args>(args)...); }
+ template<typename... Args>
+ inline Gp newGpx(Args&&... args) { return _newRegInternal<Gp>(TypeId::kUInt64, std::forward<Args>(args)...); }
+ template<typename... Args>
+ inline Gp newGpz(Args&&... args) { return _newRegInternal<Gp>(TypeId::kUIntPtr, std::forward<Args>(args)...); }
+
+ template<typename... Args>
+ inline Vec newVecS(Args&&... args) { return _newRegInternal<Vec>(TypeId::kFloat32, std::forward<Args>(args)...); }
+
+ template<typename... Args>
+ inline Vec newVecD(Args&&... args) { return _newRegInternal<Vec>(TypeId::kFloat64, std::forward<Args>(args)...); }
+
+ template<typename... Args>
+ inline Vec newVecQ(Args&&... args) { return _newRegInternal<Vec>(TypeId::kUInt8x16, std::forward<Args>(args)...); }
+
+ //! \}
+
+ //! \name Stack
+ //! \{
+
+ //! Creates a new memory chunk allocated on the current function's stack.
+ inline Mem newStack(uint32_t size, uint32_t alignment, const char* name = nullptr) {
+ Mem m(Globals::NoInit);
+ _newStack(&m, size, alignment, name);
+ return m;
+ }
+
+ //! \}
+
+ //! \name Constants
+ //! \{
+
+ //! Put data to a constant-pool and get a memory reference to it.
+ inline Mem newConst(ConstPoolScope scope, const void* data, size_t size) {
+ Mem m(Globals::NoInit);
+ _newConst(&m, scope, data, size);
+ return m;
+ }
+
+ //! Put a BYTE `val` to a constant-pool (8 bits).
+ inline Mem newByteConst(ConstPoolScope scope, uint8_t val) noexcept { return newConst(scope, &val, 1); }
+ //! Put a HWORD `val` to a constant-pool (16 bits).
+ inline Mem newHWordConst(ConstPoolScope scope, uint16_t val) noexcept { return newConst(scope, &val, 2); }
+ //! Put a WORD `val` to a constant-pool (32 bits).
+ inline Mem newWordConst(ConstPoolScope scope, uint32_t val) noexcept { return newConst(scope, &val, 4); }
+ //! Put a DWORD `val` to a constant-pool (64 bits).
+ inline Mem newDWordConst(ConstPoolScope scope, uint64_t val) noexcept { return newConst(scope, &val, 8); }
+
+ //! Put a WORD `val` to a constant-pool.
+ inline Mem newInt16Const(ConstPoolScope scope, int16_t val) noexcept { return newConst(scope, &val, 2); }
+ //! Put a WORD `val` to a constant-pool.
+ inline Mem newUInt16Const(ConstPoolScope scope, uint16_t val) noexcept { return newConst(scope, &val, 2); }
+ //! Put a DWORD `val` to a constant-pool.
+ inline Mem newInt32Const(ConstPoolScope scope, int32_t val) noexcept { return newConst(scope, &val, 4); }
+ //! Put a DWORD `val` to a constant-pool.
+ inline Mem newUInt32Const(ConstPoolScope scope, uint32_t val) noexcept { return newConst(scope, &val, 4); }
+ //! Put a QWORD `val` to a constant-pool.
+ inline Mem newInt64Const(ConstPoolScope scope, int64_t val) noexcept { return newConst(scope, &val, 8); }
+ //! Put a QWORD `val` to a constant-pool.
+ inline Mem newUInt64Const(ConstPoolScope scope, uint64_t val) noexcept { return newConst(scope, &val, 8); }
+
+ //! Put a SP-FP `val` to a constant-pool.
+ inline Mem newFloatConst(ConstPoolScope scope, float val) noexcept { return newConst(scope, &val, 4); }
+ //! Put a DP-FP `val` to a constant-pool.
+ inline Mem newDoubleConst(ConstPoolScope scope, double val) noexcept { return newConst(scope, &val, 8); }
+
+ //! \}
+
+ //! \name Instruction Options
+ //! \{
+
+ //! Force the compiler to not follow the conditional or unconditional jump.
+ inline Compiler& unfollow() noexcept { _instOptions |= InstOptions::kUnfollow; return *this; }
+
+ //! \}
+
+ //! \name Function Call & Ret Intrinsics
+ //! \{
+
+ //! Invoke a function call without `target` type enforcement.
+ inline Error invoke_(InvokeNode** out, const Operand_& target, const FuncSignature& signature) {
+ return addInvokeNode(out, Inst::kIdBlr, target, signature);
+ }
+
+ //! Invoke a function call of the given `target` and `signature` and store the added node to `out`.
+ //!
+ //! Creates a new \ref InvokeNode, initializes all the necessary members to match the given function `signature`,
+ //! adds the node to the compiler, and stores its pointer to `out`. The operation is atomic, if anything fails
+ //! nullptr is stored in `out` and error code is returned.
+ inline Error invoke(InvokeNode** out, const Gp& target, const FuncSignature& signature) { return invoke_(out, target, signature); }
+ //! \overload
+ inline Error invoke(InvokeNode** out, const Mem& target, const FuncSignature& signature) { return invoke_(out, target, signature); }
+ //! \overload
+ inline Error invoke(InvokeNode** out, const Label& target, const FuncSignature& signature) { return invoke_(out, target, signature); }
+ //! \overload
+ inline Error invoke(InvokeNode** out, const Imm& target, const FuncSignature& signature) { return invoke_(out, target, signature); }
+ //! \overload
+ inline Error invoke(InvokeNode** out, uint64_t target, const FuncSignature& signature) { return invoke_(out, Imm(int64_t(target)), signature); }
+
+ //! Return.
+ inline Error ret() { return addRet(Operand(), Operand()); }
+ //! \overload
+ inline Error ret(const BaseReg& o0) { return addRet(o0, Operand()); }
+ //! \overload
+ inline Error ret(const BaseReg& o0, const BaseReg& o1) { return addRet(o0, o1); }
+
+ //! \}
+
+ //! \name Jump Tables Support
+ //! \{
+
+ using EmitterExplicitT<Compiler>::br;
+
+ //! Adds a jump to the given `target` with the provided jump `annotation`.
+ inline Error br(const BaseReg& target, JumpAnnotation* annotation) { return emitAnnotatedJump(Inst::kIdBr, target, annotation); }
+
+ //! \}
+
+ //! \name Events
+ //! \{
+
+ ASMJIT_API Error onAttach(CodeHolder* code) noexcept override;
+ ASMJIT_API Error onDetach(CodeHolder* code) noexcept override;
+
+ //! \}
+
+ //! \name Finalize
+ //! \{
+
+ ASMJIT_API Error finalize() override;
+
+ //! \}
+};
+
+//! \}
+
+ASMJIT_END_SUB_NAMESPACE
+
+#endif // !ASMJIT_NO_COMPILER
+#endif // ASMJIT_ARM_ARMCOMPILER_H_INCLUDED
diff --git a/3rdparty/asmjit/src/asmjit/arm/a64emithelper.cpp b/3rdparty/asmjit/src/asmjit/arm/a64emithelper.cpp
new file mode 100644
index 00000000000..2d8a5781cd6
--- /dev/null
+++ b/3rdparty/asmjit/src/asmjit/arm/a64emithelper.cpp
@@ -0,0 +1,464 @@
+// This file is part of AsmJit project <https://asmjit.com>
+//
+// See asmjit.h or LICENSE.md for license and copyright information
+// SPDX-License-Identifier: Zlib
+
+#include "../core/api-build_p.h"
+#if !defined(ASMJIT_NO_AARCH64)
+
+#include "../core/formatter.h"
+#include "../core/funcargscontext_p.h"
+#include "../core/string.h"
+#include "../core/support.h"
+#include "../core/type.h"
+#include "../arm/a64emithelper_p.h"
+#include "../arm/a64formatter_p.h"
+#include "../arm/a64instapi_p.h"
+#include "../arm/a64operand.h"
+
+ASMJIT_BEGIN_SUB_NAMESPACE(a64)
+
+// a64::EmitHelper - Emit Operations
+// =================================
+
+ASMJIT_FAVOR_SIZE Error EmitHelper::emitRegMove(
+ const Operand_& dst_,
+ const Operand_& src_, TypeId typeId, const char* comment) {
+
+ Emitter* emitter = _emitter->as<Emitter>();
+
+ // Invalid or abstract TypeIds are not allowed.
+ ASMJIT_ASSERT(TypeUtils::isValid(typeId) && !TypeUtils::isAbstract(typeId));
+
+ emitter->setInlineComment(comment);
+
+ if (dst_.isReg() && src_.isMem()) {
+ Reg dst(dst_.as<Reg>());
+ Mem src(src_.as<Mem>());
+
+ switch (typeId) {
+ case TypeId::kInt8:
+ case TypeId::kUInt8:
+ return emitter->ldrb(dst.as<Gp>(), src);
+
+ case TypeId::kInt16:
+ case TypeId::kUInt16:
+ return emitter->ldrh(dst.as<Gp>(), src);
+
+ case TypeId::kInt32:
+ case TypeId::kUInt32:
+ return emitter->ldr(dst.as<Gp>().w(), src);
+
+ case TypeId::kInt64:
+ case TypeId::kUInt64:
+ return emitter->ldr(dst.as<Gp>().x(), src);
+
+ default: {
+ if (TypeUtils::isFloat32(typeId) || TypeUtils::isVec32(typeId))
+ return emitter->ldr(dst.as<Vec>().s(), src);
+
+ if (TypeUtils::isFloat64(typeId) || TypeUtils::isVec64(typeId))
+ return emitter->ldr(dst.as<Vec>().d(), src);
+
+ if (TypeUtils::isVec128(typeId))
+ return emitter->ldr(dst.as<Vec>().q(), src);
+
+ break;
+ }
+ }
+ }
+
+ if (dst_.isMem() && src_.isReg()) {
+ Mem dst(dst_.as<Mem>());
+ Reg src(src_.as<Reg>());
+
+ switch (typeId) {
+ case TypeId::kInt8:
+ case TypeId::kUInt8:
+ return emitter->strb(src.as<Gp>(), dst);
+
+ case TypeId::kInt16:
+ case TypeId::kUInt16:
+ return emitter->strh(src.as<Gp>(), dst);
+
+ case TypeId::kInt32:
+ case TypeId::kUInt32:
+ return emitter->str(src.as<Gp>().w(), dst);
+
+ case TypeId::kInt64:
+ case TypeId::kUInt64:
+ return emitter->str(src.as<Gp>().x(), dst);
+
+ default: {
+ if (TypeUtils::isFloat32(typeId) || TypeUtils::isVec32(typeId))
+ return emitter->str(src.as<Vec>().s(), dst);
+
+ if (TypeUtils::isFloat64(typeId) || TypeUtils::isVec64(typeId))
+ return emitter->str(src.as<Vec>().d(), dst);
+
+ if (TypeUtils::isVec128(typeId))
+ return emitter->str(src.as<Vec>().q(), dst);
+
+ break;
+ }
+ }
+ }
+
+ if (dst_.isReg() && src_.isReg()) {
+ Reg dst(dst_.as<Reg>());
+ Reg src(src_.as<Reg>());
+
+ switch (typeId) {
+ case TypeId::kInt8:
+ case TypeId::kUInt8:
+ case TypeId::kInt16:
+ case TypeId::kUInt16:
+ case TypeId::kInt32:
+ case TypeId::kUInt32:
+ case TypeId::kInt64:
+ case TypeId::kUInt64:
+ return emitter->mov(src.as<Gp>().x(), dst.as<Gp>().x());
+
+ default: {
+ if (TypeUtils::isFloat32(typeId) || TypeUtils::isVec32(typeId))
+ return emitter->fmov(dst.as<Vec>().s(), src.as<Vec>().s());
+
+ if (TypeUtils::isFloat64(typeId) || TypeUtils::isVec64(typeId))
+ return emitter->mov(dst.as<Vec>().b8(), src.as<Vec>().b8());
+
+ if (TypeUtils::isVec128(typeId))
+ return emitter->mov(dst.as<Vec>().b16(), src.as<Vec>().b16());
+
+ break;
+ }
+ }
+ }
+
+ emitter->setInlineComment(nullptr);
+ return DebugUtils::errored(kErrorInvalidState);
+}
+
+Error EmitHelper::emitRegSwap(
+ const BaseReg& a,
+ const BaseReg& b, const char* comment) {
+
+ DebugUtils::unused(a, b, comment);
+ return DebugUtils::errored(kErrorInvalidState);
+}
+
+// TODO: [ARM] EmitArgMove is unfinished.
+Error EmitHelper::emitArgMove(
+ const BaseReg& dst_, TypeId dstTypeId,
+ const Operand_& src_, TypeId srcTypeId, const char* comment) {
+
+ // Deduce optional `dstTypeId`, which may be `TypeId::kVoid` in some cases.
+ if (dstTypeId == TypeId::kVoid) {
+ const ArchTraits& archTraits = ArchTraits::byArch(_emitter->arch());
+ dstTypeId = archTraits.regTypeToTypeId(dst_.type());
+ }
+
+ // Invalid or abstract TypeIds are not allowed.
+ ASMJIT_ASSERT(TypeUtils::isValid(dstTypeId) && !TypeUtils::isAbstract(dstTypeId));
+ ASMJIT_ASSERT(TypeUtils::isValid(srcTypeId) && !TypeUtils::isAbstract(srcTypeId));
+
+ Reg dst(dst_.as<Reg>());
+ Operand src(src_);
+
+ uint32_t dstSize = TypeUtils::sizeOf(dstTypeId);
+ uint32_t srcSize = TypeUtils::sizeOf(srcTypeId);
+
+ if (TypeUtils::isInt(dstTypeId)) {
+ if (TypeUtils::isInt(srcTypeId)) {
+ uint32_t x = dstSize == 8;
+
+ dst.setSignature(OperandSignature{x ? uint32_t(GpX::kSignature) : uint32_t(GpW::kSignature)});
+ _emitter->setInlineComment(comment);
+
+ if (src.isReg()) {
+ src.setSignature(dst.signature());
+ return _emitter->emit(Inst::kIdMov, dst, src);
+ }
+ else if (src.isMem()) {
+ InstId instId = Inst::kIdNone;
+ switch (srcTypeId) {
+ case TypeId::kInt8: instId = Inst::kIdLdrsb; break;
+ case TypeId::kUInt8: instId = Inst::kIdLdrb; break;
+ case TypeId::kInt16: instId = Inst::kIdLdrsh; break;
+ case TypeId::kUInt16: instId = Inst::kIdLdrh; break;
+ case TypeId::kInt32: instId = x ? Inst::kIdLdrsw : Inst::kIdLdr; break;
+ case TypeId::kUInt32: instId = Inst::kIdLdr; x = 0; break;
+ case TypeId::kInt64: instId = Inst::kIdLdr; break;
+ case TypeId::kUInt64: instId = Inst::kIdLdr; break;
+ default:
+ return DebugUtils::errored(kErrorInvalidState);
+ }
+ return _emitter->emit(instId, dst, src);
+ }
+ }
+ }
+
+ if (TypeUtils::isFloat(dstTypeId) || TypeUtils::isVec(dstTypeId)) {
+ if (TypeUtils::isFloat(srcTypeId) || TypeUtils::isVec(srcTypeId)) {
+ switch (srcSize) {
+ case 2: dst.as<Vec>().setSignature(OperandSignature{VecH::kSignature}); break;
+ case 4: dst.as<Vec>().setSignature(OperandSignature{VecS::kSignature}); break;
+ case 8: dst.as<Vec>().setSignature(OperandSignature{VecD::kSignature}); break;
+ case 16: dst.as<Vec>().setSignature(OperandSignature{VecV::kSignature}); break;
+ default:
+ return DebugUtils::errored(kErrorInvalidState);
+ }
+
+ _emitter->setInlineComment(comment);
+
+ if (src.isReg()) {
+ InstId instId = srcSize <= 4 ? Inst::kIdFmov_v : Inst::kIdMov_v;
+ src.setSignature(dst.signature());
+ return _emitter->emit(instId, dst, src);
+ }
+ else if (src.isMem()) {
+ return _emitter->emit(Inst::kIdLdr_v, dst, src);
+ }
+ }
+ }
+
+ return DebugUtils::errored(kErrorInvalidState);
+}
+
+// a64::EmitHelper - Emit Prolog & Epilog
+// ======================================
+
+struct LoadStoreInstructions {
+ InstId singleInstId;
+ InstId pairInstId;
+};
+
+struct PrologEpilogInfo {
+ struct RegPair {
+ uint8_t ids[2];
+ uint16_t offset;
+ };
+
+ struct GroupData {
+ RegPair pairs[16];
+ uint32_t pairCount;
+ };
+
+ Support::Array<GroupData, 2> groups;
+ uint32_t sizeTotal;
+
+ Error init(const FuncFrame& frame) noexcept {
+ uint32_t offset = 0;
+
+ for (RegGroup group : Support::EnumValues<RegGroup, RegGroup::kGp, RegGroup::kVec>{}) {
+ GroupData& data = groups[group];
+
+ uint32_t n = 0;
+ uint32_t pairCount = 0;
+ RegPair* pairs = data.pairs;
+
+ uint32_t slotSize = frame.saveRestoreRegSize(group);
+ uint32_t savedRegs = frame.savedRegs(group);
+
+ if (group == RegGroup::kGp && frame.hasPreservedFP()) {
+ // Must be at the beginning of the push/pop sequence.
+ ASMJIT_ASSERT(pairCount == 0);
+
+ pairs[0].offset = uint16_t(offset);
+ pairs[0].ids[0] = Gp::kIdFp;
+ pairs[0].ids[1] = Gp::kIdLr;
+ offset += slotSize * 2;
+ pairCount++;
+
+ savedRegs &= ~Support::bitMask(Gp::kIdFp, Gp::kIdLr);
+ }
+
+ Support::BitWordIterator<uint32_t> it(savedRegs);
+ while (it.hasNext()) {
+ pairs[pairCount].ids[n] = uint8_t(it.next());
+
+ if (++n == 2) {
+ pairs[pairCount].offset = uint16_t(offset);
+ offset += slotSize * 2;
+
+ n = 0;
+ pairCount++;
+ }
+ }
+
+ if (n == 1) {
+ pairs[pairCount].ids[1] = uint8_t(BaseReg::kIdBad);
+ pairs[pairCount].offset = uint16_t(offset);
+ offset += slotSize * 2;
+ pairCount++;
+ }
+
+ data.pairCount = pairCount;
+ }
+
+ sizeTotal = offset;
+ return kErrorOk;
+ }
+};
+
+ASMJIT_FAVOR_SIZE Error EmitHelper::emitProlog(const FuncFrame& frame) {
+ Emitter* emitter = _emitter->as<Emitter>();
+
+ PrologEpilogInfo pei;
+ ASMJIT_PROPAGATE(pei.init(frame));
+
+ static const Support::Array<Reg, 2> groupRegs = {{ x0, d0 }};
+ static const Support::Array<LoadStoreInstructions, 2> groupInsts = {{
+ { Inst::kIdStr , Inst::kIdStp },
+ { Inst::kIdStr_v, Inst::kIdStp_v }
+ }};
+
+ uint32_t adjustInitialOffset = pei.sizeTotal;
+
+ for (RegGroup group : Support::EnumValues<RegGroup, RegGroup::kGp, RegGroup::kVec>{}) {
+ const PrologEpilogInfo::GroupData& data = pei.groups[group];
+ uint32_t pairCount = data.pairCount;
+
+ Reg regs[2] = { groupRegs[group], groupRegs[group] };
+ Mem mem = ptr(sp);
+
+ const LoadStoreInstructions& insts = groupInsts[group];
+ for (uint32_t i = 0; i < pairCount; i++) {
+ const PrologEpilogInfo::RegPair& pair = data.pairs[i];
+
+ regs[0].setId(pair.ids[0]);
+ regs[1].setId(pair.ids[1]);
+ mem.setOffsetLo32(pair.offset);
+
+ if (pair.offset == 0 && adjustInitialOffset) {
+ mem.setOffset(-int(adjustInitialOffset));
+ mem.makePreIndex();
+ }
+
+ if (pair.ids[1] == BaseReg::kIdBad)
+ ASMJIT_PROPAGATE(emitter->emit(insts.singleInstId, regs[0], mem));
+ else
+ ASMJIT_PROPAGATE(emitter->emit(insts.pairInstId, regs[0], regs[1], mem));
+
+ mem.resetToFixedOffset();
+
+ if (i == 0 && frame.hasPreservedFP()) {
+ ASMJIT_PROPAGATE(emitter->mov(x29, sp));
+ }
+ }
+ }
+
+ if (frame.hasStackAdjustment()) {
+ uint32_t adj = frame.stackAdjustment();
+ if (adj <= 0xFFFu) {
+ ASMJIT_PROPAGATE(emitter->sub(sp, sp, adj));
+ }
+ else if (adj <= 0xFFFFFFu) {
+ // TODO: [ARM] Prolog - we must touch the pages otherwise it's undefined.
+ ASMJIT_PROPAGATE(emitter->sub(sp, sp, adj & 0x000FFFu));
+ ASMJIT_PROPAGATE(emitter->sub(sp, sp, adj & 0xFFF000u));
+ }
+ else {
+ return DebugUtils::errored(kErrorInvalidState);
+ }
+ }
+
+ return kErrorOk;
+}
+
+// TODO: [ARM] Emit epilog.
+ASMJIT_FAVOR_SIZE Error EmitHelper::emitEpilog(const FuncFrame& frame) {
+ Emitter* emitter = _emitter->as<Emitter>();
+
+ PrologEpilogInfo pei;
+ ASMJIT_PROPAGATE(pei.init(frame));
+
+ static const Support::Array<Reg, 2> groupRegs = {{ x0, d0 }};
+ static const Support::Array<LoadStoreInstructions, 2> groupInsts = {{
+ { Inst::kIdLdr , Inst::kIdLdp },
+ { Inst::kIdLdr_v, Inst::kIdLdp_v }
+ }};
+
+ uint32_t adjustInitialOffset = pei.sizeTotal;
+
+ if (frame.hasStackAdjustment()) {
+ uint32_t adj = frame.stackAdjustment();
+ if (adj <= 0xFFFu) {
+ ASMJIT_PROPAGATE(emitter->add(sp, sp, adj));
+ }
+ else if (adj <= 0xFFFFFFu) {
+ ASMJIT_PROPAGATE(emitter->add(sp, sp, adj & 0x000FFFu));
+ ASMJIT_PROPAGATE(emitter->add(sp, sp, adj & 0xFFF000u));
+ }
+ else {
+ return DebugUtils::errored(kErrorInvalidState);
+ }
+ }
+
+ for (int g = 1; g >= 0; g--) {
+ RegGroup group = RegGroup(g);
+ const PrologEpilogInfo::GroupData& data = pei.groups[group];
+ uint32_t pairCount = data.pairCount;
+
+ Reg regs[2] = { groupRegs[group], groupRegs[group] };
+ Mem mem = ptr(sp);
+
+ const LoadStoreInstructions& insts = groupInsts[group];
+
+ for (int i = int(pairCount) - 1; i >= 0; i--) {
+ const PrologEpilogInfo::RegPair& pair = data.pairs[i];
+
+ regs[0].setId(pair.ids[0]);
+ regs[1].setId(pair.ids[1]);
+ mem.setOffsetLo32(pair.offset);
+
+ if (pair.offset == 0 && adjustInitialOffset) {
+ mem.setOffset(int(adjustInitialOffset));
+ mem.makePostIndex();
+ }
+
+ if (pair.ids[1] == BaseReg::kIdBad)
+ ASMJIT_PROPAGATE(emitter->emit(insts.singleInstId, regs[0], mem));
+ else
+ ASMJIT_PROPAGATE(emitter->emit(insts.pairInstId, regs[0], regs[1], mem));
+
+ mem.resetToFixedOffset();
+ }
+ }
+
+ ASMJIT_PROPAGATE(emitter->ret(x30));
+
+ return kErrorOk;
+}
+
+static Error ASMJIT_CDECL Emitter_emitProlog(BaseEmitter* emitter, const FuncFrame& frame) {
+ EmitHelper emitHelper(emitter);
+ return emitHelper.emitProlog(frame);
+}
+
+static Error ASMJIT_CDECL Emitter_emitEpilog(BaseEmitter* emitter, const FuncFrame& frame) {
+ EmitHelper emitHelper(emitter);
+ return emitHelper.emitEpilog(frame);
+}
+
+static Error ASMJIT_CDECL Emitter_emitArgsAssignment(BaseEmitter* emitter, const FuncFrame& frame, const FuncArgsAssignment& args) {
+ EmitHelper emitHelper(emitter);
+ return emitHelper.emitArgsAssignment(frame, args);
+}
+
+void assignEmitterFuncs(BaseEmitter* emitter) {
+ emitter->_funcs.emitProlog = Emitter_emitProlog;
+ emitter->_funcs.emitEpilog = Emitter_emitEpilog;
+ emitter->_funcs.emitArgsAssignment = Emitter_emitArgsAssignment;
+
+#ifndef ASMJIT_NO_LOGGING
+ emitter->_funcs.formatInstruction = FormatterInternal::formatInstruction;
+#endif
+
+#ifndef ASMJIT_NO_VALIDATION
+ emitter->_funcs.validate = InstInternal::validate;
+#endif
+}
+
+ASMJIT_END_SUB_NAMESPACE
+
+#endif // !ASMJIT_NO_AARCH64
diff --git a/3rdparty/asmjit/src/asmjit/arm/a64emithelper_p.h b/3rdparty/asmjit/src/asmjit/arm/a64emithelper_p.h
new file mode 100644
index 00000000000..b1ba1a92960
--- /dev/null
+++ b/3rdparty/asmjit/src/asmjit/arm/a64emithelper_p.h
@@ -0,0 +1,50 @@
+// This file is part of AsmJit project <https://asmjit.com>
+//
+// See asmjit.h or LICENSE.md for license and copyright information
+// SPDX-License-Identifier: Zlib
+
+#ifndef ASMJIT_ARM_ARMEMITHELPER_P_H_INCLUDED
+#define ASMJIT_ARM_ARMEMITHELPER_P_H_INCLUDED
+
+#include "../core/api-config.h"
+
+#include "../core/emithelper_p.h"
+#include "../core/func.h"
+#include "../arm/a64emitter.h"
+#include "../arm/a64operand.h"
+
+ASMJIT_BEGIN_SUB_NAMESPACE(a64)
+
+//! \cond INTERNAL
+//! \addtogroup asmjit_a64
+//! \{
+
+class EmitHelper : public BaseEmitHelper {
+public:
+ inline explicit EmitHelper(BaseEmitter* emitter = nullptr) noexcept
+ : BaseEmitHelper(emitter) {}
+
+ Error emitRegMove(
+ const Operand_& dst_,
+ const Operand_& src_, TypeId typeId, const char* comment = nullptr) override;
+
+ Error emitRegSwap(
+ const BaseReg& a,
+ const BaseReg& b, const char* comment = nullptr) override;
+
+ Error emitArgMove(
+ const BaseReg& dst_, TypeId dstTypeId,
+ const Operand_& src_, TypeId srcTypeId, const char* comment = nullptr) override;
+
+ Error emitProlog(const FuncFrame& frame);
+ Error emitEpilog(const FuncFrame& frame);
+};
+
+void assignEmitterFuncs(BaseEmitter* emitter);
+
+//! \}
+//! \endcond
+
+ASMJIT_END_SUB_NAMESPACE
+
+#endif // ASMJIT_ARM_ARMEMITHELPER_P_H_INCLUDED
diff --git a/3rdparty/asmjit/src/asmjit/arm/a64emitter.h b/3rdparty/asmjit/src/asmjit/arm/a64emitter.h
new file mode 100644
index 00000000000..54354eaca84
--- /dev/null
+++ b/3rdparty/asmjit/src/asmjit/arm/a64emitter.h
@@ -0,0 +1,1228 @@
+// This file is part of AsmJit project <https://asmjit.com>
+//
+// See asmjit.h or LICENSE.md for license and copyright information
+// SPDX-License-Identifier: Zlib
+
+#ifndef ASMJIT_ARM_A64EMITTER_H_INCLUDED
+#define ASMJIT_ARM_A64EMITTER_H_INCLUDED
+
+#include "../core/emitter.h"
+#include "../core/support.h"
+#include "../arm/a64instdb.h"
+#include "../arm/a64operand.h"
+
+ASMJIT_BEGIN_SUB_NAMESPACE(a64)
+
+#define ASMJIT_INST_0x(NAME, ID) \
+ inline Error NAME() { return _emitter()->_emitI(Inst::kId##ID); }
+
+#define ASMJIT_INST_1x(NAME, ID, T0) \
+ inline Error NAME(const T0& o0) { return _emitter()->_emitI(Inst::kId##ID, o0); }
+
+#define ASMJIT_INST_2x(NAME, ID, T0, T1) \
+ inline Error NAME(const T0& o0, const T1& o1) { return _emitter()->_emitI(Inst::kId##ID, o0, o1); }
+
+#define ASMJIT_INST_3x(NAME, ID, T0, T1, T2) \
+ inline Error NAME(const T0& o0, const T1& o1, const T2& o2) { return _emitter()->_emitI(Inst::kId##ID, o0, o1, o2); }
+
+#define ASMJIT_INST_4x(NAME, ID, T0, T1, T2, T3) \
+ inline Error NAME(const T0& o0, const T1& o1, const T2& o2, const T3& o3) { return _emitter()->_emitI(Inst::kId##ID, o0, o1, o2, o3); }
+
+#define ASMJIT_INST_5x(NAME, ID, T0, T1, T2, T3, T4) \
+ inline Error NAME(const T0& o0, const T1& o1, const T2& o2, const T3& o3, const T4& o4) { return _emitter()->_emitI(Inst::kId##ID, o0, o1, o2, o3, o4); }
+
+#define ASMJIT_INST_6x(NAME, ID, T0, T1, T2, T3, T4, T5) \
+ inline Error NAME(const T0& o0, const T1& o1, const T2& o2, const T3& o3, const T4& o4, const T5& o5) { return _emitter()->_emitI(Inst::kId##ID, o0, o1, o2, o3, o4, o5); }
+
+#define ASMJIT_INST_1cc(NAME, ID, T0) \
+ inline Error NAME(const T0& o0) { return _emitter()->_emitI(Inst::kId##ID, o0); } \
+ \
+ inline Error NAME(CondCode cc, const T0& o0) { return _emitter()->_emitI(BaseInst::composeARMInstId(Inst::kId##ID, cc), o0); } \
+ \
+ inline Error NAME##_eq(const T0& o0) { return _emitter()->_emitI(BaseInst::composeARMInstId(Inst::kId##ID, CondCode::kEQ), o0); } \
+ inline Error NAME##_ne(const T0& o0) { return _emitter()->_emitI(BaseInst::composeARMInstId(Inst::kId##ID, CondCode::kNE), o0); } \
+ inline Error NAME##_cs(const T0& o0) { return _emitter()->_emitI(BaseInst::composeARMInstId(Inst::kId##ID, CondCode::kCS), o0); } \
+ inline Error NAME##_hs(const T0& o0) { return _emitter()->_emitI(BaseInst::composeARMInstId(Inst::kId##ID, CondCode::kHS), o0); } \
+ inline Error NAME##_cc(const T0& o0) { return _emitter()->_emitI(BaseInst::composeARMInstId(Inst::kId##ID, CondCode::kCC), o0); } \
+ inline Error NAME##_lo(const T0& o0) { return _emitter()->_emitI(BaseInst::composeARMInstId(Inst::kId##ID, CondCode::kLO), o0); } \
+ inline Error NAME##_mi(const T0& o0) { return _emitter()->_emitI(BaseInst::composeARMInstId(Inst::kId##ID, CondCode::kMI), o0); } \
+ inline Error NAME##_pl(const T0& o0) { return _emitter()->_emitI(BaseInst::composeARMInstId(Inst::kId##ID, CondCode::kPL), o0); } \
+ inline Error NAME##_vs(const T0& o0) { return _emitter()->_emitI(BaseInst::composeARMInstId(Inst::kId##ID, CondCode::kVS), o0); } \
+ inline Error NAME##_vc(const T0& o0) { return _emitter()->_emitI(BaseInst::composeARMInstId(Inst::kId##ID, CondCode::kVC), o0); } \
+ inline Error NAME##_hi(const T0& o0) { return _emitter()->_emitI(BaseInst::composeARMInstId(Inst::kId##ID, CondCode::kHI), o0); } \
+ inline Error NAME##_ls(const T0& o0) { return _emitter()->_emitI(BaseInst::composeARMInstId(Inst::kId##ID, CondCode::kLS), o0); } \
+ inline Error NAME##_ge(const T0& o0) { return _emitter()->_emitI(BaseInst::composeARMInstId(Inst::kId##ID, CondCode::kGE), o0); } \
+ inline Error NAME##_lt(const T0& o0) { return _emitter()->_emitI(BaseInst::composeARMInstId(Inst::kId##ID, CondCode::kLT), o0); } \
+ inline Error NAME##_gt(const T0& o0) { return _emitter()->_emitI(BaseInst::composeARMInstId(Inst::kId##ID, CondCode::kGT), o0); } \
+ inline Error NAME##_le(const T0& o0) { return _emitter()->_emitI(BaseInst::composeARMInstId(Inst::kId##ID, CondCode::kLE), o0); } \
+ inline Error NAME##_al(const T0& o0) { return _emitter()->_emitI(BaseInst::composeARMInstId(Inst::kId##ID, CondCode::kAL), o0); }
+
+//! \addtogroup asmjit_a64
+//! \{
+
+//! ARM emitter.
+//!
+//! NOTE: This class cannot be instantiated, you can only cast to it and use it as emitter that emits to either
+//! \ref Assembler, \ref Builder, or \ref Compiler (use withcaution with \ref Compiler as it expects virtual
+//! registers to be used).
+template<typename This>
+struct EmitterExplicitT {
+ //! \cond
+
+ // These two are unfortunately reported by the sanitizer. We know what we do, however, the sanitizer doesn't.
+ // I have tried to use reinterpret_cast instead, but that would generate bad code when compiled by MSC.
+ ASMJIT_ATTRIBUTE_NO_SANITIZE_UNDEF inline This* _emitter() noexcept { return static_cast<This*>(this); }
+ ASMJIT_ATTRIBUTE_NO_SANITIZE_UNDEF inline const This* _emitter() const noexcept { return static_cast<const This*>(this); }
+
+ //! \endcond
+
+ // --------------------------------------------------------------------------
+ // [Options]
+ // --------------------------------------------------------------------------
+
+protected:
+ inline This& _addInstOptions(InstOptions options) noexcept {
+ static_cast<This*>(this)->addInstOptions(options);
+ return *static_cast<This*>(this);
+ }
+
+public:
+ //! \name General Purpose Instructions
+ //! \{
+
+ ASMJIT_INST_3x(adc, Adc, Gp, Gp, Gp)
+ ASMJIT_INST_3x(adcs, Adcs, Gp, Gp, Gp)
+
+ ASMJIT_INST_3x(add, Add, Gp, Gp, Gp)
+ ASMJIT_INST_4x(add, Add, Gp, Gp, Gp, Imm)
+ ASMJIT_INST_3x(add, Add, Gp, Gp, Imm)
+ ASMJIT_INST_4x(add, Add, Gp, Gp, Imm, Imm)
+ ASMJIT_INST_3x(adds, Adds, Gp, Gp, Gp)
+ ASMJIT_INST_3x(adds, Adds, Gp, Gp, Imm)
+ ASMJIT_INST_4x(adds, Adds, Gp, Gp, Gp, Imm)
+ ASMJIT_INST_4x(adds, Adds, Gp, Gp, Imm, Imm)
+
+ ASMJIT_INST_2x(adr, Adr, Gp, Imm)
+ ASMJIT_INST_2x(adr, Adr, Gp, Label)
+ ASMJIT_INST_2x(adrp, Adrp, Gp, Imm)
+ ASMJIT_INST_2x(adrp, Adrp, Gp, Label)
+
+ ASMJIT_INST_3x(and_, And, Gp, Gp, Imm)
+ ASMJIT_INST_3x(and_, And, Gp, Gp, Gp)
+ ASMJIT_INST_4x(and_, And, Gp, Gp, Gp, Imm)
+ ASMJIT_INST_3x(ands, Ands, Gp, Gp, Imm)
+ ASMJIT_INST_3x(ands, Ands, Gp, Gp, Gp)
+ ASMJIT_INST_4x(ands, Ands, Gp, Gp, Gp, Imm)
+
+ ASMJIT_INST_3x(asr, Asr, Gp, Gp, Imm)
+ ASMJIT_INST_3x(asr, Asr, Gp, Gp, Gp)
+ ASMJIT_INST_3x(asrv, Asrv, Gp, Gp, Gp)
+
+ ASMJIT_INST_2x(at, At, Imm, Gp)
+
+ ASMJIT_INST_3x(bfc, Bfc, Gp, Imm, Imm)
+ ASMJIT_INST_4x(bfi, Bfi, Gp, Gp, Imm, Imm)
+ ASMJIT_INST_4x(bfm, Bfm, Gp, Gp, Imm, Imm)
+ ASMJIT_INST_4x(bfxil, Bfxil, Gp, Gp, Imm, Imm)
+
+ ASMJIT_INST_3x(bic, Bic, Gp, Gp, Imm);
+ ASMJIT_INST_3x(bic, Bic, Gp, Gp, Gp);
+ ASMJIT_INST_4x(bic, Bic, Gp, Gp, Gp, Imm);
+ ASMJIT_INST_3x(bics, Bics, Gp, Gp, Imm);
+ ASMJIT_INST_3x(bics, Bics, Gp, Gp, Gp);
+ ASMJIT_INST_4x(bics, Bics, Gp, Gp, Gp, Imm);
+
+ ASMJIT_INST_1x(brk, Brk, Imm)
+
+ ASMJIT_INST_4x(ccmn, Ccmn, Gp, Gp, Imm, Imm);
+ ASMJIT_INST_4x(ccmn, Ccmn, Gp, Imm, Imm, Imm);
+ ASMJIT_INST_4x(ccmp, Ccmp, Gp, Gp, Imm, Imm);
+ ASMJIT_INST_4x(ccmp, Ccmp, Gp, Imm, Imm, Imm);
+
+ ASMJIT_INST_3x(cinc, Cinc, Gp, Gp, Imm);
+ ASMJIT_INST_3x(cinv, Cinv, Gp, Gp, Imm);
+
+ ASMJIT_INST_1x(clrex, Clrex, Imm)
+
+ ASMJIT_INST_2x(cls, Cls, Gp, Gp)
+ ASMJIT_INST_2x(clz, Clz, Gp, Gp)
+
+ ASMJIT_INST_2x(cmn, Cmn, Gp, Gp)
+ ASMJIT_INST_3x(cmn, Cmn, Gp, Gp, Imm)
+ ASMJIT_INST_2x(cmn, Cmn, Gp, Imm)
+ ASMJIT_INST_3x(cmn, Cmn, Gp, Imm, Imm)
+ ASMJIT_INST_2x(cmp, Cmp, Gp, Gp)
+ ASMJIT_INST_3x(cmp, Cmp, Gp, Gp, Imm)
+ ASMJIT_INST_2x(cmp, Cmp, Gp, Imm)
+ ASMJIT_INST_3x(cmp, Cmp, Gp, Imm, Imm)
+
+ ASMJIT_INST_3x(cneg, Cneg, Gp, Gp, Imm);
+
+ ASMJIT_INST_4x(csel, Csel, Gp, Gp, Gp, Imm);
+ ASMJIT_INST_2x(cset, Cset, Gp, Imm);
+ ASMJIT_INST_2x(csetm, Csetm, Gp, Imm);
+
+ ASMJIT_INST_4x(csinc, Csinc, Gp, Gp, Gp, Imm);
+ ASMJIT_INST_4x(csinv, Csinv, Gp, Gp, Gp, Imm);
+ ASMJIT_INST_4x(csneg, Csneg, Gp, Gp, Gp, Imm);
+
+ ASMJIT_INST_2x(dc, Dc, Imm, Gp)
+ ASMJIT_INST_1x(dmb, Dmb, Imm)
+ ASMJIT_INST_1x(dsb, Dsb, Imm)
+ ASMJIT_INST_0x(drps, Drps)
+
+ ASMJIT_INST_3x(eon, Eon, Gp, Gp, Gp)
+ ASMJIT_INST_4x(eon, Eon, Gp, Gp, Gp, Imm)
+
+ ASMJIT_INST_3x(eor, Eor, Gp, Gp, Imm)
+ ASMJIT_INST_3x(eor, Eor, Gp, Gp, Gp)
+ ASMJIT_INST_4x(eor, Eor, Gp, Gp, Gp, Imm)
+
+ ASMJIT_INST_0x(eret, Eret)
+ ASMJIT_INST_0x(esb, Esb)
+
+ ASMJIT_INST_4x(extr, Extr, Gp, Gp, Gp, Imm)
+
+ ASMJIT_INST_1x(hlt, Hlt, Imm)
+ ASMJIT_INST_1x(hvc, Hvc, Imm)
+ ASMJIT_INST_2x(ic, Ic, Imm, Gp)
+ ASMJIT_INST_1x(isb, Isb, Imm)
+
+ ASMJIT_INST_3x(lsl, Lsl, Gp, Gp, Imm)
+ ASMJIT_INST_3x(lsl, Lsl, Gp, Gp, Gp)
+ ASMJIT_INST_3x(lslv, Lslv, Gp, Gp, Gp)
+
+ ASMJIT_INST_3x(lsr, Lsr, Gp, Gp, Imm)
+ ASMJIT_INST_3x(lsr, Lsr, Gp, Gp, Gp)
+ ASMJIT_INST_3x(lsrv, Lsrv, Gp, Gp, Gp)
+
+ ASMJIT_INST_4x(madd, Madd, Gp, Gp, Gp, Gp)
+ ASMJIT_INST_3x(mneg, Mneg, Gp, Gp, Gp)
+
+ ASMJIT_INST_2x(mov, Mov, Gp, Gp)
+ ASMJIT_INST_2x(mov, Mov, Gp, Imm)
+ ASMJIT_INST_2x(movk, Movk, Gp, Imm)
+ ASMJIT_INST_3x(movk, Movk, Gp, Imm, Imm)
+ ASMJIT_INST_2x(movn, Movn, Gp, Imm)
+ ASMJIT_INST_3x(movn, Movn, Gp, Imm, Imm)
+ ASMJIT_INST_2x(movz, Movz, Gp, Imm)
+ ASMJIT_INST_3x(movz, Movz, Gp, Imm, Imm)
+
+ ASMJIT_INST_2x(mrs, Mrs, Gp, Imm)
+ ASMJIT_INST_2x(msr, Msr, Imm, Gp)
+ ASMJIT_INST_2x(msr, Msr, Imm, Imm)
+
+ ASMJIT_INST_4x(msub, Msub, Gp, Gp, Gp, Gp)
+ ASMJIT_INST_3x(mul, Mul, Gp, Gp, Gp)
+
+ ASMJIT_INST_2x(mvn, Mvn, Gp, Gp)
+ ASMJIT_INST_3x(mvn, Mvn, Gp, Gp, Imm)
+
+ ASMJIT_INST_2x(neg, Neg, Gp, Gp)
+ ASMJIT_INST_3x(neg, Neg, Gp, Gp, Imm)
+ ASMJIT_INST_2x(negs, Negs, Gp, Gp)
+ ASMJIT_INST_3x(negs, Negs, Gp, Gp, Imm)
+
+ ASMJIT_INST_2x(ngc, Ngc, Gp, Gp)
+ ASMJIT_INST_2x(ngcs, Ngcs, Gp, Gp)
+
+ ASMJIT_INST_3x(orn, Orn, Gp, Gp, Gp)
+ ASMJIT_INST_4x(orn, Orn, Gp, Gp, Gp, Imm)
+
+ ASMJIT_INST_3x(orr, Orr, Gp, Gp, Imm)
+ ASMJIT_INST_3x(orr, Orr, Gp, Gp, Gp)
+ ASMJIT_INST_4x(orr, Orr, Gp, Gp, Gp, Imm)
+
+ ASMJIT_INST_2x(rbit, Rbit, Gp, Gp)
+ ASMJIT_INST_1x(ret, Ret, Gp)
+
+ ASMJIT_INST_2x(rev, Rev, Gp, Gp)
+ ASMJIT_INST_2x(rev16, Rev16, Gp, Gp)
+ ASMJIT_INST_2x(rev32, Rev32, Gp, Gp)
+ ASMJIT_INST_2x(rev64, Rev64, Gp, Gp)
+
+ ASMJIT_INST_3x(ror, Ror, Gp, Gp, Imm)
+ ASMJIT_INST_3x(ror, Ror, Gp, Gp, Gp)
+ ASMJIT_INST_3x(rorv, Rorv, Gp, Gp, Gp)
+
+ ASMJIT_INST_3x(sbc, Sbc, Gp, Gp, Gp)
+ ASMJIT_INST_3x(sbcs, Sbcs, Gp, Gp, Gp)
+
+ ASMJIT_INST_4x(sbfiz, Sbfiz, Gp, Gp, Imm, Imm)
+ ASMJIT_INST_4x(sbfm, Sbfm, Gp, Gp, Imm, Imm)
+ ASMJIT_INST_4x(sbfx, Sbfx, Gp, Gp, Imm, Imm)
+
+ ASMJIT_INST_3x(sdiv, Sdiv, Gp, Gp, Gp)
+
+ ASMJIT_INST_4x(smaddl, Smaddl, Gp, Gp, Gp, Gp)
+ ASMJIT_INST_1x(smc, Smc, Imm)
+ ASMJIT_INST_3x(smnegl, Smnegl, Gp, Gp, Gp)
+ ASMJIT_INST_4x(smsubl, Smsubl, Gp, Gp, Gp, Gp)
+ ASMJIT_INST_3x(smulh, Smulh, Gp, Gp, Gp)
+ ASMJIT_INST_3x(smull, Smull, Gp, Gp, Gp)
+
+ ASMJIT_INST_3x(sub, Sub, Gp, Gp, Gp)
+ ASMJIT_INST_4x(sub, Sub, Gp, Gp, Gp, Imm)
+ ASMJIT_INST_3x(sub, Sub, Gp, Gp, Imm)
+ ASMJIT_INST_4x(sub, Sub, Gp, Gp, Imm, Imm)
+ ASMJIT_INST_3x(subs, Subs, Gp, Gp, Gp)
+ ASMJIT_INST_4x(subs, Subs, Gp, Gp, Gp, Imm)
+ ASMJIT_INST_3x(subs, Subs, Gp, Gp, Imm)
+ ASMJIT_INST_4x(subs, Subs, Gp, Gp, Imm, Imm)
+
+ ASMJIT_INST_1x(svc, Svc, Imm)
+
+ ASMJIT_INST_2x(sxtb, Sxtb, Gp, Gp)
+ ASMJIT_INST_2x(sxth, Sxth, Gp, Gp)
+ ASMJIT_INST_2x(sxtw, Sxtw, Gp, Gp)
+
+ ASMJIT_INST_4x(sys, Sys, Imm, Imm, Imm, Imm)
+ ASMJIT_INST_5x(sys, Sys, Imm, Imm, Imm, Imm, Gp)
+
+ ASMJIT_INST_2x(tlbi, Tlbi, Imm, Gp)
+ ASMJIT_INST_2x(tst, Tst, Gp, Imm)
+ ASMJIT_INST_2x(tst, Tst, Gp, Gp)
+ ASMJIT_INST_3x(tst, Tst, Gp, Gp, Imm)
+
+ ASMJIT_INST_3x(udiv, Udiv, Gp, Gp, Gp)
+
+ ASMJIT_INST_4x(ubfiz, Ubfiz, Gp, Gp, Imm, Imm)
+ ASMJIT_INST_4x(ubfm, Ubfm, Gp, Gp, Imm, Imm)
+ ASMJIT_INST_4x(ubfx, Ubfx, Gp, Gp, Imm, Imm)
+
+ ASMJIT_INST_4x(umaddl, Umaddl, Gp, Gp, Gp, Gp)
+ ASMJIT_INST_3x(umnegl, Umnegl, Gp, Gp, Gp)
+ ASMJIT_INST_4x(umsubl, Umsubl, Gp, Gp, Gp, Gp)
+ ASMJIT_INST_3x(umull, Umull, Gp, Gp, Gp)
+ ASMJIT_INST_3x(umulh, Umulh, Gp, Gp, Gp)
+
+ ASMJIT_INST_2x(uxtb, Uxtb, Gp, Gp)
+ ASMJIT_INST_2x(uxth, Uxth, Gp, Gp)
+
+ ASMJIT_INST_0x(csdb, Csdb)
+ ASMJIT_INST_1x(dcps1, Dcps1, Imm)
+ ASMJIT_INST_1x(dcps2, Dcps2, Imm)
+ ASMJIT_INST_1x(dcps3, Dcps3, Imm)
+ ASMJIT_INST_0x(dgh, Dgh)
+ ASMJIT_INST_0x(pssbb, Pssbb)
+ ASMJIT_INST_0x(ssbb, Ssbb)
+ ASMJIT_INST_1x(udf, Udf, Imm)
+ ASMJIT_INST_1x(setf8, Setf8, Gp)
+ ASMJIT_INST_1x(setf16, Setf16, Gp)
+
+ //! \}
+
+ //! \name ARMv8.4 Instructions
+ //! \{
+
+ ASMJIT_INST_0x(cfinv, Cfinv)
+
+ //! \}
+
+ //! \name ARMv8.5 Instructions
+ //! \{
+
+ ASMJIT_INST_0x(axflag, Axflag)
+ ASMJIT_INST_0x(xaflag, Xaflag)
+
+ //! \}
+
+ //! \name Branch Instructions
+ //! \{
+
+ ASMJIT_INST_1cc(b, B, Imm)
+ ASMJIT_INST_1cc(b, B, Label)
+ ASMJIT_INST_1x(bl, Bl, Imm)
+ ASMJIT_INST_1x(bl, Bl, Label)
+ ASMJIT_INST_1x(blr, Blr, Gp)
+ ASMJIT_INST_1x(br, Br, Gp)
+ ASMJIT_INST_2x(cbz, Cbz, Gp, Imm)
+ ASMJIT_INST_2x(cbz, Cbz, Gp, Label)
+ ASMJIT_INST_2x(cbnz, Cbnz, Gp, Imm)
+ ASMJIT_INST_2x(cbnz, Cbnz, Gp, Label)
+ ASMJIT_INST_3x(tbnz, Tbnz, Gp, Imm, Imm)
+ ASMJIT_INST_3x(tbnz, Tbnz, Gp, Imm, Label)
+ ASMJIT_INST_3x(tbz, Tbz, Gp, Imm, Imm)
+ ASMJIT_INST_3x(tbz, Tbz, Gp, Imm, Label)
+
+ //! \}
+
+ //! \name Load & Store Instructions
+ //! \{
+
+ ASMJIT_INST_3x(cas, Cas, Gp, Gp, Mem)
+ ASMJIT_INST_3x(casa, Casa, Gp, Gp, Mem)
+ ASMJIT_INST_3x(casab, Casab, Gp, Gp, Mem)
+ ASMJIT_INST_3x(casah, Casah, Gp, Gp, Mem)
+ ASMJIT_INST_3x(casal, Casal, Gp, Gp, Mem)
+ ASMJIT_INST_3x(casalb, Casalb, Gp, Gp, Mem)
+ ASMJIT_INST_3x(casalh, Casalh, Gp, Gp, Mem)
+ ASMJIT_INST_3x(casb, Casb, Gp, Gp, Mem)
+ ASMJIT_INST_3x(cash, Cash, Gp, Gp, Mem)
+ ASMJIT_INST_3x(casl, Casl, Gp, Gp, Mem)
+ ASMJIT_INST_3x(caslb, Caslb, Gp, Gp, Mem)
+ ASMJIT_INST_3x(caslh, Caslh, Gp, Gp, Mem)
+
+ ASMJIT_INST_5x(casp, Casp, Gp, Gp, Gp, Gp, Mem)
+ ASMJIT_INST_5x(caspa, Caspa, Gp, Gp, Gp, Gp, Mem)
+ ASMJIT_INST_5x(caspal, Caspal, Gp, Gp, Gp, Gp, Mem)
+ ASMJIT_INST_5x(caspl, Caspl, Gp, Gp, Gp, Gp, Mem)
+
+ ASMJIT_INST_3x(ldadd, Ldadd, Gp, Gp, Mem)
+ ASMJIT_INST_3x(ldadda, Ldadda, Gp, Gp, Mem)
+ ASMJIT_INST_3x(ldaddab, Ldaddab, Gp, Gp, Mem)
+ ASMJIT_INST_3x(ldaddah, Ldaddah, Gp, Gp, Mem)
+ ASMJIT_INST_3x(ldaddal, Ldaddal, Gp, Gp, Mem)
+ ASMJIT_INST_3x(ldaddalb, Ldaddalb, Gp, Gp, Mem)
+ ASMJIT_INST_3x(ldaddalh, Ldaddalh, Gp, Gp, Mem)
+ ASMJIT_INST_3x(ldaddb, Ldaddb, Gp, Gp, Mem)
+ ASMJIT_INST_3x(ldaddh, Ldaddh, Gp, Gp, Mem)
+ ASMJIT_INST_3x(ldaddl, Ldaddl, Gp, Gp, Mem)
+ ASMJIT_INST_3x(ldaddlb, Ldaddlb, Gp, Gp, Mem)
+ ASMJIT_INST_3x(ldaddlh, Ldaddlh, Gp, Gp, Mem)
+
+ ASMJIT_INST_2x(ldar, Ldar, Gp, Mem)
+ ASMJIT_INST_2x(ldarb, Ldarb, Gp, Mem)
+ ASMJIT_INST_2x(ldarh, Ldarh, Gp, Mem)
+
+ ASMJIT_INST_2x(ldaxr, Ldaxr, Gp, Mem)
+ ASMJIT_INST_2x(ldaxrb, Ldaxrb, Gp, Mem)
+ ASMJIT_INST_2x(ldaxrh, Ldaxrh, Gp, Mem)
+
+ ASMJIT_INST_3x(ldclr, Ldclr, Gp, Gp, Mem)
+ ASMJIT_INST_3x(ldclra, Ldclra, Gp, Gp, Mem)
+ ASMJIT_INST_3x(ldclrab, Ldclrab, Gp, Gp, Mem)
+ ASMJIT_INST_3x(ldclrah, Ldclrah, Gp, Gp, Mem)
+ ASMJIT_INST_3x(ldclral, Ldclral, Gp, Gp, Mem)
+ ASMJIT_INST_3x(ldclralb, Ldclralb, Gp, Gp, Mem)
+ ASMJIT_INST_3x(ldclralh, Ldclralh, Gp, Gp, Mem)
+ ASMJIT_INST_3x(ldclrb, Ldclrb, Gp, Gp, Mem)
+ ASMJIT_INST_3x(ldclrh, Ldclrh, Gp, Gp, Mem)
+ ASMJIT_INST_3x(ldclrl, Ldclrl, Gp, Gp, Mem)
+ ASMJIT_INST_3x(ldclrlb, Ldclrlb, Gp, Gp, Mem)
+ ASMJIT_INST_3x(ldclrlh, Ldclrlh, Gp, Gp, Mem)
+
+ ASMJIT_INST_3x(ldeor, Ldeor, Gp, Gp, Mem)
+ ASMJIT_INST_3x(ldeora, Ldeora, Gp, Gp, Mem)
+ ASMJIT_INST_3x(ldeorab, Ldeorab, Gp, Gp, Mem)
+ ASMJIT_INST_3x(ldeorah, Ldeorah, Gp, Gp, Mem)
+ ASMJIT_INST_3x(ldeoral, Ldeoral, Gp, Gp, Mem)
+ ASMJIT_INST_3x(ldeoralb, Ldeoralb, Gp, Gp, Mem)
+ ASMJIT_INST_3x(ldeoralh, Ldeoralh, Gp, Gp, Mem)
+ ASMJIT_INST_3x(ldeorb, Ldeorb, Gp, Gp, Mem)
+ ASMJIT_INST_3x(ldeorh, Ldeorh, Gp, Gp, Mem)
+ ASMJIT_INST_3x(ldeorl, Ldeorl, Gp, Gp, Mem)
+ ASMJIT_INST_3x(ldeorlb, Ldeorlb, Gp, Gp, Mem)
+ ASMJIT_INST_3x(ldeorlh, Ldeorlh, Gp, Gp, Mem)
+
+ ASMJIT_INST_2x(ldlar, Ldlar, Gp, Mem)
+ ASMJIT_INST_2x(ldlarb, Ldlarb, Gp, Mem)
+ ASMJIT_INST_2x(ldlarh, Ldlarh, Gp, Mem)
+
+ ASMJIT_INST_3x(ldnp, Ldnp, Gp, Gp, Mem)
+
+ ASMJIT_INST_3x(ldp, Ldp, Gp, Gp, Mem)
+ ASMJIT_INST_3x(ldpsw, Ldpsw, Gp, Gp, Mem)
+
+ ASMJIT_INST_2x(ldr, Ldr, Gp, Mem)
+ ASMJIT_INST_2x(ldrb, Ldrb, Gp, Mem)
+ ASMJIT_INST_2x(ldrh, Ldrh, Gp, Mem)
+ ASMJIT_INST_2x(ldrsb, Ldrsb, Gp, Mem)
+ ASMJIT_INST_2x(ldrsh, Ldrsh, Gp, Mem)
+ ASMJIT_INST_2x(ldrsw, Ldrsw, Gp, Mem)
+
+ ASMJIT_INST_3x(ldset, Ldset, Gp, Gp, Mem)
+ ASMJIT_INST_3x(ldseta, Ldseta, Gp, Gp, Mem)
+ ASMJIT_INST_3x(ldsetab, Ldsetab, Gp, Gp, Mem)
+ ASMJIT_INST_3x(ldsetah, Ldsetah, Gp, Gp, Mem)
+ ASMJIT_INST_3x(ldsetal, Ldsetal, Gp, Gp, Mem)
+ ASMJIT_INST_3x(ldsetalb, Ldsetalb, Gp, Gp, Mem)
+ ASMJIT_INST_3x(ldsetalh, Ldsetalh, Gp, Gp, Mem)
+ ASMJIT_INST_3x(ldsetb, Ldsetb, Gp, Gp, Mem)
+ ASMJIT_INST_3x(ldseth, Ldseth, Gp, Gp, Mem)
+ ASMJIT_INST_3x(ldsetl, Ldsetl, Gp, Gp, Mem)
+ ASMJIT_INST_3x(ldsetlb, Ldsetlb, Gp, Gp, Mem)
+ ASMJIT_INST_3x(ldsetlh, Ldsetlh, Gp, Gp, Mem)
+
+ ASMJIT_INST_3x(ldsmax, Ldsmax, Gp, Gp, Mem)
+ ASMJIT_INST_3x(ldsmaxa, Ldsmaxa, Gp, Gp, Mem)
+ ASMJIT_INST_3x(ldsmaxab, Ldsmaxab, Gp, Gp, Mem)
+ ASMJIT_INST_3x(ldsmaxah, Ldsmaxah, Gp, Gp, Mem)
+ ASMJIT_INST_3x(ldsmaxal, Ldsmaxal, Gp, Gp, Mem)
+ ASMJIT_INST_3x(ldsmaxalb, Ldsmaxalb, Gp, Gp, Mem)
+ ASMJIT_INST_3x(ldsmaxalh, Ldsmaxalh, Gp, Gp, Mem)
+ ASMJIT_INST_3x(ldsmaxb, Ldsmaxb, Gp, Gp, Mem)
+ ASMJIT_INST_3x(ldsmaxh, Ldsmaxh, Gp, Gp, Mem)
+ ASMJIT_INST_3x(ldsmaxl, Ldsmaxl, Gp, Gp, Mem)
+ ASMJIT_INST_3x(ldsmaxlb, Ldsmaxlb, Gp, Gp, Mem)
+ ASMJIT_INST_3x(ldsmaxlh, Ldsmaxlh, Gp, Gp, Mem)
+
+ ASMJIT_INST_3x(ldsmin, Ldsmin, Gp, Gp, Mem)
+ ASMJIT_INST_3x(ldsmina, Ldsmina, Gp, Gp, Mem)
+ ASMJIT_INST_3x(ldsminab, Ldsminab, Gp, Gp, Mem)
+ ASMJIT_INST_3x(ldsminah, Ldsminah, Gp, Gp, Mem)
+ ASMJIT_INST_3x(ldsminal, Ldsminal, Gp, Gp, Mem)
+ ASMJIT_INST_3x(ldsminalb, Ldsminalb, Gp, Gp, Mem)
+ ASMJIT_INST_3x(ldsminalh, Ldsminalh, Gp, Gp, Mem)
+ ASMJIT_INST_3x(ldsminb, Ldsminb, Gp, Gp, Mem)
+ ASMJIT_INST_3x(ldsminh, Ldsminh, Gp, Gp, Mem)
+ ASMJIT_INST_3x(ldsminl, Ldsminl, Gp, Gp, Mem)
+ ASMJIT_INST_3x(ldsminlb, Ldsminlb, Gp, Gp, Mem)
+ ASMJIT_INST_3x(ldsminlh, Ldsminlh, Gp, Gp, Mem)
+
+ ASMJIT_INST_2x(ldtr, Ldtr, Gp, Mem)
+ ASMJIT_INST_2x(ldtrb, Ldtrb, Gp, Mem)
+ ASMJIT_INST_2x(ldtrh, Ldtrh, Gp, Mem)
+ ASMJIT_INST_2x(ldtrsb, Ldtrsb, Gp, Mem)
+ ASMJIT_INST_2x(ldtrsh, Ldtrsh, Gp, Mem)
+ ASMJIT_INST_2x(ldtrsw, Ldtrsw, Gp, Mem)
+
+ ASMJIT_INST_3x(ldumax, Ldumax, Gp, Gp, Mem)
+ ASMJIT_INST_3x(ldumaxa, Ldumaxa, Gp, Gp, Mem)
+ ASMJIT_INST_3x(ldumaxab, Ldumaxab, Gp, Gp, Mem)
+ ASMJIT_INST_3x(ldumaxah, Ldumaxah, Gp, Gp, Mem)
+ ASMJIT_INST_3x(ldumaxal, Ldumaxal, Gp, Gp, Mem)
+ ASMJIT_INST_3x(ldumaxalb, Ldumaxalb, Gp, Gp, Mem)
+ ASMJIT_INST_3x(ldumaxalh, Ldumaxalh, Gp, Gp, Mem)
+ ASMJIT_INST_3x(ldumaxb, Ldumaxb, Gp, Gp, Mem)
+ ASMJIT_INST_3x(ldumaxh, Ldumaxh, Gp, Gp, Mem)
+ ASMJIT_INST_3x(ldumaxl, Ldumaxl, Gp, Gp, Mem)
+ ASMJIT_INST_3x(ldumaxlb, Ldumaxlb, Gp, Gp, Mem)
+ ASMJIT_INST_3x(ldumaxlh, Ldumaxlh, Gp, Gp, Mem)
+
+ ASMJIT_INST_3x(ldumin, Ldumin, Gp, Gp, Mem)
+ ASMJIT_INST_3x(ldumina, Ldumina, Gp, Gp, Mem)
+ ASMJIT_INST_3x(lduminab, Lduminab, Gp, Gp, Mem)
+ ASMJIT_INST_3x(lduminah, Lduminah, Gp, Gp, Mem)
+ ASMJIT_INST_3x(lduminal, Lduminal, Gp, Gp, Mem)
+ ASMJIT_INST_3x(lduminalb, Lduminalb, Gp, Gp, Mem)
+ ASMJIT_INST_3x(lduminalh, Lduminalh, Gp, Gp, Mem)
+ ASMJIT_INST_3x(lduminb, Lduminb, Gp, Gp, Mem)
+ ASMJIT_INST_3x(lduminh, Lduminh, Gp, Gp, Mem)
+ ASMJIT_INST_3x(lduminl, Lduminl, Gp, Gp, Mem)
+ ASMJIT_INST_3x(lduminlb, Lduminlb, Gp, Gp, Mem)
+ ASMJIT_INST_3x(lduminlh, Lduminlh, Gp, Gp, Mem)
+
+ ASMJIT_INST_2x(ldur, Ldur, Gp, Mem)
+ ASMJIT_INST_2x(ldurb, Ldurb, Gp, Mem)
+ ASMJIT_INST_2x(ldurh, Ldurh, Gp, Mem)
+ ASMJIT_INST_2x(ldursb, Ldursb, Gp, Mem)
+ ASMJIT_INST_2x(ldursh, Ldursh, Gp, Mem)
+ ASMJIT_INST_2x(ldursw, Ldursw, Gp, Mem)
+
+ ASMJIT_INST_3x(ldxp, Ldxp, Gp, Gp, Mem)
+ ASMJIT_INST_3x(ldaxp, Ldaxp, Gp, Gp, Mem)
+
+ ASMJIT_INST_2x(ldxr, Ldxr, Gp, Mem)
+ ASMJIT_INST_2x(ldxrb, Ldxrb, Gp, Mem)
+ ASMJIT_INST_2x(ldxrh, Ldxrh, Gp, Mem)
+
+ ASMJIT_INST_2x(stadd, Stadd, Gp, Mem)
+ ASMJIT_INST_2x(staddb, Staddb, Gp, Mem)
+ ASMJIT_INST_2x(staddh, Staddh, Gp, Mem)
+ ASMJIT_INST_2x(staddl, Staddl, Gp, Mem)
+ ASMJIT_INST_2x(staddlb, Staddlb, Gp, Mem)
+ ASMJIT_INST_2x(staddlh, Staddlh, Gp, Mem)
+
+ ASMJIT_INST_2x(stclr, Stclr, Gp, Mem)
+ ASMJIT_INST_2x(stclrb, Stclrb, Gp, Mem)
+ ASMJIT_INST_2x(stclrh, Stclrh, Gp, Mem)
+ ASMJIT_INST_2x(stclrl, Stclrl, Gp, Mem)
+ ASMJIT_INST_2x(stclrlb, Stclrlb, Gp, Mem)
+ ASMJIT_INST_2x(stclrlh, Stclrlh, Gp, Mem)
+
+ ASMJIT_INST_2x(steor, Steor, Gp, Mem)
+ ASMJIT_INST_2x(steorb, Steorb, Gp, Mem)
+ ASMJIT_INST_2x(steorh, Steorh, Gp, Mem)
+ ASMJIT_INST_2x(steorl, Steorl, Gp, Mem)
+ ASMJIT_INST_2x(steorlb, Steorlb, Gp, Mem)
+ ASMJIT_INST_2x(steorlh, Steorlh, Gp, Mem)
+
+ ASMJIT_INST_2x(stllr, Stllr, Gp, Mem)
+ ASMJIT_INST_2x(stllrb, Stllrb, Gp, Mem)
+ ASMJIT_INST_2x(stllrh, Stllrh, Gp, Mem)
+
+ ASMJIT_INST_2x(stlr, Stllr, Gp, Mem)
+ ASMJIT_INST_2x(stlrb, Stllrb, Gp, Mem)
+ ASMJIT_INST_2x(stlrh, Stllrh, Gp, Mem)
+
+ ASMJIT_INST_3x(stlxr, Stlxr, Gp, Gp, Mem)
+ ASMJIT_INST_3x(stlxrb, Stlxrb, Gp, Gp, Mem)
+ ASMJIT_INST_3x(stlxrh, Stlxrh, Gp, Gp, Mem)
+
+ ASMJIT_INST_3x(stnp, Stnp, Gp, Gp, Mem)
+ ASMJIT_INST_3x(stp, Stp, Gp, Gp, Mem)
+
+ ASMJIT_INST_2x(str, Str, Gp, Mem)
+ ASMJIT_INST_2x(strb, Strb, Gp, Mem)
+ ASMJIT_INST_2x(strh, Strh, Gp, Mem)
+
+ ASMJIT_INST_2x(stset, Stset, Gp, Mem)
+ ASMJIT_INST_2x(stsetb, Stsetb, Gp, Mem)
+ ASMJIT_INST_2x(stseth, Stseth, Gp, Mem)
+ ASMJIT_INST_2x(stsetl, Stsetl, Gp, Mem)
+ ASMJIT_INST_2x(stsetlb, Stsetlb, Gp, Mem)
+ ASMJIT_INST_2x(stsetlh, Stsetlh, Gp, Mem)
+
+ ASMJIT_INST_2x(stsmax, Stsmax, Gp, Mem)
+ ASMJIT_INST_2x(stsmaxb, Stsmaxb, Gp, Mem)
+ ASMJIT_INST_2x(stsmaxh, Stsmaxh, Gp, Mem)
+ ASMJIT_INST_2x(stsmaxl, Stsmaxl, Gp, Mem)
+ ASMJIT_INST_2x(stsmaxlb, Stsmaxlb, Gp, Mem)
+ ASMJIT_INST_2x(stsmaxlh, Stsmaxlh, Gp, Mem)
+
+ ASMJIT_INST_2x(stsmin, Stsmin, Gp, Mem)
+ ASMJIT_INST_2x(stsminb, Stsminb, Gp, Mem)
+ ASMJIT_INST_2x(stsminh, Stsminh, Gp, Mem)
+ ASMJIT_INST_2x(stsminl, Stsminl, Gp, Mem)
+ ASMJIT_INST_2x(stsminlb, Stsminlb, Gp, Mem)
+ ASMJIT_INST_2x(stsminlh, Stsminlh, Gp, Mem)
+
+ ASMJIT_INST_2x(sttr, Sttr, Gp, Mem)
+ ASMJIT_INST_2x(sttrb, Sttrb, Gp, Mem)
+ ASMJIT_INST_2x(sttrh, Sttrh, Gp, Mem)
+
+ ASMJIT_INST_2x(stumax, Stumax, Gp, Mem)
+ ASMJIT_INST_2x(stumaxb, Stumaxb, Gp, Mem)
+ ASMJIT_INST_2x(stumaxh, Stumaxh, Gp, Mem)
+ ASMJIT_INST_2x(stumaxl, Stumaxl, Gp, Mem)
+ ASMJIT_INST_2x(stumaxlb, Stumaxlb, Gp, Mem)
+ ASMJIT_INST_2x(stumaxlh, Stumaxlh, Gp, Mem)
+
+ ASMJIT_INST_2x(stumin, Stumin, Gp, Mem)
+ ASMJIT_INST_2x(stuminb, Stuminb, Gp, Mem)
+ ASMJIT_INST_2x(stuminh, Stuminh, Gp, Mem)
+ ASMJIT_INST_2x(stuminl, Stuminl, Gp, Mem)
+ ASMJIT_INST_2x(stuminlb, Stuminlb, Gp, Mem)
+ ASMJIT_INST_2x(stuminlh, Stuminlh, Gp, Mem)
+
+ ASMJIT_INST_2x(stur, Stur, Gp, Mem)
+ ASMJIT_INST_2x(sturb, Sturb, Gp, Mem)
+ ASMJIT_INST_2x(sturh, Sturh, Gp, Mem)
+
+ ASMJIT_INST_4x(stxp, Stxp, Gp, Gp, Gp, Mem)
+ ASMJIT_INST_4x(stlxp, Stlxp, Gp, Gp, Gp, Mem)
+
+ ASMJIT_INST_3x(stxr, Stxr, Gp, Gp, Mem)
+ ASMJIT_INST_3x(stxrb, Stxrb, Gp, Gp, Mem)
+ ASMJIT_INST_3x(stxrh, Stxrh, Gp, Gp, Mem)
+
+ ASMJIT_INST_3x(swp, Swp, Gp, Gp, Mem)
+ ASMJIT_INST_3x(swpa, Swpa, Gp, Gp, Mem)
+ ASMJIT_INST_3x(swpab, Swpab, Gp, Gp, Mem)
+ ASMJIT_INST_3x(swpah, Swpah, Gp, Gp, Mem)
+ ASMJIT_INST_3x(swpal, Swpal, Gp, Gp, Mem)
+ ASMJIT_INST_3x(swpalb, Swpalb, Gp, Gp, Mem)
+ ASMJIT_INST_3x(swpalh, Swpalh, Gp, Gp, Mem)
+ ASMJIT_INST_3x(swpb, Swpb, Gp, Gp, Mem)
+ ASMJIT_INST_3x(swph, Swph, Gp, Gp, Mem)
+ ASMJIT_INST_3x(swpl, Swpl, Gp, Gp, Mem)
+ ASMJIT_INST_3x(swplb, Swplb, Gp, Gp, Mem)
+ ASMJIT_INST_3x(swplh, Swplh, Gp, Gp, Mem)
+ //! \}
+
+ //! \name CRC Instructions (ARMv8.1-A, optional in ARMv8.0-A)
+ //! \{
+
+ ASMJIT_INST_3x(crc32b, Crc32b, Gp, Gp, Gp);
+ ASMJIT_INST_3x(crc32h, Crc32h, Gp, Gp, Gp);
+ ASMJIT_INST_3x(crc32w, Crc32w, Gp, Gp, Gp);
+ ASMJIT_INST_3x(crc32x, Crc32x, Gp, Gp, Gp);
+
+ ASMJIT_INST_3x(crc32cb, Crc32cb, Gp, Gp, Gp);
+ ASMJIT_INST_3x(crc32ch, Crc32ch, Gp, Gp, Gp);
+ ASMJIT_INST_3x(crc32cw, Crc32cw, Gp, Gp, Gp);
+ ASMJIT_INST_3x(crc32cx, Crc32cx, Gp, Gp, Gp);
+
+ //! \}
+
+ //! \name MTE Instructions
+ //! \{
+
+ ASMJIT_INST_2x(autda, Autda, Gp, Gp);
+ ASMJIT_INST_2x(autdb, Autdb, Gp, Gp);
+ ASMJIT_INST_1x(autdza, Autdza, Gp);
+ ASMJIT_INST_1x(autdzb, Autdzb, Gp);
+ ASMJIT_INST_2x(autia, Autia, Gp, Gp);
+ ASMJIT_INST_0x(autia1716, Autia1716);
+ ASMJIT_INST_0x(autiasp, Autiasp);
+ ASMJIT_INST_0x(autiaz, Autiaz);
+ ASMJIT_INST_2x(autib, Autib, Gp, Gp);
+ ASMJIT_INST_0x(autib1716, Autib1716);
+ ASMJIT_INST_0x(autibsp, Autibsp);
+ ASMJIT_INST_0x(autibz, Autibz);
+ ASMJIT_INST_1x(autiza, Autiza, Gp);
+ ASMJIT_INST_1x(autizb, Autizb, Gp);
+
+ ASMJIT_INST_3x(gmi, Gmi, Gp, Gp, Gp);
+
+ ASMJIT_INST_2x(cmpp, Cmpp, Gp, Gp);
+ ASMJIT_INST_4x(addg, Addg, Gp, Gp, Imm, Imm);
+
+ ASMJIT_INST_2x(ldg, Ldg, Gp, Mem)
+ ASMJIT_INST_2x(ldgm, Ldgm, Gp, Mem)
+ ASMJIT_INST_2x(ldraa, Ldraa, Gp, Mem)
+ ASMJIT_INST_2x(ldrab, Ldrab, Gp, Mem)
+
+ ASMJIT_INST_2x(pacda, Pacda, Gp, Gp);
+ ASMJIT_INST_2x(pacdb, Pacdb, Gp, Gp);
+ ASMJIT_INST_1x(pacdza, Pacdza, Gp);
+ ASMJIT_INST_1x(pacdzb, Pacdzb, Gp);
+ ASMJIT_INST_3x(pacga, Pacga, Gp, Gp, Gp);
+
+ ASMJIT_INST_3x(subp, Subp, Gp, Gp, Gp);
+ ASMJIT_INST_3x(subps, Subps, Gp, Gp, Gp);
+ ASMJIT_INST_4x(subg, Subg, Gp, Gp, Imm, Imm);
+
+ ASMJIT_INST_2x(st2g, St2g, Gp, Mem)
+ ASMJIT_INST_2x(stg, Stg, Gp, Mem)
+ ASMJIT_INST_3x(stgp, Stgp, Gp, Gp, Mem)
+ ASMJIT_INST_2x(stgm, Stgm, Gp, Mem)
+ ASMJIT_INST_2x(stzg, Stzg, Gp, Mem)
+ ASMJIT_INST_2x(stz2g, Stz2g, Gp, Mem)
+ ASMJIT_INST_2x(stzgm, Stzgm, Gp, Mem)
+
+ ASMJIT_INST_1x(xpacd, Xpacd, Gp);
+ ASMJIT_INST_1x(xpaci, Xpaci, Gp);
+ ASMJIT_INST_0x(xpaclri, Xpaclri);
+
+ //! \}
+
+ //! \name Hint Instructions
+ //! \{
+
+ ASMJIT_INST_1x(hint, Hint, Imm)
+ ASMJIT_INST_0x(nop, Nop)
+ ASMJIT_INST_0x(sev, Sev)
+ ASMJIT_INST_0x(sevl, Sevl)
+ ASMJIT_INST_0x(wfe, Wfe)
+ ASMJIT_INST_0x(wfi, Wfi)
+ ASMJIT_INST_0x(yield, Yield)
+
+ //! \}
+
+ //! \name SIMD & FP Instructions
+ //! \{
+
+ ASMJIT_INST_2x(abs, Abs_v, Vec, Vec);
+ ASMJIT_INST_3x(add, Add_v, Vec, Vec, Vec);
+ ASMJIT_INST_3x(addhn, Addhn_v, Vec, Vec, Vec);
+ ASMJIT_INST_3x(addhn2, Addhn2_v, Vec, Vec, Vec);
+ ASMJIT_INST_2x(addp, Addp_v, Vec, Vec);
+ ASMJIT_INST_3x(addp, Addp_v, Vec, Vec, Vec);
+ ASMJIT_INST_2x(addv, Addv_v, Vec, Vec);
+ ASMJIT_INST_3x(and_, And_v, Vec, Vec, Vec);
+ ASMJIT_INST_2x(bic, Bic_v, Vec, Imm);
+ ASMJIT_INST_3x(bic, Bic_v, Vec, Vec, Vec);
+ ASMJIT_INST_3x(bic, Bic_v, Vec, Imm, Imm);
+ ASMJIT_INST_3x(bif, Bif_v, Vec, Vec, Vec);
+ ASMJIT_INST_3x(bit, Bit_v, Vec, Vec, Vec);
+ ASMJIT_INST_3x(bsl, Bsl_v, Vec, Vec, Vec);
+ ASMJIT_INST_2x(cls, Cls_v, Vec, Vec);
+ ASMJIT_INST_2x(clz, Clz_v, Vec, Vec);
+ ASMJIT_INST_3x(cmeq, Cmeq_v, Vec, Vec, Vec);
+ ASMJIT_INST_3x(cmeq, Cmeq_v, Vec, Vec, Imm);
+ ASMJIT_INST_3x(cmge, Cmge_v, Vec, Vec, Vec);
+ ASMJIT_INST_3x(cmge, Cmge_v, Vec, Vec, Imm);
+ ASMJIT_INST_3x(cmgt, Cmgt_v, Vec, Vec, Vec);
+ ASMJIT_INST_3x(cmgt, Cmgt_v, Vec, Vec, Imm);
+ ASMJIT_INST_3x(cmhi, Cmhi_v, Vec, Vec, Vec);
+ ASMJIT_INST_3x(cmhs, Cmhs_v, Vec, Vec, Vec);
+ ASMJIT_INST_3x(cmle, Cmle_v, Vec, Vec, Imm);
+ ASMJIT_INST_3x(cmlt, Cmlt_v, Vec, Vec, Imm);
+ ASMJIT_INST_3x(cmtst, Cmtst_v, Vec, Vec, Vec);
+ ASMJIT_INST_2x(cnt, Cnt_v, Vec, Vec);
+ ASMJIT_INST_2x(dup, Dup_v, Vec, Gp);
+ ASMJIT_INST_2x(dup, Dup_v, Vec, Vec);
+ ASMJIT_INST_3x(eor, Eor_v, Vec, Vec, Vec);
+ ASMJIT_INST_4x(ext, Ext_v, Vec, Vec, Vec, Imm);
+ ASMJIT_INST_3x(fabd, Fabd_v, Vec, Vec, Vec);
+ ASMJIT_INST_2x(fabs, Fabs_v, Vec, Vec);
+ ASMJIT_INST_3x(facge, Facge_v, Vec, Vec, Vec);
+ ASMJIT_INST_3x(facgt, Facgt_v, Vec, Vec, Vec);
+ ASMJIT_INST_3x(fadd, Fadd_v, Vec, Vec, Vec);
+ ASMJIT_INST_2x(faddp, Faddp_v, Vec, Vec);
+ ASMJIT_INST_3x(faddp, Faddp_v, Vec, Vec, Vec);
+ ASMJIT_INST_4x(fccmp, Fccmp_v, Vec, Vec, Imm, Imm);
+ ASMJIT_INST_4x(fccmpe, Fccmpe_v, Vec, Vec, Imm, Imm);
+ ASMJIT_INST_3x(fcmeq, Fcmeq_v, Vec, Vec, Vec);
+ ASMJIT_INST_3x(fcmeq, Fcmeq_v, Vec, Vec, Imm);
+ ASMJIT_INST_3x(fcmge, Fcmge_v, Vec, Vec, Vec);
+ ASMJIT_INST_3x(fcmge, Fcmge_v, Vec, Vec, Imm);
+ ASMJIT_INST_3x(fcmgt, Fcmgt_v, Vec, Vec, Vec);
+ ASMJIT_INST_3x(fcmgt, Fcmgt_v, Vec, Vec, Imm);
+ ASMJIT_INST_3x(fcmle, Fcmle_v, Vec, Vec, Imm);
+ ASMJIT_INST_3x(fcmlt, Fcmlt_v, Vec, Vec, Imm);
+ ASMJIT_INST_2x(fcmp, Fcmp_v, Vec, Vec);
+ ASMJIT_INST_2x(fcmp, Fcmp_v, Vec, Imm);
+ ASMJIT_INST_2x(fcmpe, Fcmpe_v, Vec, Vec);
+ ASMJIT_INST_2x(fcmpe, Fcmpe_v, Vec, Imm);
+ ASMJIT_INST_4x(fcsel, Fcsel_v, Vec, Vec, Vec, Imm);
+ ASMJIT_INST_2x(fcvt, Fcvt_v, Vec, Vec);
+ ASMJIT_INST_2x(fcvtas, Fcvtas_v, Gp, Vec);
+ ASMJIT_INST_2x(fcvtas, Fcvtas_v, Vec, Vec);
+ ASMJIT_INST_2x(fcvtau, Fcvtau_v, Gp, Vec);
+ ASMJIT_INST_2x(fcvtau, Fcvtau_v, Vec, Vec);
+ ASMJIT_INST_2x(fcvtl, Fcvtl_v, Vec, Vec);
+ ASMJIT_INST_2x(fcvtl2, Fcvtl2_v, Vec, Vec);
+ ASMJIT_INST_2x(fcvtms, Fcvtms_v, Gp, Vec);
+ ASMJIT_INST_2x(fcvtms, Fcvtms_v, Vec, Vec);
+ ASMJIT_INST_2x(fcvtmu, Fcvtmu_v, Gp, Vec);
+ ASMJIT_INST_2x(fcvtmu, Fcvtmu_v, Vec, Vec);
+ ASMJIT_INST_2x(fcvtn, Fcvtn_v, Vec, Vec);
+ ASMJIT_INST_2x(fcvtn2, Fcvtn2_v, Vec, Vec);
+ ASMJIT_INST_2x(fcvtns, Fcvtns_v, Gp, Vec);
+ ASMJIT_INST_2x(fcvtns, Fcvtns_v, Vec, Vec);
+ ASMJIT_INST_2x(fcvtnu, Fcvtnu_v, Gp, Vec);
+ ASMJIT_INST_2x(fcvtnu, Fcvtnu_v, Vec, Vec);
+ ASMJIT_INST_2x(fcvtps, Fcvtps_v, Gp, Vec);
+ ASMJIT_INST_2x(fcvtps, Fcvtps_v, Vec, Vec);
+ ASMJIT_INST_2x(fcvtpu, Fcvtpu_v, Gp, Vec);
+ ASMJIT_INST_2x(fcvtpu, Fcvtpu_v, Vec, Vec);
+ ASMJIT_INST_2x(fcvtxn, Fcvtxn_v, Vec, Vec);
+ ASMJIT_INST_2x(fcvtxn2, Fcvtxn2_v, Vec, Vec);
+ ASMJIT_INST_2x(fcvtzs, Fcvtzs_v, Gp, Vec);
+ ASMJIT_INST_3x(fcvtzs, Fcvtzs_v, Gp, Vec, Imm);
+ ASMJIT_INST_2x(fcvtzs, Fcvtzs_v, Vec, Vec);
+ ASMJIT_INST_3x(fcvtzs, Fcvtzs_v, Vec, Vec, Imm);
+ ASMJIT_INST_2x(fcvtzu, Fcvtzu_v, Gp, Vec);
+ ASMJIT_INST_3x(fcvtzu, Fcvtzu_v, Gp, Vec, Imm);
+ ASMJIT_INST_2x(fcvtzu, Fcvtzu_v, Vec, Vec);
+ ASMJIT_INST_3x(fcvtzu, Fcvtzu_v, Vec, Vec, Imm);
+ ASMJIT_INST_3x(fdiv, Fdiv_v, Vec, Vec, Vec);
+ ASMJIT_INST_4x(fmadd, Fmadd_v, Vec, Vec, Vec, Vec);
+ ASMJIT_INST_3x(fmax, Fmax_v, Vec, Vec, Vec);
+ ASMJIT_INST_3x(fmaxnm, Fmaxnm_v, Vec, Vec, Vec);
+ ASMJIT_INST_3x(fmaxnmp, Fmaxnmp_v, Vec, Vec, Vec);
+ ASMJIT_INST_2x(fmaxnmp, Fmaxnmp_v, Vec, Vec);
+ ASMJIT_INST_2x(fmaxnmv, Fmaxnmv_v, Vec, Vec);
+ ASMJIT_INST_3x(fmaxp, Fmaxp_v, Vec, Vec, Vec);
+ ASMJIT_INST_2x(fmaxp, Fmaxp_v, Vec, Vec);
+ ASMJIT_INST_2x(fmaxv, Fmaxv_v, Vec, Vec);
+ ASMJIT_INST_3x(fmin, Fmin_v, Vec, Vec, Vec);
+ ASMJIT_INST_3x(fminnm, Fminnm_v, Vec, Vec, Vec);
+ ASMJIT_INST_2x(fminnmv, Fminnmv_v, Vec, Vec);
+ ASMJIT_INST_3x(fminnmp, Fminnmp_v, Vec, Vec, Vec);
+ ASMJIT_INST_2x(fminnmp, Fminnmp_v, Vec, Vec);
+ ASMJIT_INST_2x(fminp, Fminp_v, Vec, Vec);
+ ASMJIT_INST_3x(fminp, Fminp_v, Vec, Vec, Vec);
+ ASMJIT_INST_2x(fminv, Fminv_v, Vec, Vec);
+ ASMJIT_INST_3x(fmla, Fmla_v, Vec, Vec, Vec);
+ ASMJIT_INST_3x(fmls, Fmls_v, Vec, Vec, Vec);
+ ASMJIT_INST_2x(fmov, Fmov_v, Gp, Vec);
+ ASMJIT_INST_2x(fmov, Fmov_v, Vec, Gp);
+ ASMJIT_INST_2x(fmov, Fmov_v, Vec, Vec);
+ ASMJIT_INST_2x(fmov, Fmov_v, Vec, Imm);
+ ASMJIT_INST_4x(fmsub, Fmsub_v, Vec, Vec, Vec, Vec);
+ ASMJIT_INST_3x(fmul, Fmul_v, Vec, Vec, Vec);
+ ASMJIT_INST_3x(fmulx, Fmulx_v, Vec, Vec, Vec);
+ ASMJIT_INST_2x(fneg, Fneg_v, Vec, Vec);
+ ASMJIT_INST_4x(fnmadd, Fnmadd_v, Vec, Vec, Vec, Vec);
+ ASMJIT_INST_4x(fnmsub, Fnmsub_v, Vec, Vec, Vec, Vec);
+ ASMJIT_INST_3x(fnmul, Fnmul_v, Vec, Vec, Vec);
+ ASMJIT_INST_2x(frecpe, Frecpe_v, Vec, Vec);
+ ASMJIT_INST_3x(frecps, Frecps_v, Vec, Vec, Vec);
+ ASMJIT_INST_2x(frecpx, Frecpx_v, Vec, Vec);
+ ASMJIT_INST_2x(frint32x, Frint32x_v, Vec, Vec);
+ ASMJIT_INST_2x(frint32z, Frint32z_v, Vec, Vec);
+ ASMJIT_INST_2x(frint64x, Frint64x_v, Vec, Vec);
+ ASMJIT_INST_2x(frint64z, Frint64z_v, Vec, Vec);
+ ASMJIT_INST_2x(frinta, Frinta_v, Vec, Vec);
+ ASMJIT_INST_2x(frinti, Frinti_v, Vec, Vec);
+ ASMJIT_INST_2x(frintm, Frintm_v, Vec, Vec);
+ ASMJIT_INST_2x(frintn, Frintn_v, Vec, Vec);
+ ASMJIT_INST_2x(frintp, Frintp_v, Vec, Vec);
+ ASMJIT_INST_2x(frintx, Frintx_v, Vec, Vec);
+ ASMJIT_INST_2x(frintz, Frintz_v, Vec, Vec);
+ ASMJIT_INST_2x(frsqrte, Frsqrte_v, Vec, Vec);
+ ASMJIT_INST_3x(frsqrts, Frsqrts_v, Vec, Vec, Vec);
+ ASMJIT_INST_2x(fsqrt, Fsqrt_v, Vec, Vec);
+ ASMJIT_INST_3x(fsub, Fsub_v, Vec, Vec, Vec);
+ ASMJIT_INST_2x(ins, Ins_v, Vec, Gp);
+ ASMJIT_INST_2x(ins, Ins_v, Vec, Vec);
+ ASMJIT_INST_2x(ld1, Ld1_v, Vec, Mem);
+ ASMJIT_INST_3x(ld1, Ld1_v, Vec, Vec, Mem);
+ ASMJIT_INST_4x(ld1, Ld1_v, Vec, Vec, Vec, Mem);
+ ASMJIT_INST_5x(ld1, Ld1_v, Vec, Vec, Vec, Vec, Mem);
+ ASMJIT_INST_2x(ld1r, Ld1r_v, Vec, Mem);
+ ASMJIT_INST_3x(ld2, Ld2_v, Vec, Vec, Mem);
+ ASMJIT_INST_3x(ld2r, Ld2r_v, Vec, Vec, Mem);
+ ASMJIT_INST_4x(ld3, Ld3_v, Vec, Vec, Vec, Mem);
+ ASMJIT_INST_4x(ld3r, Ld3r_v, Vec, Vec, Vec, Mem);
+ ASMJIT_INST_5x(ld4, Ld4_v, Vec, Vec, Vec, Vec, Mem);
+ ASMJIT_INST_5x(ld4r, Ld4r_v, Vec, Vec, Vec, Vec, Mem);
+ ASMJIT_INST_3x(ldnp, Ldnp_v, Vec, Vec, Mem);
+ ASMJIT_INST_3x(ldp, Ldp_v, Vec, Vec, Mem);
+ ASMJIT_INST_2x(ldr, Ldr_v, Vec, Mem);
+ ASMJIT_INST_2x(ldur, Ldur_v, Vec, Mem);
+ ASMJIT_INST_3x(mla, Mla_v, Vec, Vec, Vec);
+ ASMJIT_INST_3x(mls, Mls_v, Vec, Vec, Vec);
+ ASMJIT_INST_2x(mov, Mov_v, Vec, Vec);
+ ASMJIT_INST_2x(mov, Mov_v, Gp, Vec);
+ ASMJIT_INST_2x(mov, Mov_v, Vec, Gp);
+ ASMJIT_INST_2x(movi, Movi_v, Vec, Imm);
+ ASMJIT_INST_3x(movi, Movi_v, Vec, Imm, Imm);
+ ASMJIT_INST_3x(mul, Mul_v, Vec, Vec, Vec);
+ ASMJIT_INST_2x(mvn, Mvn_v, Vec, Vec);
+ ASMJIT_INST_2x(mvni, Mvni_v, Vec, Imm);
+ ASMJIT_INST_3x(mvni, Mvni_v, Vec, Imm, Imm);
+ ASMJIT_INST_2x(neg, Neg_v, Vec, Vec);
+ ASMJIT_INST_2x(not_, Not_v, Vec, Vec);
+ ASMJIT_INST_3x(orn, Orn_v, Vec, Vec, Vec);
+ ASMJIT_INST_2x(orr, Orr_v, Vec, Imm);
+ ASMJIT_INST_3x(orr, Orr_v, Vec, Vec, Vec);
+ ASMJIT_INST_3x(orr, Orr_v, Vec, Imm, Imm);
+ ASMJIT_INST_3x(pmul, Pmul_v, Vec, Vec, Vec);
+ ASMJIT_INST_3x(pmull, Pmull_v, Vec, Vec, Vec);
+ ASMJIT_INST_3x(pmull2, Pmull2_v, Vec, Vec, Vec);
+ ASMJIT_INST_3x(raddhn, Raddhn_v, Vec, Vec, Vec);
+ ASMJIT_INST_3x(raddhn2, Raddhn2_v, Vec, Vec, Vec);
+ ASMJIT_INST_2x(rbit, Rbit_v, Vec, Vec);
+ ASMJIT_INST_2x(rev16, Rev16_v, Vec, Vec);
+ ASMJIT_INST_2x(rev32, Rev32_v, Vec, Vec);
+ ASMJIT_INST_2x(rev64, Rev64_v, Vec, Vec);
+ ASMJIT_INST_3x(rshrn, Rshrn_v, Vec, Vec, Imm);
+ ASMJIT_INST_3x(rshrn2, Rshrn2_v, Vec, Vec, Imm);
+ ASMJIT_INST_3x(rsubhn, Rsubhn_v, Vec, Vec, Vec);
+ ASMJIT_INST_3x(rsubhn2, Rsubhn2_v, Vec, Vec, Vec);
+ ASMJIT_INST_3x(saba, Saba_v, Vec, Vec, Vec);
+ ASMJIT_INST_3x(sabal, Sabal_v, Vec, Vec, Vec);
+ ASMJIT_INST_3x(sabal2, Sabal2_v, Vec, Vec, Vec);
+ ASMJIT_INST_3x(sabd, Sabd_v, Vec, Vec, Vec);
+ ASMJIT_INST_3x(sabdl, Sabdl_v, Vec, Vec, Vec);
+ ASMJIT_INST_3x(sabdl2, Sabdl2_v, Vec, Vec, Vec);
+ ASMJIT_INST_2x(sadalp, Sadalp_v, Vec, Vec);
+ ASMJIT_INST_3x(saddl, Saddl_v, Vec, Vec, Vec);
+ ASMJIT_INST_3x(saddl2, Saddl2_v, Vec, Vec, Vec);
+ ASMJIT_INST_2x(saddlp, Saddlp_v, Vec, Vec);
+ ASMJIT_INST_2x(saddlv, Saddlv_v, Vec, Vec);
+ ASMJIT_INST_3x(saddw, Saddw_v, Vec, Vec, Vec);
+ ASMJIT_INST_3x(saddw2, Saddw2_v, Vec, Vec, Vec);
+ ASMJIT_INST_2x(scvtf, Scvtf_v, Vec, Gp);
+ ASMJIT_INST_3x(scvtf, Scvtf_v, Vec, Gp, Imm);
+ ASMJIT_INST_2x(scvtf, Scvtf_v, Vec, Vec);
+ ASMJIT_INST_3x(scvtf, Scvtf_v, Vec, Vec, Imm);
+ ASMJIT_INST_3x(shadd, Shadd_v, Vec, Vec, Vec);
+ ASMJIT_INST_3x(shl, Shl_v, Vec, Vec, Imm);
+ ASMJIT_INST_3x(shll, Shll_v, Vec, Vec, Imm);
+ ASMJIT_INST_3x(shll2, Shll2_v, Vec, Vec, Imm);
+ ASMJIT_INST_3x(shrn, Shrn_v, Vec, Vec, Imm);
+ ASMJIT_INST_3x(shrn2, Shrn2_v, Vec, Vec, Imm);
+ ASMJIT_INST_3x(shsub, Shsub_v, Vec, Vec, Vec);
+ ASMJIT_INST_3x(sli, Sli_v, Vec, Vec, Imm);
+ ASMJIT_INST_3x(smax, Smax_v, Vec, Vec, Vec);
+ ASMJIT_INST_3x(smaxp, Smaxp_v, Vec, Vec, Vec);
+ ASMJIT_INST_2x(smaxv, Smaxv_v, Vec, Vec);
+ ASMJIT_INST_3x(smin, Smin_v, Vec, Vec, Vec);
+ ASMJIT_INST_3x(sminp, Sminp_v, Vec, Vec, Vec);
+ ASMJIT_INST_2x(sminv, Sminv_v, Vec, Vec);
+ ASMJIT_INST_3x(smlal, Smlal_v, Vec, Vec, Vec);
+ ASMJIT_INST_3x(smlal2, Smlal2_v, Vec, Vec, Vec);
+ ASMJIT_INST_3x(smlsl, Smlsl_v, Vec, Vec, Vec);
+ ASMJIT_INST_3x(smlsl2, Smlsl2_v, Vec, Vec, Vec);
+ ASMJIT_INST_2x(smov, Smov_v, Gp, Vec);
+ ASMJIT_INST_3x(smull, Smull_v, Vec, Vec, Vec);
+ ASMJIT_INST_3x(smull2, Smull2_v, Vec, Vec, Vec);
+ ASMJIT_INST_2x(sqabs, Sqabs_v, Vec, Vec);
+ ASMJIT_INST_3x(sqadd, Sqadd_v, Vec, Vec, Vec);
+ ASMJIT_INST_3x(sqdmlal, Sqdmlal_v, Vec, Vec, Vec);
+ ASMJIT_INST_3x(sqdmlal2, Sqdmlal2_v, Vec, Vec, Vec);
+ ASMJIT_INST_3x(sqdmlsl, Sqdmlsl_v, Vec, Vec, Vec);
+ ASMJIT_INST_3x(sqdmlsl2, Sqdmlsl2_v, Vec, Vec, Vec);
+ ASMJIT_INST_3x(sqdmulh, Sqdmulh_v, Vec, Vec, Vec);
+ ASMJIT_INST_3x(sqdmull, Sqdmull_v, Vec, Vec, Vec);
+ ASMJIT_INST_3x(sqdmull2, Sqdmull2_v, Vec, Vec, Vec);
+ ASMJIT_INST_2x(sqneg, Sqneg_v, Vec, Vec);
+ ASMJIT_INST_3x(sqrdmulh, Sqrdmulh_v, Vec, Vec, Vec);
+ ASMJIT_INST_3x(sqrshl, Sqrshl_v, Vec, Vec, Vec);
+ ASMJIT_INST_3x(sqrshrn, Sqrshrn_v, Vec, Vec, Imm);
+ ASMJIT_INST_3x(sqrshrn2, Sqrshrn2_v, Vec, Vec, Imm);
+ ASMJIT_INST_3x(sqrshrun, Sqrshrun_v, Vec, Vec, Imm);
+ ASMJIT_INST_3x(sqrshrun2, Sqrshrun2_v, Vec, Vec, Imm);
+ ASMJIT_INST_3x(sqshl, Sqshl_v, Vec, Vec, Vec);
+ ASMJIT_INST_3x(sqshl, Sqshl_v, Vec, Vec, Imm);
+ ASMJIT_INST_3x(sqshlu, Sqshlu_v, Vec, Vec, Imm);
+ ASMJIT_INST_3x(sqshrn, Sqshrn_v, Vec, Vec, Imm);
+ ASMJIT_INST_3x(sqshrn2, Sqshrn2_v, Vec, Vec, Imm);
+ ASMJIT_INST_3x(sqshrun, Sqshrun_v, Vec, Vec, Imm);
+ ASMJIT_INST_3x(sqshrun2, Sqshrun2_v, Vec, Vec, Imm);
+ ASMJIT_INST_3x(sqsub, Sqsub_v, Vec, Vec, Vec);
+ ASMJIT_INST_2x(sqxtn, Sqxtn_v, Vec, Vec);
+ ASMJIT_INST_2x(sqxtn2, Sqxtn2_v, Vec, Vec);
+ ASMJIT_INST_2x(sqxtun, Sqxtun_v, Vec, Vec);
+ ASMJIT_INST_2x(sqxtun2, Sqxtun2_v, Vec, Vec);
+ ASMJIT_INST_3x(srhadd, Srhadd_v, Vec, Vec, Vec);
+ ASMJIT_INST_3x(sri, Sri_v, Vec, Vec, Imm);
+ ASMJIT_INST_3x(srshl, Srshl_v, Vec, Vec, Vec);
+ ASMJIT_INST_3x(srshr, Srshr_v, Vec, Vec, Imm);
+ ASMJIT_INST_3x(srsra, Srsra_v, Vec, Vec, Imm);
+ ASMJIT_INST_3x(sshl, Sshl_v, Vec, Vec, Vec);
+ ASMJIT_INST_3x(sshll, Sshll_v, Vec, Vec, Imm);
+ ASMJIT_INST_3x(sshll2, Sshll2_v, Vec, Vec, Imm);
+ ASMJIT_INST_3x(sshr, Sshr_v, Vec, Vec, Imm);
+ ASMJIT_INST_3x(ssra, Ssra_v, Vec, Vec, Imm);
+ ASMJIT_INST_3x(ssubl, Ssubl_v, Vec, Vec, Vec);
+ ASMJIT_INST_3x(ssubl2, Ssubl2_v, Vec, Vec, Vec);
+ ASMJIT_INST_3x(ssubw, Ssubw_v, Vec, Vec, Vec);
+ ASMJIT_INST_3x(ssubw2, Ssubw2_v, Vec, Vec, Vec);
+ ASMJIT_INST_2x(st1, St1_v, Vec, Mem);
+ ASMJIT_INST_3x(st1, St1_v, Vec, Vec, Mem);
+ ASMJIT_INST_4x(st1, St1_v, Vec, Vec, Vec, Mem);
+ ASMJIT_INST_5x(st1, St1_v, Vec, Vec, Vec, Vec, Mem);
+ ASMJIT_INST_3x(st2, St2_v, Vec, Vec, Mem);
+ ASMJIT_INST_4x(st3, St3_v, Vec, Vec, Vec, Mem);
+ ASMJIT_INST_5x(st4, St4_v, Vec, Vec, Vec, Vec, Mem);
+ ASMJIT_INST_3x(stnp, Stnp_v, Vec, Vec, Mem);
+ ASMJIT_INST_3x(stp, Stp_v, Vec, Vec, Mem);
+ ASMJIT_INST_2x(str, Str_v, Vec, Mem);
+ ASMJIT_INST_2x(stur, Stur_v, Vec, Mem);
+ ASMJIT_INST_3x(sub, Sub_v, Vec, Vec, Vec);
+ ASMJIT_INST_3x(subhn, Subhn_v, Vec, Vec, Vec);
+ ASMJIT_INST_3x(subhn2, Subhn2_v, Vec, Vec, Vec);
+ ASMJIT_INST_2x(suqadd, Suqadd_v, Vec, Vec);
+ ASMJIT_INST_2x(sxtl, Sxtl_v, Vec, Vec);
+ ASMJIT_INST_2x(sxtl2, Sxtl2_v, Vec, Vec);
+ ASMJIT_INST_3x(tbl, Tbl_v, Vec, Vec, Vec);
+ ASMJIT_INST_4x(tbl, Tbl_v, Vec, Vec, Vec, Vec);
+ ASMJIT_INST_5x(tbl, Tbl_v, Vec, Vec, Vec, Vec, Vec);
+ ASMJIT_INST_6x(tbl, Tbl_v, Vec, Vec, Vec, Vec, Vec, Vec);
+ ASMJIT_INST_3x(tbx, Tbx_v, Vec, Vec, Vec);
+ ASMJIT_INST_4x(tbx, Tbx_v, Vec, Vec, Vec, Vec);
+ ASMJIT_INST_5x(tbx, Tbx_v, Vec, Vec, Vec, Vec, Vec);
+ ASMJIT_INST_6x(tbx, Tbx_v, Vec, Vec, Vec, Vec, Vec, Vec);
+ ASMJIT_INST_3x(trn1, Trn1_v, Vec, Vec, Vec);
+ ASMJIT_INST_3x(trn2, Trn2_v, Vec, Vec, Vec);
+ ASMJIT_INST_3x(uaba, Uaba_v, Vec, Vec, Vec);
+ ASMJIT_INST_3x(uabal, Uabal_v, Vec, Vec, Vec);
+ ASMJIT_INST_3x(uabal2, Uabal2_v, Vec, Vec, Vec);
+ ASMJIT_INST_3x(uabd, Uabd_v, Vec, Vec, Vec);
+ ASMJIT_INST_3x(uabdl, Uabdl_v, Vec, Vec, Vec);
+ ASMJIT_INST_3x(uabdl2, Uabdl2_v, Vec, Vec, Vec);
+ ASMJIT_INST_2x(uadalp, Uadalp_v, Vec, Vec);
+ ASMJIT_INST_3x(uaddl, Uaddl_v, Vec, Vec, Vec);
+ ASMJIT_INST_3x(uaddl2, Uaddl2_v, Vec, Vec, Vec);
+ ASMJIT_INST_2x(uaddlp, Uaddlp_v, Vec, Vec);
+ ASMJIT_INST_2x(uaddlv, Uaddlv_v, Vec, Vec);
+ ASMJIT_INST_3x(uaddw, Uaddw_v, Vec, Vec, Vec);
+ ASMJIT_INST_3x(uaddw2, Uaddw2_v, Vec, Vec, Vec);
+ ASMJIT_INST_2x(ucvtf, Ucvtf_v, Vec, Gp);
+ ASMJIT_INST_3x(ucvtf, Ucvtf_v, Vec, Gp, Imm);
+ ASMJIT_INST_2x(ucvtf, Ucvtf_v, Vec, Vec);
+ ASMJIT_INST_3x(ucvtf, Ucvtf_v, Vec, Vec, Imm);
+ ASMJIT_INST_3x(uhadd, Uhadd_v, Vec, Vec, Vec);
+ ASMJIT_INST_3x(uhsub, Uhsub_v, Vec, Vec, Vec);
+ ASMJIT_INST_3x(umax, Umax_v, Vec, Vec, Vec);
+ ASMJIT_INST_3x(umaxp, Umaxp_v, Vec, Vec, Vec);
+ ASMJIT_INST_2x(umaxv, Umaxv_v, Vec, Vec);
+ ASMJIT_INST_3x(umin, Umin_v, Vec, Vec, Vec);
+ ASMJIT_INST_3x(uminp, Uminp_v, Vec, Vec, Vec);
+ ASMJIT_INST_2x(uminv, Uminv_v, Vec, Vec);
+ ASMJIT_INST_3x(umlal, Umlal_v, Vec, Vec, Vec);
+ ASMJIT_INST_3x(umlal2, Umlal2_v, Vec, Vec, Vec);
+ ASMJIT_INST_3x(umlsl, Umlsl_v, Vec, Vec, Vec);
+ ASMJIT_INST_3x(umlsl2, Umlsl2_v, Vec, Vec, Vec);
+ ASMJIT_INST_2x(umov, Umov_v, Gp, Vec);
+ ASMJIT_INST_3x(umull, Umull_v, Vec, Vec, Vec);
+ ASMJIT_INST_3x(umull2, Umull2_v, Vec, Vec, Vec);
+ ASMJIT_INST_3x(uqadd, Uqadd_v, Vec, Vec, Vec);
+ ASMJIT_INST_3x(uqrshl, Uqrshl_v, Vec, Vec, Vec);
+ ASMJIT_INST_3x(uqrshl, Uqrshl_v, Vec, Vec, Imm);
+ ASMJIT_INST_3x(uqrshrn, Uqrshrn_v, Vec, Vec, Imm);
+ ASMJIT_INST_3x(uqrshrn2, Uqrshrn2_v, Vec, Vec, Imm);
+ ASMJIT_INST_3x(uqshl, Uqshl_v, Vec, Vec, Vec);
+ ASMJIT_INST_3x(uqshl, Uqshl_v, Vec, Vec, Imm);
+ ASMJIT_INST_3x(uqshrn, Uqshrn_v, Vec, Vec, Imm);
+ ASMJIT_INST_3x(uqshrn2, Uqshrn2_v, Vec, Vec, Imm);
+ ASMJIT_INST_3x(uqsub, Uqsub_v, Vec, Vec, Vec);
+ ASMJIT_INST_2x(uqxtn, Uqxtn_v, Vec, Vec);
+ ASMJIT_INST_2x(uqxtn2, Uqxtn2_v, Vec, Vec);
+ ASMJIT_INST_2x(urecpe, Urecpe_v, Vec, Vec);
+ ASMJIT_INST_3x(urhadd, Urhadd_v, Vec, Vec, Vec);
+ ASMJIT_INST_3x(urshl, Urshl_v, Vec, Vec, Vec);
+ ASMJIT_INST_3x(urshr, Urshr_v, Vec, Vec, Imm);
+ ASMJIT_INST_2x(ursqrte, Ursqrte_v, Vec, Vec);
+ ASMJIT_INST_3x(ursra, Ursra_v, Vec, Vec, Imm);
+ ASMJIT_INST_3x(ushl, Ushl_v, Vec, Vec, Vec);
+ ASMJIT_INST_3x(ushll, Ushll_v, Vec, Vec, Imm);
+ ASMJIT_INST_3x(ushll2, Ushll2_v, Vec, Vec, Imm);
+ ASMJIT_INST_3x(ushr, Ushr_v, Vec, Vec, Imm);
+ ASMJIT_INST_2x(usqadd, Usqadd_v, Vec, Vec);
+ ASMJIT_INST_3x(usra, Usra_v, Vec, Vec, Imm);
+ ASMJIT_INST_3x(usubl, Usubl_v, Vec, Vec, Vec);
+ ASMJIT_INST_3x(usubl2, Usubl2_v, Vec, Vec, Vec);
+ ASMJIT_INST_3x(usubw, Usubw_v, Vec, Vec, Vec);
+ ASMJIT_INST_3x(usubw2, Usubw2_v, Vec, Vec, Vec);
+ ASMJIT_INST_2x(uxtl, Uxtl_v, Vec, Vec);
+ ASMJIT_INST_2x(uxtl2, Uxtl2_v, Vec, Vec);
+ ASMJIT_INST_3x(uzp1, Uzp1_v, Vec, Vec, Vec);
+ ASMJIT_INST_3x(uzp2, Uzp2_v, Vec, Vec, Vec);
+ ASMJIT_INST_2x(xtn, Xtn_v, Vec, Vec);
+ ASMJIT_INST_2x(xtn2, Xtn2_v, Vec, Vec);
+ ASMJIT_INST_3x(zip1, Zip1_v, Vec, Vec, Vec);
+ ASMJIT_INST_3x(zip2, Zip2_v, Vec, Vec, Vec);
+
+ //! \}
+
+ //! \name AES Instructions
+ //! \{
+
+ ASMJIT_INST_2x(aesd, Aesd_v, Vec, Vec);
+ ASMJIT_INST_2x(aese, Aese_v, Vec, Vec);
+ ASMJIT_INST_2x(aesimc, Aesimc_v, Vec, Vec);
+ ASMJIT_INST_2x(aesmc, Aesmc_v, Vec, Vec);
+
+ //! \}
+
+ //! \name SHA1 Instructions
+ //! \{
+
+ ASMJIT_INST_3x(sha1c, Sha1c_v, Vec, Vec, Vec);
+ ASMJIT_INST_2x(sha1h, Sha1h_v, Vec, Vec);
+ ASMJIT_INST_3x(sha1m, Sha1m_v, Vec, Vec, Vec);
+ ASMJIT_INST_3x(sha1p, Sha1p_v, Vec, Vec, Vec);
+ ASMJIT_INST_3x(sha1su0, Sha1su0_v, Vec, Vec, Vec);
+ ASMJIT_INST_2x(sha1su1, Sha1su1_v, Vec, Vec);
+
+ //! \}
+
+ //! \name SHA2 Instructions
+ //! \{
+
+ ASMJIT_INST_3x(sha256h, Sha256h_v, Vec, Vec, Vec);
+ ASMJIT_INST_3x(sha256h2, Sha256h2_v, Vec, Vec, Vec);
+ ASMJIT_INST_2x(sha256su0, Sha256su0_v, Vec, Vec);
+ ASMJIT_INST_3x(sha256su1, Sha256su1_v, Vec, Vec, Vec);
+
+ //! \}
+
+ //! \name RDMA Instructions (ARMv8.1-A)
+ //! \{
+
+ ASMJIT_INST_3x(sqrdmlah, Sqrdmlah_v, Vec, Vec, Vec);
+ ASMJIT_INST_3x(sqrdmlsh, Sqrdmlsh_v, Vec, Vec, Vec);
+
+ //! \}
+
+ //! \name FCMA Instruction (ARMv8.3-A)
+ //! \{
+
+ ASMJIT_INST_4x(fcadd, Fcadd_v, Vec, Vec, Vec, Imm);
+ ASMJIT_INST_4x(fcmla, Fcmla_v, Vec, Vec, Vec, Imm);
+
+ //! \}
+
+ //! \name FJCVTZS Instruction (ARMv8.3-A)
+ //! \{
+
+ ASMJIT_INST_2x(fjcvtzs, Fjcvtzs_v, Gp, Vec);
+
+ //! \}
+
+ //! \name FP16FML Instructions (ARMv8.4-A, optional in ARMv8.2-A)
+ //! \{
+
+ ASMJIT_INST_3x(fmlal, Fmlal_v, Vec, Vec, Vec);
+ ASMJIT_INST_3x(fmlal2, Fmlal2_v, Vec, Vec, Vec);
+ ASMJIT_INST_3x(fmlsl, Fmlsl_v, Vec, Vec, Vec);
+ ASMJIT_INST_3x(fmlsl2, Fmlsl2_v, Vec, Vec, Vec);
+
+
+ //! \}
+
+ //! \name SHA3 Instructions (ARMv8.4-A, optional in ARMv8.2-A)
+ //! \{
+
+ ASMJIT_INST_4x(bcax, Bcax_v, Vec, Vec, Vec, Vec);
+ ASMJIT_INST_4x(eor3, Eor3_v, Vec, Vec, Vec, Vec);
+ ASMJIT_INST_3x(rax1, Rax1_v, Vec, Vec, Vec);
+ ASMJIT_INST_4x(xar, Xar_v, Vec, Vec, Vec, Imm);
+
+ //! \}
+
+ //! \name SHA512 Instructions (ARMv8.4-A)
+ //! \{
+
+ ASMJIT_INST_3x(sha512h, Sha512h_v, Vec, Vec, Vec);
+ ASMJIT_INST_3x(sha512h2, Sha512h2_v, Vec, Vec, Vec);
+ ASMJIT_INST_2x(sha512su0, Sha512su0_v, Vec, Vec);
+ ASMJIT_INST_3x(sha512su1, Sha512su1_v, Vec, Vec, Vec);
+
+ //! \}
+
+ //! \name SM3 Instructions (ARMv8.4-A)
+ //! \{
+
+ ASMJIT_INST_3x(sm3partw1, Sm3partw1_v, Vec, Vec, Vec);
+ ASMJIT_INST_3x(sm3partw2, Sm3partw2_v, Vec, Vec, Vec);
+ ASMJIT_INST_4x(sm3ss1, Sm3ss1_v, Vec, Vec, Vec, Vec);
+ ASMJIT_INST_3x(sm3tt1a, Sm3tt1a_v, Vec, Vec, Vec);
+ ASMJIT_INST_3x(sm3tt1b, Sm3tt1b_v, Vec, Vec, Vec);
+ ASMJIT_INST_3x(sm3tt2a, Sm3tt2a_v, Vec, Vec, Vec);
+ ASMJIT_INST_3x(sm3tt2b, Sm3tt2b_v, Vec, Vec, Vec);
+
+ //! \}
+
+ //! \name SM4 Instructions (ARMv8.4-A)
+ //! \{
+
+ ASMJIT_INST_2x(sm4e, Sm4e_v, Vec, Vec);
+ ASMJIT_INST_3x(sm4ekey, Sm4ekey_v, Vec, Vec, Vec);
+
+ //! \}
+
+ //! \name DOTPROD Instructions (ARMv8.4-A, optional in ARMv8.2-A)
+ //! \{
+
+ ASMJIT_INST_3x(sdot, Sdot_v, Vec, Vec, Vec);
+ ASMJIT_INST_3x(udot, Udot_v, Vec, Vec, Vec);
+
+ //! \}
+
+ //! \name BF16 Instructions (ARMv8.6-A)
+ //! \{
+
+ ASMJIT_INST_2x(bfcvt, Bfcvt_v, Vec, Vec);
+ ASMJIT_INST_2x(bfcvtn, Bfcvtn_v, Vec, Vec);
+ ASMJIT_INST_2x(bfcvtn2, Bfcvtn2_v, Vec, Vec);
+ ASMJIT_INST_3x(bfmlalb, Bfmlalb_v, Vec, Vec, Vec);
+ ASMJIT_INST_3x(bfmlalt, Bfmlalt_v, Vec, Vec, Vec);
+ ASMJIT_INST_3x(bfmmla, Bfmmla_v, Vec, Vec, Vec);
+ ASMJIT_INST_3x(bfdot, Bfdot_v, Vec, Vec, Vec);
+
+ //! \}
+
+ //! \name I8MM Instructions (ARMv8.6-A)
+ //! \{
+
+ ASMJIT_INST_3x(smmla, Smmla_v, Vec, Vec, Vec);
+ ASMJIT_INST_3x(sudot, Sudot_v, Vec, Vec, Vec);
+ ASMJIT_INST_3x(ummla, Ummla_v, Vec, Vec, Vec);
+ ASMJIT_INST_3x(usdot, Usdot_v, Vec, Vec, Vec);
+ ASMJIT_INST_3x(usmmla, Usmmla_v, Vec, Vec, Vec);
+
+ //! \}
+};
+
+//! Emitter (ARM).
+//!
+//! \note This class cannot be instantiated, you can only cast to it and use it as emitter that emits to either
+//! `a64::Assembler`, `a64::Builder`, or `a64::Compiler` (use with caution with `a64::Compiler` as it requires
+//! virtual registers).
+class Emitter : public BaseEmitter, public EmitterExplicitT<Emitter> {
+ ASMJIT_NONCONSTRUCTIBLE(Emitter)
+};
+
+//! \}
+
+#undef ASMJIT_INST_0x
+#undef ASMJIT_INST_1x
+#undef ASMJIT_INST_2x
+#undef ASMJIT_INST_3x
+#undef ASMJIT_INST_4x
+#undef ASMJIT_INST_5x
+#undef ASMJIT_INST_6x
+#undef ASMJIT_INST_1cc
+
+ASMJIT_END_SUB_NAMESPACE
+
+#endif // ASMJIT_ARM_A64EMITTER_H_INCLUDED
diff --git a/3rdparty/asmjit/src/asmjit/arm/a64formatter.cpp b/3rdparty/asmjit/src/asmjit/arm/a64formatter.cpp
new file mode 100644
index 00000000000..bccb68b99b0
--- /dev/null
+++ b/3rdparty/asmjit/src/asmjit/arm/a64formatter.cpp
@@ -0,0 +1,298 @@
+// This file is part of AsmJit project <https://asmjit.com>
+//
+// See asmjit.h or LICENSE.md for license and copyright information
+// SPDX-License-Identifier: Zlib
+
+#include "../core/api-build_p.h"
+#ifndef ASMJIT_NO_LOGGING
+
+#include "../core/misc_p.h"
+#include "../core/support.h"
+#include "../arm/a64formatter_p.h"
+#include "../arm/a64instapi_p.h"
+#include "../arm/a64instdb_p.h"
+#include "../arm/a64operand.h"
+
+#ifndef ASMJIT_NO_COMPILER
+ #include "../core/compiler.h"
+#endif
+
+ASMJIT_BEGIN_SUB_NAMESPACE(a64)
+
+// a64::FormatterInternal - Format Register
+// ========================================
+
+ASMJIT_FAVOR_SIZE Error FormatterInternal::formatRegister(
+ String& sb,
+ FormatFlags flags,
+ const BaseEmitter* emitter,
+ Arch arch,
+ RegType regType,
+ uint32_t rId,
+ uint32_t elementType,
+ uint32_t elementIndex) noexcept {
+
+ DebugUtils::unused(flags);
+ DebugUtils::unused(arch);
+
+ static const char bhsdq[] = "bhsdq";
+
+ bool virtRegFormatted = false;
+
+#ifndef ASMJIT_NO_COMPILER
+ if (Operand::isVirtId(rId)) {
+ if (emitter && emitter->isCompiler()) {
+ const BaseCompiler* cc = static_cast<const BaseCompiler*>(emitter);
+ if (cc->isVirtIdValid(rId)) {
+ VirtReg* vReg = cc->virtRegById(rId);
+ ASMJIT_ASSERT(vReg != nullptr);
+
+ const char* name = vReg->name();
+ if (name && name[0] != '\0')
+ ASMJIT_PROPAGATE(sb.append(name));
+ else
+ ASMJIT_PROPAGATE(sb.appendFormat("%%%u", unsigned(Operand::virtIdToIndex(rId))));
+
+ virtRegFormatted = true;
+ }
+ }
+ }
+#else
+ DebugUtils::unused(emitter, flags);
+#endif
+
+ if (!virtRegFormatted) {
+ char letter = '\0';
+ switch (regType) {
+ case RegType::kARM_GpW:
+ if (rId == Gp::kIdZr)
+ return sb.append("wzr");
+ if (rId == Gp::kIdSp)
+ return sb.append("wsp");
+
+ letter = 'w';
+ break;
+
+ case RegType::kARM_GpX:
+ if (rId == Gp::kIdZr)
+ return sb.append("xzr");
+ if (rId == Gp::kIdSp)
+ return sb.append("sp");
+
+ letter = 'x';
+ break;
+
+ case RegType::kARM_VecB:
+ case RegType::kARM_VecH:
+ case RegType::kARM_VecS:
+ case RegType::kARM_VecD:
+ case RegType::kARM_VecV:
+ letter = bhsdq[uint32_t(regType) - uint32_t(RegType::kARM_VecB)];
+ if (elementType)
+ letter = 'v';
+ break;
+
+ default:
+ ASMJIT_PROPAGATE(sb.appendFormat("<Reg-%u>?$u", uint32_t(regType), rId));
+ break;
+ }
+
+ if (letter)
+ ASMJIT_PROPAGATE(sb.appendFormat("%c%u", letter, rId));
+ }
+
+ if (elementType) {
+ char elementLetter = '\0';
+ uint32_t elementCount = 0;
+
+ switch (elementType) {
+ case Vec::kElementTypeB:
+ elementLetter = 'b';
+ elementCount = 16;
+ break;
+
+ case Vec::kElementTypeH:
+ elementLetter = 'h';
+ elementCount = 8;
+ break;
+
+ case Vec::kElementTypeS:
+ elementLetter = 's';
+ elementCount = 4;
+ break;
+
+ case Vec::kElementTypeD:
+ elementLetter = 'd';
+ elementCount = 2;
+ break;
+
+ default:
+ return sb.append(".<Unknown>");
+ }
+
+ if (elementLetter) {
+ if (elementIndex == 0xFFFFFFFFu) {
+ if (regType == RegType::kARM_VecD)
+ elementCount /= 2u;
+ ASMJIT_PROPAGATE(sb.appendFormat(".%u%c", elementCount, elementLetter));
+ }
+ else {
+ ASMJIT_PROPAGATE(sb.appendFormat(".%c[%u]", elementLetter, elementIndex));
+ }
+ }
+ }
+
+ return kErrorOk;
+}
+
+// a64::FormatterInternal - Format Operand
+// =======================================
+
+ASMJIT_FAVOR_SIZE Error FormatterInternal::formatOperand(
+ String& sb,
+ FormatFlags flags,
+ const BaseEmitter* emitter,
+ Arch arch,
+ const Operand_& op) noexcept {
+
+ if (op.isReg()) {
+ const BaseReg& reg = op.as<BaseReg>();
+
+ uint32_t elementType = op.as<Vec>().elementType();
+ uint32_t elementIndex = op.as<Vec>().elementIndex();
+
+ if (!op.as<Vec>().hasElementIndex())
+ elementIndex = 0xFFFFFFFFu;
+
+ return formatRegister(sb, flags, emitter, arch, reg.type(), reg.id(), elementType, elementIndex);
+ }
+
+ if (op.isMem()) {
+ const Mem& m = op.as<Mem>();
+ ASMJIT_PROPAGATE(sb.append('['));
+
+ if (m.hasBase()) {
+ if (m.hasBaseLabel()) {
+ ASMJIT_PROPAGATE(Formatter::formatLabel(sb, flags, emitter, m.baseId()));
+ }
+ else {
+ FormatFlags modifiedFlags = flags;
+ if (m.isRegHome()) {
+ ASMJIT_PROPAGATE(sb.append('&'));
+ modifiedFlags &= ~FormatFlags::kRegCasts;
+ }
+ ASMJIT_PROPAGATE(formatRegister(sb, modifiedFlags, emitter, arch, m.baseType(), m.baseId()));
+ }
+ }
+ else {
+ // ARM really requires base.
+ if (m.hasIndex() || m.hasOffset()) {
+ ASMJIT_PROPAGATE(sb.append("<None>"));
+ }
+ }
+
+ // The post index makes it look like there was another operand, but it's
+ // still the part of AsmJit's `arm::Mem` operand so it's consistent with
+ // other architectures.
+ if (m.isPostIndex())
+ ASMJIT_PROPAGATE(sb.append(']'));
+
+ if (m.hasIndex()) {
+ ASMJIT_PROPAGATE(sb.append(", "));
+ ASMJIT_PROPAGATE(formatRegister(sb, flags, emitter, arch, m.indexType(), m.indexId()));
+ }
+
+ if (m.hasOffset()) {
+ ASMJIT_PROPAGATE(sb.append(", "));
+
+ int64_t off = int64_t(m.offset());
+ uint32_t base = 10;
+
+ if (Support::test(flags, FormatFlags::kHexOffsets) && uint64_t(off) > 9)
+ base = 16;
+
+ if (base == 10) {
+ ASMJIT_PROPAGATE(sb.appendInt(off, base));
+ }
+ else {
+ ASMJIT_PROPAGATE(sb.append("0x"));
+ ASMJIT_PROPAGATE(sb.appendUInt(uint64_t(off), base));
+ }
+ }
+
+ if (m.hasShift()) {
+ ASMJIT_PROPAGATE(sb.append(' '));
+ if (!m.isPreOrPost())
+ ASMJIT_PROPAGATE(formatShiftOp(sb, (ShiftOp)m.predicate()));
+ ASMJIT_PROPAGATE(sb.appendFormat(" %u", m.shift()));
+ }
+
+ if (!m.isPostIndex())
+ ASMJIT_PROPAGATE(sb.append(']'));
+
+ if (m.isPreIndex())
+ ASMJIT_PROPAGATE(sb.append('!'));
+
+ return kErrorOk;
+ }
+
+ if (op.isImm()) {
+ const Imm& i = op.as<Imm>();
+ int64_t val = i.value();
+
+ if (Support::test(flags, FormatFlags::kHexImms) && uint64_t(val) > 9) {
+ ASMJIT_PROPAGATE(sb.append("0x"));
+ return sb.appendUInt(uint64_t(val), 16);
+ }
+ else {
+ return sb.appendInt(val, 10);
+ }
+ }
+
+ if (op.isLabel()) {
+ return Formatter::formatLabel(sb, flags, emitter, op.id());
+ }
+
+ return sb.append("<None>");
+}
+
+// a64::FormatterInternal - Format Instruction
+// ===========================================
+
+ASMJIT_FAVOR_SIZE Error FormatterInternal::formatInstruction(
+ String& sb,
+ FormatFlags flags,
+ const BaseEmitter* emitter,
+ Arch arch,
+ const BaseInst& inst, const Operand_* operands, size_t opCount) noexcept {
+
+ DebugUtils::unused(arch);
+
+ // Format instruction options and instruction mnemonic.
+ InstId instId = inst.realId();
+ if (instId < Inst::_kIdCount)
+ ASMJIT_PROPAGATE(InstInternal::instIdToString(arch, instId, sb));
+ else
+ ASMJIT_PROPAGATE(sb.appendFormat("[InstId=#%u]", unsigned(instId)));
+
+ CondCode cc = inst.armCondCode();
+ if (cc != CondCode::kAL) {
+ ASMJIT_PROPAGATE(sb.append('.'));
+ ASMJIT_PROPAGATE(formatCondCode(sb, cc));
+ }
+
+ for (uint32_t i = 0; i < opCount; i++) {
+ const Operand_& op = operands[i];
+ if (op.isNone())
+ break;
+
+ ASMJIT_PROPAGATE(sb.append(i == 0 ? " " : ", "));
+ ASMJIT_PROPAGATE(formatOperand(sb, flags, emitter, arch, op));
+ }
+
+ return kErrorOk;
+}
+
+ASMJIT_END_SUB_NAMESPACE
+
+#endif // !ASMJIT_NO_LOGGING
diff --git a/3rdparty/asmjit/src/asmjit/arm/a64formatter_p.h b/3rdparty/asmjit/src/asmjit/arm/a64formatter_p.h
new file mode 100644
index 00000000000..bd7a1440cb0
--- /dev/null
+++ b/3rdparty/asmjit/src/asmjit/arm/a64formatter_p.h
@@ -0,0 +1,59 @@
+// This file is part of AsmJit project <https://asmjit.com>
+//
+// See asmjit.h or LICENSE.md for license and copyright information
+// SPDX-License-Identifier: Zlib
+
+#ifndef ASMJIT_ARM_A64FORMATTER_P_H_INCLUDED
+#define ASMJIT_ARM_A64FORMATTER_P_H_INCLUDED
+
+#include "../core/api-config.h"
+#ifndef ASMJIT_NO_LOGGING
+
+#include "../core/formatter.h"
+#include "../core/string.h"
+#include "../arm/armformatter_p.h"
+#include "../arm/a64globals.h"
+
+ASMJIT_BEGIN_SUB_NAMESPACE(a64)
+
+//! \cond INTERNAL
+//! \addtogroup asmjit_a64
+//! \{
+
+namespace FormatterInternal {
+
+using namespace arm::FormatterInternal;
+
+Error ASMJIT_CDECL formatRegister(
+ String& sb,
+ FormatFlags flags,
+ const BaseEmitter* emitter,
+ Arch arch,
+ RegType regType,
+ uint32_t regId,
+ uint32_t elementType = 0,
+ uint32_t elementIndex = 0xFFFFFFFFu) noexcept;
+
+Error ASMJIT_CDECL formatOperand(
+ String& sb,
+ FormatFlags flags,
+ const BaseEmitter* emitter,
+ Arch arch,
+ const Operand_& op) noexcept;
+
+Error ASMJIT_CDECL formatInstruction(
+ String& sb,
+ FormatFlags flags,
+ const BaseEmitter* emitter,
+ Arch arch,
+ const BaseInst& inst, const Operand_* operands, size_t opCount) noexcept;
+
+} // {FormatterInternal}
+
+//! \}
+//! \endcond
+
+ASMJIT_END_SUB_NAMESPACE
+
+#endif // !ASMJIT_NO_LOGGING
+#endif // ASMJIT_ARM_A64FORMATTER_P_H_INCLUDED
diff --git a/3rdparty/asmjit/src/asmjit/arm/a64func.cpp b/3rdparty/asmjit/src/asmjit/arm/a64func.cpp
new file mode 100644
index 00000000000..55e3f2e71ec
--- /dev/null
+++ b/3rdparty/asmjit/src/asmjit/arm/a64func.cpp
@@ -0,0 +1,189 @@
+// This file is part of AsmJit project <https://asmjit.com>
+//
+// See asmjit.h or LICENSE.md for license and copyright information
+// SPDX-License-Identifier: Zlib
+
+#include "../core/api-build_p.h"
+#if !defined(ASMJIT_NO_AARCH64)
+
+#include "../arm/a64func_p.h"
+#include "../arm/a64operand.h"
+
+ASMJIT_BEGIN_SUB_NAMESPACE(a64)
+
+namespace FuncInternal {
+
+static inline bool shouldThreatAsCDecl(CallConvId ccId) noexcept {
+ return ccId == CallConvId::kCDecl ||
+ ccId == CallConvId::kStdCall ||
+ ccId == CallConvId::kFastCall ||
+ ccId == CallConvId::kVectorCall ||
+ ccId == CallConvId::kThisCall ||
+ ccId == CallConvId::kRegParm1 ||
+ ccId == CallConvId::kRegParm2 ||
+ ccId == CallConvId::kRegParm3;
+}
+
+static RegType regTypeFromFpOrVecTypeId(TypeId typeId) noexcept {
+ if (typeId == TypeId::kFloat32)
+ return RegType::kARM_VecS;
+ else if (typeId == TypeId::kFloat64)
+ return RegType::kARM_VecD;
+ else if (TypeUtils::isVec32(typeId))
+ return RegType::kARM_VecS;
+ else if (TypeUtils::isVec64(typeId))
+ return RegType::kARM_VecD;
+ else if (TypeUtils::isVec128(typeId))
+ return RegType::kARM_VecV;
+ else
+ return RegType::kNone;
+}
+
+ASMJIT_FAVOR_SIZE Error initCallConv(CallConv& cc, CallConvId ccId, const Environment& environment) noexcept {
+ cc.setArch(environment.arch());
+
+ cc.setSaveRestoreRegSize(RegGroup::kGp, 8);
+ cc.setSaveRestoreRegSize(RegGroup::kVec, 8);
+ cc.setSaveRestoreAlignment(RegGroup::kGp, 16);
+ cc.setSaveRestoreAlignment(RegGroup::kVec, 16);
+ cc.setSaveRestoreAlignment(RegGroup::kExtraVirt2, 1);
+ cc.setSaveRestoreAlignment(RegGroup::kExtraVirt3, 1);
+ cc.setPassedOrder(RegGroup::kGp, 0, 1, 2, 3, 4, 5, 6, 7);
+ cc.setPassedOrder(RegGroup::kVec, 0, 1, 2, 3, 4, 5, 6, 7);
+ cc.setNaturalStackAlignment(16);
+
+ if (shouldThreatAsCDecl(ccId)) {
+ // ARM doesn't have that many calling conventions as we can find in X86 world, treat most conventions as __cdecl.
+ cc.setId(CallConvId::kCDecl);
+ cc.setPreservedRegs(RegGroup::kGp, Support::bitMask(Gp::kIdOs, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30));
+ cc.setPreservedRegs(RegGroup::kVec, Support::bitMask(8, 9, 10, 11, 12, 13, 14, 15));
+ }
+ else {
+ cc.setId(ccId);
+ cc.setSaveRestoreRegSize(RegGroup::kVec, 16);
+ cc.setPreservedRegs(RegGroup::kGp, Support::bitMask(4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30));
+ cc.setPreservedRegs(RegGroup::kVec, Support::bitMask(4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31));
+ }
+
+ return kErrorOk;
+}
+
+ASMJIT_FAVOR_SIZE Error initFuncDetail(FuncDetail& func, const FuncSignature& signature, uint32_t registerSize) noexcept {
+ DebugUtils::unused(signature);
+
+ const CallConv& cc = func.callConv();
+ uint32_t stackOffset = 0;
+
+ uint32_t i;
+ uint32_t argCount = func.argCount();
+
+ if (func.hasRet()) {
+ for (uint32_t valueIndex = 0; valueIndex < Globals::kMaxValuePack; valueIndex++) {
+ TypeId typeId = func._rets[valueIndex].typeId();
+
+ // Terminate at the first void type (end of the pack).
+ if (typeId == TypeId::kVoid)
+ break;
+
+ switch (typeId) {
+ case TypeId::kInt8:
+ case TypeId::kInt16:
+ case TypeId::kInt32: {
+ func._rets[valueIndex].initReg(RegType::kARM_GpW, valueIndex, TypeId::kInt32);
+ break;
+ }
+
+ case TypeId::kUInt8:
+ case TypeId::kUInt16:
+ case TypeId::kUInt32: {
+ func._rets[valueIndex].initReg(RegType::kARM_GpW, valueIndex, TypeId::kUInt32);
+ break;
+ }
+
+ case TypeId::kInt64:
+ case TypeId::kUInt64: {
+ func._rets[valueIndex].initReg(RegType::kARM_GpX, valueIndex, typeId);
+ break;
+ }
+
+ default: {
+ RegType regType = regTypeFromFpOrVecTypeId(typeId);
+ if (regType == RegType::kNone)
+ return DebugUtils::errored(kErrorInvalidRegType);
+
+ func._rets[valueIndex].initReg(regType, valueIndex, typeId);
+ break;
+ }
+ }
+ }
+ }
+
+ switch (cc.strategy()) {
+ case CallConvStrategy::kDefault: {
+ uint32_t gpzPos = 0;
+ uint32_t vecPos = 0;
+
+ for (i = 0; i < argCount; i++) {
+ FuncValue& arg = func._args[i][0];
+ TypeId typeId = arg.typeId();
+
+ if (TypeUtils::isInt(typeId)) {
+ uint32_t regId = BaseReg::kIdBad;
+
+ if (gpzPos < CallConv::kMaxRegArgsPerGroup)
+ regId = cc._passedOrder[RegGroup::kGp].id[gpzPos];
+
+ if (regId != BaseReg::kIdBad) {
+ RegType regType = typeId <= TypeId::kUInt32 ? RegType::kARM_GpW : RegType::kARM_GpX;
+ arg.assignRegData(regType, regId);
+ func.addUsedRegs(RegGroup::kGp, Support::bitMask(regId));
+ gpzPos++;
+ }
+ else {
+ uint32_t size = Support::max<uint32_t>(TypeUtils::sizeOf(typeId), registerSize);
+ arg.assignStackOffset(int32_t(stackOffset));
+ stackOffset += size;
+ }
+ continue;
+ }
+
+ if (TypeUtils::isFloat(typeId) || TypeUtils::isVec(typeId)) {
+ uint32_t regId = BaseReg::kIdBad;
+
+ if (vecPos < CallConv::kMaxRegArgsPerGroup)
+ regId = cc._passedOrder[RegGroup::kVec].id[vecPos];
+
+ if (regId != BaseReg::kIdBad) {
+ RegType regType = regTypeFromFpOrVecTypeId(typeId);
+ if (regType == RegType::kNone)
+ return DebugUtils::errored(kErrorInvalidRegType);
+
+ arg.initTypeId(typeId);
+ arg.assignRegData(regType, regId);
+ func.addUsedRegs(RegGroup::kVec, Support::bitMask(regId));
+ vecPos++;
+ }
+ else {
+ uint32_t size = TypeUtils::sizeOf(typeId);
+ arg.assignStackOffset(int32_t(stackOffset));
+ stackOffset += size;
+ }
+ continue;
+ }
+ }
+ break;
+ }
+
+ default:
+ return DebugUtils::errored(kErrorInvalidState);
+ }
+
+ func._argStackSize = stackOffset;
+ return kErrorOk;
+}
+
+} // {FuncInternal}
+
+ASMJIT_END_SUB_NAMESPACE
+
+#endif // !ASMJIT_NO_AARCH64
diff --git a/3rdparty/asmjit/src/asmjit/arm/a64func_p.h b/3rdparty/asmjit/src/asmjit/arm/a64func_p.h
new file mode 100644
index 00000000000..9f531fc5a23
--- /dev/null
+++ b/3rdparty/asmjit/src/asmjit/arm/a64func_p.h
@@ -0,0 +1,33 @@
+// This file is part of AsmJit project <https://asmjit.com>
+//
+// See asmjit.h or LICENSE.md for license and copyright information
+// SPDX-License-Identifier: Zlib
+
+#ifndef ASMJIT_ARM_A64FUNC_P_H_INCLUDED
+#define ASMJIT_ARM_A64FUNC_P_H_INCLUDED
+
+#include "../core/func.h"
+
+ASMJIT_BEGIN_SUB_NAMESPACE(a64)
+
+//! \cond INTERNAL
+//! \addtogroup asmjit_a64
+//! \{
+
+//! AArch64-specific function API (calling conventions and other utilities).
+namespace FuncInternal {
+
+//! Initialize `CallConv` structure (AArch64 specific).
+Error initCallConv(CallConv& cc, CallConvId ccId, const Environment& environment) noexcept;
+
+//! Initialize `FuncDetail` (AArch64 specific).
+Error initFuncDetail(FuncDetail& func, const FuncSignature& signature, uint32_t registerSize) noexcept;
+
+} // {FuncInternal}
+
+//! \}
+//! \endcond
+
+ASMJIT_END_SUB_NAMESPACE
+
+#endif // ASMJIT_ARM_A64FUNC_P_H_INCLUDED
diff --git a/3rdparty/asmjit/src/asmjit/arm/a64globals.h b/3rdparty/asmjit/src/asmjit/arm/a64globals.h
new file mode 100644
index 00000000000..2b6b6f0ce91
--- /dev/null
+++ b/3rdparty/asmjit/src/asmjit/arm/a64globals.h
@@ -0,0 +1,1894 @@
+// This file is part of AsmJit project <https://asmjit.com>
+//
+// See asmjit.h or LICENSE.md for license and copyright information
+// SPDX-License-Identifier: Zlib
+
+#ifndef ASMJIT_ARM_A64GLOBALS_H_INCLUDED
+#define ASMJIT_ARM_A64GLOBALS_H_INCLUDED
+
+#include "../arm/armglobals.h"
+
+//! \namespace asmjit::a64
+//! \ingroup asmjit_a64
+//!
+//! AArch64 backend.
+
+ASMJIT_BEGIN_SUB_NAMESPACE(a64)
+
+// a64 uses everything from arm namespace and adds into it.
+using namespace arm;
+
+//! \addtogroup asmjit_a64
+//! \{
+
+//! AArch64 instruction.
+//!
+//! \note Only used to hold ARM-specific enumerations and static functions.
+struct Inst {
+ //! Instruction id.
+ enum Id : uint32_t {
+ // ${InstId:Begin}
+ kIdNone = 0, //!< Instruction ''.
+ kIdAdc, //!< Instruction 'adc'.
+ kIdAdcs, //!< Instruction 'adcs'.
+ kIdAdd, //!< Instruction 'add'.
+ kIdAddg, //!< Instruction 'addg'.
+ kIdAdds, //!< Instruction 'adds'.
+ kIdAdr, //!< Instruction 'adr'.
+ kIdAdrp, //!< Instruction 'adrp'.
+ kIdAnd, //!< Instruction 'and'.
+ kIdAnds, //!< Instruction 'ands'.
+ kIdAsr, //!< Instruction 'asr'.
+ kIdAsrv, //!< Instruction 'asrv'.
+ kIdAt, //!< Instruction 'at'.
+ kIdAutda, //!< Instruction 'autda'.
+ kIdAutdza, //!< Instruction 'autdza'.
+ kIdAutdb, //!< Instruction 'autdb'.
+ kIdAutdzb, //!< Instruction 'autdzb'.
+ kIdAutia, //!< Instruction 'autia'.
+ kIdAutia1716, //!< Instruction 'autia1716'.
+ kIdAutiasp, //!< Instruction 'autiasp'.
+ kIdAutiaz, //!< Instruction 'autiaz'.
+ kIdAutib, //!< Instruction 'autib'.
+ kIdAutib1716, //!< Instruction 'autib1716'.
+ kIdAutibsp, //!< Instruction 'autibsp'.
+ kIdAutibz, //!< Instruction 'autibz'.
+ kIdAutiza, //!< Instruction 'autiza'.
+ kIdAutizb, //!< Instruction 'autizb'.
+ kIdAxflag, //!< Instruction 'axflag'.
+ kIdB, //!< Instruction 'b'.
+ kIdBfc, //!< Instruction 'bfc'.
+ kIdBfi, //!< Instruction 'bfi'.
+ kIdBfm, //!< Instruction 'bfm'.
+ kIdBfxil, //!< Instruction 'bfxil'.
+ kIdBic, //!< Instruction 'bic'.
+ kIdBics, //!< Instruction 'bics'.
+ kIdBl, //!< Instruction 'bl'.
+ kIdBlr, //!< Instruction 'blr'.
+ kIdBr, //!< Instruction 'br'.
+ kIdBrk, //!< Instruction 'brk'.
+ kIdCas, //!< Instruction 'cas'.
+ kIdCasa, //!< Instruction 'casa'.
+ kIdCasab, //!< Instruction 'casab'.
+ kIdCasah, //!< Instruction 'casah'.
+ kIdCasal, //!< Instruction 'casal'.
+ kIdCasalb, //!< Instruction 'casalb'.
+ kIdCasalh, //!< Instruction 'casalh'.
+ kIdCasb, //!< Instruction 'casb'.
+ kIdCash, //!< Instruction 'cash'.
+ kIdCasl, //!< Instruction 'casl'.
+ kIdCaslb, //!< Instruction 'caslb'.
+ kIdCaslh, //!< Instruction 'caslh'.
+ kIdCasp, //!< Instruction 'casp'.
+ kIdCaspa, //!< Instruction 'caspa'.
+ kIdCaspal, //!< Instruction 'caspal'.
+ kIdCaspl, //!< Instruction 'caspl'.
+ kIdCbnz, //!< Instruction 'cbnz'.
+ kIdCbz, //!< Instruction 'cbz'.
+ kIdCcmn, //!< Instruction 'ccmn'.
+ kIdCcmp, //!< Instruction 'ccmp'.
+ kIdCfinv, //!< Instruction 'cfinv'.
+ kIdCinc, //!< Instruction 'cinc'.
+ kIdCinv, //!< Instruction 'cinv'.
+ kIdClrex, //!< Instruction 'clrex'.
+ kIdCls, //!< Instruction 'cls'.
+ kIdClz, //!< Instruction 'clz'.
+ kIdCmn, //!< Instruction 'cmn'.
+ kIdCmp, //!< Instruction 'cmp'.
+ kIdCmpp, //!< Instruction 'cmpp'.
+ kIdCneg, //!< Instruction 'cneg'.
+ kIdCrc32b, //!< Instruction 'crc32b'.
+ kIdCrc32cb, //!< Instruction 'crc32cb'.
+ kIdCrc32ch, //!< Instruction 'crc32ch'.
+ kIdCrc32cw, //!< Instruction 'crc32cw'.
+ kIdCrc32cx, //!< Instruction 'crc32cx'.
+ kIdCrc32h, //!< Instruction 'crc32h'.
+ kIdCrc32w, //!< Instruction 'crc32w'.
+ kIdCrc32x, //!< Instruction 'crc32x'.
+ kIdCsdb, //!< Instruction 'csdb'.
+ kIdCsel, //!< Instruction 'csel'.
+ kIdCset, //!< Instruction 'cset'.
+ kIdCsetm, //!< Instruction 'csetm'.
+ kIdCsinc, //!< Instruction 'csinc'.
+ kIdCsinv, //!< Instruction 'csinv'.
+ kIdCsneg, //!< Instruction 'csneg'.
+ kIdDc, //!< Instruction 'dc'.
+ kIdDcps1, //!< Instruction 'dcps1'.
+ kIdDcps2, //!< Instruction 'dcps2'.
+ kIdDcps3, //!< Instruction 'dcps3'.
+ kIdDgh, //!< Instruction 'dgh'.
+ kIdDmb, //!< Instruction 'dmb'.
+ kIdDrps, //!< Instruction 'drps'.
+ kIdDsb, //!< Instruction 'dsb'.
+ kIdEon, //!< Instruction 'eon'.
+ kIdEor, //!< Instruction 'eor'.
+ kIdEsb, //!< Instruction 'esb'.
+ kIdExtr, //!< Instruction 'extr'.
+ kIdEret, //!< Instruction 'eret'.
+ kIdGmi, //!< Instruction 'gmi'.
+ kIdHint, //!< Instruction 'hint'.
+ kIdHlt, //!< Instruction 'hlt'.
+ kIdHvc, //!< Instruction 'hvc'.
+ kIdIc, //!< Instruction 'ic'.
+ kIdIsb, //!< Instruction 'isb'.
+ kIdLdadd, //!< Instruction 'ldadd'.
+ kIdLdadda, //!< Instruction 'ldadda'.
+ kIdLdaddab, //!< Instruction 'ldaddab'.
+ kIdLdaddah, //!< Instruction 'ldaddah'.
+ kIdLdaddal, //!< Instruction 'ldaddal'.
+ kIdLdaddalb, //!< Instruction 'ldaddalb'.
+ kIdLdaddalh, //!< Instruction 'ldaddalh'.
+ kIdLdaddb, //!< Instruction 'ldaddb'.
+ kIdLdaddh, //!< Instruction 'ldaddh'.
+ kIdLdaddl, //!< Instruction 'ldaddl'.
+ kIdLdaddlb, //!< Instruction 'ldaddlb'.
+ kIdLdaddlh, //!< Instruction 'ldaddlh'.
+ kIdLdar, //!< Instruction 'ldar'.
+ kIdLdarb, //!< Instruction 'ldarb'.
+ kIdLdarh, //!< Instruction 'ldarh'.
+ kIdLdaxp, //!< Instruction 'ldaxp'.
+ kIdLdaxr, //!< Instruction 'ldaxr'.
+ kIdLdaxrb, //!< Instruction 'ldaxrb'.
+ kIdLdaxrh, //!< Instruction 'ldaxrh'.
+ kIdLdclr, //!< Instruction 'ldclr'.
+ kIdLdclra, //!< Instruction 'ldclra'.
+ kIdLdclrab, //!< Instruction 'ldclrab'.
+ kIdLdclrah, //!< Instruction 'ldclrah'.
+ kIdLdclral, //!< Instruction 'ldclral'.
+ kIdLdclralb, //!< Instruction 'ldclralb'.
+ kIdLdclralh, //!< Instruction 'ldclralh'.
+ kIdLdclrb, //!< Instruction 'ldclrb'.
+ kIdLdclrh, //!< Instruction 'ldclrh'.
+ kIdLdclrl, //!< Instruction 'ldclrl'.
+ kIdLdclrlb, //!< Instruction 'ldclrlb'.
+ kIdLdclrlh, //!< Instruction 'ldclrlh'.
+ kIdLdeor, //!< Instruction 'ldeor'.
+ kIdLdeora, //!< Instruction 'ldeora'.
+ kIdLdeorab, //!< Instruction 'ldeorab'.
+ kIdLdeorah, //!< Instruction 'ldeorah'.
+ kIdLdeoral, //!< Instruction 'ldeoral'.
+ kIdLdeoralb, //!< Instruction 'ldeoralb'.
+ kIdLdeoralh, //!< Instruction 'ldeoralh'.
+ kIdLdeorb, //!< Instruction 'ldeorb'.
+ kIdLdeorh, //!< Instruction 'ldeorh'.
+ kIdLdeorl, //!< Instruction 'ldeorl'.
+ kIdLdeorlb, //!< Instruction 'ldeorlb'.
+ kIdLdeorlh, //!< Instruction 'ldeorlh'.
+ kIdLdg, //!< Instruction 'ldg'.
+ kIdLdgm, //!< Instruction 'ldgm'.
+ kIdLdlar, //!< Instruction 'ldlar'.
+ kIdLdlarb, //!< Instruction 'ldlarb'.
+ kIdLdlarh, //!< Instruction 'ldlarh'.
+ kIdLdnp, //!< Instruction 'ldnp'.
+ kIdLdp, //!< Instruction 'ldp'.
+ kIdLdpsw, //!< Instruction 'ldpsw'.
+ kIdLdr, //!< Instruction 'ldr'.
+ kIdLdraa, //!< Instruction 'ldraa'.
+ kIdLdrab, //!< Instruction 'ldrab'.
+ kIdLdrb, //!< Instruction 'ldrb'.
+ kIdLdrh, //!< Instruction 'ldrh'.
+ kIdLdrsb, //!< Instruction 'ldrsb'.
+ kIdLdrsh, //!< Instruction 'ldrsh'.
+ kIdLdrsw, //!< Instruction 'ldrsw'.
+ kIdLdset, //!< Instruction 'ldset'.
+ kIdLdseta, //!< Instruction 'ldseta'.
+ kIdLdsetab, //!< Instruction 'ldsetab'.
+ kIdLdsetah, //!< Instruction 'ldsetah'.
+ kIdLdsetal, //!< Instruction 'ldsetal'.
+ kIdLdsetalb, //!< Instruction 'ldsetalb'.
+ kIdLdsetalh, //!< Instruction 'ldsetalh'.
+ kIdLdsetb, //!< Instruction 'ldsetb'.
+ kIdLdseth, //!< Instruction 'ldseth'.
+ kIdLdsetl, //!< Instruction 'ldsetl'.
+ kIdLdsetlb, //!< Instruction 'ldsetlb'.
+ kIdLdsetlh, //!< Instruction 'ldsetlh'.
+ kIdLdsmax, //!< Instruction 'ldsmax'.
+ kIdLdsmaxa, //!< Instruction 'ldsmaxa'.
+ kIdLdsmaxab, //!< Instruction 'ldsmaxab'.
+ kIdLdsmaxah, //!< Instruction 'ldsmaxah'.
+ kIdLdsmaxal, //!< Instruction 'ldsmaxal'.
+ kIdLdsmaxalb, //!< Instruction 'ldsmaxalb'.
+ kIdLdsmaxalh, //!< Instruction 'ldsmaxalh'.
+ kIdLdsmaxb, //!< Instruction 'ldsmaxb'.
+ kIdLdsmaxh, //!< Instruction 'ldsmaxh'.
+ kIdLdsmaxl, //!< Instruction 'ldsmaxl'.
+ kIdLdsmaxlb, //!< Instruction 'ldsmaxlb'.
+ kIdLdsmaxlh, //!< Instruction 'ldsmaxlh'.
+ kIdLdsmin, //!< Instruction 'ldsmin'.
+ kIdLdsmina, //!< Instruction 'ldsmina'.
+ kIdLdsminab, //!< Instruction 'ldsminab'.
+ kIdLdsminah, //!< Instruction 'ldsminah'.
+ kIdLdsminal, //!< Instruction 'ldsminal'.
+ kIdLdsminalb, //!< Instruction 'ldsminalb'.
+ kIdLdsminalh, //!< Instruction 'ldsminalh'.
+ kIdLdsminb, //!< Instruction 'ldsminb'.
+ kIdLdsminh, //!< Instruction 'ldsminh'.
+ kIdLdsminl, //!< Instruction 'ldsminl'.
+ kIdLdsminlb, //!< Instruction 'ldsminlb'.
+ kIdLdsminlh, //!< Instruction 'ldsminlh'.
+ kIdLdtr, //!< Instruction 'ldtr'.
+ kIdLdtrb, //!< Instruction 'ldtrb'.
+ kIdLdtrh, //!< Instruction 'ldtrh'.
+ kIdLdtrsb, //!< Instruction 'ldtrsb'.
+ kIdLdtrsh, //!< Instruction 'ldtrsh'.
+ kIdLdtrsw, //!< Instruction 'ldtrsw'.
+ kIdLdumax, //!< Instruction 'ldumax'.
+ kIdLdumaxa, //!< Instruction 'ldumaxa'.
+ kIdLdumaxab, //!< Instruction 'ldumaxab'.
+ kIdLdumaxah, //!< Instruction 'ldumaxah'.
+ kIdLdumaxal, //!< Instruction 'ldumaxal'.
+ kIdLdumaxalb, //!< Instruction 'ldumaxalb'.
+ kIdLdumaxalh, //!< Instruction 'ldumaxalh'.
+ kIdLdumaxb, //!< Instruction 'ldumaxb'.
+ kIdLdumaxh, //!< Instruction 'ldumaxh'.
+ kIdLdumaxl, //!< Instruction 'ldumaxl'.
+ kIdLdumaxlb, //!< Instruction 'ldumaxlb'.
+ kIdLdumaxlh, //!< Instruction 'ldumaxlh'.
+ kIdLdumin, //!< Instruction 'ldumin'.
+ kIdLdumina, //!< Instruction 'ldumina'.
+ kIdLduminab, //!< Instruction 'lduminab'.
+ kIdLduminah, //!< Instruction 'lduminah'.
+ kIdLduminal, //!< Instruction 'lduminal'.
+ kIdLduminalb, //!< Instruction 'lduminalb'.
+ kIdLduminalh, //!< Instruction 'lduminalh'.
+ kIdLduminb, //!< Instruction 'lduminb'.
+ kIdLduminh, //!< Instruction 'lduminh'.
+ kIdLduminl, //!< Instruction 'lduminl'.
+ kIdLduminlb, //!< Instruction 'lduminlb'.
+ kIdLduminlh, //!< Instruction 'lduminlh'.
+ kIdLdur, //!< Instruction 'ldur'.
+ kIdLdurb, //!< Instruction 'ldurb'.
+ kIdLdurh, //!< Instruction 'ldurh'.
+ kIdLdursb, //!< Instruction 'ldursb'.
+ kIdLdursh, //!< Instruction 'ldursh'.
+ kIdLdursw, //!< Instruction 'ldursw'.
+ kIdLdxp, //!< Instruction 'ldxp'.
+ kIdLdxr, //!< Instruction 'ldxr'.
+ kIdLdxrb, //!< Instruction 'ldxrb'.
+ kIdLdxrh, //!< Instruction 'ldxrh'.
+ kIdLsl, //!< Instruction 'lsl'.
+ kIdLslv, //!< Instruction 'lslv'.
+ kIdLsr, //!< Instruction 'lsr'.
+ kIdLsrv, //!< Instruction 'lsrv'.
+ kIdMadd, //!< Instruction 'madd'.
+ kIdMneg, //!< Instruction 'mneg'.
+ kIdMov, //!< Instruction 'mov'.
+ kIdMovk, //!< Instruction 'movk'.
+ kIdMovn, //!< Instruction 'movn'.
+ kIdMovz, //!< Instruction 'movz'.
+ kIdMrs, //!< Instruction 'mrs'.
+ kIdMsr, //!< Instruction 'msr'.
+ kIdMsub, //!< Instruction 'msub'.
+ kIdMul, //!< Instruction 'mul'.
+ kIdMvn, //!< Instruction 'mvn'.
+ kIdNeg, //!< Instruction 'neg'.
+ kIdNegs, //!< Instruction 'negs'.
+ kIdNgc, //!< Instruction 'ngc'.
+ kIdNgcs, //!< Instruction 'ngcs'.
+ kIdNop, //!< Instruction 'nop'.
+ kIdOrn, //!< Instruction 'orn'.
+ kIdOrr, //!< Instruction 'orr'.
+ kIdPacda, //!< Instruction 'pacda'.
+ kIdPacdb, //!< Instruction 'pacdb'.
+ kIdPacdza, //!< Instruction 'pacdza'.
+ kIdPacdzb, //!< Instruction 'pacdzb'.
+ kIdPacga, //!< Instruction 'pacga'.
+ kIdPssbb, //!< Instruction 'pssbb'.
+ kIdRbit, //!< Instruction 'rbit'.
+ kIdRet, //!< Instruction 'ret'.
+ kIdRev, //!< Instruction 'rev'.
+ kIdRev16, //!< Instruction 'rev16'.
+ kIdRev32, //!< Instruction 'rev32'.
+ kIdRev64, //!< Instruction 'rev64'.
+ kIdRor, //!< Instruction 'ror'.
+ kIdRorv, //!< Instruction 'rorv'.
+ kIdSbc, //!< Instruction 'sbc'.
+ kIdSbcs, //!< Instruction 'sbcs'.
+ kIdSbfiz, //!< Instruction 'sbfiz'.
+ kIdSbfm, //!< Instruction 'sbfm'.
+ kIdSbfx, //!< Instruction 'sbfx'.
+ kIdSdiv, //!< Instruction 'sdiv'.
+ kIdSetf8, //!< Instruction 'setf8'.
+ kIdSetf16, //!< Instruction 'setf16'.
+ kIdSev, //!< Instruction 'sev'.
+ kIdSevl, //!< Instruction 'sevl'.
+ kIdSmaddl, //!< Instruction 'smaddl'.
+ kIdSmc, //!< Instruction 'smc'.
+ kIdSmnegl, //!< Instruction 'smnegl'.
+ kIdSmsubl, //!< Instruction 'smsubl'.
+ kIdSmulh, //!< Instruction 'smulh'.
+ kIdSmull, //!< Instruction 'smull'.
+ kIdSsbb, //!< Instruction 'ssbb'.
+ kIdSt2g, //!< Instruction 'st2g'.
+ kIdStadd, //!< Instruction 'stadd'.
+ kIdStaddl, //!< Instruction 'staddl'.
+ kIdStaddb, //!< Instruction 'staddb'.
+ kIdStaddlb, //!< Instruction 'staddlb'.
+ kIdStaddh, //!< Instruction 'staddh'.
+ kIdStaddlh, //!< Instruction 'staddlh'.
+ kIdStclr, //!< Instruction 'stclr'.
+ kIdStclrl, //!< Instruction 'stclrl'.
+ kIdStclrb, //!< Instruction 'stclrb'.
+ kIdStclrlb, //!< Instruction 'stclrlb'.
+ kIdStclrh, //!< Instruction 'stclrh'.
+ kIdStclrlh, //!< Instruction 'stclrlh'.
+ kIdSteor, //!< Instruction 'steor'.
+ kIdSteorl, //!< Instruction 'steorl'.
+ kIdSteorb, //!< Instruction 'steorb'.
+ kIdSteorlb, //!< Instruction 'steorlb'.
+ kIdSteorh, //!< Instruction 'steorh'.
+ kIdSteorlh, //!< Instruction 'steorlh'.
+ kIdStg, //!< Instruction 'stg'.
+ kIdStgm, //!< Instruction 'stgm'.
+ kIdStgp, //!< Instruction 'stgp'.
+ kIdStllr, //!< Instruction 'stllr'.
+ kIdStllrb, //!< Instruction 'stllrb'.
+ kIdStllrh, //!< Instruction 'stllrh'.
+ kIdStlr, //!< Instruction 'stlr'.
+ kIdStlrb, //!< Instruction 'stlrb'.
+ kIdStlrh, //!< Instruction 'stlrh'.
+ kIdStlxp, //!< Instruction 'stlxp'.
+ kIdStlxr, //!< Instruction 'stlxr'.
+ kIdStlxrb, //!< Instruction 'stlxrb'.
+ kIdStlxrh, //!< Instruction 'stlxrh'.
+ kIdStnp, //!< Instruction 'stnp'.
+ kIdStp, //!< Instruction 'stp'.
+ kIdStr, //!< Instruction 'str'.
+ kIdStrb, //!< Instruction 'strb'.
+ kIdStrh, //!< Instruction 'strh'.
+ kIdStset, //!< Instruction 'stset'.
+ kIdStsetl, //!< Instruction 'stsetl'.
+ kIdStsetb, //!< Instruction 'stsetb'.
+ kIdStsetlb, //!< Instruction 'stsetlb'.
+ kIdStseth, //!< Instruction 'stseth'.
+ kIdStsetlh, //!< Instruction 'stsetlh'.
+ kIdStsmax, //!< Instruction 'stsmax'.
+ kIdStsmaxl, //!< Instruction 'stsmaxl'.
+ kIdStsmaxb, //!< Instruction 'stsmaxb'.
+ kIdStsmaxlb, //!< Instruction 'stsmaxlb'.
+ kIdStsmaxh, //!< Instruction 'stsmaxh'.
+ kIdStsmaxlh, //!< Instruction 'stsmaxlh'.
+ kIdStsmin, //!< Instruction 'stsmin'.
+ kIdStsminl, //!< Instruction 'stsminl'.
+ kIdStsminb, //!< Instruction 'stsminb'.
+ kIdStsminlb, //!< Instruction 'stsminlb'.
+ kIdStsminh, //!< Instruction 'stsminh'.
+ kIdStsminlh, //!< Instruction 'stsminlh'.
+ kIdSttr, //!< Instruction 'sttr'.
+ kIdSttrb, //!< Instruction 'sttrb'.
+ kIdSttrh, //!< Instruction 'sttrh'.
+ kIdStumax, //!< Instruction 'stumax'.
+ kIdStumaxl, //!< Instruction 'stumaxl'.
+ kIdStumaxb, //!< Instruction 'stumaxb'.
+ kIdStumaxlb, //!< Instruction 'stumaxlb'.
+ kIdStumaxh, //!< Instruction 'stumaxh'.
+ kIdStumaxlh, //!< Instruction 'stumaxlh'.
+ kIdStumin, //!< Instruction 'stumin'.
+ kIdStuminl, //!< Instruction 'stuminl'.
+ kIdStuminb, //!< Instruction 'stuminb'.
+ kIdStuminlb, //!< Instruction 'stuminlb'.
+ kIdStuminh, //!< Instruction 'stuminh'.
+ kIdStuminlh, //!< Instruction 'stuminlh'.
+ kIdStur, //!< Instruction 'stur'.
+ kIdSturb, //!< Instruction 'sturb'.
+ kIdSturh, //!< Instruction 'sturh'.
+ kIdStxp, //!< Instruction 'stxp'.
+ kIdStxr, //!< Instruction 'stxr'.
+ kIdStxrb, //!< Instruction 'stxrb'.
+ kIdStxrh, //!< Instruction 'stxrh'.
+ kIdStz2g, //!< Instruction 'stz2g'.
+ kIdStzg, //!< Instruction 'stzg'.
+ kIdStzgm, //!< Instruction 'stzgm'.
+ kIdSub, //!< Instruction 'sub'.
+ kIdSubg, //!< Instruction 'subg'.
+ kIdSubp, //!< Instruction 'subp'.
+ kIdSubps, //!< Instruction 'subps'.
+ kIdSubs, //!< Instruction 'subs'.
+ kIdSvc, //!< Instruction 'svc'.
+ kIdSwp, //!< Instruction 'swp'.
+ kIdSwpa, //!< Instruction 'swpa'.
+ kIdSwpab, //!< Instruction 'swpab'.
+ kIdSwpah, //!< Instruction 'swpah'.
+ kIdSwpal, //!< Instruction 'swpal'.
+ kIdSwpalb, //!< Instruction 'swpalb'.
+ kIdSwpalh, //!< Instruction 'swpalh'.
+ kIdSwpb, //!< Instruction 'swpb'.
+ kIdSwph, //!< Instruction 'swph'.
+ kIdSwpl, //!< Instruction 'swpl'.
+ kIdSwplb, //!< Instruction 'swplb'.
+ kIdSwplh, //!< Instruction 'swplh'.
+ kIdSxtb, //!< Instruction 'sxtb'.
+ kIdSxth, //!< Instruction 'sxth'.
+ kIdSxtw, //!< Instruction 'sxtw'.
+ kIdSys, //!< Instruction 'sys'.
+ kIdTlbi, //!< Instruction 'tlbi'.
+ kIdTst, //!< Instruction 'tst'.
+ kIdTbnz, //!< Instruction 'tbnz'.
+ kIdTbz, //!< Instruction 'tbz'.
+ kIdUbfiz, //!< Instruction 'ubfiz'.
+ kIdUbfm, //!< Instruction 'ubfm'.
+ kIdUbfx, //!< Instruction 'ubfx'.
+ kIdUdf, //!< Instruction 'udf'.
+ kIdUdiv, //!< Instruction 'udiv'.
+ kIdUmaddl, //!< Instruction 'umaddl'.
+ kIdUmnegl, //!< Instruction 'umnegl'.
+ kIdUmull, //!< Instruction 'umull'.
+ kIdUmulh, //!< Instruction 'umulh'.
+ kIdUmsubl, //!< Instruction 'umsubl'.
+ kIdUxtb, //!< Instruction 'uxtb'.
+ kIdUxth, //!< Instruction 'uxth'.
+ kIdWfe, //!< Instruction 'wfe'.
+ kIdWfi, //!< Instruction 'wfi'.
+ kIdXaflag, //!< Instruction 'xaflag'.
+ kIdXpacd, //!< Instruction 'xpacd'.
+ kIdXpaci, //!< Instruction 'xpaci'.
+ kIdXpaclri, //!< Instruction 'xpaclri'.
+ kIdYield, //!< Instruction 'yield'.
+ kIdAbs_v, //!< Instruction 'abs' {ASIMD}.
+ kIdAdd_v, //!< Instruction 'add' {ASIMD}.
+ kIdAddhn_v, //!< Instruction 'addhn' {ASIMD}.
+ kIdAddhn2_v, //!< Instruction 'addhn2' {ASIMD}.
+ kIdAddp_v, //!< Instruction 'addp' {ASIMD}.
+ kIdAddv_v, //!< Instruction 'addv' {ASIMD}.
+ kIdAesd_v, //!< Instruction 'aesd' {ASIMD}.
+ kIdAese_v, //!< Instruction 'aese' {ASIMD}.
+ kIdAesimc_v, //!< Instruction 'aesimc' {ASIMD}.
+ kIdAesmc_v, //!< Instruction 'aesmc' {ASIMD}.
+ kIdAnd_v, //!< Instruction 'and' {ASIMD}.
+ kIdBcax_v, //!< Instruction 'bcax' {ASIMD}.
+ kIdBfcvt_v, //!< Instruction 'bfcvt' {ASIMD}.
+ kIdBfcvtn_v, //!< Instruction 'bfcvtn' {ASIMD}.
+ kIdBfcvtn2_v, //!< Instruction 'bfcvtn2' {ASIMD}.
+ kIdBfdot_v, //!< Instruction 'bfdot' {ASIMD}.
+ kIdBfmlalb_v, //!< Instruction 'bfmlalb' {ASIMD}.
+ kIdBfmlalt_v, //!< Instruction 'bfmlalt' {ASIMD}.
+ kIdBfmmla_v, //!< Instruction 'bfmmla' {ASIMD}.
+ kIdBic_v, //!< Instruction 'bic' {ASIMD}.
+ kIdBif_v, //!< Instruction 'bif' {ASIMD}.
+ kIdBit_v, //!< Instruction 'bit' {ASIMD}.
+ kIdBsl_v, //!< Instruction 'bsl' {ASIMD}.
+ kIdCls_v, //!< Instruction 'cls' {ASIMD}.
+ kIdClz_v, //!< Instruction 'clz' {ASIMD}.
+ kIdCmeq_v, //!< Instruction 'cmeq' {ASIMD}.
+ kIdCmge_v, //!< Instruction 'cmge' {ASIMD}.
+ kIdCmgt_v, //!< Instruction 'cmgt' {ASIMD}.
+ kIdCmhi_v, //!< Instruction 'cmhi' {ASIMD}.
+ kIdCmhs_v, //!< Instruction 'cmhs' {ASIMD}.
+ kIdCmle_v, //!< Instruction 'cmle' {ASIMD}.
+ kIdCmlt_v, //!< Instruction 'cmlt' {ASIMD}.
+ kIdCmtst_v, //!< Instruction 'cmtst' {ASIMD}.
+ kIdCnt_v, //!< Instruction 'cnt' {ASIMD}.
+ kIdDup_v, //!< Instruction 'dup' {ASIMD}.
+ kIdEor_v, //!< Instruction 'eor' {ASIMD}.
+ kIdEor3_v, //!< Instruction 'eor3' {ASIMD}.
+ kIdExt_v, //!< Instruction 'ext' {ASIMD}.
+ kIdFabd_v, //!< Instruction 'fabd' {ASIMD}.
+ kIdFabs_v, //!< Instruction 'fabs' {ASIMD}.
+ kIdFacge_v, //!< Instruction 'facge' {ASIMD}.
+ kIdFacgt_v, //!< Instruction 'facgt' {ASIMD}.
+ kIdFadd_v, //!< Instruction 'fadd' {ASIMD}.
+ kIdFaddp_v, //!< Instruction 'faddp' {ASIMD}.
+ kIdFcadd_v, //!< Instruction 'fcadd' {ASIMD}.
+ kIdFccmp_v, //!< Instruction 'fccmp' {ASIMD}.
+ kIdFccmpe_v, //!< Instruction 'fccmpe' {ASIMD}.
+ kIdFcmeq_v, //!< Instruction 'fcmeq' {ASIMD}.
+ kIdFcmge_v, //!< Instruction 'fcmge' {ASIMD}.
+ kIdFcmgt_v, //!< Instruction 'fcmgt' {ASIMD}.
+ kIdFcmla_v, //!< Instruction 'fcmla' {ASIMD}.
+ kIdFcmle_v, //!< Instruction 'fcmle' {ASIMD}.
+ kIdFcmlt_v, //!< Instruction 'fcmlt' {ASIMD}.
+ kIdFcmp_v, //!< Instruction 'fcmp' {ASIMD}.
+ kIdFcmpe_v, //!< Instruction 'fcmpe' {ASIMD}.
+ kIdFcsel_v, //!< Instruction 'fcsel' {ASIMD}.
+ kIdFcvt_v, //!< Instruction 'fcvt' {ASIMD}.
+ kIdFcvtas_v, //!< Instruction 'fcvtas' {ASIMD}.
+ kIdFcvtau_v, //!< Instruction 'fcvtau' {ASIMD}.
+ kIdFcvtl_v, //!< Instruction 'fcvtl' {ASIMD}.
+ kIdFcvtl2_v, //!< Instruction 'fcvtl2' {ASIMD}.
+ kIdFcvtms_v, //!< Instruction 'fcvtms' {ASIMD}.
+ kIdFcvtmu_v, //!< Instruction 'fcvtmu' {ASIMD}.
+ kIdFcvtn_v, //!< Instruction 'fcvtn' {ASIMD}.
+ kIdFcvtn2_v, //!< Instruction 'fcvtn2' {ASIMD}.
+ kIdFcvtns_v, //!< Instruction 'fcvtns' {ASIMD}.
+ kIdFcvtnu_v, //!< Instruction 'fcvtnu' {ASIMD}.
+ kIdFcvtps_v, //!< Instruction 'fcvtps' {ASIMD}.
+ kIdFcvtpu_v, //!< Instruction 'fcvtpu' {ASIMD}.
+ kIdFcvtxn_v, //!< Instruction 'fcvtxn' {ASIMD}.
+ kIdFcvtxn2_v, //!< Instruction 'fcvtxn2' {ASIMD}.
+ kIdFcvtzs_v, //!< Instruction 'fcvtzs' {ASIMD}.
+ kIdFcvtzu_v, //!< Instruction 'fcvtzu' {ASIMD}.
+ kIdFdiv_v, //!< Instruction 'fdiv' {ASIMD}.
+ kIdFjcvtzs_v, //!< Instruction 'fjcvtzs' {ASIMD}.
+ kIdFmadd_v, //!< Instruction 'fmadd' {ASIMD}.
+ kIdFmax_v, //!< Instruction 'fmax' {ASIMD}.
+ kIdFmaxnm_v, //!< Instruction 'fmaxnm' {ASIMD}.
+ kIdFmaxnmp_v, //!< Instruction 'fmaxnmp' {ASIMD}.
+ kIdFmaxnmv_v, //!< Instruction 'fmaxnmv' {ASIMD}.
+ kIdFmaxp_v, //!< Instruction 'fmaxp' {ASIMD}.
+ kIdFmaxv_v, //!< Instruction 'fmaxv' {ASIMD}.
+ kIdFmin_v, //!< Instruction 'fmin' {ASIMD}.
+ kIdFminnm_v, //!< Instruction 'fminnm' {ASIMD}.
+ kIdFminnmp_v, //!< Instruction 'fminnmp' {ASIMD}.
+ kIdFminnmv_v, //!< Instruction 'fminnmv' {ASIMD}.
+ kIdFminp_v, //!< Instruction 'fminp' {ASIMD}.
+ kIdFminv_v, //!< Instruction 'fminv' {ASIMD}.
+ kIdFmla_v, //!< Instruction 'fmla' {ASIMD}.
+ kIdFmlal_v, //!< Instruction 'fmlal' {ASIMD}.
+ kIdFmlal2_v, //!< Instruction 'fmlal2' {ASIMD}.
+ kIdFmls_v, //!< Instruction 'fmls' {ASIMD}.
+ kIdFmlsl_v, //!< Instruction 'fmlsl' {ASIMD}.
+ kIdFmlsl2_v, //!< Instruction 'fmlsl2' {ASIMD}.
+ kIdFmov_v, //!< Instruction 'fmov' {ASIMD}.
+ kIdFmsub_v, //!< Instruction 'fmsub' {ASIMD}.
+ kIdFmul_v, //!< Instruction 'fmul' {ASIMD}.
+ kIdFmulx_v, //!< Instruction 'fmulx' {ASIMD}.
+ kIdFneg_v, //!< Instruction 'fneg' {ASIMD}.
+ kIdFnmadd_v, //!< Instruction 'fnmadd' {ASIMD}.
+ kIdFnmsub_v, //!< Instruction 'fnmsub' {ASIMD}.
+ kIdFnmul_v, //!< Instruction 'fnmul' {ASIMD}.
+ kIdFrecpe_v, //!< Instruction 'frecpe' {ASIMD}.
+ kIdFrecps_v, //!< Instruction 'frecps' {ASIMD}.
+ kIdFrecpx_v, //!< Instruction 'frecpx' {ASIMD}.
+ kIdFrint32x_v, //!< Instruction 'frint32x' {ASIMD}.
+ kIdFrint32z_v, //!< Instruction 'frint32z' {ASIMD}.
+ kIdFrint64x_v, //!< Instruction 'frint64x' {ASIMD}.
+ kIdFrint64z_v, //!< Instruction 'frint64z' {ASIMD}.
+ kIdFrinta_v, //!< Instruction 'frinta' {ASIMD}.
+ kIdFrinti_v, //!< Instruction 'frinti' {ASIMD}.
+ kIdFrintm_v, //!< Instruction 'frintm' {ASIMD}.
+ kIdFrintn_v, //!< Instruction 'frintn' {ASIMD}.
+ kIdFrintp_v, //!< Instruction 'frintp' {ASIMD}.
+ kIdFrintx_v, //!< Instruction 'frintx' {ASIMD}.
+ kIdFrintz_v, //!< Instruction 'frintz' {ASIMD}.
+ kIdFrsqrte_v, //!< Instruction 'frsqrte' {ASIMD}.
+ kIdFrsqrts_v, //!< Instruction 'frsqrts' {ASIMD}.
+ kIdFsqrt_v, //!< Instruction 'fsqrt' {ASIMD}.
+ kIdFsub_v, //!< Instruction 'fsub' {ASIMD}.
+ kIdIns_v, //!< Instruction 'ins' {ASIMD}.
+ kIdLd1_v, //!< Instruction 'ld1' {ASIMD}.
+ kIdLd1r_v, //!< Instruction 'ld1r' {ASIMD}.
+ kIdLd2_v, //!< Instruction 'ld2' {ASIMD}.
+ kIdLd2r_v, //!< Instruction 'ld2r' {ASIMD}.
+ kIdLd3_v, //!< Instruction 'ld3' {ASIMD}.
+ kIdLd3r_v, //!< Instruction 'ld3r' {ASIMD}.
+ kIdLd4_v, //!< Instruction 'ld4' {ASIMD}.
+ kIdLd4r_v, //!< Instruction 'ld4r' {ASIMD}.
+ kIdLdnp_v, //!< Instruction 'ldnp' {ASIMD}.
+ kIdLdp_v, //!< Instruction 'ldp' {ASIMD}.
+ kIdLdr_v, //!< Instruction 'ldr' {ASIMD}.
+ kIdLdur_v, //!< Instruction 'ldur' {ASIMD}.
+ kIdMla_v, //!< Instruction 'mla' {ASIMD}.
+ kIdMls_v, //!< Instruction 'mls' {ASIMD}.
+ kIdMov_v, //!< Instruction 'mov' {ASIMD}.
+ kIdMovi_v, //!< Instruction 'movi' {ASIMD}.
+ kIdMul_v, //!< Instruction 'mul' {ASIMD}.
+ kIdMvn_v, //!< Instruction 'mvn' {ASIMD}.
+ kIdMvni_v, //!< Instruction 'mvni' {ASIMD}.
+ kIdNeg_v, //!< Instruction 'neg' {ASIMD}.
+ kIdNot_v, //!< Instruction 'not' {ASIMD}.
+ kIdOrn_v, //!< Instruction 'orn' {ASIMD}.
+ kIdOrr_v, //!< Instruction 'orr' {ASIMD}.
+ kIdPmul_v, //!< Instruction 'pmul' {ASIMD}.
+ kIdPmull_v, //!< Instruction 'pmull' {ASIMD}.
+ kIdPmull2_v, //!< Instruction 'pmull2' {ASIMD}.
+ kIdRaddhn_v, //!< Instruction 'raddhn' {ASIMD}.
+ kIdRaddhn2_v, //!< Instruction 'raddhn2' {ASIMD}.
+ kIdRax1_v, //!< Instruction 'rax1' {ASIMD}.
+ kIdRbit_v, //!< Instruction 'rbit' {ASIMD}.
+ kIdRev16_v, //!< Instruction 'rev16' {ASIMD}.
+ kIdRev32_v, //!< Instruction 'rev32' {ASIMD}.
+ kIdRev64_v, //!< Instruction 'rev64' {ASIMD}.
+ kIdRshrn_v, //!< Instruction 'rshrn' {ASIMD}.
+ kIdRshrn2_v, //!< Instruction 'rshrn2' {ASIMD}.
+ kIdRsubhn_v, //!< Instruction 'rsubhn' {ASIMD}.
+ kIdRsubhn2_v, //!< Instruction 'rsubhn2' {ASIMD}.
+ kIdSaba_v, //!< Instruction 'saba' {ASIMD}.
+ kIdSabal_v, //!< Instruction 'sabal' {ASIMD}.
+ kIdSabal2_v, //!< Instruction 'sabal2' {ASIMD}.
+ kIdSabd_v, //!< Instruction 'sabd' {ASIMD}.
+ kIdSabdl_v, //!< Instruction 'sabdl' {ASIMD}.
+ kIdSabdl2_v, //!< Instruction 'sabdl2' {ASIMD}.
+ kIdSadalp_v, //!< Instruction 'sadalp' {ASIMD}.
+ kIdSaddl_v, //!< Instruction 'saddl' {ASIMD}.
+ kIdSaddl2_v, //!< Instruction 'saddl2' {ASIMD}.
+ kIdSaddlp_v, //!< Instruction 'saddlp' {ASIMD}.
+ kIdSaddlv_v, //!< Instruction 'saddlv' {ASIMD}.
+ kIdSaddw_v, //!< Instruction 'saddw' {ASIMD}.
+ kIdSaddw2_v, //!< Instruction 'saddw2' {ASIMD}.
+ kIdScvtf_v, //!< Instruction 'scvtf' {ASIMD}.
+ kIdSdot_v, //!< Instruction 'sdot' {ASIMD}.
+ kIdSha1c_v, //!< Instruction 'sha1c' {ASIMD}.
+ kIdSha1h_v, //!< Instruction 'sha1h' {ASIMD}.
+ kIdSha1m_v, //!< Instruction 'sha1m' {ASIMD}.
+ kIdSha1p_v, //!< Instruction 'sha1p' {ASIMD}.
+ kIdSha1su0_v, //!< Instruction 'sha1su0' {ASIMD}.
+ kIdSha1su1_v, //!< Instruction 'sha1su1' {ASIMD}.
+ kIdSha256h_v, //!< Instruction 'sha256h' {ASIMD}.
+ kIdSha256h2_v, //!< Instruction 'sha256h2' {ASIMD}.
+ kIdSha256su0_v, //!< Instruction 'sha256su0' {ASIMD}.
+ kIdSha256su1_v, //!< Instruction 'sha256su1' {ASIMD}.
+ kIdSha512h_v, //!< Instruction 'sha512h' {ASIMD}.
+ kIdSha512h2_v, //!< Instruction 'sha512h2' {ASIMD}.
+ kIdSha512su0_v, //!< Instruction 'sha512su0' {ASIMD}.
+ kIdSha512su1_v, //!< Instruction 'sha512su1' {ASIMD}.
+ kIdShadd_v, //!< Instruction 'shadd' {ASIMD}.
+ kIdShl_v, //!< Instruction 'shl' {ASIMD}.
+ kIdShll_v, //!< Instruction 'shll' {ASIMD}.
+ kIdShll2_v, //!< Instruction 'shll2' {ASIMD}.
+ kIdShrn_v, //!< Instruction 'shrn' {ASIMD}.
+ kIdShrn2_v, //!< Instruction 'shrn2' {ASIMD}.
+ kIdShsub_v, //!< Instruction 'shsub' {ASIMD}.
+ kIdSli_v, //!< Instruction 'sli' {ASIMD}.
+ kIdSm3partw1_v, //!< Instruction 'sm3partw1' {ASIMD}.
+ kIdSm3partw2_v, //!< Instruction 'sm3partw2' {ASIMD}.
+ kIdSm3ss1_v, //!< Instruction 'sm3ss1' {ASIMD}.
+ kIdSm3tt1a_v, //!< Instruction 'sm3tt1a' {ASIMD}.
+ kIdSm3tt1b_v, //!< Instruction 'sm3tt1b' {ASIMD}.
+ kIdSm3tt2a_v, //!< Instruction 'sm3tt2a' {ASIMD}.
+ kIdSm3tt2b_v, //!< Instruction 'sm3tt2b' {ASIMD}.
+ kIdSm4e_v, //!< Instruction 'sm4e' {ASIMD}.
+ kIdSm4ekey_v, //!< Instruction 'sm4ekey' {ASIMD}.
+ kIdSmax_v, //!< Instruction 'smax' {ASIMD}.
+ kIdSmaxp_v, //!< Instruction 'smaxp' {ASIMD}.
+ kIdSmaxv_v, //!< Instruction 'smaxv' {ASIMD}.
+ kIdSmin_v, //!< Instruction 'smin' {ASIMD}.
+ kIdSminp_v, //!< Instruction 'sminp' {ASIMD}.
+ kIdSminv_v, //!< Instruction 'sminv' {ASIMD}.
+ kIdSmlal_v, //!< Instruction 'smlal' {ASIMD}.
+ kIdSmlal2_v, //!< Instruction 'smlal2' {ASIMD}.
+ kIdSmlsl_v, //!< Instruction 'smlsl' {ASIMD}.
+ kIdSmlsl2_v, //!< Instruction 'smlsl2' {ASIMD}.
+ kIdSmmla_v, //!< Instruction 'smmla' {ASIMD}.
+ kIdSmov_v, //!< Instruction 'smov' {ASIMD}.
+ kIdSmull_v, //!< Instruction 'smull' {ASIMD}.
+ kIdSmull2_v, //!< Instruction 'smull2' {ASIMD}.
+ kIdSqabs_v, //!< Instruction 'sqabs' {ASIMD}.
+ kIdSqadd_v, //!< Instruction 'sqadd' {ASIMD}.
+ kIdSqdmlal_v, //!< Instruction 'sqdmlal' {ASIMD}.
+ kIdSqdmlal2_v, //!< Instruction 'sqdmlal2' {ASIMD}.
+ kIdSqdmlsl_v, //!< Instruction 'sqdmlsl' {ASIMD}.
+ kIdSqdmlsl2_v, //!< Instruction 'sqdmlsl2' {ASIMD}.
+ kIdSqdmulh_v, //!< Instruction 'sqdmulh' {ASIMD}.
+ kIdSqdmull_v, //!< Instruction 'sqdmull' {ASIMD}.
+ kIdSqdmull2_v, //!< Instruction 'sqdmull2' {ASIMD}.
+ kIdSqneg_v, //!< Instruction 'sqneg' {ASIMD}.
+ kIdSqrdmlah_v, //!< Instruction 'sqrdmlah' {ASIMD}.
+ kIdSqrdmlsh_v, //!< Instruction 'sqrdmlsh' {ASIMD}.
+ kIdSqrdmulh_v, //!< Instruction 'sqrdmulh' {ASIMD}.
+ kIdSqrshl_v, //!< Instruction 'sqrshl' {ASIMD}.
+ kIdSqrshrn_v, //!< Instruction 'sqrshrn' {ASIMD}.
+ kIdSqrshrn2_v, //!< Instruction 'sqrshrn2' {ASIMD}.
+ kIdSqrshrun_v, //!< Instruction 'sqrshrun' {ASIMD}.
+ kIdSqrshrun2_v, //!< Instruction 'sqrshrun2' {ASIMD}.
+ kIdSqshl_v, //!< Instruction 'sqshl' {ASIMD}.
+ kIdSqshlu_v, //!< Instruction 'sqshlu' {ASIMD}.
+ kIdSqshrn_v, //!< Instruction 'sqshrn' {ASIMD}.
+ kIdSqshrn2_v, //!< Instruction 'sqshrn2' {ASIMD}.
+ kIdSqshrun_v, //!< Instruction 'sqshrun' {ASIMD}.
+ kIdSqshrun2_v, //!< Instruction 'sqshrun2' {ASIMD}.
+ kIdSqsub_v, //!< Instruction 'sqsub' {ASIMD}.
+ kIdSqxtn_v, //!< Instruction 'sqxtn' {ASIMD}.
+ kIdSqxtn2_v, //!< Instruction 'sqxtn2' {ASIMD}.
+ kIdSqxtun_v, //!< Instruction 'sqxtun' {ASIMD}.
+ kIdSqxtun2_v, //!< Instruction 'sqxtun2' {ASIMD}.
+ kIdSrhadd_v, //!< Instruction 'srhadd' {ASIMD}.
+ kIdSri_v, //!< Instruction 'sri' {ASIMD}.
+ kIdSrshl_v, //!< Instruction 'srshl' {ASIMD}.
+ kIdSrshr_v, //!< Instruction 'srshr' {ASIMD}.
+ kIdSrsra_v, //!< Instruction 'srsra' {ASIMD}.
+ kIdSshl_v, //!< Instruction 'sshl' {ASIMD}.
+ kIdSshll_v, //!< Instruction 'sshll' {ASIMD}.
+ kIdSshll2_v, //!< Instruction 'sshll2' {ASIMD}.
+ kIdSshr_v, //!< Instruction 'sshr' {ASIMD}.
+ kIdSsra_v, //!< Instruction 'ssra' {ASIMD}.
+ kIdSsubl_v, //!< Instruction 'ssubl' {ASIMD}.
+ kIdSsubl2_v, //!< Instruction 'ssubl2' {ASIMD}.
+ kIdSsubw_v, //!< Instruction 'ssubw' {ASIMD}.
+ kIdSsubw2_v, //!< Instruction 'ssubw2' {ASIMD}.
+ kIdSt1_v, //!< Instruction 'st1' {ASIMD}.
+ kIdSt2_v, //!< Instruction 'st2' {ASIMD}.
+ kIdSt3_v, //!< Instruction 'st3' {ASIMD}.
+ kIdSt4_v, //!< Instruction 'st4' {ASIMD}.
+ kIdStnp_v, //!< Instruction 'stnp' {ASIMD}.
+ kIdStp_v, //!< Instruction 'stp' {ASIMD}.
+ kIdStr_v, //!< Instruction 'str' {ASIMD}.
+ kIdStur_v, //!< Instruction 'stur' {ASIMD}.
+ kIdSub_v, //!< Instruction 'sub' {ASIMD}.
+ kIdSubhn_v, //!< Instruction 'subhn' {ASIMD}.
+ kIdSubhn2_v, //!< Instruction 'subhn2' {ASIMD}.
+ kIdSudot_v, //!< Instruction 'sudot' {ASIMD}.
+ kIdSuqadd_v, //!< Instruction 'suqadd' {ASIMD}.
+ kIdSxtl_v, //!< Instruction 'sxtl' {ASIMD}.
+ kIdSxtl2_v, //!< Instruction 'sxtl2' {ASIMD}.
+ kIdTbl_v, //!< Instruction 'tbl' {ASIMD}.
+ kIdTbx_v, //!< Instruction 'tbx' {ASIMD}.
+ kIdTrn1_v, //!< Instruction 'trn1' {ASIMD}.
+ kIdTrn2_v, //!< Instruction 'trn2' {ASIMD}.
+ kIdUaba_v, //!< Instruction 'uaba' {ASIMD}.
+ kIdUabal_v, //!< Instruction 'uabal' {ASIMD}.
+ kIdUabal2_v, //!< Instruction 'uabal2' {ASIMD}.
+ kIdUabd_v, //!< Instruction 'uabd' {ASIMD}.
+ kIdUabdl_v, //!< Instruction 'uabdl' {ASIMD}.
+ kIdUabdl2_v, //!< Instruction 'uabdl2' {ASIMD}.
+ kIdUadalp_v, //!< Instruction 'uadalp' {ASIMD}.
+ kIdUaddl_v, //!< Instruction 'uaddl' {ASIMD}.
+ kIdUaddl2_v, //!< Instruction 'uaddl2' {ASIMD}.
+ kIdUaddlp_v, //!< Instruction 'uaddlp' {ASIMD}.
+ kIdUaddlv_v, //!< Instruction 'uaddlv' {ASIMD}.
+ kIdUaddw_v, //!< Instruction 'uaddw' {ASIMD}.
+ kIdUaddw2_v, //!< Instruction 'uaddw2' {ASIMD}.
+ kIdUcvtf_v, //!< Instruction 'ucvtf' {ASIMD}.
+ kIdUdot_v, //!< Instruction 'udot' {ASIMD}.
+ kIdUhadd_v, //!< Instruction 'uhadd' {ASIMD}.
+ kIdUhsub_v, //!< Instruction 'uhsub' {ASIMD}.
+ kIdUmax_v, //!< Instruction 'umax' {ASIMD}.
+ kIdUmaxp_v, //!< Instruction 'umaxp' {ASIMD}.
+ kIdUmaxv_v, //!< Instruction 'umaxv' {ASIMD}.
+ kIdUmin_v, //!< Instruction 'umin' {ASIMD}.
+ kIdUminp_v, //!< Instruction 'uminp' {ASIMD}.
+ kIdUminv_v, //!< Instruction 'uminv' {ASIMD}.
+ kIdUmlal_v, //!< Instruction 'umlal' {ASIMD}.
+ kIdUmlal2_v, //!< Instruction 'umlal2' {ASIMD}.
+ kIdUmlsl_v, //!< Instruction 'umlsl' {ASIMD}.
+ kIdUmlsl2_v, //!< Instruction 'umlsl2' {ASIMD}.
+ kIdUmmla_v, //!< Instruction 'ummla' {ASIMD}.
+ kIdUmov_v, //!< Instruction 'umov' {ASIMD}.
+ kIdUmull_v, //!< Instruction 'umull' {ASIMD}.
+ kIdUmull2_v, //!< Instruction 'umull2' {ASIMD}.
+ kIdUqadd_v, //!< Instruction 'uqadd' {ASIMD}.
+ kIdUqrshl_v, //!< Instruction 'uqrshl' {ASIMD}.
+ kIdUqrshrn_v, //!< Instruction 'uqrshrn' {ASIMD}.
+ kIdUqrshrn2_v, //!< Instruction 'uqrshrn2' {ASIMD}.
+ kIdUqshl_v, //!< Instruction 'uqshl' {ASIMD}.
+ kIdUqshrn_v, //!< Instruction 'uqshrn' {ASIMD}.
+ kIdUqshrn2_v, //!< Instruction 'uqshrn2' {ASIMD}.
+ kIdUqsub_v, //!< Instruction 'uqsub' {ASIMD}.
+ kIdUqxtn_v, //!< Instruction 'uqxtn' {ASIMD}.
+ kIdUqxtn2_v, //!< Instruction 'uqxtn2' {ASIMD}.
+ kIdUrecpe_v, //!< Instruction 'urecpe' {ASIMD}.
+ kIdUrhadd_v, //!< Instruction 'urhadd' {ASIMD}.
+ kIdUrshl_v, //!< Instruction 'urshl' {ASIMD}.
+ kIdUrshr_v, //!< Instruction 'urshr' {ASIMD}.
+ kIdUrsqrte_v, //!< Instruction 'ursqrte' {ASIMD}.
+ kIdUrsra_v, //!< Instruction 'ursra' {ASIMD}.
+ kIdUsdot_v, //!< Instruction 'usdot' {ASIMD}.
+ kIdUshl_v, //!< Instruction 'ushl' {ASIMD}.
+ kIdUshll_v, //!< Instruction 'ushll' {ASIMD}.
+ kIdUshll2_v, //!< Instruction 'ushll2' {ASIMD}.
+ kIdUshr_v, //!< Instruction 'ushr' {ASIMD}.
+ kIdUsmmla_v, //!< Instruction 'usmmla' {ASIMD}.
+ kIdUsqadd_v, //!< Instruction 'usqadd' {ASIMD}.
+ kIdUsra_v, //!< Instruction 'usra' {ASIMD}.
+ kIdUsubl_v, //!< Instruction 'usubl' {ASIMD}.
+ kIdUsubl2_v, //!< Instruction 'usubl2' {ASIMD}.
+ kIdUsubw_v, //!< Instruction 'usubw' {ASIMD}.
+ kIdUsubw2_v, //!< Instruction 'usubw2' {ASIMD}.
+ kIdUxtl_v, //!< Instruction 'uxtl' {ASIMD}.
+ kIdUxtl2_v, //!< Instruction 'uxtl2' {ASIMD}.
+ kIdUzp1_v, //!< Instruction 'uzp1' {ASIMD}.
+ kIdUzp2_v, //!< Instruction 'uzp2' {ASIMD}.
+ kIdXar_v, //!< Instruction 'xar' {ASIMD}.
+ kIdXtn_v, //!< Instruction 'xtn' {ASIMD}.
+ kIdXtn2_v, //!< Instruction 'xtn2' {ASIMD}.
+ kIdZip1_v, //!< Instruction 'zip1' {ASIMD}.
+ kIdZip2_v, //!< Instruction 'zip2' {ASIMD}.
+ _kIdCount
+ // ${InstId:End}
+ };
+
+ //! Tests whether the `instId` is defined (counts also Inst::kIdNone, which must be zero).
+ static inline bool isDefinedId(InstId instId) noexcept { return (instId & uint32_t(InstIdParts::kRealId)) < _kIdCount; }
+};
+
+namespace Predicate {
+
+//! Address translate options (AT).
+namespace AT {
+ static inline constexpr uint32_t encode(uint32_t op1, uint32_t cRn, uint32_t cRm, uint32_t op2) noexcept {
+ return (op1 << 11) | (cRn << 7) | (cRm << 3) | (op2 << 0);
+ }
+
+ enum Value : uint32_t {
+ kS1E1R = encode(0b000, 0b0111, 0b1000, 0b000),
+ kS1E2R = encode(0b100, 0b0111, 0b1000, 0b000),
+ kS1E3R = encode(0b110, 0b0111, 0b1000, 0b000),
+ kS1E1W = encode(0b000, 0b0111, 0b1000, 0b001),
+ kS1E2W = encode(0b100, 0b0111, 0b1000, 0b001),
+ kS1E3W = encode(0b110, 0b0111, 0b1000, 0b001),
+ kS1E0R = encode(0b000, 0b0111, 0b1000, 0b010),
+ kS1E0W = encode(0b000, 0b0111, 0b1000, 0b011),
+ kS12E1R = encode(0b100, 0b0111, 0b1000, 0b100),
+ kS12E1W = encode(0b100, 0b0111, 0b1000, 0b101),
+ kS12E0R = encode(0b100, 0b0111, 0b1000, 0b110),
+ kS12E0W = encode(0b100, 0b0111, 0b1000, 0b111),
+ kS1E1RP = encode(0b000, 0b0111, 0b1001, 0b000),
+ kS1E1WP = encode(0b000, 0b0111, 0b1001, 0b001)
+ };
+}
+
+//! Data barrier options (DMB/DSB).
+namespace DB {
+ //! Data barrier immediate values.
+ enum Value : uint32_t {
+ //! Waits only for loads to complete, and only applies to the outer shareable domain.
+ kOSHLD = 0x01u,
+ //! Waits only for stores to complete, and only applies to the outer shareable domain.
+ kOSHST = 0x02u,
+ //! Only applies to the outer shareable domain.
+ kOSH = 0x03u,
+
+ //! Waits only for loads to complete and only applies out to the point of unification.
+ kNSHLD = 0x05u,
+ //! Waits only for stores to complete and only applies out to the point of unification.
+ kNSHST = 0x06u,
+ //! Only applies out to the point of unification.
+ kNSH = 0x07u,
+
+ //! Waits only for loads to complete, and only applies to the inner shareable domain.
+ kISHLD = 0x09u,
+ //! Waits only for stores to complete, and only applies to the inner shareable domain.
+ kISHST = 0x0Au,
+ //! Only applies to the inner shareable domain.
+ kISH = 0x0Bu,
+
+ //! Waits only for loads to complete.
+ kLD = 0x0Du,
+ //! Waits only for stores to complete.
+ kST = 0x0Eu,
+ //! Full system memory barrier operation.
+ kSY = 0x0Fu
+ };
+}
+
+//! Data cache maintenance options.
+namespace DC {
+ static inline constexpr uint32_t encode(uint32_t op1, uint32_t cRn, uint32_t cRm, uint32_t op2) noexcept {
+ return (op1 << 11) | (cRn << 7) | (cRm << 3) | (op2 << 0);
+ }
+
+ //! Data cache maintenance immediate values.
+ enum Value : uint32_t {
+ kZVA = encode(0b011, 0b0111, 0b0100, 0b001),
+ kIVAC = encode(0b000, 0b0111, 0b0110, 0b001),
+ kISW = encode(0b000, 0b0111, 0b0110, 0b010),
+ kCVAC = encode(0b011, 0b0111, 0b1010, 0b001),
+ kCSW = encode(0b000, 0b0111, 0b1010, 0b010),
+ kCVAU = encode(0b011, 0b0111, 0b1011, 0b001),
+ kCIVAC = encode(0b011, 0b0111, 0b1110, 0b001),
+ kCISW = encode(0b000, 0b0111, 0b1110, 0b010),
+ kCVAP = encode(0b011, 0b0111, 0b1100, 0b001),
+ kCVADP = encode(0b011, 0b0111, 0b1101, 0b001),
+ kIGVAC = encode(0b000, 0b0111, 0b0110, 0b011),
+ kIGSW = encode(0b000, 0b0111, 0b0110, 0b100),
+ kCGSW = encode(0b000, 0b0111, 0b1010, 0b100),
+ kCIGSW = encode(0b000, 0b0111, 0b1110, 0b100),
+ kCGVAC = encode(0b011, 0b0111, 0b1010, 0b011),
+ kCGVAP = encode(0b011, 0b0111, 0b1100, 0b011),
+ kCGVADP = encode(0b011, 0b0111, 0b1101, 0b011),
+ kCIGVAC = encode(0b011, 0b0111, 0b1110, 0b011),
+ kGVA = encode(0b011, 0b0111, 0b0100, 0b011),
+ kIGDVAC = encode(0b000, 0b0111, 0b0110, 0b101),
+ kIGDSW = encode(0b000, 0b0111, 0b0110, 0b110),
+ kCGDSW = encode(0b000, 0b0111, 0b1010, 0b110),
+ kCIGDSW = encode(0b000, 0b0111, 0b1110, 0b110),
+ kCGDVAC = encode(0b011, 0b0111, 0b1010, 0b101),
+ kCGDVAP = encode(0b011, 0b0111, 0b1100, 0b101),
+ kCGDVADP = encode(0b011, 0b0111, 0b1101, 0b101),
+ kCIGDVAC = encode(0b011, 0b0111, 0b1110, 0b101),
+ kGZVA = encode(0b011, 0b0111, 0b0100, 0b100)
+ };
+}
+
+//! Instruction cache maintenance options.
+namespace IC {
+ static inline constexpr uint32_t encode(uint32_t op1, uint32_t cRn, uint32_t cRm, uint32_t op2) noexcept {
+ return (op1 << 11) | (cRn << 7) | (cRm << 3) | (op2 << 0);
+ }
+
+ //! Instruction cache maintenance immediate values.
+ enum Value : uint32_t {
+ kIALLUIS = encode(0b000, 0b0111, 0b0001, 0b000),
+ kIALLU = encode(0b000, 0b0111, 0b0101, 0b000),
+ kIVAU = encode(0b011, 0b0111, 0b0101, 0b001)
+ };
+}
+
+//! Instruction-fetch barrier options.
+namespace ISB {
+ //! Instruction-fetch barrier immediate values.
+ enum Value : uint32_t {
+ kSY = 0xF
+ };
+}
+
+//! Prefetch options.
+namespace PRFOp {
+ //! Prefetch immediate values.
+ enum Value : uint32_t {
+ kPLDL1KEEP = 0x00,
+ kPLDL1STRM = 0x01,
+ kPLDL2KEEP = 0x02,
+ kPLDL2STRM = 0x03,
+ kPLDL3KEEP = 0x04,
+ kPLDL3STRM = 0x05,
+ kPLIL1KEEP = 0x08,
+ kPLIL1STRM = 0x09,
+ kPLIL2KEEP = 0x0A,
+ kPLIL2STRM = 0x0B,
+ kPLIL3KEEP = 0x0C,
+ kPLIL3STRM = 0x0D,
+ kPSTL1KEEP = 0x10,
+ kPSTL1STRM = 0x11,
+ kPSTL2KEEP = 0x12,
+ kPSTL2STRM = 0x13,
+ kPSTL3KEEP = 0x14,
+ kPSTL3STRM = 0x15
+ };
+}
+
+//! PSB instruction options.
+namespace PSB {
+ //! PSB immediate values.
+ enum Value : uint32_t {
+ kCSYNC = 0x11u
+ };
+}
+
+namespace TLBI {
+ static inline constexpr uint32_t encode(uint32_t op1, uint32_t cRn, uint32_t cRm, uint32_t op2) noexcept {
+ return (op1 << 11) | (cRn << 7) | (cRm << 3) | (op2 << 0);
+ }
+
+ enum Value : uint32_t {
+ kIPAS2E1IS = encode(0b100, 0b1000, 0b0000, 0b001),
+ kIPAS2LE1IS = encode(0b100, 0b1000, 0b0000, 0b101),
+ kVMALLE1IS = encode(0b000, 0b1000, 0b0011, 0b000),
+ kALLE2IS = encode(0b100, 0b1000, 0b0011, 0b000),
+ kALLE3IS = encode(0b110, 0b1000, 0b0011, 0b000),
+ kVAE1IS = encode(0b000, 0b1000, 0b0011, 0b001),
+ kVAE2IS = encode(0b100, 0b1000, 0b0011, 0b001),
+ kVAE3IS = encode(0b110, 0b1000, 0b0011, 0b001),
+ kASIDE1IS = encode(0b000, 0b1000, 0b0011, 0b010),
+ kVAAE1IS = encode(0b000, 0b1000, 0b0011, 0b011),
+ kALLE1IS = encode(0b100, 0b1000, 0b0011, 0b100),
+ kVALE1IS = encode(0b000, 0b1000, 0b0011, 0b101),
+ kVALE2IS = encode(0b100, 0b1000, 0b0011, 0b101),
+ kVALE3IS = encode(0b110, 0b1000, 0b0011, 0b101),
+ kVMALLS12E1IS = encode(0b100, 0b1000, 0b0011, 0b110),
+ kVAALE1IS = encode(0b000, 0b1000, 0b0011, 0b111),
+ kIPAS2E1 = encode(0b100, 0b1000, 0b0100, 0b001),
+ kIPAS2LE1 = encode(0b100, 0b1000, 0b0100, 0b101),
+ kVMALLE1 = encode(0b000, 0b1000, 0b0111, 0b000),
+ kALLE2 = encode(0b100, 0b1000, 0b0111, 0b000),
+ kALLE3 = encode(0b110, 0b1000, 0b0111, 0b000),
+ kVAE1 = encode(0b000, 0b1000, 0b0111, 0b001),
+ kVAE2 = encode(0b100, 0b1000, 0b0111, 0b001),
+ kVAE3 = encode(0b110, 0b1000, 0b0111, 0b001),
+ kASIDE1 = encode(0b000, 0b1000, 0b0111, 0b010),
+ kVAAE1 = encode(0b000, 0b1000, 0b0111, 0b011),
+ kALLE1 = encode(0b100, 0b1000, 0b0111, 0b100),
+ kVALE1 = encode(0b000, 0b1000, 0b0111, 0b101),
+ kVALE2 = encode(0b100, 0b1000, 0b0111, 0b101),
+ kVALE3 = encode(0b110, 0b1000, 0b0111, 0b101),
+ kVMALLS12E1 = encode(0b100, 0b1000, 0b0111, 0b110),
+ kVAALE1 = encode(0b000, 0b1000, 0b0111, 0b111),
+
+ kVMALLE1OS = encode(0b000, 0b1000, 0b0001, 0b000),
+ kVAE1OS = encode(0b000, 0b1000, 0b0001, 0b001),
+ kASIDE1OS = encode(0b000, 0b1000, 0b0001, 0b010),
+ kVAAE1OS = encode(0b000, 0b1000, 0b0001, 0b011),
+ kVALE1OS = encode(0b000, 0b1000, 0b0001, 0b101),
+ kVAALE1OS = encode(0b000, 0b1000, 0b0001, 0b111),
+ kIPAS2E1OS = encode(0b100, 0b1000, 0b0100, 0b000),
+ kIPAS2LE1OS = encode(0b100, 0b1000, 0b0100, 0b100),
+ kVAE2OS = encode(0b100, 0b1000, 0b0001, 0b001),
+ kVALE2OS = encode(0b100, 0b1000, 0b0001, 0b101),
+ kVMALLS12E1OS = encode(0b100, 0b1000, 0b0001, 0b110),
+ kVAE3OS = encode(0b110, 0b1000, 0b0001, 0b001),
+ kVALE3OS = encode(0b110, 0b1000, 0b0001, 0b101),
+ kALLE2OS = encode(0b100, 0b1000, 0b0001, 0b000),
+ kALLE1OS = encode(0b100, 0b1000, 0b0001, 0b100),
+ kALLE3OS = encode(0b110, 0b1000, 0b0001, 0b000),
+
+ kRVAE1 = encode(0b000, 0b1000, 0b0110, 0b001),
+ kRVAAE1 = encode(0b000, 0b1000, 0b0110, 0b011),
+ kRVALE1 = encode(0b000, 0b1000, 0b0110, 0b101),
+ kRVAALE1 = encode(0b000, 0b1000, 0b0110, 0b111),
+ kRVAE1IS = encode(0b000, 0b1000, 0b0010, 0b001),
+ kRVAAE1IS = encode(0b000, 0b1000, 0b0010, 0b011),
+ kRVALE1IS = encode(0b000, 0b1000, 0b0010, 0b101),
+ kRVAALE1IS = encode(0b000, 0b1000, 0b0010, 0b111),
+ kRVAE1OS = encode(0b000, 0b1000, 0b0101, 0b001),
+ kRVAAE1OS = encode(0b000, 0b1000, 0b0101, 0b011),
+ kRVALE1OS = encode(0b000, 0b1000, 0b0101, 0b101),
+ kRVAALE1OS = encode(0b000, 0b1000, 0b0101, 0b111),
+ kRIPAS2E1IS = encode(0b100, 0b1000, 0b0000, 0b010),
+ kRIPAS2LE1IS = encode(0b100, 0b1000, 0b0000, 0b110),
+ kRIPAS2E1 = encode(0b100, 0b1000, 0b0100, 0b010),
+ kRIPAS2LE1 = encode(0b100, 0b1000, 0b0100, 0b110),
+ kRIPAS2E1OS = encode(0b100, 0b1000, 0b0100, 0b011),
+ kRIPAS2LE1OS = encode(0b100, 0b1000, 0b0100, 0b111),
+ kRVAE2 = encode(0b100, 0b1000, 0b0110, 0b001),
+ kRVALE2 = encode(0b100, 0b1000, 0b0110, 0b101),
+ kRVAE2IS = encode(0b100, 0b1000, 0b0010, 0b001),
+ kRVALE2IS = encode(0b100, 0b1000, 0b0010, 0b101),
+ kRVAE2OS = encode(0b100, 0b1000, 0b0101, 0b001),
+ kRVALE2OS = encode(0b100, 0b1000, 0b0101, 0b101),
+ kRVAE3 = encode(0b110, 0b1000, 0b0110, 0b001),
+ kRVALE3 = encode(0b110, 0b1000, 0b0110, 0b101),
+ kRVAE3IS = encode(0b110, 0b1000, 0b0010, 0b001),
+ kRVALE3IS = encode(0b110, 0b1000, 0b0010, 0b101),
+ kRVAE3OS = encode(0b110, 0b1000, 0b0101, 0b001),
+ kRVALE3OS = encode(0b110, 0b1000, 0b0101, 0b101),
+ };
+}
+
+//! Trace synchronization barrier options.
+namespace TSB {
+ //! Trace synchronization immediate values.
+ enum Value : uint32_t {
+ kCSYNC = 0
+ };
+}
+
+//! Processor state access through MSR.
+namespace PState {
+ //! Encodes a pstate from `op0` and `op1`.
+ static inline constexpr uint32_t encode(uint32_t op0, uint32_t op1) noexcept {
+ return (op0 << 3) | (op1 << 0);
+ }
+
+ //! Processor state access immediates.
+ enum Value : uint32_t {
+ kSPSel = encode(0b000, 0b101),
+ kDAIFSet = encode(0b011, 0b110),
+ kDAIFClr = encode(0b011, 0b111),
+ kPAN = encode(0b000, 0b100),
+ kUAO = encode(0b000, 0b011),
+ kDIT = encode(0b011, 0b010),
+ kSSBS = encode(0b011, 0b001),
+ kTCO = encode(0b011, 0b100)
+ };
+};
+
+//! System register identifiers and utilities (MSR/MRS).
+namespace SysReg {
+ //! System register fields.
+ struct Fields {
+ uint8_t op0;
+ uint8_t op1;
+ uint8_t cRn;
+ uint8_t cRm;
+ uint8_t op2;
+ };
+
+ //! Encodes a system register from `op0`, `op1`, `cRn`, `cRm`, and `op2` fields.
+ static inline constexpr uint32_t encode(uint32_t op0, uint32_t op1, uint32_t cRn, uint32_t cRm, uint32_t op2) noexcept {
+ return (op0 << 14) | (op1 << 11) | (cRn << 7) | (cRm << 3) | (op2 << 0);
+ }
+
+ //! Encodes a system register from `fields`.
+ static inline constexpr uint32_t encode(const Fields& fields) noexcept {
+ return encode(fields.op0, fields.op1, fields.cRn, fields.cRm, fields.op2);
+ }
+
+ //! Decodes a system register to \ref Fields.
+ static inline constexpr Fields decode(uint32_t id) noexcept {
+ return Fields {
+ uint8_t((id >> 14) & 0x3u),
+ uint8_t((id >> 11) & 0x7u),
+ uint8_t((id >> 7) & 0xFu),
+ uint8_t((id >> 3) & 0xFu),
+ uint8_t((id >> 0) & 0x7u)
+ };
+ }
+
+ //! System register identifiers.
+ enum Id : uint32_t {
+ kACTLR_EL1 = encode(0b11, 0b000, 0b0001, 0b0000, 0b001), // RW
+ kACTLR_EL2 = encode(0b11, 0b100, 0b0001, 0b0000, 0b001), // RW
+ kACTLR_EL3 = encode(0b11, 0b110, 0b0001, 0b0000, 0b001), // RW
+ kAFSR0_EL1 = encode(0b11, 0b000, 0b0101, 0b0001, 0b000), // RW
+ kAFSR0_EL12 = encode(0b11, 0b101, 0b0101, 0b0001, 0b000), // RW
+ kAFSR0_EL2 = encode(0b11, 0b100, 0b0101, 0b0001, 0b000), // RW
+ kAFSR0_EL3 = encode(0b11, 0b110, 0b0101, 0b0001, 0b000), // RW
+ kAFSR1_EL1 = encode(0b11, 0b000, 0b0101, 0b0001, 0b001), // RW
+ kAFSR1_EL12 = encode(0b11, 0b101, 0b0101, 0b0001, 0b001), // RW
+ kAFSR1_EL2 = encode(0b11, 0b100, 0b0101, 0b0001, 0b001), // RW
+ kAFSR1_EL3 = encode(0b11, 0b110, 0b0101, 0b0001, 0b001), // RW
+ kAIDR_EL1 = encode(0b11, 0b001, 0b0000, 0b0000, 0b111), // RO
+ kAMAIR_EL1 = encode(0b11, 0b000, 0b1010, 0b0011, 0b000), // RW
+ kAMAIR_EL12 = encode(0b11, 0b101, 0b1010, 0b0011, 0b000), // RW
+ kAMAIR_EL2 = encode(0b11, 0b100, 0b1010, 0b0011, 0b000), // RW
+ kAMAIR_EL3 = encode(0b11, 0b110, 0b1010, 0b0011, 0b000), // RW
+ kAMCFGR_EL0 = encode(0b11, 0b011, 0b1101, 0b0010, 0b001), // RO
+ kAMCGCR_EL0 = encode(0b11, 0b011, 0b1101, 0b0010, 0b010), // RO
+ kAMCNTENCLR0_EL0 = encode(0b11, 0b011, 0b1101, 0b0010, 0b100), // RW
+ kAMCNTENCLR1_EL0 = encode(0b11, 0b011, 0b1101, 0b0011, 0b000), // RW
+ kAMCNTENSET0_EL0 = encode(0b11, 0b011, 0b1101, 0b0010, 0b101), // RW
+ kAMCNTENSET1_EL0 = encode(0b11, 0b011, 0b1101, 0b0011, 0b001), // RW
+ kAMCR_EL0 = encode(0b11, 0b011, 0b1101, 0b0010, 0b000), // RW
+ kAMEVCNTR00_EL0 = encode(0b11, 0b011, 0b1101, 0b0100, 0b000), // RW
+ kAMEVCNTR01_EL0 = encode(0b11, 0b011, 0b1101, 0b0100, 0b001), // RW
+ kAMEVCNTR02_EL0 = encode(0b11, 0b011, 0b1101, 0b0100, 0b010), // RW
+ kAMEVCNTR03_EL0 = encode(0b11, 0b011, 0b1101, 0b0100, 0b011), // RW
+ kAMEVCNTR10_EL0 = encode(0b11, 0b011, 0b1101, 0b1100, 0b000), // RW
+ kAMEVCNTR110_EL0 = encode(0b11, 0b011, 0b1101, 0b1101, 0b010), // RW
+ kAMEVCNTR111_EL0 = encode(0b11, 0b011, 0b1101, 0b1101, 0b011), // RW
+ kAMEVCNTR112_EL0 = encode(0b11, 0b011, 0b1101, 0b1101, 0b100), // RW
+ kAMEVCNTR113_EL0 = encode(0b11, 0b011, 0b1101, 0b1101, 0b101), // RW
+ kAMEVCNTR114_EL0 = encode(0b11, 0b011, 0b1101, 0b1101, 0b110), // RW
+ kAMEVCNTR115_EL0 = encode(0b11, 0b011, 0b1101, 0b1101, 0b111), // RW
+ kAMEVCNTR11_EL0 = encode(0b11, 0b011, 0b1101, 0b1100, 0b001), // RW
+ kAMEVCNTR12_EL0 = encode(0b11, 0b011, 0b1101, 0b1100, 0b010), // RW
+ kAMEVCNTR13_EL0 = encode(0b11, 0b011, 0b1101, 0b1100, 0b011), // RW
+ kAMEVCNTR14_EL0 = encode(0b11, 0b011, 0b1101, 0b1100, 0b100), // RW
+ kAMEVCNTR15_EL0 = encode(0b11, 0b011, 0b1101, 0b1100, 0b101), // RW
+ kAMEVCNTR16_EL0 = encode(0b11, 0b011, 0b1101, 0b1100, 0b110), // RW
+ kAMEVCNTR17_EL0 = encode(0b11, 0b011, 0b1101, 0b1100, 0b111), // RW
+ kAMEVCNTR18_EL0 = encode(0b11, 0b011, 0b1101, 0b1101, 0b000), // RW
+ kAMEVCNTR19_EL0 = encode(0b11, 0b011, 0b1101, 0b1101, 0b001), // RW
+ kAMEVTYPER00_EL0 = encode(0b11, 0b011, 0b1101, 0b0110, 0b000), // RO
+ kAMEVTYPER01_EL0 = encode(0b11, 0b011, 0b1101, 0b0110, 0b001), // RO
+ kAMEVTYPER02_EL0 = encode(0b11, 0b011, 0b1101, 0b0110, 0b010), // RO
+ kAMEVTYPER03_EL0 = encode(0b11, 0b011, 0b1101, 0b0110, 0b011), // RO
+ kAMEVTYPER10_EL0 = encode(0b11, 0b011, 0b1101, 0b1110, 0b000), // RW
+ kAMEVTYPER110_EL0 = encode(0b11, 0b011, 0b1101, 0b1111, 0b010), // RW
+ kAMEVTYPER111_EL0 = encode(0b11, 0b011, 0b1101, 0b1111, 0b011), // RW
+ kAMEVTYPER112_EL0 = encode(0b11, 0b011, 0b1101, 0b1111, 0b100), // RW
+ kAMEVTYPER113_EL0 = encode(0b11, 0b011, 0b1101, 0b1111, 0b101), // RW
+ kAMEVTYPER114_EL0 = encode(0b11, 0b011, 0b1101, 0b1111, 0b110), // RW
+ kAMEVTYPER115_EL0 = encode(0b11, 0b011, 0b1101, 0b1111, 0b111), // RW
+ kAMEVTYPER11_EL0 = encode(0b11, 0b011, 0b1101, 0b1110, 0b001), // RW
+ kAMEVTYPER12_EL0 = encode(0b11, 0b011, 0b1101, 0b1110, 0b010), // RW
+ kAMEVTYPER13_EL0 = encode(0b11, 0b011, 0b1101, 0b1110, 0b011), // RW
+ kAMEVTYPER14_EL0 = encode(0b11, 0b011, 0b1101, 0b1110, 0b100), // RW
+ kAMEVTYPER15_EL0 = encode(0b11, 0b011, 0b1101, 0b1110, 0b101), // RW
+ kAMEVTYPER16_EL0 = encode(0b11, 0b011, 0b1101, 0b1110, 0b110), // RW
+ kAMEVTYPER17_EL0 = encode(0b11, 0b011, 0b1101, 0b1110, 0b111), // RW
+ kAMEVTYPER18_EL0 = encode(0b11, 0b011, 0b1101, 0b1111, 0b000), // RW
+ kAMEVTYPER19_EL0 = encode(0b11, 0b011, 0b1101, 0b1111, 0b001), // RW
+ kAMUSERENR_EL0 = encode(0b11, 0b011, 0b1101, 0b0010, 0b011), // RW
+ kAPDAKeyHi_EL1 = encode(0b11, 0b000, 0b0010, 0b0010, 0b001), // RW
+ kAPDAKeyLo_EL1 = encode(0b11, 0b000, 0b0010, 0b0010, 0b000), // RW
+ kAPDBKeyHi_EL1 = encode(0b11, 0b000, 0b0010, 0b0010, 0b011), // RW
+ kAPDBKeyLo_EL1 = encode(0b11, 0b000, 0b0010, 0b0010, 0b010), // RW
+ kAPGAKeyHi_EL1 = encode(0b11, 0b000, 0b0010, 0b0011, 0b001), // RW
+ kAPGAKeyLo_EL1 = encode(0b11, 0b000, 0b0010, 0b0011, 0b000), // RW
+ kAPIAKeyHi_EL1 = encode(0b11, 0b000, 0b0010, 0b0001, 0b001), // RW
+ kAPIAKeyLo_EL1 = encode(0b11, 0b000, 0b0010, 0b0001, 0b000), // RW
+ kAPIBKeyHi_EL1 = encode(0b11, 0b000, 0b0010, 0b0001, 0b011), // RW
+ kAPIBKeyLo_EL1 = encode(0b11, 0b000, 0b0010, 0b0001, 0b010), // RW
+ kCCSIDR2_EL1 = encode(0b11, 0b001, 0b0000, 0b0000, 0b010), // RO
+ kCCSIDR_EL1 = encode(0b11, 0b001, 0b0000, 0b0000, 0b000), // RO
+ kCLIDR_EL1 = encode(0b11, 0b001, 0b0000, 0b0000, 0b001), // RO
+ kCNTFRQ_EL0 = encode(0b11, 0b011, 0b1110, 0b0000, 0b000), // RW
+ kCNTHCTL_EL2 = encode(0b11, 0b100, 0b1110, 0b0001, 0b000), // RW
+ kCNTHPS_CTL_EL2 = encode(0b11, 0b100, 0b1110, 0b0101, 0b001), // RW
+ kCNTHPS_CVAL_EL2 = encode(0b11, 0b100, 0b1110, 0b0101, 0b010), // RW
+ kCNTHPS_TVAL_EL2 = encode(0b11, 0b100, 0b1110, 0b0101, 0b000), // RW
+ kCNTHP_CTL_EL2 = encode(0b11, 0b100, 0b1110, 0b0010, 0b001), // RW
+ kCNTHP_CVAL_EL2 = encode(0b11, 0b100, 0b1110, 0b0010, 0b010), // RW
+ kCNTHP_TVAL_EL2 = encode(0b11, 0b100, 0b1110, 0b0010, 0b000), // RW
+ kCNTHVS_CTL_EL2 = encode(0b11, 0b100, 0b1110, 0b0100, 0b001), // RW
+ kCNTHVS_CVAL_EL2 = encode(0b11, 0b100, 0b1110, 0b0100, 0b010), // RW
+ kCNTHVS_TVAL_EL2 = encode(0b11, 0b100, 0b1110, 0b0100, 0b000), // RW
+ kCNTHV_CTL_EL2 = encode(0b11, 0b100, 0b1110, 0b0011, 0b001), // RW
+ kCNTHV_CVAL_EL2 = encode(0b11, 0b100, 0b1110, 0b0011, 0b010), // RW
+ kCNTHV_TVAL_EL2 = encode(0b11, 0b100, 0b1110, 0b0011, 0b000), // RW
+ kCNTISCALE_EL2 = encode(0b11, 0b100, 0b1110, 0b0000, 0b101), // RW
+ kCNTKCTL_EL1 = encode(0b11, 0b000, 0b1110, 0b0001, 0b000), // RW
+ kCNTKCTL_EL12 = encode(0b11, 0b101, 0b1110, 0b0001, 0b000), // RW
+ kCNTPCTSS_EL0 = encode(0b11, 0b011, 0b1110, 0b0000, 0b101), // RW
+ kCNTPCT_EL0 = encode(0b11, 0b011, 0b1110, 0b0000, 0b001), // RO
+ kCNTPOFF_EL2 = encode(0b11, 0b100, 0b1110, 0b0000, 0b110), // RW
+ kCNTPS_CTL_EL1 = encode(0b11, 0b111, 0b1110, 0b0010, 0b001), // RW
+ kCNTPS_CVAL_EL1 = encode(0b11, 0b111, 0b1110, 0b0010, 0b010), // RW
+ kCNTPS_TVAL_EL1 = encode(0b11, 0b111, 0b1110, 0b0010, 0b000), // RW
+ kCNTP_CTL_EL0 = encode(0b11, 0b011, 0b1110, 0b0010, 0b001), // RW
+ kCNTP_CTL_EL02 = encode(0b11, 0b101, 0b1110, 0b0010, 0b001), // RW
+ kCNTP_CVAL_EL0 = encode(0b11, 0b011, 0b1110, 0b0010, 0b010), // RW
+ kCNTP_CVAL_EL02 = encode(0b11, 0b101, 0b1110, 0b0010, 0b010), // RW
+ kCNTP_TVAL_EL0 = encode(0b11, 0b011, 0b1110, 0b0010, 0b000), // RW
+ kCNTP_TVAL_EL02 = encode(0b11, 0b101, 0b1110, 0b0010, 0b000), // RW
+ kCNTSCALE_EL2 = encode(0b11, 0b100, 0b1110, 0b0000, 0b100), // RW
+ kCNTVCTSS_EL0 = encode(0b11, 0b011, 0b1110, 0b0000, 0b110), // RW
+ kCNTVCT_EL0 = encode(0b11, 0b011, 0b1110, 0b0000, 0b010), // RO
+ kCNTVFRQ_EL2 = encode(0b11, 0b100, 0b1110, 0b0000, 0b111), // RW
+ kCNTVOFF_EL2 = encode(0b11, 0b100, 0b1110, 0b0000, 0b011), // RW
+ kCNTV_CTL_EL0 = encode(0b11, 0b011, 0b1110, 0b0011, 0b001), // RW
+ kCNTV_CTL_EL02 = encode(0b11, 0b101, 0b1110, 0b0011, 0b001), // RW
+ kCNTV_CVAL_EL0 = encode(0b11, 0b011, 0b1110, 0b0011, 0b010), // RW
+ kCNTV_CVAL_EL02 = encode(0b11, 0b101, 0b1110, 0b0011, 0b010), // RW
+ kCNTV_TVAL_EL0 = encode(0b11, 0b011, 0b1110, 0b0011, 0b000), // RW
+ kCNTV_TVAL_EL02 = encode(0b11, 0b101, 0b1110, 0b0011, 0b000), // RW
+ kCONTEXTIDR_EL1 = encode(0b11, 0b000, 0b1101, 0b0000, 0b001), // RW
+ kCONTEXTIDR_EL12 = encode(0b11, 0b101, 0b1101, 0b0000, 0b001), // RW
+ kCONTEXTIDR_EL2 = encode(0b11, 0b100, 0b1101, 0b0000, 0b001), // RW
+ kCPACR_EL1 = encode(0b11, 0b000, 0b0001, 0b0000, 0b010), // RW
+ kCPACR_EL12 = encode(0b11, 0b101, 0b0001, 0b0000, 0b010), // RW
+ kCPM_IOACC_CTL_EL3 = encode(0b11, 0b111, 0b1111, 0b0010, 0b000), // RW
+ kCPTR_EL2 = encode(0b11, 0b100, 0b0001, 0b0001, 0b010), // RW
+ kCPTR_EL3 = encode(0b11, 0b110, 0b0001, 0b0001, 0b010), // RW
+ kCSSELR_EL1 = encode(0b11, 0b010, 0b0000, 0b0000, 0b000), // RW
+ kCTR_EL0 = encode(0b11, 0b011, 0b0000, 0b0000, 0b001), // RO
+ kCurrentEL = encode(0b11, 0b000, 0b0100, 0b0010, 0b010), // RO
+ kDACR32_EL2 = encode(0b11, 0b100, 0b0011, 0b0000, 0b000), // RW
+ kDAIF = encode(0b11, 0b011, 0b0100, 0b0010, 0b001), // RW
+ kDBGAUTHSTATUS_EL1 = encode(0b10, 0b000, 0b0111, 0b1110, 0b110), // RO
+ kDBGBCR0_EL1 = encode(0b10, 0b000, 0b0000, 0b0000, 0b101), // RW
+ kDBGBCR10_EL1 = encode(0b10, 0b000, 0b0000, 0b1010, 0b101), // RW
+ kDBGBCR11_EL1 = encode(0b10, 0b000, 0b0000, 0b1011, 0b101), // RW
+ kDBGBCR12_EL1 = encode(0b10, 0b000, 0b0000, 0b1100, 0b101), // RW
+ kDBGBCR13_EL1 = encode(0b10, 0b000, 0b0000, 0b1101, 0b101), // RW
+ kDBGBCR14_EL1 = encode(0b10, 0b000, 0b0000, 0b1110, 0b101), // RW
+ kDBGBCR15_EL1 = encode(0b10, 0b000, 0b0000, 0b1111, 0b101), // RW
+ kDBGBCR1_EL1 = encode(0b10, 0b000, 0b0000, 0b0001, 0b101), // RW
+ kDBGBCR2_EL1 = encode(0b10, 0b000, 0b0000, 0b0010, 0b101), // RW
+ kDBGBCR3_EL1 = encode(0b10, 0b000, 0b0000, 0b0011, 0b101), // RW
+ kDBGBCR4_EL1 = encode(0b10, 0b000, 0b0000, 0b0100, 0b101), // RW
+ kDBGBCR5_EL1 = encode(0b10, 0b000, 0b0000, 0b0101, 0b101), // RW
+ kDBGBCR6_EL1 = encode(0b10, 0b000, 0b0000, 0b0110, 0b101), // RW
+ kDBGBCR7_EL1 = encode(0b10, 0b000, 0b0000, 0b0111, 0b101), // RW
+ kDBGBCR8_EL1 = encode(0b10, 0b000, 0b0000, 0b1000, 0b101), // RW
+ kDBGBCR9_EL1 = encode(0b10, 0b000, 0b0000, 0b1001, 0b101), // RW
+ kDBGBVR0_EL1 = encode(0b10, 0b000, 0b0000, 0b0000, 0b100), // RW
+ kDBGBVR10_EL1 = encode(0b10, 0b000, 0b0000, 0b1010, 0b100), // RW
+ kDBGBVR11_EL1 = encode(0b10, 0b000, 0b0000, 0b1011, 0b100), // RW
+ kDBGBVR12_EL1 = encode(0b10, 0b000, 0b0000, 0b1100, 0b100), // RW
+ kDBGBVR13_EL1 = encode(0b10, 0b000, 0b0000, 0b1101, 0b100), // RW
+ kDBGBVR14_EL1 = encode(0b10, 0b000, 0b0000, 0b1110, 0b100), // RW
+ kDBGBVR15_EL1 = encode(0b10, 0b000, 0b0000, 0b1111, 0b100), // RW
+ kDBGBVR1_EL1 = encode(0b10, 0b000, 0b0000, 0b0001, 0b100), // RW
+ kDBGBVR2_EL1 = encode(0b10, 0b000, 0b0000, 0b0010, 0b100), // RW
+ kDBGBVR3_EL1 = encode(0b10, 0b000, 0b0000, 0b0011, 0b100), // RW
+ kDBGBVR4_EL1 = encode(0b10, 0b000, 0b0000, 0b0100, 0b100), // RW
+ kDBGBVR5_EL1 = encode(0b10, 0b000, 0b0000, 0b0101, 0b100), // RW
+ kDBGBVR6_EL1 = encode(0b10, 0b000, 0b0000, 0b0110, 0b100), // RW
+ kDBGBVR7_EL1 = encode(0b10, 0b000, 0b0000, 0b0111, 0b100), // RW
+ kDBGBVR8_EL1 = encode(0b10, 0b000, 0b0000, 0b1000, 0b100), // RW
+ kDBGBVR9_EL1 = encode(0b10, 0b000, 0b0000, 0b1001, 0b100), // RW
+ kDBGCLAIMCLR_EL1 = encode(0b10, 0b000, 0b0111, 0b1001, 0b110), // RW
+ kDBGCLAIMSET_EL1 = encode(0b10, 0b000, 0b0111, 0b1000, 0b110), // RW
+ kDBGDTRRX_EL0 = encode(0b10, 0b011, 0b0000, 0b0101, 0b000), // RO
+ kDBGDTRTX_EL0 = encode(0b10, 0b011, 0b0000, 0b0101, 0b000), // WO
+ kDBGDTR_EL0 = encode(0b10, 0b011, 0b0000, 0b0100, 0b000), // RW
+ kDBGPRCR_EL1 = encode(0b10, 0b000, 0b0001, 0b0100, 0b100), // RW
+ kDBGVCR32_EL2 = encode(0b10, 0b100, 0b0000, 0b0111, 0b000), // RW
+ kDBGWCR0_EL1 = encode(0b10, 0b000, 0b0000, 0b0000, 0b111), // RW
+ kDBGWCR10_EL1 = encode(0b10, 0b000, 0b0000, 0b1010, 0b111), // RW
+ kDBGWCR11_EL1 = encode(0b10, 0b000, 0b0000, 0b1011, 0b111), // RW
+ kDBGWCR12_EL1 = encode(0b10, 0b000, 0b0000, 0b1100, 0b111), // RW
+ kDBGWCR13_EL1 = encode(0b10, 0b000, 0b0000, 0b1101, 0b111), // RW
+ kDBGWCR14_EL1 = encode(0b10, 0b000, 0b0000, 0b1110, 0b111), // RW
+ kDBGWCR15_EL1 = encode(0b10, 0b000, 0b0000, 0b1111, 0b111), // RW
+ kDBGWCR1_EL1 = encode(0b10, 0b000, 0b0000, 0b0001, 0b111), // RW
+ kDBGWCR2_EL1 = encode(0b10, 0b000, 0b0000, 0b0010, 0b111), // RW
+ kDBGWCR3_EL1 = encode(0b10, 0b000, 0b0000, 0b0011, 0b111), // RW
+ kDBGWCR4_EL1 = encode(0b10, 0b000, 0b0000, 0b0100, 0b111), // RW
+ kDBGWCR5_EL1 = encode(0b10, 0b000, 0b0000, 0b0101, 0b111), // RW
+ kDBGWCR6_EL1 = encode(0b10, 0b000, 0b0000, 0b0110, 0b111), // RW
+ kDBGWCR7_EL1 = encode(0b10, 0b000, 0b0000, 0b0111, 0b111), // RW
+ kDBGWCR8_EL1 = encode(0b10, 0b000, 0b0000, 0b1000, 0b111), // RW
+ kDBGWCR9_EL1 = encode(0b10, 0b000, 0b0000, 0b1001, 0b111), // RW
+ kDBGWVR0_EL1 = encode(0b10, 0b000, 0b0000, 0b0000, 0b110), // RW
+ kDBGWVR10_EL1 = encode(0b10, 0b000, 0b0000, 0b1010, 0b110), // RW
+ kDBGWVR11_EL1 = encode(0b10, 0b000, 0b0000, 0b1011, 0b110), // RW
+ kDBGWVR12_EL1 = encode(0b10, 0b000, 0b0000, 0b1100, 0b110), // RW
+ kDBGWVR13_EL1 = encode(0b10, 0b000, 0b0000, 0b1101, 0b110), // RW
+ kDBGWVR14_EL1 = encode(0b10, 0b000, 0b0000, 0b1110, 0b110), // RW
+ kDBGWVR15_EL1 = encode(0b10, 0b000, 0b0000, 0b1111, 0b110), // RW
+ kDBGWVR1_EL1 = encode(0b10, 0b000, 0b0000, 0b0001, 0b110), // RW
+ kDBGWVR2_EL1 = encode(0b10, 0b000, 0b0000, 0b0010, 0b110), // RW
+ kDBGWVR3_EL1 = encode(0b10, 0b000, 0b0000, 0b0011, 0b110), // RW
+ kDBGWVR4_EL1 = encode(0b10, 0b000, 0b0000, 0b0100, 0b110), // RW
+ kDBGWVR5_EL1 = encode(0b10, 0b000, 0b0000, 0b0101, 0b110), // RW
+ kDBGWVR6_EL1 = encode(0b10, 0b000, 0b0000, 0b0110, 0b110), // RW
+ kDBGWVR7_EL1 = encode(0b10, 0b000, 0b0000, 0b0111, 0b110), // RW
+ kDBGWVR8_EL1 = encode(0b10, 0b000, 0b0000, 0b1000, 0b110), // RW
+ kDBGWVR9_EL1 = encode(0b10, 0b000, 0b0000, 0b1001, 0b110), // RW
+ kDCZID_EL0 = encode(0b11, 0b011, 0b0000, 0b0000, 0b111), // RO
+ kDISR_EL1 = encode(0b11, 0b000, 0b1100, 0b0001, 0b001), // RW
+ kDIT = encode(0b11, 0b011, 0b0100, 0b0010, 0b101), // RW
+ kDLR_EL0 = encode(0b11, 0b011, 0b0100, 0b0101, 0b001), // RW
+ kDSPSR_EL0 = encode(0b11, 0b011, 0b0100, 0b0101, 0b000), // RW
+ kELR_EL1 = encode(0b11, 0b000, 0b0100, 0b0000, 0b001), // RW
+ kELR_EL12 = encode(0b11, 0b101, 0b0100, 0b0000, 0b001), // RW
+ kELR_EL2 = encode(0b11, 0b100, 0b0100, 0b0000, 0b001), // RW
+ kELR_EL3 = encode(0b11, 0b110, 0b0100, 0b0000, 0b001), // RW
+ kERRIDR_EL1 = encode(0b11, 0b000, 0b0101, 0b0011, 0b000), // RO
+ kERRSELR_EL1 = encode(0b11, 0b000, 0b0101, 0b0011, 0b001), // RW
+ kERXADDR_EL1 = encode(0b11, 0b000, 0b0101, 0b0100, 0b011), // RW
+ kERXCTLR_EL1 = encode(0b11, 0b000, 0b0101, 0b0100, 0b001), // RW
+ kERXFR_EL1 = encode(0b11, 0b000, 0b0101, 0b0100, 0b000), // RO
+ kERXMISC0_EL1 = encode(0b11, 0b000, 0b0101, 0b0101, 0b000), // RW
+ kERXMISC1_EL1 = encode(0b11, 0b000, 0b0101, 0b0101, 0b001), // RW
+ kERXMISC2_EL1 = encode(0b11, 0b000, 0b0101, 0b0101, 0b010), // RW
+ kERXMISC3_EL1 = encode(0b11, 0b000, 0b0101, 0b0101, 0b011), // RW
+ kERXPFGCDN_EL1 = encode(0b11, 0b000, 0b0101, 0b0100, 0b110), // RW
+ kERXPFGCTL_EL1 = encode(0b11, 0b000, 0b0101, 0b0100, 0b101), // RW
+ kERXPFGF_EL1 = encode(0b11, 0b000, 0b0101, 0b0100, 0b100), // RO
+ kERXSTATUS_EL1 = encode(0b11, 0b000, 0b0101, 0b0100, 0b010), // RW
+ kESR_EL1 = encode(0b11, 0b000, 0b0101, 0b0010, 0b000), // RW
+ kESR_EL12 = encode(0b11, 0b101, 0b0101, 0b0010, 0b000), // RW
+ kESR_EL2 = encode(0b11, 0b100, 0b0101, 0b0010, 0b000), // RW
+ kESR_EL3 = encode(0b11, 0b110, 0b0101, 0b0010, 0b000), // RW
+ kFAR_EL1 = encode(0b11, 0b000, 0b0110, 0b0000, 0b000), // RW
+ kFAR_EL12 = encode(0b11, 0b101, 0b0110, 0b0000, 0b000), // RW
+ kFAR_EL2 = encode(0b11, 0b100, 0b0110, 0b0000, 0b000), // RW
+ kFAR_EL3 = encode(0b11, 0b110, 0b0110, 0b0000, 0b000), // RW
+ kFPCR = encode(0b11, 0b011, 0b0100, 0b0100, 0b000), // RW
+ kFPEXC32_EL2 = encode(0b11, 0b100, 0b0101, 0b0011, 0b000), // RW
+ kFPSR = encode(0b11, 0b011, 0b0100, 0b0100, 0b001), // RW
+ kGCR_EL1 = encode(0b11, 0b000, 0b0001, 0b0000, 0b110), // RW
+ kGMID_EL1 = encode(0b11, 0b001, 0b0000, 0b0000, 0b100), // RO
+ kHACR_EL2 = encode(0b11, 0b100, 0b0001, 0b0001, 0b111), // RW
+ kHCR_EL2 = encode(0b11, 0b100, 0b0001, 0b0001, 0b000), // RW
+ kHDFGRTR_EL2 = encode(0b11, 0b100, 0b0011, 0b0001, 0b100), // RW
+ kHDFGWTR_EL2 = encode(0b11, 0b100, 0b0011, 0b0001, 0b101), // RW
+ kHFGITR_EL2 = encode(0b11, 0b100, 0b0001, 0b0001, 0b110), // RW
+ kHFGRTR_EL2 = encode(0b11, 0b100, 0b0001, 0b0001, 0b100), // RW
+ kHFGWTR_EL2 = encode(0b11, 0b100, 0b0001, 0b0001, 0b101), // RW
+ kHPFAR_EL2 = encode(0b11, 0b100, 0b0110, 0b0000, 0b100), // RW
+ kHSTR_EL2 = encode(0b11, 0b100, 0b0001, 0b0001, 0b011), // RW
+ kICC_AP0R0_EL1 = encode(0b11, 0b000, 0b1100, 0b1000, 0b100), // RW
+ kICC_AP0R1_EL1 = encode(0b11, 0b000, 0b1100, 0b1000, 0b101), // RW
+ kICC_AP0R2_EL1 = encode(0b11, 0b000, 0b1100, 0b1000, 0b110), // RW
+ kICC_AP0R3_EL1 = encode(0b11, 0b000, 0b1100, 0b1000, 0b111), // RW
+ kICC_AP1R0_EL1 = encode(0b11, 0b000, 0b1100, 0b1001, 0b000), // RW
+ kICC_AP1R1_EL1 = encode(0b11, 0b000, 0b1100, 0b1001, 0b001), // RW
+ kICC_AP1R2_EL1 = encode(0b11, 0b000, 0b1100, 0b1001, 0b010), // RW
+ kICC_AP1R3_EL1 = encode(0b11, 0b000, 0b1100, 0b1001, 0b011), // RW
+ kICC_ASGI1R_EL1 = encode(0b11, 0b000, 0b1100, 0b1011, 0b110), // WO
+ kICC_BPR0_EL1 = encode(0b11, 0b000, 0b1100, 0b1000, 0b011), // RW
+ kICC_BPR1_EL1 = encode(0b11, 0b000, 0b1100, 0b1100, 0b011), // RW
+ kICC_CTLR_EL1 = encode(0b11, 0b000, 0b1100, 0b1100, 0b100), // RW
+ kICC_CTLR_EL3 = encode(0b11, 0b110, 0b1100, 0b1100, 0b100), // RW
+ kICC_DIR_EL1 = encode(0b11, 0b000, 0b1100, 0b1011, 0b001), // WO
+ kICC_EOIR0_EL1 = encode(0b11, 0b000, 0b1100, 0b1000, 0b001), // WO
+ kICC_EOIR1_EL1 = encode(0b11, 0b000, 0b1100, 0b1100, 0b001), // WO
+ kICC_HPPIR0_EL1 = encode(0b11, 0b000, 0b1100, 0b1000, 0b010), // RO
+ kICC_HPPIR1_EL1 = encode(0b11, 0b000, 0b1100, 0b1100, 0b010), // RO
+ kICC_IAR0_EL1 = encode(0b11, 0b000, 0b1100, 0b1000, 0b000), // RO
+ kICC_IAR1_EL1 = encode(0b11, 0b000, 0b1100, 0b1100, 0b000), // RO
+ kICC_IGRPEN0_EL1 = encode(0b11, 0b000, 0b1100, 0b1100, 0b110), // RW
+ kICC_IGRPEN1_EL1 = encode(0b11, 0b000, 0b1100, 0b1100, 0b111), // RW
+ kICC_IGRPEN1_EL3 = encode(0b11, 0b110, 0b1100, 0b1100, 0b111), // RW
+ kICC_PMR_EL1 = encode(0b11, 0b000, 0b0100, 0b0110, 0b000), // RW
+ kICC_RPR_EL1 = encode(0b11, 0b000, 0b1100, 0b1011, 0b011), // RO
+ kICC_SGI0R_EL1 = encode(0b11, 0b000, 0b1100, 0b1011, 0b111), // WO
+ kICC_SGI1R_EL1 = encode(0b11, 0b000, 0b1100, 0b1011, 0b101), // WO
+ kICC_SRE_EL1 = encode(0b11, 0b000, 0b1100, 0b1100, 0b101), // RW
+ kICC_SRE_EL2 = encode(0b11, 0b100, 0b1100, 0b1001, 0b101), // RW
+ kICC_SRE_EL3 = encode(0b11, 0b110, 0b1100, 0b1100, 0b101), // RW
+ kICH_AP0R0_EL2 = encode(0b11, 0b100, 0b1100, 0b1000, 0b000), // RW
+ kICH_AP0R1_EL2 = encode(0b11, 0b100, 0b1100, 0b1000, 0b001), // RW
+ kICH_AP0R2_EL2 = encode(0b11, 0b100, 0b1100, 0b1000, 0b010), // RW
+ kICH_AP0R3_EL2 = encode(0b11, 0b100, 0b1100, 0b1000, 0b011), // RW
+ kICH_AP1R0_EL2 = encode(0b11, 0b100, 0b1100, 0b1001, 0b000), // RW
+ kICH_AP1R1_EL2 = encode(0b11, 0b100, 0b1100, 0b1001, 0b001), // RW
+ kICH_AP1R2_EL2 = encode(0b11, 0b100, 0b1100, 0b1001, 0b010), // RW
+ kICH_AP1R3_EL2 = encode(0b11, 0b100, 0b1100, 0b1001, 0b011), // RW
+ kICH_EISR_EL2 = encode(0b11, 0b100, 0b1100, 0b1011, 0b011), // RO
+ kICH_ELRSR_EL2 = encode(0b11, 0b100, 0b1100, 0b1011, 0b101), // RO
+ kICH_HCR_EL2 = encode(0b11, 0b100, 0b1100, 0b1011, 0b000), // RW
+ kICH_LR0_EL2 = encode(0b11, 0b100, 0b1100, 0b1100, 0b000), // RW
+ kICH_LR10_EL2 = encode(0b11, 0b100, 0b1100, 0b1101, 0b010), // RW
+ kICH_LR11_EL2 = encode(0b11, 0b100, 0b1100, 0b1101, 0b011), // RW
+ kICH_LR12_EL2 = encode(0b11, 0b100, 0b1100, 0b1101, 0b100), // RW
+ kICH_LR13_EL2 = encode(0b11, 0b100, 0b1100, 0b1101, 0b101), // RW
+ kICH_LR14_EL2 = encode(0b11, 0b100, 0b1100, 0b1101, 0b110), // RW
+ kICH_LR15_EL2 = encode(0b11, 0b100, 0b1100, 0b1101, 0b111), // RW
+ kICH_LR1_EL2 = encode(0b11, 0b100, 0b1100, 0b1100, 0b001), // RW
+ kICH_LR2_EL2 = encode(0b11, 0b100, 0b1100, 0b1100, 0b010), // RW
+ kICH_LR3_EL2 = encode(0b11, 0b100, 0b1100, 0b1100, 0b011), // RW
+ kICH_LR4_EL2 = encode(0b11, 0b100, 0b1100, 0b1100, 0b100), // RW
+ kICH_LR5_EL2 = encode(0b11, 0b100, 0b1100, 0b1100, 0b101), // RW
+ kICH_LR6_EL2 = encode(0b11, 0b100, 0b1100, 0b1100, 0b110), // RW
+ kICH_LR7_EL2 = encode(0b11, 0b100, 0b1100, 0b1100, 0b111), // RW
+ kICH_LR8_EL2 = encode(0b11, 0b100, 0b1100, 0b1101, 0b000), // RW
+ kICH_LR9_EL2 = encode(0b11, 0b100, 0b1100, 0b1101, 0b001), // RW
+ kICH_MISR_EL2 = encode(0b11, 0b100, 0b1100, 0b1011, 0b010), // RO
+ kICH_VMCR_EL2 = encode(0b11, 0b100, 0b1100, 0b1011, 0b111), // RW
+ kICH_VTR_EL2 = encode(0b11, 0b100, 0b1100, 0b1011, 0b001), // RO
+ kID_AA64AFR0_EL1 = encode(0b11, 0b000, 0b0000, 0b0101, 0b100), // RO
+ kID_AA64AFR1_EL1 = encode(0b11, 0b000, 0b0000, 0b0101, 0b101), // RO
+ kID_AA64DFR0_EL1 = encode(0b11, 0b000, 0b0000, 0b0101, 0b000), // RO
+ kID_AA64DFR1_EL1 = encode(0b11, 0b000, 0b0000, 0b0101, 0b001), // RO
+ kID_AA64ISAR0_EL1 = encode(0b11, 0b000, 0b0000, 0b0110, 0b000), // RO
+ kID_AA64ISAR1_EL1 = encode(0b11, 0b000, 0b0000, 0b0110, 0b001), // RO
+ kID_AA64MMFR0_EL1 = encode(0b11, 0b000, 0b0000, 0b0111, 0b000), // RO
+ kID_AA64MMFR1_EL1 = encode(0b11, 0b000, 0b0000, 0b0111, 0b001), // RO
+ kID_AA64MMFR2_EL1 = encode(0b11, 0b000, 0b0000, 0b0111, 0b010), // RO
+ kID_AA64PFR0_EL1 = encode(0b11, 0b000, 0b0000, 0b0100, 0b000), // RO
+ kID_AA64PFR1_EL1 = encode(0b11, 0b000, 0b0000, 0b0100, 0b001), // RO
+ kID_AA64ZFR0_EL1 = encode(0b11, 0b000, 0b0000, 0b0100, 0b100), // RO
+ kID_AFR0_EL1 = encode(0b11, 0b000, 0b0000, 0b0001, 0b011), // RO
+ kID_DFR0_EL1 = encode(0b11, 0b000, 0b0000, 0b0001, 0b010), // RO
+ kID_ISAR0_EL1 = encode(0b11, 0b000, 0b0000, 0b0010, 0b000), // RO
+ kID_ISAR1_EL1 = encode(0b11, 0b000, 0b0000, 0b0010, 0b001), // RO
+ kID_ISAR2_EL1 = encode(0b11, 0b000, 0b0000, 0b0010, 0b010), // RO
+ kID_ISAR3_EL1 = encode(0b11, 0b000, 0b0000, 0b0010, 0b011), // RO
+ kID_ISAR4_EL1 = encode(0b11, 0b000, 0b0000, 0b0010, 0b100), // RO
+ kID_ISAR5_EL1 = encode(0b11, 0b000, 0b0000, 0b0010, 0b101), // RO
+ kID_ISAR6_EL1 = encode(0b11, 0b000, 0b0000, 0b0010, 0b111), // RO
+ kID_MMFR0_EL1 = encode(0b11, 0b000, 0b0000, 0b0001, 0b100), // RO
+ kID_MMFR1_EL1 = encode(0b11, 0b000, 0b0000, 0b0001, 0b101), // RO
+ kID_MMFR2_EL1 = encode(0b11, 0b000, 0b0000, 0b0001, 0b110), // RO
+ kID_MMFR3_EL1 = encode(0b11, 0b000, 0b0000, 0b0001, 0b111), // RO
+ kID_MMFR4_EL1 = encode(0b11, 0b000, 0b0000, 0b0010, 0b110), // RO
+ kID_MMFR5_EL1 = encode(0b11, 0b000, 0b0000, 0b0011, 0b110), // RO
+ kID_PFR0_EL1 = encode(0b11, 0b000, 0b0000, 0b0001, 0b000), // RO
+ kID_PFR1_EL1 = encode(0b11, 0b000, 0b0000, 0b0001, 0b001), // RO
+ kID_PFR2_EL1 = encode(0b11, 0b000, 0b0000, 0b0011, 0b100), // RO
+ kIFSR32_EL2 = encode(0b11, 0b100, 0b0101, 0b0000, 0b001), // RW
+ kISR_EL1 = encode(0b11, 0b000, 0b1100, 0b0001, 0b000), // RO
+ kLORC_EL1 = encode(0b11, 0b000, 0b1010, 0b0100, 0b011), // RW
+ kLOREA_EL1 = encode(0b11, 0b000, 0b1010, 0b0100, 0b001), // RW
+ kLORID_EL1 = encode(0b11, 0b000, 0b1010, 0b0100, 0b111), // RO
+ kLORN_EL1 = encode(0b11, 0b000, 0b1010, 0b0100, 0b010), // RW
+ kLORSA_EL1 = encode(0b11, 0b000, 0b1010, 0b0100, 0b000), // RW
+ kMAIR_EL1 = encode(0b11, 0b000, 0b1010, 0b0010, 0b000), // RW
+ kMAIR_EL12 = encode(0b11, 0b101, 0b1010, 0b0010, 0b000), // RW
+ kMAIR_EL2 = encode(0b11, 0b100, 0b1010, 0b0010, 0b000), // RW
+ kMAIR_EL3 = encode(0b11, 0b110, 0b1010, 0b0010, 0b000), // RW
+ kMDCCINT_EL1 = encode(0b10, 0b000, 0b0000, 0b0010, 0b000), // RW
+ kMDCCSR_EL0 = encode(0b10, 0b011, 0b0000, 0b0001, 0b000), // RO
+ kMDCR_EL2 = encode(0b11, 0b100, 0b0001, 0b0001, 0b001), // RW
+ kMDCR_EL3 = encode(0b11, 0b110, 0b0001, 0b0011, 0b001), // RW
+ kMDRAR_EL1 = encode(0b10, 0b000, 0b0001, 0b0000, 0b000), // RO
+ kMDSCR_EL1 = encode(0b10, 0b000, 0b0000, 0b0010, 0b010), // RW
+ kMIDR_EL1 = encode(0b11, 0b000, 0b0000, 0b0000, 0b000), // RO
+ kMPAM0_EL1 = encode(0b11, 0b000, 0b1010, 0b0101, 0b001), // RW
+ kMPAM1_EL1 = encode(0b11, 0b000, 0b1010, 0b0101, 0b000), // RW
+ kMPAM1_EL12 = encode(0b11, 0b101, 0b1010, 0b0101, 0b000), // RW
+ kMPAM2_EL2 = encode(0b11, 0b100, 0b1010, 0b0101, 0b000), // RW
+ kMPAM3_EL3 = encode(0b11, 0b110, 0b1010, 0b0101, 0b000), // RW
+ kMPAMHCR_EL2 = encode(0b11, 0b100, 0b1010, 0b0100, 0b000), // RW
+ kMPAMIDR_EL1 = encode(0b11, 0b000, 0b1010, 0b0100, 0b100), // RO
+ kMPAMVPM0_EL2 = encode(0b11, 0b100, 0b1010, 0b0110, 0b000), // RW
+ kMPAMVPM1_EL2 = encode(0b11, 0b100, 0b1010, 0b0110, 0b001), // RW
+ kMPAMVPM2_EL2 = encode(0b11, 0b100, 0b1010, 0b0110, 0b010), // RW
+ kMPAMVPM3_EL2 = encode(0b11, 0b100, 0b1010, 0b0110, 0b011), // RW
+ kMPAMVPM4_EL2 = encode(0b11, 0b100, 0b1010, 0b0110, 0b100), // RW
+ kMPAMVPM5_EL2 = encode(0b11, 0b100, 0b1010, 0b0110, 0b101), // RW
+ kMPAMVPM6_EL2 = encode(0b11, 0b100, 0b1010, 0b0110, 0b110), // RW
+ kMPAMVPM7_EL2 = encode(0b11, 0b100, 0b1010, 0b0110, 0b111), // RW
+ kMPAMVPMV_EL2 = encode(0b11, 0b100, 0b1010, 0b0100, 0b001), // RW
+ kMPIDR_EL1 = encode(0b11, 0b000, 0b0000, 0b0000, 0b101), // RO
+ kMVFR0_EL1 = encode(0b11, 0b000, 0b0000, 0b0011, 0b000), // RO
+ kMVFR1_EL1 = encode(0b11, 0b000, 0b0000, 0b0011, 0b001), // RO
+ kMVFR2_EL1 = encode(0b11, 0b000, 0b0000, 0b0011, 0b010), // RO
+ kNZCV = encode(0b11, 0b011, 0b0100, 0b0010, 0b000), // RW
+ kOSDLR_EL1 = encode(0b10, 0b000, 0b0001, 0b0011, 0b100), // RW
+ kOSDTRRX_EL1 = encode(0b10, 0b000, 0b0000, 0b0000, 0b010), // RW
+ kOSDTRTX_EL1 = encode(0b10, 0b000, 0b0000, 0b0011, 0b010), // RW
+ kOSECCR_EL1 = encode(0b10, 0b000, 0b0000, 0b0110, 0b010), // RW
+ kOSLAR_EL1 = encode(0b10, 0b000, 0b0001, 0b0000, 0b100), // WO
+ kOSLSR_EL1 = encode(0b10, 0b000, 0b0001, 0b0001, 0b100), // RO
+ kPAN = encode(0b11, 0b000, 0b0100, 0b0010, 0b011), // RW
+ kPAR_EL1 = encode(0b11, 0b000, 0b0111, 0b0100, 0b000), // RW
+ kPMBIDR_EL1 = encode(0b11, 0b000, 0b1001, 0b1010, 0b111), // RO
+ kPMBLIMITR_EL1 = encode(0b11, 0b000, 0b1001, 0b1010, 0b000), // RW
+ kPMBPTR_EL1 = encode(0b11, 0b000, 0b1001, 0b1010, 0b001), // RW
+ kPMBSR_EL1 = encode(0b11, 0b000, 0b1001, 0b1010, 0b011), // RW
+ kPMCCFILTR_EL0 = encode(0b11, 0b011, 0b1110, 0b1111, 0b111), // RW
+ kPMCCNTR_EL0 = encode(0b11, 0b011, 0b1001, 0b1101, 0b000), // RW
+ kPMCEID0_EL0 = encode(0b11, 0b011, 0b1001, 0b1100, 0b110), // RO
+ kPMCEID1_EL0 = encode(0b11, 0b011, 0b1001, 0b1100, 0b111), // RO
+ kPMCNTENCLR_EL0 = encode(0b11, 0b011, 0b1001, 0b1100, 0b010), // RW
+ kPMCNTENSET_EL0 = encode(0b11, 0b011, 0b1001, 0b1100, 0b001), // RW
+ kPMCR_EL0 = encode(0b11, 0b011, 0b1001, 0b1100, 0b000), // RW
+ kPMEVCNTR0_EL0 = encode(0b11, 0b011, 0b1110, 0b1000, 0b000), // RW
+ kPMEVCNTR10_EL0 = encode(0b11, 0b011, 0b1110, 0b1001, 0b010), // RW
+ kPMEVCNTR11_EL0 = encode(0b11, 0b011, 0b1110, 0b1001, 0b011), // RW
+ kPMEVCNTR12_EL0 = encode(0b11, 0b011, 0b1110, 0b1001, 0b100), // RW
+ kPMEVCNTR13_EL0 = encode(0b11, 0b011, 0b1110, 0b1001, 0b101), // RW
+ kPMEVCNTR14_EL0 = encode(0b11, 0b011, 0b1110, 0b1001, 0b110), // RW
+ kPMEVCNTR15_EL0 = encode(0b11, 0b011, 0b1110, 0b1001, 0b111), // RW
+ kPMEVCNTR16_EL0 = encode(0b11, 0b011, 0b1110, 0b1010, 0b000), // RW
+ kPMEVCNTR17_EL0 = encode(0b11, 0b011, 0b1110, 0b1010, 0b001), // RW
+ kPMEVCNTR18_EL0 = encode(0b11, 0b011, 0b1110, 0b1010, 0b010), // RW
+ kPMEVCNTR19_EL0 = encode(0b11, 0b011, 0b1110, 0b1010, 0b011), // RW
+ kPMEVCNTR1_EL0 = encode(0b11, 0b011, 0b1110, 0b1000, 0b001), // RW
+ kPMEVCNTR20_EL0 = encode(0b11, 0b011, 0b1110, 0b1010, 0b100), // RW
+ kPMEVCNTR21_EL0 = encode(0b11, 0b011, 0b1110, 0b1010, 0b101), // RW
+ kPMEVCNTR22_EL0 = encode(0b11, 0b011, 0b1110, 0b1010, 0b110), // RW
+ kPMEVCNTR23_EL0 = encode(0b11, 0b011, 0b1110, 0b1010, 0b111), // RW
+ kPMEVCNTR24_EL0 = encode(0b11, 0b011, 0b1110, 0b1011, 0b000), // RW
+ kPMEVCNTR25_EL0 = encode(0b11, 0b011, 0b1110, 0b1011, 0b001), // RW
+ kPMEVCNTR26_EL0 = encode(0b11, 0b011, 0b1110, 0b1011, 0b010), // RW
+ kPMEVCNTR27_EL0 = encode(0b11, 0b011, 0b1110, 0b1011, 0b011), // RW
+ kPMEVCNTR28_EL0 = encode(0b11, 0b011, 0b1110, 0b1011, 0b100), // RW
+ kPMEVCNTR29_EL0 = encode(0b11, 0b011, 0b1110, 0b1011, 0b101), // RW
+ kPMEVCNTR2_EL0 = encode(0b11, 0b011, 0b1110, 0b1000, 0b010), // RW
+ kPMEVCNTR30_EL0 = encode(0b11, 0b011, 0b1110, 0b1011, 0b110), // RW
+ kPMEVCNTR3_EL0 = encode(0b11, 0b011, 0b1110, 0b1000, 0b011), // RW
+ kPMEVCNTR4_EL0 = encode(0b11, 0b011, 0b1110, 0b1000, 0b100), // RW
+ kPMEVCNTR5_EL0 = encode(0b11, 0b011, 0b1110, 0b1000, 0b101), // RW
+ kPMEVCNTR6_EL0 = encode(0b11, 0b011, 0b1110, 0b1000, 0b110), // RW
+ kPMEVCNTR7_EL0 = encode(0b11, 0b011, 0b1110, 0b1000, 0b111), // RW
+ kPMEVCNTR8_EL0 = encode(0b11, 0b011, 0b1110, 0b1001, 0b000), // RW
+ kPMEVCNTR9_EL0 = encode(0b11, 0b011, 0b1110, 0b1001, 0b001), // RW
+ kPMEVTYPER0_EL0 = encode(0b11, 0b011, 0b1110, 0b1100, 0b000), // RW
+ kPMEVTYPER10_EL0 = encode(0b11, 0b011, 0b1110, 0b1101, 0b010), // RW
+ kPMEVTYPER11_EL0 = encode(0b11, 0b011, 0b1110, 0b1101, 0b011), // RW
+ kPMEVTYPER12_EL0 = encode(0b11, 0b011, 0b1110, 0b1101, 0b100), // RW
+ kPMEVTYPER13_EL0 = encode(0b11, 0b011, 0b1110, 0b1101, 0b101), // RW
+ kPMEVTYPER14_EL0 = encode(0b11, 0b011, 0b1110, 0b1101, 0b110), // RW
+ kPMEVTYPER15_EL0 = encode(0b11, 0b011, 0b1110, 0b1101, 0b111), // RW
+ kPMEVTYPER16_EL0 = encode(0b11, 0b011, 0b1110, 0b1110, 0b000), // RW
+ kPMEVTYPER17_EL0 = encode(0b11, 0b011, 0b1110, 0b1110, 0b001), // RW
+ kPMEVTYPER18_EL0 = encode(0b11, 0b011, 0b1110, 0b1110, 0b010), // RW
+ kPMEVTYPER19_EL0 = encode(0b11, 0b011, 0b1110, 0b1110, 0b011), // RW
+ kPMEVTYPER1_EL0 = encode(0b11, 0b011, 0b1110, 0b1100, 0b001), // RW
+ kPMEVTYPER20_EL0 = encode(0b11, 0b011, 0b1110, 0b1110, 0b100), // RW
+ kPMEVTYPER21_EL0 = encode(0b11, 0b011, 0b1110, 0b1110, 0b101), // RW
+ kPMEVTYPER22_EL0 = encode(0b11, 0b011, 0b1110, 0b1110, 0b110), // RW
+ kPMEVTYPER23_EL0 = encode(0b11, 0b011, 0b1110, 0b1110, 0b111), // RW
+ kPMEVTYPER24_EL0 = encode(0b11, 0b011, 0b1110, 0b1111, 0b000), // RW
+ kPMEVTYPER25_EL0 = encode(0b11, 0b011, 0b1110, 0b1111, 0b001), // RW
+ kPMEVTYPER26_EL0 = encode(0b11, 0b011, 0b1110, 0b1111, 0b010), // RW
+ kPMEVTYPER27_EL0 = encode(0b11, 0b011, 0b1110, 0b1111, 0b011), // RW
+ kPMEVTYPER28_EL0 = encode(0b11, 0b011, 0b1110, 0b1111, 0b100), // RW
+ kPMEVTYPER29_EL0 = encode(0b11, 0b011, 0b1110, 0b1111, 0b101), // RW
+ kPMEVTYPER2_EL0 = encode(0b11, 0b011, 0b1110, 0b1100, 0b010), // RW
+ kPMEVTYPER30_EL0 = encode(0b11, 0b011, 0b1110, 0b1111, 0b110), // RW
+ kPMEVTYPER3_EL0 = encode(0b11, 0b011, 0b1110, 0b1100, 0b011), // RW
+ kPMEVTYPER4_EL0 = encode(0b11, 0b011, 0b1110, 0b1100, 0b100), // RW
+ kPMEVTYPER5_EL0 = encode(0b11, 0b011, 0b1110, 0b1100, 0b101), // RW
+ kPMEVTYPER6_EL0 = encode(0b11, 0b011, 0b1110, 0b1100, 0b110), // RW
+ kPMEVTYPER7_EL0 = encode(0b11, 0b011, 0b1110, 0b1100, 0b111), // RW
+ kPMEVTYPER8_EL0 = encode(0b11, 0b011, 0b1110, 0b1101, 0b000), // RW
+ kPMEVTYPER9_EL0 = encode(0b11, 0b011, 0b1110, 0b1101, 0b001), // RW
+ kPMINTENCLR_EL1 = encode(0b11, 0b000, 0b1001, 0b1110, 0b010), // RW
+ kPMINTENSET_EL1 = encode(0b11, 0b000, 0b1001, 0b1110, 0b001), // RW
+ kPMMIR_EL1 = encode(0b11, 0b000, 0b1001, 0b1110, 0b110), // RW
+ kPMOVSCLR_EL0 = encode(0b11, 0b011, 0b1001, 0b1100, 0b011), // RW
+ kPMOVSSET_EL0 = encode(0b11, 0b011, 0b1001, 0b1110, 0b011), // RW
+ kPMSCR_EL1 = encode(0b11, 0b000, 0b1001, 0b1001, 0b000), // RW
+ kPMSCR_EL12 = encode(0b11, 0b101, 0b1001, 0b1001, 0b000), // RW
+ kPMSCR_EL2 = encode(0b11, 0b100, 0b1001, 0b1001, 0b000), // RW
+ kPMSELR_EL0 = encode(0b11, 0b011, 0b1001, 0b1100, 0b101), // RW
+ kPMSEVFR_EL1 = encode(0b11, 0b000, 0b1001, 0b1001, 0b101), // RW
+ kPMSFCR_EL1 = encode(0b11, 0b000, 0b1001, 0b1001, 0b100), // RW
+ kPMSICR_EL1 = encode(0b11, 0b000, 0b1001, 0b1001, 0b010), // RW
+ kPMSIDR_EL1 = encode(0b11, 0b000, 0b1001, 0b1001, 0b111), // RO
+ kPMSIRR_EL1 = encode(0b11, 0b000, 0b1001, 0b1001, 0b011), // RW
+ kPMSLATFR_EL1 = encode(0b11, 0b000, 0b1001, 0b1001, 0b110), // RW
+ kPMSWINC_EL0 = encode(0b11, 0b011, 0b1001, 0b1100, 0b100), // WO
+ kPMUSERENR_EL0 = encode(0b11, 0b011, 0b1001, 0b1110, 0b000), // RW
+ kPMXEVCNTR_EL0 = encode(0b11, 0b011, 0b1001, 0b1101, 0b010), // RW
+ kPMXEVTYPER_EL0 = encode(0b11, 0b011, 0b1001, 0b1101, 0b001), // RW
+ kREVIDR_EL1 = encode(0b11, 0b000, 0b0000, 0b0000, 0b110), // RO
+ kRGSR_EL1 = encode(0b11, 0b000, 0b0001, 0b0000, 0b101), // RW
+ kRMR_EL1 = encode(0b11, 0b000, 0b1100, 0b0000, 0b010), // RW
+ kRMR_EL2 = encode(0b11, 0b100, 0b1100, 0b0000, 0b010), // RW
+ kRMR_EL3 = encode(0b11, 0b110, 0b1100, 0b0000, 0b010), // RW
+ kRNDR = encode(0b11, 0b011, 0b0010, 0b0100, 0b000), // RO
+ kRNDRRS = encode(0b11, 0b011, 0b0010, 0b0100, 0b001), // RO
+ kRVBAR_EL1 = encode(0b11, 0b000, 0b1100, 0b0000, 0b001), // RO
+ kRVBAR_EL2 = encode(0b11, 0b100, 0b1100, 0b0000, 0b001), // RO
+ kRVBAR_EL3 = encode(0b11, 0b110, 0b1100, 0b0000, 0b001), // RO
+ kSCR_EL3 = encode(0b11, 0b110, 0b0001, 0b0001, 0b000), // RW
+ kSCTLR_EL1 = encode(0b11, 0b000, 0b0001, 0b0000, 0b000), // RW
+ kSCTLR_EL12 = encode(0b11, 0b101, 0b0001, 0b0000, 0b000), // RW
+ kSCTLR_EL2 = encode(0b11, 0b100, 0b0001, 0b0000, 0b000), // RW
+ kSCTLR_EL3 = encode(0b11, 0b110, 0b0001, 0b0000, 0b000), // RW
+ kSCXTNUM_EL0 = encode(0b11, 0b011, 0b1101, 0b0000, 0b111), // RW
+ kSCXTNUM_EL1 = encode(0b11, 0b000, 0b1101, 0b0000, 0b111), // RW
+ kSCXTNUM_EL12 = encode(0b11, 0b101, 0b1101, 0b0000, 0b111), // RW
+ kSCXTNUM_EL2 = encode(0b11, 0b100, 0b1101, 0b0000, 0b111), // RW
+ kSCXTNUM_EL3 = encode(0b11, 0b110, 0b1101, 0b0000, 0b111), // RW
+ kSDER32_EL2 = encode(0b11, 0b100, 0b0001, 0b0011, 0b001), // RW
+ kSDER32_EL3 = encode(0b11, 0b110, 0b0001, 0b0001, 0b001), // RW
+ kSPSR_EL1 = encode(0b11, 0b000, 0b0100, 0b0000, 0b000), // RW
+ kSPSR_EL12 = encode(0b11, 0b101, 0b0100, 0b0000, 0b000), // RW
+ kSPSR_EL2 = encode(0b11, 0b100, 0b0100, 0b0000, 0b000), // RW
+ kSPSR_EL3 = encode(0b11, 0b110, 0b0100, 0b0000, 0b000), // RW
+ kSPSR_abt = encode(0b11, 0b100, 0b0100, 0b0011, 0b001), // RW
+ kSPSR_fiq = encode(0b11, 0b100, 0b0100, 0b0011, 0b011), // RW
+ kSPSR_irq = encode(0b11, 0b100, 0b0100, 0b0011, 0b000), // RW
+ kSPSR_und = encode(0b11, 0b100, 0b0100, 0b0011, 0b010), // RW
+ kSPSel = encode(0b11, 0b000, 0b0100, 0b0010, 0b000), // RW
+ kSP_EL0 = encode(0b11, 0b000, 0b0100, 0b0001, 0b000), // RW
+ kSP_EL1 = encode(0b11, 0b100, 0b0100, 0b0001, 0b000), // RW
+ kSP_EL2 = encode(0b11, 0b110, 0b0100, 0b0001, 0b000), // RW
+ kSSBS = encode(0b11, 0b011, 0b0100, 0b0010, 0b110), // RW
+ kTCO = encode(0b11, 0b011, 0b0100, 0b0010, 0b111), // RW
+ kTCR_EL1 = encode(0b11, 0b000, 0b0010, 0b0000, 0b010), // RW
+ kTCR_EL12 = encode(0b11, 0b101, 0b0010, 0b0000, 0b010), // RW
+ kTCR_EL2 = encode(0b11, 0b100, 0b0010, 0b0000, 0b010), // RW
+ kTCR_EL3 = encode(0b11, 0b110, 0b0010, 0b0000, 0b010), // RW
+ kTEECR32_EL1 = encode(0b10, 0b010, 0b0000, 0b0000, 0b000), // RW
+ kTEEHBR32_EL1 = encode(0b10, 0b010, 0b0001, 0b0000, 0b000), // RW
+ kTFSRE0_EL1 = encode(0b11, 0b000, 0b0101, 0b0110, 0b001), // RW
+ kTFSR_EL1 = encode(0b11, 0b000, 0b0101, 0b0110, 0b000), // RW
+ kTFSR_EL12 = encode(0b11, 0b101, 0b0101, 0b0110, 0b000), // RW
+ kTFSR_EL2 = encode(0b11, 0b100, 0b0101, 0b0110, 0b000), // RW
+ kTFSR_EL3 = encode(0b11, 0b110, 0b0101, 0b0110, 0b000), // RW
+ kTPIDRRO_EL0 = encode(0b11, 0b011, 0b1101, 0b0000, 0b011), // RW
+ kTPIDR_EL0 = encode(0b11, 0b011, 0b1101, 0b0000, 0b010), // RW
+ kTPIDR_EL1 = encode(0b11, 0b000, 0b1101, 0b0000, 0b100), // RW
+ kTPIDR_EL2 = encode(0b11, 0b100, 0b1101, 0b0000, 0b010), // RW
+ kTPIDR_EL3 = encode(0b11, 0b110, 0b1101, 0b0000, 0b010), // RW
+ kTRBBASER_EL1 = encode(0b11, 0b000, 0b1001, 0b1011, 0b010), // RW
+ kTRBIDR_EL1 = encode(0b11, 0b000, 0b1001, 0b1011, 0b111), // RO
+ kTRBLIMITR_EL1 = encode(0b11, 0b000, 0b1001, 0b1011, 0b000), // RW
+ kTRBMAR_EL1 = encode(0b11, 0b000, 0b1001, 0b1011, 0b100), // RW
+ kTRBPTR_EL1 = encode(0b11, 0b000, 0b1001, 0b1011, 0b001), // RW
+ kTRBSR_EL1 = encode(0b11, 0b000, 0b1001, 0b1011, 0b011), // RW
+ kTRBTRG_EL1 = encode(0b11, 0b000, 0b1001, 0b1011, 0b110), // RW
+ kTRCACATR0 = encode(0b10, 0b001, 0b0010, 0b0000, 0b010), // RW
+ kTRCACATR1 = encode(0b10, 0b001, 0b0010, 0b0010, 0b010), // RW
+ kTRCACATR10 = encode(0b10, 0b001, 0b0010, 0b0100, 0b011), // RW
+ kTRCACATR11 = encode(0b10, 0b001, 0b0010, 0b0110, 0b011), // RW
+ kTRCACATR12 = encode(0b10, 0b001, 0b0010, 0b1000, 0b011), // RW
+ kTRCACATR13 = encode(0b10, 0b001, 0b0010, 0b1010, 0b011), // RW
+ kTRCACATR14 = encode(0b10, 0b001, 0b0010, 0b1100, 0b011), // RW
+ kTRCACATR15 = encode(0b10, 0b001, 0b0010, 0b1110, 0b011), // RW
+ kTRCACATR2 = encode(0b10, 0b001, 0b0010, 0b0100, 0b010), // RW
+ kTRCACATR3 = encode(0b10, 0b001, 0b0010, 0b0110, 0b010), // RW
+ kTRCACATR4 = encode(0b10, 0b001, 0b0010, 0b1000, 0b010), // RW
+ kTRCACATR5 = encode(0b10, 0b001, 0b0010, 0b1010, 0b010), // RW
+ kTRCACATR6 = encode(0b10, 0b001, 0b0010, 0b1100, 0b010), // RW
+ kTRCACATR7 = encode(0b10, 0b001, 0b0010, 0b1110, 0b010), // RW
+ kTRCACATR8 = encode(0b10, 0b001, 0b0010, 0b0000, 0b011), // RW
+ kTRCACATR9 = encode(0b10, 0b001, 0b0010, 0b0010, 0b011), // RW
+ kTRCACVR0 = encode(0b10, 0b001, 0b0010, 0b0000, 0b000), // RW
+ kTRCACVR1 = encode(0b10, 0b001, 0b0010, 0b0010, 0b000), // RW
+ kTRCACVR10 = encode(0b10, 0b001, 0b0010, 0b0100, 0b001), // RW
+ kTRCACVR11 = encode(0b10, 0b001, 0b0010, 0b0110, 0b001), // RW
+ kTRCACVR12 = encode(0b10, 0b001, 0b0010, 0b1000, 0b001), // RW
+ kTRCACVR13 = encode(0b10, 0b001, 0b0010, 0b1010, 0b001), // RW
+ kTRCACVR14 = encode(0b10, 0b001, 0b0010, 0b1100, 0b001), // RW
+ kTRCACVR15 = encode(0b10, 0b001, 0b0010, 0b1110, 0b001), // RW
+ kTRCACVR2 = encode(0b10, 0b001, 0b0010, 0b0100, 0b000), // RW
+ kTRCACVR3 = encode(0b10, 0b001, 0b0010, 0b0110, 0b000), // RW
+ kTRCACVR4 = encode(0b10, 0b001, 0b0010, 0b1000, 0b000), // RW
+ kTRCACVR5 = encode(0b10, 0b001, 0b0010, 0b1010, 0b000), // RW
+ kTRCACVR6 = encode(0b10, 0b001, 0b0010, 0b1100, 0b000), // RW
+ kTRCACVR7 = encode(0b10, 0b001, 0b0010, 0b1110, 0b000), // RW
+ kTRCACVR8 = encode(0b10, 0b001, 0b0010, 0b0000, 0b001), // RW
+ kTRCACVR9 = encode(0b10, 0b001, 0b0010, 0b0010, 0b001), // RW
+ kTRCAUTHSTATUS = encode(0b10, 0b001, 0b0111, 0b1110, 0b110), // RO
+ kTRCAUXCTLR = encode(0b10, 0b001, 0b0000, 0b0110, 0b000), // RW
+ kTRCBBCTLR = encode(0b10, 0b001, 0b0000, 0b1111, 0b000), // RW
+ kTRCCCCTLR = encode(0b10, 0b001, 0b0000, 0b1110, 0b000), // RW
+ kTRCCIDCCTLR0 = encode(0b10, 0b001, 0b0011, 0b0000, 0b010), // RW
+ kTRCCIDCCTLR1 = encode(0b10, 0b001, 0b0011, 0b0001, 0b010), // RW
+ kTRCCIDCVR0 = encode(0b10, 0b001, 0b0011, 0b0000, 0b000), // RW
+ kTRCCIDCVR1 = encode(0b10, 0b001, 0b0011, 0b0010, 0b000), // RW
+ kTRCCIDCVR2 = encode(0b10, 0b001, 0b0011, 0b0100, 0b000), // RW
+ kTRCCIDCVR3 = encode(0b10, 0b001, 0b0011, 0b0110, 0b000), // RW
+ kTRCCIDCVR4 = encode(0b10, 0b001, 0b0011, 0b1000, 0b000), // RW
+ kTRCCIDCVR5 = encode(0b10, 0b001, 0b0011, 0b1010, 0b000), // RW
+ kTRCCIDCVR6 = encode(0b10, 0b001, 0b0011, 0b1100, 0b000), // RW
+ kTRCCIDCVR7 = encode(0b10, 0b001, 0b0011, 0b1110, 0b000), // RW
+ kTRCCIDR0 = encode(0b10, 0b001, 0b0111, 0b1100, 0b111), // RO
+ kTRCCIDR1 = encode(0b10, 0b001, 0b0111, 0b1101, 0b111), // RO
+ kTRCCIDR2 = encode(0b10, 0b001, 0b0111, 0b1110, 0b111), // RO
+ kTRCCIDR3 = encode(0b10, 0b001, 0b0111, 0b1111, 0b111), // RO
+ kTRCCLAIMCLR = encode(0b10, 0b001, 0b0111, 0b1001, 0b110), // RW
+ kTRCCLAIMSET = encode(0b10, 0b001, 0b0111, 0b1000, 0b110), // RW
+ kTRCCNTCTLR0 = encode(0b10, 0b001, 0b0000, 0b0100, 0b101), // RW
+ kTRCCNTCTLR1 = encode(0b10, 0b001, 0b0000, 0b0101, 0b101), // RW
+ kTRCCNTCTLR2 = encode(0b10, 0b001, 0b0000, 0b0110, 0b101), // RW
+ kTRCCNTCTLR3 = encode(0b10, 0b001, 0b0000, 0b0111, 0b101), // RW
+ kTRCCNTRLDVR0 = encode(0b10, 0b001, 0b0000, 0b0000, 0b101), // RW
+ kTRCCNTRLDVR1 = encode(0b10, 0b001, 0b0000, 0b0001, 0b101), // RW
+ kTRCCNTRLDVR2 = encode(0b10, 0b001, 0b0000, 0b0010, 0b101), // RW
+ kTRCCNTRLDVR3 = encode(0b10, 0b001, 0b0000, 0b0011, 0b101), // RW
+ kTRCCNTVR0 = encode(0b10, 0b001, 0b0000, 0b1000, 0b101), // RW
+ kTRCCNTVR1 = encode(0b10, 0b001, 0b0000, 0b1001, 0b101), // RW
+ kTRCCNTVR2 = encode(0b10, 0b001, 0b0000, 0b1010, 0b101), // RW
+ kTRCCNTVR3 = encode(0b10, 0b001, 0b0000, 0b1011, 0b101), // RW
+ kTRCCONFIGR = encode(0b10, 0b001, 0b0000, 0b0100, 0b000), // RW
+ kTRCDEVAFF0 = encode(0b10, 0b001, 0b0111, 0b1010, 0b110), // RO
+ kTRCDEVAFF1 = encode(0b10, 0b001, 0b0111, 0b1011, 0b110), // RO
+ kTRCDEVARCH = encode(0b10, 0b001, 0b0111, 0b1111, 0b110), // RO
+ kTRCDEVID = encode(0b10, 0b001, 0b0111, 0b0010, 0b111), // RO
+ kTRCDEVTYPE = encode(0b10, 0b001, 0b0111, 0b0011, 0b111), // RO
+ kTRCDVCMR0 = encode(0b10, 0b001, 0b0010, 0b0000, 0b110), // RW
+ kTRCDVCMR1 = encode(0b10, 0b001, 0b0010, 0b0100, 0b110), // RW
+ kTRCDVCMR2 = encode(0b10, 0b001, 0b0010, 0b1000, 0b110), // RW
+ kTRCDVCMR3 = encode(0b10, 0b001, 0b0010, 0b1100, 0b110), // RW
+ kTRCDVCMR4 = encode(0b10, 0b001, 0b0010, 0b0000, 0b111), // RW
+ kTRCDVCMR5 = encode(0b10, 0b001, 0b0010, 0b0100, 0b111), // RW
+ kTRCDVCMR6 = encode(0b10, 0b001, 0b0010, 0b1000, 0b111), // RW
+ kTRCDVCMR7 = encode(0b10, 0b001, 0b0010, 0b1100, 0b111), // RW
+ kTRCDVCVR0 = encode(0b10, 0b001, 0b0010, 0b0000, 0b100), // RW
+ kTRCDVCVR1 = encode(0b10, 0b001, 0b0010, 0b0100, 0b100), // RW
+ kTRCDVCVR2 = encode(0b10, 0b001, 0b0010, 0b1000, 0b100), // RW
+ kTRCDVCVR3 = encode(0b10, 0b001, 0b0010, 0b1100, 0b100), // RW
+ kTRCDVCVR4 = encode(0b10, 0b001, 0b0010, 0b0000, 0b101), // RW
+ kTRCDVCVR5 = encode(0b10, 0b001, 0b0010, 0b0100, 0b101), // RW
+ kTRCDVCVR6 = encode(0b10, 0b001, 0b0010, 0b1000, 0b101), // RW
+ kTRCDVCVR7 = encode(0b10, 0b001, 0b0010, 0b1100, 0b101), // RW
+ kTRCEVENTCTL0R = encode(0b10, 0b001, 0b0000, 0b1000, 0b000), // RW
+ kTRCEVENTCTL1R = encode(0b10, 0b001, 0b0000, 0b1001, 0b000), // RW
+ kTRCEXTINSELR = encode(0b10, 0b001, 0b0000, 0b1000, 0b100), // RW
+ kTRCEXTINSELR0 = encode(0b10, 0b001, 0b0000, 0b1000, 0b100), // RW
+ kTRCEXTINSELR1 = encode(0b10, 0b001, 0b0000, 0b1001, 0b100), // RW
+ kTRCEXTINSELR2 = encode(0b10, 0b001, 0b0000, 0b1010, 0b100), // RW
+ kTRCEXTINSELR3 = encode(0b10, 0b001, 0b0000, 0b1011, 0b100), // RW
+ kTRCIDR0 = encode(0b10, 0b001, 0b0000, 0b1000, 0b111), // RO
+ kTRCIDR1 = encode(0b10, 0b001, 0b0000, 0b1001, 0b111), // RO
+ kTRCIDR10 = encode(0b10, 0b001, 0b0000, 0b0010, 0b110), // RO
+ kTRCIDR11 = encode(0b10, 0b001, 0b0000, 0b0011, 0b110), // RO
+ kTRCIDR12 = encode(0b10, 0b001, 0b0000, 0b0100, 0b110), // RO
+ kTRCIDR13 = encode(0b10, 0b001, 0b0000, 0b0101, 0b110), // RO
+ kTRCIDR2 = encode(0b10, 0b001, 0b0000, 0b1010, 0b111), // RO
+ kTRCIDR3 = encode(0b10, 0b001, 0b0000, 0b1011, 0b111), // RO
+ kTRCIDR4 = encode(0b10, 0b001, 0b0000, 0b1100, 0b111), // RO
+ kTRCIDR5 = encode(0b10, 0b001, 0b0000, 0b1101, 0b111), // RO
+ kTRCIDR6 = encode(0b10, 0b001, 0b0000, 0b1110, 0b111), // RO
+ kTRCIDR7 = encode(0b10, 0b001, 0b0000, 0b1111, 0b111), // RO
+ kTRCIDR8 = encode(0b10, 0b001, 0b0000, 0b0000, 0b110), // RO
+ kTRCIDR9 = encode(0b10, 0b001, 0b0000, 0b0001, 0b110), // RO
+ kTRCIMSPEC0 = encode(0b10, 0b001, 0b0000, 0b0000, 0b111), // RW
+ kTRCIMSPEC1 = encode(0b10, 0b001, 0b0000, 0b0001, 0b111), // RW
+ kTRCIMSPEC2 = encode(0b10, 0b001, 0b0000, 0b0010, 0b111), // RW
+ kTRCIMSPEC3 = encode(0b10, 0b001, 0b0000, 0b0011, 0b111), // RW
+ kTRCIMSPEC4 = encode(0b10, 0b001, 0b0000, 0b0100, 0b111), // RW
+ kTRCIMSPEC5 = encode(0b10, 0b001, 0b0000, 0b0101, 0b111), // RW
+ kTRCIMSPEC6 = encode(0b10, 0b001, 0b0000, 0b0110, 0b111), // RW
+ kTRCIMSPEC7 = encode(0b10, 0b001, 0b0000, 0b0111, 0b111), // RW
+ kTRCITCTRL = encode(0b10, 0b001, 0b0111, 0b0000, 0b100), // RW
+ kTRCLAR = encode(0b10, 0b001, 0b0111, 0b1100, 0b110), // WO
+ kTRCLSR = encode(0b10, 0b001, 0b0111, 0b1101, 0b110), // RO
+ kTRCOSLAR = encode(0b10, 0b001, 0b0001, 0b0000, 0b100), // WO
+ kTRCOSLSR = encode(0b10, 0b001, 0b0001, 0b0001, 0b100), // RO
+ kTRCPDCR = encode(0b10, 0b001, 0b0001, 0b0100, 0b100), // RW
+ kTRCPDSR = encode(0b10, 0b001, 0b0001, 0b0101, 0b100), // RO
+ kTRCPIDR0 = encode(0b10, 0b001, 0b0111, 0b1000, 0b111), // RO
+ kTRCPIDR1 = encode(0b10, 0b001, 0b0111, 0b1001, 0b111), // RO
+ kTRCPIDR2 = encode(0b10, 0b001, 0b0111, 0b1010, 0b111), // RO
+ kTRCPIDR3 = encode(0b10, 0b001, 0b0111, 0b1011, 0b111), // RO
+ kTRCPIDR4 = encode(0b10, 0b001, 0b0111, 0b0100, 0b111), // RO
+ kTRCPIDR5 = encode(0b10, 0b001, 0b0111, 0b0101, 0b111), // RO
+ kTRCPIDR6 = encode(0b10, 0b001, 0b0111, 0b0110, 0b111), // RO
+ kTRCPIDR7 = encode(0b10, 0b001, 0b0111, 0b0111, 0b111), // RO
+ kTRCPRGCTLR = encode(0b10, 0b001, 0b0000, 0b0001, 0b000), // RW
+ kTRCPROCSELR = encode(0b10, 0b001, 0b0000, 0b0010, 0b000), // RW
+ kTRCQCTLR = encode(0b10, 0b001, 0b0000, 0b0001, 0b001), // RW
+ kTRCRSCTLR10 = encode(0b10, 0b001, 0b0001, 0b1010, 0b000), // RW
+ kTRCRSCTLR11 = encode(0b10, 0b001, 0b0001, 0b1011, 0b000), // RW
+ kTRCRSCTLR12 = encode(0b10, 0b001, 0b0001, 0b1100, 0b000), // RW
+ kTRCRSCTLR13 = encode(0b10, 0b001, 0b0001, 0b1101, 0b000), // RW
+ kTRCRSCTLR14 = encode(0b10, 0b001, 0b0001, 0b1110, 0b000), // RW
+ kTRCRSCTLR15 = encode(0b10, 0b001, 0b0001, 0b1111, 0b000), // RW
+ kTRCRSCTLR16 = encode(0b10, 0b001, 0b0001, 0b0000, 0b001), // RW
+ kTRCRSCTLR17 = encode(0b10, 0b001, 0b0001, 0b0001, 0b001), // RW
+ kTRCRSCTLR18 = encode(0b10, 0b001, 0b0001, 0b0010, 0b001), // RW
+ kTRCRSCTLR19 = encode(0b10, 0b001, 0b0001, 0b0011, 0b001), // RW
+ kTRCRSCTLR2 = encode(0b10, 0b001, 0b0001, 0b0010, 0b000), // RW
+ kTRCRSCTLR20 = encode(0b10, 0b001, 0b0001, 0b0100, 0b001), // RW
+ kTRCRSCTLR21 = encode(0b10, 0b001, 0b0001, 0b0101, 0b001), // RW
+ kTRCRSCTLR22 = encode(0b10, 0b001, 0b0001, 0b0110, 0b001), // RW
+ kTRCRSCTLR23 = encode(0b10, 0b001, 0b0001, 0b0111, 0b001), // RW
+ kTRCRSCTLR24 = encode(0b10, 0b001, 0b0001, 0b1000, 0b001), // RW
+ kTRCRSCTLR25 = encode(0b10, 0b001, 0b0001, 0b1001, 0b001), // RW
+ kTRCRSCTLR26 = encode(0b10, 0b001, 0b0001, 0b1010, 0b001), // RW
+ kTRCRSCTLR27 = encode(0b10, 0b001, 0b0001, 0b1011, 0b001), // RW
+ kTRCRSCTLR28 = encode(0b10, 0b001, 0b0001, 0b1100, 0b001), // RW
+ kTRCRSCTLR29 = encode(0b10, 0b001, 0b0001, 0b1101, 0b001), // RW
+ kTRCRSCTLR3 = encode(0b10, 0b001, 0b0001, 0b0011, 0b000), // RW
+ kTRCRSCTLR30 = encode(0b10, 0b001, 0b0001, 0b1110, 0b001), // RW
+ kTRCRSCTLR31 = encode(0b10, 0b001, 0b0001, 0b1111, 0b001), // RW
+ kTRCRSCTLR4 = encode(0b10, 0b001, 0b0001, 0b0100, 0b000), // RW
+ kTRCRSCTLR5 = encode(0b10, 0b001, 0b0001, 0b0101, 0b000), // RW
+ kTRCRSCTLR6 = encode(0b10, 0b001, 0b0001, 0b0110, 0b000), // RW
+ kTRCRSCTLR7 = encode(0b10, 0b001, 0b0001, 0b0111, 0b000), // RW
+ kTRCRSCTLR8 = encode(0b10, 0b001, 0b0001, 0b1000, 0b000), // RW
+ kTRCRSCTLR9 = encode(0b10, 0b001, 0b0001, 0b1001, 0b000), // RW
+ kTRCRSR = encode(0b10, 0b001, 0b0000, 0b1010, 0b000), // RW
+ kTRCSEQEVR0 = encode(0b10, 0b001, 0b0000, 0b0000, 0b100), // RW
+ kTRCSEQEVR1 = encode(0b10, 0b001, 0b0000, 0b0001, 0b100), // RW
+ kTRCSEQEVR2 = encode(0b10, 0b001, 0b0000, 0b0010, 0b100), // RW
+ kTRCSEQRSTEVR = encode(0b10, 0b001, 0b0000, 0b0110, 0b100), // RW
+ kTRCSEQSTR = encode(0b10, 0b001, 0b0000, 0b0111, 0b100), // RW
+ kTRCSSCCR0 = encode(0b10, 0b001, 0b0001, 0b0000, 0b010), // RW
+ kTRCSSCCR1 = encode(0b10, 0b001, 0b0001, 0b0001, 0b010), // RW
+ kTRCSSCCR2 = encode(0b10, 0b001, 0b0001, 0b0010, 0b010), // RW
+ kTRCSSCCR3 = encode(0b10, 0b001, 0b0001, 0b0011, 0b010), // RW
+ kTRCSSCCR4 = encode(0b10, 0b001, 0b0001, 0b0100, 0b010), // RW
+ kTRCSSCCR5 = encode(0b10, 0b001, 0b0001, 0b0101, 0b010), // RW
+ kTRCSSCCR6 = encode(0b10, 0b001, 0b0001, 0b0110, 0b010), // RW
+ kTRCSSCCR7 = encode(0b10, 0b001, 0b0001, 0b0111, 0b010), // RW
+ kTRCSSCSR0 = encode(0b10, 0b001, 0b0001, 0b1000, 0b010), // RW
+ kTRCSSCSR1 = encode(0b10, 0b001, 0b0001, 0b1001, 0b010), // RW
+ kTRCSSCSR2 = encode(0b10, 0b001, 0b0001, 0b1010, 0b010), // RW
+ kTRCSSCSR3 = encode(0b10, 0b001, 0b0001, 0b1011, 0b010), // RW
+ kTRCSSCSR4 = encode(0b10, 0b001, 0b0001, 0b1100, 0b010), // RW
+ kTRCSSCSR5 = encode(0b10, 0b001, 0b0001, 0b1101, 0b010), // RW
+ kTRCSSCSR6 = encode(0b10, 0b001, 0b0001, 0b1110, 0b010), // RW
+ kTRCSSCSR7 = encode(0b10, 0b001, 0b0001, 0b1111, 0b010), // RW
+ kTRCSSPCICR0 = encode(0b10, 0b001, 0b0001, 0b0000, 0b011), // RW
+ kTRCSSPCICR1 = encode(0b10, 0b001, 0b0001, 0b0001, 0b011), // RW
+ kTRCSSPCICR2 = encode(0b10, 0b001, 0b0001, 0b0010, 0b011), // RW
+ kTRCSSPCICR3 = encode(0b10, 0b001, 0b0001, 0b0011, 0b011), // RW
+ kTRCSSPCICR4 = encode(0b10, 0b001, 0b0001, 0b0100, 0b011), // RW
+ kTRCSSPCICR5 = encode(0b10, 0b001, 0b0001, 0b0101, 0b011), // RW
+ kTRCSSPCICR6 = encode(0b10, 0b001, 0b0001, 0b0110, 0b011), // RW
+ kTRCSSPCICR7 = encode(0b10, 0b001, 0b0001, 0b0111, 0b011), // RW
+ kTRCSTALLCTLR = encode(0b10, 0b001, 0b0000, 0b1011, 0b000), // RW
+ kTRCSTATR = encode(0b10, 0b001, 0b0000, 0b0011, 0b000), // RO
+ kTRCSYNCPR = encode(0b10, 0b001, 0b0000, 0b1101, 0b000), // RW
+ kTRCTRACEIDR = encode(0b10, 0b001, 0b0000, 0b0000, 0b001), // RW
+ kTRCTSCTLR = encode(0b10, 0b001, 0b0000, 0b1100, 0b000), // RW
+ kTRCVDARCCTLR = encode(0b10, 0b001, 0b0000, 0b1010, 0b010), // RW
+ kTRCVDCTLR = encode(0b10, 0b001, 0b0000, 0b1000, 0b010), // RW
+ kTRCVDSACCTLR = encode(0b10, 0b001, 0b0000, 0b1001, 0b010), // RW
+ kTRCVICTLR = encode(0b10, 0b001, 0b0000, 0b0000, 0b010), // RW
+ kTRCVIIECTLR = encode(0b10, 0b001, 0b0000, 0b0001, 0b010), // RW
+ kTRCVIPCSSCTLR = encode(0b10, 0b001, 0b0000, 0b0011, 0b010), // RW
+ kTRCVISSCTLR = encode(0b10, 0b001, 0b0000, 0b0010, 0b010), // RW
+ kTRCVMIDCCTLR0 = encode(0b10, 0b001, 0b0011, 0b0010, 0b010), // RW
+ kTRCVMIDCCTLR1 = encode(0b10, 0b001, 0b0011, 0b0011, 0b010), // RW
+ kTRCVMIDCVR0 = encode(0b10, 0b001, 0b0011, 0b0000, 0b001), // RW
+ kTRCVMIDCVR1 = encode(0b10, 0b001, 0b0011, 0b0010, 0b001), // RW
+ kTRCVMIDCVR2 = encode(0b10, 0b001, 0b0011, 0b0100, 0b001), // RW
+ kTRCVMIDCVR3 = encode(0b10, 0b001, 0b0011, 0b0110, 0b001), // RW
+ kTRCVMIDCVR4 = encode(0b10, 0b001, 0b0011, 0b1000, 0b001), // RW
+ kTRCVMIDCVR5 = encode(0b10, 0b001, 0b0011, 0b1010, 0b001), // RW
+ kTRCVMIDCVR6 = encode(0b10, 0b001, 0b0011, 0b1100, 0b001), // RW
+ kTRCVMIDCVR7 = encode(0b10, 0b001, 0b0011, 0b1110, 0b001), // RW
+ kTRFCR_EL1 = encode(0b11, 0b000, 0b0001, 0b0010, 0b001), // RW
+ kTRFCR_EL12 = encode(0b11, 0b101, 0b0001, 0b0010, 0b001), // RW
+ kTRFCR_EL2 = encode(0b11, 0b100, 0b0001, 0b0010, 0b001), // RW
+ kTTBR0_EL1 = encode(0b11, 0b000, 0b0010, 0b0000, 0b000), // RW
+ kTTBR0_EL12 = encode(0b11, 0b101, 0b0010, 0b0000, 0b000), // RW
+ kTTBR0_EL2 = encode(0b11, 0b100, 0b0010, 0b0000, 0b000), // RW
+ kTTBR0_EL3 = encode(0b11, 0b110, 0b0010, 0b0000, 0b000), // RW
+ kTTBR1_EL1 = encode(0b11, 0b000, 0b0010, 0b0000, 0b001), // RW
+ kTTBR1_EL12 = encode(0b11, 0b101, 0b0010, 0b0000, 0b001), // RW
+ kTTBR1_EL2 = encode(0b11, 0b100, 0b0010, 0b0000, 0b001), // RW
+ kUAO = encode(0b11, 0b000, 0b0100, 0b0010, 0b100), // RW
+ kVBAR_EL1 = encode(0b11, 0b000, 0b1100, 0b0000, 0b000), // RW
+ kVBAR_EL12 = encode(0b11, 0b101, 0b1100, 0b0000, 0b000), // RW
+ kVBAR_EL2 = encode(0b11, 0b100, 0b1100, 0b0000, 0b000), // RW
+ kVBAR_EL3 = encode(0b11, 0b110, 0b1100, 0b0000, 0b000), // RW
+ kVDISR_EL2 = encode(0b11, 0b100, 0b1100, 0b0001, 0b001), // RW
+ kVMPIDR_EL2 = encode(0b11, 0b100, 0b0000, 0b0000, 0b101), // RW
+ kVNCR_EL2 = encode(0b11, 0b100, 0b0010, 0b0010, 0b000), // RW
+ kVPIDR_EL2 = encode(0b11, 0b100, 0b0000, 0b0000, 0b000), // RW
+ kVSESR_EL2 = encode(0b11, 0b100, 0b0101, 0b0010, 0b011), // RW
+ kVSTCR_EL2 = encode(0b11, 0b100, 0b0010, 0b0110, 0b010), // RW
+ kVSTTBR_EL2 = encode(0b11, 0b100, 0b0010, 0b0110, 0b000), // RW
+ kVTCR_EL2 = encode(0b11, 0b100, 0b0010, 0b0001, 0b010), // RW
+ kVTTBR_EL2 = encode(0b11, 0b100, 0b0010, 0b0001, 0b000), // RW
+ kZCR_EL1 = encode(0b11, 0b000, 0b0001, 0b0010, 0b000), // RW
+ kZCR_EL12 = encode(0b11, 0b101, 0b0001, 0b0010, 0b000), // RW
+ kZCR_EL2 = encode(0b11, 0b100, 0b0001, 0b0010, 0b000), // RW
+ kZCR_EL3 = encode(0b11, 0b110, 0b0001, 0b0010, 0b000) // RW
+ };
+};
+
+} // {Predicate}
+
+//! \}
+
+ASMJIT_END_SUB_NAMESPACE
+
+#endif // ASMJIT_ARM_A64GLOBALS_H_INCLUDED
diff --git a/3rdparty/asmjit/src/asmjit/arm/a64instapi.cpp b/3rdparty/asmjit/src/asmjit/arm/a64instapi.cpp
new file mode 100644
index 00000000000..dc98bc8f73c
--- /dev/null
+++ b/3rdparty/asmjit/src/asmjit/arm/a64instapi.cpp
@@ -0,0 +1,278 @@
+// This file is part of AsmJit project <https://asmjit.com>
+//
+// See asmjit.h or LICENSE.md for license and copyright information
+// SPDX-License-Identifier: Zlib
+
+#include "../core/api-build_p.h"
+#if !defined(ASMJIT_NO_AARCH64)
+
+#include "../core/cpuinfo.h"
+#include "../core/misc_p.h"
+#include "../core/support.h"
+#include "../arm/a64instapi_p.h"
+#include "../arm/a64instdb_p.h"
+#include "../arm/a64operand.h"
+
+ASMJIT_BEGIN_SUB_NAMESPACE(a64)
+
+// a64::InstInternal - Text
+// ========================
+
+#ifndef ASMJIT_NO_TEXT
+Error InstInternal::instIdToString(Arch arch, InstId instId, String& output) noexcept {
+ uint32_t realId = instId & uint32_t(InstIdParts::kRealId);
+ DebugUtils::unused(arch);
+
+ if (ASMJIT_UNLIKELY(!Inst::isDefinedId(realId)))
+ return DebugUtils::errored(kErrorInvalidInstruction);
+
+ const InstDB::InstInfo& info = InstDB::infoById(realId);
+ return output.append(InstDB::_nameData + info._nameDataIndex);
+}
+
+InstId InstInternal::stringToInstId(Arch arch, const char* s, size_t len) noexcept {
+ DebugUtils::unused(arch);
+
+ if (ASMJIT_UNLIKELY(!s))
+ return Inst::kIdNone;
+
+ if (len == SIZE_MAX)
+ len = strlen(s);
+
+ if (ASMJIT_UNLIKELY(len == 0 || len > InstDB::kMaxNameSize))
+ return Inst::kIdNone;
+
+ uint32_t prefix = uint32_t(s[0]) - 'a';
+ if (ASMJIT_UNLIKELY(prefix > 'z' - 'a'))
+ return Inst::kIdNone;
+
+ uint32_t index = InstDB::instNameIndex[prefix].start;
+ if (ASMJIT_UNLIKELY(!index))
+ return Inst::kIdNone;
+
+ const char* nameData = InstDB::_nameData;
+ const InstDB::InstInfo* table = InstDB::_instInfoTable;
+
+ const InstDB::InstInfo* base = table + index;
+ const InstDB::InstInfo* end = table + InstDB::instNameIndex[prefix].end;
+
+ for (size_t lim = (size_t)(end - base); lim != 0; lim >>= 1) {
+ const InstDB::InstInfo* cur = base + (lim >> 1);
+ int result = Support::cmpInstName(nameData + cur[0]._nameDataIndex, s, len);
+
+ if (result < 0) {
+ base = cur + 1;
+ lim--;
+ continue;
+ }
+
+ if (result > 0)
+ continue;
+
+ return uint32_t((size_t)(cur - table));
+ }
+
+ return Inst::kIdNone;
+}
+#endif // !ASMJIT_NO_TEXT
+
+// a64::InstInternal - Validate
+// ============================
+
+#ifndef ASMJIT_NO_VALIDATION
+ASMJIT_FAVOR_SIZE Error InstInternal::validate(Arch arch, const BaseInst& inst, const Operand_* operands, size_t opCount, ValidationFlags validationFlags) noexcept {
+ // TODO:
+ DebugUtils::unused(arch, inst, operands, opCount, validationFlags);
+ return kErrorOk;
+}
+#endif // !ASMJIT_NO_VALIDATION
+
+// a64::InstInternal - QueryRWInfo
+// ===============================
+
+#ifndef ASMJIT_NO_INTROSPECTION
+struct InstRWInfoData {
+ uint8_t rwx[Globals::kMaxOpCount];
+};
+
+static const InstRWInfoData instRWInfoData[] = {
+ #define R uint8_t(OpRWFlags::kRead)
+ #define W uint8_t(OpRWFlags::kWrite)
+ #define X uint8_t(OpRWFlags::kRW)
+
+ {{ R, R, R, R, R, R }}, // kRWI_R
+ {{ R, W, R, R, R, R }}, // kRWI_RW
+ {{ R, X, R, R, R, R }}, // kRWI_RX
+ {{ R, R, W, R, R, R }}, // kRWI_RRW
+ {{ R, W, X, R, R, R }}, // kRWI_RWX
+ {{ W, R, R, R, R, R }}, // kRWI_W
+ {{ W, R, W, R, R, R }}, // kRWI_WRW
+ {{ W, R, X, R, R, R }}, // kRWI_WRX
+ {{ W, R, R, W, R, R }}, // kRWI_WRRW
+ {{ W, R, R, X, R, R }}, // kRWI_WRRX
+ {{ W, W, R, R, R, R }}, // kRWI_WW
+ {{ X, R, R, R, R, R }}, // kRWI_X
+ {{ X, R, X, R, R, R }}, // kRWI_XRX
+ {{ X, X, R, R, X, R }}, // kRWI_XXRRX
+
+ {{ W, R, R, R, R, R }}, // kRWI_LDn
+ {{ R, W, R, R, R, R }}, // kRWI_STn
+ {{ R, R, R, R, R, R }} // kRWI_TODO
+
+ #undef R
+ #undef W
+ #undef X
+};
+
+static const uint8_t elementTypeSize[8] = { 0, 1, 2, 4, 8, 4, 4, 0 };
+
+Error InstInternal::queryRWInfo(Arch arch, const BaseInst& inst, const Operand_* operands, size_t opCount, InstRWInfo* out) noexcept {
+ // Unused in Release configuration as the assert is not compiled in.
+ DebugUtils::unused(arch);
+
+ // Only called when `arch` matches X86 family.
+ ASMJIT_ASSERT(Environment::isFamilyARM(arch));
+
+ // Get the instruction data.
+ uint32_t realId = inst.id() & uint32_t(InstIdParts::kRealId);
+
+ if (ASMJIT_UNLIKELY(!Inst::isDefinedId(realId)))
+ return DebugUtils::errored(kErrorInvalidInstruction);
+
+ out->_instFlags = 0;
+ out->_opCount = uint8_t(opCount);
+ out->_rmFeature = 0;
+ out->_extraReg.reset();
+ out->_readFlags = CpuRWFlags::kNone; // TODO: [ARM] Read PSTATUS.
+ out->_writeFlags = CpuRWFlags::kNone; // TODO: [ARM] Write PSTATUS
+
+ const InstDB::InstInfo& instInfo = InstDB::_instInfoTable[realId];
+ const InstRWInfoData& rwInfo = instRWInfoData[instInfo.rwInfoIndex()];
+
+ if (instInfo.hasFlag(InstDB::kInstFlagConsecutive) && opCount > 2) {
+ for (uint32_t i = 0; i < opCount; i++) {
+ OpRWInfo& op = out->_operands[i];
+ const Operand_& srcOp = operands[i];
+
+ if (!srcOp.isRegOrMem()) {
+ op.reset();
+ continue;
+ }
+
+ OpRWFlags rwFlags = i < opCount - 1 ? (OpRWFlags)rwInfo.rwx[0] : (OpRWFlags)rwInfo.rwx[1];
+
+ op._opFlags = rwFlags & ~(OpRWFlags::kZExt);
+ op._physId = BaseReg::kIdBad;
+ op._rmSize = 0;
+ op._resetReserved();
+
+ uint64_t rByteMask = op.isRead() ? 0xFFFFFFFFFFFFFFFFu : 0x0000000000000000u;
+ uint64_t wByteMask = op.isWrite() ? 0xFFFFFFFFFFFFFFFFu : 0x0000000000000000u;
+
+ op._readByteMask = rByteMask;
+ op._writeByteMask = wByteMask;
+ op._extendByteMask = 0;
+ op._consecutiveLeadCount = 0;
+
+ if (srcOp.isReg()) {
+ if (i == 0)
+ op._consecutiveLeadCount = uint8_t(opCount - 1);
+ else
+ op.addOpFlags(OpRWFlags::kConsecutive);
+ }
+ else {
+ const Mem& memOp = srcOp.as<Mem>();
+
+ if (memOp.hasBase()) {
+ op.addOpFlags(OpRWFlags::kMemBaseRead);
+ }
+
+ if (memOp.hasIndex()) {
+ op.addOpFlags(OpRWFlags::kMemIndexRead);
+ op.addOpFlags(memOp.isPreOrPost() ? OpRWFlags::kMemIndexWrite : OpRWFlags::kNone);
+ }
+ }
+ }
+ }
+ else {
+ for (uint32_t i = 0; i < opCount; i++) {
+ OpRWInfo& op = out->_operands[i];
+ const Operand_& srcOp = operands[i];
+
+ if (!srcOp.isRegOrMem()) {
+ op.reset();
+ continue;
+ }
+
+ OpRWFlags rwFlags = (OpRWFlags)rwInfo.rwx[i];
+
+ op._opFlags = rwFlags & ~(OpRWFlags::kZExt);
+ op._physId = BaseReg::kIdBad;
+ op._rmSize = 0;
+ op._resetReserved();
+
+ uint64_t rByteMask = op.isRead() ? 0xFFFFFFFFFFFFFFFFu : 0x0000000000000000u;
+ uint64_t wByteMask = op.isWrite() ? 0xFFFFFFFFFFFFFFFFu : 0x0000000000000000u;
+
+ op._readByteMask = rByteMask;
+ op._writeByteMask = wByteMask;
+ op._extendByteMask = 0;
+ op._consecutiveLeadCount = 0;
+
+ if (srcOp.isReg()) {
+ if (srcOp.as<Vec>().hasElementIndex()) {
+ // Only part of the vector is accessed if element index [] is used.
+ uint32_t elementType = srcOp.as<Vec>().elementType();
+ uint32_t elementIndex = srcOp.as<Vec>().elementIndex();
+
+ uint32_t elementSize = elementTypeSize[elementType];
+ uint64_t accessMask = uint64_t(Support::lsbMask<uint32_t>(elementSize)) << (elementIndex * elementSize);
+
+ op._readByteMask &= accessMask;
+ op._writeByteMask &= accessMask;
+ }
+
+ // TODO: [ARM] RW info is not finished.
+ }
+ else {
+ const Mem& memOp = srcOp.as<Mem>();
+
+ if (memOp.hasBase()) {
+ op.addOpFlags(OpRWFlags::kMemBaseRead);
+ }
+
+ if (memOp.hasIndex()) {
+ op.addOpFlags(OpRWFlags::kMemIndexRead);
+ op.addOpFlags(memOp.isPreOrPost() ? OpRWFlags::kMemIndexWrite : OpRWFlags::kNone);
+ }
+ }
+ }
+ }
+
+ return kErrorOk;
+}
+#endif // !ASMJIT_NO_INTROSPECTION
+
+// a64::InstInternal - QueryFeatures
+// =================================
+
+#ifndef ASMJIT_NO_INTROSPECTION
+Error InstInternal::queryFeatures(Arch arch, const BaseInst& inst, const Operand_* operands, size_t opCount, CpuFeatures* out) noexcept {
+ // TODO: [ARM] QueryFeatures not implemented yet.
+ DebugUtils::unused(arch, inst, operands, opCount, out);
+ return kErrorOk;
+}
+#endif // !ASMJIT_NO_INTROSPECTION
+
+// a64::InstInternal - Unit
+// ========================
+
+#if defined(ASMJIT_TEST)
+UNIT(arm_inst_api_text) {
+ // TODO:
+}
+#endif
+
+ASMJIT_END_SUB_NAMESPACE
+
+#endif // !ASMJIT_NO_AARCH64
diff --git a/3rdparty/asmjit/src/asmjit/arm/a64instapi_p.h b/3rdparty/asmjit/src/asmjit/arm/a64instapi_p.h
new file mode 100644
index 00000000000..320a3e881d9
--- /dev/null
+++ b/3rdparty/asmjit/src/asmjit/arm/a64instapi_p.h
@@ -0,0 +1,41 @@
+// This file is part of AsmJit project <https://asmjit.com>
+//
+// See asmjit.h or LICENSE.md for license and copyright information
+// SPDX-License-Identifier: Zlib
+
+#ifndef ASMJIT_ARM_A64INSTAPI_P_H_INCLUDED
+#define ASMJIT_ARM_A64INSTAPI_P_H_INCLUDED
+
+#include "../core/inst.h"
+#include "../core/operand.h"
+
+ASMJIT_BEGIN_SUB_NAMESPACE(a64)
+
+//! \cond INTERNAL
+//! \addtogroup asmjit_a64
+//! \{
+
+namespace InstInternal {
+
+#ifndef ASMJIT_NO_TEXT
+Error ASMJIT_CDECL instIdToString(Arch arch, InstId instId, String& output) noexcept;
+InstId ASMJIT_CDECL stringToInstId(Arch arch, const char* s, size_t len) noexcept;
+#endif // !ASMJIT_NO_TEXT
+
+#ifndef ASMJIT_NO_VALIDATION
+Error ASMJIT_CDECL validate(Arch arch, const BaseInst& inst, const Operand_* operands, size_t opCount, ValidationFlags validationFlags) noexcept;
+#endif // !ASMJIT_NO_VALIDATION
+
+#ifndef ASMJIT_NO_INTROSPECTION
+Error ASMJIT_CDECL queryRWInfo(Arch arch, const BaseInst& inst, const Operand_* operands, size_t opCount, InstRWInfo* out) noexcept;
+Error ASMJIT_CDECL queryFeatures(Arch arch, const BaseInst& inst, const Operand_* operands, size_t opCount, CpuFeatures* out) noexcept;
+#endif // !ASMJIT_NO_INTROSPECTION
+
+} // {InstInternal}
+
+//! \}
+//! \endcond
+
+ASMJIT_END_SUB_NAMESPACE
+
+#endif // ASMJIT_ARM_A64INSTAPI_P_H_INCLUDED
diff --git a/3rdparty/asmjit/src/asmjit/arm/a64instdb.cpp b/3rdparty/asmjit/src/asmjit/arm/a64instdb.cpp
new file mode 100644
index 00000000000..64709b5db03
--- /dev/null
+++ b/3rdparty/asmjit/src/asmjit/arm/a64instdb.cpp
@@ -0,0 +1,1957 @@
+// This file is part of AsmJit project <https://asmjit.com>
+//
+// See asmjit.h or LICENSE.md for license and copyright information
+// SPDX-License-Identifier: Zlib
+
+#include "../core/api-build_p.h"
+#if !defined(ASMJIT_NO_AARCH64)
+
+#include "../core/codeholder.h"
+#include "../core/support.h"
+#include "../arm/a64instdb_p.h"
+#include "../arm/a64operand.h"
+
+ASMJIT_BEGIN_SUB_NAMESPACE(a64)
+
+namespace InstDB {
+
+// a64::InstDB - InstInfoTable
+// ===========================
+
+// Don't store `_nameDataIndex` if instruction names are disabled. Since some
+// APIs can use `_nameDataIndex` it's much safer if it's zero if it's not used.
+#if defined(ASMJIT_NO_TEXT)
+ #define NAME_DATA_INDEX(x) 0
+#else
+ #define NAME_DATA_INDEX(x) x
+#endif
+
+// Defines an ARM/AArch64 instruction.
+#define INST(id, opcodeEncoding, opcodeData, rwInfoIndex, flags, opcodeDataIndex, nameDataIndex) { \
+ uint32_t(kEncoding##opcodeEncoding), \
+ uint32_t(opcodeDataIndex), \
+ 0, \
+ uint32_t(NAME_DATA_INDEX(nameDataIndex)), \
+ uint16_t(rwInfoIndex), \
+ uint16_t(flags) \
+}
+
+#define F(flag) kInstFlag##flag
+
+// TODO: [ARM] Missing Instructions:
+/*
+BLRAA, BLRAAZ, BLRAB, BLRABZ: Branch with Link to Register, with pointer authentication.
+BRAA, BRAAZ, BRAB, BRABZ: Branch to Register, with pointer authentication.
+
+CFP: Control Flow Prediction Restriction by Context: an alias of SYS.
+CPP: Cache Prefetch Prediction Restriction by Context: an alias of SYS.
+DVP: Data Value Prediction Restriction by Context: an alias of SYS.
+PSB CSYNC: Profiling Synchronization Barrier.
+
+ERETAA, ERETAB: Exception Return, with pointer authentication.
+LDAPxxx
+PACIA, PACIA1716, PACIASP, PACIAZ, PACIZA: Pointer Authentication Code for Instruction address, using key A.
+PACIB, PACIB1716, PACIBSP, PACIBZ, PACIZB: Pointer Authentication Code for Instruction address, using key B.
+PRFM (immediate): Prefetch Memory (immediate).
+PRFM (literal): Prefetch Memory (literal).
+PRFM (register): Prefetch Memory (register).
+PRFUM: Prefetch Memory (unscaled offset).
+RETAA, RETAB: Return from subroutine, with pointer authentication.
+RMIF: Rotate, Mask Insert Flags.
+SYSL
+IRG: Insert Random Tag.
+INST_(Irg , BaseRRR , (0b1001101011000000000100, kX , kSP, kX , kSP, kX , kZR, true) , kRWI_W , 0 , 0 , 1 ), // #1
+*/
+const InstInfo _instInfoTable[] = {
+ // +------------------+---------------------+--------------------------------------------------------------------------------------+-----------+---------------------------+----+-----+
+ // | Instruction Id | Encoding | Opcode Data | RW Info | Instruction Flags |DatX|NameX|
+ // +------------------+---------------------+--------------------------------------------------------------------------------------+-----------+---------------------------+----+-----+
+ // ${InstInfo:Begin}
+ INST(None , None , (_) , 0 , 0 , 0 , 0 ), // #0
+ INST(Adc , BaseRRR , (0b0001101000000000000000, kWX, kZR, kWX, kZR, kWX, kZR, true) , kRWI_W , 0 , 0 , 1 ), // #1
+ INST(Adcs , BaseRRR , (0b0011101000000000000000, kWX, kZR, kWX, kZR, kWX, kZR, true) , kRWI_W , 0 , 1 , 5 ), // #2
+ INST(Add , BaseAddSub , (0b0001011000, 0b0001011001, 0b0010001) , kRWI_W , 0 , 0 , 978 ), // #3
+ INST(Addg , BaseRRII , (0b1001000110000000000000, kX, kSP, kX, kSP, 6, 4, 16, 4, 0, 10) , kRWI_W , 0 , 0 , 10 ), // #4
+ INST(Adds , BaseAddSub , (0b0101011000, 0b0101011001, 0b0110001) , kRWI_W , 0 , 1 , 15 ), // #5
+ INST(Adr , BaseAdr , (0b0001000000000000000000, OffsetType::kAArch64_ADR) , kRWI_W , 0 , 0 , 25 ), // #6
+ INST(Adrp , BaseAdr , (0b1001000000000000000000, OffsetType::kAArch64_ADRP) , kRWI_W , 0 , 1 , 29 ), // #7
+ INST(And , BaseLogical , (0b0001010000, 0b00100100, 0) , kRWI_W , 0 , 0 , 57 ), // #8
+ INST(Ands , BaseLogical , (0b1101010000, 0b11100100, 0) , kRWI_W , 0 , 1 , 61 ), // #9
+ INST(Asr , BaseShift , (0b0001101011000000001010, 0b0001001100000000011111, 0) , kRWI_W , 0 , 0 , 66 ), // #10
+ INST(Asrv , BaseShift , (0b0001101011000000001010, 0b0000000000000000000000, 0) , kRWI_W , 0 , 1 , 70 ), // #11
+ INST(At , BaseAtDcIcTlbi , (0b00011111110000, 0b00001111000000, true) , kRWI_RX , 0 , 0 , 75 ), // #12
+ INST(Autda , BaseRR , (0b11011010110000010001100000000000, kX, kZR, 0, kX, kSP, 5, true) , kRWI_X , 0 , 0 , 78 ), // #13
+ INST(Autdza , BaseR , (0b11011010110000010011101111100000, kX, kZR, 0) , kRWI_X , 0 , 0 , 90 ), // #14
+ INST(Autdb , BaseRR , (0b11011010110000010001110000000000, kX, kZR, 0, kX, kSP, 5, true) , kRWI_X , 0 , 1 , 84 ), // #15
+ INST(Autdzb , BaseR , (0b11011010110000010011111111100000, kX, kZR, 0) , kRWI_X , 0 , 1 , 97 ), // #16
+ INST(Autia , BaseRR , (0b11011010110000010001000000000000, kX, kZR, 0, kX, kSP, 5, true) , kRWI_X , 0 , 2 , 104 ), // #17
+ INST(Autia1716 , BaseOp , (0b11010101000000110010000110011111) , 0 , 0 , 0 , 110 ), // #18
+ INST(Autiasp , BaseOp , (0b11010101000000110010001110111111) , 0 , 0 , 1 , 120 ), // #19
+ INST(Autiaz , BaseOp , (0b11010101000000110010001110011111) , 0 , 0 , 2 , 128 ), // #20
+ INST(Autib , BaseRR , (0b11011010110000010001010000000000, kX, kZR, 0, kX, kSP, 5, true) , kRWI_X , 0 , 3 , 135 ), // #21
+ INST(Autib1716 , BaseOp , (0b11010101000000110010000111011111) , 0 , 0 , 3 , 141 ), // #22
+ INST(Autibsp , BaseOp , (0b11010101000000110010001111111111) , 0 , 0 , 4 , 151 ), // #23
+ INST(Autibz , BaseOp , (0b11010101000000110010001111011111) , 0 , 0 , 5 , 159 ), // #24
+ INST(Autiza , BaseR , (0b11011010110000010011001111100000, kX, kZR, 0) , kRWI_X , 0 , 2 , 166 ), // #25
+ INST(Autizb , BaseR , (0b11011010110000010011011111100000, kX, kZR, 0) , kRWI_X , 0 , 3 , 173 ), // #26
+ INST(Axflag , BaseOp , (0b11010101000000000100000001011111) , 0 , 0 , 6 , 180 ), // #27
+ INST(B , BaseBranchRel , (0b00010100000000000000000000000000) , 0 , F(Cond) , 0 , 1738), // #28
+ INST(Bfc , BaseBfc , (0b00110011000000000000001111100000) , kRWI_X , 0 , 0 , 192 ), // #29
+ INST(Bfi , BaseBfi , (0b00110011000000000000000000000000) , kRWI_X , 0 , 0 , 223 ), // #30
+ INST(Bfm , BaseBfm , (0b00110011000000000000000000000000) , kRWI_X , 0 , 0 , 2514), // #31
+ INST(Bfxil , BaseBfx , (0b00110011000000000000000000000000) , kRWI_X , 0 , 0 , 250 ), // #32
+ INST(Bic , BaseLogical , (0b0001010001, 0b00100100, 1) , kRWI_W , 0 , 2 , 256 ), // #33
+ INST(Bics , BaseLogical , (0b1101010001, 0b11100100, 1) , kRWI_W , 0 , 3 , 260 ), // #34
+ INST(Bl , BaseBranchRel , (0b10010100000000000000000000000000) , 0 , 0 , 1 , 2831), // #35
+ INST(Blr , BaseBranchReg , (0b11010110001111110000000000000000) , kRWI_R , 0 , 0 , 269 ), // #36
+ INST(Br , BaseBranchReg , (0b11010110000111110000000000000000) , kRWI_R , 0 , 1 , 273 ), // #37
+ INST(Brk , BaseOpImm , (0b11010100001000000000000000000000, 16, 5) , 0 , 0 , 0 , 276 ), // #38
+ INST(Cas , BaseAtomicOp , (0b1000100010100000011111, kWX, 30, 0) , kRWI_XRX , 0 , 0 , 284 ), // #39
+ INST(Casa , BaseAtomicOp , (0b1000100011100000011111, kWX, 30, 1) , kRWI_XRX , 0 , 1 , 288 ), // #40
+ INST(Casab , BaseAtomicOp , (0b0000100011100000011111, kW , 0 , 1) , kRWI_XRX , 0 , 2 , 293 ), // #41
+ INST(Casah , BaseAtomicOp , (0b0100100011100000011111, kW , 0 , 1) , kRWI_XRX , 0 , 3 , 299 ), // #42
+ INST(Casal , BaseAtomicOp , (0b1000100011100000111111, kWX, 30, 1) , kRWI_XRX , 0 , 4 , 305 ), // #43
+ INST(Casalb , BaseAtomicOp , (0b0000100011100000111111, kW , 0 , 1) , kRWI_XRX , 0 , 5 , 311 ), // #44
+ INST(Casalh , BaseAtomicOp , (0b0100100011100000111111, kW , 0 , 1) , kRWI_XRX , 0 , 6 , 318 ), // #45
+ INST(Casb , BaseAtomicOp , (0b0000100010100000011111, kW , 0 , 0) , kRWI_XRX , 0 , 7 , 325 ), // #46
+ INST(Cash , BaseAtomicOp , (0b0100100010100000011111, kW , 0 , 0) , kRWI_XRX , 0 , 8 , 330 ), // #47
+ INST(Casl , BaseAtomicOp , (0b1000100010100000111111, kWX, 30, 0) , kRWI_XRX , 0 , 9 , 335 ), // #48
+ INST(Caslb , BaseAtomicOp , (0b0000100010100000111111, kW , 0 , 0) , kRWI_XRX , 0 , 10 , 340 ), // #49
+ INST(Caslh , BaseAtomicOp , (0b0100100010100000111111, kW , 0 , 0) , kRWI_XRX , 0 , 11 , 346 ), // #50
+ INST(Casp , BaseAtomicCasp , (0b0000100000100000011111, kWX, 30) , kRWI_XXRRX, 0 , 0 , 352 ), // #51
+ INST(Caspa , BaseAtomicCasp , (0b0000100001100000011111, kWX, 30) , kRWI_XXRRX, 0 , 1 , 357 ), // #52
+ INST(Caspal , BaseAtomicCasp , (0b0000100001100000111111, kWX, 30) , kRWI_XXRRX, 0 , 2 , 363 ), // #53
+ INST(Caspl , BaseAtomicCasp , (0b0000100000100000111111, kWX, 30) , kRWI_XXRRX, 0 , 3 , 370 ), // #54
+ INST(Cbnz , BaseBranchCmp , (0b00110101000000000000000000000000) , kRWI_R , 0 , 0 , 376 ), // #55
+ INST(Cbz , BaseBranchCmp , (0b00110100000000000000000000000000) , kRWI_R , 0 , 1 , 381 ), // #56
+ INST(Ccmn , BaseCCmp , (0b00111010010000000000000000000000) , kRWI_R , 0 , 0 , 385 ), // #57
+ INST(Ccmp , BaseCCmp , (0b01111010010000000000000000000000) , kRWI_R , 0 , 1 , 650 ), // #58
+ INST(Cfinv , BaseOp , (0b11010101000000000100000000011111) , 0 , 0 , 7 , 390 ), // #59
+ INST(Cinc , BaseCInc , (0b00011010100000000000010000000000) , kRWI_W , 0 , 0 , 396 ), // #60
+ INST(Cinv , BaseCInc , (0b01011010100000000000000000000000) , kRWI_W , 0 , 1 , 401 ), // #61
+ INST(Clrex , BaseOpImm , (0b11010101000000110011000001011111, 4, 8) , 0 , 0 , 1 , 406 ), // #62
+ INST(Cls , BaseRR , (0b01011010110000000001010000000000, kWX, kZR, 0, kWX, kZR, 5, true) , kRWI_W , 0 , 4 , 412 ), // #63
+ INST(Clz , BaseRR , (0b01011010110000000001000000000000, kWX, kZR, 0, kWX, kZR, 5, true) , kRWI_W , 0 , 5 , 416 ), // #64
+ INST(Cmn , BaseCmpCmn , (0b0101011000, 0b0101011001, 0b0110001) , kRWI_R , 0 , 0 , 386 ), // #65
+ INST(Cmp , BaseCmpCmn , (0b1101011000, 0b1101011001, 0b1110001) , kRWI_R , 0 , 1 , 651 ), // #66
+ INST(Cmpp , BaseRR , (0b10111010110000000000000000011111, kX, kSP, 5, kX, kSP, 16, true) , kRWI_R , 0 , 6 , 430 ), // #67
+ INST(Cneg , BaseCInc , (0b01011010100000000000010000000000) , kRWI_W , 0 , 2 , 441 ), // #68
+ INST(Crc32b , BaseRRR , (0b0001101011000000010000, kW, kZR, kW, kZR, kW, kZR, false) , kRWI_W , 0 , 2 , 450 ), // #69
+ INST(Crc32cb , BaseRRR , (0b0001101011000000010100, kW, kZR, kW, kZR, kW, kZR, false) , kRWI_W , 0 , 3 , 457 ), // #70
+ INST(Crc32ch , BaseRRR , (0b0001101011000000010101, kW, kZR, kW, kZR, kW, kZR, false) , kRWI_W , 0 , 4 , 465 ), // #71
+ INST(Crc32cw , BaseRRR , (0b0001101011000000010110, kW, kZR, kW, kZR, kW, kZR, false) , kRWI_W , 0 , 5 , 473 ), // #72
+ INST(Crc32cx , BaseRRR , (0b1001101011000000010111, kW, kZR, kW, kZR, kX, kZR, false) , kRWI_W , 0 , 6 , 481 ), // #73
+ INST(Crc32h , BaseRRR , (0b0001101011000000010001, kW, kZR, kW, kZR, kW, kZR, false) , kRWI_W , 0 , 7 , 489 ), // #74
+ INST(Crc32w , BaseRRR , (0b0001101011000000010010, kW, kZR, kW, kZR, kW, kZR, false) , kRWI_W , 0 , 8 , 496 ), // #75
+ INST(Crc32x , BaseRRR , (0b1001101011000000010011, kW, kZR, kW, kZR, kX, kZR, false) , kRWI_W , 0 , 9 , 503 ), // #76
+ INST(Csdb , BaseOp , (0b11010101000000110010001010011111) , 0 , 0 , 8 , 510 ), // #77
+ INST(Csel , BaseCSel , (0b00011010100000000000000000000000) , kRWI_W , 0 , 0 , 710 ), // #78
+ INST(Cset , BaseCSet , (0b00011010100111110000011111100000) , kRWI_W , 0 , 0 , 515 ), // #79
+ INST(Csetm , BaseCSet , (0b01011010100111110000001111100000) , kRWI_W , 0 , 1 , 520 ), // #80
+ INST(Csinc , BaseCSel , (0b00011010100000000000010000000000) , kRWI_W , 0 , 1 , 526 ), // #81
+ INST(Csinv , BaseCSel , (0b01011010100000000000000000000000) , kRWI_W , 0 , 2 , 532 ), // #82
+ INST(Csneg , BaseCSel , (0b01011010100000000000010000000000) , kRWI_W , 0 , 3 , 538 ), // #83
+ INST(Dc , BaseAtDcIcTlbi , (0b00011110000000, 0b00001110000000, true) , kRWI_RX , 0 , 1 , 2 ), // #84
+ INST(Dcps1 , BaseOpImm , (0b11010100101000000000000000000001, 16, 5) , 0 , 0 , 2 , 544 ), // #85
+ INST(Dcps2 , BaseOpImm , (0b11010100101000000000000000000010, 16, 5) , 0 , 0 , 3 , 550 ), // #86
+ INST(Dcps3 , BaseOpImm , (0b11010100101000000000000000000011, 16, 5) , 0 , 0 , 4 , 556 ), // #87
+ INST(Dgh , BaseOp , (0b11010101000000110010000011011111) , 0 , 0 , 9 , 562 ), // #88
+ INST(Dmb , BaseOpImm , (0b11010101000000110011000010111111, 4, 8) , 0 , 0 , 5 , 566 ), // #89
+ INST(Drps , BaseOp , (0b11010110101111110000001111100000) , 0 , 0 , 10 , 570 ), // #90
+ INST(Dsb , BaseOpImm , (0b11010101000000110011000010011111, 4, 8) , 0 , 0 , 6 , 575 ), // #91
+ INST(Eon , BaseLogical , (0b1001010001, 0b10100100, 1) , kRWI_W , 0 , 4 , 583 ), // #92
+ INST(Eor , BaseLogical , (0b1001010000, 0b10100100, 0) , kRWI_W , 0 , 5 , 1418), // #93
+ INST(Esb , BaseOp , (0b11010101000000110010001000011111) , 0 , 0 , 11 , 597 ), // #94
+ INST(Extr , BaseExtract , (0b00010011100000000000000000000000) , kRWI_W , 0 , 0 , 605 ), // #95
+ INST(Eret , BaseOp , (0b11010110100111110000001111100000) , 0 , 0 , 12 , 592 ), // #96
+ INST(Gmi , BaseRRR , (0b1001101011000000000101, kX , kZR, kX , kSP, kX , kZR, true) , kRWI_W , 0 , 10 , 1128), // #97
+ INST(Hint , BaseOpImm , (0b11010101000000110010000000011111, 7, 5) , 0 , 0 , 7 , 1132), // #98
+ INST(Hlt , BaseOpImm , (0b11010100010000000000000000000000, 16, 5) , 0 , 0 , 8 , 1137), // #99
+ INST(Hvc , BaseOpImm , (0b11010100000000000000000000000010, 16, 5) , 0 , 0 , 9 , 1141), // #100
+ INST(Ic , BaseAtDcIcTlbi , (0b00011110000000, 0b00001110000000, false) , kRWI_RX , 0 , 2 , 257 ), // #101
+ INST(Isb , BaseOpImm , (0b11010101000000110011000011011111, 4, 8) , 0 , 0 , 10 , 1149), // #102
+ INST(Ldadd , BaseAtomicOp , (0b1011100000100000000000, kWX, 30, 0) , kRWI_WRX , 0 , 12 , 1189), // #103
+ INST(Ldadda , BaseAtomicOp , (0b1011100010100000000000, kWX, 30, 1) , kRWI_WRX , 0 , 13 , 1195), // #104
+ INST(Ldaddab , BaseAtomicOp , (0b0011100010100000000000, kW , 0 , 1) , kRWI_WRX , 0 , 14 , 1202), // #105
+ INST(Ldaddah , BaseAtomicOp , (0b0111100010100000000000, kW , 0 , 1) , kRWI_WRX , 0 , 15 , 1210), // #106
+ INST(Ldaddal , BaseAtomicOp , (0b1011100011100000000000, kWX, 30, 1) , kRWI_WRX , 0 , 16 , 1218), // #107
+ INST(Ldaddalb , BaseAtomicOp , (0b0011100011100000000000, kW , 0 , 1) , kRWI_WRX , 0 , 17 , 1226), // #108
+ INST(Ldaddalh , BaseAtomicOp , (0b0111100011100000000000, kW , 0 , 1) , kRWI_WRX , 0 , 18 , 1235), // #109
+ INST(Ldaddb , BaseAtomicOp , (0b0011100000100000000000, kW , 0 , 0) , kRWI_WRX , 0 , 19 , 1244), // #110
+ INST(Ldaddh , BaseAtomicOp , (0b0111100000100000000000, kW , 0 , 0) , kRWI_WRX , 0 , 20 , 1251), // #111
+ INST(Ldaddl , BaseAtomicOp , (0b1011100001100000000000, kWX, 30, 0) , kRWI_WRX , 0 , 21 , 1258), // #112
+ INST(Ldaddlb , BaseAtomicOp , (0b0011100001100000000000, kW , 0 , 0) , kRWI_WRX , 0 , 22 , 1265), // #113
+ INST(Ldaddlh , BaseAtomicOp , (0b0111100001100000000000, kW , 0 , 0) , kRWI_WRX , 0 , 23 , 1273), // #114
+ INST(Ldar , BaseRM_NoImm , (0b1000100011011111111111, kWX, kZR, 30) , kRWI_W , 0 , 0 , 1281), // #115
+ INST(Ldarb , BaseRM_NoImm , (0b0000100011011111111111, kW , kZR, 0 ) , kRWI_W , 0 , 1 , 1286), // #116
+ INST(Ldarh , BaseRM_NoImm , (0b0100100011011111111111, kW , kZR, 0 ) , kRWI_W , 0 , 2 , 1292), // #117
+ INST(Ldaxp , BaseLdxp , (0b1000100001111111100000, kWX, 30) , kRWI_WW , 0 , 0 , 1298), // #118
+ INST(Ldaxr , BaseRM_NoImm , (0b1000100001011111111111, kWX, kZR, 30) , kRWI_W , 0 , 3 , 1304), // #119
+ INST(Ldaxrb , BaseRM_NoImm , (0b0000100001011111111111, kW , kZR, 0 ) , kRWI_W , 0 , 4 , 1310), // #120
+ INST(Ldaxrh , BaseRM_NoImm , (0b0100100001011111111111, kW , kZR, 0 ) , kRWI_W , 0 , 5 , 1317), // #121
+ INST(Ldclr , BaseAtomicOp , (0b1011100000100000000100, kWX, 30, 0) , kRWI_WRX , 0 , 24 , 1324), // #122
+ INST(Ldclra , BaseAtomicOp , (0b1011100010100000000100, kWX, 30, 1) , kRWI_WRX , 0 , 25 , 1330), // #123
+ INST(Ldclrab , BaseAtomicOp , (0b0011100010100000000100, kW , 0 , 1) , kRWI_WRX , 0 , 26 , 1337), // #124
+ INST(Ldclrah , BaseAtomicOp , (0b0111100010100000000100, kW , 0 , 1) , kRWI_WRX , 0 , 27 , 1345), // #125
+ INST(Ldclral , BaseAtomicOp , (0b1011100011100000000100, kWX, 30, 1) , kRWI_WRX , 0 , 28 , 1353), // #126
+ INST(Ldclralb , BaseAtomicOp , (0b0011100011100000000100, kW , 0 , 1) , kRWI_WRX , 0 , 29 , 1361), // #127
+ INST(Ldclralh , BaseAtomicOp , (0b0111100011100000000100, kW , 0 , 1) , kRWI_WRX , 0 , 30 , 1370), // #128
+ INST(Ldclrb , BaseAtomicOp , (0b0011100000100000000100, kW , 0 , 0) , kRWI_WRX , 0 , 31 , 1379), // #129
+ INST(Ldclrh , BaseAtomicOp , (0b0111100000100000000100, kW , 0 , 0) , kRWI_WRX , 0 , 32 , 1386), // #130
+ INST(Ldclrl , BaseAtomicOp , (0b1011100001100000000100, kWX, 30, 0) , kRWI_WRX , 0 , 33 , 1393), // #131
+ INST(Ldclrlb , BaseAtomicOp , (0b0011100001100000000100, kW , 0 , 0) , kRWI_WRX , 0 , 34 , 1400), // #132
+ INST(Ldclrlh , BaseAtomicOp , (0b0111100001100000000100, kW , 0 , 0) , kRWI_WRX , 0 , 35 , 1408), // #133
+ INST(Ldeor , BaseAtomicOp , (0b1011100000100000001000, kWX, 30, 0) , kRWI_WRX , 0 , 36 , 1416), // #134
+ INST(Ldeora , BaseAtomicOp , (0b1011100010100000001000, kWX, 30, 1) , kRWI_WRX , 0 , 37 , 1422), // #135
+ INST(Ldeorab , BaseAtomicOp , (0b0011100010100000001000, kW , 0 , 1) , kRWI_WRX , 0 , 38 , 1429), // #136
+ INST(Ldeorah , BaseAtomicOp , (0b0111100010100000001000, kW , 0 , 1) , kRWI_WRX , 0 , 39 , 1437), // #137
+ INST(Ldeoral , BaseAtomicOp , (0b1011100011100000001000, kWX, 30, 1) , kRWI_WRX , 0 , 40 , 1445), // #138
+ INST(Ldeoralb , BaseAtomicOp , (0b0011100011100000001000, kW , 0 , 1) , kRWI_WRX , 0 , 41 , 1453), // #139
+ INST(Ldeoralh , BaseAtomicOp , (0b0111100011100000001000, kW , 0 , 1) , kRWI_WRX , 0 , 42 , 1462), // #140
+ INST(Ldeorb , BaseAtomicOp , (0b0011100000100000001000, kW , 0 , 0) , kRWI_WRX , 0 , 43 , 1471), // #141
+ INST(Ldeorh , BaseAtomicOp , (0b0111100000100000001000, kW , 0 , 0) , kRWI_WRX , 0 , 44 , 1478), // #142
+ INST(Ldeorl , BaseAtomicOp , (0b1011100001100000001000, kWX, 30, 0) , kRWI_WRX , 0 , 45 , 1485), // #143
+ INST(Ldeorlb , BaseAtomicOp , (0b0011100001100000001000, kW , 0 , 0) , kRWI_WRX , 0 , 46 , 1492), // #144
+ INST(Ldeorlh , BaseAtomicOp , (0b0111100001100000001000, kW , 0 , 0) , kRWI_WRX , 0 , 47 , 1500), // #145
+ INST(Ldg , BaseRM_SImm9 , (0b1101100101100000000000, 0b0000000000000000000000, kX , kZR, 0, 4) , kRWI_W , 0 , 0 , 1508), // #146
+ INST(Ldgm , BaseRM_NoImm , (0b1101100111100000000000, kX , kZR, 0 ) , kRWI_W , 0 , 6 , 1512), // #147
+ INST(Ldlar , BaseRM_NoImm , (0b1000100011011111011111, kWX, kZR, 30) , kRWI_W , 0 , 7 , 1517), // #148
+ INST(Ldlarb , BaseRM_NoImm , (0b0000100011011111011111, kW , kZR, 0 ) , kRWI_W , 0 , 8 , 1523), // #149
+ INST(Ldlarh , BaseRM_NoImm , (0b0100100011011111011111, kW , kZR, 0 ) , kRWI_W , 0 , 9 , 1530), // #150
+ INST(Ldnp , BaseLdpStp , (0b0010100001, 0 , kWX, 31, 2) , kRWI_WW , 0 , 0 , 1537), // #151
+ INST(Ldp , BaseLdpStp , (0b0010100101, 0b0010100011, kWX, 31, 2) , kRWI_W , 0 , 1 , 1542), // #152
+ INST(Ldpsw , BaseLdpStp , (0b0110100101, 0b0110100011, kX , 0 , 2) , kRWI_WW , 0 , 2 , 1546), // #153
+ INST(Ldr , BaseLdSt , (0b1011100101, 0b10111000010, 0b10111000011, 0b00011000, kWX, 30, 2, Inst::kIdLdur) , kRWI_W , 0 , 0 , 1552), // #154
+ INST(Ldraa , BaseRM_SImm10 , (0b1111100000100000000001, kX , kZR, 0, 3) , kRWI_W , 0 , 0 , 1556), // #155
+ INST(Ldrab , BaseRM_SImm10 , (0b1111100010100000000001, kX , kZR, 0, 3) , kRWI_W , 0 , 1 , 1562), // #156
+ INST(Ldrb , BaseLdSt , (0b0011100101, 0b00111000010, 0b00111000011, 0 , kW , 0 , 0, Inst::kIdLdurb) , kRWI_W , 0 , 1 , 1568), // #157
+ INST(Ldrh , BaseLdSt , (0b0111100101, 0b01111000010, 0b01111000011, 0 , kW , 0 , 1, Inst::kIdLdurh) , kRWI_W , 0 , 2 , 1573), // #158
+ INST(Ldrsb , BaseLdSt , (0b0011100111, 0b00111000100, 0b00111000101, 0 , kWX, 22, 0, Inst::kIdLdursb) , kRWI_W , 0 , 3 , 1578), // #159
+ INST(Ldrsh , BaseLdSt , (0b0111100110, 0b01111000100, 0b01111000101, 0 , kWX, 22, 1, Inst::kIdLdursh) , kRWI_W , 0 , 4 , 1584), // #160
+ INST(Ldrsw , BaseLdSt , (0b1011100110, 0b10111000100, 0b10111000101, 0b10011000, kX , 0 , 2, Inst::kIdLdursw) , kRWI_W , 0 , 5 , 1590), // #161
+ INST(Ldset , BaseAtomicOp , (0b1011100000100000001100, kWX, 30, 0) , kRWI_WRX , 0 , 48 , 1596), // #162
+ INST(Ldseta , BaseAtomicOp , (0b1011100010100000001100, kWX, 30, 1) , kRWI_WRX , 0 , 49 , 1602), // #163
+ INST(Ldsetab , BaseAtomicOp , (0b0011100010100000001100, kW , 0 , 1) , kRWI_WRX , 0 , 50 , 1609), // #164
+ INST(Ldsetah , BaseAtomicOp , (0b0111100010100000001100, kW , 0 , 1) , kRWI_WRX , 0 , 51 , 1617), // #165
+ INST(Ldsetal , BaseAtomicOp , (0b1011100011100000001100, kWX, 30, 1) , kRWI_WRX , 0 , 52 , 1625), // #166
+ INST(Ldsetalb , BaseAtomicOp , (0b0011100011100000001100, kW , 0 , 1) , kRWI_WRX , 0 , 53 , 1633), // #167
+ INST(Ldsetalh , BaseAtomicOp , (0b0111100011100000001100, kW , 0 , 1) , kRWI_WRX , 0 , 54 , 1642), // #168
+ INST(Ldsetb , BaseAtomicOp , (0b0011100000100000001100, kW , 0 , 0) , kRWI_WRX , 0 , 55 , 1651), // #169
+ INST(Ldseth , BaseAtomicOp , (0b0111100000100000001100, kW , 0 , 0) , kRWI_WRX , 0 , 56 , 1658), // #170
+ INST(Ldsetl , BaseAtomicOp , (0b1011100001100000001100, kWX, 30, 0) , kRWI_WRX , 0 , 57 , 1665), // #171
+ INST(Ldsetlb , BaseAtomicOp , (0b0011100001100000001100, kW , 0 , 0) , kRWI_WRX , 0 , 58 , 1672), // #172
+ INST(Ldsetlh , BaseAtomicOp , (0b0111100001100000001100, kW , 0 , 0) , kRWI_WRX , 0 , 59 , 1680), // #173
+ INST(Ldsmax , BaseAtomicOp , (0b1011100000100000010000, kWX, 30, 0) , kRWI_WRX , 0 , 60 , 1688), // #174
+ INST(Ldsmaxa , BaseAtomicOp , (0b1011100010100000010000, kWX, 30, 1) , kRWI_WRX , 0 , 61 , 1695), // #175
+ INST(Ldsmaxab , BaseAtomicOp , (0b0011100010100000010000, kW , 0 , 1) , kRWI_WRX , 0 , 62 , 1703), // #176
+ INST(Ldsmaxah , BaseAtomicOp , (0b0111100010100000010000, kW , 0 , 1) , kRWI_WRX , 0 , 63 , 1712), // #177
+ INST(Ldsmaxal , BaseAtomicOp , (0b1011100011100000010000, kWX, 30, 1) , kRWI_WRX , 0 , 64 , 1721), // #178
+ INST(Ldsmaxalb , BaseAtomicOp , (0b0011100011100000010000, kW , 0 , 1) , kRWI_WRX , 0 , 65 , 1730), // #179
+ INST(Ldsmaxalh , BaseAtomicOp , (0b0111100011100000010000, kW , 0 , 1) , kRWI_WRX , 0 , 66 , 1740), // #180
+ INST(Ldsmaxb , BaseAtomicOp , (0b0011100000100000010000, kW , 0 , 0) , kRWI_WRX , 0 , 67 , 1750), // #181
+ INST(Ldsmaxh , BaseAtomicOp , (0b0111100000100000010000, kW , 0 , 0) , kRWI_WRX , 0 , 68 , 1758), // #182
+ INST(Ldsmaxl , BaseAtomicOp , (0b1011100001100000010000, kWX, 30, 0) , kRWI_WRX , 0 , 69 , 1766), // #183
+ INST(Ldsmaxlb , BaseAtomicOp , (0b0011100001100000010000, kW , 0 , 0) , kRWI_WRX , 0 , 70 , 1774), // #184
+ INST(Ldsmaxlh , BaseAtomicOp , (0b0111100001100000010000, kW , 0 , 0) , kRWI_WRX , 0 , 71 , 1783), // #185
+ INST(Ldsmin , BaseAtomicOp , (0b1011100000100000010100, kWX, 30, 0) , kRWI_WRX , 0 , 72 , 1792), // #186
+ INST(Ldsmina , BaseAtomicOp , (0b1011100010100000010100, kWX, 30, 1) , kRWI_WRX , 0 , 73 , 1799), // #187
+ INST(Ldsminab , BaseAtomicOp , (0b0011100010100000010100, kW , 0 , 1) , kRWI_WRX , 0 , 74 , 1807), // #188
+ INST(Ldsminah , BaseAtomicOp , (0b0111100010100000010100, kW , 0 , 1) , kRWI_WRX , 0 , 75 , 1816), // #189
+ INST(Ldsminal , BaseAtomicOp , (0b1011100011100000010100, kWX, 30, 1) , kRWI_WRX , 0 , 76 , 1825), // #190
+ INST(Ldsminalb , BaseAtomicOp , (0b0011100011100000010100, kW , 0 , 1) , kRWI_WRX , 0 , 77 , 1834), // #191
+ INST(Ldsminalh , BaseAtomicOp , (0b0111100011100000010100, kW , 0 , 1) , kRWI_WRX , 0 , 78 , 1844), // #192
+ INST(Ldsminb , BaseAtomicOp , (0b0011100000100000010100, kW , 0 , 0) , kRWI_WRX , 0 , 79 , 1854), // #193
+ INST(Ldsminh , BaseAtomicOp , (0b0111100000100000010100, kW , 0 , 0) , kRWI_WRX , 0 , 80 , 1862), // #194
+ INST(Ldsminl , BaseAtomicOp , (0b1011100001100000010100, kWX, 30, 0) , kRWI_WRX , 0 , 81 , 1870), // #195
+ INST(Ldsminlb , BaseAtomicOp , (0b0011100001100000010100, kW , 0 , 0) , kRWI_WRX , 0 , 82 , 1878), // #196
+ INST(Ldsminlh , BaseAtomicOp , (0b0111100001100000010100, kW , 0 , 0) , kRWI_WRX , 0 , 83 , 1887), // #197
+ INST(Ldtr , BaseRM_SImm9 , (0b1011100001000000000010, 0b0000000000000000000000, kWX, kZR, 30, 0) , kRWI_W , 0 , 1 , 1896), // #198
+ INST(Ldtrb , BaseRM_SImm9 , (0b0011100001000000000010, 0b0000000000000000000000, kW , kZR, 0 , 0) , kRWI_W , 0 , 2 , 1901), // #199
+ INST(Ldtrh , BaseRM_SImm9 , (0b0111100001000000000010, 0b0000000000000000000000, kW , kZR, 0 , 0) , kRWI_W , 0 , 3 , 1907), // #200
+ INST(Ldtrsb , BaseRM_SImm9 , (0b0011100011000000000010, 0b0000000000000000000000, kWX, kZR, 22, 0) , kRWI_W , 0 , 4 , 1913), // #201
+ INST(Ldtrsh , BaseRM_SImm9 , (0b0111100011000000000010, 0b0000000000000000000000, kWX, kZR, 22, 0) , kRWI_W , 0 , 5 , 1920), // #202
+ INST(Ldtrsw , BaseRM_SImm9 , (0b1011100010000000000010, 0b0000000000000000000000, kX , kZR, 0 , 0) , kRWI_W , 0 , 6 , 1927), // #203
+ INST(Ldumax , BaseAtomicOp , (0b1011100000100000011000, kWX, 30, 0) , kRWI_WRX , 0 , 84 , 1934), // #204
+ INST(Ldumaxa , BaseAtomicOp , (0b1011100010100000011000, kWX, 30, 1) , kRWI_WRX , 0 , 85 , 1941), // #205
+ INST(Ldumaxab , BaseAtomicOp , (0b0011100010100000011000, kW , 0 , 1) , kRWI_WRX , 0 , 86 , 1949), // #206
+ INST(Ldumaxah , BaseAtomicOp , (0b0111100010100000011000, kW , 0 , 1) , kRWI_WRX , 0 , 87 , 1958), // #207
+ INST(Ldumaxal , BaseAtomicOp , (0b1011100011100000011000, kWX, 30, 1) , kRWI_WRX , 0 , 88 , 1967), // #208
+ INST(Ldumaxalb , BaseAtomicOp , (0b0011100011100000011000, kW , 0 , 1) , kRWI_WRX , 0 , 89 , 1976), // #209
+ INST(Ldumaxalh , BaseAtomicOp , (0b0111100011100000011000, kW , 0 , 1) , kRWI_WRX , 0 , 90 , 1986), // #210
+ INST(Ldumaxb , BaseAtomicOp , (0b0011100000100000011000, kW , 0 , 0) , kRWI_WRX , 0 , 91 , 1996), // #211
+ INST(Ldumaxh , BaseAtomicOp , (0b0111100000100000011000, kW , 0 , 0) , kRWI_WRX , 0 , 92 , 2004), // #212
+ INST(Ldumaxl , BaseAtomicOp , (0b1011100001100000011000, kWX, 30, 0) , kRWI_WRX , 0 , 93 , 2012), // #213
+ INST(Ldumaxlb , BaseAtomicOp , (0b0011100001100000011000, kW , 0 , 0) , kRWI_WRX , 0 , 94 , 2020), // #214
+ INST(Ldumaxlh , BaseAtomicOp , (0b0111100001100000011000, kW , 0 , 0) , kRWI_WRX , 0 , 95 , 2029), // #215
+ INST(Ldumin , BaseAtomicOp , (0b1011100000100000011100, kWX, 30, 0) , kRWI_WRX , 0 , 96 , 2038), // #216
+ INST(Ldumina , BaseAtomicOp , (0b1011100010100000011100, kWX, 30, 1) , kRWI_WRX , 0 , 97 , 2045), // #217
+ INST(Lduminab , BaseAtomicOp , (0b0011100010100000011100, kW , 0 , 1) , kRWI_WRX , 0 , 98 , 2053), // #218
+ INST(Lduminah , BaseAtomicOp , (0b0111100010100000011100, kW , 0 , 1) , kRWI_WRX , 0 , 99 , 2062), // #219
+ INST(Lduminal , BaseAtomicOp , (0b1011100011100000011100, kWX, 30, 1) , kRWI_WRX , 0 , 100, 2071), // #220
+ INST(Lduminalb , BaseAtomicOp , (0b0011100011100000011100, kW , 0 , 1) , kRWI_WRX , 0 , 101, 2080), // #221
+ INST(Lduminalh , BaseAtomicOp , (0b0111100011100000011100, kW , 0 , 1) , kRWI_WRX , 0 , 102, 2090), // #222
+ INST(Lduminb , BaseAtomicOp , (0b0011100000100000011100, kW , 0 , 0) , kRWI_WRX , 0 , 103, 2100), // #223
+ INST(Lduminh , BaseAtomicOp , (0b0111100000100000011100, kW , 0 , 0) , kRWI_WRX , 0 , 104, 2108), // #224
+ INST(Lduminl , BaseAtomicOp , (0b1011100001100000011100, kWX, 30, 0) , kRWI_WRX , 0 , 105, 2116), // #225
+ INST(Lduminlb , BaseAtomicOp , (0b0011100001100000011100, kW , 0 , 0) , kRWI_WRX , 0 , 106, 2124), // #226
+ INST(Lduminlh , BaseAtomicOp , (0b0111100001100000011100, kW , 0 , 0) , kRWI_WRX , 0 , 107, 2133), // #227
+ INST(Ldur , BaseRM_SImm9 , (0b1011100001000000000000, 0b0000000000000000000000, kWX, kZR, 30, 0) , kRWI_W , 0 , 7 , 2142), // #228
+ INST(Ldurb , BaseRM_SImm9 , (0b0011100001000000000000, 0b0000000000000000000000, kW , kZR, 0 , 0) , kRWI_W , 0 , 8 , 2147), // #229
+ INST(Ldurh , BaseRM_SImm9 , (0b0111100001000000000000, 0b0000000000000000000000, kW , kZR, 0 , 0) , kRWI_W , 0 , 9 , 2153), // #230
+ INST(Ldursb , BaseRM_SImm9 , (0b0011100011000000000000, 0b0000000000000000000000, kWX, kZR, 22, 0) , kRWI_W , 0 , 10 , 2159), // #231
+ INST(Ldursh , BaseRM_SImm9 , (0b0111100011000000000000, 0b0000000000000000000000, kWX, kZR, 22, 0) , kRWI_W , 0 , 11 , 2166), // #232
+ INST(Ldursw , BaseRM_SImm9 , (0b1011100010000000000000, 0b0000000000000000000000, kWX, kZR, 0 , 0) , kRWI_W , 0 , 12 , 2173), // #233
+ INST(Ldxp , BaseLdxp , (0b1000100001111111000000, kWX, 30) , kRWI_WW , 0 , 1 , 2180), // #234
+ INST(Ldxr , BaseRM_NoImm , (0b1000100001011111011111, kWX, kZR, 30) , kRWI_W , 0 , 10 , 2185), // #235
+ INST(Ldxrb , BaseRM_NoImm , (0b0000100001011111011111, kW , kZR, 0 ) , kRWI_W , 0 , 11 , 2190), // #236
+ INST(Ldxrh , BaseRM_NoImm , (0b0100100001011111011111, kW , kZR, 0 ) , kRWI_W , 0 , 12 , 2196), // #237
+ INST(Lsl , BaseShift , (0b0001101011000000001000, 0b0101001100000000000000, 0) , kRWI_W , 0 , 2 , 2880), // #238
+ INST(Lslv , BaseShift , (0b0001101011000000001000, 0b0000000000000000000000, 0) , kRWI_W , 0 , 3 , 2202), // #239
+ INST(Lsr , BaseShift , (0b0001101011000000001001, 0b0101001100000000011111, 0) , kRWI_W , 0 , 4 , 2207), // #240
+ INST(Lsrv , BaseShift , (0b0001101011000000001001, 0b0000000000000000000000, 0) , kRWI_W , 0 , 5 , 2211), // #241
+ INST(Madd , BaseRRRR , (0b0001101100000000000000, kWX, kZR, kWX, kZR, kWX, kZR, kWX, kZR, true) , kRWI_W , 0 , 0 , 977 ), // #242
+ INST(Mneg , BaseRRR , (0b0001101100000000111111, kWX, kZR, kWX, kZR, kWX, kZR, true) , kRWI_W , 0 , 11 , 2216), // #243
+ INST(Mov , BaseMov , (_) , kRWI_W , 0 , 0 , 949 ), // #244
+ INST(Movk , BaseMovKNZ , (0b01110010100000000000000000000000) , kRWI_X , 0 , 0 , 2226), // #245
+ INST(Movn , BaseMovKNZ , (0b00010010100000000000000000000000) , kRWI_W , 0 , 1 , 2231), // #246
+ INST(Movz , BaseMovKNZ , (0b01010010100000000000000000000000) , kRWI_W , 0 , 2 , 2236), // #247
+ INST(Mrs , BaseMrs , (_) , kRWI_W , 0 , 0 , 2241), // #248
+ INST(Msr , BaseMsr , (_) , kRWI_W , 0 , 0 , 2245), // #249
+ INST(Msub , BaseRRRR , (0b0001101100000000100000, kWX, kZR, kWX, kZR, kWX, kZR, kWX, kZR, true) , kRWI_W , 0 , 1 , 984 ), // #250
+ INST(Mul , BaseRRR , (0b0001101100000000011111, kWX, kZR, kWX, kZR, kWX, kZR, true) , kRWI_W , 0 , 12 , 991 ), // #251
+ INST(Mvn , BaseMvnNeg , (0b00101010001000000000001111100000) , kRWI_W , 0 , 0 , 2249), // #252
+ INST(Neg , BaseMvnNeg , (0b01001011000000000000001111100000) , kRWI_W , 0 , 1 , 540 ), // #253
+ INST(Negs , BaseMvnNeg , (0b01101011000000000000001111100000) , kRWI_W , 0 , 2 , 2258), // #254
+ INST(Ngc , BaseRR , (0b01011010000000000000001111100000, kWX, kZR, 0, kWX, kZR, 16, true) , kRWI_W , 0 , 7 , 2263), // #255
+ INST(Ngcs , BaseRR , (0b01111010000000000000001111100000, kWX, kZR, 0, kWX, kZR, 16, true) , kRWI_W , 0 , 8 , 2267), // #256
+ INST(Nop , BaseOp , (0b11010101000000110010000000011111) , 0 , 0 , 13 , 2272), // #257
+ INST(Orn , BaseLogical , (0b0101010001, 0b01100100, 1) , kRWI_W , 0 , 6 , 2280), // #258
+ INST(Orr , BaseLogical , (0b0101010000, 0b01100100, 0) , kRWI_W , 0 , 7 , 2284), // #259
+ INST(Pacda , BaseRR , (0b11011010110000010000100000000000, kX, kZR, 0, kX, kSP, 5, true) , kRWI_X , 0 , 9 , 2288), // #260
+ INST(Pacdb , BaseRR , (0b11011010110000010000110000000000, kX, kZR, 0, kX, kSP, 5, true) , kRWI_X , 0 , 10 , 2294), // #261
+ INST(Pacdza , BaseR , (0b11011010110000010010101111100000, kX, kZR, 0) , kRWI_X , 0 , 4 , 2300), // #262
+ INST(Pacdzb , BaseR , (0b11011010110000010010111111100000, kX, kZR, 0) , kRWI_X , 0 , 5 , 2307), // #263
+ INST(Pacga , BaseRRR , (0b1001101011000000001100, kX, kZR, kX, kZR, kX, kSP, false) , kRWI_W , 0 , 13 , 2314), // #264
+ INST(Pssbb , BaseOp , (0b11010101000000110011010010011111) , 0 , 0 , 14 , 2338), // #265
+ INST(Rbit , BaseRR , (0b01011010110000000000000000000000, kWX, kZR, 0, kWX, kZR, 5, true) , kRWI_W , 0 , 11 , 2364), // #266
+ INST(Ret , BaseBranchReg , (0b11010110010111110000000000000000) , kRWI_R , 0 , 2 , 593 ), // #267
+ INST(Rev , BaseRev , (_) , kRWI_W , 0 , 0 , 2369), // #268
+ INST(Rev16 , BaseRR , (0b01011010110000000000010000000000, kWX, kZR, 0, kWX, kZR, 5, true) , kRWI_W , 0 , 12 , 2373), // #269
+ INST(Rev32 , BaseRR , (0b11011010110000000000100000000000, kWX, kZR, 0, kWX, kZR, 5, true) , kRWI_W , 0 , 13 , 2379), // #270
+ INST(Rev64 , BaseRR , (0b11011010110000000000110000000000, kWX, kZR, 0, kWX, kZR, 5, true) , kRWI_W , 0 , 14 , 2385), // #271
+ INST(Ror , BaseShift , (0b0001101011000000001011, 0b0001001110000000000000, 1) , kRWI_W , 0 , 6 , 2391), // #272
+ INST(Rorv , BaseShift , (0b0001101011000000001011, 0b0000000000000000000000, 1) , kRWI_W , 0 , 7 , 2395), // #273
+ INST(Sbc , BaseRRR , (0b0101101000000000000000, kWX, kZR, kWX, kZR, kWX, kZR, true) , kRWI_W , 0 , 14 , 2498), // #274
+ INST(Sbcs , BaseRRR , (0b0111101000000000000000, kWX, kZR, kWX, kZR, kWX, kZR, true) , kRWI_W , 0 , 15 , 2502), // #275
+ INST(Sbfiz , BaseBfi , (0b00010011000000000000000000000000) , kRWI_W , 0 , 1 , 2507), // #276
+ INST(Sbfm , BaseBfm , (0b00010011000000000000000000000000) , kRWI_W , 0 , 1 , 2513), // #277
+ INST(Sbfx , BaseBfx , (0b00010011000000000000000000000000) , kRWI_W , 0 , 1 , 2518), // #278
+ INST(Sdiv , BaseRRR , (0b0001101011000000000011, kWX, kZR, kWX, kZR, kWX, kZR, true) , kRWI_W , 0 , 16 , 2529), // #279
+ INST(Setf8 , BaseR , (0b00111010000000000000100000001101, kW, kZR, 5) , 0 , 0 , 6 , 2541), // #280
+ INST(Setf16 , BaseR , (0b00111010000000000100100000001101, kW, kZR, 5) , 0 , 0 , 7 , 2534), // #281
+ INST(Sev , BaseOp , (0b11010101000000110010000010011111) , 0 , 0 , 15 , 2547), // #282
+ INST(Sevl , BaseOp , (0b11010101000000110010000010111111) , 0 , 0 , 16 , 2551), // #283
+ INST(Smaddl , BaseRRRR , (0b1001101100100000000000, kX , kZR, kW , kZR, kW , kZR, kX , kZR, false) , kRWI_W , 0 , 2 , 2758), // #284
+ INST(Smc , BaseOpImm , (0b11010100000000000000000000000011, 16, 5) , 0 , 0 , 11 , 53 ), // #285
+ INST(Smnegl , BaseRRR , (0b1001101100100000111111, kX , kZR, kW , kZR, kW , kZR, false) , kRWI_W , 0 , 17 , 2815), // #286
+ INST(Smsubl , BaseRRRR , (0b1001101100100000100000, kX , kZR, kW , kZR, kW , kZR, kX , kZR, false) , kRWI_W , 0 , 3 , 2827), // #287
+ INST(Smulh , BaseRRR , (0b1001101101000000011111, kX , kZR, kX , kZR, kX , kZR, true) , kRWI_W , 0 , 18 , 2834), // #288
+ INST(Smull , BaseRRR , (0b1001101100100000011111, kX , kZR, kW , kZR, kW , kZR, false) , kRWI_W , 0 , 19 , 2840), // #289
+ INST(Ssbb , BaseOp , (0b11010101000000110011000010011111) , 0 , 0 , 17 , 2339), // #290
+ INST(St2g , BaseRM_SImm9 , (0b1101100110100000000010, 0b1101100110100000000001, kX, kSP, 0, 4) , kRWI_RW , 0 , 13 , 3164), // #291
+ INST(Stadd , BaseAtomicSt , (0b1011100000100000000000, kWX, 30) , kRWI_RX , 0 , 0 , 3177), // #292
+ INST(Staddl , BaseAtomicSt , (0b1011100001100000000000, kWX, 30) , kRWI_RX , 0 , 1 , 3197), // #293
+ INST(Staddb , BaseAtomicSt , (0b0011100000100000000000, kW , 0 ) , kRWI_RX , 0 , 2 , 3183), // #294
+ INST(Staddlb , BaseAtomicSt , (0b0011100001100000000000, kW , 0 ) , kRWI_RX , 0 , 3 , 3204), // #295
+ INST(Staddh , BaseAtomicSt , (0b0111100000100000000000, kW , 0 ) , kRWI_RX , 0 , 4 , 3190), // #296
+ INST(Staddlh , BaseAtomicSt , (0b0111100001100000000000, kW , 0 ) , kRWI_RX , 0 , 5 , 3212), // #297
+ INST(Stclr , BaseAtomicSt , (0b1011100000100000000100, kWX, 30) , kRWI_RX , 0 , 6 , 3220), // #298
+ INST(Stclrl , BaseAtomicSt , (0b1011100001100000000100, kWX, 30) , kRWI_RX , 0 , 7 , 3240), // #299
+ INST(Stclrb , BaseAtomicSt , (0b0011100000100000000100, kW , 0 ) , kRWI_RX , 0 , 8 , 3226), // #300
+ INST(Stclrlb , BaseAtomicSt , (0b0011100001100000000100, kW , 0 ) , kRWI_RX , 0 , 9 , 3247), // #301
+ INST(Stclrh , BaseAtomicSt , (0b0111100000100000000100, kW , 0 ) , kRWI_RX , 0 , 10 , 3233), // #302
+ INST(Stclrlh , BaseAtomicSt , (0b0111100001100000000100, kW , 0 ) , kRWI_RX , 0 , 11 , 3255), // #303
+ INST(Steor , BaseAtomicSt , (0b1011100000100000001000, kWX, 30) , kRWI_RX , 0 , 12 , 3263), // #304
+ INST(Steorl , BaseAtomicSt , (0b1011100001100000001000, kWX, 30) , kRWI_RX , 0 , 13 , 3283), // #305
+ INST(Steorb , BaseAtomicSt , (0b0011100000100000001000, kW , 0 ) , kRWI_RX , 0 , 14 , 3269), // #306
+ INST(Steorlb , BaseAtomicSt , (0b0011100001100000001000, kW , 0 ) , kRWI_RX , 0 , 15 , 3290), // #307
+ INST(Steorh , BaseAtomicSt , (0b0111100000100000001000, kW , 0 ) , kRWI_RX , 0 , 16 , 3276), // #308
+ INST(Steorlh , BaseAtomicSt , (0b0111100001100000001000, kW , 0 ) , kRWI_RX , 0 , 17 , 3298), // #309
+ INST(Stg , BaseRM_SImm9 , (0b1101100100100000000010, 0b1101100100100000000001, kX, kSP, 0, 4) , kRWI_RW , 0 , 14 , 3306), // #310
+ INST(Stgm , BaseRM_NoImm , (0b1101100110100000000000, kX , kZR, 0 ) , kRWI_RW , 0 , 13 , 3310), // #311
+ INST(Stgp , BaseLdpStp , (0b0110100100, 0b0110100010, kX, 0, 4) , kRWI_RRW , 0 , 3 , 3315), // #312
+ INST(Stllr , BaseRM_NoImm , (0b1000100010011111011111, kWX, kZR, 30) , kRWI_RW , 0 , 14 , 3320), // #313
+ INST(Stllrb , BaseRM_NoImm , (0b0000100010011111011111, kW , kZR, 0 ) , kRWI_RW , 0 , 15 , 3326), // #314
+ INST(Stllrh , BaseRM_NoImm , (0b0100100010011111011111, kW , kZR, 0 ) , kRWI_RW , 0 , 16 , 3333), // #315
+ INST(Stlr , BaseRM_NoImm , (0b1000100010011111111111, kWX, kZR, 30) , kRWI_RW , 0 , 17 , 3340), // #316
+ INST(Stlrb , BaseRM_NoImm , (0b0000100010011111111111, kW , kZR, 0 ) , kRWI_RW , 0 , 18 , 3345), // #317
+ INST(Stlrh , BaseRM_NoImm , (0b0100100010011111111111, kW , kZR, 0 ) , kRWI_RW , 0 , 19 , 3351), // #318
+ INST(Stlxp , BaseStxp , (0b1000100000100000100000, kWX, 30) , kRWI_WRRX , 0 , 0 , 3357), // #319
+ INST(Stlxr , BaseAtomicOp , (0b1000100000000000111111, kWX, 30, 1) , kRWI_WRX , 0 , 108, 3363), // #320
+ INST(Stlxrb , BaseAtomicOp , (0b0000100000000000111111, kW , 0 , 1) , kRWI_WRX , 0 , 109, 3369), // #321
+ INST(Stlxrh , BaseAtomicOp , (0b0100100000000000111111, kW , 0 , 1) , kRWI_WRX , 0 , 110, 3376), // #322
+ INST(Stnp , BaseLdpStp , (0b0010100000, 0 , kWX, 31, 2) , kRWI_RRW , 0 , 4 , 3383), // #323
+ INST(Stp , BaseLdpStp , (0b0010100100, 0b0010100010, kWX, 31, 2) , kRWI_RRW , 0 , 5 , 3388), // #324
+ INST(Str , BaseLdSt , (0b1011100100, 0b10111000000, 0b10111000001, 0 , kWX, 30, 2, Inst::kIdStur) , kRWI_RW , 0 , 6 , 3392), // #325
+ INST(Strb , BaseLdSt , (0b0011100100, 0b00111000000, 0b00111000001, 0 , kW , 30, 0, Inst::kIdSturb) , kRWI_RW , 0 , 7 , 3396), // #326
+ INST(Strh , BaseLdSt , (0b0111100100, 0b01111000000, 0b01111000001, 0 , kWX, 30, 1, Inst::kIdSturh) , kRWI_RW , 0 , 8 , 3401), // #327
+ INST(Stset , BaseAtomicSt , (0b1011100000100000001100, kWX, 30) , kRWI_RX , 0 , 18 , 3406), // #328
+ INST(Stsetl , BaseAtomicSt , (0b1011100001100000001100, kWX, 30) , kRWI_RX , 0 , 19 , 3426), // #329
+ INST(Stsetb , BaseAtomicSt , (0b0011100000100000001100, kW , 0 ) , kRWI_RX , 0 , 20 , 3412), // #330
+ INST(Stsetlb , BaseAtomicSt , (0b0011100001100000001100, kW , 0 ) , kRWI_RX , 0 , 21 , 3433), // #331
+ INST(Stseth , BaseAtomicSt , (0b0111100000100000001100, kW , 0 ) , kRWI_RX , 0 , 22 , 3419), // #332
+ INST(Stsetlh , BaseAtomicSt , (0b0111100001100000001100, kW , 0 ) , kRWI_RX , 0 , 23 , 3441), // #333
+ INST(Stsmax , BaseAtomicSt , (0b1011100000100000010000, kWX, 30) , kRWI_RX , 0 , 24 , 3449), // #334
+ INST(Stsmaxl , BaseAtomicSt , (0b1011100001100000010000, kWX, 30) , kRWI_RX , 0 , 25 , 3472), // #335
+ INST(Stsmaxb , BaseAtomicSt , (0b0011100000100000010000, kW , 0 ) , kRWI_RX , 0 , 26 , 3456), // #336
+ INST(Stsmaxlb , BaseAtomicSt , (0b0011100001100000010000, kW , 0 ) , kRWI_RX , 0 , 27 , 3480), // #337
+ INST(Stsmaxh , BaseAtomicSt , (0b0111100000100000010000, kW , 0 ) , kRWI_RX , 0 , 28 , 3464), // #338
+ INST(Stsmaxlh , BaseAtomicSt , (0b0111100001100000010000, kW , 0 ) , kRWI_RX , 0 , 29 , 3489), // #339
+ INST(Stsmin , BaseAtomicSt , (0b1011100000100000010100, kWX, 30) , kRWI_RX , 0 , 30 , 3498), // #340
+ INST(Stsminl , BaseAtomicSt , (0b1011100001100000010100, kWX, 30) , kRWI_RX , 0 , 31 , 3521), // #341
+ INST(Stsminb , BaseAtomicSt , (0b0011100000100000010100, kW , 0 ) , kRWI_RX , 0 , 32 , 3505), // #342
+ INST(Stsminlb , BaseAtomicSt , (0b0011100001100000010100, kW , 0 ) , kRWI_RX , 0 , 33 , 3529), // #343
+ INST(Stsminh , BaseAtomicSt , (0b0111100000100000010100, kW , 0 ) , kRWI_RX , 0 , 34 , 3513), // #344
+ INST(Stsminlh , BaseAtomicSt , (0b0111100001100000010100, kW , 0 ) , kRWI_RX , 0 , 35 , 3538), // #345
+ INST(Sttr , BaseRM_SImm9 , (0b1011100000000000000010, 0b0000000000000000000000, kWX, kZR, 30, 0) , kRWI_RW , 0 , 15 , 3547), // #346
+ INST(Sttrb , BaseRM_SImm9 , (0b0011100000000000000010, 0b0000000000000000000000, kW , kZR, 0 , 0) , kRWI_RW , 0 , 16 , 3552), // #347
+ INST(Sttrh , BaseRM_SImm9 , (0b0111100000000000000010, 0b0000000000000000000000, kW , kZR, 0 , 0) , kRWI_RW , 0 , 17 , 3558), // #348
+ INST(Stumax , BaseAtomicSt , (0b1011100000100000011000, kWX, 30) , kRWI_RX , 0 , 36 , 3564), // #349
+ INST(Stumaxl , BaseAtomicSt , (0b1011100001100000011000, kWX, 30) , kRWI_RX , 0 , 37 , 3587), // #350
+ INST(Stumaxb , BaseAtomicSt , (0b0011100000100000011000, kW , 0 ) , kRWI_RX , 0 , 38 , 3571), // #351
+ INST(Stumaxlb , BaseAtomicSt , (0b0011100001100000011000, kW , 0 ) , kRWI_RX , 0 , 39 , 3595), // #352
+ INST(Stumaxh , BaseAtomicSt , (0b0111100000100000011000, kW , 0 ) , kRWI_RX , 0 , 40 , 3579), // #353
+ INST(Stumaxlh , BaseAtomicSt , (0b0111100001100000011000, kW , 0 ) , kRWI_RX , 0 , 41 , 3604), // #354
+ INST(Stumin , BaseAtomicSt , (0b1011100000100000011100, kWX, 30) , kRWI_RX , 0 , 42 , 3613), // #355
+ INST(Stuminl , BaseAtomicSt , (0b1011100001100000011100, kWX, 30) , kRWI_RX , 0 , 43 , 3636), // #356
+ INST(Stuminb , BaseAtomicSt , (0b0011100000100000011100, kW , 0 ) , kRWI_RX , 0 , 44 , 3620), // #357
+ INST(Stuminlb , BaseAtomicSt , (0b0011100001100000011100, kW , 0 ) , kRWI_RX , 0 , 45 , 3644), // #358
+ INST(Stuminh , BaseAtomicSt , (0b0111100000100000011100, kW , 0 ) , kRWI_RX , 0 , 46 , 3628), // #359
+ INST(Stuminlh , BaseAtomicSt , (0b0111100001100000011100, kW , 0 ) , kRWI_RX , 0 , 47 , 3653), // #360
+ INST(Stur , BaseRM_SImm9 , (0b1011100000000000000000, 0b0000000000000000000000, kWX, kZR, 30, 0) , kRWI_RW , 0 , 18 , 3662), // #361
+ INST(Sturb , BaseRM_SImm9 , (0b0011100000000000000000, 0b0000000000000000000000, kW , kZR, 0 , 0) , kRWI_RW , 0 , 19 , 3667), // #362
+ INST(Sturh , BaseRM_SImm9 , (0b0111100000000000000000, 0b0000000000000000000000, kW , kZR, 0 , 0) , kRWI_RW , 0 , 20 , 3673), // #363
+ INST(Stxp , BaseStxp , (0b1000100000100000000000, kWX, 30) , kRWI_WRRW , 0 , 1 , 3679), // #364
+ INST(Stxr , BaseStx , (0b1000100000000000011111, kWX, 30) , kRWI_WRW , 0 , 0 , 3684), // #365
+ INST(Stxrb , BaseStx , (0b0000100000000000011111, kW , 0 ) , kRWI_WRW , 0 , 1 , 3689), // #366
+ INST(Stxrh , BaseStx , (0b0100100000000000011111, kW , 0 ) , kRWI_WRW , 0 , 2 , 3695), // #367
+ INST(Stz2g , BaseRM_SImm9 , (0b1101100111100000000010, 0b1101100111100000000001, kX , kSP, 0, 4) , kRWI_RW , 0 , 21 , 3701), // #368
+ INST(Stzg , BaseRM_SImm9 , (0b1101100101100000000010, 0b1101100101100000000001, kX , kSP, 0, 4) , kRWI_RW , 0 , 22 , 3707), // #369
+ INST(Stzgm , BaseRM_NoImm , (0b1101100100100000000000, kX , kZR, 0) , kRWI_RW , 0 , 20 , 3712), // #370
+ INST(Sub , BaseAddSub , (0b1001011000, 0b1001011001, 0b1010001) , kRWI_X , 0 , 2 , 985 ), // #371
+ INST(Subg , BaseRRII , (0b1101000110000000000000, kX, kSP, kX, kSP, 6, 4, 16, 4, 0, 10) , kRWI_W , 0 , 1 , 3718), // #372
+ INST(Subp , BaseRRR , (0b1001101011000000000000, kX, kZR, kX, kSP, kX, kSP, false) , kRWI_W , 0 , 20 , 3723), // #373
+ INST(Subps , BaseRRR , (0b1011101011000000000000, kX, kZR, kX, kSP, kX, kSP, false) , kRWI_W , 0 , 21 , 3728), // #374
+ INST(Subs , BaseAddSub , (0b1101011000, 0b1101011001, 0b1110001) , kRWI_X , 0 , 3 , 3734), // #375
+ INST(Svc , BaseOpImm , (0b11010100000000000000000000000001, 16, 5) , 0 , 0 , 12 , 3752), // #376
+ INST(Swp , BaseAtomicOp , (0b1011100000100000100000, kWX, 30, 1) , kRWI_RWX , 0 , 111, 3756), // #377
+ INST(Swpa , BaseAtomicOp , (0b1011100010100000100000, kWX, 30, 1) , kRWI_RWX , 0 , 112, 3760), // #378
+ INST(Swpab , BaseAtomicOp , (0b0011100010100000100000, kW , 0 , 1) , kRWI_RWX , 0 , 113, 3765), // #379
+ INST(Swpah , BaseAtomicOp , (0b0111100010100000100000, kW , 0 , 1) , kRWI_RWX , 0 , 114, 3771), // #380
+ INST(Swpal , BaseAtomicOp , (0b1011100011100000100000, kWX, 30, 1) , kRWI_RWX , 0 , 115, 3777), // #381
+ INST(Swpalb , BaseAtomicOp , (0b0011100011100000100000, kW , 0 , 1) , kRWI_RWX , 0 , 116, 3783), // #382
+ INST(Swpalh , BaseAtomicOp , (0b0111100011100000100000, kW , 0 , 1) , kRWI_RWX , 0 , 117, 3790), // #383
+ INST(Swpb , BaseAtomicOp , (0b0011100000100000100000, kW , 0 , 1) , kRWI_RWX , 0 , 118, 3797), // #384
+ INST(Swph , BaseAtomicOp , (0b0111100000100000100000, kW , 0 , 1) , kRWI_RWX , 0 , 119, 3802), // #385
+ INST(Swpl , BaseAtomicOp , (0b1011100001100000100000, kWX, 30, 1) , kRWI_RWX , 0 , 120, 3807), // #386
+ INST(Swplb , BaseAtomicOp , (0b0011100001100000100000, kW , 0 , 1) , kRWI_RWX , 0 , 121, 3812), // #387
+ INST(Swplh , BaseAtomicOp , (0b0111100001100000100000, kW , 0 , 1) , kRWI_RWX , 0 , 122, 3818), // #388
+ INST(Sxtb , BaseExtend , (0b0001001100000000000111, kWX, 0) , kRWI_W , 0 , 0 , 3824), // #389
+ INST(Sxth , BaseExtend , (0b0001001100000000001111, kWX, 0) , kRWI_W , 0 , 1 , 3829), // #390
+ INST(Sxtw , BaseExtend , (0b1001001101000000011111, kX , 0) , kRWI_W , 0 , 2 , 3845), // #391
+ INST(Sys , BaseSys , (_) , kRWI_W , 0 , 0 , 3850), // #392
+ INST(Tlbi , BaseAtDcIcTlbi , (0b00011110000000, 0b00010000000000, false) , kRWI_RX , 0 , 3 , 3871), // #393
+ INST(Tst , BaseTst , (0b1101010000, 0b111001000) , kRWI_R , 0 , 0 , 437 ), // #394
+ INST(Tbnz , BaseBranchTst , (0b00110111000000000000000000000000) , kRWI_R , 0 , 0 , 3858), // #395
+ INST(Tbz , BaseBranchTst , (0b00110110000000000000000000000000) , kRWI_R , 0 , 1 , 3867), // #396
+ INST(Ubfiz , BaseBfi , (0b01010011000000000000000000000000) , kRWI_W , 0 , 2 , 3969), // #397
+ INST(Ubfm , BaseBfm , (0b01010011000000000000000000000000) , kRWI_W , 0 , 2 , 3975), // #398
+ INST(Ubfx , BaseBfx , (0b01010011000000000000000000000000) , kRWI_W , 0 , 2 , 3980), // #399
+ INST(Udf , BaseOpImm , (0b00000000000000000000000000000000, 16, 0) , 0 , 0 , 13 , 3991), // #400
+ INST(Udiv , BaseRRR , (0b0001101011000000000010, kWX, kZR, kWX, kZR, kWX, kZR, true) , kRWI_W , 0 , 22 , 3995), // #401
+ INST(Umaddl , BaseRRRR , (0b1001101110100000000000, kX , kZR, kW , kZR, kW , kZR, kX , kZR, false) , kRWI_W , 0 , 4 , 4012), // #402
+ INST(Umnegl , BaseRRR , (0b1001101110100000111111, kX , kZR, kW , kZR, kW , kZR, false) , kRWI_W , 0 , 23 , 4075), // #403
+ INST(Umull , BaseRRR , (0b1001101110100000011111, kX , kZR, kW , kZR, kW , kZR, false) , kRWI_W , 0 , 24 , 4100), // #404
+ INST(Umulh , BaseRRR , (0b1001101111000000011111, kX , kZR, kX , kZR, kX , kZR, false) , kRWI_W , 0 , 25 , 4094), // #405
+ INST(Umsubl , BaseRRRR , (0b1001101110100000100000, kX , kZR, kW , kZR, kW , kZR, kX , kZR, false) , kRWI_W , 0 , 5 , 4087), // #406
+ INST(Uxtb , BaseExtend , (0b0101001100000000000111, kW, 1) , kRWI_W , 0 , 3 , 4291), // #407
+ INST(Uxth , BaseExtend , (0b0101001100000000001111, kW, 1) , kRWI_W , 0 , 4 , 4296), // #408
+ INST(Wfe , BaseOp , (0b11010101000000110010000001011111) , 0 , 0 , 18 , 4322), // #409
+ INST(Wfi , BaseOp , (0b11010101000000110010000001111111) , 0 , 0 , 19 , 4326), // #410
+ INST(Xaflag , BaseOp , (0b11010101000000000100000000111111) , 0 , 0 , 20 , 4330), // #411
+ INST(Xpacd , BaseR , (0b11011010110000010100011111100000, kX, kZR, 0) , kRWI_X , 0 , 8 , 4341), // #412
+ INST(Xpaci , BaseR , (0b11011010110000010100001111100000, kX, kZR, 0) , kRWI_X , 0 , 9 , 4347), // #413
+ INST(Xpaclri , BaseOp , (0b11010101000000110010000011111111) , kRWI_X , 0 , 21 , 4353), // #414
+ INST(Yield , BaseOp , (0b11010101000000110010000000111111) , 0 , 0 , 22 , 4361), // #415
+ INST(Abs_v , ISimdVV , (0b0000111000100000101110, kVO_V_Any) , kRWI_W , 0 , 0 , 2855), // #416
+ INST(Add_v , ISimdVVV , (0b0000111000100000100001, kVO_V_Any) , kRWI_W , 0 , 0 , 978 ), // #417
+ INST(Addhn_v , ISimdVVV , (0b0000111000100000010000, kVO_V_B8H4S2) , kRWI_W , F(Narrow) , 1 , 2345), // #418
+ INST(Addhn2_v , ISimdVVV , (0b0100111000100000010000, kVO_V_B16H8S4) , kRWI_W , F(Narrow) , 2 , 2352), // #419
+ INST(Addp_v , ISimdPair , (0b0101111000110001101110, 0b0000111000100000101111, kVO_V_Any) , kRWI_W , F(Pair) , 0 , 638 ), // #420
+ INST(Addv_v , ISimdSV , (0b0000111000110001101110, kVO_V_BH_4S) , kRWI_W , 0 , 0 , 20 ), // #421
+ INST(Aesd_v , ISimdVVx , (0b0100111000101000010110, kOp_V16B, kOp_V16B) , kRWI_X , 0 , 0 , 34 ), // #422
+ INST(Aese_v , ISimdVVx , (0b0100111000101000010010, kOp_V16B, kOp_V16B) , kRWI_X , 0 , 1 , 39 ), // #423
+ INST(Aesimc_v , ISimdVVx , (0b0100111000101000011110, kOp_V16B, kOp_V16B) , kRWI_W , 0 , 2 , 44 ), // #424
+ INST(Aesmc_v , ISimdVVx , (0b0100111000101000011010, kOp_V16B, kOp_V16B) , kRWI_W , 0 , 3 , 51 ), // #425
+ INST(And_v , ISimdVVV , (0b0000111000100000000111, kVO_V_B) , kRWI_W , 0 , 3 , 57 ), // #426
+ INST(Bcax_v , ISimdVVVV , (0b1100111000100000000000, kVO_V_B16) , kRWI_W , 0 , 0 , 187 ), // #427
+ INST(Bfcvt_v , ISimdVVx , (0b0001111001100011010000, kOp_H, kOp_S) , kRWI_W , 0 , 4 , 196 ), // #428
+ INST(Bfcvtn_v , ISimdVVx , (0b0000111010100001011010, kOp_V4H, kOp_V4S) , kRWI_W , F(Narrow) , 5 , 202 ), // #429
+ INST(Bfcvtn2_v , ISimdVVx , (0b0100111010100001011010, kOp_V8H, kOp_V4S) , kRWI_W , F(Narrow) , 6 , 209 ), // #430
+ INST(Bfdot_v , SimdDot , (0b0010111001000000111111, 0b0000111101000000111100, kET_S, kET_H, kET_2H) , kRWI_X , 0 , 0 , 217 ), // #431
+ INST(Bfmlalb_v , SimdFmlal , (0b0010111011000000111111, 0b0000111111000000111100, 0, kET_S, kET_H, kET_H) , kRWI_X , F(VH0_15) , 0 , 227 ), // #432
+ INST(Bfmlalt_v , SimdFmlal , (0b0110111011000000111111, 0b0100111111000000111100, 0, kET_S, kET_H, kET_H) , kRWI_X , F(VH0_15) , 1 , 235 ), // #433
+ INST(Bfmmla_v , ISimdVVVx , (0b0110111001000000111011, kOp_V4S, kOp_V8H, kOp_V8H) , kRWI_X , F(Long) , 0 , 243 ), // #434
+ INST(Bic_v , SimdBicOrr , (0b0000111001100000000111, 0b0010111100000000000001) , kRWI_W , 0 , 0 , 256 ), // #435
+ INST(Bif_v , ISimdVVV , (0b0010111011100000000111, kVO_V_B) , kRWI_X , 0 , 4 , 265 ), // #436
+ INST(Bit_v , ISimdVVV , (0b0010111010100000000111, kVO_V_B) , kRWI_X , 0 , 5 , 2365), // #437
+ INST(Bsl_v , ISimdVVV , (0b0010111001100000000111, kVO_V_B) , kRWI_X , 0 , 6 , 280 ), // #438
+ INST(Cls_v , ISimdVV , (0b0000111000100000010010, kVO_V_BHS) , kRWI_W , 0 , 1 , 412 ), // #439
+ INST(Clz_v , ISimdVV , (0b0010111000100000010010, kVO_V_BHS) , kRWI_W , 0 , 2 , 416 ), // #440
+ INST(Cmeq_v , SimdCmp , (0b0010111000100000100011, 0b0000111000100000100110, kVO_V_Any) , kRWI_W , 0 , 0 , 663 ), // #441
+ INST(Cmge_v , SimdCmp , (0b0000111000100000001111, 0b0010111000100000100010, kVO_V_Any) , kRWI_W , 0 , 1 , 669 ), // #442
+ INST(Cmgt_v , SimdCmp , (0b0000111000100000001101, 0b0000111000100000100010, kVO_V_Any) , kRWI_W , 0 , 2 , 675 ), // #443
+ INST(Cmhi_v , SimdCmp , (0b0010111000100000001101, 0b0000000000000000000000, kVO_V_Any) , kRWI_W , 0 , 3 , 420 ), // #444
+ INST(Cmhs_v , SimdCmp , (0b0010111000100000001111, 0b0000000000000000000000, kVO_V_Any) , kRWI_W , 0 , 4 , 425 ), // #445
+ INST(Cmle_v , SimdCmp , (0b0000000000000000000000, 0b0010111000100000100110, kVO_V_Any) , kRWI_W , 0 , 5 , 687 ), // #446
+ INST(Cmlt_v , SimdCmp , (0b0000000000000000000000, 0b0000111000100000101010, kVO_V_Any) , kRWI_W , 0 , 6 , 693 ), // #447
+ INST(Cmtst_v , ISimdVVV , (0b0000111000100000100011, kVO_V_Any) , kRWI_W , 0 , 7 , 435 ), // #448
+ INST(Cnt_v , ISimdVV , (0b0000111000100000010110, kVO_V_B) , kRWI_W , 0 , 3 , 446 ), // #449
+ INST(Dup_v , SimdDup , (_) , kRWI_W , 0 , 0 , 579 ), // #450
+ INST(Eor_v , ISimdVVV , (0b0010111000100000000111, kVO_V_B) , kRWI_W , 0 , 8 , 1418), // #451
+ INST(Eor3_v , ISimdVVVV , (0b1100111000000000000000, kVO_V_B16) , kRWI_W , 0 , 1 , 587 ), // #452
+ INST(Ext_v , ISimdVVVI , (0b0010111000000000000000, kVO_V_B, 4, 11, 1) , kRWI_W , 0 , 0 , 601 ), // #453
+ INST(Fabd_v , FSimdVVV , (0b0111111010100000110101, kHF_C, 0b0010111010100000110101, kHF_C) , kRWI_W , 0 , 0 , 610 ), // #454
+ INST(Fabs_v , FSimdVV , (0b0001111000100000110000, kHF_A, 0b0000111010100000111110, kHF_B) , kRWI_W , 0 , 0 , 615 ), // #455
+ INST(Facge_v , FSimdVVV , (0b0111111000100000111011, kHF_C, 0b0010111000100000111011, kHF_C) , kRWI_W , 0 , 1 , 620 ), // #456
+ INST(Facgt_v , FSimdVVV , (0b0111111010100000111011, kHF_C, 0b0010111010100000111011, kHF_C) , kRWI_W , 0 , 2 , 626 ), // #457
+ INST(Fadd_v , FSimdVVV , (0b0001111000100000001010, kHF_A, 0b0000111000100000110101, kHF_C) , kRWI_W , 0 , 3 , 632 ), // #458
+ INST(Faddp_v , FSimdPair , (0b0111111000110000110110, 0b0010111000100000110101) , kRWI_W , 0 , 0 , 637 ), // #459
+ INST(Fcadd_v , SimdFcadd , (0b0010111000000000111001) , kRWI_W , 0 , 0 , 643 ), // #460
+ INST(Fccmp_v , SimdFccmpFccmpe , (0b00011110001000000000010000000000) , kRWI_R , 0 , 0 , 649 ), // #461
+ INST(Fccmpe_v , SimdFccmpFccmpe , (0b00011110001000000000010000010000) , kRWI_R , 0 , 1 , 655 ), // #462
+ INST(Fcmeq_v , SimdFcm , (0b0000111000100000111001, kHF_C, 0b0000111010100000110110) , kRWI_W , 0 , 0 , 662 ), // #463
+ INST(Fcmge_v , SimdFcm , (0b0010111000100000111001, kHF_C, 0b0010111010100000110010) , kRWI_W , 0 , 1 , 668 ), // #464
+ INST(Fcmgt_v , SimdFcm , (0b0010111010100000111001, kHF_C, 0b0000111010100000110010) , kRWI_W , 0 , 2 , 674 ), // #465
+ INST(Fcmla_v , SimdFcmla , (0b0010111000000000110001, 0b0010111100000000000100) , kRWI_X , 0 , 0 , 680 ), // #466
+ INST(Fcmle_v , SimdFcm , (0b0000000000000000000000, kHF_C, 0b0010111010100000110110) , kRWI_W , 0 , 3 , 686 ), // #467
+ INST(Fcmlt_v , SimdFcm , (0b0000000000000000000000, kHF_C, 0b0000111010100000111010) , kRWI_W , 0 , 4 , 692 ), // #468
+ INST(Fcmp_v , SimdFcmpFcmpe , (0b00011110001000000010000000000000) , kRWI_R , 0 , 0 , 698 ), // #469
+ INST(Fcmpe_v , SimdFcmpFcmpe , (0b00011110001000000010000000010000) , kRWI_R , 0 , 1 , 703 ), // #470
+ INST(Fcsel_v , SimdFcsel , (_) , kRWI_W , 0 , 0 , 709 ), // #471
+ INST(Fcvt_v , SimdFcvt , (_) , kRWI_W , 0 , 0 , 197 ), // #472
+ INST(Fcvtas_v , SimdFcvtSV , (0b0000111000100001110010, 0b0000000000000000000000, 0b0001111000100100000000, 1) , kRWI_W , 0 , 0 , 715 ), // #473
+ INST(Fcvtau_v , SimdFcvtSV , (0b0010111000100001110010, 0b0000000000000000000000, 0b0001111000100101000000, 1) , kRWI_W , 0 , 1 , 722 ), // #474
+ INST(Fcvtl_v , SimdFcvtLN , (0b0000111000100001011110, 0, 0) , kRWI_W , F(Long) , 0 , 729 ), // #475
+ INST(Fcvtl2_v , SimdFcvtLN , (0b0100111000100001011110, 0, 0) , kRWI_W , F(Long) , 1 , 735 ), // #476
+ INST(Fcvtms_v , SimdFcvtSV , (0b0000111000100001101110, 0b0000000000000000000000, 0b0001111000110000000000, 1) , kRWI_W , 0 , 2 , 742 ), // #477
+ INST(Fcvtmu_v , SimdFcvtSV , (0b0010111000100001101110, 0b0000000000000000000000, 0b0001111000110001000000, 1) , kRWI_W , 0 , 3 , 749 ), // #478
+ INST(Fcvtn_v , SimdFcvtLN , (0b0000111000100001011010, 0, 0) , kRWI_W , F(Narrow) , 2 , 203 ), // #479
+ INST(Fcvtn2_v , SimdFcvtLN , (0b0100111000100001011010, 0, 0) , kRWI_X , F(Narrow) , 3 , 210 ), // #480
+ INST(Fcvtns_v , SimdFcvtSV , (0b0000111000100001101010, 0b0000000000000000000000, 0b0001111000100000000000, 1) , kRWI_W , 0 , 4 , 756 ), // #481
+ INST(Fcvtnu_v , SimdFcvtSV , (0b0010111000100001101010, 0b0000000000000000000000, 0b0001111000100001000000, 1) , kRWI_W , 0 , 5 , 763 ), // #482
+ INST(Fcvtps_v , SimdFcvtSV , (0b0000111010100001101010, 0b0000000000000000000000, 0b0001111000101000000000, 1) , kRWI_W , 0 , 6 , 770 ), // #483
+ INST(Fcvtpu_v , SimdFcvtSV , (0b0010111010100001101010, 0b0000000000000000000000, 0b0001111000101001000000, 1) , kRWI_W , 0 , 7 , 777 ), // #484
+ INST(Fcvtxn_v , SimdFcvtLN , (0b0010111000100001011010, 1, 1) , kRWI_W , F(Narrow) , 4 , 784 ), // #485
+ INST(Fcvtxn2_v , SimdFcvtLN , (0b0110111000100001011010, 1, 0) , kRWI_X , F(Narrow) , 5 , 791 ), // #486
+ INST(Fcvtzs_v , SimdFcvtSV , (0b0000111010100001101110, 0b0000111100000000111111, 0b0001111000111000000000, 1) , kRWI_W , 0 , 8 , 799 ), // #487
+ INST(Fcvtzu_v , SimdFcvtSV , (0b0010111010100001101110, 0b0010111100000000111111, 0b0001111000111001000000, 1) , kRWI_W , 0 , 9 , 806 ), // #488
+ INST(Fdiv_v , FSimdVVV , (0b0001111000100000000110, kHF_A, 0b0010111000100000111111, kHF_C) , kRWI_W , 0 , 4 , 813 ), // #489
+ INST(Fjcvtzs_v , ISimdVVx , (0b0001111001111110000000, kOp_GpW, kOp_D) , kRWI_W , 0 , 7 , 818 ), // #490
+ INST(Fmadd_v , FSimdVVVV , (0b0001111100000000000000, kHF_A, 0b0000000000000000000000, kHF_N) , kRWI_W , 0 , 0 , 826 ), // #491
+ INST(Fmax_v , FSimdVVV , (0b0001111000100000010010, kHF_A, 0b0000111000100000111101, kHF_C) , kRWI_W , 0 , 5 , 832 ), // #492
+ INST(Fmaxnm_v , FSimdVVV , (0b0001111000100000011010, kHF_A, 0b0000111000100000110001, kHF_C) , kRWI_W , 0 , 6 , 837 ), // #493
+ INST(Fmaxnmp_v , FSimdPair , (0b0111111000110000110010, 0b0010111000100000110001) , kRWI_W , 0 , 1 , 844 ), // #494
+ INST(Fmaxnmv_v , FSimdSV , (0b0010111000110000110010) , kRWI_W , 0 , 0 , 852 ), // #495
+ INST(Fmaxp_v , FSimdPair , (0b0111111000110000111110, 0b0010111000100000111101) , kRWI_W , 0 , 2 , 860 ), // #496
+ INST(Fmaxv_v , FSimdSV , (0b0010111000110000111110) , kRWI_W , 0 , 1 , 866 ), // #497
+ INST(Fmin_v , FSimdVVV , (0b0001111000100000010110, kHF_A, 0b0000111010100000111101, kHF_C) , kRWI_W , 0 , 7 , 872 ), // #498
+ INST(Fminnm_v , FSimdVVV , (0b0001111000100000011110, kHF_A, 0b0000111010100000110001, kHF_C) , kRWI_W , 0 , 8 , 877 ), // #499
+ INST(Fminnmp_v , FSimdPair , (0b0111111010110000110010, 0b0010111010100000110001) , kRWI_W , 0 , 3 , 884 ), // #500
+ INST(Fminnmv_v , FSimdSV , (0b0010111010110000110010) , kRWI_W , 0 , 2 , 892 ), // #501
+ INST(Fminp_v , FSimdPair , (0b0111111010110000111110, 0b0010111010100000111101) , kRWI_W , 0 , 4 , 900 ), // #502
+ INST(Fminv_v , FSimdSV , (0b0010111010110000111110) , kRWI_W , 0 , 3 , 906 ), // #503
+ INST(Fmla_v , FSimdVVVe , (0b0000000000000000000000, kHF_N, 0b0000111000100000110011, 0b0000111110000000000100) , kRWI_X , F(VH0_15) , 0 , 912 ), // #504
+ INST(Fmlal_v , SimdFmlal , (0b0000111000100000111011, 0b0000111110000000000000, 1, kET_S, kET_H, kET_H) , kRWI_X , F(VH0_15) , 2 , 917 ), // #505
+ INST(Fmlal2_v , SimdFmlal , (0b0010111000100000110011, 0b0010111110000000100000, 1, kET_S, kET_H, kET_H) , kRWI_X , F(VH0_15) , 3 , 923 ), // #506
+ INST(Fmls_v , FSimdVVVe , (0b0000000000000000000000, kHF_N, 0b0000111010100000110011, 0b0000111110000000010100) , kRWI_X , F(VH0_15) , 1 , 930 ), // #507
+ INST(Fmlsl_v , SimdFmlal , (0b0000111010100000111011, 0b0000111110000000010000, 1, kET_S, kET_H, kET_H) , kRWI_X , F(VH0_15) , 4 , 935 ), // #508
+ INST(Fmlsl2_v , SimdFmlal , (0b0010111010100000110011, 0b0010111110000000110000, 1, kET_S, kET_H, kET_H) , kRWI_X , F(VH0_15) , 5 , 941 ), // #509
+ INST(Fmov_v , SimdFmov , (_) , kRWI_W , 0 , 0 , 948 ), // #510
+ INST(Fmsub_v , FSimdVVVV , (0b0001111100000000100000, kHF_A, 0b0000000000000000000000, kHF_N) , kRWI_W , 0 , 1 , 953 ), // #511
+ INST(Fmul_v , FSimdVVVe , (0b0001111000100000000010, kHF_A, 0b0010111000100000110111, 0b0000111110000000100100) , kRWI_W , F(VH0_15) , 2 , 959 ), // #512
+ INST(Fmulx_v , FSimdVVVe , (0b0101111000100000110111, kHF_C, 0b0000111000100000110111, 0b0010111110000000100100) , kRWI_W , F(VH0_15) , 3 , 964 ), // #513
+ INST(Fneg_v , FSimdVV , (0b0001111000100001010000, kHF_A, 0b0010111010100000111110, kHF_B) , kRWI_W , 0 , 1 , 970 ), // #514
+ INST(Fnmadd_v , FSimdVVVV , (0b0001111100100000000000, kHF_A, 0b0000000000000000000000, kHF_N) , kRWI_W , 0 , 2 , 975 ), // #515
+ INST(Fnmsub_v , FSimdVVVV , (0b0001111100100000100000, kHF_A, 0b0000000000000000000000, kHF_N) , kRWI_W , 0 , 3 , 982 ), // #516
+ INST(Fnmul_v , FSimdVVV , (0b0001111000100000100010, kHF_A, 0b0000000000000000000000, kHF_N) , kRWI_W , 0 , 9 , 989 ), // #517
+ INST(Frecpe_v , FSimdVV , (0b0101111010100001110110, kHF_B, 0b0000111010100001110110, kHF_B) , kRWI_W , 0 , 2 , 995 ), // #518
+ INST(Frecps_v , FSimdVVV , (0b0101111000100000111111, kHF_C, 0b0000111000100000111111, kHF_C) , kRWI_W , 0 , 10 , 1002), // #519
+ INST(Frecpx_v , FSimdVV , (0b0101111010100001111110, kHF_B, 0b0000000000000000000000, kHF_N) , kRWI_W , 0 , 3 , 1009), // #520
+ INST(Frint32x_v , FSimdVV , (0b0001111000101000110000, kHF_N, 0b0010111000100001111010, kHF_N) , kRWI_W , 0 , 4 , 1016), // #521
+ INST(Frint32z_v , FSimdVV , (0b0001111000101000010000, kHF_N, 0b0000111000100001111010, kHF_N) , kRWI_W , 0 , 5 , 1025), // #522
+ INST(Frint64x_v , FSimdVV , (0b0001111000101001110000, kHF_N, 0b0010111000100001111110, kHF_N) , kRWI_W , 0 , 6 , 1034), // #523
+ INST(Frint64z_v , FSimdVV , (0b0001111000101001010000, kHF_N, 0b0000111000100001111110, kHF_N) , kRWI_W , 0 , 7 , 1043), // #524
+ INST(Frinta_v , FSimdVV , (0b0001111000100110010000, kHF_A, 0b0010111000100001100010, kHF_B) , kRWI_W , 0 , 8 , 1052), // #525
+ INST(Frinti_v , FSimdVV , (0b0001111000100111110000, kHF_A, 0b0010111010100001100110, kHF_B) , kRWI_W , 0 , 9 , 1059), // #526
+ INST(Frintm_v , FSimdVV , (0b0001111000100101010000, kHF_A, 0b0000111000100001100110, kHF_B) , kRWI_W , 0 , 10 , 1066), // #527
+ INST(Frintn_v , FSimdVV , (0b0001111000100100010000, kHF_A, 0b0000111000100001100010, kHF_B) , kRWI_W , 0 , 11 , 1073), // #528
+ INST(Frintp_v , FSimdVV , (0b0001111000100100110000, kHF_A, 0b0000111010100001100010, kHF_B) , kRWI_W , 0 , 12 , 1080), // #529
+ INST(Frintx_v , FSimdVV , (0b0001111000100111010000, kHF_A, 0b0010111000100001100110, kHF_B) , kRWI_W , 0 , 13 , 1087), // #530
+ INST(Frintz_v , FSimdVV , (0b0001111000100101110000, kHF_A, 0b0000111010100001100110, kHF_B) , kRWI_W , 0 , 14 , 1094), // #531
+ INST(Frsqrte_v , FSimdVV , (0b0111111010100001110110, kHF_B, 0b0010111010100001110110, kHF_B) , kRWI_W , 0 , 15 , 1101), // #532
+ INST(Frsqrts_v , FSimdVVV , (0b0101111010100000111111, kHF_C, 0b0000111010100000111111, kHF_C) , kRWI_W , 0 , 11 , 1109), // #533
+ INST(Fsqrt_v , FSimdVV , (0b0001111000100001110000, kHF_A, 0b0010111010100001111110, kHF_B) , kRWI_W , 0 , 16 , 1117), // #534
+ INST(Fsub_v , FSimdVVV , (0b0001111000100000001110, kHF_A, 0b0000111010100000110101, kHF_C) , kRWI_W , 0 , 12 , 1123), // #535
+ INST(Ins_v , SimdIns , (_) , kRWI_X , 0 , 0 , 1145), // #536
+ INST(Ld1_v , SimdLdNStN , (0b0000110101000000000000, 0b0000110001000000001000, 1, 0) , kRWI_LDn , F(Consecutive) , 0 , 1153), // #537
+ INST(Ld1r_v , SimdLdNStN , (0b0000110101000000110000, 0b0000000000000000000000, 1, 1) , kRWI_LDn , F(Consecutive) , 1 , 1157), // #538
+ INST(Ld2_v , SimdLdNStN , (0b0000110101100000000000, 0b0000110001000000100000, 2, 0) , kRWI_LDn , F(Consecutive) , 2 , 1162), // #539
+ INST(Ld2r_v , SimdLdNStN , (0b0000110101100000110000, 0b0000000000000000000000, 2, 1) , kRWI_LDn , F(Consecutive) , 3 , 1166), // #540
+ INST(Ld3_v , SimdLdNStN , (0b0000110101000000001000, 0b0000110001000000010000, 3, 0) , kRWI_LDn , F(Consecutive) , 4 , 1171), // #541
+ INST(Ld3r_v , SimdLdNStN , (0b0000110101000000111000, 0b0000000000000000000000, 3, 1) , kRWI_LDn , F(Consecutive) , 5 , 1175), // #542
+ INST(Ld4_v , SimdLdNStN , (0b0000110101100000001000, 0b0000110001000000000000, 4, 0) , kRWI_LDn , F(Consecutive) , 6 , 1180), // #543
+ INST(Ld4r_v , SimdLdNStN , (0b0000110101100000111000, 0b0000000000000000000000, 4, 1) , kRWI_LDn , F(Consecutive) , 7 , 1184), // #544
+ INST(Ldnp_v , SimdLdpStp , (0b0010110001, 0b0000000000) , kRWI_WW , 0 , 0 , 1537), // #545
+ INST(Ldp_v , SimdLdpStp , (0b0010110101, 0b0010110011) , kRWI_WW , 0 , 1 , 1542), // #546
+ INST(Ldr_v , SimdLdSt , (0b0011110101, 0b00111100010, 0b00111100011, 0b00011100, Inst::kIdLdur_v) , kRWI_W , 0 , 0 , 1552), // #547
+ INST(Ldur_v , SimdLdurStur , (0b0011110001000000000000) , kRWI_W , 0 , 0 , 2142), // #548
+ INST(Mla_v , ISimdVVVe , (0b0000111000100000100101, kVO_V_BHS, 0b0010111100000000000000, kVO_V_HS) , kRWI_X , F(VH0_15) , 0 , 246 ), // #549
+ INST(Mls_v , ISimdVVVe , (0b0010111000100000100101, kVO_V_BHS, 0b0010111100000000010000, kVO_V_HS) , kRWI_X , F(VH0_15) , 1 , 931 ), // #550
+ INST(Mov_v , SimdMov , (_) , kRWI_W , 0 , 0 , 949 ), // #551
+ INST(Movi_v , SimdMoviMvni , (0b0000111100000000000001, 0) , kRWI_W , 0 , 0 , 2221), // #552
+ INST(Mul_v , ISimdVVVe , (0b0000111000100000100111, kVO_V_BHS, 0b0000111100000000100000, kVO_V_HS) , kRWI_W , F(VH0_15) , 2 , 991 ), // #553
+ INST(Mvn_v , ISimdVV , (0b0010111000100000010110, kVO_V_B) , kRWI_W , 0 , 4 , 2249), // #554
+ INST(Mvni_v , SimdMoviMvni , (0b0000111100000000000001, 1) , kRWI_W , 0 , 1 , 2253), // #555
+ INST(Neg_v , ISimdVV , (0b0010111000100000101110, kVO_V_Any) , kRWI_W , 0 , 5 , 540 ), // #556
+ INST(Not_v , ISimdVV , (0b0010111000100000010110, kVO_V_B) , kRWI_W , 0 , 6 , 2276), // #557
+ INST(Orn_v , ISimdVVV , (0b0000111011100000000111, kVO_V_B) , kRWI_W , 0 , 9 , 2280), // #558
+ INST(Orr_v , SimdBicOrr , (0b0000111010100000000111, 0b0000111100000000000001) , kRWI_W , 0 , 1 , 2284), // #559
+ INST(Pmul_v , ISimdVVV , (0b0010111000100000100111, kVO_V_B) , kRWI_W , 0 , 10 , 2320), // #560
+ INST(Pmull_v , ISimdVVV , (0b0000111000100000111000, kVO_V_B8D1) , kRWI_W , F(Long) , 11 , 2325), // #561
+ INST(Pmull2_v , ISimdVVV , (0b0100111000100000111000, kVO_V_B16D2) , kRWI_W , F(Long) , 12 , 2331), // #562
+ INST(Raddhn_v , ISimdVVV , (0b0010111000100000010000, kVO_V_B8H4S2) , kRWI_W , F(Narrow) , 13 , 2344), // #563
+ INST(Raddhn2_v , ISimdVVV , (0b0110111000100000010000, kVO_V_B16H8S4) , kRWI_X , F(Narrow) , 14 , 2351), // #564
+ INST(Rax1_v , ISimdVVV , (0b1100111001100000100011, kVO_V_D2) , kRWI_W , 0 , 15 , 2359), // #565
+ INST(Rbit_v , ISimdVV , (0b0010111001100000010110, kVO_V_B) , kRWI_W , 0 , 7 , 2364), // #566
+ INST(Rev16_v , ISimdVV , (0b0000111000100000000110, kVO_V_B) , kRWI_W , 0 , 8 , 2373), // #567
+ INST(Rev32_v , ISimdVV , (0b0010111000100000000010, kVO_V_BH) , kRWI_W , 0 , 9 , 2379), // #568
+ INST(Rev64_v , ISimdVV , (0b0000111000100000000010, kVO_V_BHS) , kRWI_W , 0 , 10 , 2385), // #569
+ INST(Rshrn_v , SimdShift , (0b0000000000000000000000, 0b0000111100000000100011, 1, kVO_V_B8H4S2) , kRWI_W , F(Narrow) , 0 , 2960), // #570
+ INST(Rshrn2_v , SimdShift , (0b0000000000000000000000, 0b0100111100000000100011, 1, kVO_V_B16H8S4) , kRWI_X , F(Narrow) , 1 , 2968), // #571
+ INST(Rsubhn_v , ISimdVVV , (0b0010111000100000011000, kVO_V_B8H4S2) , kRWI_W , F(Narrow) , 16 , 2400), // #572
+ INST(Rsubhn2_v , ISimdVVV , (0b0110111000100000011000, kVO_V_B16H8S4) , kRWI_X , F(Narrow) , 17 , 2407), // #573
+ INST(Saba_v , ISimdVVV , (0b0000111000100000011111, kVO_V_BHS) , kRWI_X , 0 , 18 , 2415), // #574
+ INST(Sabal_v , ISimdVVV , (0b0000111000100000010100, kVO_V_B8H4S2) , kRWI_X , F(Long) , 19 , 2420), // #575
+ INST(Sabal2_v , ISimdVVV , (0b0100111000100000010100, kVO_V_B16H8S4) , kRWI_X , F(Long) , 20 , 2426), // #576
+ INST(Sabd_v , ISimdVVV , (0b0000111000100000011101, kVO_V_BHS) , kRWI_W , 0 , 21 , 2433), // #577
+ INST(Sabdl_v , ISimdVVV , (0b0000111000100000011100, kVO_V_B8H4S2) , kRWI_W , F(Long) , 22 , 2438), // #578
+ INST(Sabdl2_v , ISimdVVV , (0b0100111000100000011100, kVO_V_B16H8S4) , kRWI_W , F(Long) , 23 , 2444), // #579
+ INST(Sadalp_v , ISimdVV , (0b0000111000100000011010, kVO_V_BHS) , kRWI_X , F(Long) | F(Pair) , 11 , 2451), // #580
+ INST(Saddl_v , ISimdVVV , (0b0000111000100000000000, kVO_V_B8H4S2) , kRWI_W , F(Long) , 24 , 2458), // #581
+ INST(Saddl2_v , ISimdVVV , (0b0100111000100000000000, kVO_V_B16H8S4) , kRWI_W , F(Long) , 25 , 2464), // #582
+ INST(Saddlp_v , ISimdVV , (0b0000111000100000001010, kVO_V_BHS) , kRWI_W , F(Long) | F(Pair) , 12 , 2471), // #583
+ INST(Saddlv_v , ISimdSV , (0b0000111000110000001110, kVO_V_BH_4S) , kRWI_W , F(Long) , 1 , 2478), // #584
+ INST(Saddw_v , ISimdWWV , (0b0000111000100000000100, kVO_V_B8H4S2) , kRWI_W , 0 , 0 , 2485), // #585
+ INST(Saddw2_v , ISimdWWV , (0b0000111000100000000100, kVO_V_B16H8S4) , kRWI_W , 0 , 1 , 2491), // #586
+ INST(Scvtf_v , SimdFcvtSV , (0b0000111000100001110110, 0b0000111100000000111001, 0b0001111000100010000000, 0) , kRWI_W , 0 , 10 , 2523), // #587
+ INST(Sdot_v , SimdDot , (0b0000111010000000100101, 0b0000111110000000111000, kET_S, kET_B, kET_4B) , kRWI_X , 0 , 1 , 4218), // #588
+ INST(Sha1c_v , ISimdVVVx , (0b0101111000000000000000, kOp_Q, kOp_S, kOp_V4S) , kRWI_X , 0 , 1 , 2556), // #589
+ INST(Sha1h_v , ISimdVVx , (0b0101111000101000000010, kOp_S, kOp_S) , kRWI_W , 0 , 8 , 2562), // #590
+ INST(Sha1m_v , ISimdVVVx , (0b0101111000000000001000, kOp_Q, kOp_S, kOp_V4S) , kRWI_X , 0 , 2 , 2568), // #591
+ INST(Sha1p_v , ISimdVVVx , (0b0101111000000000000100, kOp_Q, kOp_S, kOp_V4S) , kRWI_X , 0 , 3 , 2574), // #592
+ INST(Sha1su0_v , ISimdVVVx , (0b0101111000000000001100, kOp_V4S, kOp_V4S, kOp_V4S) , kRWI_X , 0 , 4 , 2580), // #593
+ INST(Sha1su1_v , ISimdVVx , (0b0101111000101000000110, kOp_V4S, kOp_V4S) , kRWI_X , 0 , 9 , 2588), // #594
+ INST(Sha256h_v , ISimdVVVx , (0b0101111000000000010000, kOp_Q, kOp_Q, kOp_V4S) , kRWI_X , 0 , 5 , 2596), // #595
+ INST(Sha256h2_v , ISimdVVVx , (0b0101111000000000010100, kOp_Q, kOp_Q, kOp_V4S) , kRWI_X , 0 , 6 , 2604), // #596
+ INST(Sha256su0_v , ISimdVVx , (0b0101111000101000001010, kOp_V4S, kOp_V4S) , kRWI_X , 0 , 10 , 2613), // #597
+ INST(Sha256su1_v , ISimdVVVx , (0b0101111000000000011000, kOp_V4S, kOp_V4S, kOp_V4S) , kRWI_X , 0 , 7 , 2623), // #598
+ INST(Sha512h_v , ISimdVVVx , (0b1100111001100000100000, kOp_Q, kOp_Q, kOp_V2D) , kRWI_X , 0 , 8 , 2633), // #599
+ INST(Sha512h2_v , ISimdVVVx , (0b1100111001100000100001, kOp_Q, kOp_Q, kOp_V2D) , kRWI_X , 0 , 9 , 2641), // #600
+ INST(Sha512su0_v , ISimdVVx , (0b1100111011000000100000, kOp_V2D, kOp_V2D) , kRWI_X , 0 , 11 , 2650), // #601
+ INST(Sha512su1_v , ISimdVVVx , (0b1100111001100000100010, kOp_V2D, kOp_V2D, kOp_V2D) , kRWI_X , 0 , 10 , 2660), // #602
+ INST(Shadd_v , ISimdVVV , (0b0000111000100000000001, kVO_V_BHS) , kRWI_W , 0 , 26 , 2670), // #603
+ INST(Shl_v , SimdShift , (0b0000000000000000000000, 0b0000111100000000010101, 0, kVO_V_Any) , kRWI_W , 0 , 2 , 2954), // #604
+ INST(Shll_v , SimdShiftES , (0b0010111000100001001110, kVO_V_B8H4S2) , kRWI_W , F(Long) , 0 , 3108), // #605
+ INST(Shll2_v , SimdShiftES , (0b0110111000100001001110, kVO_V_B16H8S4) , kRWI_W , F(Long) , 1 , 3114), // #606
+ INST(Shrn_v , SimdShift , (0b0000000000000000000000, 0b0000111100000000100001, 1, kVO_V_B8H4S2) , kRWI_W , F(Narrow) , 3 , 2961), // #607
+ INST(Shrn2_v , SimdShift , (0b0000000000000000000000, 0b0100111100000000100001, 1, kVO_V_B16H8S4) , kRWI_X , F(Narrow) , 4 , 2969), // #608
+ INST(Shsub_v , ISimdVVV , (0b0000111000100000001001, kVO_V_BHS) , kRWI_W , 0 , 27 , 2676), // #609
+ INST(Sli_v , SimdShift , (0b0000000000000000000000, 0b0010111100000000010101, 0, kVO_V_Any) , kRWI_X , 0 , 5 , 2682), // #610
+ INST(Sm3partw1_v , ISimdVVVx , (0b1100111001100000110000, kOp_V4S, kOp_V4S, kOp_V4S) , kRWI_X , 0 , 11 , 2686), // #611
+ INST(Sm3partw2_v , ISimdVVVx , (0b1100111001100000110001, kOp_V4S, kOp_V4S, kOp_V4S) , kRWI_X , 0 , 12 , 2696), // #612
+ INST(Sm3ss1_v , ISimdVVVVx , (0b1100111001000000000000, kOp_V4S, kOp_V4S, kOp_V4S, kOp_V4S) , kRWI_W , 0 , 0 , 2706), // #613
+ INST(Sm3tt1a_v , SimdSm3tt , (0b1100111001000000100000) , kRWI_X , 0 , 0 , 2713), // #614
+ INST(Sm3tt1b_v , SimdSm3tt , (0b1100111001000000100001) , kRWI_X , 0 , 1 , 2721), // #615
+ INST(Sm3tt2a_v , SimdSm3tt , (0b1100111001000000100010) , kRWI_X , 0 , 2 , 2729), // #616
+ INST(Sm3tt2b_v , SimdSm3tt , (0b1100111001000000100011) , kRWI_X , 0 , 3 , 2737), // #617
+ INST(Sm4e_v , ISimdVVx , (0b1100111011000000100001, kOp_V4S, kOp_V4S) , kRWI_X , 0 , 12 , 2745), // #618
+ INST(Sm4ekey_v , ISimdVVVx , (0b1100111001100000110010, kOp_V4S, kOp_V4S, kOp_V4S) , kRWI_X , 0 , 13 , 2750), // #619
+ INST(Smax_v , ISimdVVV , (0b0000111000100000011001, kVO_V_BHS) , kRWI_W , 0 , 28 , 1690), // #620
+ INST(Smaxp_v , ISimdVVV , (0b0000111000100000101001, kVO_V_BHS) , kRWI_W , 0 , 29 , 2765), // #621
+ INST(Smaxv_v , ISimdSV , (0b0000111000110000101010, kVO_V_BH_4S) , kRWI_W , 0 , 2 , 2771), // #622
+ INST(Smin_v , ISimdVVV , (0b0000111000100000011011, kVO_V_BHS) , kRWI_W , 0 , 30 , 1794), // #623
+ INST(Sminp_v , ISimdVVV , (0b0000111000100000101011, kVO_V_BHS) , kRWI_W , 0 , 31 , 2777), // #624
+ INST(Sminv_v , ISimdSV , (0b0000111000110001101010, kVO_V_BH_4S) , kRWI_W , 0 , 3 , 2783), // #625
+ INST(Smlal_v , ISimdVVVe , (0b0000111000100000100000, kVO_V_B8H4S2, 0b0000111100000000001000, kVO_V_H4S2) , kRWI_X , F(Long) | F(VH0_15) , 3 , 2789), // #626
+ INST(Smlal2_v , ISimdVVVe , (0b0100111000100000100000, kVO_V_B16H8S4, 0b0100111100000000001000, kVO_V_H8S4) , kRWI_X , F(Long) | F(VH0_15) , 4 , 2795), // #627
+ INST(Smlsl_v , ISimdVVVe , (0b0000111000100000101000, kVO_V_B8H4S2, 0b0000111100000000011000, kVO_V_H4S2) , kRWI_X , F(Long) | F(VH0_15) , 5 , 2802), // #628
+ INST(Smlsl2_v , ISimdVVVe , (0b0100111000100000101000, kVO_V_B16H8S4, 0b0100111100000000011000, kVO_V_H8S4) , kRWI_X , F(Long) | F(VH0_15) , 6 , 2808), // #629
+ INST(Smmla_v , ISimdVVVx , (0b0100111010000000101001, kOp_V4S, kOp_V16B, kOp_V16B) , kRWI_X , 0 , 14 , 4247), // #630
+ INST(Smov_v , SimdSmovUmov , (0b0000111000000000001011, kVO_V_BHS, 1) , kRWI_W , 0 , 0 , 2822), // #631
+ INST(Smull_v , ISimdVVVe , (0b0000111000100000110000, kVO_V_B8H4S2, 0b0000111100000000101000, kVO_V_H4S2) , kRWI_W , F(Long) | F(VH0_15) , 7 , 2840), // #632
+ INST(Smull2_v , ISimdVVVe , (0b0100111000100000110000, kVO_V_B16H8S4, 0b0100111100000000101000, kVO_V_H8S4) , kRWI_W , F(Long) | F(VH0_15) , 8 , 2846), // #633
+ INST(Sqabs_v , ISimdVV , (0b0000111000100000011110, kVO_SV_Any) , kRWI_W , 0 , 13 , 2853), // #634
+ INST(Sqadd_v , ISimdVVV , (0b0000111000100000000011, kVO_SV_Any) , kRWI_W , 0 , 32 , 4254), // #635
+ INST(Sqdmlal_v , ISimdVVVe , (0b0000111000100000100100, kVO_SV_BHS, 0b0000111100000000001100, kVO_V_H4S2) , kRWI_X , F(Long) | F(VH0_15) , 9 , 2859), // #636
+ INST(Sqdmlal2_v , ISimdVVVe , (0b0100111000100000100100, kVO_V_B16H8S4, 0b0100111100000000001100, kVO_V_H8S4) , kRWI_X , F(Long) | F(VH0_15) , 10 , 2867), // #637
+ INST(Sqdmlsl_v , ISimdVVVe , (0b0000111000100000101100, kVO_SV_BHS, 0b0000111100000000011100, kVO_V_H4S2) , kRWI_X , F(Long) | F(VH0_15) , 11 , 2876), // #638
+ INST(Sqdmlsl2_v , ISimdVVVe , (0b0100111000100000101100, kVO_V_B16H8S4, 0b0100111100000000011100, kVO_V_H8S4) , kRWI_X , F(Long) | F(VH0_15) , 12 , 2884), // #639
+ INST(Sqdmulh_v , ISimdVVVe , (0b0000111000100000101101, kVO_SV_HS, 0b0000111100000000110000, kVO_SV_HS) , kRWI_W , F(VH0_15) , 13 , 2893), // #640
+ INST(Sqdmull_v , ISimdVVVe , (0b0000111000100000110100, kVO_SV_BHS, 0b0000111100000000101100, kVO_V_H4S2) , kRWI_W , F(Long) | F(VH0_15) , 14 , 2901), // #641
+ INST(Sqdmull2_v , ISimdVVVe , (0b0100111000100000110100, kVO_V_B16H8S4, 0b0100111100000000101100, kVO_V_H8S4) , kRWI_W , F(Long) | F(VH0_15) , 15 , 2909), // #642
+ INST(Sqneg_v , ISimdVV , (0b0010111000100000011110, kVO_SV_Any) , kRWI_W , 0 , 14 , 2918), // #643
+ INST(Sqrdmlah_v , ISimdVVVe , (0b0010111000000000100001, kVO_SV_HS, 0b0010111100000000110100, kVO_SV_HS) , kRWI_X , F(VH0_15) , 16 , 2924), // #644
+ INST(Sqrdmlsh_v , ISimdVVVe , (0b0010111000000000100011, kVO_SV_HS, 0b0010111100000000111100, kVO_SV_HS) , kRWI_X , F(VH0_15) , 17 , 2933), // #645
+ INST(Sqrdmulh_v , ISimdVVVe , (0b0010111000100000101101, kVO_SV_HS, 0b0000111100000000110100, kVO_SV_HS) , kRWI_W , F(VH0_15) , 18 , 2942), // #646
+ INST(Sqrshl_v , SimdShift , (0b0000111000100000010111, 0b0000000000000000000000, 1, kVO_SV_Any) , kRWI_W , 0 , 6 , 2951), // #647
+ INST(Sqrshrn_v , SimdShift , (0b0000000000000000000000, 0b0000111100000000100111, 1, kVO_SV_B8H4S2) , kRWI_W , F(Narrow) , 7 , 2958), // #648
+ INST(Sqrshrn2_v , SimdShift , (0b0000000000000000000000, 0b0100111100000000100111, 1, kVO_V_B16H8S4) , kRWI_X , F(Narrow) , 8 , 2966), // #649
+ INST(Sqrshrun_v , SimdShift , (0b0000000000000000000000, 0b0010111100000000100011, 1, kVO_SV_B8H4S2) , kRWI_W , F(Narrow) , 9 , 2975), // #650
+ INST(Sqrshrun2_v , SimdShift , (0b0000000000000000000000, 0b0110111100000000100011, 1, kVO_V_B16H8S4) , kRWI_X , F(Narrow) , 10 , 2984), // #651
+ INST(Sqshl_v , SimdShift , (0b0000111000100000010011, 0b0000111100000000011101, 0, kVO_SV_Any) , kRWI_W , 0 , 11 , 2994), // #652
+ INST(Sqshlu_v , SimdShift , (0b0000000000000000000000, 0b0010111100000000011001, 0, kVO_SV_Any) , kRWI_W , 0 , 12 , 3000), // #653
+ INST(Sqshrn_v , SimdShift , (0b0000000000000000000000, 0b0000111100000000100101, 1, kVO_SV_B8H4S2) , kRWI_W , F(Narrow) , 13 , 3007), // #654
+ INST(Sqshrn2_v , SimdShift , (0b0000000000000000000000, 0b0100111100000000100101, 1, kVO_V_B16H8S4) , kRWI_X , F(Narrow) , 14 , 3014), // #655
+ INST(Sqshrun_v , SimdShift , (0b0000000000000000000000, 0b0010111100000000100001, 1, kVO_SV_B8H4S2) , kRWI_W , F(Narrow) , 15 , 3022), // #656
+ INST(Sqshrun2_v , SimdShift , (0b0000000000000000000000, 0b0110111100000000100001, 1, kVO_V_B16H8S4) , kRWI_X , F(Narrow) , 16 , 3030), // #657
+ INST(Sqsub_v , ISimdVVV , (0b0000111000100000001011, kVO_SV_Any) , kRWI_W , 0 , 33 , 3039), // #658
+ INST(Sqxtn_v , ISimdVV , (0b0000111000100001010010, kVO_SV_B8H4S2) , kRWI_W , F(Narrow) , 15 , 3045), // #659
+ INST(Sqxtn2_v , ISimdVV , (0b0100111000100001010010, kVO_V_B16H8S4) , kRWI_X , F(Narrow) , 16 , 3051), // #660
+ INST(Sqxtun_v , ISimdVV , (0b0010111000100001001010, kVO_SV_B8H4S2) , kRWI_W , F(Narrow) , 17 , 3058), // #661
+ INST(Sqxtun2_v , ISimdVV , (0b0110111000100001001010, kVO_V_B16H8S4) , kRWI_X , F(Narrow) , 18 , 3065), // #662
+ INST(Srhadd_v , ISimdVVV , (0b0000111000100000000101, kVO_V_BHS) , kRWI_W , 0 , 34 , 3073), // #663
+ INST(Sri_v , SimdShift , (0b0000000000000000000000, 0b0010111100000000010001, 1, kVO_V_Any) , kRWI_W , 0 , 17 , 3080), // #664
+ INST(Srshl_v , SimdShift , (0b0000111000100000010101, 0b0000000000000000000000, 0, kVO_V_Any) , kRWI_W , 0 , 18 , 3084), // #665
+ INST(Srshr_v , SimdShift , (0b0000000000000000000000, 0b0000111100000000001001, 1, kVO_V_Any) , kRWI_W , 0 , 19 , 3090), // #666
+ INST(Srsra_v , SimdShift , (0b0000000000000000000000, 0b0000111100000000001101, 1, kVO_V_Any) , kRWI_X , 0 , 20 , 3096), // #667
+ INST(Sshl_v , SimdShift , (0b0000111000100000010001, 0b0000000000000000000000, 0, kVO_V_Any) , kRWI_W , 0 , 21 , 3102), // #668
+ INST(Sshll_v , SimdShift , (0b0000000000000000000000, 0b0000111100000000101001, 0, kVO_V_B8H4S2) , kRWI_W , F(Long) , 22 , 3107), // #669
+ INST(Sshll2_v , SimdShift , (0b0000000000000000000000, 0b0100111100000000101001, 0, kVO_V_B16H8S4) , kRWI_W , F(Long) , 23 , 3113), // #670
+ INST(Sshr_v , SimdShift , (0b0000000000000000000000, 0b0000111100000000000001, 1, kVO_V_Any) , kRWI_W , 0 , 24 , 3120), // #671
+ INST(Ssra_v , SimdShift , (0b0000000000000000000000, 0b0000111100000000000101, 1, kVO_V_Any) , kRWI_X , 0 , 25 , 3125), // #672
+ INST(Ssubl_v , ISimdVVV , (0b0000111000100000001000, kVO_V_B8H4S2) , kRWI_W , F(Long) , 35 , 3130), // #673
+ INST(Ssubl2_v , ISimdVVV , (0b0100111000100000001000, kVO_V_B16H8S4) , kRWI_W , F(Long) , 36 , 3136), // #674
+ INST(Ssubw_v , ISimdWWV , (0b0000111000100000001100, kVO_V_B8H4S2) , kRWI_W , 0 , 2 , 3143), // #675
+ INST(Ssubw2_v , ISimdWWV , (0b0000111000100000001100, kVO_V_B16H8S4) , kRWI_X , 0 , 3 , 3149), // #676
+ INST(St1_v , SimdLdNStN , (0b0000110100000000000000, 0b0000110000000000001000, 1, 0) , kRWI_STn , F(Consecutive) , 8 , 3156), // #677
+ INST(St2_v , SimdLdNStN , (0b0000110100100000000000, 0b0000110000000000100000, 2, 0) , kRWI_STn , F(Consecutive) , 9 , 3160), // #678
+ INST(St3_v , SimdLdNStN , (0b0000110100000000001000, 0b0000110000000000010000, 3, 0) , kRWI_STn , F(Consecutive) , 10 , 3169), // #679
+ INST(St4_v , SimdLdNStN , (0b0000110100100000001000, 0b0000110000000000000000, 4, 0) , kRWI_STn , F(Consecutive) , 11 , 3173), // #680
+ INST(Stnp_v , SimdLdpStp , (0b0010110000, 0b0000000000) , kRWI_RRW , 0 , 2 , 3383), // #681
+ INST(Stp_v , SimdLdpStp , (0b0010110100, 0b0010110010) , kRWI_RRW , 0 , 3 , 3388), // #682
+ INST(Str_v , SimdLdSt , (0b0011110100, 0b00111100000, 0b00111100001, 0b00000000, Inst::kIdStur_v) , kRWI_RW , 0 , 1 , 3392), // #683
+ INST(Stur_v , SimdLdurStur , (0b0011110000000000000000) , kRWI_RW , 0 , 1 , 3662), // #684
+ INST(Sub_v , ISimdVVV , (0b0010111000100000100001, kVO_V_Any) , kRWI_W , 0 , 37 , 985 ), // #685
+ INST(Subhn_v , ISimdVVV , (0b0000111000100000011000, kVO_V_B8H4S2) , kRWI_W , F(Narrow) , 38 , 2401), // #686
+ INST(Subhn2_v , ISimdVVV , (0b0000111000100000011000, kVO_V_B16H8S4) , kRWI_X , F(Narrow) , 39 , 2408), // #687
+ INST(Sudot_v , SimdDot , (0b0000000000000000000000, 0b0000111100000000111100, kET_S, kET_B, kET_4B) , kRWI_X , 0 , 2 , 3739), // #688
+ INST(Suqadd_v , ISimdVV , (0b0000111000100000001110, kVO_SV_Any) , kRWI_X , 0 , 19 , 3745), // #689
+ INST(Sxtl_v , SimdSxtlUxtl , (0b0000111100000000101001, kVO_V_B8H4S2) , kRWI_W , F(Long) , 0 , 3834), // #690
+ INST(Sxtl2_v , SimdSxtlUxtl , (0b0100111100000000101001, kVO_V_B16H8S4) , kRWI_W , F(Long) , 1 , 3839), // #691
+ INST(Tbl_v , SimdTblTbx , (0b0000111000000000000000) , kRWI_W , 0 , 0 , 3854), // #692
+ INST(Tbx_v , SimdTblTbx , (0b0000111000000000000100) , kRWI_W , 0 , 1 , 3863), // #693
+ INST(Trn1_v , ISimdVVV , (0b0000111000000000001010, kVO_V_BHS_D2) , kRWI_W , 0 , 40 , 3876), // #694
+ INST(Trn2_v , ISimdVVV , (0b0000111000000000011010, kVO_V_BHS_D2) , kRWI_W , 0 , 41 , 3881), // #695
+ INST(Uaba_v , ISimdVVV , (0b0010111000100000011111, kVO_V_BHS) , kRWI_X , 0 , 42 , 3886), // #696
+ INST(Uabal_v , ISimdVVV , (0b0010111000100000010100, kVO_V_B8H4S2) , kRWI_X , F(Long) , 43 , 3891), // #697
+ INST(Uabal2_v , ISimdVVV , (0b0110111000100000010100, kVO_V_B16H8S4) , kRWI_X , F(Long) , 44 , 3897), // #698
+ INST(Uabd_v , ISimdVVV , (0b0010111000100000011101, kVO_V_BHS) , kRWI_W , 0 , 45 , 3904), // #699
+ INST(Uabdl_v , ISimdVVV , (0b0010111000100000011100, kVO_V_B8H4S2) , kRWI_W , F(Long) , 46 , 3909), // #700
+ INST(Uabdl2_v , ISimdVVV , (0b0110111000100000011100, kVO_V_B16H8S4) , kRWI_W , F(Long) , 47 , 3915), // #701
+ INST(Uadalp_v , ISimdVV , (0b0010111000100000011010, kVO_V_BHS) , kRWI_X , F(Long) | F(Pair) , 20 , 3922), // #702
+ INST(Uaddl_v , ISimdVVV , (0b0010111000100000000000, kVO_V_B8H4S2) , kRWI_W , F(Long) , 48 , 3929), // #703
+ INST(Uaddl2_v , ISimdVVV , (0b0110111000100000000000, kVO_V_B16H8S4) , kRWI_W , F(Long) , 49 , 3935), // #704
+ INST(Uaddlp_v , ISimdVV , (0b0010111000100000001010, kVO_V_BHS) , kRWI_W , F(Long) | F(Pair) , 21 , 3942), // #705
+ INST(Uaddlv_v , ISimdSV , (0b0010111000110000001110, kVO_V_BH_4S) , kRWI_W , F(Long) , 4 , 3949), // #706
+ INST(Uaddw_v , ISimdWWV , (0b0010111000100000000100, kVO_V_B8H4S2) , kRWI_W , 0 , 4 , 3956), // #707
+ INST(Uaddw2_v , ISimdWWV , (0b0010111000100000000100, kVO_V_B16H8S4) , kRWI_W , 0 , 5 , 3962), // #708
+ INST(Ucvtf_v , SimdFcvtSV , (0b0010111000100001110110, 0b0010111100000000111001, 0b0001111000100011000000, 0) , kRWI_W , 0 , 11 , 3985), // #709
+ INST(Udot_v , SimdDot , (0b0010111010000000100101, 0b0010111110000000111000, kET_S, kET_B, kET_4B) , kRWI_X , 0 , 3 , 3740), // #710
+ INST(Uhadd_v , ISimdVVV , (0b0010111000100000000001, kVO_V_BHS) , kRWI_W , 0 , 50 , 4000), // #711
+ INST(Uhsub_v , ISimdVVV , (0b0010111000100000001001, kVO_V_BHS) , kRWI_W , 0 , 51 , 4006), // #712
+ INST(Umax_v , ISimdVVV , (0b0010111000100000011001, kVO_V_BHS) , kRWI_W , 0 , 52 , 1936), // #713
+ INST(Umaxp_v , ISimdVVV , (0b0010111000100000101001, kVO_V_BHS) , kRWI_W , 0 , 53 , 4019), // #714
+ INST(Umaxv_v , ISimdSV , (0b0010111000110000101010, kVO_V_BH_4S) , kRWI_W , 0 , 5 , 4025), // #715
+ INST(Umin_v , ISimdVVV , (0b0010111000100000011011, kVO_V_BHS) , kRWI_W , 0 , 54 , 2040), // #716
+ INST(Uminp_v , ISimdVVV , (0b0010111000100000101011, kVO_V_BHS) , kRWI_W , 0 , 55 , 4031), // #717
+ INST(Uminv_v , ISimdSV , (0b0010111000110001101010, kVO_V_BH_4S) , kRWI_W , 0 , 6 , 4037), // #718
+ INST(Umlal_v , ISimdVVVe , (0b0010111000100000100000, kVO_V_B8H4S2, 0b0010111100000000001000, kVO_V_H4S2) , kRWI_X , F(Long) | F(VH0_15) , 19 , 4043), // #719
+ INST(Umlal2_v , ISimdVVVe , (0b0110111000100000100000, kVO_V_B16H8S4, 0b0010111100000000001000, kVO_V_H8S4) , kRWI_X , F(Long) | F(VH0_15) , 20 , 4049), // #720
+ INST(Umlsl_v , ISimdVVVe , (0b0010111000100000101000, kVO_V_B8H4S2, 0b0010111100000000011000, kVO_V_H4S2) , kRWI_X , F(Long) | F(VH0_15) , 21 , 4056), // #721
+ INST(Umlsl2_v , ISimdVVVe , (0b0110111000100000101000, kVO_V_B16H8S4, 0b0110111100000000011000, kVO_V_H8S4) , kRWI_X , F(Long) | F(VH0_15) , 22 , 4062), // #722
+ INST(Ummla_v , ISimdVVVx , (0b0110111010000000101001, kOp_V4S, kOp_V16B, kOp_V16B) , kRWI_X , 0 , 15 , 4069), // #723
+ INST(Umov_v , SimdSmovUmov , (0b0000111000000000001111, kVO_V_Any, 0) , kRWI_W , 0 , 1 , 4082), // #724
+ INST(Umull_v , ISimdVVVe , (0b0010111000100000110000, kVO_V_B8H4S2, 0b0010111100000000101000, kVO_V_H4S2) , kRWI_W , F(Long) | F(VH0_15) , 23 , 4100), // #725
+ INST(Umull2_v , ISimdVVVe , (0b0110111000100000110000, kVO_V_B16H8S4, 0b0110111100000000101000, kVO_V_H8S4) , kRWI_W , F(Long) | F(VH0_15) , 24 , 4106), // #726
+ INST(Uqadd_v , ISimdVVV , (0b0010111000100000000011, kVO_SV_Any) , kRWI_W , 0 , 56 , 3746), // #727
+ INST(Uqrshl_v , SimdShift , (0b0010111000100000010111, 0b0000000000000000000000, 0, kVO_SV_Any) , kRWI_W , 0 , 26 , 4113), // #728
+ INST(Uqrshrn_v , SimdShift , (0b0000000000000000000000, 0b0010111100000000100111, 1, kVO_SV_B8H4S2) , kRWI_W , F(Narrow) , 27 , 4120), // #729
+ INST(Uqrshrn2_v , SimdShift , (0b0000000000000000000000, 0b0110111100000000100111, 1, kVO_V_B16H8S4) , kRWI_X , F(Narrow) , 28 , 4128), // #730
+ INST(Uqshl_v , SimdShift , (0b0010111000100000010011, 0b0010111100000000011101, 0, kVO_SV_Any) , kRWI_W , 0 , 29 , 4137), // #731
+ INST(Uqshrn_v , SimdShift , (0b0000000000000000000000, 0b0010111100000000100101, 1, kVO_SV_B8H4S2) , kRWI_W , F(Narrow) , 30 , 4143), // #732
+ INST(Uqshrn2_v , SimdShift , (0b0000000000000000000000, 0b0110111100000000100101, 1, kVO_V_B16H8S4) , kRWI_X , F(Narrow) , 31 , 4150), // #733
+ INST(Uqsub_v , ISimdVVV , (0b0010111000100000001011, kVO_SV_Any) , kRWI_W , 0 , 57 , 4158), // #734
+ INST(Uqxtn_v , ISimdVV , (0b0010111000100001010010, kVO_SV_B8H4S2) , kRWI_W , F(Narrow) , 22 , 4164), // #735
+ INST(Uqxtn2_v , ISimdVV , (0b0110111000100001010010, kVO_V_B16H8S4) , kRWI_X , F(Narrow) , 23 , 4170), // #736
+ INST(Urecpe_v , ISimdVV , (0b0000111010100001110010, kVO_V_S) , kRWI_W , 0 , 24 , 4177), // #737
+ INST(Urhadd_v , ISimdVVV , (0b0010111000100000000101, kVO_V_BHS) , kRWI_W , 0 , 58 , 4184), // #738
+ INST(Urshl_v , SimdShift , (0b0010111000100000010101, 0b0000000000000000000000, 0, kVO_V_Any) , kRWI_W , 0 , 32 , 4191), // #739
+ INST(Urshr_v , SimdShift , (0b0000000000000000000000, 0b0010111100000000001001, 1, kVO_V_Any) , kRWI_W , 0 , 33 , 4197), // #740
+ INST(Ursqrte_v , ISimdVV , (0b0010111010100001110010, kVO_V_S) , kRWI_W , 0 , 25 , 4203), // #741
+ INST(Ursra_v , SimdShift , (0b0000000000000000000000, 0b0010111100000000001101, 1, kVO_V_Any) , kRWI_X , 0 , 34 , 4211), // #742
+ INST(Usdot_v , SimdDot , (0b0000111010000000100111, 0b0000111110000000111100, kET_S, kET_B, kET_4B) , kRWI_X , 0 , 4 , 4217), // #743
+ INST(Ushl_v , SimdShift , (0b0010111000100000010001, 0b0000000000000000000000, 0, kVO_V_Any) , kRWI_W , 0 , 35 , 4223), // #744
+ INST(Ushll_v , SimdShift , (0b0000000000000000000000, 0b0010111100000000101001, 0, kVO_V_B8H4S2) , kRWI_W , F(Long) , 36 , 4228), // #745
+ INST(Ushll2_v , SimdShift , (0b0000000000000000000000, 0b0110111100000000101001, 0, kVO_V_B16H8S4) , kRWI_W , F(Long) , 37 , 4234), // #746
+ INST(Ushr_v , SimdShift , (0b0000000000000000000000, 0b0010111100000000000001, 1, kVO_V_Any) , kRWI_W , 0 , 38 , 4241), // #747
+ INST(Usmmla_v , ISimdVVVx , (0b0100111010000000101011, kOp_V4S, kOp_V16B, kOp_V16B) , kRWI_X , 0 , 16 , 4246), // #748
+ INST(Usqadd_v , ISimdVV , (0b0010111000100000001110, kVO_SV_Any) , kRWI_X , 0 , 26 , 4253), // #749
+ INST(Usra_v , SimdShift , (0b0000000000000000000000, 0b0010111100000000000101, 1, kVO_V_Any) , kRWI_X , 0 , 39 , 4260), // #750
+ INST(Usubl_v , ISimdVVV , (0b0010111000100000001000, kVO_V_B8H4S2) , kRWI_W , F(Long) , 59 , 4265), // #751
+ INST(Usubl2_v , ISimdVVV , (0b0110111000100000001000, kVO_V_B16H8S4) , kRWI_W , F(Long) , 60 , 4271), // #752
+ INST(Usubw_v , ISimdWWV , (0b0010111000100000001100, kVO_V_B8H4S2) , kRWI_W , 0 , 6 , 4278), // #753
+ INST(Usubw2_v , ISimdWWV , (0b0010111000100000001100, kVO_V_B16H8S4) , kRWI_W , 0 , 7 , 4284), // #754
+ INST(Uxtl_v , SimdSxtlUxtl , (0b0010111100000000101001, kVO_V_B8H4S2) , kRWI_W , F(Long) , 2 , 4301), // #755
+ INST(Uxtl2_v , SimdSxtlUxtl , (0b0110111100000000101001, kVO_V_B16H8S4) , kRWI_W , F(Long) , 3 , 4306), // #756
+ INST(Uzp1_v , ISimdVVV , (0b0000111000000000000110, kVO_V_BHS_D2) , kRWI_W , 0 , 61 , 4312), // #757
+ INST(Uzp2_v , ISimdVVV , (0b0000111000000000010110, kVO_V_BHS_D2) , kRWI_W , 0 , 62 , 4317), // #758
+ INST(Xar_v , ISimdVVVI , (0b1100111001100000100011, kVO_V_D2, 6, 10, 0) , kRWI_W , 0 , 1 , 4337), // #759
+ INST(Xtn_v , ISimdVV , (0b0000111000100001001010, kVO_V_B8H4S2) , kRWI_W , F(Narrow) , 27 , 3047), // #760
+ INST(Xtn2_v , ISimdVV , (0b0100111000100001001010, kVO_V_B16H8S4) , kRWI_X , F(Narrow) , 28 , 3053), // #761
+ INST(Zip1_v , ISimdVVV , (0b0000111000000000001110, kVO_V_BHS_D2) , kRWI_W , 0 , 63 , 4367), // #762
+ INST(Zip2_v , ISimdVVV , (0b0000111000000000011110, kVO_V_BHS_D2) , kRWI_W , 0 , 64 , 4372) // #763
+ // ${InstInfo:End}
+};
+
+#undef F
+#undef INST
+#undef NAME_DATA_INDEX
+
+namespace EncodingData {
+
+// ${EncodingData:Begin}
+// ------------------- Automatically generated, do not edit -------------------
+const BaseAddSub baseAddSub[4] = {
+ { 0b0001011000, 0b0001011001, 0b0010001 }, // add
+ { 0b0101011000, 0b0101011001, 0b0110001 }, // adds
+ { 0b1001011000, 0b1001011001, 0b1010001 }, // sub
+ { 0b1101011000, 0b1101011001, 0b1110001 } // subs
+};
+
+const BaseAdr baseAdr[2] = {
+ { 0b0001000000000000000000, OffsetType::kAArch64_ADR }, // adr
+ { 0b1001000000000000000000, OffsetType::kAArch64_ADRP } // adrp
+};
+
+const BaseAtDcIcTlbi baseAtDcIcTlbi[4] = {
+ { 0b00011111110000, 0b00001111000000, true }, // at
+ { 0b00011110000000, 0b00001110000000, true }, // dc
+ { 0b00011110000000, 0b00001110000000, false }, // ic
+ { 0b00011110000000, 0b00010000000000, false } // tlbi
+};
+
+const BaseAtomicCasp baseAtomicCasp[4] = {
+ { 0b0000100000100000011111, kWX, 30 }, // casp
+ { 0b0000100001100000011111, kWX, 30 }, // caspa
+ { 0b0000100001100000111111, kWX, 30 }, // caspal
+ { 0b0000100000100000111111, kWX, 30 } // caspl
+};
+
+const BaseAtomicOp baseAtomicOp[123] = {
+ { 0b1000100010100000011111, kWX, 30, 0 }, // cas
+ { 0b1000100011100000011111, kWX, 30, 1 }, // casa
+ { 0b0000100011100000011111, kW , 0 , 1 }, // casab
+ { 0b0100100011100000011111, kW , 0 , 1 }, // casah
+ { 0b1000100011100000111111, kWX, 30, 1 }, // casal
+ { 0b0000100011100000111111, kW , 0 , 1 }, // casalb
+ { 0b0100100011100000111111, kW , 0 , 1 }, // casalh
+ { 0b0000100010100000011111, kW , 0 , 0 }, // casb
+ { 0b0100100010100000011111, kW , 0 , 0 }, // cash
+ { 0b1000100010100000111111, kWX, 30, 0 }, // casl
+ { 0b0000100010100000111111, kW , 0 , 0 }, // caslb
+ { 0b0100100010100000111111, kW , 0 , 0 }, // caslh
+ { 0b1011100000100000000000, kWX, 30, 0 }, // ldadd
+ { 0b1011100010100000000000, kWX, 30, 1 }, // ldadda
+ { 0b0011100010100000000000, kW , 0 , 1 }, // ldaddab
+ { 0b0111100010100000000000, kW , 0 , 1 }, // ldaddah
+ { 0b1011100011100000000000, kWX, 30, 1 }, // ldaddal
+ { 0b0011100011100000000000, kW , 0 , 1 }, // ldaddalb
+ { 0b0111100011100000000000, kW , 0 , 1 }, // ldaddalh
+ { 0b0011100000100000000000, kW , 0 , 0 }, // ldaddb
+ { 0b0111100000100000000000, kW , 0 , 0 }, // ldaddh
+ { 0b1011100001100000000000, kWX, 30, 0 }, // ldaddl
+ { 0b0011100001100000000000, kW , 0 , 0 }, // ldaddlb
+ { 0b0111100001100000000000, kW , 0 , 0 }, // ldaddlh
+ { 0b1011100000100000000100, kWX, 30, 0 }, // ldclr
+ { 0b1011100010100000000100, kWX, 30, 1 }, // ldclra
+ { 0b0011100010100000000100, kW , 0 , 1 }, // ldclrab
+ { 0b0111100010100000000100, kW , 0 , 1 }, // ldclrah
+ { 0b1011100011100000000100, kWX, 30, 1 }, // ldclral
+ { 0b0011100011100000000100, kW , 0 , 1 }, // ldclralb
+ { 0b0111100011100000000100, kW , 0 , 1 }, // ldclralh
+ { 0b0011100000100000000100, kW , 0 , 0 }, // ldclrb
+ { 0b0111100000100000000100, kW , 0 , 0 }, // ldclrh
+ { 0b1011100001100000000100, kWX, 30, 0 }, // ldclrl
+ { 0b0011100001100000000100, kW , 0 , 0 }, // ldclrlb
+ { 0b0111100001100000000100, kW , 0 , 0 }, // ldclrlh
+ { 0b1011100000100000001000, kWX, 30, 0 }, // ldeor
+ { 0b1011100010100000001000, kWX, 30, 1 }, // ldeora
+ { 0b0011100010100000001000, kW , 0 , 1 }, // ldeorab
+ { 0b0111100010100000001000, kW , 0 , 1 }, // ldeorah
+ { 0b1011100011100000001000, kWX, 30, 1 }, // ldeoral
+ { 0b0011100011100000001000, kW , 0 , 1 }, // ldeoralb
+ { 0b0111100011100000001000, kW , 0 , 1 }, // ldeoralh
+ { 0b0011100000100000001000, kW , 0 , 0 }, // ldeorb
+ { 0b0111100000100000001000, kW , 0 , 0 }, // ldeorh
+ { 0b1011100001100000001000, kWX, 30, 0 }, // ldeorl
+ { 0b0011100001100000001000, kW , 0 , 0 }, // ldeorlb
+ { 0b0111100001100000001000, kW , 0 , 0 }, // ldeorlh
+ { 0b1011100000100000001100, kWX, 30, 0 }, // ldset
+ { 0b1011100010100000001100, kWX, 30, 1 }, // ldseta
+ { 0b0011100010100000001100, kW , 0 , 1 }, // ldsetab
+ { 0b0111100010100000001100, kW , 0 , 1 }, // ldsetah
+ { 0b1011100011100000001100, kWX, 30, 1 }, // ldsetal
+ { 0b0011100011100000001100, kW , 0 , 1 }, // ldsetalb
+ { 0b0111100011100000001100, kW , 0 , 1 }, // ldsetalh
+ { 0b0011100000100000001100, kW , 0 , 0 }, // ldsetb
+ { 0b0111100000100000001100, kW , 0 , 0 }, // ldseth
+ { 0b1011100001100000001100, kWX, 30, 0 }, // ldsetl
+ { 0b0011100001100000001100, kW , 0 , 0 }, // ldsetlb
+ { 0b0111100001100000001100, kW , 0 , 0 }, // ldsetlh
+ { 0b1011100000100000010000, kWX, 30, 0 }, // ldsmax
+ { 0b1011100010100000010000, kWX, 30, 1 }, // ldsmaxa
+ { 0b0011100010100000010000, kW , 0 , 1 }, // ldsmaxab
+ { 0b0111100010100000010000, kW , 0 , 1 }, // ldsmaxah
+ { 0b1011100011100000010000, kWX, 30, 1 }, // ldsmaxal
+ { 0b0011100011100000010000, kW , 0 , 1 }, // ldsmaxalb
+ { 0b0111100011100000010000, kW , 0 , 1 }, // ldsmaxalh
+ { 0b0011100000100000010000, kW , 0 , 0 }, // ldsmaxb
+ { 0b0111100000100000010000, kW , 0 , 0 }, // ldsmaxh
+ { 0b1011100001100000010000, kWX, 30, 0 }, // ldsmaxl
+ { 0b0011100001100000010000, kW , 0 , 0 }, // ldsmaxlb
+ { 0b0111100001100000010000, kW , 0 , 0 }, // ldsmaxlh
+ { 0b1011100000100000010100, kWX, 30, 0 }, // ldsmin
+ { 0b1011100010100000010100, kWX, 30, 1 }, // ldsmina
+ { 0b0011100010100000010100, kW , 0 , 1 }, // ldsminab
+ { 0b0111100010100000010100, kW , 0 , 1 }, // ldsminah
+ { 0b1011100011100000010100, kWX, 30, 1 }, // ldsminal
+ { 0b0011100011100000010100, kW , 0 , 1 }, // ldsminalb
+ { 0b0111100011100000010100, kW , 0 , 1 }, // ldsminalh
+ { 0b0011100000100000010100, kW , 0 , 0 }, // ldsminb
+ { 0b0111100000100000010100, kW , 0 , 0 }, // ldsminh
+ { 0b1011100001100000010100, kWX, 30, 0 }, // ldsminl
+ { 0b0011100001100000010100, kW , 0 , 0 }, // ldsminlb
+ { 0b0111100001100000010100, kW , 0 , 0 }, // ldsminlh
+ { 0b1011100000100000011000, kWX, 30, 0 }, // ldumax
+ { 0b1011100010100000011000, kWX, 30, 1 }, // ldumaxa
+ { 0b0011100010100000011000, kW , 0 , 1 }, // ldumaxab
+ { 0b0111100010100000011000, kW , 0 , 1 }, // ldumaxah
+ { 0b1011100011100000011000, kWX, 30, 1 }, // ldumaxal
+ { 0b0011100011100000011000, kW , 0 , 1 }, // ldumaxalb
+ { 0b0111100011100000011000, kW , 0 , 1 }, // ldumaxalh
+ { 0b0011100000100000011000, kW , 0 , 0 }, // ldumaxb
+ { 0b0111100000100000011000, kW , 0 , 0 }, // ldumaxh
+ { 0b1011100001100000011000, kWX, 30, 0 }, // ldumaxl
+ { 0b0011100001100000011000, kW , 0 , 0 }, // ldumaxlb
+ { 0b0111100001100000011000, kW , 0 , 0 }, // ldumaxlh
+ { 0b1011100000100000011100, kWX, 30, 0 }, // ldumin
+ { 0b1011100010100000011100, kWX, 30, 1 }, // ldumina
+ { 0b0011100010100000011100, kW , 0 , 1 }, // lduminab
+ { 0b0111100010100000011100, kW , 0 , 1 }, // lduminah
+ { 0b1011100011100000011100, kWX, 30, 1 }, // lduminal
+ { 0b0011100011100000011100, kW , 0 , 1 }, // lduminalb
+ { 0b0111100011100000011100, kW , 0 , 1 }, // lduminalh
+ { 0b0011100000100000011100, kW , 0 , 0 }, // lduminb
+ { 0b0111100000100000011100, kW , 0 , 0 }, // lduminh
+ { 0b1011100001100000011100, kWX, 30, 0 }, // lduminl
+ { 0b0011100001100000011100, kW , 0 , 0 }, // lduminlb
+ { 0b0111100001100000011100, kW , 0 , 0 }, // lduminlh
+ { 0b1000100000000000111111, kWX, 30, 1 }, // stlxr
+ { 0b0000100000000000111111, kW , 0 , 1 }, // stlxrb
+ { 0b0100100000000000111111, kW , 0 , 1 }, // stlxrh
+ { 0b1011100000100000100000, kWX, 30, 1 }, // swp
+ { 0b1011100010100000100000, kWX, 30, 1 }, // swpa
+ { 0b0011100010100000100000, kW , 0 , 1 }, // swpab
+ { 0b0111100010100000100000, kW , 0 , 1 }, // swpah
+ { 0b1011100011100000100000, kWX, 30, 1 }, // swpal
+ { 0b0011100011100000100000, kW , 0 , 1 }, // swpalb
+ { 0b0111100011100000100000, kW , 0 , 1 }, // swpalh
+ { 0b0011100000100000100000, kW , 0 , 1 }, // swpb
+ { 0b0111100000100000100000, kW , 0 , 1 }, // swph
+ { 0b1011100001100000100000, kWX, 30, 1 }, // swpl
+ { 0b0011100001100000100000, kW , 0 , 1 }, // swplb
+ { 0b0111100001100000100000, kW , 0 , 1 } // swplh
+};
+
+const BaseAtomicSt baseAtomicSt[48] = {
+ { 0b1011100000100000000000, kWX, 30 }, // stadd
+ { 0b1011100001100000000000, kWX, 30 }, // staddl
+ { 0b0011100000100000000000, kW , 0 }, // staddb
+ { 0b0011100001100000000000, kW , 0 }, // staddlb
+ { 0b0111100000100000000000, kW , 0 }, // staddh
+ { 0b0111100001100000000000, kW , 0 }, // staddlh
+ { 0b1011100000100000000100, kWX, 30 }, // stclr
+ { 0b1011100001100000000100, kWX, 30 }, // stclrl
+ { 0b0011100000100000000100, kW , 0 }, // stclrb
+ { 0b0011100001100000000100, kW , 0 }, // stclrlb
+ { 0b0111100000100000000100, kW , 0 }, // stclrh
+ { 0b0111100001100000000100, kW , 0 }, // stclrlh
+ { 0b1011100000100000001000, kWX, 30 }, // steor
+ { 0b1011100001100000001000, kWX, 30 }, // steorl
+ { 0b0011100000100000001000, kW , 0 }, // steorb
+ { 0b0011100001100000001000, kW , 0 }, // steorlb
+ { 0b0111100000100000001000, kW , 0 }, // steorh
+ { 0b0111100001100000001000, kW , 0 }, // steorlh
+ { 0b1011100000100000001100, kWX, 30 }, // stset
+ { 0b1011100001100000001100, kWX, 30 }, // stsetl
+ { 0b0011100000100000001100, kW , 0 }, // stsetb
+ { 0b0011100001100000001100, kW , 0 }, // stsetlb
+ { 0b0111100000100000001100, kW , 0 }, // stseth
+ { 0b0111100001100000001100, kW , 0 }, // stsetlh
+ { 0b1011100000100000010000, kWX, 30 }, // stsmax
+ { 0b1011100001100000010000, kWX, 30 }, // stsmaxl
+ { 0b0011100000100000010000, kW , 0 }, // stsmaxb
+ { 0b0011100001100000010000, kW , 0 }, // stsmaxlb
+ { 0b0111100000100000010000, kW , 0 }, // stsmaxh
+ { 0b0111100001100000010000, kW , 0 }, // stsmaxlh
+ { 0b1011100000100000010100, kWX, 30 }, // stsmin
+ { 0b1011100001100000010100, kWX, 30 }, // stsminl
+ { 0b0011100000100000010100, kW , 0 }, // stsminb
+ { 0b0011100001100000010100, kW , 0 }, // stsminlb
+ { 0b0111100000100000010100, kW , 0 }, // stsminh
+ { 0b0111100001100000010100, kW , 0 }, // stsminlh
+ { 0b1011100000100000011000, kWX, 30 }, // stumax
+ { 0b1011100001100000011000, kWX, 30 }, // stumaxl
+ { 0b0011100000100000011000, kW , 0 }, // stumaxb
+ { 0b0011100001100000011000, kW , 0 }, // stumaxlb
+ { 0b0111100000100000011000, kW , 0 }, // stumaxh
+ { 0b0111100001100000011000, kW , 0 }, // stumaxlh
+ { 0b1011100000100000011100, kWX, 30 }, // stumin
+ { 0b1011100001100000011100, kWX, 30 }, // stuminl
+ { 0b0011100000100000011100, kW , 0 }, // stuminb
+ { 0b0011100001100000011100, kW , 0 }, // stuminlb
+ { 0b0111100000100000011100, kW , 0 }, // stuminh
+ { 0b0111100001100000011100, kW , 0 } // stuminlh
+};
+
+const BaseBfc baseBfc[1] = {
+ { 0b00110011000000000000001111100000 } // bfc
+};
+
+const BaseBfi baseBfi[3] = {
+ { 0b00110011000000000000000000000000 }, // bfi
+ { 0b00010011000000000000000000000000 }, // sbfiz
+ { 0b01010011000000000000000000000000 } // ubfiz
+};
+
+const BaseBfm baseBfm[3] = {
+ { 0b00110011000000000000000000000000 }, // bfm
+ { 0b00010011000000000000000000000000 }, // sbfm
+ { 0b01010011000000000000000000000000 } // ubfm
+};
+
+const BaseBfx baseBfx[3] = {
+ { 0b00110011000000000000000000000000 }, // bfxil
+ { 0b00010011000000000000000000000000 }, // sbfx
+ { 0b01010011000000000000000000000000 } // ubfx
+};
+
+const BaseBranchCmp baseBranchCmp[2] = {
+ { 0b00110101000000000000000000000000 }, // cbnz
+ { 0b00110100000000000000000000000000 } // cbz
+};
+
+const BaseBranchReg baseBranchReg[3] = {
+ { 0b11010110001111110000000000000000 }, // blr
+ { 0b11010110000111110000000000000000 }, // br
+ { 0b11010110010111110000000000000000 } // ret
+};
+
+const BaseBranchRel baseBranchRel[2] = {
+ { 0b00010100000000000000000000000000 }, // b
+ { 0b10010100000000000000000000000000 } // bl
+};
+
+const BaseBranchTst baseBranchTst[2] = {
+ { 0b00110111000000000000000000000000 }, // tbnz
+ { 0b00110110000000000000000000000000 } // tbz
+};
+
+const BaseCCmp baseCCmp[2] = {
+ { 0b00111010010000000000000000000000 }, // ccmn
+ { 0b01111010010000000000000000000000 } // ccmp
+};
+
+const BaseCInc baseCInc[3] = {
+ { 0b00011010100000000000010000000000 }, // cinc
+ { 0b01011010100000000000000000000000 }, // cinv
+ { 0b01011010100000000000010000000000 } // cneg
+};
+
+const BaseCSel baseCSel[4] = {
+ { 0b00011010100000000000000000000000 }, // csel
+ { 0b00011010100000000000010000000000 }, // csinc
+ { 0b01011010100000000000000000000000 }, // csinv
+ { 0b01011010100000000000010000000000 } // csneg
+};
+
+const BaseCSet baseCSet[2] = {
+ { 0b00011010100111110000011111100000 }, // cset
+ { 0b01011010100111110000001111100000 } // csetm
+};
+
+const BaseCmpCmn baseCmpCmn[2] = {
+ { 0b0101011000, 0b0101011001, 0b0110001 }, // cmn
+ { 0b1101011000, 0b1101011001, 0b1110001 } // cmp
+};
+
+const BaseExtend baseExtend[5] = {
+ { 0b0001001100000000000111, kWX, 0 }, // sxtb
+ { 0b0001001100000000001111, kWX, 0 }, // sxth
+ { 0b1001001101000000011111, kX , 0 }, // sxtw
+ { 0b0101001100000000000111, kW, 1 }, // uxtb
+ { 0b0101001100000000001111, kW, 1 } // uxth
+};
+
+const BaseExtract baseExtract[1] = {
+ { 0b00010011100000000000000000000000 } // extr
+};
+
+const BaseLdSt baseLdSt[9] = {
+ { 0b1011100101, 0b10111000010, 0b10111000011, 0b00011000, kWX, 30, 2, Inst::kIdLdur }, // ldr
+ { 0b0011100101, 0b00111000010, 0b00111000011, 0 , kW , 0 , 0, Inst::kIdLdurb }, // ldrb
+ { 0b0111100101, 0b01111000010, 0b01111000011, 0 , kW , 0 , 1, Inst::kIdLdurh }, // ldrh
+ { 0b0011100111, 0b00111000100, 0b00111000101, 0 , kWX, 22, 0, Inst::kIdLdursb }, // ldrsb
+ { 0b0111100110, 0b01111000100, 0b01111000101, 0 , kWX, 22, 1, Inst::kIdLdursh }, // ldrsh
+ { 0b1011100110, 0b10111000100, 0b10111000101, 0b10011000, kX , 0 , 2, Inst::kIdLdursw }, // ldrsw
+ { 0b1011100100, 0b10111000000, 0b10111000001, 0 , kWX, 30, 2, Inst::kIdStur }, // str
+ { 0b0011100100, 0b00111000000, 0b00111000001, 0 , kW , 30, 0, Inst::kIdSturb }, // strb
+ { 0b0111100100, 0b01111000000, 0b01111000001, 0 , kWX, 30, 1, Inst::kIdSturh } // strh
+};
+
+const BaseLdpStp baseLdpStp[6] = {
+ { 0b0010100001, 0 , kWX, 31, 2 }, // ldnp
+ { 0b0010100101, 0b0010100011, kWX, 31, 2 }, // ldp
+ { 0b0110100101, 0b0110100011, kX , 0 , 2 }, // ldpsw
+ { 0b0110100100, 0b0110100010, kX, 0, 4 }, // stgp
+ { 0b0010100000, 0 , kWX, 31, 2 }, // stnp
+ { 0b0010100100, 0b0010100010, kWX, 31, 2 } // stp
+};
+
+const BaseLdxp baseLdxp[2] = {
+ { 0b1000100001111111100000, kWX, 30 }, // ldaxp
+ { 0b1000100001111111000000, kWX, 30 } // ldxp
+};
+
+const BaseLogical baseLogical[8] = {
+ { 0b0001010000, 0b00100100, 0 }, // and
+ { 0b1101010000, 0b11100100, 0 }, // ands
+ { 0b0001010001, 0b00100100, 1 }, // bic
+ { 0b1101010001, 0b11100100, 1 }, // bics
+ { 0b1001010001, 0b10100100, 1 }, // eon
+ { 0b1001010000, 0b10100100, 0 }, // eor
+ { 0b0101010001, 0b01100100, 1 }, // orn
+ { 0b0101010000, 0b01100100, 0 } // orr
+};
+
+const BaseMovKNZ baseMovKNZ[3] = {
+ { 0b01110010100000000000000000000000 }, // movk
+ { 0b00010010100000000000000000000000 }, // movn
+ { 0b01010010100000000000000000000000 } // movz
+};
+
+const BaseMvnNeg baseMvnNeg[3] = {
+ { 0b00101010001000000000001111100000 }, // mvn
+ { 0b01001011000000000000001111100000 }, // neg
+ { 0b01101011000000000000001111100000 } // negs
+};
+
+const BaseOp baseOp[23] = {
+ { 0b11010101000000110010000110011111 }, // autia1716
+ { 0b11010101000000110010001110111111 }, // autiasp
+ { 0b11010101000000110010001110011111 }, // autiaz
+ { 0b11010101000000110010000111011111 }, // autib1716
+ { 0b11010101000000110010001111111111 }, // autibsp
+ { 0b11010101000000110010001111011111 }, // autibz
+ { 0b11010101000000000100000001011111 }, // axflag
+ { 0b11010101000000000100000000011111 }, // cfinv
+ { 0b11010101000000110010001010011111 }, // csdb
+ { 0b11010101000000110010000011011111 }, // dgh
+ { 0b11010110101111110000001111100000 }, // drps
+ { 0b11010101000000110010001000011111 }, // esb
+ { 0b11010110100111110000001111100000 }, // eret
+ { 0b11010101000000110010000000011111 }, // nop
+ { 0b11010101000000110011010010011111 }, // pssbb
+ { 0b11010101000000110010000010011111 }, // sev
+ { 0b11010101000000110010000010111111 }, // sevl
+ { 0b11010101000000110011000010011111 }, // ssbb
+ { 0b11010101000000110010000001011111 }, // wfe
+ { 0b11010101000000110010000001111111 }, // wfi
+ { 0b11010101000000000100000000111111 }, // xaflag
+ { 0b11010101000000110010000011111111 }, // xpaclri
+ { 0b11010101000000110010000000111111 } // yield
+};
+
+const BaseOpImm baseOpImm[14] = {
+ { 0b11010100001000000000000000000000, 16, 5 }, // brk
+ { 0b11010101000000110011000001011111, 4, 8 }, // clrex
+ { 0b11010100101000000000000000000001, 16, 5 }, // dcps1
+ { 0b11010100101000000000000000000010, 16, 5 }, // dcps2
+ { 0b11010100101000000000000000000011, 16, 5 }, // dcps3
+ { 0b11010101000000110011000010111111, 4, 8 }, // dmb
+ { 0b11010101000000110011000010011111, 4, 8 }, // dsb
+ { 0b11010101000000110010000000011111, 7, 5 }, // hint
+ { 0b11010100010000000000000000000000, 16, 5 }, // hlt
+ { 0b11010100000000000000000000000010, 16, 5 }, // hvc
+ { 0b11010101000000110011000011011111, 4, 8 }, // isb
+ { 0b11010100000000000000000000000011, 16, 5 }, // smc
+ { 0b11010100000000000000000000000001, 16, 5 }, // svc
+ { 0b00000000000000000000000000000000, 16, 0 } // udf
+};
+
+const BaseR baseR[10] = {
+ { 0b11011010110000010011101111100000, kX, kZR, 0 }, // autdza
+ { 0b11011010110000010011111111100000, kX, kZR, 0 }, // autdzb
+ { 0b11011010110000010011001111100000, kX, kZR, 0 }, // autiza
+ { 0b11011010110000010011011111100000, kX, kZR, 0 }, // autizb
+ { 0b11011010110000010010101111100000, kX, kZR, 0 }, // pacdza
+ { 0b11011010110000010010111111100000, kX, kZR, 0 }, // pacdzb
+ { 0b00111010000000000000100000001101, kW, kZR, 5 }, // setf8
+ { 0b00111010000000000100100000001101, kW, kZR, 5 }, // setf16
+ { 0b11011010110000010100011111100000, kX, kZR, 0 }, // xpacd
+ { 0b11011010110000010100001111100000, kX, kZR, 0 } // xpaci
+};
+
+const BaseRM_NoImm baseRM_NoImm[21] = {
+ { 0b1000100011011111111111, kWX, kZR, 30 }, // ldar
+ { 0b0000100011011111111111, kW , kZR, 0 }, // ldarb
+ { 0b0100100011011111111111, kW , kZR, 0 }, // ldarh
+ { 0b1000100001011111111111, kWX, kZR, 30 }, // ldaxr
+ { 0b0000100001011111111111, kW , kZR, 0 }, // ldaxrb
+ { 0b0100100001011111111111, kW , kZR, 0 }, // ldaxrh
+ { 0b1101100111100000000000, kX , kZR, 0 }, // ldgm
+ { 0b1000100011011111011111, kWX, kZR, 30 }, // ldlar
+ { 0b0000100011011111011111, kW , kZR, 0 }, // ldlarb
+ { 0b0100100011011111011111, kW , kZR, 0 }, // ldlarh
+ { 0b1000100001011111011111, kWX, kZR, 30 }, // ldxr
+ { 0b0000100001011111011111, kW , kZR, 0 }, // ldxrb
+ { 0b0100100001011111011111, kW , kZR, 0 }, // ldxrh
+ { 0b1101100110100000000000, kX , kZR, 0 }, // stgm
+ { 0b1000100010011111011111, kWX, kZR, 30 }, // stllr
+ { 0b0000100010011111011111, kW , kZR, 0 }, // stllrb
+ { 0b0100100010011111011111, kW , kZR, 0 }, // stllrh
+ { 0b1000100010011111111111, kWX, kZR, 30 }, // stlr
+ { 0b0000100010011111111111, kW , kZR, 0 }, // stlrb
+ { 0b0100100010011111111111, kW , kZR, 0 }, // stlrh
+ { 0b1101100100100000000000, kX , kZR, 0 } // stzgm
+};
+
+const BaseRM_SImm10 baseRM_SImm10[2] = {
+ { 0b1111100000100000000001, kX , kZR, 0, 3 }, // ldraa
+ { 0b1111100010100000000001, kX , kZR, 0, 3 } // ldrab
+};
+
+const BaseRM_SImm9 baseRM_SImm9[23] = {
+ { 0b1101100101100000000000, 0b0000000000000000000000, kX , kZR, 0, 4 }, // ldg
+ { 0b1011100001000000000010, 0b0000000000000000000000, kWX, kZR, 30, 0 }, // ldtr
+ { 0b0011100001000000000010, 0b0000000000000000000000, kW , kZR, 0 , 0 }, // ldtrb
+ { 0b0111100001000000000010, 0b0000000000000000000000, kW , kZR, 0 , 0 }, // ldtrh
+ { 0b0011100011000000000010, 0b0000000000000000000000, kWX, kZR, 22, 0 }, // ldtrsb
+ { 0b0111100011000000000010, 0b0000000000000000000000, kWX, kZR, 22, 0 }, // ldtrsh
+ { 0b1011100010000000000010, 0b0000000000000000000000, kX , kZR, 0 , 0 }, // ldtrsw
+ { 0b1011100001000000000000, 0b0000000000000000000000, kWX, kZR, 30, 0 }, // ldur
+ { 0b0011100001000000000000, 0b0000000000000000000000, kW , kZR, 0 , 0 }, // ldurb
+ { 0b0111100001000000000000, 0b0000000000000000000000, kW , kZR, 0 , 0 }, // ldurh
+ { 0b0011100011000000000000, 0b0000000000000000000000, kWX, kZR, 22, 0 }, // ldursb
+ { 0b0111100011000000000000, 0b0000000000000000000000, kWX, kZR, 22, 0 }, // ldursh
+ { 0b1011100010000000000000, 0b0000000000000000000000, kWX, kZR, 0 , 0 }, // ldursw
+ { 0b1101100110100000000010, 0b1101100110100000000001, kX, kSP, 0, 4 }, // st2g
+ { 0b1101100100100000000010, 0b1101100100100000000001, kX, kSP, 0, 4 }, // stg
+ { 0b1011100000000000000010, 0b0000000000000000000000, kWX, kZR, 30, 0 }, // sttr
+ { 0b0011100000000000000010, 0b0000000000000000000000, kW , kZR, 0 , 0 }, // sttrb
+ { 0b0111100000000000000010, 0b0000000000000000000000, kW , kZR, 0 , 0 }, // sttrh
+ { 0b1011100000000000000000, 0b0000000000000000000000, kWX, kZR, 30, 0 }, // stur
+ { 0b0011100000000000000000, 0b0000000000000000000000, kW , kZR, 0 , 0 }, // sturb
+ { 0b0111100000000000000000, 0b0000000000000000000000, kW , kZR, 0 , 0 }, // sturh
+ { 0b1101100111100000000010, 0b1101100111100000000001, kX , kSP, 0, 4 }, // stz2g
+ { 0b1101100101100000000010, 0b1101100101100000000001, kX , kSP, 0, 4 } // stzg
+};
+
+const BaseRR baseRR[15] = {
+ { 0b11011010110000010001100000000000, kX, kZR, 0, kX, kSP, 5, true }, // autda
+ { 0b11011010110000010001110000000000, kX, kZR, 0, kX, kSP, 5, true }, // autdb
+ { 0b11011010110000010001000000000000, kX, kZR, 0, kX, kSP, 5, true }, // autia
+ { 0b11011010110000010001010000000000, kX, kZR, 0, kX, kSP, 5, true }, // autib
+ { 0b01011010110000000001010000000000, kWX, kZR, 0, kWX, kZR, 5, true }, // cls
+ { 0b01011010110000000001000000000000, kWX, kZR, 0, kWX, kZR, 5, true }, // clz
+ { 0b10111010110000000000000000011111, kX, kSP, 5, kX, kSP, 16, true }, // cmpp
+ { 0b01011010000000000000001111100000, kWX, kZR, 0, kWX, kZR, 16, true }, // ngc
+ { 0b01111010000000000000001111100000, kWX, kZR, 0, kWX, kZR, 16, true }, // ngcs
+ { 0b11011010110000010000100000000000, kX, kZR, 0, kX, kSP, 5, true }, // pacda
+ { 0b11011010110000010000110000000000, kX, kZR, 0, kX, kSP, 5, true }, // pacdb
+ { 0b01011010110000000000000000000000, kWX, kZR, 0, kWX, kZR, 5, true }, // rbit
+ { 0b01011010110000000000010000000000, kWX, kZR, 0, kWX, kZR, 5, true }, // rev16
+ { 0b11011010110000000000100000000000, kWX, kZR, 0, kWX, kZR, 5, true }, // rev32
+ { 0b11011010110000000000110000000000, kWX, kZR, 0, kWX, kZR, 5, true } // rev64
+};
+
+const BaseRRII baseRRII[2] = {
+ { 0b1001000110000000000000, kX, kSP, kX, kSP, 6, 4, 16, 4, 0, 10 }, // addg
+ { 0b1101000110000000000000, kX, kSP, kX, kSP, 6, 4, 16, 4, 0, 10 } // subg
+};
+
+const BaseRRR baseRRR[26] = {
+ { 0b0001101000000000000000, kWX, kZR, kWX, kZR, kWX, kZR, true }, // adc
+ { 0b0011101000000000000000, kWX, kZR, kWX, kZR, kWX, kZR, true }, // adcs
+ { 0b0001101011000000010000, kW, kZR, kW, kZR, kW, kZR, false }, // crc32b
+ { 0b0001101011000000010100, kW, kZR, kW, kZR, kW, kZR, false }, // crc32cb
+ { 0b0001101011000000010101, kW, kZR, kW, kZR, kW, kZR, false }, // crc32ch
+ { 0b0001101011000000010110, kW, kZR, kW, kZR, kW, kZR, false }, // crc32cw
+ { 0b1001101011000000010111, kW, kZR, kW, kZR, kX, kZR, false }, // crc32cx
+ { 0b0001101011000000010001, kW, kZR, kW, kZR, kW, kZR, false }, // crc32h
+ { 0b0001101011000000010010, kW, kZR, kW, kZR, kW, kZR, false }, // crc32w
+ { 0b1001101011000000010011, kW, kZR, kW, kZR, kX, kZR, false }, // crc32x
+ { 0b1001101011000000000101, kX , kZR, kX , kSP, kX , kZR, true }, // gmi
+ { 0b0001101100000000111111, kWX, kZR, kWX, kZR, kWX, kZR, true }, // mneg
+ { 0b0001101100000000011111, kWX, kZR, kWX, kZR, kWX, kZR, true }, // mul
+ { 0b1001101011000000001100, kX, kZR, kX, kZR, kX, kSP, false }, // pacga
+ { 0b0101101000000000000000, kWX, kZR, kWX, kZR, kWX, kZR, true }, // sbc
+ { 0b0111101000000000000000, kWX, kZR, kWX, kZR, kWX, kZR, true }, // sbcs
+ { 0b0001101011000000000011, kWX, kZR, kWX, kZR, kWX, kZR, true }, // sdiv
+ { 0b1001101100100000111111, kX , kZR, kW , kZR, kW , kZR, false }, // smnegl
+ { 0b1001101101000000011111, kX , kZR, kX , kZR, kX , kZR, true }, // smulh
+ { 0b1001101100100000011111, kX , kZR, kW , kZR, kW , kZR, false }, // smull
+ { 0b1001101011000000000000, kX, kZR, kX, kSP, kX, kSP, false }, // subp
+ { 0b1011101011000000000000, kX, kZR, kX, kSP, kX, kSP, false }, // subps
+ { 0b0001101011000000000010, kWX, kZR, kWX, kZR, kWX, kZR, true }, // udiv
+ { 0b1001101110100000111111, kX , kZR, kW , kZR, kW , kZR, false }, // umnegl
+ { 0b1001101110100000011111, kX , kZR, kW , kZR, kW , kZR, false }, // umull
+ { 0b1001101111000000011111, kX , kZR, kX , kZR, kX , kZR, false } // umulh
+};
+
+const BaseRRRR baseRRRR[6] = {
+ { 0b0001101100000000000000, kWX, kZR, kWX, kZR, kWX, kZR, kWX, kZR, true }, // madd
+ { 0b0001101100000000100000, kWX, kZR, kWX, kZR, kWX, kZR, kWX, kZR, true }, // msub
+ { 0b1001101100100000000000, kX , kZR, kW , kZR, kW , kZR, kX , kZR, false }, // smaddl
+ { 0b1001101100100000100000, kX , kZR, kW , kZR, kW , kZR, kX , kZR, false }, // smsubl
+ { 0b1001101110100000000000, kX , kZR, kW , kZR, kW , kZR, kX , kZR, false }, // umaddl
+ { 0b1001101110100000100000, kX , kZR, kW , kZR, kW , kZR, kX , kZR, false } // umsubl
+};
+
+const BaseShift baseShift[8] = {
+ { 0b0001101011000000001010, 0b0001001100000000011111, 0 }, // asr
+ { 0b0001101011000000001010, 0b0000000000000000000000, 0 }, // asrv
+ { 0b0001101011000000001000, 0b0101001100000000000000, 0 }, // lsl
+ { 0b0001101011000000001000, 0b0000000000000000000000, 0 }, // lslv
+ { 0b0001101011000000001001, 0b0101001100000000011111, 0 }, // lsr
+ { 0b0001101011000000001001, 0b0000000000000000000000, 0 }, // lsrv
+ { 0b0001101011000000001011, 0b0001001110000000000000, 1 }, // ror
+ { 0b0001101011000000001011, 0b0000000000000000000000, 1 } // rorv
+};
+
+const BaseStx baseStx[3] = {
+ { 0b1000100000000000011111, kWX, 30 }, // stxr
+ { 0b0000100000000000011111, kW , 0 }, // stxrb
+ { 0b0100100000000000011111, kW , 0 } // stxrh
+};
+
+const BaseStxp baseStxp[2] = {
+ { 0b1000100000100000100000, kWX, 30 }, // stlxp
+ { 0b1000100000100000000000, kWX, 30 } // stxp
+};
+
+const BaseTst baseTst[1] = {
+ { 0b1101010000, 0b111001000 } // tst
+};
+
+const FSimdPair fSimdPair[5] = {
+ { 0b0111111000110000110110, 0b0010111000100000110101 }, // faddp_v
+ { 0b0111111000110000110010, 0b0010111000100000110001 }, // fmaxnmp_v
+ { 0b0111111000110000111110, 0b0010111000100000111101 }, // fmaxp_v
+ { 0b0111111010110000110010, 0b0010111010100000110001 }, // fminnmp_v
+ { 0b0111111010110000111110, 0b0010111010100000111101 } // fminp_v
+};
+
+const FSimdSV fSimdSV[4] = {
+ { 0b0010111000110000110010 }, // fmaxnmv_v
+ { 0b0010111000110000111110 }, // fmaxv_v
+ { 0b0010111010110000110010 }, // fminnmv_v
+ { 0b0010111010110000111110 } // fminv_v
+};
+
+const FSimdVV fSimdVV[17] = {
+ { 0b0001111000100000110000, kHF_A, 0b0000111010100000111110, kHF_B }, // fabs_v
+ { 0b0001111000100001010000, kHF_A, 0b0010111010100000111110, kHF_B }, // fneg_v
+ { 0b0101111010100001110110, kHF_B, 0b0000111010100001110110, kHF_B }, // frecpe_v
+ { 0b0101111010100001111110, kHF_B, 0b0000000000000000000000, kHF_N }, // frecpx_v
+ { 0b0001111000101000110000, kHF_N, 0b0010111000100001111010, kHF_N }, // frint32x_v