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authorGravatarGravatar Ryan Holtz <therealmogminer@gmail.com>2018-04-02 13:27:35 +0200
committerGravatarGravatar Ryan Holtz <therealmogminer@gmail.com>2018-04-02 13:27:35 +0200
commitbe21c87b75a43af1865d2b6f8c35f2c4c5a0743a (patch) (github)
tree320e279645223123ec27c52127521428f2b7f03e
parent60a418b0f91bfb358100b416c410825b6f90e0bf (diff)
downloadmame-arm_playground.tar.bz2
mame-arm_playground.zip
Even more performance boost, 39in1 runs 86.62% on an -str 60 bencharm_playground
-rw-r--r--src/devices/cpu/arm7/arm7.cpp102
-rw-r--r--src/devices/cpu/arm7/arm7.h27
-rw-r--r--src/devices/cpu/arm7/arm7core.h12
-rw-r--r--src/devices/cpu/arm7/arm7help.h4
-rw-r--r--src/devices/cpu/arm7/arm7ops.hxx128
5 files changed, 211 insertions, 62 deletions
diff --git a/src/devices/cpu/arm7/arm7.cpp b/src/devices/cpu/arm7/arm7.cpp
index f9676e63136..94e0e2e14ab 100644
--- a/src/devices/cpu/arm7/arm7.cpp
+++ b/src/devices/cpu/arm7/arm7.cpp
@@ -267,10 +267,87 @@ device_memory_interface::space_config_vector arm7_cpu_device::memory_space_confi
};
}
-void arm7_cpu_device::update_reg_ptr()
+void arm7_cpu_device::update_reg_ptr(const uint32_t old_mode)
{
- m_reg_group = s_register_table[m_mode];
- m_rp = m_register_pointers[m_mode];
+ //m_reg_group = s_register_table[m_mode];
+ //m_rp = m_register_pointers[m_mode];
+ if ((old_mode == eARM7_MODE_USER && m_mode == eARM7_MODE_SYS) || (old_mode == eARM7_MODE_SYS && m_mode == eARM7_MODE_USER))
+ return;
+
+ if (old_mode == eARM7_MODE_USER || old_mode == eARM7_MODE_SYS)
+ {
+ memcpy(&m_r[eR8_USR], &m_r[eR8], sizeof(uint32_t) * 7);
+ m_r[eSPSR_USR] = m_r[eSPSR];
+ }
+ else if (old_mode == eARM7_MODE_IRQ)
+ {
+ m_r[eR13_IRQ] = m_r[eR13];
+ m_r[eR14_IRQ] = m_r[eR14];
+ m_r[eSPSR_IRQ] = m_r[eSPSR];
+ }
+ else if (old_mode == eARM7_MODE_FIQ)
+ {
+ memcpy(&m_r[eR8_FIQ], &m_r[eR8], sizeof(uint32_t) * 7);
+ m_r[eSPSR_FIQ] = m_r[eSPSR];
+ }
+ else if (old_mode == eARM7_MODE_SVC)
+ {
+ m_r[eR13_SVC] = m_r[eR13];
+ m_r[eR14_SVC] = m_r[eR14];
+ m_r[eSPSR_SVC] = m_r[eSPSR];
+ }
+ else if (old_mode == eARM7_MODE_ABT)
+ {
+ m_r[eR13_ABT] = m_r[eR13];
+ m_r[eR14_ABT] = m_r[eR14];
+ m_r[eSPSR_ABT] = m_r[eSPSR];
+ }
+ else if (old_mode == eARM7_MODE_UND)
+ {
+ m_r[eR13_UND] = m_r[eR13];
+ m_r[eR14_UND] = m_r[eR14];
+ m_r[eSPSR_UND] = m_r[eSPSR];
+ }
+
+ init_reg_ptr();
+}
+
+void arm7_cpu_device::init_reg_ptr()
+{
+ if (m_mode == eARM7_MODE_USER || m_mode == eARM7_MODE_SYS)
+ {
+ memcpy(&m_r[eR8], &m_r[eR8_USR], sizeof(uint32_t) * 7);
+ m_r[eSPSR] = m_r[eSPSR_USR];
+ }
+ else if (m_mode == eARM7_MODE_IRQ)
+ {
+ m_r[eR13] = m_r[eR13_IRQ];
+ m_r[eR14] = m_r[eR14_IRQ];
+ m_r[eSPSR] = m_r[eSPSR_IRQ];
+ }
+ else if (m_mode == eARM7_MODE_FIQ)
+ {
+ memcpy(&m_r[eR8], &m_r[eR8_FIQ], sizeof(uint32_t) * 7);
+ m_r[eSPSR] = m_r[eSPSR_FIQ];
+ }
+ else if (m_mode == eARM7_MODE_SVC)
+ {
+ m_r[eR13] = m_r[eR13_SVC];
+ m_r[eR14] = m_r[eR14_SVC];
+ m_r[eSPSR] = m_r[eSPSR_SVC];
+ }
+ else if (m_mode == eARM7_MODE_ABT)
+ {
+ m_r[eR13] = m_r[eR13_ABT];
+ m_r[eR14] = m_r[eR14_ABT];
+ m_r[eSPSR] = m_r[eSPSR_ABT];
+ }
+ else if (m_mode == eARM7_MODE_UND)
+ {
+ m_r[eR13] = m_r[eR13_UND];
+ m_r[eR14] = m_r[eR14_UND];
+ m_r[eSPSR] = m_r[eSPSR_UND];
+ }
}
void arm7_cpu_device::split_flags()
@@ -294,12 +371,13 @@ void arm7_cpu_device::set_cpsr(uint32_t val)
const uint32_t mode = m_cpsr & MODE_FLAG;
if (mode != m_mode)
{
+ const uint32_t old_mode = m_mode;
m_mode = mode;
m_read_fault_table = ((m_mode == eARM7_MODE_USER) ? s_read_fault_table_user : s_read_fault_table_no_user);
m_write_fault_table = ((m_mode == eARM7_MODE_USER) ? s_write_fault_table_user : s_write_fault_table_no_user);
//m_read_fault_word = ((m_mode == eARM7_MODE_USER) ? s_read_fault_word_user : s_read_fault_word_no_user);
//m_write_fault_word = ((m_mode == eARM7_MODE_USER) ? s_write_fault_word_user : s_write_fault_word_no_user);
- update_reg_ptr();
+ update_reg_ptr(old_mode);
}
}
@@ -332,12 +410,13 @@ void arm7500_cpu_device::set_cpsr(uint32_t val)
const uint32_t mode = m_cpsr & MODE_FLAG;
if (mode != m_mode)
{
+ const uint32_t old_mode = m_mode;
m_mode = mode;
m_read_fault_table = ((m_mode == eARM7_MODE_USER) ? s_read_fault_table_user : s_read_fault_table_no_user);
m_write_fault_table = ((m_mode == eARM7_MODE_USER) ? s_write_fault_table_user : s_write_fault_table_no_user);
//m_read_fault_word = ((m_mode == eARM7_MODE_USER) ? s_read_fault_word_user : s_read_fault_word_no_user);
//m_write_fault_word = ((m_mode == eARM7_MODE_USER) ? s_write_fault_word_user : s_write_fault_word_no_user);
- update_reg_ptr();
+ update_reg_ptr(old_mode);
}
}
@@ -925,7 +1004,7 @@ bool arm7_cpu_device::memory_translate(int spacenum, int intention, offs_t &addr
void arm7_cpu_device::postload()
{
- update_reg_ptr();
+ init_reg_ptr();
}
void arm7_cpu_device::device_start()
@@ -1038,6 +1117,16 @@ void arm7_cpu_device::device_start()
state_add( ARM7_R13, "R13", m_r[13]).formatstr("%08X");
state_add( ARM7_R14, "R14", m_r[14]).formatstr("%08X");
state_add( ARM7_R15, "R15", m_r[15]).formatstr("%08X");
+ state_add( ARM7_SPSR, "SPSR", m_r[16]).formatstr("%08X");
+ /* USR/SYS Mode Shadowed Registers */
+ state_add( ARM7_USRR8, "USR8", m_r[eR8_USR] ).formatstr("%08X");
+ state_add( ARM7_USRR9, "USR9", m_r[eR9_USR] ).formatstr("%08X");
+ state_add( ARM7_USRR10, "USR10", m_r[eR10_USR] ).formatstr("%08X");
+ state_add( ARM7_USRR11, "USR11", m_r[eR11_USR] ).formatstr("%08X");
+ state_add( ARM7_USRR12, "USR12", m_r[eR12_USR] ).formatstr("%08X");
+ state_add( ARM7_USRR13, "USR13", m_r[eR13_USR] ).formatstr("%08X");
+ state_add( ARM7_USRR14, "USR14", m_r[eR14_USR] ).formatstr("%08X");
+ state_add( ARM7_USRSPSR, "USR16", m_r[eSPSR_USR]).formatstr("%08X");
/* FIRQ Mode Shadowed Registers */
state_add( ARM7_FR8, "FR8", m_r[eR8_FIQ] ).formatstr("%08X");
state_add( ARM7_FR9, "FR9", m_r[eR9_FIQ] ).formatstr("%08X");
@@ -1334,7 +1423,6 @@ void arm7_cpu_device::execute_core()
do
{
uint32_t pc = R15;
- //printf("%x: %x\n", pc & ~3, m_icount);
if (DEBUG)
debugger_instruction_hook(this, pc);
diff --git a/src/devices/cpu/arm7/arm7.h b/src/devices/cpu/arm7/arm7.h
index ee13d584ce8..a5dc74f2709 100644
--- a/src/devices/cpu/arm7/arm7.h
+++ b/src/devices/cpu/arm7/arm7.h
@@ -85,6 +85,10 @@ enum
eR13, /* Stack Pointer */
eR14, /* Link Register (holds return address) */
eR15, /* Program Counter */
+ eSPSR,
+
+ /* User - All possible bank switched registers */
+ eR8_USR, eR9_USR, eR10_USR, eR11_USR, eR12_USR, eR13_USR, eR14_USR, eSPSR_USR,
/* Fast Interrupt - Bank switched registers */
eR8_FIQ, eR9_FIQ, eR10_FIQ, eR11_FIQ, eR12_FIQ, eR13_FIQ, eR14_FIQ, eSPSR_FIQ,
@@ -311,6 +315,12 @@ protected:
OPCODE_MVN /* 1111 */
};
+ enum stldm_mode
+ {
+ DEFAULT_MODE = 0,
+ USER_MODE = 1
+ };
+
arm7_cpu_device(const machine_config &mconfig, device_type type, const char *tag, device_t *owner, uint32_t clock, uint8_t archRev, uint8_t archFlags, endianness_t endianness);
void postload();
@@ -348,7 +358,7 @@ protected:
struct internal_arm_state
{
- uint32_t m_r[37];
+ uint32_t m_r[NUM_REGS];
uint32_t m_cpsr;
uint32_t m_nflag;
uint32_t m_zflag;
@@ -389,7 +399,7 @@ protected:
const int* m_reg_group;
};
- uint32_t m_r[37];
+ uint32_t m_r[NUM_REGS];
uint32_t m_cpsr;
uint32_t m_nflag;
uint32_t m_zflag;
@@ -472,10 +482,10 @@ protected:
void SwitchMode(uint32_t cpsr_mode_val);
inline ATTR_FORCE_INLINE uint32_t decodeShiftWithCarry(const uint32_t insn, uint32_t *pCarry);
inline ATTR_FORCE_INLINE uint32_t decodeShift(const uint32_t insn);
- template <copro_mode MMU, bdt_s_bit S_BIT> int loadInc(const uint32_t insn, uint32_t rbv, const int mode);
- template <copro_mode MMU, bdt_s_bit S_BIT> int loadDec(const uint32_t insn, uint32_t rbv, const int mode);
- template <copro_mode MMU> int storeInc(const uint32_t insn, uint32_t rbv, const int mode);
- template <copro_mode MMU> int storeDec(const uint32_t insn, uint32_t rbv, const int mode);
+ template <copro_mode MMU, bdt_s_bit S_BIT, stldm_mode USER> int loadInc(const uint32_t insn, uint32_t rbv);
+ template <copro_mode MMU, bdt_s_bit S_BIT, stldm_mode USER> int loadDec(const uint32_t insn, uint32_t rbv);
+ template <copro_mode MMU, stldm_mode USER> int storeInc(const uint32_t insn, uint32_t rbv);
+ template <copro_mode MMU, stldm_mode USER> int storeDec(const uint32_t insn, uint32_t rbv);
void HandleCoProcRT(const uint32_t insn);
void HandleCoProcDT(const uint32_t insn);
template <link_mode LINK> void HandleBranch(const uint32_t insn);
@@ -697,7 +707,7 @@ protected:
uint32_t arg1; /* print_debug argument 2 */
/* register mappings */
- uml::parameter regmap[/*NUM_REGS*/37]; /* parameter to register mappings for all integer registers */
+ uml::parameter regmap[/*NUM_REGS*/45]; /* parameter to register mappings for all integer registers */
/* subroutines */
uml::code_handle * entry; /* entry point */
@@ -833,7 +843,8 @@ protected:
void drctg0f_0(drcuml_block *block, compiler_state *compiler, const opcode_desc *desc);
void drctg0f_1(drcuml_block *block, compiler_state *compiler, const opcode_desc *desc); /* BL */
- inline void update_reg_ptr();
+ inline void update_reg_ptr(const uint32_t old_mode);
+ inline void init_reg_ptr();
void load_fast_iregs(drcuml_block *block);
void save_fast_iregs(drcuml_block *block);
void execute_run_drc();
diff --git a/src/devices/cpu/arm7/arm7core.h b/src/devices/cpu/arm7/arm7core.h
index 08fb91b1863..5051c34ec42 100644
--- a/src/devices/cpu/arm7/arm7core.h
+++ b/src/devices/cpu/arm7/arm7core.h
@@ -45,10 +45,14 @@ enum
{
ARM7_PC = 0,
ARM7_R0, ARM7_R1, ARM7_R2, ARM7_R3, ARM7_R4, ARM7_R5, ARM7_R6, ARM7_R7,
- ARM7_R8, ARM7_R9, ARM7_R10, ARM7_R11, ARM7_R12, ARM7_R13, ARM7_R14, ARM7_R15,
- ARM7_FR8, ARM7_FR9, ARM7_FR10, ARM7_FR11, ARM7_FR12, ARM7_FR13, ARM7_FR14,
- ARM7_IR13, ARM7_IR14, ARM7_SR13, ARM7_SR14, ARM7_FSPSR, ARM7_ISPSR, ARM7_SSPSR,
- ARM7_CPSR, ARM7_AR13, ARM7_AR14, ARM7_ASPSR, ARM7_UR13, ARM7_UR14, ARM7_USPSR
+ ARM7_R8, ARM7_R9, ARM7_R10, ARM7_R11, ARM7_R12, ARM7_R13, ARM7_R14, ARM7_R15, ARM7_SPSR,
+ ARM7_USRR8, ARM7_USRR9, ARM7_USRR10, ARM7_USRR11, ARM7_USRR12, ARM7_USRR13, ARM7_USRR14, ARM7_USRSPSR,
+ ARM7_FR8, ARM7_FR9, ARM7_FR10, ARM7_FR11, ARM7_FR12, ARM7_FR13, ARM7_FR14, ARM7_FSPSR,
+ ARM7_IR13, ARM7_IR14, ARM7_ISPSR,
+ ARM7_SR13, ARM7_SR14, ARM7_SSPSR,
+ ARM7_AR13, ARM7_AR14, ARM7_ASPSR,
+ ARM7_UR13, ARM7_UR14, ARM7_USPSR,
+ ARM7_CPSR
};
/* Coprocessor-related macros */
diff --git a/src/devices/cpu/arm7/arm7help.h b/src/devices/cpu/arm7/arm7help.h
index fcd135f8434..e3627d5be26 100644
--- a/src/devices/cpu/arm7/arm7help.h
+++ b/src/devices/cpu/arm7/arm7help.h
@@ -203,8 +203,8 @@
// used to be functions, but no longer a need, so we'll use define for better speed.
-#define GetRegister(rIndex) *m_rp[rIndex]
-#define SetRegister(rIndex, value) *m_rp[rIndex] = value
+#define GetRegister(rIndex) m_r[rIndex]
+#define SetRegister(rIndex, value) m_r[rIndex] = value
#define GetModeRegister(mode, rIndex) m_r[s_register_table[mode][rIndex]]
#define SetModeRegister(mode, rIndex, value) m_r[s_register_table[mode][rIndex]] = value
diff --git a/src/devices/cpu/arm7/arm7ops.hxx b/src/devices/cpu/arm7/arm7ops.hxx
index d03924ececa..82fe596e4c9 100644
--- a/src/devices/cpu/arm7/arm7ops.hxx
+++ b/src/devices/cpu/arm7/arm7ops.hxx
@@ -317,8 +317,8 @@ uint32_t arm7_cpu_device::decodeShift(const uint32_t insn)
return 0;
}
-template <arm7_cpu_device::copro_mode MMU, arm7_cpu_device::bdt_s_bit S_BIT>
-int arm7_cpu_device::loadInc(const uint32_t insn, uint32_t rbv, const int mode)
+template <arm7_cpu_device::copro_mode MMU, arm7_cpu_device::bdt_s_bit S_BIT, arm7_cpu_device::stldm_mode USER>
+int arm7_cpu_device::loadInc(const uint32_t insn, uint32_t rbv)
{
int result = 0;
rbv &= ~3;
@@ -343,18 +343,35 @@ int arm7_cpu_device::loadInc(const uint32_t insn, uint32_t rbv, const int mode)
}
if (i == 15)
{
- if (S_BIT) /* Pull full contents from stack */
- SetModeRegister(mode, 15, data);
- else //if (MODE32) /* Pull only address, preserve mode & status flags */
- SetModeRegister(mode, 15, data);
- //else
- //{
- // SetModeRegister(mode, 15, (GetModeRegister(mode, 15) & ~0x03FFFFFC) | (data & 0x03FFFFFC));
- //}
+ if (USER)
+ {
+ if (S_BIT) /* Pull full contents from stack */
+ SetModeRegister(eARM7_MODE_USER, 15, data);
+ else //if (MODE32) /* Pull only address, preserve mode & status flags */
+ SetModeRegister(eARM7_MODE_USER, 15, data);
+ //else
+ //{
+ // SetModeRegister(mode, 15, (GetModeRegister(mode, 15) & ~0x03FFFFFC) | (data & 0x03FFFFFC));
+ //}
+ }
+ else
+ {
+ if (S_BIT) /* Pull full contents from stack */
+ SetRegister(15, data);
+ else //if (MODE32) /* Pull only address, preserve mode & status flags */
+ SetRegister(15, data);
+ //else
+ //{
+ // SetModeRegister(mode, 15, (GetModeRegister(mode, 15) & ~0x03FFFFFC) | (data & 0x03FFFFFC));
+ //}
+ }
}
else
{
- SetModeRegister(mode, i, data);
+ if (USER)
+ SetModeRegister(eARM7_MODE_USER, i, data);
+ else
+ SetRegister(i, data);
}
result++;
}
@@ -374,8 +391,8 @@ int arm7_cpu_device::loadInc(const uint32_t insn, uint32_t rbv, const int mode)
return result;
}
-template <arm7_cpu_device::copro_mode MMU, arm7_cpu_device::bdt_s_bit S_BIT>
-int arm7_cpu_device::loadDec(const uint32_t insn, uint32_t rbv, const int mode)
+template <arm7_cpu_device::copro_mode MMU, arm7_cpu_device::bdt_s_bit S_BIT, arm7_cpu_device::stldm_mode USER>
+int arm7_cpu_device::loadDec(const uint32_t insn, uint32_t rbv)
{
int result = 0;
rbv &= ~3;
@@ -400,18 +417,35 @@ int arm7_cpu_device::loadDec(const uint32_t insn, uint32_t rbv, const int mode)
}
if (i == 15)
{
- if (S_BIT) /* Pull full contents from stack */
- SetModeRegister(mode, 15, data);
- else //if (MODE32) /* Pull only address, preserve mode & status flags */
- SetModeRegister(mode, 15, data);
- //else
- //{
- // SetModeRegister(mode, 15, (GetModeRegister(mode, 15) & ~0x03FFFFFC) | (data & 0x03FFFFFC));
- //}
+ if (USER)
+ {
+ if (S_BIT) /* Pull full contents from stack */
+ SetModeRegister(eARM7_MODE_USER, 15, data);
+ else //if (MODE32) /* Pull only address, preserve mode & status flags */
+ SetModeRegister(eARM7_MODE_USER, 15, data);
+ //else
+ //{
+ // SetModeRegister(mode, 15, (GetModeRegister(mode, 15) & ~0x03FFFFFC) | (data & 0x03FFFFFC));
+ //}
+ }
+ else
+ {
+ if (S_BIT) /* Pull full contents from stack */
+ SetRegister(15, data);
+ else //if (MODE32) /* Pull only address, preserve mode & status flags */
+ SetRegister(15, data);
+ //else
+ //{
+ // SetModeRegister(mode, 15, (GetModeRegister(mode, 15) & ~0x03FFFFFC) | (data & 0x03FFFFFC));
+ //}
+ }
}
else
{
- SetModeRegister(mode, i, data);
+ if (USER)
+ SetModeRegister(eARM7_MODE_USER, i, data);
+ else
+ SetRegister(i, data);
}
result++;
}
@@ -431,8 +465,8 @@ int arm7_cpu_device::loadDec(const uint32_t insn, uint32_t rbv, const int mode)
return result;
}
-template <arm7_cpu_device::copro_mode MMU>
-int arm7_cpu_device::storeInc(const uint32_t insn, uint32_t rbv, const int mode)
+template <arm7_cpu_device::copro_mode MMU, arm7_cpu_device::stldm_mode USER>
+int arm7_cpu_device::storeInc(const uint32_t insn, uint32_t rbv)
{
int result = 0;
for (int i = 0; i < 16; i++)
@@ -443,18 +477,24 @@ int arm7_cpu_device::storeInc(const uint32_t insn, uint32_t rbv, const int mode)
if (i == 15) /* R15 is plus 12 from address of STM */
LOG(("%08x: StoreInc on R15\n", R15));
#endif
- if (MMU)
- arm7_cpu_write32_mmu(rbv += 4, GetModeRegister(mode, i));
+ if (USER)
+ if (MMU)
+ arm7_cpu_write32_mmu(rbv += 4, GetModeRegister(eARM7_MODE_USER, i));
+ else
+ arm7_cpu_write32(rbv += 4, GetModeRegister(eARM7_MODE_USER, i));
else
- arm7_cpu_write32(rbv += 4, GetModeRegister(mode, i));
+ if (MMU)
+ arm7_cpu_write32_mmu(rbv += 4, GetRegister(i));
+ else
+ arm7_cpu_write32(rbv += 4, GetRegister(i));
result++;
}
}
return result;
} /* storeInc */
-template <arm7_cpu_device::copro_mode MMU>
-int arm7_cpu_device::storeDec(const uint32_t insn, uint32_t rbv, const int mode)
+template <arm7_cpu_device::copro_mode MMU, arm7_cpu_device::stldm_mode USER>
+int arm7_cpu_device::storeDec(const uint32_t insn, uint32_t rbv)
{
// pre-count the # of registers being stored
int const result = population_count_32(insn & 0x0000ffff);
@@ -470,10 +510,16 @@ int arm7_cpu_device::storeDec(const uint32_t insn, uint32_t rbv, const int mode)
if (i == 15) /* R15 is plus 12 from address of STM */
LOG(("%08x: StoreDec on R15\n", R15));
#endif
- if (MMU)
- arm7_cpu_write32_mmu(rbv, GetModeRegister(mode, i));
+ if (USER)
+ if (MMU)
+ arm7_cpu_write32_mmu(rbv, GetModeRegister(eARM7_MODE_USER, i));
+ else
+ arm7_cpu_write32(rbv, GetModeRegister(eARM7_MODE_USER, i));
else
- arm7_cpu_write32(rbv, GetModeRegister(mode, i));
+ if (MMU)
+ arm7_cpu_write32_mmu(rbv, GetRegister(i));
+ else
+ arm7_cpu_write32(rbv, GetRegister(i));
rbv += 4;
}
}
@@ -524,7 +570,7 @@ void arm7_cpu_device::HandleCoProcDT(const uint32_t insn)
uint32_t rnv = GetRegister(rn); // Get Address Value stored from Rn
uint32_t ornv = rnv; // Keep value of Rn
uint32_t off = (insn & 0xff) << 2; // Offset is << 2 according to manual
- uint32_t *prn = &ARM7REG(rn); // Pointer to our register, so it can be changed in the callback
+ uint32_t *prn = &m_r[s_register_table[m_mode][rn]]; // Pointer to our register, so it can be changed in the callback
#if ARM7_DEBUG_CORE
if (((insn >> 16) & 0xf) == 15 && (insn & 0x200000))
@@ -1651,12 +1697,12 @@ void arm7_cpu_device::HandleMemBlock(const uint32_t insn)
//int curmode = GET_MODE;
//SwitchMode(eARM7_MODE_USER);
LOG(("%08x: User Bank Transfer not fully tested - please check if working properly!\n", R15));
- result = loadInc<MMU, S_BIT>(insn, rbp, eARM7_MODE_USER);
+ result = loadInc<MMU, S_BIT, USER_MODE>(insn, rbp);
// todo - not sure if Writeback occurs on User registers also..
//SwitchMode(curmode);
}
else
- result = loadInc<MMU, S_BIT>(insn, rbp, GET_MODE);
+ result = loadInc<MMU, S_BIT, DEFAULT_MODE>(insn, rbp);
if (WRITEBACK && !m_pendingAbtD)
{
@@ -1725,13 +1771,13 @@ void arm7_cpu_device::HandleMemBlock(const uint32_t insn)
//int curmode = GET_MODE;
//SwitchMode(eARM7_MODE_USER);
LOG(("%08x: User Bank Transfer not fully tested - please check if working properly!\n", R15));
- result = loadDec<MMU, S_BIT>(insn, rbp, eARM7_MODE_USER);
+ result = loadDec<MMU, S_BIT, USER_MODE>(insn, rbp);
// todo - not sure if Writeback occurs on User registers also..
//SwitchMode(curmode);
}
else
{
- result = loadDec<MMU, S_BIT>(insn, rbp, GET_MODE);
+ result = loadDec<MMU, S_BIT, DEFAULT_MODE>(insn, rbp);
}
if (WRITEBACK && !m_pendingAbtD)
@@ -1816,13 +1862,13 @@ void arm7_cpu_device::HandleMemBlock(const uint32_t insn)
//int curmode = GET_MODE;
//SwitchMode(eARM7_MODE_USER);
LOG(("%08x: User Bank Transfer not fully tested - please check if working properly!\n", R15));
- result = storeInc<MMU>(insn, rbp, eARM7_MODE_USER);
+ result = storeInc<MMU, USER_MODE>(insn, rbp);
// todo - not sure if Writeback occurs on User registers also..
//SwitchMode(curmode);
}
else
{
- result = storeInc<MMU>(insn, rbp, GET_MODE);
+ result = storeInc<MMU, DEFAULT_MODE>(insn, rbp);
}
if (WRITEBACK && !m_pendingAbtD)
@@ -1845,13 +1891,13 @@ void arm7_cpu_device::HandleMemBlock(const uint32_t insn)
//int curmode = GET_MODE;
//SwitchMode(eARM7_MODE_USER);
LOG(("%08x: User Bank Transfer not fully tested - please check if working properly!\n", R15));
- result = storeDec<MMU>(insn, rbp, eARM7_MODE_USER);
+ result = storeDec<MMU, USER_MODE>(insn, rbp);
// todo - not sure if Writeback occurs on User registers also..
//SwitchMode(curmode);
}
else
{
- result = storeDec<MMU>(insn, rbp, GET_MODE);
+ result = storeDec<MMU, DEFAULT_MODE>(insn, rbp);
}
if (WRITEBACK && !m_pendingAbtD)