summaryrefslogblamecommitdiffstatshomepage
path: root/src/devices/machine/am79c30.cpp
blob: 9c041d8c383eadcf7ecd16e830e0931ef8c27964 (plain) (tree)
982
983
984
985
986
987
988
989
990
991
992
993
994
995
996
997
998
999
1000
1001
1002
1003
1004
1005
1006
1007
1008
1009
1010
1011
1012
1013
1014
1015
1016
1017
1018
1019
1020
1021
1022
1023
1024
1025
1026
1027
1028
1029
1030
1031
1032
1033
1034
1035
1036
1037
1038
1039
1040
1041
1042
1043
1044
1045
1046
1047
1048
1049
1050
1051
1052
1053
1054
1055
1056
1057
1058
1059
1060
1061
1062
1063
1064
1065
1066
1067
1068
1069
1070
1071
1072
1073
1074
1075
1076
1077
1078
1079
1080
1081
1082
1083
1084
1085
1086
1087
1088
1089
1090
1091
1092
1093
1094
1095
1096
1097
1098
1099
1100
1101
1102
1103
1104
1105
1106
1107
1108
1109
1110
1111
1112
1113
1114
1115
1116
1117
1118
1119
1120
1121
1122
1123
1124
1125
1126
1127
1128
1129
1130
1131
1132
1133
1134
1135
1136
1137
1138
1139
1140
1141
1142
1143
1144
1145
1146
1147
1148
1149
1150
1151
1152
1153
1154
1155
1156
1157
1158
1159
1160
1161
1162
1163
1164
1165
1166
1167
1168
1169
1170
1171
1172
1173
1174
1175
1176
1177
1178
1179
1180
1181
1182
1183
1184
1185
1186
1187
1188
1189
1190
1191
1192
1193
1194
1195
1196
1197
1198
1199
1200
1201
1202
1203
1204
1205
1206
1207
1208
1209
1210
1211
1212
1213
1214
1215
1216
1217
1218
1219
1220
1221
1222
1223
1224
1225
1226
1227
1228
1229
1230
1231
1232
1233
1234
1235
1236
1237
1238
1239
1240
1241
1242
1243
1244
1245
1246
1247
1248
1249
1250
1251
1252
1253
1254
1255
1256
1257
1258
1259
1260
1261
1262
1263
1264
1265
1266
1267
1268
1269
1270
1271
1272
1273
1274
1275
1276
1277
1278
1279
1280
1281
1282
1283
1284
1285
1286
1287
1288
1289
1290
1291
1292
1293
1294
1295
1296
1297
1298
1299
1300
1301
1302
1303
1304
1305
1306
1307
1308
1309
1310
1311
1312
1313
1314
1315
1316
1317
1318
1319
1320
1321
1322
1323
1324
1325
1326
1327
1328
1329
1330
1331
1332
1333
1334
1335
1336
1337
1338
1339
1340
1341
1342
1343
1344
1345
1346
1347
1348
1349
1350
1351
1352
1353
1354
1355
1356
1357
1358
1359
1360
1361
1362
1363
1364
1365
1366
1367
1368
1369
1370
1371
1372
1373
1374
1375
1376
1377
1378
1379
1380
1381
1382
1383
1384
1385
1386
1387
1388
1389
1390
1391
1392
1393
1394
1395
1396
1397
1398
1399
1400
1401
1402
1403
1404
1405
1406
1407
1408
1409
1410
1411
1412
1413
1414
1415
1416
1417
1418
1419
1420
1421
1422
1423
1424
1425
1426
1427
1428
1429
1430
1431
1432
1433
1434
1435
1436
1437
1438
1439
1440
1441
1442
1443
1444
1445
1446
1447
1448
1449
1450
1451
1452
1453
1454
1455
1456
1457
1458
1459
1460
1461
1462
1463
1464
1465
1466
1467
1468
1469
1470
1471
1472
1473
1474
1475
1476
1477
1478
1479
1480
1481
1482
1483
1484
1485
1486
1487
1488
1489
1490
1491
1492
1493
1494
1495
1496
1497
1498
1499
1500
1501
1502
1503
1504
1505
1506
1507
1508
1509
1510
1511
1512
1513
1514
1515
1516
1517
1518
1519
1520
1521
1522
1523
1524
1525
1526
1527
1528
1529
1530
1531
1532
1533
1534
1535
1536
1537
1538
1539
1540
1541
1542
1543
1544
1545
1546
1547
1548
1549
1550
1551
1552
1553
1554
1555
1556
1557
1558
1559
1560
1561
1562
1563
1564
1565
1566
1567
1568
1569
1570
1571
1572
1573
1574
1575
1576
1577
1578
1579
1580
1581
1582
1583
1584
1585
1586
1587
1588
1589
1590
1591
1592
1593
1594
1595
1596
1597
1598
1599
1600
1601
1602
1603
1604
1605
1606
1607
1608
1609
1610
1611
1612
1613
1614
1615
1616
1617
1618
1619
1620
1621
1622
1623
1624
1625
1626
1627
1628
1629
1630
1631
1632
1633
1634
1635
1636
1637
1638
1639
1640
1641
1642
1643
1644
1645
1646
1647
1648
1649
1650
1651
1652
1653
1654
1655
1656
1657
1658
1659
1660
1661
1662
1663
1664
1665
1666
1667
1668
1669
1670
1671
1672
1673
1674
1675
1676
1677
1678
1679
1680
1681
1682
1683
1684
1685
1686
1687
1688
1689
1690
1691
1692
1693
1694
1695
1696
1697
1698
1699
1700
1701
1702
1703
1704
1705
1706
1707
1708
1709
1710
1711
1712
1713
1714
1715
1716
1717
1718
1719
1720
1721
1722
1723
1724
1725
1726
1727
1728
1729
1730
1731
1732
1733
1734
1735
1736
1737
1738
1739
1740
1741
1742
1743
1744
1745
1746
1747
1748
1749
1750
1751
1752
1753
1754
1755
1756
1757
1758
1759
1760
1761
1762
1763
1764
1765
1766
1767
1768
1769
1770
1771
1772
1773
1774
1775
1776
1777
1778
1779
1780
1781
1782
1783
1784
1785
1786
1787
1788
1789
1790
1791
1792
1793
1794
1795
1796
1797
1798
1799
1800
1801
1802
1803
1804
1805
1806
1807
1808
1809
1810
1811
1812
1813
1814
1815
1816
1817
1818
1819
1820
1821
1822
1823
1824
1825
1826
1827
1828
1829
1830
1831
1832
1833
1834
1835
1836
1837
1838
1839
1840
1841
1842
1843
1844
1845
1846
1847
1848
1849
1850
1851
1852
1853
1854
1855
1856
1857
1858
1859
1860
1861
1862
1863
1864
1865
1866
1867
1868
1869
1870
1871
1872
1873
1874
1875
1876
1877
1878
1879
1880
1881
1882
1883
1884
1885
1886
1887
1888
1889
1890
1891
1892
1893
1894
1895
1896
1897
1898
1899
1900
1901
1902
1903
1904
1905
1906
1907
1908
1909
1910
1911
1912
1913
1914
1915
1916
1917
1918
1919
1920
1921
1922
1923
1924
1925
1926
1927
1928
1929
1930
1931
1932
1933
1934
1935
1936
1937
1938
1939
1940
1941
1942
1943
1944
1945
1946
1947
1948
1949
1950
1951
1952
1953
1954
1955
1956
1957
1958
1959
1960
1961
1962
1963
1964
1965
1966
1967
1968
1969
1970
1971
1972
1973
1974
1975
1976
1977
1978
1979
1980
1981
1982
1983
1984
1985
1986
1987
1988
1989
1990
1991
1992
1993
1994
1995
1996
1997
1998
1999
2000
2001
2002
2003
2004
2005
2006
2007
2008
2009
2010
2011
2012
2013
2014
2015
2016
2017
2018
2019
2020
2021
2022
2023
2024
2025
2026
2027
2028
2029
2030
2031
2032
2033
2034
2035
2036
2037
2038
2039
2040
































































































                                                                                                            






















































































































































































































































































                                                                                                                                              
                                                                                        


























                                                                                                                             
                                                                                        












































































                                                                                                                                     
                                                                                                                           
                    
                                                                                                                                                             

































































































































































































































































                                                                                                                                                            


                                                                                                                            









































































































































































































































                                                                                                                                              
                                                                                                                                                             


































































































































































































































































































































































































































































































































































































































































































































































































































































































































































































































































































                                                                                                                                                      
// license:BSD-3-Clause
// copyright-holders:AJR
/****************************************************************************

    AMD Am79C30A Digital Subscriber Controller (DSC)

    TODO: everything (this is a glorified skeleton device)

****************************************************************************/

#include "emu.h"
#include "am79c30.h"

#define VERBOSE 1
#include "logmacro.h"

//**************************************************************************
//  GLOBAL VARIABLES
//**************************************************************************

// device type definitions
DEFINE_DEVICE_TYPE(AM79C30A, am79c30a_device, "am79c30a", "Am79C30A DSC")
//DEFINE_DEVICE_TYPE(AM79C32A, am79c32a_device, "am79c32a", "Am79C32A IDC")


//**************************************************************************
//  DEVICE CONSTRUCTION AND INITIALIZATION
//**************************************************************************

//-------------------------------------------------
//  am79c30a_device - constructor
//-------------------------------------------------

am79c30a_device::am79c30a_device(const machine_config &mconfig, const char *tag, device_t *owner, u32 clock)
	: device_t(mconfig, AM79C30A, tag, owner, clock)
	, m_int_callback(*this)
	, m_init(0)
	, m_init2(0)
	, m_ir(0)
	, m_lsr(0)
	, m_lpr(0)
	, m_lmr1(0)
	, m_lmr2(0)
	, m_mf(0)
	, m_mfsb(0)
	, m_mfqb(0)
	, m_mcr{0, 0, 0}
	, m_mcr4(0)
	, m_x_coeff{0, 0, 0, 0, 0, 0, 0, 0}
	, m_r_coeff{0, 0, 0, 0, 0, 0, 0, 0}
	, m_gx_coeff(0)
	, m_gr_coeff(0)
	, m_ger_coeff(0)
	, m_stgr(0)
	, m_ftgr{0, 0}
	, m_atgr{0, 0}
	, m_mmr1(0)
	, m_mmr2(0)
	, m_mmr3(0)
	, m_stra(0)
	, m_strf(0)
	, m_peakx(0)
	, m_peakr(0)
	, m_tar(0)
	, m_frar{0, 0, 0, 0}
	, m_srar{0, 0, 0, 0}
	, m_drlr(0)
	, m_dtcr(0)
	, m_drcr(0)
	, m_rngr(0)
	, m_dmr1(0)
	, m_dmr2(0)
	, m_dmr3(0)
	, m_dmr4(0)
	, m_asr(0)
	, m_dsr1(0)
	, m_dsr2(0)
	, m_der(0)
	, m_efcr(0)
	, m_ppcr1(0)
	, m_ppsr(0)
	, m_ppier(0)
	, m_mtdr(0)
	, m_mrdr(0)
	, m_citdr0(0)
	, m_cirdr0(0)
	, m_citdr1(0)
	, m_cirdr1(0)
	, m_ppcr2(0)
	, m_ppcr3(0)
	, m_cr(0)
	, m_byte_seq(0)
{
}


//-------------------------------------------------
//  device_start - device-specific startup
//-------------------------------------------------

void am79c30a_device::device_start()
{
	// Save state
	save_item(NAME(m_init));
	save_item(NAME(m_init2));
	save_item(NAME(m_ir));
	save_item(NAME(m_lsr));
	save_item(NAME(m_lpr));
	save_item(NAME(m_lmr1));
	save_item(NAME(m_lmr2));
	save_item(NAME(m_mf));
	save_item(NAME(m_mfsb));
	save_item(NAME(m_mfqb));
	save_item(NAME(m_mcr));
	save_item(NAME(m_mcr4));
	save_item(NAME(m_x_coeff));
	save_item(NAME(m_r_coeff));
	save_item(NAME(m_gx_coeff));
	save_item(NAME(m_gr_coeff));
	save_item(NAME(m_ger_coeff));
	save_item(NAME(m_stgr));
	save_item(NAME(m_ftgr));
	save_item(NAME(m_atgr));
	save_item(NAME(m_mmr1));
	save_item(NAME(m_mmr2));
	save_item(NAME(m_mmr3));
	save_item(NAME(m_stra));
	save_item(NAME(m_strf));
	save_item(NAME(m_peakx));
	save_item(NAME(m_peakr));
	save_item(NAME(m_tar));
	save_item(NAME(m_frar));
	save_item(NAME(m_srar));
	save_item(NAME(m_drlr));
	save_item(NAME(m_dtcr));
	save_item(NAME(m_drcr));
	save_item(NAME(m_rngr));
	save_item(NAME(m_dmr1));
	save_item(NAME(m_dmr2));
	save_item(NAME(m_dmr3));
	save_item(NAME(m_dmr4));
	save_item(NAME(m_asr));
	save_item(NAME(m_dsr1));
	save_item(NAME(m_dsr2));
	save_item(NAME(m_der));
	save_item(NAME(m_efcr));
	save_item(NAME(m_ppcr1));
	save_item(NAME(m_ppsr));
	save_item(NAME(m_ppier));
	save_item(NAME(m_mtdr));
	save_item(NAME(m_mrdr));
	save_item(NAME(m_citdr0));
	save_item(NAME(m_cirdr0));
	save_item(NAME(m_citdr1));
	save_item(NAME(m_cirdr1));
	save_item(NAME(m_ppcr2));
	save_item(NAME(m_ppcr3));
	save_item(NAME(m_cr));
	save_item(NAME(m_byte_seq));
}


//-------------------------------------------------
//  device_reset - device-specific reset
//-------------------------------------------------

void am79c30a_device::device_reset()
{
	// Clear init registers
	m_init = 0;
	m_init2 = 0;

	// Clear interrupt register and deactivate INT
	m_ir = 0;
	m_int_callback(CLEAR_LINE);

	// Clear LIU registers (except HSW bit)
	m_lsr &= 0x40;
	m_lpr = 0;
	m_lmr1 = 0;
	m_lmr2 = 0;
	m_mf = 0;
	m_mfsb = 0x40;
	m_mfqb = 0x0f;

	// Clear MUX registers
	m_mcr[0] = m_mcr[1] = m_mcr[2] = 0;
	m_mcr4 = 0;

	// Clear MAP registers
	m_ftgr[0] = m_ftgr[1] = 0;
	m_mmr1 = 0;
	m_mmr2 = 0;
	m_mmr3 = 0;
	m_stra = 0;
	m_strf = 0;

	// Clear DLC registers
	m_dmr1 = 0;
	m_dmr2 = 0;
	m_dmr3 = 0;
	m_dmr4 = 0;
	m_asr = 0;
	m_dsr1 = 0;
	m_dsr2 = 0;
	m_der = 0;

	// Set PP register defaults
	m_ppcr1 = 0x01;
	m_ppsr = 0x02;
	m_ppier = 0x80;
	m_mtdr = 0xff;
	m_mrdr = 0;
	m_citdr0 = 0x0f;
	m_cirdr0 = 0x0f;
	m_citdr1 = 0x3f;
	m_cirdr1 = 0x3f;
	m_ppcr2 = 0xc0; // revision-level dependent
	m_ppcr3 = 0x17;
}


//**************************************************************************
//  GLOBAL INITIALIZATION
//**************************************************************************

//-------------------------------------------------
//  set_init - indirect write to INIT register
//-------------------------------------------------

void am79c30a_device::set_init(u8 data)
{
	if ((m_init & 0x03) != (data & 0x03))
		LOG("%s: %s mode\n", machine().describe_context(),
					(data & 0x03) == 0x01 ? "Active voice and data" :
					(data & 0x03) == 0x02 ? "Active data only" :
					(data & 0x03) == 0x03 ? "Power-down" : "Idle");
	if (BIT(m_init, 2) != BIT(data, 2))
		LOG("%s: INT output %sabled\n", machine().describe_context(), BIT(data, 2) ? "en" : "dis");
	if ((m_init & 0x38) != (data & 0x38))
	{
		unsigned div;
		if ((data & 0x38) == 0x08)
			div = 1;
		else if ((data & 0x38) == 0x10)
			div = 4;
		else if ((data & 0x38) == 0x20)
			div = 3;
		else
			div = 2;
		LOG("%s: MCLK frequency = %.3f MHz\n", machine().describe_context(), clocks_to_attotime(div).as_mhz());
	}
	if (BIT(m_init, 6) != BIT(data, 6))
		LOG("%s: DLC receiver abort %sabled\n", machine().describe_context(), BIT(data, 6) ? "en" : "dis");
	if (BIT(m_init, 7) != BIT(data, 7))
		LOG("%s: DLC transmitter abort %sabled\n", machine().describe_context(), BIT(data, 7) ? "en" : "dis");

	m_init = data;
}


//-------------------------------------------------
//  set_init2 - indirect write to INIT2 register
//-------------------------------------------------

void am79c30a_device::set_init2(u8 data)
{
	if (BIT(m_init2, 5) != BIT(data, 5))
		LOG("%s: Power-down %sabled\n", machine().describe_context(), BIT(data, 5) ? "en" : "dis");
	if (BIT(m_init2, 4) != BIT(data, 4))
		LOG("%s: Multiframe interrupt filter %sabled\n", machine().describe_context(), BIT(data, 4) ? "en" : "dis");
	if (BIT(m_init2, 3) != BIT(data, 3))
		LOG("%s: Clock speed-up option %sabled\n", machine().describe_context(), BIT(data, 3) ? "en" : "dis");
	if ((m_init2 & 0x07) != (data & 0x07))
	{
		if ((data & 0x07) == 0x00)
			LOG("%s: MCLK frequency determined by INIT\n", machine().describe_context());
		else if ((data & 0x07) < 0x04)
			LOG("%s: MCLK frequency = %.1f kHz\n", machine().describe_context(), clocks_to_attotime(4 << (data & 0x07)).as_khz());
		else if ((data & 0x07) == 0x04)
			LOG("%s: MCLK stopped in high state\n", machine().describe_context());
		else
			logerror("%s: MCLK reserved setting\n", machine().describe_context());
	}
	if ((data & 0xc0) != 0 && !machine().side_effects_disabled())
		logerror("%s: Writing %02XH to INIT2 reserved bits\n", machine().describe_context(), data & 0xc0);

	m_init2 = data;
}


//**************************************************************************
//  INTERRUPT HANDLING
//**************************************************************************

//-------------------------------------------------
//  ir_r - direct read from interrupt register
//-------------------------------------------------

u8 am79c30a_device::ir_r()
{
	u8 ir = m_ir;

	if (ir != 0 && !machine().side_effects_disabled())
	{
		// Clear register and deactivate INT output
		m_ir = 0;
		m_int_callback(CLEAR_LINE);
	}

	return ir;
}


//**************************************************************************
//  LINE INTERFACE UNIT (LIU)
//**************************************************************************

//-------------------------------------------------
//  get_lsr - indirect read from LIU status
//  register
//-------------------------------------------------

u8 am79c30a_device::get_lsr()
{
	u8 lsr = m_lsr;

	// Bits 3, 4, 5 and 7 are cleared when read by microprocessor
	if (!machine().side_effects_disabled())
		m_lsr &= 0x47;

	return lsr;
}


//-------------------------------------------------
//  set_lpr - indirect write to LIU D-channel
//  priority register
//-------------------------------------------------

void am79c30a_device::set_lpr(u8 data)
{
	if ((data & 0xf0) != 0)
	{
		logerror("%s: Writing %X to LPR reserved upper bits\n", machine().describe_context(), data);
		data &= 0x0f;
	}

	LOG("%s: LIU D-channel access priority level set to %d\n", machine().describe_context(), data);

	m_lpr = data;
}


//-------------------------------------------------
//  set_lmr1 - indirect write to LIU mode register
//  1
//-------------------------------------------------

void am79c30a_device::set_lmr1(u8 data)
{
	if (BIT(data, 0) != BIT(m_lmr1, 0))
		LOG("%s: B1 transmit %sabled\n", machine().describe_context(), BIT(data, 0) ? "en" : "dis");
	if (BIT(data, 1) != BIT(m_lmr1, 1))
		LOG("%s: B2 transmit %sabled\n", machine().describe_context(), BIT(data, 1) ? "en" : "dis");
	if (BIT(data, 2) != BIT(m_lmr1, 2))
		LOG("%s: F transmit %sabled\n", machine().describe_context(), BIT(data, 2) ? "dis" : "en");
	if (BIT(data, 3) != BIT(m_lmr1, 3))
		LOG("%s: Fa transmit %sabled\n", machine().describe_context(), BIT(data, 3) ? "dis" : "en");
	if (BIT(data, 4) != BIT(m_lmr1, 4))
		LOG("%s: %sctivation request\n", machine().describe_context(), BIT(data, 4) ? "A" : "No a");
	if (BIT(data, 5) != BIT(m_lmr1, 5))
		LOG("%s: %sF8 to F3 transition %s\n", machine().describe_context(), BIT(data, 5) ? "" : "No ");
	if (BIT(data, 6) != BIT(m_lmr1, 6))
		LOG("%s: LIU receiver/transmitter %sabled\n", machine().describe_context(), BIT(data, 6) ? "en" : "dis");
	if (BIT(data, 7))
		logerror("%s: LMR1 reserved bit 7 set\n", machine().describe_context());

	m_lmr1 = data;
}


//-------------------------------------------------
//  set_lmr2 - indirect write to LIU mode register
//  2
//-------------------------------------------------

void am79c30a_device::set_lmr2(u8 data)
{
	if (BIT(data, 0) != BIT(m_lmr2, 0))
		LOG("%s: D-channel loopback at DSC %sabled\n", machine().describe_context(), BIT(data, 0) ? "en" : "dis");
	if (BIT(data, 1) != BIT(m_lmr2, 1))
		LOG("%s: D-channel loopback at LIU %sabled\n", machine().describe_context(), BIT(data, 1) ? "en" : "dis");
	if (BIT(data, 2) != BIT(m_lmr2, 2))
		LOG("%s: D-channel back-off %sabled\n", machine().describe_context(), BIT(data, 2) ? "dis" : "en");
	if (BIT(data, 3) != BIT(m_lmr2, 3))
		LOG("%s: F3 change of state interrupt %sabled\n", machine().describe_context(), BIT(data, 3) ? "en" : "dis");
	if (BIT(data, 4) != BIT(m_lmr2, 4))
		LOG("%s: F8 change of state interrupt %sabled\n", machine().describe_context(), BIT(data, 4) ? "en" : "dis");
	if (BIT(data, 5) != BIT(m_lmr2, 5))
		LOG("%s: HSW interrupt %sabled\n", machine().describe_context(), BIT(data, 5) ? "en" : "dis");
	if (BIT(data, 6) != BIT(m_lmr2, 6))
		LOG("%s: F7 change of state interrupt %sabled\n", machine().describe_context(), BIT(data, 6) ? "en" : "dis");
	if (BIT(data, 7))
		logerror("%s: LMR2 reserved bit 7 set\n", machine().describe_context());

	m_lmr2 = data;
}


//-------------------------------------------------
//  set_mf - indirect write to multiframe register
//-------------------------------------------------

void am79c30a_device::set_mf(u8 data)
{
	if (BIT(data, 0) != BIT(m_mf, 0))
		LOG("%s: Multiframe sync %sabled\n", machine().describe_context(), BIT(data, 0) ? "en" : "dis");
	if (BIT(data, 1) != BIT(m_mf, 1))
		LOG("%s: S-data available interrupt %sabled\n", machine().describe_context(), BIT(data, 1) ? "en" : "dis");
	if (BIT(data, 2) != BIT(m_mf, 2))
		LOG("%s: Q-bit buffer available interrupt %sabled\n", machine().describe_context(), BIT(data, 2) ? "en" : "dis");
	if (BIT(data, 3) != BIT(m_mf, 3))
		LOG("%s: Multiframe change of state interrupt %sabled\n", machine().describe_context(), BIT(data, 3) ? "en" : "dis");
	if (BIT(data, 4) != BIT(m_mf, 4))
		LOG("%s: %sirst subframe\n", machine().describe_context(), BIT(data, 4) ? "F" : "Not f");

	// Bit 7 is read-only
	m_mf = (data & 0x1f) | (m_mf & 0x80);
}


//-------------------------------------------------
//  set_mfqb - indirect write to multiframe Q-bit
//  buffer
//-------------------------------------------------

void am79c30a_device::set_mfqb(u8 data)
{
	LOG("%s: Multiframe Q-bit buffer = %02XH\n", machine().describe_context(), data);

	// Bits 5, 6, 7 not used
	m_mfqb = data & 0x1f;
}


//**************************************************************************
//  MULTIPLEXER (MUX)
//**************************************************************************

const char *const am79c30a_device::s_mcr_channels[16] = {
	"No connection",
	"B1 (LIU)",
	"B2 (LIU)",
	"Ba (MAP)",
	"Bb (MPI)",
	"Bc (MPI)",
	"Bd (PP channel 1)",
	"Be (PP channel 2)",
	"Bf (PP channel 3)",
	"Reserved",
	"Reserved",
	"Reserved",
	"Reserved",
	"Reserved",
	"Reserved",
	"Reserved"
};


//-------------------------------------------------
//  set_mcr - indirect write to MUX control
//  register 1, 2 or 3 (bidirectional paths)
//-------------------------------------------------

void am79c30a_device::set_mcr(unsigned n, u8 data)
{
	if (m_mcr[n] != data)
	{
		if (data == 0)
			LOG("%s: No connect (MCR%d)\n", machine().describe_context(), n + 1);
		else if ((data & 0xf0) >> 4 == (data & 0x0f))
			LOG("%s: %s loopback (MCR%d)\n", machine().describe_context(), s_mcr_channels[data & 0x0f], n + 1);
		else
			LOG("%s: %s <-> %s (MCR%d)\n", machine().describe_context(), s_mcr_channels[(data & 0xf0) >> 4], s_mcr_channels[data & 0x0f], n + 1);
	}

	m_mcr[n] = data;
}


//-------------------------------------------------
//  set_mcr4 - indirect write to MUX control
//  register 4
//-------------------------------------------------

void am79c30a_device::set_mcr4(u8 data)
{
	if (BIT(data, 3) != BIT(m_mcr4, 3))
		LOG("%s: Bb-/Bc-channel byte available interrupt %sabled\n", machine().describe_context(), BIT(data, 3) ? "en" : "dis");
	if (BIT(data, 4) != BIT(m_mcr4, 4))
		LOG("%s: Bb bit order %sreversed (%cSB first)\n", machine().describe_context(), BIT(data, 4) ? "" : "not ", BIT(data, 4) ? 'L' : 'M');
	if (BIT(data, 5) != BIT(m_mcr4, 5))
		LOG("%s: Bc bit order %sreversed (%cSB first)\n", machine().describe_context(), BIT(data, 5) ? "" : "not ", BIT(data, 5) ? 'L' : 'M');
	if ((data & 0xc7) != 0)
		logerror("%s: Writing %02XH to MCR4 reserved bits\n", machine().describe_context(), data & 0xc7);

	m_mcr4 = data;
}


//**************************************************************************
//  MAIN AUDIO PROCESSOR (MAP)
//**************************************************************************

//-------------------------------------------------
//  set_x_coeff - indirect write to X-filter
//  coefficient register (16 bytes)
//-------------------------------------------------

void am79c30a_device::set_x_coeff(unsigned n, u8 data, bool msb)
{
	LOG("%s: Writing %02XH to X h%u %cSB\n", machine().describe_context(), data, n, msb ? 'M' : 'L');

	if (msb)
		m_x_coeff[n] = (m_x_coeff[n] & 0x00ff) | u16(data) << 8;
	else
		m_x_coeff[n] = (m_x_coeff[n] & 0xff00) | data;
}


//-------------------------------------------------
//  set_r_coeff - indirect write to R-filter
//  coefficient register (16 bytes)
//-------------------------------------------------

void am79c30a_device::set_r_coeff(unsigned n, u8 data, bool msb)
{
	LOG("%s: Writing %02XH to R h%u %cSB\n", machine().describe_context(), data, n, msb ? 'M' : 'L');

	if (msb)
		m_r_coeff[n] = (m_r_coeff[n] & 0x00ff) | u16(data) << 8;
	else
		m_r_coeff[n] = (m_r_coeff[n] & 0xff00) | data;

}


//-------------------------------------------------
//  set_gx_coeff - indirect write to GX-gain
//  coefficient register (2 bytes)
//-------------------------------------------------

void am79c30a_device::set_gx_coeff(u8 data, bool msb)
{
	LOG("%s: Writing %02XH to GX %cSB\n", machine().describe_context(), data, msb ? 'M' : 'L');

	if (msb)
		m_gx_coeff = (m_gx_coeff & 0x00ff) | u16(data) << 8;
	else
		m_gx_coeff = (m_gx_coeff & 0xff00) | data;
}


//-------------------------------------------------
//  set_gr_coeff - indirect write to GR-gain
//  coefficient register (2 bytes)
//-------------------------------------------------

void am79c30a_device::set_gr_coeff(u8 data, bool msb)
{
	LOG("%s: Writing %02XH to GR %cSB\n", machine().describe_context(), data, msb ? 'M' : 'L');

	if (msb)
		m_gr_coeff = (m_gr_coeff & 0x00ff) | u16(data) << 8;
	else
		m_gr_coeff = (m_gr_coeff & 0xff00) | data;
}


//-------------------------------------------------
//  set_ger_coeff - indirect write to GER-gain
//  coefficient register (2 bytes)
//-------------------------------------------------

void am79c30a_device::set_ger_coeff(u8 data, bool msb)
{
	LOG("%s: Writing %02XH to GER %cSB\n", machine().describe_context(), data, msb ? 'M' : 'L');

	if (msb)
		m_ger_coeff = (m_ger_coeff & 0x00ff) | u16(data) << 8;
	else
		m_ger_coeff = (m_ger_coeff & 0xff00) | data;
}


//-------------------------------------------------
//  set_stgr - indirect write to sidetone-gain
//  coefficient register (2 bytes)
//-------------------------------------------------

void am79c30a_device::set_stgr(u8 data, bool msb)
{
	LOG("%s: Writing %02XH to STGR %cSB\n", machine().describe_context(), data, msb ? 'M' : 'L');

	if (msb)
		m_stgr = (m_stgr & 0x00ff) | u16(data) << 8;
	else
		m_stgr = (m_stgr & 0xff00) | data;
}


//-------------------------------------------------
//  set_ftgr - indirect write to frequency
//  tone generator register 1 or 2
//-------------------------------------------------

void am79c30a_device::set_ftgr(unsigned n, u8 data)
{
	LOG("%s: Writing %02XH to FTGR%u\n", machine().describe_context(), data, n + 1);

	m_ftgr[n] = data;
}


//-------------------------------------------------
//  set_atgr - indirect write to amplitude
//  tone generator register 1 or 2
//-------------------------------------------------

void am79c30a_device::set_atgr(unsigned n, u8 data)
{
	LOG("%s: Writing %02XH to ATGR%u\n", machine().describe_context(), data, n + 1);

	m_atgr[n] = data;
}


//-------------------------------------------------
//  set_mmr1 - indirect write to MAP mode register
//  1
//-------------------------------------------------

void am79c30a_device::set_mmr1(u8 data)
{
	if (BIT(m_mmr1, 0) != BIT(data, 0))
		LOG("%s: %s-law\n", machine().describe_context(), BIT(data, 0) ? "A" : "u");
	if (BIT(m_mmr1, 1) != BIT(data, 1))
		LOG("%s: GX %s\n", machine().describe_context(), BIT(data, 1) ? "coefficient loaded" : "bypassed");
	if (BIT(m_mmr1, 2) != BIT(data, 2))
		LOG("%s: GR %s\n", machine().describe_context(), BIT(data, 2) ? "coefficient loaded" : "bypassed");
	if (BIT(m_mmr1, 3) != BIT(data, 3))
		LOG("%s: GER %s\n", machine().describe_context(), BIT(data, 3) ? "coefficient loaded" : "bypassed");
	if (BIT(m_mmr1, 4) != BIT(data, 4))
		LOG("%s: X %s\n", machine().describe_context(), BIT(data, 4) ? "coefficient loaded" : "bypassed");
	if (BIT(m_mmr1, 5) != BIT(data, 5))
		LOG("%s: R %s\n", machine().describe_context(), BIT(data, 5) ? "coefficient loaded" : "bypassed");
	if (BIT(m_mmr1, 6) != BIT(data, 6))
		LOG("%s: Sidetone gain %s\n", machine().describe_context(), BIT(data, 6) ? "coefficient loaded" : "= -18 dB");
	if (BIT(m_mmr1, 7) != BIT(data, 7))
		LOG("%s: Digital loopback at MAP #1 %sabled\n", machine().describe_context(), BIT(data, 7) ? "en" : "dis");

	m_mmr1 = data;
}


//-------------------------------------------------
//  set_mmr2 - indirect write to MAP mode register
//  2
//-------------------------------------------------

void am79c30a_device::set_mmr2(u8 data)
{
	if (BIT(m_mmr2, 0) != BIT(data, 0))
		LOG("%s: AIN%c selected\n", machine().describe_context(), BIT(data, 0) ? 'B' : 'A');
	if (BIT(m_mmr2, 1) != BIT(data, 1))
		LOG("%s: %s selected\n", machine().describe_context(), BIT(data, 1) ? "LS1/LS2" : "EAR1/EAR2");
	if (BIT(m_mmr2, 2) != BIT(data, 2))
		LOG("%s: DTMF %sabled\n", machine().describe_context(), BIT(data, 2) ? "en" : "dis");
	if (BIT(m_mmr2, 3) != BIT(data, 3))
		LOG("%s: Tone generator %sabled\n", machine().describe_context(), BIT(data, 3) ? "en" : "dis");
	if (BIT(m_mmr2, 4) != BIT(data, 4))
		LOG("%s: Tone ringer %sabled\n", machine().describe_context(), BIT(data, 4) ? "en" : "dis");
	if (BIT(m_mmr2, 5) != BIT(data, 5))
		LOG("%s: High pass filter %sabled\n", machine().describe_context(), BIT(data, 5) ? "en" : "dis");
	if (BIT(m_mmr2, 6) != BIT(data, 6))
		LOG("%s: ADC auto-zero function %sabled\n", machine().describe_context(), BIT(data, 6) ? "en" : "dis");
	if (BIT(data, 7))
		logerror("%s: MMR2 reserved bit 7 set\n", machine().describe_context());

	m_mmr2 = data;
}


//-------------------------------------------------
//  set_mmr3 - indirect write to MAP mode register
//  3
//-------------------------------------------------

void am79c30a_device::set_mmr3(u8 data)
{
	if (BIT(data, 7))
		logerror("%s: MMR3 reserved bit 7 set\n", machine().describe_context());
	if ((m_mmr3 & 0x70) != (data & 0x70))
	{
		if ((data & 0x70) > 0x40)
			logerror("%s: Reserved pre-amplifier setting\n", machine().describe_context());
		else
			LOG("%s: +%d-dB pre-amplifier gain (%.3f-V maximum peak input voltage)\n", machine().describe_context(),
				((data & 0x70) >> 4) * 6,
				1.250 / (1 << ((data & 0x70) >> 4)));
	}
	if (BIT(m_mmr3, 3) != BIT(data, 3))
		LOG("%s: Mute %s\n", machine().describe_context(), BIT(data, 3) ? "on" : "off");
	if (BIT(m_mmr3, 2) != BIT(data, 2))
		LOG("%s: Digital loopback 2 %sabled\n", machine().describe_context(), BIT(data, 2) ? "en" : "dis");
	if (BIT(m_mmr3, 1) != BIT(data, 1))
		LOG("%s: EAR %s LS %sly enabled\n", machine().describe_context(), BIT(data, 1) ? "and" : "or", BIT(data, 1) ? "simultaneous" : "exclusive");
	if (BIT(m_mmr3, 0) != BIT(data, 0))
		LOG("%s: Secondary tone ringer %sabled\n", machine().describe_context(), BIT(data, 0) ? "en" : "dis");

	m_mmr3 = data;
}


//-------------------------------------------------
//  set_stra - indirect write to secondary tone
//  ringer amplitude register
//-------------------------------------------------

void am79c30a_device::set_stra(u8 data)
{
	if ((data & 0x0f) != 0)
		logerror("%s: STRA reserved bits %02XH set\n", machine().describe_context(), data & 0x0f);
	if ((m_stra & 0xf0) != (data & 0xf0))
	{
		if ((data & 0xf0) == 0)
			LOG("%s: Secondary tone ringer silent\n", machine().describe_context());
		else if ((data & 0xf0) < 0x80)
			logerror("%s: Secondary tone ringer reserved setting\n", machine().describe_context());
		else
		{
			u8 a = 15 - ((data & 0xf0) >> 4);
			LOG("%s: Secondary tone ringer %.2f V peak-to-peak, %d dB relative\n", machine().describe_context(),
				BIT(a, 0) ? 3.53553390593274 : 5.0 / (1 << (a / 2)),
				a * -3);
		}
	}

	m_stra = data;
}


//-------------------------------------------------
//  set_strf - indirect write to secondary tone
//  ringer frequency register
//-------------------------------------------------

void am79c30a_device::set_strf(u8 data)
{
	if (m_strf != data)
		LOG("%s: Secondary tone ringer frequency control = %02XH\n", machine().describe_context(), data);

	m_strf = data;
}


//**************************************************************************
//  DATA LINK CONTROLLER (DLC)
//**************************************************************************

//-------------------------------------------------
//  set_tar - indirect write to transmit address
//  register
//-------------------------------------------------

void am79c30a_device::set_tar(u8 data, bool msb)
{
	LOG("%s: Writing %02XH to TAR %cSB\n", machine().describe_context(), data, msb ? 'M' : 'L');

	if (msb)
		m_tar = (m_tar & 0x00ff) | u16(data) << 8;
	else
		m_tar = (m_tar & 0xff00) | data;
}


//-------------------------------------------------
//  set_frar - indirect write to first received
//  byte address register
//-------------------------------------------------

void am79c30a_device::set_frar(unsigned n, u8 data)
{
	LOG("%s: Writing %02XH to FRAR%u\n", machine().describe_context(), data, n + 1);

	m_frar[n] = data;
}


//-------------------------------------------------
//  set_srar - indirect write to second received
//  byte address register
//-------------------------------------------------

void am79c30a_device::set_srar(unsigned n, u8 data)
{
	LOG("%s: Writing %02XH to SRAR%u\n", machine().describe_context(), data, n + 1);

	m_srar[n] = data;
}


//-------------------------------------------------
//  set_drlr - indirect write to D-channel receive
//  byte limit register
//-------------------------------------------------

void am79c30a_device::set_drlr(u8 data, bool msb)
{
	LOG("%s: Writing %02XH to DRLR %cSB\n", machine().describe_context(), data, msb ? 'M' : 'L');

	if (msb)
		m_drlr = (m_drlr & 0x00ff) | u16(data) << 8;
	else
		m_drlr = (m_drlr & 0xff00) | data;
}


//-------------------------------------------------
//  set_dtcr - indirect write to D-channel transmit
//  byte count register
//-------------------------------------------------

void am79c30a_device::set_dtcr(u8 data, bool msb)
{
	LOG("%s: Writing %02XH to DTCR %cSB\n", machine().describe_context(), data, msb ? 'M' : 'L');

	if (msb)
		m_dtcr = (m_dtcr & 0x00ff) | u16(data) << 8;
	else
		m_dtcr = (m_dtcr & 0xff00) | data;

	m_dsr1 &= 0x3f;
	m_der &= 0x7b;
}


//-------------------------------------------------
//  set_rngr - indirect write to random number
//  generator register
//-------------------------------------------------

void am79c30a_device::set_rngr(u8 data, bool msb)
{
	LOG("%s: Writing %02XH to RNGR %cSB\n", machine().describe_context(), data, msb ? 'M' : 'L');

	if (msb)
		m_rngr = (m_rngr & 0x00ff) | u16(data) << 8;
	else
		m_rngr = (m_rngr & 0xff00) | data;
}


//-------------------------------------------------
//  dctb_w - direct write to D-channel transmit
//  buffer register (FIFO)
//-------------------------------------------------

void am79c30a_device::dctb_w(u8 data)
{
	LOG("%s: Writing %02XH to DCTB\n", machine().describe_context(), data);
}


//-------------------------------------------------
//  dcrb_r - direct read from D-channel receive
//  buffer register (FIFO)
//-------------------------------------------------

u8 am79c30a_device::dcrb_r()
{
	if (!machine().side_effects_disabled())
		LOG("%s: Reading from DCRB\n", machine().describe_context());

	return 0;
}


//-------------------------------------------------
//  set_dmr1 - indirect write to D-channel mode
//  register 1
//-------------------------------------------------

void am79c30a_device::set_dmr1(u8 data)
{
	if (BIT(m_dmr1, 0) != BIT(data, 0))
		LOG("%s: D-channel transmit threshold interrupt %sabled\n", machine().describe_context(), BIT(data, 0) ? "en" : "dis");
	if (BIT(m_dmr1, 1) != BIT(data, 1))
		LOG("%s: D-channel receive threshold interrupt %sabled\n", machine().describe_context(), BIT(data, 1) ? "en" : "dis");
	if (BIT(m_dmr1, 2) != BIT(data, 2))
		LOG("%s: Transmit Address Register %sabled\n", machine().describe_context(), BIT(data, 2) ? "en" : "dis");
	if (BIT(m_dmr1, 3) != BIT(data, 3))
		LOG("%s: End of receive packet interrupt %sabled\n", machine().describe_context(), BIT(data, 3) ? "en" : "dis");
	for (int n = 0; n < 4; n++)
		if (BIT(m_dmr1, n + 4) != BIT(data, n + 4))
			LOG("%s: FRAR%d/SRAR%d %sabled\n", machine().describe_context(), n + 1, n + 1, BIT(data, n + 4) ? "en" : "dis");

	m_dmr1 = data;
}


//-------------------------------------------------
//  set_dmr2 - indirect write to D-channel mode
//  register 2
//-------------------------------------------------

void am79c30a_device::set_dmr2(u8 data)
{
	if (BIT(m_dmr2, 0) != BIT(data, 0))
		LOG("%s: Receiver abort interrupt %sabled\n", machine().describe_context(), BIT(data, 0) ? "en" : "dis");
	if (BIT(m_dmr2, 1) != BIT(data, 1))
		LOG("%s: Non-integer number of bytes receive interrupt %sabled\n", machine().describe_context(), BIT(data, 1) ? "en" : "dis");
	if (BIT(m_dmr2, 2) != BIT(data, 2))
		LOG("%s: Collision abort detected interrupt %sabled\n", machine().describe_context(), BIT(data, 2) ? "en" : "dis");
	if (BIT(m_dmr2, 3) != BIT(data, 3))
		LOG("%s: FCS error interrupt %sabled\n", machine().describe_context(), BIT(data, 3) ? "en" : "dis");
	if (BIT(m_dmr2, 4) != BIT(data, 4))
		LOG("%s: Overflow error interrupt %sabled\n", machine().describe_context(), BIT(data, 4) ? "en" : "dis");
	if (BIT(m_dmr2, 5) != BIT(data, 5))
		LOG("%s: Underflow error interrupt %sabled\n", machine().describe_context(), BIT(data, 5) ? "en" : "dis");
	if (BIT(m_dmr2, 6) != BIT(data, 6))
		LOG("%s: Overrun error interrupt %sabled\n", machine().describe_context(), BIT(data, 6) ? "en" : "dis");
	if (BIT(m_dmr2, 7) != BIT(data, 7))
		LOG("%s: Underrun error interrupt %sabled\n", machine().describe_context(), BIT(data, 7) ? "en" : "dis");

	m_dmr2 = data;
}


//-------------------------------------------------
//  set_dmr3 - indirect write to D-channel mode
//  register 3
//-------------------------------------------------

void am79c30a_device::set_dmr3(u8 data)
{
	if (BIT(m_dmr3, 0) != BIT(data, 0))
		LOG("%s: Valid address/end of address interrupt %sabled\n", machine().describe_context(), BIT(data, 0) ? "en" : "dis");
	if (BIT(m_dmr3, 1) != BIT(data, 1))
		LOG("%s: End of valid transmit packet interrupt %sabled\n", machine().describe_context(), BIT(data, 1) ? "en" : "dis");
	if (BIT(m_dmr3, 2) != BIT(data, 2))
		LOG("%s: Last byte of received packet interrupt %sabled\n", machine().describe_context(), BIT(data, 2) ? "en" : "dis");
	if (BIT(m_dmr3, 3) != BIT(data, 3))
		LOG("%s: Receive byte available interrupt %sabled\n", machine().describe_context(), BIT(data, 3) ? "en" : "dis");
	if (BIT(m_dmr3, 4) != BIT(data, 4))
		LOG("%s: Last byte transmitted interrupt %sabled\n", machine().describe_context(), BIT(data, 4) ? "en" : "dis");
	if (BIT(m_dmr3, 5) != BIT(data, 5))
		LOG("%s: Transmit buffer available interrupt %sabled\n", machine().describe_context(), BIT(data, 5) ? "en" : "dis");
	if (BIT(m_dmr3, 6) != BIT(data, 6))
		LOG("%s: Received packet lost interrupt %sabled\n", machine().describe_context(), BIT(data, 6) ? "en" : "dis");
	if (BIT(m_dmr3, 7) != BIT(data, 7))
		LOG("%s: FCS transfer to FIFO %sabled\n", machine().describe_context(), BIT(data, 7) ? "en" : "dis");

	m_dmr3 = data;
}


//-------------------------------------------------
//  set_dmr4 - indirect write to D-channel mode
//  register 4
//-------------------------------------------------

void am79c30a_device::set_dmr4(u8 data)
{
	if ((m_dmr4 & 0x03) != (data & 0x03))
	{
		if ((data & 0x03) == 0)
			LOG("%s: Receiver threshold = 1 byte\n", machine().describe_context());
		else
			LOG("%s: Receiver threshold = %d/%d bytes\n", machine().describe_context(), 1 << (data & 0x03), std::min((data & 0x03) * 8 + 8, 30));
	}
	if ((m_dmr4 & 0x0c) != (data & 0x0c))
	{
		if ((data & 0x0c) == 0)
			LOG("%s: Transmitter threshold = 1 byte\n", machine().describe_context());
		else
			LOG("%s: Transmitter threshold = %d/%d bytes\n", machine().describe_context(), 1 << ((data & 0x0c) >> 2), (data & 0x0c) + 2);
	}
	if (BIT(m_dmr4, 4) != BIT(data, 4))
		LOG("%s: Interframe fill = %s idle\n", machine().describe_context(), BIT(data, 4) ? "flag" : "mark");
	if ((m_dmr4 & 0xa0) != (data & 0xa0))
	{
		if (BIT(data, 5))
			LOG("%s: Address recognition on %s received byte only\n", machine().describe_context(), BIT(data, 7) ? "second" : "first");
		else
			LOG("%s: 2-byte address recognition\n", machine().describe_context());
	}
	if (BIT(m_dmr4, 6) != BIT(data, 6))
		LOG("%s: FRAR bit 1 compare %sabled\n", machine().describe_context(), BIT(data, 6) ? "en" : "dis");

	m_dmr4 = data;
}


//-------------------------------------------------
//  dsr1_r - direct read from D-channel status
//  register 1
//-------------------------------------------------

u8 am79c30a_device::dsr1_r()
{
	u8 dsr1 = m_dsr1;

	// Bits 0, 1, 6, 7 cleared when read by microprocessor
	if (!machine().side_effects_disabled())
		m_dsr1 &= 0x3c;

	return dsr1;
}


//-------------------------------------------------
//  dsr2_r - direct read from D-channel status
//  register 2
//-------------------------------------------------

u8 am79c30a_device::dsr2_r()
{
	u8 dsr2 = m_dsr2;

	// Bits 0, 1, 3 cleared when read by microprocessor
	if (!machine().side_effects_disabled())
		m_dsr2 &= 0xf2;

	return dsr2;
}


//-------------------------------------------------
//  der_r - direct read from D-channel error
//  register
//-------------------------------------------------

u8 am79c30a_device::der_r()
{
	u8 der = m_der;

	// All bits cleared when read by microprocessor
	if (!machine().side_effects_disabled())
		m_der = 0;

	return der;
}


//-------------------------------------------------
//  set_efcr - indirect write to extended FIFO
//  control register
//-------------------------------------------------

void am79c30a_device::set_efcr(u8 data)
{
	if ((m_efcr & 0x78) != (data & 0x78))
	{
		if ((data & 0x78) == 0)
			LOG("%s: Analog sidetone = <inf>\n", machine().describe_context());
		else
			LOG("%s: Analog sidetone = %.1f dB\n", machine().describe_context(), (19 - ((data & 0x78) >> 3)) * 1.5);
	}
	if (BIT(m_efcr, 1) != BIT(data, 1))
		LOG("%s: Start of second received packet in FIFO interrupt %sabled\n", machine().describe_context(), BIT(data, 1) ? "en" : "dis");
	if (BIT(m_efcr, 0) != BIT(data, 0))
		LOG("%s: %s mode of FIFO operation\n", machine().describe_context(), BIT(data, 0) ? "Extended" : "Normal");
	if ((data & 0x84) != 0)
		logerror("%s: Writing %02XH to EFCR reserved bits\n", machine().describe_context(), data & 0x84);

	m_efcr = data;
}


//**************************************************************************
//  PERIPHERAL PORT (PP)
//**************************************************************************

//-------------------------------------------------
//  set_ppcr1 - indirect write to peripheral port
//  control register 1
//-------------------------------------------------

void am79c30a_device::set_ppcr1(u8 data)
{
	if (BIT(m_ppcr1, 7) != BIT(data, 7))
		LOG("%s: Monitor channel abort request %s\n", machine().describe_context(), BIT(data, 7) ? "on" : "off");
	if ((m_ppcr1 & 0x60) != (data & 0x60))
	{
		LOG("%s: Monitor channel %d %sabled\n", machine().describe_context(), (data & 0x20) >> 5, BIT(data, 6) ? "en" : "dis");
		if (!BIT(data, 6))
			m_ppsr &= 0xf0;
	}
	if (BIT(m_ppcr1, 4) != BIT(data, 4))
		LOG("%s: Monitor end-of-message request %sabled\n", machine().describe_context(), BIT(data, 4) ? "en" : "dis");
	if (BIT(m_ppcr1, 2) != BIT(data, 2))
		LOG("%s: IOM-2 activation/deactivation bit %sset\n", machine().describe_context(), BIT(data, 2) ? "" : "re");
	if ((m_ppcr1 & 0x03) != (data & 0x03))
	{
		if ((data & 0x03) == 0x00)
			LOG("%s: Peripheral port disabled\n", machine().describe_context());
		else if ((data & 0x03) == 0x01)
			LOG("%s: Serial Bus Port mode enabled\n", machine().describe_context());
		else
			LOG("%s: IOM-2 %s mode enabled\n", machine().describe_context(), BIT(data, 1) ? "slave" : "master");
	}

	m_ppcr1 = data;
}


//-------------------------------------------------
//  get_ppsr - indirect read from peripheral port
//  status register
//-------------------------------------------------

u8 am79c30a_device::get_ppsr()
{
	u8 ppsr = m_ppsr;

	// Bits 6, 3 and 2 are cleared when read by microprocessor
	if (!machine().side_effects_disabled())
		m_ppsr &= 0xb3;

	return ppsr;
}


//-------------------------------------------------
//  set_ppier - indirect write to peripheral port
//  interrupt enable register
//-------------------------------------------------

void am79c30a_device::set_ppier(u8 data)
{
	if (BIT(m_ppier, 0) != BIT(data, 0))
		LOG("%s: Monitor receive data available interrupt %sabled\n", machine().describe_context(), BIT(data, 0) ? "en" : "dis");
	if (BIT(m_ppier, 1) != BIT(data, 1))
		LOG("%s: Monitor transmit buffer available interrupt %sabled\n", machine().describe_context(), BIT(data, 1) ? "en" : "dis");
	if (BIT(m_ppier, 2) != BIT(data, 2))
		LOG("%s: Monitor EOM received interrupt %sabled\n", machine().describe_context(), BIT(data, 2) ? "en" : "dis");
	if (BIT(m_ppier, 3) != BIT(data, 3))
		LOG("%s: Monitor abort received interrupt %sabled\n", machine().describe_context(), BIT(data, 3) ? "en" : "dis");
	if (BIT(m_ppier, 4) != BIT(data, 4))
		LOG("%s: C/I channel 0 data change interrupt %sabled\n", machine().describe_context(), BIT(data, 4) ? "en" : "dis");
	if (BIT(m_ppier, 5) != BIT(data, 5))
		LOG("%s: C/I channel 1 data change interrupt %sabled\n", machine().describe_context(), BIT(data, 5) ? "en" : "dis");
	if (BIT(m_ppier, 6) != BIT(data, 6))
		LOG("%s: IOM-2 timing request interrupt %sabled\n", machine().describe_context(), BIT(data, 6) ? "en" : "dis");
	if (BIT(m_ppier, 7) != BIT(data, 7))
		LOG("%s: Peripheral port/multiframing interrupt %sabled\n", machine().describe_context(), BIT(data, 7) ? "en" : "dis");

	m_ppier = data;
}


//-------------------------------------------------
//  set_mtdr - indirect write to monitor transmit
//  data register
//-------------------------------------------------

void am79c30a_device::set_mtdr(u8 data)
{
	// Clear Monitor Channel Transmit Buffer Available bit
	if (!machine().side_effects_disabled())
		m_ppsr &= 0xfd;

	m_mtdr = data;
}


//-------------------------------------------------
//  get_mrdr - indirect read from monitor receive
//  data register
//-------------------------------------------------

u8 am79c30a_device::get_mrdr()
{
	// Clear Monitor Channel Receive Buffer Available bit
	if (!machine().side_effects_disabled())
		m_ppsr &= 0xfe;

	return m_mrdr;
}


//-------------------------------------------------
//  set_citdr0 - indirect write to C/I transmit
//  data register 0
//-------------------------------------------------

void am79c30a_device::set_citdr0(u8 data)
{
	LOG("%s: C/I Transmit Data Register 0 = %02XH\n", machine().describe_context(), data);

	m_citdr0 = data;
}


//-------------------------------------------------
//  set_citdr1 - indirect write to C/I transmit
//  data register 1
//-------------------------------------------------

void am79c30a_device::set_citdr1(u8 data)
{
	LOG("%s: C/I Transmit Data Register 1 = %02XH\n", machine().describe_context(), data);

	m_citdr1 = data;
}


//-------------------------------------------------
//  set_ppcr2 - indirect write to peripheral port
//  control register 2
//-------------------------------------------------

void am79c30a_device::set_ppcr2(u8 data)
{
	if (BIT(m_ppcr2, 0) != BIT(data, 0))
		LOG("%s: SCLK inversion %sabled\n", machine().describe_context(), BIT(data, 0) ? "en" : "dis");

	// Hardware revision code is read-only
	m_ppcr2 = (data & 0x1f) | (m_ppcr2 & 0xe0);
}


//-------------------------------------------------
//  set_ppcr3 - indirect write to peripheral port
//  control register 3
//-------------------------------------------------

void am79c30a_device::set_ppcr3(u8 data)
{
	if (BIT(m_ppcr3, 4) != BIT(data, 4))
		LOG("%s: IOM-2 slave mode bus reversal %sabled\n", machine().describe_context(), BIT(data, 4) ? "en" : "dis");
	if (BIT(m_ppcr3, 3) != BIT(data, 3))
		LOG("%s: TIC bus %sabled\n", machine().describe_context(), BIT(data, 3) ? "en" : "dis");
	if ((m_ppcr3 & 0x07) != (data & 0x07))
		LOG("%s: TIC bus address = %d\n", machine().describe_context(), data & 0x07);

	m_ppcr3 = data;
}


//**************************************************************************
//  MICROPROCESSOR INTERFACE (MPI)
//**************************************************************************

//-------------------------------------------------
//  cr_w - write to command register
//-------------------------------------------------

void am79c30a_device::cr_w(u8 data)
{
	m_cr = data;
	m_byte_seq = 0;
}


//-------------------------------------------------
//  dr_r - read from data register
//-------------------------------------------------

u8 am79c30a_device::dr_r()
{
	u8 data = 0;

	switch (m_cr)
	{
	case 0x20:
		data = m_init2;
		break;

	case 0x21:
		data = m_init;
		break;

	case 0x41: case 0x42: case 0x43:
		data = m_mcr[m_cr - 0x41];
		break;

	case 0x44:
		data = m_mcr4;
		break;

	case 0x45:
		data = (m_byte_seq & 0x03) == 0x03 ? m_mcr4 : m_mcr[m_byte_seq & 0x03];
		break;

	case 0x61:
		data = (m_x_coeff[(m_byte_seq & 0x0e) >> 1] >> (BIT(m_byte_seq, 0) ? 8 : 0)) & 0xff;
		break;

	case 0x62:
		data = (m_r_coeff[(m_byte_seq & 0x0e) >> 1] >> (BIT(m_byte_seq, 0) ? 8 : 0)) & 0xff;
		break;

	case 0x63:
		data = (m_gx_coeff >> (BIT(m_byte_seq, 0) ? 8 : 0)) & 0xff;
		break;

	case 0x64:
		data = (m_gr_coeff >> (BIT(m_byte_seq, 0) ? 8 : 0)) & 0xff;
		break;

	case 0x65:
		data = (m_ger_coeff >> (BIT(m_byte_seq, 0) ? 8 : 0)) & 0xff;
		break;

	case 0x66:
		data = (m_stgr >> (BIT(m_byte_seq, 0) ? 8 : 0)) & 0xff;
		break;

	case 0x67:
		data = m_ftgr[m_byte_seq & 1];
		break;

	case 0x68:
		data = m_atgr[m_byte_seq & 1];
		break;

	case 0x69:
		data = m_mmr1;
		break;

	case 0x6a:
		data = m_mmr2;
		break;

	case 0x6b:
		switch (m_byte_seq % 46)
		{
		case 0: case 1: case 2: case 3: case 4: case 5: case 6: case 7:
		case 8: case 9: case 10: case 11: case 12: case 13: case 14: case 15:
			data = (m_x_coeff[(m_byte_seq % 46) >> 1] >> (BIT(m_byte_seq, 0) ? 8 : 0)) & 0xff;
			break;

		case 16: case 17: case 18: case 19: case 20: case 21: case 22: case 23:
		case 24: case 25: case 26: case 27: case 28: case 29: case 30: case 31:
			data = (m_r_coeff[((m_byte_seq % 46) - 16) >> 1] >> (BIT(m_byte_seq, 0) ? 8 : 0)) & 0xff;
			break;

		case 32: case 33:
			data = (m_gx_coeff >> (BIT(m_byte_seq, 0) ? 8 : 0)) & 0xff;
			break;

		case 34: case 35:
			data = (m_gr_coeff >> (BIT(m_byte_seq, 0) ? 8 : 0)) & 0xff;
			break;

		case 36: case 37:
			data = (m_ger_coeff >> (BIT(m_byte_seq, 0) ? 8 : 0)) & 0xff;
			break;

		case 38: case 39:
			data = (m_stgr >> (BIT(m_byte_seq, 0) ? 8 : 0)) & 0xff;
			break;

		case 40: case 41:
			data = m_ftgr[m_byte_seq & 1];
			break;

		case 42: case 43:
			data = m_atgr[m_byte_seq & 1];
			break;

		case 44:
			data = m_mmr1;
			break;

		case 45:
			data = m_mmr2;
			break;
		}
		break;

	case 0x6c:
		data = m_mmr3;
		break;

	case 0x6d:
		data = m_stra;
		break;

	case 0x6e:
		data = m_strf;
		break;

	case 0x70:
		data = m_peakx;
		break;

	case 0x71:
		data = m_peakr;
		break;

	case 0x72:
		data = BIT(m_byte_seq, 0) ? m_peakr : m_peakx;
		break;

	case 0x81:
		data = m_frar[m_byte_seq % 3];
		break;

	case 0x82:
		data = m_srar[m_byte_seq % 3];
		break;

	case 0x83:
		data = (m_tar >> (BIT(m_byte_seq, 0) ? 8 : 0)) & 0xff;
		break;

	case 0x84:
		data = (m_drlr >> (BIT(m_byte_seq, 0) ? 8 : 0)) & 0xff;
		break;

	case 0x85:
		data = (m_dtcr >> (BIT(m_byte_seq, 0) ? 8 : 0)) & 0xff;
		break;

	case 0x86:
		data = m_dmr1;
		break;

	case 0x87:
		data = m_dmr2;
		break;

	case 0x88:
		switch (m_byte_seq % 14)
		{
		case 0: case 1: case 2:
			data = m_frar[m_byte_seq % 14];
			break;

		case 3: case 4: case 5:
			data = m_srar[(m_byte_seq % 14) - 3];
			break;

		case 6: case 7:
			data = (m_tar >> (BIT(m_byte_seq, 0) ? 8 : 0)) & 0xff;
			break;

		case 8: case 9:
			data = (m_drlr >> (BIT(m_byte_seq, 0) ? 8 : 0)) & 0xff;
			break;

		case 10: case 11:
			data = (m_dtcr >> (BIT(m_byte_seq, 0) ? 8 : 0)) & 0xff;
			break;

		case 12:
			data = m_dmr1;
			break;

		case 13:
			data = m_dmr2;
			break;
		}
		break;

	case 0x89:
		data = (m_drcr >> (BIT(m_byte_seq, 0) ? 8 : 0)) & 0xff;
		break;

	case 0x8a: case 0x8b:
		data = (m_rngr >> (BIT(m_cr, 0) ? 8 : 0)) & 0xff;
		break;

	case 0x8c:
		data = m_frar[3];
		break;

	case 0x8d:
		data = m_srar[3];
		break;

	case 0x8e:
		data = m_dmr3;
		break;

	case 0x8f:
		data = m_dmr4;
		break;

	case 0x90:
		switch (m_byte_seq & 0x03)
		{
		case 0:
			data = m_frar[3];
			break;

		case 1:
			data = m_srar[3];
			break;

		case 2:
			data = m_dmr3;
			break;

		case 3:
			data = m_dmr4;
			break;
		}
		break;

	case 0x91:
		data = m_asr;
		break;

	case 0x92:
		data = m_efcr;
		break;

	case 0xa1:
		data = m_lsr;
		break;

	case 0xa2:
		data = m_lpr;
		break;

	case 0xa3:
		data = m_lmr1;
		break;

	case 0xa4:
		data = m_lmr2;
		break;

	case 0xa5:
		switch (m_byte_seq % 3)
		{
		case 0:
			data = m_lpr;
			break;

		case 1:
			data = m_lmr1;
			break;

		case 2:
			data = m_lmr2;
			break;
		}
		break;

	case 0xa6:
		data = m_mf;
		break;

	case 0xa7:
		data = m_mfsb;
		break;

	case 0xc0:
		data = m_ppcr1;
		break;

	case 0xc1:
		data = get_ppsr();
		break;

	case 0xc2:
		data = m_ppier;
		break;

	case 0xc3:
		data = get_mrdr();
		break;

	case 0xc4:
		data = m_cirdr0;
		break;

	case 0xc5:
		data = m_cirdr1;
		break;

	case 0xc8:
		data = m_ppcr2;
		break;

	case 0xc9:
		data = m_ppcr3;
		break;

	default:
		if (!machine().side_effects_disabled())
			logerror("%s: Indirect read from unimplemented/write-only register %02XH\n", machine().describe_context(), m_cr);
		break;
	}

	if (!machine().side_effects_disabled())
		m_byte_seq++;
	return data;
}


//-------------------------------------------------
//  dr_w - write to data register
//-------------------------------------------------

void am79c30a_device::dr_w(u8 data)
{
	switch (m_cr)
	{
	case 0x20:
		set_init2(data);
		break;

	case 0x21:
		set_init(data);
		break;

	case 0x41: case 0x42: case 0x43:
		set_mcr(m_cr - 0x41, data);
		break;

	case 0x44:
		set_mcr4(data);
		break;

	case 0x45:
		if ((m_byte_seq & 0x03) == 0x03)
			set_mcr4(data);
		else
			set_mcr(m_byte_seq & 0x03, data);
		break;

	case 0x61:
		set_x_coeff((m_byte_seq & 0x0e) >> 1, data, BIT(m_byte_seq, 0));
		break;

	case 0x62:
		set_r_coeff((m_byte_seq & 0x0e) >> 1, data, BIT(m_byte_seq, 0));
		break;

	case 0x63:
		set_gx_coeff(data, BIT(m_byte_seq, 0));
		break;

	case 0x64:
		set_gr_coeff(data, BIT(m_byte_seq, 0));
		break;

	case 0x65:
		set_ger_coeff(data, BIT(m_byte_seq, 0));
		break;

	case 0x66:
		set_stgr(data, BIT(m_byte_seq, 0));
		break;

	case 0x67:
		set_ftgr(m_byte_seq & 1, data);
		break;

	case 0x68:
		set_atgr(m_byte_seq & 1, data);
		break;

	case 0x69:
		set_mmr1(data);
		break;

	case 0x6a:
		set_mmr2(data);
		break;

	case 0x6b:
		switch (m_byte_seq % 46)
		{
		case 0: case 1: case 2: case 3: case 4: case 5: case 6: case 7:
		case 8: case 9: case 10: case 11: case 12: case 13: case 14: case 15:
			set_x_coeff((m_byte_seq % 46) >> 1, data, BIT(m_byte_seq, 0));
			break;

		case 16: case 17: case 18: case 19: case 20: case 21: case 22: case 23:
		case 24: case 25: case 26: case 27: case 28: case 29: case 30: case 31:
			set_r_coeff(((m_byte_seq % 46) - 16) >> 1, data, BIT(m_byte_seq, 0));
			break;

		case 32: case 33:
			set_gx_coeff(data, BIT(m_byte_seq, 0));
			break;

		case 34: case 35:
			set_gr_coeff(data, BIT(m_byte_seq, 0));
			break;

		case 36: case 37:
			set_ger_coeff(data, BIT(m_byte_seq, 0));
			break;

		case 38: case 39:
			set_stgr(data, BIT(m_byte_seq, 0));
			break;

		case 40: case 41:
			set_ftgr(m_byte_seq & 1, data);
			break;

		case 42: case 43:
			set_atgr(m_byte_seq & 1, data);
			break;

		case 44:
			set_mmr1(data);
			break;

		case 45:
			set_mmr2(data);
			break;
		}
		break;

	case 0x6c:
		set_mmr3(data);
		break;

	case 0x6d:
		set_stra(data);
		break;

	case 0x6e:
		set_strf(data);
		break;

	case 0x81:
		set_frar(m_byte_seq % 3, data);
		break;

	case 0x82:
		set_srar(m_byte_seq % 3, data);
		break;

	case 0x83:
		set_tar(data, BIT(m_byte_seq, 0));
		break;

	case 0x84:
		set_drlr(data, BIT(m_byte_seq, 0));
		break;

	case 0x85:
		set_dtcr(data, BIT(m_byte_seq, 0));
		break;

	case 0x86:
		set_dmr1(data);
		break;

	case 0x87:
		set_dmr2(data);
		break;

	case 0x88:
		switch (m_byte_seq % 14)
		{
		case 0: case 1: case 2:
			set_frar(m_byte_seq % 14, data);
			break;

		case 3: case 4: case 5:
			set_srar((m_byte_seq % 14) - 3, data);
			break;

		case 6: case 7:
			set_tar(data, BIT(m_byte_seq, 0));
			break;

		case 8: case 9:
			set_drlr(data, BIT(m_byte_seq, 0));
			break;

		case 10: case 11:
			set_dtcr(data, BIT(m_byte_seq, 0));
			break;

		case 12:
			set_dmr1(data);
			break;

		case 13:
			set_dmr2(data);
			break;
		}
		break;

	case 0x8a: case 0x8b:
		set_rngr(data, BIT(m_cr, 0));
		break;

	case 0x8c:
		set_frar(3, data);
		break;

	case 0x8d:
		set_srar(3, data);
		break;

	case 0x8e:
		set_dmr3(data);
		break;

	case 0x8f:
		set_dmr4(data);
		break;

	case 0x90:
		switch (m_byte_seq & 0x03)
		{
		case 0:
			set_frar(3, data);
			break;

		case 1:
			set_srar(3, data);
			break;

		case 2:
			set_dmr3(data);
			break;

		case 3:
			set_dmr4(data);
			break;
		}
		break;

	case 0x92:
		set_efcr(data);
		break;

	case 0xa2:
		set_lpr(data);
		break;

	case 0xa3:
		set_lmr1(data);
		break;

	case 0xa4:
		set_lmr2(data);
		break;

	case 0xa5:
		switch (m_byte_seq % 3)
		{
		case 0:
			set_lpr(data);
			break;

		case 1:
			set_lmr1(data);
			break;

		case 2:
			set_lmr2(data);
			break;
		}
		break;

	case 0xa6:
		set_mf(data);
		break;

	case 0xa8:
		set_mfqb(data);
		break;

	case 0xc0:
		set_ppcr1(data);
		break;

	case 0xc2:
		set_ppier(data);
		break;

	case 0xc3:
		set_mtdr(data);
		break;

	case 0xc4:
		set_citdr0(data);
		break;

	case 0xc5:
		set_citdr1(data);
		break;

	case 0xc8:
		set_ppcr2(data);
		break;

	case 0xc9:
		set_ppcr3(data);
		break;

	default:
		if (!machine().side_effects_disabled())
			logerror("%s: Indirect write of %02XH to unimplemented/read-only register %02XH\n", machine().describe_context(), data, m_cr);
		break;
	}

	if (!machine().side_effects_disabled())
		m_byte_seq++;
}


//-------------------------------------------------
//  bbrb_r - direct read from Bb-channel receive
//  buffer
//-------------------------------------------------

u8 am79c30a_device::bbrb_r()
{
	if (!machine().side_effects_disabled())
		logerror("%s: Reading from BBRB\n", machine().describe_context());

	return 0;
}


//-------------------------------------------------
//  bbtb_w - direct write to Bb-channel transmit
//  buffer
//-------------------------------------------------

void am79c30a_device::bbtb_w(u8 data)
{
	logerror("%s: Writing %02XH to BBTB\n", machine().describe_context(), data);
}


//-------------------------------------------------
//  bcrb_r - direct read from Bc-channel receive
//  buffer
//-------------------------------------------------

u8 am79c30a_device::bcrb_r()
{
	if (!machine().side_effects_disabled())
		logerror("%s: Reading from BCRB\n", machine().describe_context());

	return 0;
}


//-------------------------------------------------
//  bctb_w - direct write to Bc-channel transmit
//  buffer
//-------------------------------------------------

void am79c30a_device::bctb_w(u8 data)
{
	logerror("%s: Writing %02XH to BCTB\n", machine().describe_context(), data);
}


//-------------------------------------------------
//  read - microprocessor direct read
//-------------------------------------------------

u8 am79c30a_device::read(offs_t offset)
{
	switch (offset & 7)
	{
	case 0:
		return ir_r();

	case 1:
		return dr_r();

	case 2:
		return dsr1_r();

	case 3:
		return der_r();

	case 4:
		return dcrb_r();

	case 5:
		return bbrb_r();

	case 6:
		return bcrb_r();

	case 7:
		return dsr2_r();

	default: // can't happen despite what compilers believe
		return 0;
	}
}


//-------------------------------------------------
//  write - microprocessor direct write
//-------------------------------------------------

void am79c30a_device::write(offs_t offset, u8 data)
{
	switch (offset & 7)
	{
	case 0:
		cr_w(data);
		break;

	case 1:
		dr_w(data);
		break;

	case 4:
		dctb_w(data);
		break;

	case 5:
		bbtb_w(data);
		break;

	case 6:
		bctb_w(data);
		break;

	default:
		logerror("%s: Writing %02XH to unknown/reserved address %d\n", machine().describe_context(), data, offset & 7);
		break;
	}
}