diff options
Diffstat (limited to 'src')
148 files changed, 2036 insertions, 1203 deletions
diff --git a/src/devices/cpu/8x300/8x300dasm.cpp b/src/devices/cpu/8x300/8x300dasm.cpp index 3f03ed19cfd..be7623761f8 100644 --- a/src/devices/cpu/8x300/8x300dasm.cpp +++ b/src/devices/cpu/8x300/8x300dasm.cpp @@ -49,6 +49,7 @@ u32 n8x300_disassembler::opcode_alignment() const offs_t n8x300_disassembler::disassemble(std::ostream &stream, offs_t pc, const data_buffer &opcodes, const data_buffer ¶ms) { unsigned startpc = pc; + offs_t flags = 0; uint16_t opcode = opcodes.r16(pc); uint8_t inst = opcode >> 13; pc+=1; @@ -111,6 +112,7 @@ offs_t n8x300_disassembler::disassemble(std::ostream &stream, offs_t pc, const d util::stream_format(stream, ",%i", ROTLEN); util::stream_format(stream, ",%02XH", IMM5); } + flags = STEP_COND; break; case 0x06: stream << "XMIT "; @@ -132,5 +134,5 @@ offs_t n8x300_disassembler::disassemble(std::ostream &stream, offs_t pc, const d } - return (pc - startpc); + return (pc - startpc) | flags | SUPPORTED; } diff --git a/src/devices/cpu/adsp2100/2100dasm.cpp b/src/devices/cpu/adsp2100/2100dasm.cpp index b3efa6ac6ec..dfdc7fdca4b 100644 --- a/src/devices/cpu/adsp2100/2100dasm.cpp +++ b/src/devices/cpu/adsp2100/2100dasm.cpp @@ -278,10 +278,13 @@ offs_t adsp21xx_disassembler::disassemble(std::ostream &stream, offs_t pc, const if (op & 1) { util::stream_format(stream, "%s", "CALL "); - dasmflags = STEP_OVER; + dasmflags = STEP_OVER | STEP_COND; } else + { util::stream_format(stream, "%s", "JUMP "); + dasmflags = STEP_COND; + } temp = ((op >> 4) & 0x0fff) | ((op << 10) & 0x3000); util::stream_format(stream, "$%04X", temp); break; @@ -347,6 +350,8 @@ offs_t adsp21xx_disassembler::disassemble(std::ostream &stream, offs_t pc, const else util::stream_format(stream, "%s", "RTS"); dasmflags = STEP_OUT; + if ((op & 15) != 15) + dasmflags |= STEP_COND; } else util::stream_format(stream, "??? (%06X)", op); @@ -363,6 +368,8 @@ offs_t adsp21xx_disassembler::disassemble(std::ostream &stream, offs_t pc, const } else util::stream_format(stream, "JUMP (I%d)", 4 + ((op >> 6) & 3)); + if ((op & 15) != 15) + dasmflags |= STEP_COND; } else util::stream_format(stream, "??? (%06X)", op); @@ -441,6 +448,8 @@ offs_t adsp21xx_disassembler::disassemble(std::ostream &stream, offs_t pc, const } else util::stream_format(stream, "%sJUMP $%04X", condition[op & 15], (op >> 4) & 0x3fff); + if ((op & 15) != 15) + dasmflags |= STEP_COND; break; case 0x20: case 0x21: case 0x22: case 0x23: case 0x24: case 0x25: case 0x26: case 0x27: /* 00100xxx xxxxxxxx xxxxxxxx conditional ALU/MAC */ diff --git a/src/devices/cpu/alpha/alphad.cpp b/src/devices/cpu/alpha/alphad.cpp index 97f9dc6fb40..1608811cbd2 100644 --- a/src/devices/cpu/alpha/alphad.cpp +++ b/src/devices/cpu/alpha/alphad.cpp @@ -1225,21 +1225,21 @@ offs_t alpha_disassembler::disassemble(std::ostream &stream, offs_t pc, const da else BRANCH_R("br", Ra(instruction), Disp_B(instruction)); // BR break; - case 0x31: BRANCH_F("fbeq", Ra(instruction), Disp_B(instruction)); break; // FBEQ - case 0x32: BRANCH_F("fblt", Ra(instruction), Disp_B(instruction)); break; // FBLT - case 0x33: BRANCH_F("fble", Ra(instruction), Disp_B(instruction)); break; // FBLE - case 0x34: BRANCH_R("bsr", Ra(instruction), Disp_B(instruction)); break; // BSR - case 0x35: BRANCH_F("fbne", Ra(instruction), Disp_B(instruction)); break; // FBNE - case 0x36: BRANCH_F("fbge", Ra(instruction), Disp_B(instruction)); break; // FBGE - case 0x37: BRANCH_F("fbgt", Ra(instruction), Disp_B(instruction)); break; // FBGT - case 0x38: BRANCH_R("blbc", Ra(instruction), Disp_B(instruction)); break; // BLBC - case 0x39: BRANCH_R("beq", Ra(instruction), Disp_B(instruction)); break; // BEQ - case 0x3a: BRANCH_R("blt", Ra(instruction), Disp_B(instruction)); break; // BLT - case 0x3b: BRANCH_R("ble", Ra(instruction), Disp_B(instruction)); break; // BLE - case 0x3c: BRANCH_R("blbs", Ra(instruction), Disp_B(instruction)); break; // BLBS - case 0x3d: BRANCH_R("bne", Ra(instruction), Disp_B(instruction)); break; // BNE - case 0x3e: BRANCH_R("bge", Ra(instruction), Disp_B(instruction)); break; // BGE - case 0x3f: BRANCH_R("bgt", Ra(instruction), Disp_B(instruction)); break; // BGT + case 0x31: BRANCH_F("fbeq", Ra(instruction), Disp_B(instruction)); flags |= STEP_COND; break; // FBEQ + case 0x32: BRANCH_F("fblt", Ra(instruction), Disp_B(instruction)); flags |= STEP_COND; break; // FBLT + case 0x33: BRANCH_F("fble", Ra(instruction), Disp_B(instruction)); flags |= STEP_COND; break; // FBLE + case 0x34: BRANCH_R("bsr", Ra(instruction), Disp_B(instruction)); flags |= STEP_OVER; break; // BSR + case 0x35: BRANCH_F("fbne", Ra(instruction), Disp_B(instruction)); flags |= STEP_COND; break; // FBNE + case 0x36: BRANCH_F("fbge", Ra(instruction), Disp_B(instruction)); flags |= STEP_COND; break; // FBGE + case 0x37: BRANCH_F("fbgt", Ra(instruction), Disp_B(instruction)); flags |= STEP_COND; break; // FBGT + case 0x38: BRANCH_R("blbc", Ra(instruction), Disp_B(instruction)); flags |= STEP_COND; break; // BLBC + case 0x39: BRANCH_R("beq", Ra(instruction), Disp_B(instruction)); flags |= STEP_COND; break; // BEQ + case 0x3a: BRANCH_R("blt", Ra(instruction), Disp_B(instruction)); flags |= STEP_COND; break; // BLT + case 0x3b: BRANCH_R("ble", Ra(instruction), Disp_B(instruction)); flags |= STEP_COND; break; // BLE + case 0x3c: BRANCH_R("blbs", Ra(instruction), Disp_B(instruction)); flags |= STEP_COND; break; // BLBS + case 0x3d: BRANCH_R("bne", Ra(instruction), Disp_B(instruction)); flags |= STEP_COND; break; // BNE + case 0x3e: BRANCH_R("bge", Ra(instruction), Disp_B(instruction)); flags |= STEP_COND; break; // BGE + case 0x3f: BRANCH_R("bgt", Ra(instruction), Disp_B(instruction)); flags |= STEP_COND; break; // BGT } return bytes | flags; diff --git a/src/devices/cpu/am29000/am29dasm.cpp b/src/devices/cpu/am29000/am29dasm.cpp index 7e69544ab2c..1751b3779c8 100644 --- a/src/devices/cpu/am29000/am29dasm.cpp +++ b/src/devices/cpu/am29000/am29dasm.cpp @@ -212,17 +212,17 @@ offs_t am29000_disassembler::disassemble(std::ostream &stream, offs_t pc, const case 0x9f: util::stream_format(stream, "inv"); break; case 0xa0: util::stream_format(stream, "jmp $%04x", pc + OP_SJMP); break; case 0xa1: util::stream_format(stream, "jmp $%04x", OP_IJMP); break; - case 0xa4: case 0xa5: util::stream_format(stream, "jmpf %s", TYPE_4); break; - case 0xa8: case 0xa9: util::stream_format(stream, "call %s", TYPE_4); break; - case 0xac: case 0xad: util::stream_format(stream, "jmpt %s", TYPE_4); break; - case 0xb4: case 0xb5: util::stream_format(stream, "jmpfdec %s", TYPE_4); break; + case 0xa4: case 0xa5: util::stream_format(stream, "jmpf %s", TYPE_4); flags = STEP_COND | step_over_extra(1); break; + case 0xa8: case 0xa9: util::stream_format(stream, "call %s", TYPE_4); flags = STEP_OVER | step_over_extra(1); break; + case 0xac: case 0xad: util::stream_format(stream, "jmpt %s", TYPE_4); flags = STEP_COND | step_over_extra(1); break; + case 0xb4: case 0xb5: util::stream_format(stream, "jmpfdec %s", TYPE_4); flags = STEP_COND | step_over_extra(1); break; case 0xb6: util::stream_format(stream, "mftlb r%d, r%d", OP_RC, OP_RA); break; case 0xbe: util::stream_format(stream, "mttlb r%d, r%d", OP_RA, OP_RB); break; case 0xc0: util::stream_format(stream, "jmpi r%d", OP_RB); break; - case 0xc4: util::stream_format(stream, "jmpfi r%d, r%d", OP_RA, OP_RB); break; + case 0xc4: util::stream_format(stream, "jmpfi r%d, r%d", OP_RA, OP_RB); flags = STEP_COND | step_over_extra(1); break; case 0xc6: util::stream_format(stream, "mfsr r%d, %s", OP_RC, get_spr(OP_SA)); break; - case 0xc8: util::stream_format(stream, "calli r%d, r%d", OP_RA, OP_RB); break; - case 0xcc: util::stream_format(stream, "jmpti r%d, r%d", OP_RA, OP_RB); break; + case 0xc8: util::stream_format(stream, "calli r%d, r%d", OP_RA, OP_RB); flags = STEP_OVER | step_over_extra(1); break; + case 0xcc: util::stream_format(stream, "jmpti r%d, r%d", OP_RA, OP_RB); flags = STEP_COND | step_over_extra(1); break; case 0xce: util::stream_format(stream, "mtsr %s, r%d", get_spr(OP_SA), OP_RB); break; case 0xd7: util::stream_format(stream, "emulate %s", TYPE_5); break; case 0xde: util::stream_format(stream, "multm %s", TYPE_2); break; diff --git a/src/devices/cpu/amis2000/amis2000d.cpp b/src/devices/cpu/amis2000/amis2000d.cpp index 8db607d1b4b..a9a3e5acb70 100644 --- a/src/devices/cpu/amis2000/amis2000d.cpp +++ b/src/devices/cpu/amis2000/amis2000d.cpp @@ -33,9 +33,9 @@ const s8 amis2000_disassembler::s_bits[] = const u32 amis2000_disassembler::s_flags[] = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, - 0, 0, 0, 0, 0, 0, - 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, - 0, 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, STEP_COND, STEP_COND, 0, 0, + 0, STEP_COND, STEP_COND, 0, 0, 0, 0, 0, 0, 0, 0, 0, + STEP_COND, STEP_COND, STEP_COND, STEP_COND, STEP_COND, STEP_COND, STEP_COND, STEP_COND, STEP_COND, 0, 0, STEP_OVER, STEP_OUT, STEP_OUT, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }; diff --git a/src/devices/cpu/arm/armdasm.cpp b/src/devices/cpu/arm/armdasm.cpp index 053b2bc7c08..9034d3ac6f3 100644 --- a/src/devices/cpu/arm/armdasm.cpp +++ b/src/devices/cpu/arm/armdasm.cpp @@ -226,8 +226,13 @@ offs_t arm_disassembler::disassemble(std::ostream &stream, offs_t pc, const data break; case 0x0d: /* look for mov pc,lr */ - if (((opcode >> 12) & 0x0f) == 15 && ((opcode >> 0) & 0x0f) == 14 && (opcode & 0x02000000) == 0) - dasmflags = STEP_OUT; + if (((opcode >> 12) & 0x0f) == 15) + { + if (((opcode >> 0) & 0x0f) == 14 && (opcode & 0x02000000) == 0) + dasmflags = STEP_OUT; + if (opcode < 0xe0000000) + dasmflags |= STEP_COND; + } [[fallthrough]]; case 0x0f: WriteDataProcessingOperand(stream, opcode, true, false, pc); @@ -337,7 +342,11 @@ offs_t arm_disassembler::disassemble(std::ostream &stream, offs_t pc, const data util::stream_format( stream, "%c%c", ( opcode&0x00800000 ) ? 'I' : 'D', ( opcode&0x01000000 ) ? 'B' : 'A'); if( opcode & 0x00008000 ) + { dasmflags = STEP_OUT; + if (opcode < 0xe0000000) + dasmflags |= STEP_COND; + } } else { @@ -397,6 +406,8 @@ offs_t arm_disassembler::disassemble(std::ostream &stream, offs_t pc, const data { stream << "B"; } + if (opcode < 0xe0000000) + dasmflags |= STEP_COND; stream << pConditionCode; @@ -446,6 +457,8 @@ offs_t arm_disassembler::disassemble(std::ostream &stream, offs_t pc, const data WritePadding(stream, start_position); util::stream_format( stream, "&%X", opcode&0x00ffffff ); dasmflags = STEP_OVER; + if (opcode < 0xe0000000) + dasmflags |= STEP_COND; } else { diff --git a/src/devices/cpu/arm7/arm7dasm.cpp b/src/devices/cpu/arm7/arm7dasm.cpp index 7e59fdfaf98..3a5ec37a7f7 100644 --- a/src/devices/cpu/arm7/arm7dasm.cpp +++ b/src/devices/cpu/arm7/arm7dasm.cpp @@ -226,6 +226,8 @@ u32 arm7_disassembler::arm7_disasm( std::ostream &stream, uint32_t pc, uint32_t /* BLX(2) */ stream << "BLX"; dasmflags = STEP_OVER; + if (opcode < 0xe0000000) + dasmflags |= STEP_COND; WritePadding(stream, start_position); util::stream_format( stream, "R%d",(opcode&0xf)); } @@ -237,6 +239,8 @@ u32 arm7_disassembler::arm7_disasm( std::ostream &stream, uint32_t pc, uint32_t util::stream_format( stream, "R%d",(opcode&0xf)); if ((opcode & 0x0f) == 14) dasmflags = STEP_OUT; + if (opcode < 0xe0000000) + dasmflags |= STEP_COND; } else if ((opcode & 0x0ff000f0) == 0x01600010) // CLZ - v5 { @@ -290,11 +294,11 @@ u32 arm7_disassembler::arm7_disasm( std::ostream &stream, uint32_t pc, uint32_t /* half word data transfer */ if (((opcode & 0x60) == 0x40) && !(opcode & 0x100000)) // bit 20 = 0, bits 5&6 = 10 is ARMv5TE LDRD { - util::stream_format(stream, "LDRD%s", pConditionCode); + stream << "LDRD"; } else if (((opcode & 0x60) == 0x60) && !(opcode & 0x100000)) // bit 20 = 0, bits 5&6 = 11 is ARMv5TE STRD { - util::stream_format(stream, "STRD%s", pConditionCode); + stream << "STRD"; } else { @@ -309,9 +313,8 @@ u32 arm7_disassembler::arm7_disasm( std::ostream &stream, uint32_t pc, uint32_t util::stream_format(stream, "S%c", (opcode & 0x20) ? 'H' : 'B'); //Bit 5 = 1 for Half Word, 0 for Byte else stream << 'H'; - - stream << pConditionCode; } + stream << pConditionCode; WritePadding(stream, start_position); @@ -529,8 +532,13 @@ u32 arm7_disassembler::arm7_disasm( std::ostream &stream, uint32_t pc, uint32_t switch (op) { case 0x02: // check for SUBS PC, LR, #imm - if (((opcode >> 12) & 0x0f) == 15 && ((opcode >> 0) & 0x0f) == 14 && (opcode & 0x02100000) == 0x02100000) - dasmflags = STEP_OUT; + if (((opcode >> 12) & 0x0f) == 15) + { + if (((opcode >> 0) & 0x0f) == 14 && (opcode & 0x02100000) == 0x02100000) + dasmflags = STEP_OUT; + if (opcode < 0xe0000000) + dasmflags |= STEP_COND; + } [[fallthrough]]; case 0x04: if (is_adr) @@ -576,8 +584,13 @@ u32 arm7_disassembler::arm7_disasm( std::ostream &stream, uint32_t pc, uint32_t break; } /* look for mov pc,lr */ - if (((opcode >> 12) & 0x0f) == 15 && ((opcode >> 0) & 0x0f) == 14 && (opcode & 0x02000000) == 0) - dasmflags = STEP_OUT; + if (((opcode >> 12) & 0x0f) == 15) + { + if (((opcode >> 0) & 0x0f) == 14 && (opcode & 0x02000000) == 0) + dasmflags = STEP_OUT; + if (opcode < 0xe0000000) + dasmflags |= STEP_COND; + } [[fallthrough]]; case 0x0f: WriteDataProcessingOperand(stream, opcode, true, false); @@ -707,6 +720,8 @@ u32 arm7_disassembler::arm7_disasm( std::ostream &stream, uint32_t pc, uint32_t util::stream_format(stream, "R%d-", last); stream << "R15"; dasmflags = STEP_OUT; + if (opcode < 0xe0000000) + dasmflags |= STEP_COND; } } @@ -732,6 +747,8 @@ u32 arm7_disassembler::arm7_disasm( std::ostream &stream, uint32_t pc, uint32_t } stream << pConditionCode; + if (opcode < 0xe0000000) + dasmflags |= STEP_COND; WritePadding(stream, start_position); @@ -767,6 +784,8 @@ u32 arm7_disassembler::arm7_disasm( std::ostream &stream, uint32_t pc, uint32_t WritePadding(stream, start_position); util::stream_format( stream, "0x%X", opcode&0x00ffffff ); dasmflags = STEP_OVER; + if (opcode < 0xe0000000) + dasmflags |= STEP_COND; } else { @@ -1330,6 +1349,7 @@ u32 arm7_disassembler::thumb_disasm(std::ostream &stream, uint32_t pc, uint16_t util::stream_format( stream, "B%s", pConditionCodeTable[( opcode & THUMB_COND_TYPE ) >> THUMB_COND_TYPE_SHIFT]); WritePadding(stream, start_position); util::stream_format( stream, "0x%08X", pc + 4 + (offs << 1)); + dasmflags = STEP_COND; break; } break; diff --git a/src/devices/cpu/asap/asap.cpp b/src/devices/cpu/asap/asap.cpp index 8edc3734b08..7b0f8a690f5 100644 --- a/src/devices/cpu/asap/asap.cpp +++ b/src/devices/cpu/asap/asap.cpp @@ -615,7 +615,7 @@ void asap_device::bsp() { m_nextpc = m_ppc + ((int32_t)(m_op << 10) >> 8); - fetch_instruction(); + fetch_instruction_debug(); m_pc = m_nextpc; m_nextpc = ~0; @@ -630,7 +630,7 @@ void asap_device::bmz() { m_nextpc = m_ppc + ((int32_t)(m_op << 10) >> 8); - fetch_instruction(); + fetch_instruction_debug(); m_pc = m_nextpc; m_nextpc = ~0; @@ -645,7 +645,7 @@ void asap_device::bgt() { m_nextpc = m_ppc + ((int32_t)(m_op << 10) >> 8); - fetch_instruction(); + fetch_instruction_debug(); m_pc = m_nextpc; m_nextpc = ~0; @@ -660,7 +660,7 @@ void asap_device::ble() { m_nextpc = m_ppc + ((int32_t)(m_op << 10) >> 8); - fetch_instruction(); + fetch_instruction_debug(); m_pc = m_nextpc; m_nextpc = ~0; @@ -675,7 +675,7 @@ void asap_device::bge() { m_nextpc = m_ppc + ((int32_t)(m_op << 10) >> 8); - fetch_instruction(); + fetch_instruction_debug(); m_pc = m_nextpc; m_nextpc = ~0; @@ -690,7 +690,7 @@ void asap_device::blt() { m_nextpc = m_ppc + ((int32_t)(m_op << 10) >> 8); - fetch_instruction(); + fetch_instruction_debug(); m_pc = m_nextpc; m_nextpc = ~0; @@ -705,7 +705,7 @@ void asap_device::bhi() { m_nextpc = m_ppc + ((int32_t)(m_op << 10) >> 8); - fetch_instruction(); + fetch_instruction_debug(); m_pc = m_nextpc; m_nextpc = ~0; @@ -720,7 +720,7 @@ void asap_device::bls() { m_nextpc = m_ppc + ((int32_t)(m_op << 10) >> 8); - fetch_instruction(); + fetch_instruction_debug(); m_pc = m_nextpc; m_nextpc = ~0; @@ -735,7 +735,7 @@ void asap_device::bcc() { m_nextpc = m_ppc + ((int32_t)(m_op << 10) >> 8); - fetch_instruction(); + fetch_instruction_debug(); m_pc = m_nextpc; m_nextpc = ~0; @@ -750,7 +750,7 @@ void asap_device::bcs() { m_nextpc = m_ppc + ((int32_t)(m_op << 10) >> 8); - fetch_instruction(); + fetch_instruction_debug(); m_pc = m_nextpc; m_nextpc = ~0; @@ -765,7 +765,7 @@ void asap_device::bpl() { m_nextpc = m_ppc + ((int32_t)(m_op << 10) >> 8); - fetch_instruction(); + fetch_instruction_debug(); m_pc = m_nextpc; m_nextpc = ~0; @@ -780,7 +780,7 @@ void asap_device::bmi() { m_nextpc = m_ppc + ((int32_t)(m_op << 10) >> 8); - fetch_instruction(); + fetch_instruction_debug(); m_pc = m_nextpc; m_nextpc = ~0; @@ -795,7 +795,7 @@ void asap_device::bne() { m_nextpc = m_ppc + ((int32_t)(m_op << 10) >> 8); - fetch_instruction(); + fetch_instruction_debug(); m_pc = m_nextpc; m_nextpc = ~0; @@ -810,7 +810,7 @@ void asap_device::beq() { m_nextpc = m_ppc + ((int32_t)(m_op << 10) >> 8); - fetch_instruction(); + fetch_instruction_debug(); m_pc = m_nextpc; m_nextpc = ~0; @@ -825,7 +825,7 @@ void asap_device::bvc() { m_nextpc = m_ppc + ((int32_t)(m_op << 10) >> 8); - fetch_instruction(); + fetch_instruction_debug(); m_pc = m_nextpc; m_nextpc = ~0; @@ -840,7 +840,7 @@ void asap_device::bvs() { m_nextpc = m_ppc + ((int32_t)(m_op << 10) >> 8); - fetch_instruction(); + fetch_instruction_debug(); m_pc = m_nextpc; m_nextpc = ~0; @@ -856,7 +856,7 @@ void asap_device::bsr() DSTVAL = m_pc + 4; m_nextpc = m_ppc + ((int32_t)(m_op << 10) >> 8); - fetch_instruction(); + fetch_instruction_debug(); m_pc = m_nextpc; m_nextpc = ~0; @@ -868,7 +868,7 @@ void asap_device::bsr_0() { m_nextpc = m_ppc + ((int32_t)(m_op << 10) >> 8); - fetch_instruction(); + fetch_instruction_debug(); m_pc = m_nextpc; m_nextpc = ~0; @@ -1603,7 +1603,7 @@ void asap_device::jsr() DSTVAL = m_pc + 4; m_nextpc = SRC1VAL + (SRC2VAL << 2); - fetch_instruction(); + fetch_instruction_debug(); m_pc = m_nextpc; m_nextpc = ~0; @@ -1615,7 +1615,7 @@ void asap_device::jsr_0() { m_nextpc = SRC1VAL + (SRC2VAL << 2); - fetch_instruction(); + fetch_instruction_debug(); m_pc = m_nextpc; m_nextpc = ~0; @@ -1629,7 +1629,7 @@ void asap_device::jsr_c() m_nextpc = SRC1VAL + (SRC2VAL << 2); m_iflag = m_pflag; - fetch_instruction(); + fetch_instruction_debug(); m_pc = m_nextpc; m_nextpc = ~0; @@ -1643,7 +1643,7 @@ void asap_device::jsr_c0() m_nextpc = SRC1VAL + (SRC2VAL << 2); m_iflag = m_pflag; - fetch_instruction(); + fetch_instruction_debug(); m_pc = m_nextpc; m_nextpc = ~0; diff --git a/src/devices/cpu/asap/asapdasm.cpp b/src/devices/cpu/asap/asapdasm.cpp index 8f652b6dad4..6744ad9a754 100644 --- a/src/devices/cpu/asap/asapdasm.cpp +++ b/src/devices/cpu/asap/asapdasm.cpp @@ -57,7 +57,7 @@ offs_t asap_disassembler::disassemble(std::ostream &stream, offs_t pc, const dat switch (opcode) { case 0x00: util::stream_format(stream, "trap $00"); flags = STEP_OVER; break; - case 0x01: util::stream_format(stream, "b%s $%08x", condition[rdst & 15], pc + ((int32_t)(op << 10) >> 8)); break; + case 0x01: util::stream_format(stream, "b%s $%08x", condition[rdst & 15], pc + ((int32_t)(op << 10) >> 8)); flags = STEP_COND | step_over_extra(1); break; case 0x02: if ((op & 0x003fffff) == 3) { uint32_t nextop = opcodes.r32(pc+4); @@ -132,7 +132,7 @@ offs_t asap_disassembler::disassemble(std::ostream &stream, offs_t pc, const dat else if (rsrc2_iszero) { if (rsrc1 == 28) - flags = STEP_OUT; + flags = STEP_OUT | step_over_extra(1); util::stream_format(stream, "jmp%s %s", setcond[cond], reg[rsrc1]); } else diff --git a/src/devices/cpu/avr8/avr8dasm.cpp b/src/devices/cpu/avr8/avr8dasm.cpp index cd1ba5f4fb7..866845ceb15 100644 --- a/src/devices/cpu/avr8/avr8dasm.cpp +++ b/src/devices/cpu/avr8/avr8dasm.cpp @@ -161,6 +161,7 @@ offs_t avr8_disassembler::disassemble(std::ostream &stream, offs_t pc, const dat { case 0x0000: util::stream_format(stream, "CPSE R%d, R%d", RD5(op), RR5(op)); + flags = STEP_COND; break; case 0x0400: util::stream_format(stream, "CP R%d, R%d", RD5(op), RR5(op)); @@ -541,12 +542,14 @@ offs_t avr8_disassembler::disassemble(std::ostream &stream, offs_t pc, const dat break; case 0x0900: util::stream_format(stream, "SBIC %s, %s", register_names[ACONST5(op)], register_bit_names[ACONST5(op)][RR3(op)]); + flags = STEP_COND; break; case 0x0a00: util::stream_format(stream, "SBI %s, %s", register_names[ACONST5(op)], register_bit_names[ACONST5(op)][RR3(op)]); break; case 0x0b00: util::stream_format(stream, "SBIS %s, %s", register_names[ACONST5(op)], register_bit_names[ACONST5(op)][RR3(op)]); + flags = STEP_COND; break; case 0x0c00: case 0x0d00: @@ -603,6 +606,7 @@ offs_t avr8_disassembler::disassemble(std::ostream &stream, offs_t pc, const dat util::stream_format(stream, "BRIE %08x", (((op & 0x0200) ? (KCONST7(op) | 0xff80) : KCONST7(op)) << 1)); break; } + flags = STEP_COND; break; case 0x0400: switch(op & 0x0007) @@ -632,6 +636,7 @@ offs_t avr8_disassembler::disassemble(std::ostream &stream, offs_t pc, const dat util::stream_format(stream, "BRID %08x", (((op & 0x0200) ? (KCONST7(op) | 0xff80) : KCONST7(op)) << 1)); break; } + flags = STEP_COND; break; case 0x0800: if(op & 0x0200) @@ -644,6 +649,7 @@ offs_t avr8_disassembler::disassemble(std::ostream &stream, offs_t pc, const dat util::stream_format(stream, "SBRS R%d, %d", RD5(op), RR3(op)); else util::stream_format(stream, "SBRC R%d, %d", RD5(op), RR3(op)); + flags = STEP_COND; break; } break; diff --git a/src/devices/cpu/b5000/b5000d.cpp b/src/devices/cpu/b5000/b5000d.cpp index 3e40a00daff..ca0006a602d 100644 --- a/src/devices/cpu/b5000/b5000d.cpp +++ b/src/devices/cpu/b5000/b5000d.cpp @@ -61,13 +61,13 @@ const u8 b5000_common_disassembler::s_bits[] = const u32 b5000_common_disassembler::s_flags[] = { 0, - 0, 0, 0, 0, 0, - 0, 0, 0, 0, 0, - 0, 0, 0, 0, 0, + 0, 0, 0, STEP_COND, STEP_COND, + 0, STEP_COND, 0, 0, 0, + 0, 0, STEP_COND, STEP_COND, 0, 0, 0, 0, 0, 0, 0, - 0, 0, 0, + 0, 0, STEP_COND, 0, STEP_OVER, 0, STEP_OUT, - 0, 0, 0, 0, 0, 0 + STEP_COND, STEP_COND, STEP_COND, 0, 0 }; @@ -93,6 +93,7 @@ offs_t b5000_common_disassembler::common_disasm(const u8 *lut_opmap, std::ostrea // disassemble it util::stream_format(stream, "%-6s", s_name[instr]); + u32 flags = s_flags[instr]; if (bits > 0) { // exceptions for opcodes with 2 params @@ -110,9 +111,9 @@ offs_t b5000_common_disassembler::common_disasm(const u8 *lut_opmap, std::ostrea { switch (param ^ 2) { - case 1: stream << "S"; break; // 0,1 + case 1: stream << "S"; flags |= STEP_COND; break; // 0,1 case 2: stream << "C"; break; // 1,0 - case 3: stream << "C,S"; break; // 1,1 + case 3: stream << "C,S"; flags |= STEP_COND; break; // 1,1 default: break; } } @@ -130,7 +131,7 @@ offs_t b5000_common_disassembler::common_disasm(const u8 *lut_opmap, std::ostrea util::stream_format(stream, "%d", param); } - return 1 | s_flags[instr] | SUPPORTED; + return 1 | flags | SUPPORTED; } diff --git a/src/devices/cpu/bcp/bcpdasm.cpp b/src/devices/cpu/bcp/bcpdasm.cpp index ddcaec55829..c7fc6fdf6f6 100644 --- a/src/devices/cpu/bcp/bcpdasm.cpp +++ b/src/devices/cpu/bcp/bcpdasm.cpp @@ -7,15 +7,8 @@ ***************************************************************************/ #include "emu.h" -#include "util/disasmintf.h" #include "bcpdasm.h" -#include "util/strformat.h" - -using osd::u32; -using util::BIT; -using offs_t = u32; - //************************************************************************** // BCP DISASSEMBLER @@ -230,12 +223,13 @@ offs_t dp8344_disassembler::disassemble(std::ostream &stream, offs_t pc, const d { // 8C00-8DFF, 0000-FFFF: LJMP Rs,p,s,nn (2 + 2 T-states) util::stream_format(stream, "%-8s", "ljmp"); + words |= STEP_COND; } else { // 8E00-8FFF, 0000-FFFF: LCALL Rs,p,s,nn (2 + 2 T-states) util::stream_format(stream, "%-8s", "lcall"); - words |= STEP_OVER; + words |= STEP_OVER | STEP_COND; } format_register(stream, inst & 0x001f); util::stream_format(stream, ",%d,%d,", (inst & 0x00e0) >> 5, BIT(inst, 8)); @@ -304,7 +298,10 @@ offs_t dp8344_disassembler::disassemble(std::ostream &stream, offs_t pc, const d // AF00-A7FF: RETF f,s{,{g}{,rf}} (2 or 3 T-states) // AF80-AFF0: RET {g{,rf}} (2 T-states) if (!BIT(inst, 7)) + { util::stream_format(stream, (inst & 0x0070) == 0 ? "r%s" : "r%-7s", cc_to_string(inst & 0x0007, BIT(inst, 3))); + words |= STEP_COND; + } else util::stream_format(stream, (inst & 0x0070) == 0 ? "%s" : "%-8s", "ret"); @@ -455,6 +452,7 @@ offs_t dp8344_disassembler::disassemble(std::ostream &stream, offs_t pc, const d // D000-DFFF: JMP f,s,n (2 or 3 T-states) util::stream_format(stream, "j%-7s", cc_to_string((inst & 0x0700) >> 8, BIT(inst, 11))); format_address(stream, pc + 1 + s8(inst & 0x00ff)); + words |= STEP_COND; break; case 0xe000: case 0xf000: diff --git a/src/devices/cpu/capricorn/capricorn_dasm.cpp b/src/devices/cpu/capricorn/capricorn_dasm.cpp index 1b1794a954f..70adb657b17 100644 --- a/src/devices/cpu/capricorn/capricorn_dasm.cpp +++ b/src/devices/cpu/capricorn/capricorn_dasm.cpp @@ -154,21 +154,21 @@ const capricorn_disassembler::dis_entry_t capricorn_disassembler::dis_table[] = { 0xfc, 0xe8, "PO" , true , 'I' , &capricorn_disassembler::param_dr_id_ar, 0 }, { 0xfc, 0xec, "PU" , true , 'I' , &capricorn_disassembler::param_dr_id_ar, 0 }, { 0xff, 0xf0, "JMP" , false, '\0', &capricorn_disassembler::param_jmp_off, 0 }, - { 0xff, 0xf1, "JNO" , false, '\0', &capricorn_disassembler::param_jmp_off, 0 }, - { 0xff, 0xf2, "JOD" , false, '\0', &capricorn_disassembler::param_jmp_off, 0 }, - { 0xff, 0xf3, "JEV" , false, '\0', &capricorn_disassembler::param_jmp_off, 0 }, - { 0xff, 0xf4, "JNG" , false, '\0', &capricorn_disassembler::param_jmp_off, 0 }, - { 0xff, 0xf5, "JPS" , false, '\0', &capricorn_disassembler::param_jmp_off, 0 }, - { 0xff, 0xf6, "JNZ" , false, '\0', &capricorn_disassembler::param_jmp_off, 0 }, - { 0xff, 0xf7, "JZR" , false, '\0', &capricorn_disassembler::param_jmp_off, 0 }, - { 0xff, 0xf8, "JEN" , false, '\0', &capricorn_disassembler::param_jmp_off, 0 }, - { 0xff, 0xf9, "JEZ" , false, '\0', &capricorn_disassembler::param_jmp_off, 0 }, - { 0xff, 0xfa, "JNC" , false, '\0', &capricorn_disassembler::param_jmp_off, 0 }, - { 0xff, 0xfb, "JCY" , false, '\0', &capricorn_disassembler::param_jmp_off, 0 }, - { 0xff, 0xfc, "JLZ" , false, '\0', &capricorn_disassembler::param_jmp_off, 0 }, - { 0xff, 0xfd, "JLN" , false, '\0', &capricorn_disassembler::param_jmp_off, 0 }, - { 0xff, 0xfe, "JRZ" , false, '\0', &capricorn_disassembler::param_jmp_off, 0 }, - { 0xff, 0xff, "JRN" , false, '\0', &capricorn_disassembler::param_jmp_off, 0 }, + { 0xff, 0xf1, "JNO" , false, '\0', &capricorn_disassembler::param_jmp_off, STEP_COND }, + { 0xff, 0xf2, "JOD" , false, '\0', &capricorn_disassembler::param_jmp_off, STEP_COND }, + { 0xff, 0xf3, "JEV" , false, '\0', &capricorn_disassembler::param_jmp_off, STEP_COND }, + { 0xff, 0xf4, "JNG" , false, '\0', &capricorn_disassembler::param_jmp_off, STEP_COND }, + { 0xff, 0xf5, "JPS" , false, '\0', &capricorn_disassembler::param_jmp_off, STEP_COND }, + { 0xff, 0xf6, "JNZ" , false, '\0', &capricorn_disassembler::param_jmp_off, STEP_COND }, + { 0xff, 0xf7, "JZR" , false, '\0', &capricorn_disassembler::param_jmp_off, STEP_COND }, + { 0xff, 0xf8, "JEN" , false, '\0', &capricorn_disassembler::param_jmp_off, STEP_COND }, + { 0xff, 0xf9, "JEZ" , false, '\0', &capricorn_disassembler::param_jmp_off, STEP_COND }, + { 0xff, 0xfa, "JNC" , false, '\0', &capricorn_disassembler::param_jmp_off, STEP_COND }, + { 0xff, 0xfb, "JCY" , false, '\0', &capricorn_disassembler::param_jmp_off, STEP_COND }, + { 0xff, 0xfc, "JLZ" , false, '\0', &capricorn_disassembler::param_jmp_off, STEP_COND }, + { 0xff, 0xfd, "JLN" , false, '\0', &capricorn_disassembler::param_jmp_off, STEP_COND }, + { 0xff, 0xfe, "JRZ" , false, '\0', &capricorn_disassembler::param_jmp_off, STEP_COND }, + { 0xff, 0xff, "JRN" , false, '\0', &capricorn_disassembler::param_jmp_off, STEP_COND }, // *** END *** {0, 0, nullptr, false, 0, nullptr, 0 } }; diff --git a/src/devices/cpu/ccpu/ccpudasm.cpp b/src/devices/cpu/ccpu/ccpudasm.cpp index feb4ebcb58d..2d9f968f684 100644 --- a/src/devices/cpu/ccpu/ccpudasm.cpp +++ b/src/devices/cpu/ccpu/ccpudasm.cpp @@ -23,6 +23,7 @@ offs_t ccpu_disassembler::disassemble(std::ostream &stream, offs_t pc, const dat unsigned startpc = pc; uint8_t opcode = opcodes.r8(pc++); uint8_t tempval; + offs_t flags = 0; switch (opcode) { @@ -85,31 +86,37 @@ offs_t ccpu_disassembler::disassemble(std::ostream &stream, offs_t pc, const dat /* JMIB/JEHB */ case 0x51: util::stream_format(stream, "JMIB/JEHB"); + flags = STEP_COND; break; /* JVNB */ case 0x52: util::stream_format(stream, "JVNB"); + flags = STEP_COND; break; /* JLTB */ case 0x53: util::stream_format(stream, "JLTB"); + flags = STEP_COND; break; /* JEQB */ case 0x54: util::stream_format(stream, "JEQB"); + flags = STEP_COND; break; /* JCZB */ case 0x55: util::stream_format(stream, "JCZB"); + flags = STEP_COND; break; /* JOSB */ case 0x56: util::stream_format(stream, "JOSB"); + flags = STEP_COND; break; /* SSA */ @@ -125,31 +132,37 @@ offs_t ccpu_disassembler::disassemble(std::ostream &stream, offs_t pc, const dat /* JMI/JEH */ case 0x59: util::stream_format(stream, "JMI/JEH"); + flags = STEP_COND; break; /* JVN */ case 0x5a: util::stream_format(stream, "JVN"); + flags = STEP_COND; break; /* JLT */ case 0x5b: util::stream_format(stream, "JLT"); + flags = STEP_COND; break; /* JEQ */ case 0x5c: util::stream_format(stream, "JEQ"); + flags = STEP_COND; break; /* JCZ */ case 0x5d: util::stream_format(stream, "JCZ"); + flags = STEP_COND; break; /* JOS */ case 0x5e: util::stream_format(stream, "JOS"); + flags = STEP_COND; break; /* NOP */ diff --git a/src/devices/cpu/clipper/clipperd.cpp b/src/devices/cpu/clipper/clipperd.cpp index 5af39805227..40c25b3da7a 100644 --- a/src/devices/cpu/clipper/clipperd.cpp +++ b/src/devices/cpu/clipper/clipperd.cpp @@ -150,22 +150,22 @@ offs_t clipper_disassembler::disassemble(std::ostream &stream, offs_t pc, const case 0x46: util::stream_format(stream, "loadd2 (r%d),f%d", R1, R2); bytes = 2; break; case 0x47: util::stream_format(stream, "loadd2 %s,f%d", address(pc, opcodes), ADDR_R2); bytes = 2 + ADDR_SIZE; break; #endif - case 0x48: util::stream_format(stream, "b%-4s (r%d)", cc[R2], R1); bytes = 2; break; - case 0x49: util::stream_format(stream, "b%-4s %s", cc[ADDR_R2], address(pc, opcodes)); bytes = 2 + ADDR_SIZE; break; + case 0x48: util::stream_format(stream, "b%-4s (r%d)", cc[R2], R1); bytes = 2; if (R2 != 0) flags |= STEP_COND; break; + case 0x49: util::stream_format(stream, "b%-4s %s", cc[ADDR_R2], address(pc, opcodes)); bytes = 2 + ADDR_SIZE; if (ADDR_R2 != 0) flags |= STEP_COND; break; #if C400_INSTRUCTIONS // delayed branches - case 0x4a: util::stream_format(stream, "cdb r%d,(r%d)", R2, R1); bytes = 2; break; - case 0x4b: util::stream_format(stream, "cdb r%d,%s", ADDR_R2, address(pc, opcodes)); bytes = 2 + ADDR_SIZE; break; - case 0x4c: util::stream_format(stream, "cdbeq r%d,(r%d)", R2, R1); bytes = 2; break; - case 0x4d: util::stream_format(stream, "cdbeq r%d,%s", ADDR_R2, address(pc, opcodes)); bytes = 2 + ADDR_SIZE; break; - case 0x4e: util::stream_format(stream, "cdbne r%d,(r%d)", R2, R1); bytes = 2; break; - case 0x4f: util::stream_format(stream, "cdbne r%d,%s", ADDR_R2, address(pc, opcodes)); bytes = 2 + ADDR_SIZE; break; - case 0x50: util::stream_format(stream, "db%-4s (r%d)", cc[R2], R1); bytes = 2; break; - case 0x51: util::stream_format(stream, "db%-4s %s", cc[ADDR_R2], address(pc, opcodes)); bytes = 2 + ADDR_SIZE; break; + case 0x4a: util::stream_format(stream, "cdb r%d,(r%d)", R2, R1); bytes = 2; flags |= STEP_COND | step_over_extra(1); break; + case 0x4b: util::stream_format(stream, "cdb r%d,%s", ADDR_R2, address(pc, opcodes)); bytes = 2 + ADDR_SIZE; flags |= STEP_COND | step_over_extra(1); break; + case 0x4c: util::stream_format(stream, "cdbeq r%d,(r%d)", R2, R1); bytes = 2; flags |= STEP_COND | step_over_extra(1); break; + case 0x4d: util::stream_format(stream, "cdbeq r%d,%s", ADDR_R2, address(pc, opcodes)); bytes = 2 + ADDR_SIZE; flags |= STEP_COND | step_over_extra(1); break; + case 0x4e: util::stream_format(stream, "cdbne r%d,(r%d)", R2, R1); bytes = 2; flags |= STEP_COND | step_over_extra(1); break; + case 0x4f: util::stream_format(stream, "cdbne r%d,%s", ADDR_R2, address(pc, opcodes)); bytes = 2 + ADDR_SIZE; flags |= STEP_COND | step_over_extra(1); break; + case 0x50: util::stream_format(stream, "db%-4s (r%d)", cc[R2], R1); bytes = 2; if (R2 != 0) flags |= STEP_COND | step_over_extra(1); break; + case 0x51: util::stream_format(stream, "db%-4s %s", cc[ADDR_R2], address(pc, opcodes)); bytes = 2 + ADDR_SIZE; if (ADDR_R2 != 0) flags |= STEP_COND | step_over_extra(1); break; #else // these instructions are in the C300 documentation, but appear to be replaced in the C400 - case 0x4c: util::stream_format(stream, "bf%s (r%d)", R2 == 0 ? "any" : "bad", R1); bytes = 2; break; - case 0x4d: util::stream_format(stream, "bf%s %s", ADDR_R2 == 0 ? "any" : "bad", address(pc, opcodes)); bytes = 2 + ADDR_SIZE; break; + case 0x4c: util::stream_format(stream, "bf%s (r%d)", R2 == 0 ? "any" : "bad", R1); bytes = 2; flags |= STEP_COND; break; + case 0x4d: util::stream_format(stream, "bf%s %s", ADDR_R2 == 0 ? "any" : "bad", address(pc, opcodes)); bytes = 2 + ADDR_SIZE; flags |= STEP_COND; break; #endif case 0x60: util::stream_format(stream, "loadw (r%d),r%d", R1, R2); bytes = 2; break; diff --git a/src/devices/cpu/cop400/cop410ds.cpp b/src/devices/cpu/cop400/cop410ds.cpp index bbf1308077d..f0c5ed6b0f2 100644 --- a/src/devices/cpu/cop400/cop410ds.cpp +++ b/src/devices/cpu/cop400/cop410ds.cpp @@ -67,6 +67,7 @@ offs_t cop410_disassembler::disassemble(std::ostream &stream, offs_t pc, const d else if (opcode >= 0x51 && opcode <= 0x5F) { util::stream_format(stream, "AISC %u", opcode & 0xF); + flags = STEP_COND; } else if (opcode >= 0x60 && opcode <= 0x61) { @@ -95,6 +96,7 @@ offs_t cop410_disassembler::disassemble(std::ostream &stream, offs_t pc, const d case 1: util::stream_format(stream, "SKMBZ 0"); + flags = STEP_COND; break; case 2: @@ -103,10 +105,12 @@ offs_t cop410_disassembler::disassemble(std::ostream &stream, offs_t pc, const d case 3: util::stream_format(stream, "SKMBZ 2"); + flags = STEP_COND; break; case 4: util::stream_format(stream, "XIS 0"); + flags = STEP_COND; break; case 5: @@ -119,18 +123,22 @@ offs_t cop410_disassembler::disassemble(std::ostream &stream, offs_t pc, const d case 7: util::stream_format(stream, "XDS 0"); + flags = STEP_COND; break; case 0x11: util::stream_format(stream, "SKMBZ 1"); + flags = STEP_COND; break; case 0x13: util::stream_format(stream, "SKMBZ 3"); + flags = STEP_COND; break; case 0x14: util::stream_format(stream, "XIS 1"); + flags = STEP_COND; break; case 0x15: @@ -143,14 +151,17 @@ offs_t cop410_disassembler::disassemble(std::ostream &stream, offs_t pc, const d case 0x17: util::stream_format(stream, "XDS 1"); + flags = STEP_COND; break; case 0x20: util::stream_format(stream, "SKC"); + flags = STEP_COND; break; case 0x21: util::stream_format(stream, "SKE"); + flags = STEP_COND; break; case 0x22: @@ -173,6 +184,7 @@ offs_t cop410_disassembler::disassemble(std::ostream &stream, offs_t pc, const d case 0x24: util::stream_format(stream, "XIS 2"); + flags = STEP_COND; break; case 0x25: @@ -185,10 +197,12 @@ offs_t cop410_disassembler::disassemble(std::ostream &stream, offs_t pc, const d case 0x27: util::stream_format(stream, "XDS 2"); + flags = STEP_COND; break; case 0x30: util::stream_format(stream, "ASC"); + flags = STEP_COND; break; case 0x31: @@ -212,22 +226,27 @@ offs_t cop410_disassembler::disassemble(std::ostream &stream, offs_t pc, const d { case 0x01: util::stream_format(stream, "SKGBZ 0"); + flags = STEP_COND; break; case 0x03: util::stream_format(stream, "SKGBZ 2"); + flags = STEP_COND; break; case 0x11: util::stream_format(stream, "SKGBZ 1"); + flags = STEP_COND; break; case 0x13: util::stream_format(stream, "SKGBZ 3"); + flags = STEP_COND; break; case 0x21: util::stream_format(stream, "SKGZ"); + flags = STEP_COND; break; case 0x2A: @@ -264,6 +283,7 @@ offs_t cop410_disassembler::disassemble(std::ostream &stream, offs_t pc, const d case 0x34: util::stream_format(stream, "XIS 3"); + flags = STEP_COND; break; case 0x35: @@ -276,6 +296,7 @@ offs_t cop410_disassembler::disassemble(std::ostream &stream, offs_t pc, const d case 0x37: util::stream_format(stream, "XDS 3"); + flags = STEP_COND; break; case 0x40: diff --git a/src/devices/cpu/cop400/cop420ds.cpp b/src/devices/cpu/cop400/cop420ds.cpp index ec0c3581ac7..8347937ccee 100644 --- a/src/devices/cpu/cop400/cop420ds.cpp +++ b/src/devices/cpu/cop400/cop420ds.cpp @@ -67,6 +67,7 @@ offs_t cop420_disassembler::disassemble(std::ostream &stream, offs_t pc, const d else if (opcode >= 0x51 && opcode <= 0x5F) { util::stream_format(stream, "AISC %u", opcode & 0xF); + flags = STEP_COND; } else if (opcode >= 0x60 && opcode <= 0x63) { @@ -95,6 +96,7 @@ offs_t cop420_disassembler::disassemble(std::ostream &stream, offs_t pc, const d case 1: util::stream_format(stream, "SKMBZ 0"); + flags = STEP_COND; break; case 2: @@ -103,10 +105,12 @@ offs_t cop420_disassembler::disassemble(std::ostream &stream, offs_t pc, const d case 3: util::stream_format(stream, "SKMBZ 2"); + flags = STEP_COND; break; case 4: util::stream_format(stream, "XIS 0"); + flags = STEP_COND; break; case 5: @@ -119,14 +123,17 @@ offs_t cop420_disassembler::disassemble(std::ostream &stream, offs_t pc, const d case 7: util::stream_format(stream, "XDS 0"); + flags = STEP_COND; break; case 0x10: util::stream_format(stream, "CASC"); + flags = STEP_COND; break; case 0x11: util::stream_format(stream, "SKMBZ 1"); + flags = STEP_COND; break; case 0x12: @@ -135,10 +142,12 @@ offs_t cop420_disassembler::disassemble(std::ostream &stream, offs_t pc, const d case 0x13: util::stream_format(stream, "SKMBZ 3"); + flags = STEP_COND; break; case 0x14: util::stream_format(stream, "XIS 1"); + flags = STEP_COND; break; case 0x15: @@ -151,14 +160,17 @@ offs_t cop420_disassembler::disassemble(std::ostream &stream, offs_t pc, const d case 0x17: util::stream_format(stream, "XDS 1"); + flags = STEP_COND; break; case 0x20: util::stream_format(stream, "SKC"); + flags = STEP_COND; break; case 0x21: util::stream_format(stream, "SKE"); + flags = STEP_COND; break; case 0x22: @@ -186,6 +198,7 @@ offs_t cop420_disassembler::disassemble(std::ostream &stream, offs_t pc, const d case 0x24: util::stream_format(stream, "XIS 2"); + flags = STEP_COND; break; case 0x25: @@ -198,10 +211,12 @@ offs_t cop420_disassembler::disassemble(std::ostream &stream, offs_t pc, const d case 0x27: util::stream_format(stream, "XDS 2"); + flags = STEP_COND; break; case 0x30: util::stream_format(stream, "ASC"); + flags = STEP_COND; break; case 0x31: @@ -245,22 +260,27 @@ offs_t cop420_disassembler::disassemble(std::ostream &stream, offs_t pc, const d { case 0x01: util::stream_format(stream, "SKGBZ 0"); + flags = STEP_COND; break; case 0x03: util::stream_format(stream, "SKGBZ 2"); + flags = STEP_COND; break; case 0x11: util::stream_format(stream, "SKGBZ 1"); + flags = STEP_COND; break; case 0x13: util::stream_format(stream, "SKGBZ 3"); + flags = STEP_COND; break; case 0x21: util::stream_format(stream, "SKGZ"); + flags = STEP_COND; break; case 0x28: @@ -304,6 +324,7 @@ offs_t cop420_disassembler::disassemble(std::ostream &stream, offs_t pc, const d case 0x34: util::stream_format(stream, "XIS 3"); + flags = STEP_COND; break; case 0x35: @@ -316,6 +337,7 @@ offs_t cop420_disassembler::disassemble(std::ostream &stream, offs_t pc, const d case 0x37: util::stream_format(stream, "XDS 3"); + flags = STEP_COND; break; case 0x40: @@ -324,6 +346,7 @@ offs_t cop420_disassembler::disassemble(std::ostream &stream, offs_t pc, const d case 0x41: util::stream_format(stream, "SKT"); + flags = STEP_COND; break; case 0x42: diff --git a/src/devices/cpu/cop400/cop424ds.cpp b/src/devices/cpu/cop400/cop424ds.cpp index bd754dc4131..fb491d919ea 100644 --- a/src/devices/cpu/cop400/cop424ds.cpp +++ b/src/devices/cpu/cop400/cop424ds.cpp @@ -67,6 +67,7 @@ offs_t cop424_disassembler::disassemble(std::ostream &stream, offs_t pc, const d else if (opcode >= 0x51 && opcode <= 0x5F) { util::stream_format(stream, "AISC %u", opcode & 0xF); + flags = STEP_COND; } else if (opcode >= 0x60 && opcode <= 0x67) { @@ -95,6 +96,7 @@ offs_t cop424_disassembler::disassemble(std::ostream &stream, offs_t pc, const d case 1: util::stream_format(stream, "SKMBZ 0"); + flags = STEP_COND; break; case 2: @@ -103,10 +105,12 @@ offs_t cop424_disassembler::disassemble(std::ostream &stream, offs_t pc, const d case 3: util::stream_format(stream, "SKMBZ 2"); + flags = STEP_COND; break; case 4: util::stream_format(stream, "XIS 0"); + flags = STEP_COND; break; case 5: @@ -119,14 +123,17 @@ offs_t cop424_disassembler::disassemble(std::ostream &stream, offs_t pc, const d case 7: util::stream_format(stream, "XDS 0"); + flags = STEP_COND; break; case 0x10: util::stream_format(stream, "CASC"); + flags = STEP_COND; break; case 0x11: util::stream_format(stream, "SKMBZ 1"); + flags = STEP_COND; break; case 0x12: @@ -135,10 +142,12 @@ offs_t cop424_disassembler::disassemble(std::ostream &stream, offs_t pc, const d case 0x13: util::stream_format(stream, "SKMBZ 3"); + flags = STEP_COND; break; case 0x14: util::stream_format(stream, "XIS 1"); + flags = STEP_COND; break; case 0x15: @@ -151,14 +160,17 @@ offs_t cop424_disassembler::disassemble(std::ostream &stream, offs_t pc, const d case 0x17: util::stream_format(stream, "XDS 1"); + flags = STEP_COND; break; case 0x20: util::stream_format(stream, "SKC"); + flags = STEP_COND; break; case 0x21: util::stream_format(stream, "SKE"); + flags = STEP_COND; break; case 0x22: @@ -182,6 +194,7 @@ offs_t cop424_disassembler::disassemble(std::ostream &stream, offs_t pc, const d case 0x24: util::stream_format(stream, "XIS 2"); + flags = STEP_COND; break; case 0x25: @@ -194,10 +207,12 @@ offs_t cop424_disassembler::disassemble(std::ostream &stream, offs_t pc, const d case 0x27: util::stream_format(stream, "XDS 2"); + flags = STEP_COND; break; case 0x30: util::stream_format(stream, "ASC"); + flags = STEP_COND; break; case 0x31: @@ -229,22 +244,27 @@ offs_t cop424_disassembler::disassemble(std::ostream &stream, offs_t pc, const d { case 0x01: util::stream_format(stream, "SKGBZ 0"); + flags = STEP_COND; break; case 0x03: util::stream_format(stream, "SKGBZ 2"); + flags = STEP_COND; break; case 0x11: util::stream_format(stream, "SKGBZ 1"); + flags = STEP_COND; break; case 0x13: util::stream_format(stream, "SKGBZ 3"); + flags = STEP_COND; break; case 0x21: util::stream_format(stream, "SKGZ"); + flags = STEP_COND; break; case 0x28: @@ -305,6 +325,7 @@ offs_t cop424_disassembler::disassemble(std::ostream &stream, offs_t pc, const d case 0x34: util::stream_format(stream, "XIS 3"); + flags = STEP_COND; break; case 0x35: @@ -317,6 +338,7 @@ offs_t cop424_disassembler::disassemble(std::ostream &stream, offs_t pc, const d case 0x37: util::stream_format(stream, "XDS 3"); + flags = STEP_COND; break; case 0x40: @@ -325,6 +347,7 @@ offs_t cop424_disassembler::disassemble(std::ostream &stream, offs_t pc, const d case 0x41: util::stream_format(stream, "SKT"); + flags = STEP_COND; break; case 0x42: diff --git a/src/devices/cpu/cop400/cop444ds.cpp b/src/devices/cpu/cop400/cop444ds.cpp index 6c0001a30cd..b9087cdc029 100644 --- a/src/devices/cpu/cop400/cop444ds.cpp +++ b/src/devices/cpu/cop400/cop444ds.cpp @@ -67,6 +67,7 @@ offs_t cop444_disassembler::disassemble(std::ostream &stream, offs_t pc, const d else if (opcode >= 0x51 && opcode <= 0x5F) { util::stream_format(stream, "AISC %u", opcode & 0xF); + flags = STEP_COND; } else if (opcode >= 0x60 && opcode <= 0x67) { @@ -95,6 +96,7 @@ offs_t cop444_disassembler::disassemble(std::ostream &stream, offs_t pc, const d case 1: util::stream_format(stream, "SKMBZ 0"); + flags = STEP_COND; break; case 2: @@ -103,10 +105,12 @@ offs_t cop444_disassembler::disassemble(std::ostream &stream, offs_t pc, const d case 3: util::stream_format(stream, "SKMBZ 2"); + flags = STEP_COND; break; case 4: util::stream_format(stream, "XIS 0"); + flags = STEP_COND; break; case 5: @@ -119,14 +123,17 @@ offs_t cop444_disassembler::disassemble(std::ostream &stream, offs_t pc, const d case 7: util::stream_format(stream, "XDS 0"); + flags = STEP_COND; break; case 0x10: util::stream_format(stream, "CASC"); + flags = STEP_COND; break; case 0x11: util::stream_format(stream, "SKMBZ 1"); + flags = STEP_COND; break; case 0x12: @@ -135,10 +142,12 @@ offs_t cop444_disassembler::disassemble(std::ostream &stream, offs_t pc, const d case 0x13: util::stream_format(stream, "SKMBZ 3"); + flags = STEP_COND; break; case 0x14: util::stream_format(stream, "XIS 1"); + flags = STEP_COND; break; case 0x15: @@ -151,14 +160,17 @@ offs_t cop444_disassembler::disassemble(std::ostream &stream, offs_t pc, const d case 0x17: util::stream_format(stream, "XDS 1"); + flags = STEP_COND; break; case 0x20: util::stream_format(stream, "SKC"); + flags = STEP_COND; break; case 0x21: util::stream_format(stream, "SKE"); + flags = STEP_COND; break; case 0x22: @@ -182,6 +194,7 @@ offs_t cop444_disassembler::disassemble(std::ostream &stream, offs_t pc, const d case 0x24: util::stream_format(stream, "XIS 2"); + flags = STEP_COND; break; case 0x25: @@ -194,10 +207,12 @@ offs_t cop444_disassembler::disassemble(std::ostream &stream, offs_t pc, const d case 0x27: util::stream_format(stream, "XDS 2"); + flags = STEP_COND; break; case 0x30: util::stream_format(stream, "ASC"); + flags = STEP_COND; break; case 0x31: @@ -229,22 +244,27 @@ offs_t cop444_disassembler::disassemble(std::ostream &stream, offs_t pc, const d { case 0x01: util::stream_format(stream, "SKGBZ 0"); + flags = STEP_COND; break; case 0x03: util::stream_format(stream, "SKGBZ 2"); + flags = STEP_COND; break; case 0x11: util::stream_format(stream, "SKGBZ 1"); + flags = STEP_COND; break; case 0x13: util::stream_format(stream, "SKGBZ 3"); + flags = STEP_COND; break; case 0x21: util::stream_format(stream, "SKGZ"); + flags = STEP_COND; break; case 0x28: @@ -288,6 +308,7 @@ offs_t cop444_disassembler::disassemble(std::ostream &stream, offs_t pc, const d case 0x34: util::stream_format(stream, "XIS 3"); + flags = STEP_COND; break; case 0x35: @@ -300,6 +321,7 @@ offs_t cop444_disassembler::disassemble(std::ostream &stream, offs_t pc, const d case 0x37: util::stream_format(stream, "XDS 3"); + flags = STEP_COND; break; case 0x40: @@ -308,6 +330,7 @@ offs_t cop444_disassembler::disassemble(std::ostream &stream, offs_t pc, const d case 0x41: util::stream_format(stream, "SKT"); + flags = STEP_COND; break; case 0x42: diff --git a/src/devices/cpu/cops1/cops1d.cpp b/src/devices/cpu/cops1/cops1d.cpp index c6d9b96df41..d78a1e050d1 100644 --- a/src/devices/cpu/cops1/cops1d.cpp +++ b/src/devices/cpu/cops1/cops1d.cpp @@ -60,11 +60,11 @@ const u8 cops1_common_disassembler::s_bits[] = const u32 cops1_common_disassembler::s_flags[] = { 0, - 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, - 0, 0, 0, 0, + 0, STEP_COND, STEP_COND, 0, 0, STEP_COND, 0, STEP_COND, 0, 0, STEP_COND, + STEP_COND, STEP_COND, STEP_COND, STEP_COND, 0, 0, 0, 0, 0, 0, 0, STEP_OVER, STEP_OUT, STEP_OUT, 0, STEP_OVER, 0, - 0, 0, 0, 0, 0, + 0, STEP_COND, STEP_COND, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }; diff --git a/src/devices/cpu/cosmac/cosdasm.cpp b/src/devices/cpu/cosmac/cosdasm.cpp index b54bd167386..d491651da50 100644 --- a/src/devices/cpu/cosmac/cosdasm.cpp +++ b/src/devices/cpu/cosmac/cosdasm.cpp @@ -150,19 +150,19 @@ offs_t cosmac_disassembler::disassemble(std::ostream &stream, offs_t pc, const d case 0x28: case 0x29: case 0x2a: case 0x2b: case 0x2c: case 0x2d: case 0x2e: case 0x2f: CDP1801_OPCODE("DEC R%d", implied(opcode)); break; case 0x30: CDP1801_OPCODE("BR %04X", short_branch(base_pc, pc, params)); break; - case 0x32: CDP1801_OPCODE("BZ %04X", short_branch(base_pc, pc, params)); break; - case 0x33: CDP1801_OPCODE("BDF %04X", short_branch(base_pc, pc, params)); break; - case 0x34: CDP1801_OPCODE("B1 %04X", short_branch(base_pc, pc, params)); break; - case 0x35: CDP1801_OPCODE("B2 %04X", short_branch(base_pc, pc, params)); break; - case 0x36: CDP1801_OPCODE("B3 %04X", short_branch(base_pc, pc, params)); break; - case 0x37: CDP1801_OPCODE("B4 %04X", short_branch(base_pc, pc, params)); break; + case 0x32: CDP1801_OPCODE("BZ %04X", short_branch(base_pc, pc, params)); flags = STEP_COND; break; + case 0x33: CDP1801_OPCODE("BDF %04X", short_branch(base_pc, pc, params)); flags = STEP_COND; break; + case 0x34: CDP1801_OPCODE("B1 %04X", short_branch(base_pc, pc, params)); flags = STEP_COND; break; + case 0x35: CDP1801_OPCODE("B2 %04X", short_branch(base_pc, pc, params)); flags = STEP_COND; break; + case 0x36: CDP1801_OPCODE("B3 %04X", short_branch(base_pc, pc, params)); flags = STEP_COND; break; + case 0x37: CDP1801_OPCODE("B4 %04X", short_branch(base_pc, pc, params)); flags = STEP_COND; break; case 0x38: CDP1801_OPCODE("SKP %04X", short_skip(pc)); break; - case 0x3a: CDP1801_OPCODE("BNZ %04X", short_branch(base_pc, pc, params)); break; - case 0x3b: CDP1801_OPCODE("BNF %04X", short_branch(base_pc, pc, params)); break; - case 0x3c: CDP1801_OPCODE("BN1 %04X", short_branch(base_pc, pc, params)); break; - case 0x3d: CDP1801_OPCODE("BN2 %04X", short_branch(base_pc, pc, params)); break; - case 0x3e: CDP1801_OPCODE("BN3 %04X", short_branch(base_pc, pc, params)); break; - case 0x3f: CDP1801_OPCODE("BN4 %04X", short_branch(base_pc, pc, params)); break; + case 0x3a: CDP1801_OPCODE("BNZ %04X", short_branch(base_pc, pc, params)); flags = STEP_COND; break; + case 0x3b: CDP1801_OPCODE("BNF %04X", short_branch(base_pc, pc, params)); flags = STEP_COND; break; + case 0x3c: CDP1801_OPCODE("BN1 %04X", short_branch(base_pc, pc, params)); flags = STEP_COND; break; + case 0x3d: CDP1801_OPCODE("BN2 %04X", short_branch(base_pc, pc, params)); flags = STEP_COND; break; + case 0x3e: CDP1801_OPCODE("BN3 %04X", short_branch(base_pc, pc, params)); flags = STEP_COND; break; + case 0x3f: CDP1801_OPCODE("BN4 %04X", short_branch(base_pc, pc, params)); flags = STEP_COND; break; case 0x40: case 0x41: case 0x42: case 0x43: case 0x44: case 0x45: case 0x46: case 0x47: case 0x48: case 0x49: case 0x4a: case 0x4b: case 0x4c: case 0x4d: case 0x4e: case 0x4f: CDP1801_OPCODE("LDA R%d", implied(opcode)); break; @@ -213,8 +213,8 @@ offs_t cosmac_disassembler::disassemble(std::ostream &stream, offs_t pc, const d case 0xfd: CDP1801_OPCODE("SDI #%02X", immediate(pc, params)); break; case 0xff: CDP1801_OPCODE("SMI #%02X", immediate(pc, params)); break; // CDP1802 - case 0x31: CDP1802_OPCODE("BQ %04X", short_branch(base_pc, pc, params)); break; - case 0x39: CDP1802_OPCODE("BNQ %04X", short_branch(base_pc, pc, params)); break; + case 0x31: CDP1802_OPCODE("BQ %04X", short_branch(base_pc, pc, params)); flags = STEP_COND; break; + case 0x39: CDP1802_OPCODE("BNQ %04X", short_branch(base_pc, pc, params)); flags = STEP_COND; break; case 0x60: util::stream_format(stream, m_variant < TYPE_1802 ? "OUT 0" : "IRX"); if (m_config && m_config->get_p() == m_config->get_x()) @@ -235,21 +235,21 @@ offs_t cosmac_disassembler::disassemble(std::ostream &stream, offs_t pc, const d case 0x7e: CDP1802_OPCODE("SHLC"); break; case 0x7f: CDP1802_OPCODE("SMBI #%02X", immediate(pc, params)); break; case 0xc0: CDP1802_OPCODE("LBR %04X", long_branch(pc, params)); break; - case 0xc1: CDP1802_OPCODE("LBQ %04X", long_branch(pc, params)); break; - case 0xc2: CDP1802_OPCODE("LBZ %04X", long_branch(pc, params)); break; - case 0xc3: CDP1802_OPCODE("LBDF %04X", long_branch(pc, params)); break; + case 0xc1: CDP1802_OPCODE("LBQ %04X", long_branch(pc, params)); flags = STEP_COND; break; + case 0xc2: CDP1802_OPCODE("LBZ %04X", long_branch(pc, params)); flags = STEP_COND; break; + case 0xc3: CDP1802_OPCODE("LBDF %04X", long_branch(pc, params)); flags = STEP_COND; break; case 0xc4: CDP1802_OPCODE("NOP"); break; - case 0xc5: CDP1802_OPCODE("LSNQ %04X", long_skip(pc)); break; - case 0xc6: CDP1802_OPCODE("LSNZ %04X", long_skip(pc)); break; - case 0xc7: CDP1802_OPCODE("LSNF %04X", long_skip(pc)); break; + case 0xc5: CDP1802_OPCODE("LSNQ %04X", long_skip(pc)); flags = STEP_COND; break; + case 0xc6: CDP1802_OPCODE("LSNZ %04X", long_skip(pc)); flags = STEP_COND; break; + case 0xc7: CDP1802_OPCODE("LSNF %04X", long_skip(pc)); flags = STEP_COND; break; case 0xc8: CDP1802_OPCODE("LSKP %04X", long_skip(pc)); break; - case 0xc9: CDP1802_OPCODE("LBNQ %04X", long_skip(pc)); break; - case 0xca: CDP1802_OPCODE("LBNZ %04X", long_skip(pc)); break; - case 0xcb: CDP1802_OPCODE("LBNF %04X", long_skip(pc)); break; - case 0xcc: CDP1802_OPCODE("LSIE %04X", long_skip(pc)); break; - case 0xcd: CDP1802_OPCODE("LSQ %04X", long_skip(pc)); break; - case 0xce: CDP1802_OPCODE("LSZ %04X", long_skip(pc)); break; - case 0xcf: CDP1802_OPCODE("LSDF %04X", long_skip(pc)); break; + case 0xc9: CDP1802_OPCODE("LBNQ %04X", long_skip(pc)); flags = STEP_COND; break; + case 0xca: CDP1802_OPCODE("LBNZ %04X", long_skip(pc)); flags = STEP_COND; break; + case 0xcb: CDP1802_OPCODE("LBNF %04X", long_skip(pc)); flags = STEP_COND; break; + case 0xcc: CDP1802_OPCODE("LSIE %04X", long_skip(pc)); flags = STEP_COND; break; + case 0xcd: CDP1802_OPCODE("LSQ %04X", long_skip(pc)); flags = STEP_COND; break; + case 0xce: CDP1802_OPCODE("LSZ %04X", long_skip(pc)); flags = STEP_COND; break; + case 0xcf: CDP1802_OPCODE("LSDF %04X", long_skip(pc)); flags = STEP_COND; break; case 0xfe: CDP1802_OPCODE("SHL"); break; // default: CDP1801_OPCODE("illegal"); break; diff --git a/src/devices/cpu/cp1610/1610dasm.cpp b/src/devices/cpu/cp1610/1610dasm.cpp index 9b9c169bfa7..5cd9c05e102 100644 --- a/src/devices/cpu/cp1610/1610dasm.cpp +++ b/src/devices/cpu/cp1610/1610dasm.cpp @@ -778,36 +778,43 @@ offs_t cp1610_disassembler::disassemble(std::ostream &stream, offs_t pc, const d size += 1; ea = oprom16[1]; util::stream_format(stream, "BC %04X",pc+2+ea); + flags = STEP_COND; break; case 0x202: /* 1 000 000 010 */ size += 1; ea = oprom16[1]; util::stream_format(stream, "BOV %04X",pc+2+ea); + flags = STEP_COND; break; case 0x203: /* 1 000 000 011 */ size += 1; ea = oprom16[1]; util::stream_format(stream, "BPL %04X",pc+2+ea); + flags = STEP_COND; break; case 0x204: /* 1 000 000 100 */ size += 1; ea = oprom16[1]; util::stream_format(stream, "BZE %04X",pc+2+ea); + flags = STEP_COND; break; case 0x205: /* 1 000 000 101 */ size += 1; ea = oprom16[1]; util::stream_format(stream, "BLT %04X",pc+2+ea); + flags = STEP_COND; break; case 0x206: /* 1 000 000 110 */ size += 1; ea = oprom16[1]; util::stream_format(stream, "BLE %04X",pc+2+ea); + flags = STEP_COND; break; case 0x207: /* 1 000 000 111 */ size += 1; ea = oprom16[1]; util::stream_format(stream, "BUSC %04X",pc+2+ea); + flags = STEP_COND; break; case 0x208: /* 1 000 001 000 */ size += 1; @@ -818,36 +825,43 @@ offs_t cp1610_disassembler::disassemble(std::ostream &stream, offs_t pc, const d size += 1; ea = oprom16[1]; util::stream_format(stream, "BNC %04X",pc+2+ea); + flags = STEP_COND; break; case 0x20a: /* 1 000 001 010 */ size += 1; ea = oprom16[1]; util::stream_format(stream, "BNOV %04X",pc+2+ea); + flags = STEP_COND; break; case 0x20b: /* 1 000 001 011 */ size += 1; ea = oprom16[1]; util::stream_format(stream, "BMI %04X",pc+2+ea); + flags = STEP_COND; break; case 0x20c: /* 1 000 001 100 */ size += 1; ea = oprom16[1]; util::stream_format(stream, "BNZE %04X",pc+2+ea); + flags = STEP_COND; break; case 0x20d: /* 1 000 001 101 */ size += 1; ea = oprom16[1]; util::stream_format(stream, "BGE %04X",pc+2+ea); + flags = STEP_COND; break; case 0x20e: /* 1 000 001 110 */ size += 1; ea = oprom16[1]; util::stream_format(stream, "BGT %04X",pc+2+ea); + flags = STEP_COND; break; case 0x20f: /* 1 000 001 111 */ size += 1; ea = oprom16[1]; util::stream_format(stream, "BESC %04X",pc+2+ea); + flags = STEP_COND; break; case 0x210: /* 1 000 010 000 */ case 0x211: /* 1 000 010 001 */ @@ -868,6 +882,7 @@ offs_t cp1610_disassembler::disassemble(std::ostream &stream, offs_t pc, const d size += 1; ea = oprom16[1]; util::stream_format(stream, "BEXT %04X,%01X",pc+2+ea,op&0x0f); + flags = STEP_COND; break; case 0x220: /* 1 000 100 000 */ size += 1; @@ -878,36 +893,43 @@ offs_t cp1610_disassembler::disassemble(std::ostream &stream, offs_t pc, const d size += 1; ea = oprom16[1]; util::stream_format(stream, "BC %04X",pc+1-ea); + flags = STEP_COND; break; case 0x222: /* 1 000 100 010 */ size += 1; ea = oprom16[1]; util::stream_format(stream, "BOV %04X",pc+1-ea); + flags = STEP_COND; break; case 0x223: /* 1 000 100 011 */ size += 1; ea = oprom16[1]; util::stream_format(stream, "BPL %04X",pc+1-ea); + flags = STEP_COND; break; case 0x224: /* 1 000 100 100 */ size += 1; ea = oprom16[1]; util::stream_format(stream, "BZE %04X",pc+1-ea); + flags = STEP_COND; break; case 0x225: /* 1 000 100 101 */ size += 1; ea = oprom16[1]; util::stream_format(stream, "BLT %04X",pc+1-ea); + flags = STEP_COND; break; case 0x226: /* 1 000 100 110 */ size += 1; ea = oprom16[1]; util::stream_format(stream, "BLE %04X",pc+1-ea); + flags = STEP_COND; break; case 0x227: /* 1 000 100 111 */ size += 1; ea = oprom16[1]; util::stream_format(stream, "BUSC %04X",pc+1-ea); + flags = STEP_COND; break; case 0x228: /* 1 000 101 000 */ size += 1; @@ -918,36 +940,43 @@ offs_t cp1610_disassembler::disassemble(std::ostream &stream, offs_t pc, const d size += 1; ea = oprom16[1]; util::stream_format(stream, "BNC %04X",pc+1-ea); + flags = STEP_COND; break; case 0x22a: /* 1 000 101 010 */ size += 1; ea = oprom16[1]; util::stream_format(stream, "BNOV %04X",pc+1-ea); + flags = STEP_COND; break; case 0x22b: /* 1 000 101 011 */ size += 1; ea = oprom16[1]; util::stream_format(stream, "BMI %04X",pc+1-ea); + flags = STEP_COND; break; case 0x22c: /* 1 000 101 100 */ size += 1; ea = oprom16[1]; util::stream_format(stream, "BNZE %04X",pc+1-ea); + flags = STEP_COND; break; case 0x22d: /* 1 000 101 101 */ size += 1; ea = oprom16[1]; util::stream_format(stream, "BGE %04X",pc+1-ea); + flags = STEP_COND; break; case 0x22e: /* 1 000 101 110 */ size += 1; ea = oprom16[1]; util::stream_format(stream, "BGT %04X",pc+1-ea); + flags = STEP_COND; break; case 0x22f: /* 1 000 101 111 */ size += 1; ea = oprom16[1]; util::stream_format(stream, "BESC %04X",pc+1-ea); + flags = STEP_COND; break; case 0x230: /* 1 000 110 000 */ case 0x231: /* 1 000 110 001 */ @@ -968,6 +997,7 @@ offs_t cp1610_disassembler::disassemble(std::ostream &stream, offs_t pc, const d size += 1; ea = oprom16[1]; util::stream_format(stream, "BEXT %04X,%01X",pc+1-ea,op&0x0f); + flags = STEP_COND; break; case 0x240: /* 1 001 000 000 */ case 0x241: /* 1 001 000 001 */ diff --git a/src/devices/cpu/cr16b/cr16bdasm.cpp b/src/devices/cpu/cr16b/cr16bdasm.cpp index a39a181b240..841f41498d6 100644 --- a/src/devices/cpu/cr16b/cr16bdasm.cpp +++ b/src/devices/cpu/cr16b/cr16bdasm.cpp @@ -564,11 +564,17 @@ offs_t cr16b_disassembler::disassemble(std::ostream &stream, offs_t pc, const cr if ((opcode & 0x000e) == 0x000e && (opcode & 0x01e0) != 0x01e0) { if ((opcode & 0x01e0) == 0x01c0) + { stream << "br "; + format_pc_disp17(stream, pc, u32(opcode & 0x0010) << 12 | opcodes.r16(pc + 2)); + return 4 | SUPPORTED; + } else + { util::stream_format(stream, "b%s ", s_cc[(opcode & 0x01e0) >> 5]); - format_pc_disp17(stream, pc, u32(opcode & 0x0010) << 12 | opcodes.r16(pc + 2)); - return 4 | SUPPORTED; + format_pc_disp17(stream, pc, u32(opcode & 0x0010) << 12 | opcodes.r16(pc + 2)); + return 4 | STEP_COND | SUPPORTED; + } } else { @@ -579,15 +585,18 @@ offs_t cr16b_disassembler::disassemble(std::ostream &stream, offs_t pc, const cr case 0x1401: case 0x3401: // Compare and branch group if (m_arch == cr16_arch::CR16A) + { stream << "res"; + return 2 | SUPPORTED; + } else { util::stream_format(stream, "b%s%c%c ", BIT(opcode, 7) ? "ne" : "eq", BIT(opcode, 6) ? '1' : '0', BIT(opcode, 13) ? 'w' : 'b'); format_reg(stream, (opcode & 0x0120) >> 5); stream << ", "; format_pc_disp5(stream, pc, opcode & 0x001e); + return 2 | STEP_COND | SUPPORTED; } - return 2 | SUPPORTED; case 0x1600: // Jump and link to large address @@ -610,7 +619,7 @@ offs_t cr16b_disassembler::disassemble(std::ostream &stream, offs_t pc, const cr else util::stream_format(stream, "j%s ", s_cc[(opcode & 0x01e0) >> 5]); format_rpair(stream, (opcode & 0x001e) >> 1); - return 2 | (opcode == 0x17db ? STEP_OUT : 0) | SUPPORTED; + return 2 | ((opcode & 0x001e) == 0x001a ? STEP_OUT : 0) | ((opcode & 0x01e0) != 0x01c0 ? STEP_COND : 0) | SUPPORTED; } else { @@ -728,14 +737,23 @@ offs_t cr16b_disassembler::disassemble(std::ostream &stream, offs_t pc, const cr if ((opcode & 0x01e0) != 0x01e0) { if ((opcode & 0x01e0) == 0x01c0) + { stream << "br "; + format_pc_disp9(stream, pc, (opcode & 0x1e00) >> 4 | (opcode & 0x001e)); + return 2 | SUPPORTED; + } else + { util::stream_format(stream, "b%s ", s_cc[(opcode & 0x01e0) >> 5]); - format_pc_disp9(stream, pc, (opcode & 0x1e00) >> 4 | (opcode & 0x001e)); + format_pc_disp9(stream, pc, (opcode & 0x1e00) >> 4 | (opcode & 0x001e)); + return 2 | STEP_COND | SUPPORTED; + } } else + { stream << "res"; - return 2 | SUPPORTED; + return 2 | SUPPORTED; + } case 0x4001: case 0x6001: util::stream_format(stream, "add%c ", BIT(opcode, 13) ? 'w' : 'b'); @@ -808,7 +826,7 @@ offs_t cr16b_disassembler::disassemble(std::ostream &stream, offs_t pc, const cr else util::stream_format(stream, "j%s ", s_cc[(opcode & 0x01e0) >> 5]); format_reg(stream, (opcode & 0x001e) >> 1); - return 2 | (opcode == 0x55dd ? STEP_OUT : 0) | SUPPORTED; + return 2 | ((opcode & 0x001e) == 0x001c ? STEP_OUT : 0) | ((opcode & 0x01e0) != 0x01c0 ? STEP_COND : 0) | SUPPORTED; } else { @@ -941,11 +959,17 @@ offs_t cr16b_disassembler::disassemble(std::ostream &stream, offs_t pc, const cr if ((opcode & 0x01e0) != 0x01e0 && m_arch != cr16_arch::CR16A) { if ((opcode & 0x01e0) == 0x01c0) + { stream << "br "; + format_pc_disp21(stream, pc, u32(opcode & 0x000e) << 16 | u32(opcode & 0x0010) << 12 | opcodes.r16(pc + 2)); + return 4 | SUPPORTED; + } else + { util::stream_format(stream, "b%s ", s_cc[(opcode & 0x01e0) >> 5]); - format_pc_disp21(stream, pc, u32(opcode & 0x000e) << 16 | u32(opcode & 0x0010) << 12 | opcodes.r16(pc + 2)); - return 4 | SUPPORTED; + format_pc_disp21(stream, pc, u32(opcode & 0x000e) << 16 | u32(opcode & 0x0010) << 12 | opcodes.r16(pc + 2)); + return 4 | STEP_COND | SUPPORTED; + } } else { diff --git a/src/devices/cpu/cr16c/cr16cdasm.cpp b/src/devices/cpu/cr16c/cr16cdasm.cpp index c54f2473c6c..1d6521a2568 100644 --- a/src/devices/cpu/cr16c/cr16cdasm.cpp +++ b/src/devices/cpu/cr16c/cr16cdasm.cpp @@ -413,12 +413,21 @@ offs_t cr16c_disassembler::disassemble(std::ostream &stream, offs_t pc, const cr stream << "bal "; format_rpair(stream, (op2 & 0x00f0) >> 4); stream << ", "; + format_pc_disp24(stream, pc, u32(op2 & 0x000f) << 20 | u32(op2 & 0x0f00) << 8 | op3); + return 6 | STEP_OVER | SUPPORTED; } else if ((op2 & 0x00e0) == 0x00e0) + { stream << "br "; + format_pc_disp24(stream, pc, u32(op2 & 0x000f) << 20 | u32(op2 & 0x0f00) << 8 | op3); + return 6 | SUPPORTED; + } else + { util::stream_format(stream, "b%s ", s_cc[(opcode & 0x00f0) >> 4]); - format_pc_disp24(stream, pc, u32(op2 & 0x000f) << 20 | u32(op2 & 0x0f00) << 8 | op3); + format_pc_disp24(stream, pc, u32(op2 & 0x000f) << 20 | u32(op2 & 0x0f00) << 8 | op3); + return 6 | STEP_COND | SUPPORTED; + } } else stream << "res/nop"; @@ -829,7 +838,7 @@ offs_t cr16c_disassembler::disassemble(std::ostream &stream, offs_t pc, const cr else util::stream_format(stream, "j%s ", s_cc[(opcode & 0x00f0) >> 4]); format_rpair(stream, opcode & 0x000f); - return 2 | ((opcode & 0x00ef) == 0x00ee ? STEP_OUT : 0) | SUPPORTED; + return 2 | ((opcode & 0x000f) == 0x000e ? STEP_OUT : 0) | ((opcode & 0x00e0) != 0x00e0 ? STEP_COND : 0) | SUPPORTED; case 0x0b: stream << "mulsb "; @@ -844,7 +853,7 @@ offs_t cr16c_disassembler::disassemble(std::ostream &stream, offs_t pc, const cr format_reg(stream, opcode & 0x000f); stream << ", "; format_pc_disp4(stream, pc, (opcode & 0x00f0) >> 4); - return 2 | SUPPORTED; + return 2 | STEP_COND | SUPPORTED; case 0x10: case 0x11: case 0x12: case 0x13: case 0x14: case 0x15: case 0x16: case 0x17: @@ -858,12 +867,12 @@ offs_t cr16c_disassembler::disassemble(std::ostream &stream, offs_t pc, const cr if ((opcode & 0x0f0f) == 0x0800) { format_pc_disp16(stream, pc, opcodes.r16(pc + 2)); - return 4 | SUPPORTED; + return 4 | ((opcode & 0x00e0) != 0x00e0 ? STEP_COND : 0) | SUPPORTED; } else { format_pc_disp8(stream, pc, (opcode & 0x0f00) >> 4 | (opcode & 0x000f)); - return 2 | SUPPORTED; + return 2 | ((opcode & 0x00e0) != 0x00e0 ? STEP_COND : 0) | SUPPORTED; } case 0x20: case 0x21: case 0x22: case 0x23: diff --git a/src/devices/cpu/diablo/diablo1300dasm.cpp b/src/devices/cpu/diablo/diablo1300dasm.cpp index ed62f3957a6..f0fac2640e4 100644 --- a/src/devices/cpu/diablo/diablo1300dasm.cpp +++ b/src/devices/cpu/diablo/diablo1300dasm.cpp @@ -17,6 +17,7 @@ u32 diablo1300_disassembler::opcode_alignment() const offs_t diablo1300_disassembler::disassemble(std::ostream &stream, offs_t pc, const data_buffer &opcodes, const data_buffer ¶ms) { uint16_t op = opcodes.r16(pc); + uint32_t flags = 0; switch (op & 0x0007) { @@ -27,6 +28,7 @@ offs_t diablo1300_disassembler::disassemble(std::ostream &stream, offs_t pc, con break; case 1: // JNC Addr util::stream_format(stream, "JNC %03X", ((op & 0xff00) >> 8) + ((op & 0x0008) ? 0x100 : 0)); + flags = STEP_COND; break; case 2: // RST #Dport util::stream_format(stream, "RST dv%d", (op & 0x0700) >> 8); @@ -78,5 +80,5 @@ offs_t diablo1300_disassembler::disassemble(std::ostream &stream, offs_t pc, con break; } - return 1 | SUPPORTED; + return 1 | flags | SUPPORTED; } diff --git a/src/devices/cpu/dsp16/dsp16dis.cpp b/src/devices/cpu/dsp16/dsp16dis.cpp index 9abeb81f803..38457888fe3 100644 --- a/src/devices/cpu/dsp16/dsp16dis.cpp +++ b/src/devices/cpu/dsp16/dsp16dis.cpp @@ -92,6 +92,8 @@ offs_t dsp16_disassembler::disassemble(std::ostream &stream, offs_t pc, const da util::stream_format( stream, "if %1$s%2$s%3$s%4$s", con.text, controlled.nop ? "" : " ", controlled.text, comment); + if (!controlled.nop) + flags |= STEP_COND; } break; diff --git a/src/devices/cpu/dsp32/dsp32dis.cpp b/src/devices/cpu/dsp32/dsp32dis.cpp index 8748b2b55ab..2c1b095e9c1 100644 --- a/src/devices/cpu/dsp32/dsp32dis.cpp +++ b/src/devices/cpu/dsp32/dsp32dis.cpp @@ -354,6 +354,8 @@ offs_t dsp32c_disassembler::disassemble(std::ostream &stream, offs_t pc, const d flags = STEP_OUT; util::stream_format(stream, "if (%s) goto %s", condtable[C], rH); } + if (C > 1) + flags |= STEP_COND; } break; } diff --git a/src/devices/cpu/dsp56000/dsp56000d.cpp b/src/devices/cpu/dsp56000/dsp56000d.cpp index d01d16f2d58..116f3e33d55 100644 --- a/src/devices/cpu/dsp56000/dsp56000d.cpp +++ b/src/devices/cpu/dsp56000/dsp56000d.cpp @@ -56,7 +56,7 @@ offs_t dsp56000_disassembler::disassemble(std::ostream &stream, offs_t pc, data_ u32 flags = SUPPORTED; unsigned words = 0; - // fetch the instruction word and consume it + // fetch the instruction word and consume it"j u32 const op = opcodes.r32(pc + words++) & 0x00ffffffU; // fetch the extension word but don't consume it yet @@ -369,9 +369,9 @@ offs_t dsp56000_disassembler::disassemble(std::ostream &stream, offs_t pc, data_ switch (op & 0x010020U) { case 0x000000U: util::stream_format(stream, "jmp %s", ea(MMMRRR, ew)); break; - case 0x000020U: util::stream_format(stream, "j%s %s", CCCC[op & 15], ea(MMMRRR, ew)); break; - case 0x010000U: util::stream_format(stream, "jsr %s", ea(MMMRRR, ew)); break; - case 0x010020U: util::stream_format(stream, "js%s %s", CCCC[op & 15], ea(MMMRRR, ew)); break; + case 0x000020U: util::stream_format(stream, "j%s %s", CCCC[op & 15], ea(MMMRRR, ew)); flags |= STEP_COND; break; + case 0x010000U: util::stream_format(stream, "jsr %s", ea(MMMRRR, ew)); flags |= STEP_OVER; break; + case 0x010020U: util::stream_format(stream, "js%s %s", CCCC[op & 15], ea(MMMRRR, ew)); flags |= STEP_OVER | STEP_COND; break; } // consume absolute @@ -385,12 +385,12 @@ offs_t dsp56000_disassembler::disassemble(std::ostream &stream, offs_t pc, data_ switch (op & 0x010060U) { - case 0x000000U: util::stream_format(stream, "jclr #%d,%s,$%x", op & 31, reg(dddddd), u16(ew)); words++; break; - case 0x000020U: util::stream_format(stream, "jset #%d,%s,$%x", op & 31, reg(dddddd), u16(ew)); words++; break; + case 0x000000U: util::stream_format(stream, "jclr #%d,%s,$%x", op & 31, reg(dddddd), u16(ew)); words++; flags |= STEP_COND; break; + case 0x000020U: util::stream_format(stream, "jset #%d,%s,$%x", op & 31, reg(dddddd), u16(ew)); words++; flags |= STEP_COND; break; case 0x000040U: util::stream_format(stream, "bclr #%d,%s", op & 31, reg(dddddd)); break; case 0x000060U: util::stream_format(stream, "bset #%d,%s", op & 31, reg(dddddd)); break; - case 0x010000U: util::stream_format(stream, "jsclr #%d,%s,$%x", op & 31, reg(dddddd), u16(ew)); words++; break; - case 0x010020U: util::stream_format(stream, "jsset #%d,%s,$%x", op & 31, reg(dddddd), u16(ew)); words++; break; + case 0x010000U: util::stream_format(stream, "jsclr #%d,%s,$%x", op & 31, reg(dddddd), u16(ew)); words++; flags |= STEP_OVER | STEP_COND; break; + case 0x010020U: util::stream_format(stream, "jsset #%d,%s,$%x", op & 31, reg(dddddd), u16(ew)); words++; flags |= STEP_OVER | STEP_COND; break; case 0x010040U: util::stream_format(stream, "bchg #%d,%s", op & 31, reg(dddddd)); break; case 0x010060U: util::stream_format(stream, "btst #%d,%s", op & 31, reg(dddddd)); break; } @@ -405,12 +405,12 @@ offs_t dsp56000_disassembler::disassemble(std::ostream &stream, offs_t pc, data_ { case 0x000000U: util::stream_format(stream, "bclr #%d", op & 31); break; case 0x000020U: util::stream_format(stream, "bset #%d", op & 31); break; - case 0x000080U: util::stream_format(stream, "jclr #%d", op & 31); break; - case 0x0000a0U: util::stream_format(stream, "jset #%d", op & 31); break; + case 0x000080U: util::stream_format(stream, "jclr #%d", op & 31); flags |= STEP_COND; break; + case 0x0000a0U: util::stream_format(stream, "jset #%d", op & 31); flags |= STEP_COND; break; case 0x010000U: util::stream_format(stream, "bchg #%d", op & 31); break; case 0x010020U: util::stream_format(stream, "btst #%d", op & 31); break; - case 0x010080U: util::stream_format(stream, "jsclr #%d", op & 31); break; - case 0x0100a0U: util::stream_format(stream, "jsset #%d", op & 31); break; + case 0x010080U: util::stream_format(stream, "jsclr #%d", op & 31); flags |= STEP_OVER | STEP_COND; break; + case 0x0100a0U: util::stream_format(stream, "jsset #%d", op & 31); flags |= STEP_OVER | STEP_COND; break; } // second operand (address) @@ -432,9 +432,9 @@ offs_t dsp56000_disassembler::disassemble(std::ostream &stream, offs_t pc, data_ } break; case 0xc: util::stream_format(stream, "jmp <$%x", op & 0xfff); break; - case 0xd: util::stream_format(stream, "jsr <$%x", op & 0xfff); break; - case 0xe: util::stream_format(stream, "j%s <$%x", CCCC[(op >> 12) & 15], op & 0xfff); break; - case 0xf: util::stream_format(stream, "js%s <$%x", CCCC[(op >> 12) & 15], op & 0xfff); break; + case 0xd: util::stream_format(stream, "jsr <$%x", op & 0xfff); flags |= STEP_OVER; break; + case 0xe: util::stream_format(stream, "j%s <$%x", CCCC[(op >> 12) & 15], op & 0xfff); flags |= STEP_COND; break; + case 0xf: util::stream_format(stream, "js%s <$%x", CCCC[(op >> 12) & 15], op & 0xfff); flags |= STEP_OVER | STEP_COND; break; } } else diff --git a/src/devices/cpu/e0c6200/e0c6200d.cpp b/src/devices/cpu/e0c6200/e0c6200d.cpp index be2a4ea4d6d..22497b8839f 100644 --- a/src/devices/cpu/e0c6200/e0c6200d.cpp +++ b/src/devices/cpu/e0c6200/e0c6200d.cpp @@ -21,7 +21,7 @@ const char *const e0c6200_disassembler::em_name[] = const u32 e0c6200_disassembler::em_flags[] = { - 0, STEP_OUT, STEP_OVER, STEP_OVER, + STEP_COND, STEP_OUT, STEP_OVER, STEP_OVER, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, @@ -656,7 +656,6 @@ offs_t e0c6200_disassembler::disassemble(std::ostream &stream, offs_t pc, const } // 0xf00 (big switch) - // fetch mnemonic util::stream_format(stream, "%-6s", em_name[m]); @@ -670,7 +669,7 @@ offs_t e0c6200_disassembler::disassemble(std::ostream &stream, offs_t pc, const } } - return 1 | em_flags[m] | SUPPORTED; + return 1 | ((op & 0xf00) == 0 ? 0 : em_flags[m]) | SUPPORTED; } u32 e0c6200_disassembler::opcode_alignment() const diff --git a/src/devices/cpu/e132xs/32xsdasm.cpp b/src/devices/cpu/e132xs/32xsdasm.cpp index 00f24bf99e4..6d3ececb34d 100644 --- a/src/devices/cpu/e132xs/32xsdasm.cpp +++ b/src/devices/cpu/e132xs/32xsdasm.cpp @@ -1751,7 +1751,7 @@ offs_t hyperstone_disassembler::disassemble(std::ostream &stream, offs_t pc, con int32_t rel = PCrel_format(op, pc, opcodes) + 2; util::stream_format(stream, "DBV $%x", rel); - flags = STEP_OVER | step_over_extra(1); + flags = STEP_COND | step_over_extra(1); break; } @@ -1762,7 +1762,7 @@ offs_t hyperstone_disassembler::disassemble(std::ostream &stream, offs_t pc, con int32_t rel = PCrel_format(op, pc, opcodes) + 2; util::stream_format(stream, "DBNV $%x", rel); - flags = STEP_OVER | step_over_extra(1); + flags = STEP_COND | step_over_extra(1); break; } @@ -1773,7 +1773,7 @@ offs_t hyperstone_disassembler::disassemble(std::ostream &stream, offs_t pc, con int32_t rel = PCrel_format(op, pc, opcodes) + 2; util::stream_format(stream, "DBE $%x", rel); - flags = STEP_OVER | step_over_extra(1); + flags = STEP_COND | step_over_extra(1); break; } @@ -1784,7 +1784,7 @@ offs_t hyperstone_disassembler::disassemble(std::ostream &stream, offs_t pc, con int32_t rel = PCrel_format(op, pc, opcodes) + 2; util::stream_format(stream, "DBNE $%x", rel); - flags = STEP_OVER | step_over_extra(1); + flags = STEP_COND | step_over_extra(1); break; } @@ -1795,7 +1795,7 @@ offs_t hyperstone_disassembler::disassemble(std::ostream &stream, offs_t pc, con int32_t rel = PCrel_format(op, pc, opcodes) + 2; util::stream_format(stream, "DBC $%x", rel); - flags = STEP_OVER | step_over_extra(1); + flags = STEP_COND | step_over_extra(1); break; } @@ -1806,7 +1806,7 @@ offs_t hyperstone_disassembler::disassemble(std::ostream &stream, offs_t pc, con int32_t rel = PCrel_format(op, pc, opcodes) + 2; util::stream_format(stream, "DBNC $%x", rel); - flags = STEP_OVER | step_over_extra(1); + flags = STEP_COND | step_over_extra(1); break; } @@ -1817,7 +1817,7 @@ offs_t hyperstone_disassembler::disassemble(std::ostream &stream, offs_t pc, con int32_t rel = PCrel_format(op, pc, opcodes) + 2; util::stream_format(stream, "DBSE $%x", rel); - flags = STEP_OVER | step_over_extra(1); + flags = STEP_COND | step_over_extra(1); break; } @@ -1828,7 +1828,7 @@ offs_t hyperstone_disassembler::disassemble(std::ostream &stream, offs_t pc, con int32_t rel = PCrel_format(op, pc, opcodes) + 2; util::stream_format(stream, "DBHT $%x", rel); - flags = STEP_OVER | step_over_extra(1); + flags = STEP_COND | step_over_extra(1); break; } @@ -1839,7 +1839,7 @@ offs_t hyperstone_disassembler::disassemble(std::ostream &stream, offs_t pc, con int32_t rel = PCrel_format(op, pc, opcodes) + 2; util::stream_format(stream, "DBN $%x", rel); - flags = STEP_OVER | step_over_extra(1); + flags = STEP_COND | step_over_extra(1); break; } @@ -1850,7 +1850,7 @@ offs_t hyperstone_disassembler::disassemble(std::ostream &stream, offs_t pc, con int32_t rel = PCrel_format(op, pc, opcodes) + 2; util::stream_format(stream, "DBNN $%x", rel); - flags = STEP_OVER | step_over_extra(1); + flags = STEP_COND | step_over_extra(1); break; } @@ -1861,7 +1861,7 @@ offs_t hyperstone_disassembler::disassemble(std::ostream &stream, offs_t pc, con int32_t rel = PCrel_format(op, pc, opcodes) + 2; util::stream_format(stream, "DBLE $%x", rel); - flags = STEP_OVER | step_over_extra(1); + flags = STEP_COND | step_over_extra(1); break; } @@ -1872,7 +1872,7 @@ offs_t hyperstone_disassembler::disassemble(std::ostream &stream, offs_t pc, con int32_t rel = PCrel_format(op, pc, opcodes) + 2; util::stream_format(stream, "DBGT $%x", rel); - flags = STEP_OVER | step_over_extra(1); + flags = STEP_COND | step_over_extra(1); break; } @@ -1883,7 +1883,7 @@ offs_t hyperstone_disassembler::disassemble(std::ostream &stream, offs_t pc, con int32_t rel = PCrel_format(op, pc, opcodes) + 2; util::stream_format(stream, "DBR $%x", rel); - flags = STEP_OVER | step_over_extra(1); + flags = STEP_COND | step_over_extra(1); break; } @@ -1923,6 +1923,7 @@ offs_t hyperstone_disassembler::disassemble(std::ostream &stream, offs_t pc, con int32_t rel = PCrel_format(op, pc, opcodes) + 2; util::stream_format(stream, "BV $%x", rel); + flags = STEP_COND; break; } @@ -1933,6 +1934,7 @@ offs_t hyperstone_disassembler::disassemble(std::ostream &stream, offs_t pc, con int32_t rel = PCrel_format(op, pc, opcodes) + 2; util::stream_format(stream, "BNV $%x", rel); + flags = STEP_COND; break; } @@ -1943,6 +1945,7 @@ offs_t hyperstone_disassembler::disassemble(std::ostream &stream, offs_t pc, con int32_t rel = PCrel_format(op, pc, opcodes) + 2; util::stream_format(stream, "BE $%x", rel); + flags = STEP_COND; break; } @@ -1953,6 +1956,7 @@ offs_t hyperstone_disassembler::disassemble(std::ostream &stream, offs_t pc, con int32_t rel = PCrel_format(op, pc, opcodes) + 2; util::stream_format(stream, "BNE $%x", rel); + flags = STEP_COND; break; } @@ -1963,6 +1967,7 @@ offs_t hyperstone_disassembler::disassemble(std::ostream &stream, offs_t pc, con int32_t rel = PCrel_format(op, pc, opcodes) + 2; util::stream_format(stream, "BC $%x", rel); + flags = STEP_COND; break; } @@ -1973,6 +1978,7 @@ offs_t hyperstone_disassembler::disassemble(std::ostream &stream, offs_t pc, con int32_t rel = PCrel_format(op, pc, opcodes) + 2; util::stream_format(stream, "BNC $%x", rel); + flags = STEP_COND; break; } @@ -1983,6 +1989,7 @@ offs_t hyperstone_disassembler::disassemble(std::ostream &stream, offs_t pc, con int32_t rel = PCrel_format(op, pc, opcodes) + 2; util::stream_format(stream, "BSE $%x", rel); + flags = STEP_COND; break; } @@ -1993,6 +2000,7 @@ offs_t hyperstone_disassembler::disassemble(std::ostream &stream, offs_t pc, con int32_t rel = PCrel_format(op, pc, opcodes) + 2; util::stream_format(stream, "BHT $%x", rel); + flags = STEP_COND; break; } @@ -2003,6 +2011,7 @@ offs_t hyperstone_disassembler::disassemble(std::ostream &stream, offs_t pc, con int32_t rel = PCrel_format(op, pc, opcodes) + 2; util::stream_format(stream, "BN $%x", rel); + flags = STEP_COND; break; } @@ -2013,6 +2022,7 @@ offs_t hyperstone_disassembler::disassemble(std::ostream &stream, offs_t pc, con int32_t rel = PCrel_format(op, pc, opcodes) + 2; util::stream_format(stream, "BNN $%x", rel); + flags = STEP_COND; break; } @@ -2023,6 +2033,7 @@ offs_t hyperstone_disassembler::disassemble(std::ostream &stream, offs_t pc, con int32_t rel = PCrel_format(op, pc, opcodes) + 2; util::stream_format(stream, "BLE $%x", rel); + flags = STEP_COND; break; } @@ -2033,6 +2044,7 @@ offs_t hyperstone_disassembler::disassemble(std::ostream &stream, offs_t pc, con int32_t rel = PCrel_format(op, pc, opcodes) + 2; util::stream_format(stream, "BGT $%x", rel); + flags = STEP_COND; break; } @@ -2057,67 +2069,67 @@ offs_t hyperstone_disassembler::disassemble(std::ostream &stream, offs_t pc, con { case TRAPLE: util::stream_format(stream, "TRAPLE %d", trapno); - flags = STEP_OVER; + flags = STEP_OVER | STEP_COND; break; case TRAPGT: util::stream_format(stream, "TRAPGT %d", trapno); - flags = STEP_OVER; + flags = STEP_OVER | STEP_COND; break; case TRAPLT: util::stream_format(stream, "TRAPLT %d", trapno); - flags = STEP_OVER; + flags = STEP_OVER | STEP_COND; break; case TRAPGE: util::stream_format(stream, "TRAPGE %d", trapno); - flags = STEP_OVER; + flags = STEP_OVER | STEP_COND; break; case TRAPSE: util::stream_format(stream, "TRAPSE %d", trapno); - flags = STEP_OVER; + flags = STEP_OVER | STEP_COND; break; case TRAPHT: util::stream_format(stream, "TRAPHT %d", trapno); - flags = STEP_OVER; + flags = STEP_OVER | STEP_COND; break; case TRAPST: util::stream_format(stream, "TRAPST %d", trapno); - flags = STEP_OVER; + flags = STEP_OVER | STEP_COND; break; case TRAPHE: util::stream_format(stream, "TRAPHE %d", trapno); - flags = STEP_OVER; + flags = STEP_OVER | STEP_COND; break; case TRAPE: util::stream_format(stream, "TRAPE %d", trapno); - flags = STEP_OVER; + flags = STEP_OVER | STEP_COND; break; case TRAPNE: util::stream_format(stream, "TRAPNE %d", trapno); - flags = STEP_OVER; + flags = STEP_OVER | STEP_COND; break; case TRAPV: util::stream_format(stream, "TRAPV %d", trapno); - flags = STEP_OVER; + flags = STEP_OVER | STEP_COND; break; diff --git a/src/devices/cpu/f2mc16/f2mc16d.cpp b/src/devices/cpu/f2mc16/f2mc16d.cpp index 2d121f32f30..5d238f37aca 100644 --- a/src/devices/cpu/f2mc16/f2mc16d.cpp +++ b/src/devices/cpu/f2mc16/f2mc16d.cpp @@ -349,7 +349,7 @@ offs_t f2mc16_disassembler::dasm_bitop(std::ostream &stream, offs_t pc, u32 byte { stream << ", "; format_rel(stream, pc + bytes + 1, opcodes.r8(pc + bytes)); - ++bytes; + return (bytes + 1) | STEP_COND | SUPPORTED; } else if ((op2 & 0xe0) == 0x20) stream << ", A"; @@ -710,8 +710,7 @@ offs_t f2mc16_disassembler::dasm_eainst(std::ostream &stream, offs_t pc, u32 byt format_imm8(stream, opcodes.r8(pc + bytes)); stream << ", "; format_rel(stream, pc + bytes + 2, opcodes.r8(pc + bytes + 1)); - bytes += 2; - break; + return (bytes + 2) | STEP_COND | SUPPORTED; case 0x01: util::stream_format(stream, "%-8s@", "JMPP"); @@ -881,8 +880,7 @@ offs_t f2mc16_disassembler::dasm_eainst(std::ostream &stream, offs_t pc, u32 byt bytes += dasm_ea8(stream, pc + bytes, op2, segm, opcodes); stream << ", "; format_rel(stream, pc + bytes + 1, opcodes.r8(pc + bytes)); - ++bytes; - break; + return (bytes + 1) | STEP_COND | SUPPORTED; case 0x05: util::stream_format(stream, "%-8s", "ADD"); @@ -969,8 +967,7 @@ offs_t f2mc16_disassembler::dasm_eainst(std::ostream &stream, offs_t pc, u32 byt bytes += dasm_ea16(stream, pc + bytes, op2, segm, opcodes); stream << ", "; format_rel(stream, pc + bytes + 1, opcodes.r8(pc + bytes)); - ++bytes; - break; + return (bytes + 1) | STEP_COND | SUPPORTED; case 0x07: util::stream_format(stream, "%-8s", "ADDW"); @@ -1061,7 +1058,7 @@ offs_t f2mc16_disassembler::disassemble(std::ostream &stream, offs_t pc, const f { util::stream_format(stream, "%-8s", s_bcc_ops[op & 0x0f]); format_rel(stream, pc + bytes + 1, opcodes.r8(pc + bytes)); - ++bytes; + return (bytes + 1) | STEP_COND | SUPPORTED; } else if (op >= 0xe0) { @@ -1278,8 +1275,7 @@ offs_t f2mc16_disassembler::disassemble(std::ostream &stream, offs_t pc, const f format_imm8(stream, opcodes.r8(pc + bytes++)); stream << ", "; format_rel(stream, pc + bytes + 1, opcodes.r8(pc + bytes)); - ++bytes; - break; + return (bytes + 1) | STEP_COND | SUPPORTED; case 0x2b: case 0x3b: util::stream_format(stream, "%-8sA", "CMPW"); diff --git a/src/devices/cpu/f8/f8dasm.cpp b/src/devices/cpu/f8/f8dasm.cpp index 7f45a4094f8..ef775a78629 100644 --- a/src/devices/cpu/f8/f8dasm.cpp +++ b/src/devices/cpu/f8/f8dasm.cpp @@ -277,14 +277,17 @@ offs_t f8_disassembler::disassemble(std::ostream &stream, offs_t pc, const data_ case 0x81: /* 1000 0001 */ case 0x85: /* 1000 0101 */ util::stream_format(stream, "BP H'%04X'", base_pc + (int8_t)opcodes.r8(pc++) + 1); + flags |= STEP_COND; break; case 0x82: /* 1000 0010 */ util::stream_format(stream, "BC H'%04X'", base_pc + (int8_t)opcodes.r8(pc++) + 1); + flags |= STEP_COND; break; case 0x84: /* 1000 0100 */ util::stream_format(stream, "BZ H'%04X'", base_pc + (int8_t)opcodes.r8(pc++) + 1); + flags |= STEP_COND; break; case 0x80: /* 1000 0000 */ @@ -292,6 +295,7 @@ offs_t f8_disassembler::disassemble(std::ostream &stream, offs_t pc, const data_ case 0x86: /* 1000 0110 */ case 0x87: /* 1000 0111 */ util::stream_format(stream, "BT H'%02X',H'%04X'", op & 0x07, base_pc + (int8_t)opcodes.r8(pc++) + 1); + flags |= STEP_COND; break; case 0x88: /* 1000 1000 */ @@ -324,6 +328,7 @@ offs_t f8_disassembler::disassemble(std::ostream &stream, offs_t pc, const data_ case 0x8f: /* 1000 1111 */ util::stream_format(stream, "BR7 H'%04X'", base_pc + (int8_t)opcodes.r8(pc++) + 1); + flags |= STEP_COND; break; case 0x90: /* 1001 0000 */ @@ -333,18 +338,22 @@ offs_t f8_disassembler::disassemble(std::ostream &stream, offs_t pc, const data_ case 0x91: /* 1001 0001 */ case 0x95: /* 1001 0101 */ util::stream_format(stream, "BM H'%04X'", base_pc + (int8_t)opcodes.r8(pc++) + 1); + flags |= STEP_COND; break; case 0x92: /* 1001 0010 */ util::stream_format(stream, "BNC H'%04X'", base_pc + (int8_t)opcodes.r8(pc++) + 1); + flags |= STEP_COND; break; case 0x94: /* 1001 0100 */ util::stream_format(stream, "BNZ H'%04X'", base_pc + (int8_t)opcodes.r8(pc++) + 1); + flags |= STEP_COND; break; case 0x98: /* 1001 1000 */ util::stream_format(stream, "BNO H'%04X'", base_pc + (int8_t)opcodes.r8(pc++) + 1); + flags |= STEP_COND; break; case 0x93: /* 1001 0011 */ @@ -358,6 +367,7 @@ offs_t f8_disassembler::disassemble(std::ostream &stream, offs_t pc, const data_ case 0x9e: /* 1001 1110 */ case 0x9f: /* 1001 1111 */ util::stream_format(stream, "BF H'%02X',H'%04X'", op & 0x0f, base_pc + (int8_t)opcodes.r8(pc++) + 1); + flags |= STEP_COND; break; case 0xa0: /* 1010 0000 */ diff --git a/src/devices/cpu/fr/frdasm.cpp b/src/devices/cpu/fr/frdasm.cpp index 4a6998e0240..1af624fade2 100644 --- a/src/devices/cpu/fr/frdasm.cpp +++ b/src/devices/cpu/fr/frdasm.cpp @@ -882,46 +882,46 @@ offs_t fr_disassembler::disassemble(std::ostream &stream, offs_t pc, const fr_di return dasm_branch(stream, pc, "BNO", (opcode & 0x00ff) << 1); case 0xe2: - return dasm_branch(stream, pc, "BEQ", (opcode & 0x00ff) << 1); + return dasm_branch(stream, pc, "BEQ", (opcode & 0x00ff) << 1) | STEP_COND; case 0xe3: - return dasm_branch(stream, pc, "BNE", (opcode & 0x00ff) << 1); + return dasm_branch(stream, pc, "BNE", (opcode & 0x00ff) << 1) | STEP_COND; case 0xe4: - return dasm_branch(stream, pc, "BC", (opcode & 0x00ff) << 1); + return dasm_branch(stream, pc, "BC", (opcode & 0x00ff) << 1) | STEP_COND; case 0xe5: - return dasm_branch(stream, pc, "BNC", (opcode & 0x00ff) << 1); + return dasm_branch(stream, pc, "BNC", (opcode & 0x00ff) << 1) | STEP_COND; case 0xe6: - return dasm_branch(stream, pc, "BN", (opcode & 0x00ff) << 1); + return dasm_branch(stream, pc, "BN", (opcode & 0x00ff) << 1) | STEP_COND; case 0xe7: - return dasm_branch(stream, pc, "BP", (opcode & 0x00ff) << 1); + return dasm_branch(stream, pc, "BP", (opcode & 0x00ff) << 1) | STEP_COND; case 0xe8: - return dasm_branch(stream, pc, "BV", (opcode & 0x00ff) << 1); + return dasm_branch(stream, pc, "BV", (opcode & 0x00ff) << 1) | STEP_COND; case 0xe9: - return dasm_branch(stream, pc, "BNV", (opcode & 0x00ff) << 1); + return dasm_branch(stream, pc, "BNV", (opcode & 0x00ff) << 1) | STEP_COND; case 0xea: - return dasm_branch(stream, pc, "BLT", (opcode & 0x00ff) << 1); + return dasm_branch(stream, pc, "BLT", (opcode & 0x00ff) << 1) | STEP_COND; case 0xeb: - return dasm_branch(stream, pc, "BGE", (opcode & 0x00ff) << 1); + return dasm_branch(stream, pc, "BGE", (opcode & 0x00ff) << 1) | STEP_COND; case 0xec: - return dasm_branch(stream, pc, "BLE", (opcode & 0x00ff) << 1); + return dasm_branch(stream, pc, "BLE", (opcode & 0x00ff) << 1) | STEP_COND; case 0xed: - return dasm_branch(stream, pc, "BGT", (opcode & 0x00ff) << 1); + return dasm_branch(stream, pc, "BGT", (opcode & 0x00ff) << 1) | STEP_COND; case 0xee: - return dasm_branch(stream, pc, "BLS", (opcode & 0x00ff) << 1); + return dasm_branch(stream, pc, "BLS", (opcode & 0x00ff) << 1) | STEP_COND; case 0xef: - return dasm_branch(stream, pc, "BHI", (opcode & 0x00ff) << 1); + return dasm_branch(stream, pc, "BHI", (opcode & 0x00ff) << 1) | STEP_COND; case 0xf0: return dasm_branch(stream, pc, "BRA:D", (opcode & 0x00ff) << 1); @@ -930,46 +930,46 @@ offs_t fr_disassembler::disassemble(std::ostream &stream, offs_t pc, const fr_di return dasm_branch(stream, pc, "BNO:D", (opcode & 0x00ff) << 1); case 0xf2: - return dasm_branch(stream, pc, "BEQ:D", (opcode & 0x00ff) << 1); + return dasm_branch(stream, pc, "BEQ:D", (opcode & 0x00ff) << 1) | STEP_COND | step_over_extra(1); case 0xf3: - return dasm_branch(stream, pc, "BNE:D", (opcode & 0x00ff) << 1); + return dasm_branch(stream, pc, "BNE:D", (opcode & 0x00ff) << 1) | STEP_COND | step_over_extra(1); case 0xf4: - return dasm_branch(stream, pc, "BC:D", (opcode & 0x00ff) << 1); + return dasm_branch(stream, pc, "BC:D", (opcode & 0x00ff) << 1) | STEP_COND | step_over_extra(1); case 0xf5: - return dasm_branch(stream, pc, "BNC:D", (opcode & 0x00ff) << 1); + return dasm_branch(stream, pc, "BNC:D", (opcode & 0x00ff) << 1) | STEP_COND | step_over_extra(1); case 0xf6: - return dasm_branch(stream, pc, "BN:D", (opcode & 0x00ff) << 1); + return dasm_branch(stream, pc, "BN:D", (opcode & 0x00ff) << 1) | STEP_COND | step_over_extra(1); case 0xf7: - return dasm_branch(stream, pc, "BP:D", (opcode & 0x00ff) << 1); + return dasm_branch(stream, pc, "BP:D", (opcode & 0x00ff) << 1) | STEP_COND | step_over_extra(1); case 0xf8: - return dasm_branch(stream, pc, "BV:D", (opcode & 0x00ff) << 1); + return dasm_branch(stream, pc, "BV:D", (opcode & 0x00ff) << 1) | STEP_COND | step_over_extra(1); case 0xf9: - return dasm_branch(stream, pc, "BNV:D", (opcode & 0x00ff) << 1); + return dasm_branch(stream, pc, "BNV:D", (opcode & 0x00ff) << 1) | STEP_COND | step_over_extra(1); case 0xfa: - return dasm_branch(stream, pc, "BLT:D", (opcode & 0x00ff) << 1); + return dasm_branch(stream, pc, "BLT:D", (opcode & 0x00ff) << 1) | STEP_COND | step_over_extra(1); case 0xfb: - return dasm_branch(stream, pc, "BGE:D", (opcode & 0x00ff) << 1); + return dasm_branch(stream, pc, "BGE:D", (opcode & 0x00ff) << 1) | STEP_COND | step_over_extra(1); case 0xfc: - return dasm_branch(stream, pc, "BLE:D", (opcode & 0x00ff) << 1); + return dasm_branch(stream, pc, "BLE:D", (opcode & 0x00ff) << 1) | STEP_COND | step_over_extra(1); case 0xfd: - return dasm_branch(stream, pc, "BGT:D", (opcode & 0x00ff) << 1); + return dasm_branch(stream, pc, "BGT:D", (opcode & 0x00ff) << 1) | STEP_COND | step_over_extra(1); case 0xfe: - return dasm_branch(stream, pc, "BLS:D", (opcode & 0x00ff) << 1); + return dasm_branch(stream, pc, "BLS:D", (opcode & 0x00ff) << 1) | STEP_COND | step_over_extra(1); case 0xff: - return dasm_branch(stream, pc, "BHI:D", (opcode & 0x00ff) << 1); + return dasm_branch(stream, pc, "BHI:D", (opcode & 0x00ff) << 1) | STEP_COND | step_over_extra(1); default: return dasm_invalid(stream, opcode); diff --git a/src/devices/cpu/g65816/g65816ds.cpp b/src/devices/cpu/g65816/g65816ds.cpp index 771a3cf0d6d..4d4f5695b5c 100644 --- a/src/devices/cpu/g65816/g65816ds.cpp +++ b/src/devices/cpu/g65816/g65816ds.cpp @@ -64,6 +64,11 @@ bool g65816_disassembler::opcode_struct::is_return() const } } +bool g65816_disassembler::opcode_struct::is_cond() const +{ + return ea == RELB && m_name != op::BRA; +} + g65816_disassembler::opcode_struct::opcode_struct(op n, u8 f, u8 e) : m_name(n), flag(f), ea(e) { } @@ -183,6 +188,8 @@ offs_t g65816_disassembler::disassemble(std::ostream &stream, offs_t pc, const d dasm_flags = STEP_OVER; else if (opcode->is_return()) dasm_flags = STEP_OUT; + else if (opcode->is_cond()) + dasm_flags = STEP_COND; else dasm_flags = 0; diff --git a/src/devices/cpu/g65816/g65816ds.h b/src/devices/cpu/g65816/g65816ds.h index 9e229c0e676..fae05d12d86 100644 --- a/src/devices/cpu/g65816/g65816ds.h +++ b/src/devices/cpu/g65816/g65816ds.h @@ -76,6 +76,7 @@ private: const char *name() const; bool is_call() const; bool is_return() const; + bool is_cond() const; }; static const char *const s_opnames[]; diff --git a/src/devices/cpu/gigatron/gigatrondasm.cpp b/src/devices/cpu/gigatron/gigatrondasm.cpp index e18ec7b9b59..bae0760ab62 100644 --- a/src/devices/cpu/gigatron/gigatrondasm.cpp +++ b/src/devices/cpu/gigatron/gigatrondasm.cpp @@ -51,6 +51,8 @@ offs_t gigatron_disassembler::disassemble(std::ostream &stream, offs_t pc, const util::stream_format(stream, "%-5s", s_jumps[(inst & 0x1c00) >> 10]); if ((inst & 0x1c00) == 0) stream << "y,"; + else if (inst < 0xfc00) + flags = STEP_COND | step_over_extra(1); switch (inst & 0x0300) { @@ -73,8 +75,6 @@ offs_t gigatron_disassembler::disassemble(std::ostream &stream, offs_t pc, const stream << "in"; break; } - - flags = STEP_OVER | step_over_extra(1); } else if ((inst & 0xf300) == 0x0200) stream << "nop"; diff --git a/src/devices/cpu/h16/h16dasm.cpp b/src/devices/cpu/h16/h16dasm.cpp index ac502508e89..a7741a39070 100644 --- a/src/devices/cpu/h16/h16dasm.cpp +++ b/src/devices/cpu/h16/h16dasm.cpp @@ -832,9 +832,14 @@ offs_t h16_disassembler::disassemble(std::ostream &stream, offs_t pc, const h16_ break; case 0xa4: case 0xa5: case 0xa6: - util::stream_format(stream, "%-9s", string_format("B%s.%c", s_conditions[opcodes.r8(pc++) & 0x0f], "BWL"[op & 0x03])); + { + u8 xb = opcodes.r8(pc++); + util::stream_format(stream, "%-9s", string_format("B%s.%c", s_conditions[xb & 0x0f], "BWL"[op & 0x03])); dasm_branch_disp(stream, pc, opcodes, op & 0x03); + if ((xb & 0x0e) != 0) + flags |= STEP_COND; break; + } case 0xa8: case 0xa9: case 0xaa: util::stream_format(stream, "%-9s", string_format("BSR.%c", "BWL"[op & 0x03])); @@ -865,6 +870,7 @@ offs_t h16_disassembler::disassemble(std::ostream &stream, offs_t pc, const h16_ format_register(stream, 0, xb >> 4); stream << ", "; dasm_branch_disp(stream, pc, opcodes, op & 0x03); + flags |= STEP_COND; break; } @@ -995,9 +1001,14 @@ offs_t h16_disassembler::disassemble(std::ostream &stream, offs_t pc, const h16_ break; case 0xf3: - util::stream_format(stream, "TRAP/%s", s_conditions[opcodes.r8(pc++) & 0x0f]); + { + u8 xb = opcodes.r8(pc++); + util::stream_format(stream, "TRAP/%s", s_conditions[xb & 0x0f]); flags |= STEP_OVER; + if ((xb & 0x0e) != 0) + flags |= STEP_COND; break; + } case 0xf4: stream << "RTR"; diff --git a/src/devices/cpu/h6280/6280dasm.cpp b/src/devices/cpu/h6280/6280dasm.cpp index 35b1b60c165..72395525c69 100644 --- a/src/devices/cpu/h6280/6280dasm.cpp +++ b/src/devices/cpu/h6280/6280dasm.cpp @@ -120,6 +120,8 @@ offs_t h6280_disassembler::disassemble(std::ostream &stream, offs_t pc, const da case _rel: util::stream_format(stream, "%-5s$%04X", token[opc], (PC + 1 + (signed char)params.r8(PC)) & 0xffff); PC+=1; + if (opc != _bra && opc != _bsr) + flags = STEP_COND; break; case _imm: util::stream_format(stream, "%-5s#$%02X", token[opc], params.r8(PC)); diff --git a/src/devices/cpu/h8/h8make.py b/src/devices/cpu/h8/h8make.py index 48f4675ed81..e16e5edf766 100644 --- a/src/devices/cpu/h8/h8make.py +++ b/src/devices/cpu/h8/h8make.py @@ -201,6 +201,8 @@ class Opcode: flags = "%d | STEP_OVER" % size elif self.name == "rts" or self.name == "rte": flags = "%d | STEP_OUT" % size + elif self.am1 == "rel8" and self.name != "bt" and self.name != "bf": + flags = "%d | STEP_COND" % size else: flags = "%d" % size diff --git a/src/devices/cpu/h8500/h8500dasm.cpp b/src/devices/cpu/h8500/h8500dasm.cpp index 793ae60acd9..9810312576e 100644 --- a/src/devices/cpu/h8500/h8500dasm.cpp +++ b/src/devices/cpu/h8500/h8500dasm.cpp @@ -404,7 +404,7 @@ offs_t h8500_disassembler::dasm_misc(std::ostream &stream, offs_t pc, u8 ea, con format_reg(stream, op & 0x07, true); stream << ","; format_bdisp(stream, s16(s8(opcodes.r8(pc + 2))), pc + 3); - return 3 | SUPPORTED; + return 3 | STEP_COND | SUPPORTED; } else if (ea == 0x11 && (op & 0xf7) == 0x14 && m_expanded) { @@ -503,7 +503,7 @@ offs_t h8500_disassembler::disassemble(std::ostream &stream, offs_t pc, const h8 format_bdisp(stream, s16(opcodes.r16(pc + 1)), pc + 3); else format_bdisp(stream, s16(s8(opcodes.r8(pc + 1))), pc + 2); - return (BIT(op, 4) ? 3 : 2) | SUPPORTED; + return (BIT(op, 4) ? 3 : 2) | ((op & 0x0e) != 0 ? STEP_COND : 0) | SUPPORTED; } else switch (op) { diff --git a/src/devices/cpu/hd61700/hd61700d.cpp b/src/devices/cpu/hd61700/hd61700d.cpp index ceb21dbb221..b0915fa6378 100644 --- a/src/devices/cpu/hd61700/hd61700d.cpp +++ b/src/devices/cpu/hd61700/hd61700d.cpp @@ -166,7 +166,7 @@ const hd61700_disassembler::dasm hd61700_disassembler::ops[256] = { "rtn", OP_JX_COND, OP_NULL, 0 }, { "rtn", OP_JX_COND, OP_NULL, 0 }, { "rtn", OP_JX_COND, OP_NULL, 0 }, { "rtn", OP_JX_COND, OP_NULL, 0 }, { "rtn", OP_JX_COND, OP_NULL, 0 }, { "rtn", OP_NULL, OP_NULL, 0 }, - { "nop", OP_JX_COND, OP_NULL, 0 }, { "clt", OP_NULL, OP_NULL, 0 }, + { "nop", OP_NULL, OP_NULL, 0 }, { "clt", OP_NULL, OP_NULL, 0 }, { "fst", OP_NULL, OP_NULL, 0 }, { "slw", OP_NULL, OP_NULL, 0 }, { "can", OP_NULL, OP_NULL, 0 }, { "rtni", OP_NULL, OP_NULL, 0 }, { "off", OP_NULL, OP_NULL, 0 }, { "trp", OP_NULL, OP_NULL, 0 }, @@ -340,18 +340,17 @@ uint32_t hd61700_disassembler::get_dasmflags(uint8_t op) switch (op) { case 0x30: case 0x31: case 0x32: case 0x33: //jp - case 0x34: case 0x35: case 0x36: case 0x37: //jp + case 0x34: case 0x35: case 0x36: //jp + case 0xb0: case 0xb1: case 0xb2: case 0xb3: //jr + case 0xb4: case 0xb5: case 0xb6: //jr + return STEP_COND; case 0x70: case 0x71: case 0x72: case 0x73: //cal case 0x74: case 0x75: case 0x76: case 0x77: //cal - case 0xb0: case 0xb1: case 0xb2: case 0xb3: //jr - case 0xb4: case 0xb5: case 0xb6: case 0xb7: //jr - case 0xde: //jp - case 0xdf: //jp - return STEP_OVER; + return STEP_OVER | (op < 0x77 ? STEP_COND : 0); case 0xf0: case 0xf1: case 0xf2: case 0xf3: //rtn case 0xf4: case 0xf5: case 0xf6: case 0xf7: //rtn case 0xfd: //rtni - return STEP_OUT; + return STEP_OUT | (op < 0xf7 ? STEP_COND : 0); } return 0; diff --git a/src/devices/cpu/hmcs40/hmcs40d.cpp b/src/devices/cpu/hmcs40/hmcs40d.cpp index 01ace9aefa9..1c37047dd66 100644 --- a/src/devices/cpu/hmcs40/hmcs40d.cpp +++ b/src/devices/cpu/hmcs40/hmcs40d.cpp @@ -81,7 +81,7 @@ const u32 hmcs40_disassembler::s_flags[] = 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, - 0, STEP_OVER, 0, 0, STEP_OUT, + STEP_COND, STEP_OVER | STEP_COND, 0, 0, STEP_OUT, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, STEP_OUT, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 diff --git a/src/devices/cpu/hpc/hpcdasm.cpp b/src/devices/cpu/hpc/hpcdasm.cpp index 132416cbb64..28e1941a3b5 100644 --- a/src/devices/cpu/hpc/hpcdasm.cpp +++ b/src/devices/cpu/hpc/hpcdasm.cpp @@ -462,10 +462,12 @@ offs_t hpc_disassembler::disassemble(std::ostream &stream, offs_t pc, const hpc_ case 0x06: stream << "ifnc"; + bytes |= STEP_COND; break; case 0x07: stream << "ifc"; + bytes |= STEP_COND; break; case 0x08: case 0x09: case 0x0a: case 0x0b: @@ -476,6 +478,7 @@ offs_t hpc_disassembler::disassemble(std::ostream &stream, offs_t pc, const hpc_ case 0x10: case 0x11: case 0x12: case 0x13: case 0x14: case 0x15: case 0x16: case 0x17: disassemble_bit_op(stream, "ifbit", opcode & 0x07, reg, src, indir, idx); + bytes |= STEP_COND; break; case 0x18: case 0x19: case 0x1a: case 0x1b: @@ -515,6 +518,7 @@ offs_t hpc_disassembler::disassemble(std::ostream &stream, offs_t pc, const hpc_ case 0x3a: disassemble_op(stream, "ifbit", reg, src, imm, indir, idx, false); + bytes |= STEP_COND; break; case 0x3b: @@ -589,7 +593,7 @@ offs_t hpc_disassembler::disassemble(std::ostream &stream, offs_t pc, const hpc_ case 0x8a: case 0xaa: disassemble_unary_op(stream, "decsz", reg, src, indir, idx, BIT(opcode, 5)); - bytes |= STEP_OVER | (1 << OVERINSTSHIFT); + bytes |= STEP_COND; break; case 0x8b: @@ -643,10 +647,12 @@ offs_t hpc_disassembler::disassemble(std::ostream &stream, offs_t pc, const hpc_ case 0x9c: case 0xbc: case 0xdc: case 0xfc: disassemble_op(stream, "ifeq", reg, src, imm, indir, idx, BIT(opcode, 5)); + bytes |= STEP_COND; break; case 0x9d: case 0xbd: case 0xdd: case 0xfd: disassemble_op(stream, "ifgt", reg, src, imm, indir, idx, BIT(opcode, 5)); + bytes |= STEP_COND; break; case 0x9e: case 0xbe: case 0xde: case 0xfe: @@ -691,7 +697,7 @@ offs_t hpc_disassembler::disassemble(std::ostream &stream, offs_t pc, const hpc_ util::stream_format(stream, "%-8sA,[B%c].%c", "lds", BIT(opcode, 1) ? '-' : '+', BIT(opcode, 5) ? 'w' : 'b'); - bytes |= STEP_OVER | (1 << OVERINSTSHIFT); + bytes |= STEP_COND; break; case 0xd0: case 0xd2: @@ -706,7 +712,7 @@ offs_t hpc_disassembler::disassemble(std::ostream &stream, offs_t pc, const hpc_ util::stream_format(stream, "%-8sA,[B%c].%c", "xs", BIT(opcode, 1) ? '-' : '+', BIT(opcode, 5) ? 'w' : 'b'); - bytes |= STEP_OVER | (1 << OVERINSTSHIFT); + bytes |= STEP_COND; break; case 0xd1: case 0xd3: diff --git a/src/devices/cpu/hphybrid/hphybrid_dasm.cpp b/src/devices/cpu/hphybrid/hphybrid_dasm.cpp index fc7b63559e0..9684012e636 100644 --- a/src/devices/cpu/hphybrid/hphybrid_dasm.cpp +++ b/src/devices/cpu/hphybrid/hphybrid_dasm.cpp @@ -286,47 +286,47 @@ const hp_hybrid_disassembler::dis_entry_t hp_hybrid_disassembler::dis_table_comm {0xffff , 0x0000 , "NOP" , &hp_hybrid_disassembler::param_none , 0 }, {0x7800 , 0x0000 , "LDA" , &hp_hybrid_disassembler::param_loc , 0 }, {0x7800 , 0x0800 , "LDB" , &hp_hybrid_disassembler::param_loc , 0 }, - {0x7800 , 0x1000 , "CPA" , &hp_hybrid_disassembler::param_loc , 0 }, - {0x7800 , 0x1800 , "CPB" , &hp_hybrid_disassembler::param_loc , 0 }, + {0x7800 , 0x1000 , "CPA" , &hp_hybrid_disassembler::param_loc , STEP_COND }, + {0x7800 , 0x1800 , "CPB" , &hp_hybrid_disassembler::param_loc , STEP_COND }, {0x7800 , 0x2000 , "ADA" , &hp_hybrid_disassembler::param_loc , 0 }, {0x7800 , 0x2800 , "ADB" , &hp_hybrid_disassembler::param_loc , 0 }, {0x7800 , 0x3000 , "STA" , &hp_hybrid_disassembler::param_loc , 0 }, {0x7800 , 0x3800 , "STB" , &hp_hybrid_disassembler::param_loc , 0 }, {0x7800 , 0x4000 , "JSM" , &hp_hybrid_disassembler::param_loc , STEP_OVER }, - {0x7800 , 0x4800 , "ISZ" , &hp_hybrid_disassembler::param_loc , 0 }, + {0x7800 , 0x4800 , "ISZ" , &hp_hybrid_disassembler::param_loc , STEP_COND }, {0x7800 , 0x5000 , "AND" , &hp_hybrid_disassembler::param_loc , 0 }, - {0x7800 , 0x5800 , "DSZ" , &hp_hybrid_disassembler::param_loc , 0 }, + {0x7800 , 0x5800 , "DSZ" , &hp_hybrid_disassembler::param_loc , STEP_COND }, {0x7800 , 0x6000 , "IOR" , &hp_hybrid_disassembler::param_loc , 0 }, {0x7800 , 0x6800 , "JMP" , &hp_hybrid_disassembler::param_loc , 0 }, {0x7fe0 , 0x7000 , "EXE" , &hp_hybrid_disassembler::param_addr32 , 0 }, - {0xffc0 , 0x7400 , "RZA" , &hp_hybrid_disassembler::param_skip , 0 }, - {0xffc0 , 0x7C00 , "RZB" , &hp_hybrid_disassembler::param_skip , 0 }, - {0xffc0 , 0x7440 , "RIA" , &hp_hybrid_disassembler::param_skip , 0 }, - {0xffc0 , 0x7C40 , "RIB" , &hp_hybrid_disassembler::param_skip , 0 }, - {0xffc0 , 0x74c0 , "SDS" , &hp_hybrid_disassembler::param_skip , 0 }, - {0xffc0 , 0x7500 , "SZA" , &hp_hybrid_disassembler::param_skip , 0 }, - {0xffc0 , 0x7D00 , "SZB" , &hp_hybrid_disassembler::param_skip , 0 }, - {0xffc0 , 0x7540 , "SIA" , &hp_hybrid_disassembler::param_skip , 0 }, - {0xffc0 , 0x7D40 , "SIB" , &hp_hybrid_disassembler::param_skip , 0 }, - {0xffc0 , 0x7480 , "SFS" , &hp_hybrid_disassembler::param_skip , 0 }, - {0xffc0 , 0x7580 , "SFC" , &hp_hybrid_disassembler::param_skip , 0 }, - {0xffc0 , 0x75c0 , "SDC" , &hp_hybrid_disassembler::param_skip , 0 }, - {0xffc0 , 0x7c80 , "SSS" , &hp_hybrid_disassembler::param_skip , 0 }, - {0xffc0 , 0x7d80 , "SSC" , &hp_hybrid_disassembler::param_skip , 0 }, - {0xffc0 , 0x7cc0 , "SHS" , &hp_hybrid_disassembler::param_skip , 0 }, - {0xffc0 , 0x7dc0 , "SHC" , &hp_hybrid_disassembler::param_skip , 0 }, - {0xff00 , 0x7600 , "SLA" , &hp_hybrid_disassembler::param_skip_sc , 0 }, - {0xff00 , 0x7e00 , "SLB" , &hp_hybrid_disassembler::param_skip_sc , 0 }, - {0xff00 , 0x7700 , "RLA" , &hp_hybrid_disassembler::param_skip_sc , 0 }, - {0xff00 , 0x7f00 , "RLB" , &hp_hybrid_disassembler::param_skip_sc , 0 }, - {0xff00 , 0xf400 , "SAP" , &hp_hybrid_disassembler::param_skip_sc , 0 }, - {0xff00 , 0xfc00 , "SBP" , &hp_hybrid_disassembler::param_skip_sc , 0 }, - {0xff00 , 0xf500 , "SAM" , &hp_hybrid_disassembler::param_skip_sc , 0 }, - {0xff00 , 0xfd00 , "SBM" , &hp_hybrid_disassembler::param_skip_sc , 0 }, - {0xff00 , 0xf600 , "SOC" , &hp_hybrid_disassembler::param_skip_sc , 0 }, - {0xff00 , 0xf700 , "SOS" , &hp_hybrid_disassembler::param_skip_sc , 0 }, - {0xff00 , 0xfe00 , "SEC" , &hp_hybrid_disassembler::param_skip_sc , 0 }, - {0xff00 , 0xff00 , "SES" , &hp_hybrid_disassembler::param_skip_sc , 0 }, + {0xffc0 , 0x7400 , "RZA" , &hp_hybrid_disassembler::param_skip , STEP_COND }, + {0xffc0 , 0x7C00 , "RZB" , &hp_hybrid_disassembler::param_skip , STEP_COND }, + {0xffc0 , 0x7440 , "RIA" , &hp_hybrid_disassembler::param_skip , STEP_COND }, + {0xffc0 , 0x7C40 , "RIB" , &hp_hybrid_disassembler::param_skip , STEP_COND }, + {0xffc0 , 0x74c0 , "SDS" , &hp_hybrid_disassembler::param_skip , STEP_COND }, + {0xffc0 , 0x7500 , "SZA" , &hp_hybrid_disassembler::param_skip , STEP_COND }, + {0xffc0 , 0x7D00 , "SZB" , &hp_hybrid_disassembler::param_skip , STEP_COND }, + {0xffc0 , 0x7540 , "SIA" , &hp_hybrid_disassembler::param_skip , STEP_COND }, + {0xffc0 , 0x7D40 , "SIB" , &hp_hybrid_disassembler::param_skip , STEP_COND }, + {0xffc0 , 0x7480 , "SFS" , &hp_hybrid_disassembler::param_skip , STEP_COND }, + {0xffc0 , 0x7580 , "SFC" , &hp_hybrid_disassembler::param_skip , STEP_COND }, + {0xffc0 , 0x75c0 , "SDC" , &hp_hybrid_disassembler::param_skip , STEP_COND }, + {0xffc0 , 0x7c80 , "SSS" , &hp_hybrid_disassembler::param_skip , STEP_COND }, + {0xffc0 , 0x7d80 , "SSC" , &hp_hybrid_disassembler::param_skip , STEP_COND }, + {0xffc0 , 0x7cc0 , "SHS" , &hp_hybrid_disassembler::param_skip , STEP_COND }, + {0xffc0 , 0x7dc0 , "SHC" , &hp_hybrid_disassembler::param_skip , STEP_COND }, + {0xff00 , 0x7600 , "SLA" , &hp_hybrid_disassembler::param_skip_sc , STEP_COND }, + {0xff00 , 0x7e00 , "SLB" , &hp_hybrid_disassembler::param_skip_sc , STEP_COND }, + {0xff00 , 0x7700 , "RLA" , &hp_hybrid_disassembler::param_skip_sc , STEP_COND }, + {0xff00 , 0x7f00 , "RLB" , &hp_hybrid_disassembler::param_skip_sc , STEP_COND }, + {0xff00 , 0xf400 , "SAP" , &hp_hybrid_disassembler::param_skip_sc , STEP_COND }, + {0xff00 , 0xfc00 , "SBP" , &hp_hybrid_disassembler::param_skip_sc , STEP_COND }, + {0xff00 , 0xf500 , "SAM" , &hp_hybrid_disassembler::param_skip_sc , STEP_COND }, + {0xff00 , 0xfd00 , "SBM" , &hp_hybrid_disassembler::param_skip_sc , STEP_COND }, + {0xff00 , 0xf600 , "SOC" , &hp_hybrid_disassembler::param_skip_sc , STEP_COND }, + {0xff00 , 0xf700 , "SOS" , &hp_hybrid_disassembler::param_skip_sc , STEP_COND }, + {0xff00 , 0xfe00 , "SEC" , &hp_hybrid_disassembler::param_skip_sc , STEP_COND }, + {0xff00 , 0xff00 , "SES" , &hp_hybrid_disassembler::param_skip_sc , STEP_COND }, {0xffff , 0xf020 , "TCA" , &hp_hybrid_disassembler::param_none , 0 }, {0xffff , 0xf820 , "TCB" , &hp_hybrid_disassembler::param_none , 0 }, {0xffff , 0xf060 , "CMA" , &hp_hybrid_disassembler::param_none , 0 }, diff --git a/src/devices/cpu/i386/i386dasm.cpp b/src/devices/cpu/i386/i386dasm.cpp index d6df2dac321..2140df040b1 100644 --- a/src/devices/cpu/i386/i386dasm.cpp +++ b/src/devices/cpu/i386/i386dasm.cpp @@ -131,22 +131,22 @@ const i386_disassembler::I386_OPCODE i386_disassembler::i386_opcode_table1[256] {"outsb", 0, PARAM_PREIMP, 0, 0 }, {"outsw\0outsd\0outsd",VAR_NAME, PARAM_PREIMP, 0, 0 }, // 0x70 - {"jo", 0, PARAM_REL8, 0, 0 }, - {"jno", 0, PARAM_REL8, 0, 0 }, - {"jb", 0, PARAM_REL8, 0, 0 }, - {"jae", 0, PARAM_REL8, 0, 0 }, - {"je", 0, PARAM_REL8, 0, 0 }, - {"jne", 0, PARAM_REL8, 0, 0 }, - {"jbe", 0, PARAM_REL8, 0, 0 }, - {"ja", 0, PARAM_REL8, 0, 0 }, - {"js", 0, PARAM_REL8, 0, 0 }, - {"jns", 0, PARAM_REL8, 0, 0 }, - {"jp", 0, PARAM_REL8, 0, 0 }, - {"jnp", 0, PARAM_REL8, 0, 0 }, - {"jl", 0, PARAM_REL8, 0, 0 }, - {"jge", 0, PARAM_REL8, 0, 0 }, - {"jle", 0, PARAM_REL8, 0, 0 }, - {"jg", 0, PARAM_REL8, 0, 0 }, + {"jo", 0, PARAM_REL8, 0, 0, STEP_COND}, + {"jno", 0, PARAM_REL8, 0, 0, STEP_COND}, + {"jb", 0, PARAM_REL8, 0, 0, STEP_COND}, + {"jae", 0, PARAM_REL8, 0, 0, STEP_COND}, + {"je", 0, PARAM_REL8, 0, 0, STEP_COND}, + {"jne", 0, PARAM_REL8, 0, 0, STEP_COND}, + {"jbe", 0, PARAM_REL8, 0, 0, STEP_COND}, + {"ja", 0, PARAM_REL8, 0, 0, STEP_COND}, + {"js", 0, PARAM_REL8, 0, 0, STEP_COND}, + {"jns", 0, PARAM_REL8, 0, 0, STEP_COND}, + {"jp", 0, PARAM_REL8, 0, 0, STEP_COND}, + {"jnp", 0, PARAM_REL8, 0, 0, STEP_COND}, + {"jl", 0, PARAM_REL8, 0, 0, STEP_COND}, + {"jge", 0, PARAM_REL8, 0, 0, STEP_COND}, + {"jle", 0, PARAM_REL8, 0, 0, STEP_COND}, + {"jg", 0, PARAM_REL8, 0, 0, STEP_COND}, // 0x80 {"group80", GROUP, 0, 0, 0 }, {"group81", GROUP, 0, 0, 0 }, @@ -230,7 +230,7 @@ const i386_disassembler::I386_OPCODE i386_disassembler::i386_opcode_table1[256] {"retf", 0, 0, 0, 0, STEP_OUT}, {"int 3", 0, 0, 0, 0, STEP_OVER}, {"int", 0, PARAM_UI8, 0, 0, STEP_OVER}, - {"into", 0, 0, 0, 0 }, + {"into", 0, 0, 0, 0, STEP_OVER | STEP_COND}, {"iret", 0, 0, 0, 0, STEP_OUT}, // 0xd0 {"groupD0", GROUP, 0, 0, 0 }, @@ -250,10 +250,10 @@ const i386_disassembler::I386_OPCODE i386_disassembler::i386_opcode_table1[256] {"escape", FPU, 0, 0, 0 }, {"escape", FPU, 0, 0, 0 }, // 0xe0 - {"loopne", 0, PARAM_REL8, 0, 0, STEP_OVER}, - {"loopz", 0, PARAM_REL8, 0, 0, STEP_OVER}, - {"loop", 0, PARAM_REL8, 0, 0, STEP_OVER}, - {"jcxz\0jecxz\0jrcxz",VAR_NAME, PARAM_REL8, 0, 0 }, + {"loopne", 0, PARAM_REL8, 0, 0, STEP_COND}, + {"loopz", 0, PARAM_REL8, 0, 0, STEP_COND}, + {"loop", 0, PARAM_REL8, 0, 0, STEP_COND}, + {"jcxz\0jecxz\0jrcxz",VAR_NAME, PARAM_REL8, 0, 0, STEP_COND}, {"in", 0, PARAM_AL, PARAM_UI8, 0 }, {"in", 0, PARAM_EAX, PARAM_UI8, 0 }, {"out", 0, PARAM_UI8, PARAM_AL, 0 }, diff --git a/src/devices/cpu/i8008/8008dasm.cpp b/src/devices/cpu/i8008/8008dasm.cpp index 88d2cacf88b..cc0c6faf147 100644 --- a/src/devices/cpu/i8008/8008dasm.cpp +++ b/src/devices/cpu/i8008/8008dasm.cpp @@ -65,7 +65,7 @@ offs_t i8008_disassembler::disassemble(std::ostream &stream, offs_t pc, const da } } break; - case 3 : util::stream_format(stream, "r%c%c",(BIT(op,5) ? 't' : 'f'),flag_names[(op>>3)&3]); break; + case 3 : util::stream_format(stream, "r%c%c",(BIT(op,5) ? 't' : 'f'),flag_names[(op>>3)&3]); flags = STEP_OUT | STEP_COND; break; case 4 : { switch((op >> 3) & 7) { case 0 : util::stream_format(stream, "adi %02x",params.r8(pc)); pc++; break; @@ -81,15 +81,15 @@ offs_t i8008_disassembler::disassemble(std::ostream &stream, offs_t pc, const da break; case 5 : util::stream_format(stream, "rst %02x",(op>>3) & 7); break; case 6 : util::stream_format(stream, "l%ci %02x",reg[(op >> 3) & 7],params.r8(pc)); pc++; break; - case 7 : util::stream_format(stream, "ret"); break; + case 7 : util::stream_format(stream, "ret"); flags = STEP_OUT; break; } break; case 0x01: // starting with 01 switch(op & 7) { - case 0 : util::stream_format(stream, "j%c%c %02x%02x",(BIT(op,5)? 't' : 'f'),flag_names[(op>>3)&3], params.r8(pc+1) & 0x3f,params.r8(pc)); pc+=2; break; - case 2 : util::stream_format(stream, "c%c%c %02x%02x",(BIT(op,5)? 't' : 'f'),flag_names[(op>>3)&3], params.r8(pc+1) & 0x3f,params.r8(pc)); pc+=2; break; + case 0 : util::stream_format(stream, "j%c%c %02x%02x",(BIT(op,5)? 't' : 'f'),flag_names[(op>>3)&3], params.r8(pc+1) & 0x3f,params.r8(pc)); pc+=2; flags = STEP_COND; break; + case 2 : util::stream_format(stream, "c%c%c %02x%02x",(BIT(op,5)? 't' : 'f'),flag_names[(op>>3)&3], params.r8(pc+1) & 0x3f,params.r8(pc)); pc+=2; flags = STEP_OVER | STEP_COND; break; case 4 : util::stream_format(stream, "jmp %02x%02x",params.r8(pc+1) & 0x3f,params.r8(pc)); pc+=2; break; - case 6 : util::stream_format(stream, "cal %02x%02x",params.r8(pc+1) & 0x3f,params.r8(pc)); pc+=2; break; + case 6 : util::stream_format(stream, "cal %02x%02x",params.r8(pc+1) & 0x3f,params.r8(pc)); pc+=2; flags = STEP_OVER; break; case 1 : case 3 : case 5 : diff --git a/src/devices/cpu/i8085/8085dasm.cpp b/src/devices/cpu/i8085/8085dasm.cpp index 4f89dcd1fa2..7e895e13889 100644 --- a/src/devices/cpu/i8085/8085dasm.cpp +++ b/src/devices/cpu/i8085/8085dasm.cpp @@ -216,68 +216,68 @@ offs_t i8085_disassembler::disassemble(std::ostream &stream, offs_t pc, const da case 0xbd: util::stream_format(stream, "cmp l"); break; case 0xbe: util::stream_format(stream, "cmp m"); break; case 0xbf: util::stream_format(stream, "cmp a"); break; - case 0xc0: util::stream_format(stream, "rnz"); flags = STEP_OUT; break; + case 0xc0: util::stream_format(stream, "rnz"); flags = STEP_OUT | STEP_COND; break; case 0xc1: util::stream_format(stream, "pop b"); break; - case 0xc2: util::stream_format(stream, "jnz $%04x", params.r16(pc)); pc+=2; break; + case 0xc2: util::stream_format(stream, "jnz $%04x", params.r16(pc)); pc+=2; flags = STEP_COND; break; case 0xc3: util::stream_format(stream, "jmp $%04x", params.r16(pc)); pc+=2; break; - case 0xc4: util::stream_format(stream, "cnz $%04x", params.r16(pc)); pc+=2; flags = STEP_OVER; break; + case 0xc4: util::stream_format(stream, "cnz $%04x", params.r16(pc)); pc+=2; flags = STEP_OVER | STEP_COND; break; case 0xc5: util::stream_format(stream, "push b"); break; case 0xc6: util::stream_format(stream, "adi $%02x", params.r8(pc)); pc++; break; case 0xc7: util::stream_format(stream, "rst 0"); flags = STEP_OVER; break; - case 0xc8: util::stream_format(stream, "rz"); flags = STEP_OUT; break; + case 0xc8: util::stream_format(stream, "rz"); flags = STEP_OUT | STEP_COND; break; case 0xc9: util::stream_format(stream, "ret"); flags = STEP_OUT; break; - case 0xca: util::stream_format(stream, "jz $%04x", params.r16(pc)); pc+=2; break; - case 0xcb: util::stream_format(stream, "rstv 8 (*)"); flags = STEP_OVER; break; - case 0xcc: util::stream_format(stream, "cz $%04x", params.r16(pc)); pc+=2; flags = STEP_OVER; break; + case 0xca: util::stream_format(stream, "jz $%04x", params.r16(pc)); pc+=2; flags = STEP_COND; break; + case 0xcb: util::stream_format(stream, "rstv 8 (*)"); flags = STEP_OVER | STEP_COND; break; + case 0xcc: util::stream_format(stream, "cz $%04x", params.r16(pc)); pc+=2; flags = STEP_OVER | STEP_COND; break; case 0xcd: util::stream_format(stream, "call $%04x", params.r16(pc)); pc+=2; flags = STEP_OVER; break; case 0xce: util::stream_format(stream, "aci $%02x", params.r8(pc)); pc++; break; case 0xcf: util::stream_format(stream, "rst 1"); flags = STEP_OVER; break; - case 0xd0: util::stream_format(stream, "rnc"); flags = STEP_OUT; break; + case 0xd0: util::stream_format(stream, "rnc"); flags = STEP_OUT | STEP_COND; break; case 0xd1: util::stream_format(stream, "pop d"); break; - case 0xd2: util::stream_format(stream, "jnc $%04x", params.r16(pc)); pc+=2; break; + case 0xd2: util::stream_format(stream, "jnc $%04x", params.r16(pc)); pc+=2; flags = STEP_COND; break; case 0xd3: util::stream_format(stream, "out $%02x", params.r8(pc)); pc++; break; - case 0xd4: util::stream_format(stream, "cnc $%04x", params.r16(pc)); pc+=2; flags = STEP_OVER; break; + case 0xd4: util::stream_format(stream, "cnc $%04x", params.r16(pc)); pc+=2; flags = STEP_OVER | STEP_COND; break; case 0xd5: util::stream_format(stream, "push d"); break; case 0xd6: util::stream_format(stream, "sui $%02x", params.r8(pc)); pc++; break; case 0xd7: util::stream_format(stream, "rst 2"); flags = STEP_OVER; break; - case 0xd8: util::stream_format(stream, "rc"); flags = STEP_OUT; break; + case 0xd8: util::stream_format(stream, "rc"); flags = STEP_OUT | STEP_COND; break; case 0xd9: util::stream_format(stream, "shlx d (*)"); break; - case 0xda: util::stream_format(stream, "jc $%04x", params.r16(pc)); pc+=2; break; + case 0xda: util::stream_format(stream, "jc $%04x", params.r16(pc)); pc+=2; flags = STEP_COND; break; case 0xdb: util::stream_format(stream, "in $%02x", params.r8(pc)); pc++; break; - case 0xdc: util::stream_format(stream, "cc $%04x", params.r16(pc)); pc+=2; flags = STEP_OVER; break; - case 0xdd: util::stream_format(stream, "jnx $%04x (*)", params.r16(pc)); pc+=2; break; + case 0xdc: util::stream_format(stream, "cc $%04x", params.r16(pc)); pc+=2; flags = STEP_OVER | STEP_COND; break; + case 0xdd: util::stream_format(stream, "jnx $%04x (*)", params.r16(pc)); pc+=2; flags = STEP_COND; break; case 0xde: util::stream_format(stream, "sbi $%02x", params.r8(pc)); pc++; break; case 0xdf: util::stream_format(stream, "rst 3"); flags = STEP_OVER; break; - case 0xe0: util::stream_format(stream, "rpo"); flags = STEP_OUT; break; + case 0xe0: util::stream_format(stream, "rpo"); flags = STEP_OUT | STEP_COND; break; case 0xe1: util::stream_format(stream, "pop h"); break; - case 0xe2: util::stream_format(stream, "jpo $%04x", params.r16(pc)); pc+=2; break; + case 0xe2: util::stream_format(stream, "jpo $%04x", params.r16(pc)); pc+=2; flags = STEP_COND; break; case 0xe3: util::stream_format(stream, "xthl"); break; - case 0xe4: util::stream_format(stream, "cpo $%04x", params.r16(pc)); pc+=2; flags = STEP_OVER; break; + case 0xe4: util::stream_format(stream, "cpo $%04x", params.r16(pc)); pc+=2; flags = STEP_OVER | STEP_COND; break; case 0xe5: util::stream_format(stream, "push h"); break; case 0xe6: util::stream_format(stream, "ani $%02x", params.r8(pc)); pc++; break; case 0xe7: util::stream_format(stream, "rst 4"); flags = STEP_OVER; break; - case 0xe8: util::stream_format(stream, "rpe"); flags = STEP_OUT; break; + case 0xe8: util::stream_format(stream, "rpe"); flags = STEP_OUT | STEP_COND; break; case 0xe9: util::stream_format(stream, "pchl"); break; - case 0xea: util::stream_format(stream, "jpe $%04x", params.r16(pc)); pc+=2; break; + case 0xea: util::stream_format(stream, "jpe $%04x", params.r16(pc)); pc+=2; flags = STEP_COND; break; case 0xeb: util::stream_format(stream, "xchg"); break; - case 0xec: util::stream_format(stream, "cpe $%04x", params.r16(pc)); pc+=2; flags = STEP_OVER; break; + case 0xec: util::stream_format(stream, "cpe $%04x", params.r16(pc)); pc+=2; flags = STEP_OVER | STEP_COND; break; case 0xed: util::stream_format(stream, "lhlx d (*)"); break; case 0xee: util::stream_format(stream, "xri $%02x", params.r8(pc)); pc++; break; case 0xef: util::stream_format(stream, "rst 5"); flags = STEP_OVER; break; - case 0xf0: util::stream_format(stream, "rp"); flags = STEP_OUT; break; + case 0xf0: util::stream_format(stream, "rp"); flags = STEP_OUT | STEP_COND; break; case 0xf1: util::stream_format(stream, "pop psw"); break; - case 0xf2: util::stream_format(stream, "jp $%04x", params.r16(pc)); pc+=2; break; + case 0xf2: util::stream_format(stream, "jp $%04x", params.r16(pc)); pc+=2; flags = STEP_COND; break; case 0xf3: util::stream_format(stream, "di"); break; - case 0xf4: util::stream_format(stream, "cp $%04x", params.r16(pc)); pc+=2; break; + case 0xf4: util::stream_format(stream, "cp $%04x", params.r16(pc)); pc+=2; flags = STEP_OVER | STEP_COND; break; case 0xf5: util::stream_format(stream, "push psw"); break; case 0xf6: util::stream_format(stream, "ori $%02x", params.r8(pc)); pc++; break; case 0xf7: util::stream_format(stream, "rst 6"); flags = STEP_OVER; break; - case 0xf8: util::stream_format(stream, "rm"); flags = STEP_OUT; break; + case 0xf8: util::stream_format(stream, "rm"); flags = STEP_OUT | STEP_COND; break; case 0xf9: util::stream_format(stream, "sphl"); break; - case 0xfa: util::stream_format(stream, "jm $%04x", params.r16(pc)); pc+=2; break; + case 0xfa: util::stream_format(stream, "jm $%04x", params.r16(pc)); pc+=2; flags = STEP_COND; break; case 0xfb: util::stream_format(stream, "ei"); break; - case 0xfc: util::stream_format(stream, "cm $%04x", params.r16(pc)); pc+=2; flags = STEP_OVER; break; - case 0xfd: util::stream_format(stream, "jx $%04x (*)", params.r16(pc)); pc+=2; break; + case 0xfc: util::stream_format(stream, "cm $%04x", params.r16(pc)); pc+=2; flags = STEP_OVER | STEP_COND; break; + case 0xfd: util::stream_format(stream, "jx $%04x (*)", params.r16(pc)); pc+=2; flags = STEP_COND; break; case 0xfe: util::stream_format(stream, "cpi $%02x", params.r8(pc)); pc++; break; case 0xff: util::stream_format(stream, "rst 7"); flags = STEP_OVER; break; } diff --git a/src/devices/cpu/i8089/i8089_dasm.cpp b/src/devices/cpu/i8089/i8089_dasm.cpp index 6c31ed0e6b3..99902780c49 100644 --- a/src/devices/cpu/i8089/i8089_dasm.cpp +++ b/src/devices/cpu/i8089/i8089_dasm.cpp @@ -302,8 +302,8 @@ std::string i8089_disassembler::do_disassemble() case 0x0c: return inst_ri("movbi", "movi"); case 0x0e: return inst_r("inc"); case 0x0f: return inst_r("dec"); - case 0x10: return inst_jr("jnz", "ljnz"); - case 0x11: return inst_jr("jz", "ljz"); + case 0x10: m_flags |= STEP_COND; return inst_jr("jnz", "ljnz"); + case 0x11: m_flags |= STEP_COND; return inst_jr("jz", "ljz"); case 0x12: if (m_mm == 0 && m_w == 0 && m_aa == 0 && m_wb == 0 && m_brp == 1) @@ -368,10 +368,10 @@ std::string i8089_disassembler::do_disassemble() case 0x29: return inst_rm("orb", "or"); case 0x2a: return inst_rm("andb", "and"); case 0x2b: return inst_rm("notb", "not"); - case 0x2c: return inst_jm("jmce", "ljmce"); - case 0x2d: return inst_jm("jmcne", "ljmcne"); - case 0x2e: return inst_jmb("jnbt", "ljnbt"); - case 0x2f: return inst_jmb("jbt", "ljbt"); + case 0x2c: m_flags |= STEP_COND; return inst_jm("jmce", "ljmce"); + case 0x2d: m_flags |= STEP_COND; return inst_jm("jmcne", "ljmcne"); + case 0x2e: m_flags |= STEP_COND; return inst_jmb("jnbt", "ljnbt"); + case 0x2f: m_flags |= STEP_COND; return inst_jmb("jbt", "ljbt"); case 0x30: return inst_mi("addbi", "addi"); case 0x31: return inst_mi("orbi", "ori"); case 0x32: return inst_mi("andbi", "andi"); @@ -380,8 +380,8 @@ std::string i8089_disassembler::do_disassemble() case 0x35: return inst_mr("orb", "or"); case 0x36: return inst_mr("andb", "and"); case 0x37: return inst_mr("notb", "not"); - case 0x38: return inst_j16("jnzb", "jnz", "ljnzb", "ljnz"); - case 0x39: return inst_j16("jzb", "jz", "ljzb", "ljz"); + case 0x38: m_flags |= STEP_COND; return inst_j16("jnzb", "jnz", "ljnzb", "ljnz"); + case 0x39: m_flags |= STEP_COND; return inst_j16("jzb", "jz", "ljzb", "ljz"); case 0x3a: return inst_m("incb", "inc"); case 0x3b: return inst_m("decb", "dec"); case 0x3d: return inst_b("setb"); diff --git a/src/devices/cpu/i960/i960dis.cpp b/src/devices/cpu/i960/i960dis.cpp index 66db16451b2..42b36125da1 100644 --- a/src/devices/cpu/i960/i960dis.cpp +++ b/src/devices/cpu/i960/i960dis.cpp @@ -537,6 +537,8 @@ offs_t i960_disassembler::disassemble(std::ostream &stream, offs_t pc, const dat disflags = STEP_OVER; else if (op == 0x0a) disflags = STEP_OUT; + else if ((op & 0xd8) == 0x10 || (op > 0x38 && op < 0x3f)) + disflags = STEP_COND; switch(mnemonic[op].type) { diff --git a/src/devices/cpu/ks0164/ks0164d.cpp b/src/devices/cpu/ks0164/ks0164d.cpp index a87c7bb89b9..a62e4e293a3 100644 --- a/src/devices/cpu/ks0164/ks0164d.cpp +++ b/src/devices/cpu/ks0164/ks0164d.cpp @@ -32,21 +32,21 @@ std::string ks0164_disassembler::off16(s16 dt) #define P std::ostream &stream, u32 opcode, const data_buffer &opcodes, u32 pc const ks0164_disassembler::instruction ks0164_disassembler::instructions[] { - { 0x0000, 0xfc00, [](P) -> u32 { util::stream_format(stream, "bne %04x", (pc + 2 + off10(opcode)) & 0xffff); return 2; } }, - { 0x0400, 0xfc00, [](P) -> u32 { util::stream_format(stream, "beq %04x", (pc + 2 + off10(opcode)) & 0xffff); return 2; } }, - { 0x0800, 0xfc00, [](P) -> u32 { util::stream_format(stream, "bgeu %04x", (pc + 2 + off10(opcode)) & 0xffff); return 2; } }, - { 0x0c00, 0xfc00, [](P) -> u32 { util::stream_format(stream, "bltu %04x", (pc + 2 + off10(opcode)) & 0xffff); return 2; } }, - { 0x1000, 0xfc00, [](P) -> u32 { util::stream_format(stream, "bpl %04x", (pc + 2 + off10(opcode)) & 0xffff); return 2; } }, - { 0x1400, 0xfc00, [](P) -> u32 { util::stream_format(stream, "bmi %04x", (pc + 2 + off10(opcode)) & 0xffff); return 2; } }, - { 0x1800, 0xfc00, [](P) -> u32 { util::stream_format(stream, "bvc %04x", (pc + 2 + off10(opcode)) & 0xffff); return 2; } }, - { 0x1c00, 0xfc00, [](P) -> u32 { util::stream_format(stream, "bvs %04x", (pc + 2 + off10(opcode)) & 0xffff); return 2; } }, - { 0x2000, 0xfc00, [](P) -> u32 { util::stream_format(stream, "bnv %04x", (pc + 2 + off10(opcode)) & 0xffff); return 2; } }, - { 0x2400, 0xfc00, [](P) -> u32 { util::stream_format(stream, "bgtu %04x", (pc + 2 + off10(opcode)) & 0xffff); return 2; } }, - { 0x2800, 0xfc00, [](P) -> u32 { util::stream_format(stream, "bleu %04x", (pc + 2 + off10(opcode)) & 0xffff); return 2; } }, - { 0x2c00, 0xfc00, [](P) -> u32 { util::stream_format(stream, "bgts %04x", (pc + 2 + off10(opcode)) & 0xffff); return 2; } }, - { 0x3000, 0xfc00, [](P) -> u32 { util::stream_format(stream, "bles %04x", (pc + 2 + off10(opcode)) & 0xffff); return 2; } }, - { 0x3400, 0xfc00, [](P) -> u32 { util::stream_format(stream, "bges %04x", (pc + 2 + off10(opcode)) & 0xffff); return 2; } }, - { 0x3800, 0xfc00, [](P) -> u32 { util::stream_format(stream, "blts %04x", (pc + 2 + off10(opcode)) & 0xffff); return 2; } }, + { 0x0000, 0xfc00, [](P) -> u32 { util::stream_format(stream, "bne %04x", (pc + 2 + off10(opcode)) & 0xffff); return 2 | STEP_COND; } }, + { 0x0400, 0xfc00, [](P) -> u32 { util::stream_format(stream, "beq %04x", (pc + 2 + off10(opcode)) & 0xffff); return 2 | STEP_COND; } }, + { 0x0800, 0xfc00, [](P) -> u32 { util::stream_format(stream, "bgeu %04x", (pc + 2 + off10(opcode)) & 0xffff); return 2 | STEP_COND; } }, + { 0x0c00, 0xfc00, [](P) -> u32 { util::stream_format(stream, "bltu %04x", (pc + 2 + off10(opcode)) & 0xffff); return 2 | STEP_COND; } }, + { 0x1000, 0xfc00, [](P) -> u32 { util::stream_format(stream, "bpl %04x", (pc + 2 + off10(opcode)) & 0xffff); return 2 | STEP_COND; } }, + { 0x1400, 0xfc00, [](P) -> u32 { util::stream_format(stream, "bmi %04x", (pc + 2 + off10(opcode)) & 0xffff); return 2 | STEP_COND; } }, + { 0x1800, 0xfc00, [](P) -> u32 { util::stream_format(stream, "bvc %04x", (pc + 2 + off10(opcode)) & 0xffff); return 2 | STEP_COND; } }, + { 0x1c00, 0xfc00, [](P) -> u32 { util::stream_format(stream, "bvs %04x", (pc + 2 + off10(opcode)) & 0xffff); return 2 | STEP_COND; } }, + { 0x2000, 0xfc00, [](P) -> u32 { util::stream_format(stream, "bnv %04x", (pc + 2 + off10(opcode)) & 0xffff); return 2 | STEP_COND; } }, + { 0x2400, 0xfc00, [](P) -> u32 { util::stream_format(stream, "bgtu %04x", (pc + 2 + off10(opcode)) & 0xffff); return 2 | STEP_COND; } }, + { 0x2800, 0xfc00, [](P) -> u32 { util::stream_format(stream, "bleu %04x", (pc + 2 + off10(opcode)) & 0xffff); return 2 | STEP_COND; } }, + { 0x2c00, 0xfc00, [](P) -> u32 { util::stream_format(stream, "bgts %04x", (pc + 2 + off10(opcode)) & 0xffff); return 2 | STEP_COND; } }, + { 0x3000, 0xfc00, [](P) -> u32 { util::stream_format(stream, "bles %04x", (pc + 2 + off10(opcode)) & 0xffff); return 2 | STEP_COND; } }, + { 0x3400, 0xfc00, [](P) -> u32 { util::stream_format(stream, "bges %04x", (pc + 2 + off10(opcode)) & 0xffff); return 2 | STEP_COND; } }, + { 0x3800, 0xfc00, [](P) -> u32 { util::stream_format(stream, "blts %04x", (pc + 2 + off10(opcode)) & 0xffff); return 2 | STEP_COND; } }, { 0x3c00, 0xfc00, [](P) -> u32 { util::stream_format(stream, "bra %04x", (pc + 2 + off10(opcode)) & 0xffff); return 2; } }, { 0x4000, 0xf800, [](P) -> u32 { util::stream_format(stream, "%s += %s", regs[(opcode >> 8) & 7], imm8(opcode)); return 2; } }, @@ -215,8 +215,8 @@ const ks0164_disassembler::instruction ks0164_disassembler::instructions[] { { 0xe007, 0xf88f, [](P) -> u32 { util::stream_format(stream, "(%s%s).b = %s", regs[(opcode >> 8) & 7], off16(opcodes.r16(pc+2)), regs[(opcode >> 4) & 7]); return 4; } }, { 0xe00f, 0xf88f, [](P) -> u32 { util::stream_format(stream, "(%s%s).w = %s", regs[(opcode >> 8) & 7], off16(opcodes.r16(pc+2)), regs[(opcode >> 4) & 7]); return 4; } }, - { 0xf004, 0xf8ff, [](P) -> u32 { util::stream_format(stream, "dbra %s, %04x", regs[(opcode >> 8) & 7], opcodes.r16(pc+2)); return 4; } }, - { 0xf00d, 0xf8ff, [](P) -> u32 { util::stream_format(stream, "cmpbeq %s, %04x, %04x", regs[(opcode >> 8) & 7], opcodes.r16(pc+2), opcodes.r16(pc+4)); return 6; } }, + { 0xf004, 0xf8ff, [](P) -> u32 { util::stream_format(stream, "dbra %s, %04x", regs[(opcode >> 8) & 7], opcodes.r16(pc+2)); return 4 | STEP_COND; } }, + { 0xf00d, 0xf8ff, [](P) -> u32 { util::stream_format(stream, "cmpbeq %s, %04x, %04x", regs[(opcode >> 8) & 7], opcodes.r16(pc+2), opcodes.r16(pc+4)); return 6 | STEP_COND; } }, { 0x0000, 0x0000, [](P) -> u32 { util::stream_format(stream, "?%04x", opcode); return 2; } }, diff --git a/src/devices/cpu/lc58/lc58d.cpp b/src/devices/cpu/lc58/lc58d.cpp index 477ee00ffb0..983550c01e5 100644 --- a/src/devices/cpu/lc58/lc58d.cpp +++ b/src/devices/cpu/lc58/lc58d.cpp @@ -125,14 +125,14 @@ const lc58_disassembler::instruction lc58_disassembler::instructions[] { { 0x3000, 0xf000, [](P) -> u32 { util::stream_format(stream, "wrp %02x, %02x", (opcode >> 7) & 0x1f, opcode & 0x7f); return 1; } }, { 0xc000, 0xf800, [](P) -> u32 { util::stream_format(stream, "jmp %03x", opcode & 0x7ff); return 1; } }, - { 0x8000, 0xf800, [](P) -> u32 { util::stream_format(stream, "bab0 %03x", opcode & 0x7ff); return 1; } }, - { 0x8800, 0xf800, [](P) -> u32 { util::stream_format(stream, "bab1 %03x", opcode & 0x7ff); return 1; } }, - { 0x9000, 0xf800, [](P) -> u32 { util::stream_format(stream, "bab2 %03x", opcode & 0x7ff); return 1; } }, - { 0x9800, 0xf800, [](P) -> u32 { util::stream_format(stream, "bab3 %03x", opcode & 0x7ff); return 1; } }, - { 0xa000, 0xf800, [](P) -> u32 { util::stream_format(stream, "banz %03x", opcode & 0x7ff); return 1; } }, - { 0xb000, 0xf800, [](P) -> u32 { util::stream_format(stream, "baz %03x", opcode & 0x7ff); return 1; } }, - { 0xa800, 0xf800, [](P) -> u32 { util::stream_format(stream, "bcnh %03x", opcode & 0x7ff); return 1; } }, - { 0xb800, 0xf800, [](P) -> u32 { util::stream_format(stream, "bch %03x", opcode & 0x7ff); return 1; } }, + { 0x8000, 0xf800, [](P) -> u32 { util::stream_format(stream, "bab0 %03x", opcode & 0x7ff); return 1 | STEP_COND; } }, + { 0x8800, 0xf800, [](P) -> u32 { util::stream_format(stream, "bab1 %03x", opcode & 0x7ff); return 1 | STEP_COND; } }, + { 0x9000, 0xf800, [](P) -> u32 { util::stream_format(stream, "bab2 %03x", opcode & 0x7ff); return 1 | STEP_COND; } }, + { 0x9800, 0xf800, [](P) -> u32 { util::stream_format(stream, "bab3 %03x", opcode & 0x7ff); return 1 | STEP_COND; } }, + { 0xa000, 0xf800, [](P) -> u32 { util::stream_format(stream, "banz %03x", opcode & 0x7ff); return 1 | STEP_COND; } }, + { 0xb000, 0xf800, [](P) -> u32 { util::stream_format(stream, "baz %03x", opcode & 0x7ff); return 1 | STEP_COND; } }, + { 0xa800, 0xf800, [](P) -> u32 { util::stream_format(stream, "bcnh %03x", opcode & 0x7ff); return 1 | STEP_COND; } }, + { 0xb800, 0xf800, [](P) -> u32 { util::stream_format(stream, "bch %03x", opcode & 0x7ff); return 1 | STEP_COND; } }, { 0xc800, 0xf800, [](P) -> u32 { util::stream_format(stream, "call %03x", opcode & 0x7ff); return 1 | STEP_OVER; } }, { 0xd000, 0xffff, [](P) -> u32 { util::stream_format(stream, "rts"); return 1 | STEP_OUT; } }, diff --git a/src/devices/cpu/lr35902/lr35902d.cpp b/src/devices/cpu/lr35902/lr35902d.cpp index 3a287c10851..3b25f9b428d 100644 --- a/src/devices/cpu/lr35902/lr35902d.cpp +++ b/src/devices/cpu/lr35902/lr35902d.cpp @@ -22,13 +22,13 @@ const char *const lr35902_disassembler::s_mnemonic[] = }; const uint32_t lr35902_disassembler::s_flags[] = { - 0 ,0 ,0 ,0 ,STEP_OVER,0 ,0 , - 0 ,0 ,0 ,0 ,0 ,0 ,STEP_OVER, - 0 ,0 ,0 ,0 ,0 ,0 ,0 , - 0 ,0 ,0 ,STEP_OUT ,STEP_OUT ,0 ,0 , - 0 ,0 ,0 ,0 ,0 ,0 ,STEP_OVER, - 0 ,0 ,0 ,0 ,0 ,0 ,0 , - STEP_OVER,0 ,0 ,0 + 0 ,0 ,0 ,0 ,STEP_OVER,0 ,0 , + 0 ,0 ,0 ,0 ,0 ,0 ,STEP_OVER, + 0 ,0 ,STEP_COND,STEP_COND,0 ,0 ,0 , + 0 ,0 ,0 ,STEP_OUT ,STEP_OUT ,0 ,0 , + 0 ,0 ,0 ,0 ,0 ,0 ,STEP_OVER, + 0 ,0 ,0 ,0 ,0 ,0 ,0 , + STEP_OVER,0 ,0 ,0 }; const lr35902_disassembler::lr35902dasm lr35902_disassembler::mnemonic_cb[256] = { @@ -195,6 +195,7 @@ offs_t lr35902_disassembler::disassemble(std::ostream &stream, offs_t pc, const d = &mnemonic_main[op]; } + bool comma = false; if( d->arguments ) { util::stream_format(stream, "%-4s ", s_mnemonic[d->mnemonic]); src = d->arguments; @@ -245,6 +246,9 @@ offs_t lr35902_disassembler::disassemble(std::ostream &stream, offs_t pc, const pos += 2; util::stream_format(stream, "$%04X", ea); break; + case ',': + comma = true; + [[fallthrough]]; default: stream << *src; break; @@ -255,5 +259,9 @@ offs_t lr35902_disassembler::disassemble(std::ostream &stream, offs_t pc, const util::stream_format(stream, "%s", s_mnemonic[d->mnemonic]); } - return (pos - pc) | s_flags[d->mnemonic] | SUPPORTED; + uint32_t flags = s_flags[d->mnemonic]; + if (flags == STEP_COND && !comma) + flags = 0; + + return (pos - pc) | flags | SUPPORTED; } diff --git a/src/devices/cpu/m32c/m32cdasm.cpp b/src/devices/cpu/m32c/m32cdasm.cpp index 9c687a37f47..a198971e965 100644 --- a/src/devices/cpu/m32c/m32cdasm.cpp +++ b/src/devices/cpu/m32c/m32cdasm.cpp @@ -856,7 +856,7 @@ void m32c_disassembler::dasm_1101(std::ostream &stream, offs_t &pc, const m32c_d stream << "und"; } -void m32c_disassembler::dasm_111x(std::ostream &stream, offs_t &pc, const m32c_disassembler::data_buffer &opcodes, u8 op1, bool indirect_dest) const +void m32c_disassembler::dasm_111x(std::ostream &stream, offs_t &pc, offs_t &flags, const m32c_disassembler::data_buffer &opcodes, u8 op1, bool indirect_dest) const { u8 op2 = opcodes.r8(pc++); if ((op2 & 0x30) == 0 || ((op2 & 0x30) == 0x20 && !BIT(op1, 4))) @@ -877,6 +877,7 @@ void m32c_disassembler::dasm_111x(std::ostream &stream, offs_t &pc, const m32c_d dasm_operand(stream, pc, opcodes, (op1 & 0x0e) << 1 | BIT(op2, 6, 2), op1 & 1, indirect_dest); stream << ", "; format_label(stream, pc + s8(opcodes.r8(pc))); + flags |= STEP_COND; ++pc; } else if ((op2 & 0x30) == 0x30 && BIT(op1, 4)) @@ -1050,6 +1051,7 @@ offs_t m32c_disassembler::disassemble(std::ostream &stream, offs_t pc, const m32 util::stream_format(stream, "%-11s", util::string_format("j%s", s_cnds[bitswap<4>(op1, 6, 5, 4, 0)])); format_label(stream, pc + s8(opcodes.r8(pc))); ++pc; + flags |= STEP_COND; break; case 0x8c: case 0x8d: @@ -1211,7 +1213,7 @@ offs_t m32c_disassembler::disassemble(std::ostream &stream, offs_t pc, const m32 case 0xe0: case 0xe1: case 0xe2: case 0xe3: case 0xe4: case 0xe5: case 0xe6: case 0xe7: case 0xe8: case 0xe9: case 0xf0: case 0xf1: case 0xf2: case 0xf3: case 0xf4: case 0xf5: case 0xf6: case 0xf7: case 0xf8: case 0xf9: - dasm_111x(stream, pc, opcodes, op1, indirect_dest); + dasm_111x(stream, pc, flags, opcodes, op1, indirect_dest); break; case 0xec: diff --git a/src/devices/cpu/m32c/m32cdasm.h b/src/devices/cpu/m32c/m32cdasm.h index f71597c6c63..1b30f486376 100644 --- a/src/devices/cpu/m32c/m32cdasm.h +++ b/src/devices/cpu/m32c/m32cdasm.h @@ -51,7 +51,7 @@ private: void dasm_00000001(std::ostream &stream, offs_t &pc, const data_buffer &opcodes, bool indirect_src, bool indirect_dest) const; void dasm_general(std::ostream &stream, offs_t &pc, offs_t &flags, const data_buffer &opcodes, u8 op1, bool indirect_src, bool indirect_dest) const; void dasm_1101(std::ostream &stream, offs_t &pc, const data_buffer &opcodes, u8 op1, bool indirect_src, bool indirect_dest) const; - void dasm_111x(std::ostream &stream, offs_t &pc, const data_buffer &opcodes, u8 op1, bool indirect_dest) const; + void dasm_111x(std::ostream &stream, offs_t &pc, offs_t &flags, const data_buffer &opcodes, u8 op1, bool indirect_dest) const; }; #endif // MAME_CPU_M32C_M32CDASM_H diff --git a/src/devices/cpu/m37710/m7700ds.cpp b/src/devices/cpu/m37710/m7700ds.cpp index 12478d32903..016375ba094 100644 --- a/src/devices/cpu/m37710/m7700ds.cpp +++ b/src/devices/cpu/m37710/m7700ds.cpp @@ -354,6 +354,8 @@ offs_t m7700_disassembler::disassemble(std::ostream &stream, offs_t pc, const da flags = STEP_OVER; else if (opcode->is_return()) flags = STEP_OUT; + else if (opcode->is_bcond()) + flags = STEP_COND; stream << opcode->name(); diff --git a/src/devices/cpu/m37710/m7700ds.h b/src/devices/cpu/m37710/m7700ds.h index 07bdaf49d48..0a5bef9dd61 100644 --- a/src/devices/cpu/m37710/m7700ds.h +++ b/src/devices/cpu/m37710/m7700ds.h @@ -73,6 +73,7 @@ private: public: bool is_call() const { return m_name == op::JSR; } bool is_return() const { return (m_name == op::RTS) || (m_name == op::RTI); } + bool is_bcond() const { return (ea == RELB && m_name != op::BRA) || (m_name == op::BBS) || (m_name == op::BBC); } const char *name() const { return s_opnames[unsigned(m_name)]; } static const m7700_opcode_struct &get(unsigned char ins) { return s_opcodes[ins]; } diff --git a/src/devices/cpu/m6502/m6502make.py b/src/devices/cpu/m6502/m6502make.py index bd2ef7328a3..ed9bcc20169 100755 --- a/src/devices/cpu/m6502/m6502make.py +++ b/src/devices/cpu/m6502/m6502make.py @@ -233,6 +233,8 @@ def save_dasm(f, device, states): extra = "STEP_OVER" elif opc in ["rts", "rti", "rtn", "retf", "tpi"]: extra = "STEP_OUT" + elif opc in ["bcc", "bcs", "beq", "bmi", "bne", "bpl", "bvc", "bvs", "bbr", "bbs", "bbc", "bar", "bas"]: + extra = "STEP_COND" emit(f, '\t{ "%s", DASM_%s, %s },' % (opc, mode, extra)) emit(f, DISASM_EPILOG % d) diff --git a/src/devices/cpu/m6800/6800dasm.cpp b/src/devices/cpu/m6800/6800dasm.cpp index 7b5e1227425..6dcb60e572c 100644 --- a/src/devices/cpu/m6800/6800dasm.cpp +++ b/src/devices/cpu/m6800/6800dasm.cpp @@ -165,6 +165,8 @@ offs_t m680x_disassembler::disassemble(std::ostream &stream, offs_t pc, const da flags = STEP_OVER; else if (opcode == rti || opcode == rts) flags = STEP_OUT; + else if (args == rel && opcode != bra && opcode != brn && opcode != bsr) + flags = STEP_COND; if ( invalid & invalid_mask ) /* invalid for this cpu type ? */ { diff --git a/src/devices/cpu/m68000/m68kdasm.cpp b/src/devices/cpu/m68000/m68kdasm.cpp index d0cb3ac63d6..5377c22f4e8 100644 --- a/src/devices/cpu/m68000/m68kdasm.cpp +++ b/src/devices/cpu/m68000/m68kdasm.cpp @@ -637,12 +637,14 @@ std::string m68k_disassembler::d68000_asl_ea() std::string m68k_disassembler::d68000_bcc_8() { u32 temp_pc = m_cpu_pc; + m_flags = STEP_COND; return util::string_format("b%-2s $%x", m_cc[(m_cpu_ir>>8)&0xf], temp_pc + make_int_8(m_cpu_ir)); } std::string m68k_disassembler::d68000_bcc_16() { u32 temp_pc = m_cpu_pc; + m_flags = STEP_COND; return util::string_format("b%-2s $%x", m_cc[(m_cpu_ir>>8)&0xf], temp_pc + make_int_16(read_imm_16())); } @@ -652,6 +654,7 @@ std::string m68k_disassembler::d68020_bcc_32() auto limit = limit_cpu_types(M68020_PLUS); if(limit.first) return limit.second; + m_flags = STEP_COND; return util::string_format("b%-2s $%x; (2+)", m_cc[(m_cpu_ir>>8)&0xf], temp_pc + read_imm_32()); } @@ -933,7 +936,7 @@ std::string m68k_disassembler::d68020_cas2_32() std::string m68k_disassembler::d68000_chk_16() { - m_flags = STEP_OVER; + m_flags = STEP_OVER | STEP_COND; return util::string_format("chk.w %s, D%d", get_ea_mode_str_16(m_cpu_ir), (m_cpu_ir>>9)&7); } @@ -942,7 +945,7 @@ std::string m68k_disassembler::d68020_chk_32() auto limit = limit_cpu_types(M68020_PLUS); if(limit.first) return limit.second; - m_flags = STEP_OVER; + m_flags = STEP_OVER | STEP_COND; return util::string_format("chk.l %s, D%d; (2+)", get_ea_mode_str_32(m_cpu_ir), (m_cpu_ir>>9)&7); } @@ -1265,14 +1268,14 @@ std::string m68k_disassembler::d68040_cpush() std::string m68k_disassembler::d68000_dbra() { u32 temp_pc = m_cpu_pc; - m_flags = STEP_OVER; + m_flags = STEP_COND; return util::string_format("dbra D%d, $%x", m_cpu_ir & 7, temp_pc + make_int_16(read_imm_16())); } std::string m68k_disassembler::d68000_dbcc() { u32 temp_pc = m_cpu_pc; - m_flags = STEP_OVER; + m_flags = STEP_COND; return util::string_format("db%-2s D%d, $%x", m_cc[(m_cpu_ir>>8)&0xf], m_cpu_ir & 7, temp_pc + make_int_16(read_imm_16())); } @@ -2749,7 +2752,7 @@ std::string m68k_disassembler::d68020_trapcc_0() auto limit = limit_cpu_types(M68020_PLUS); if(limit.first) return limit.second; - m_flags = STEP_OVER; + m_flags = STEP_OVER | STEP_COND; return util::string_format("trap%-2s; (2+)", m_cc[(m_cpu_ir>>8)&0xf]); } @@ -2758,7 +2761,7 @@ std::string m68k_disassembler::d68020_trapcc_16() auto limit = limit_cpu_types(M68020_PLUS); if(limit.first) return limit.second; - m_flags = STEP_OVER; + m_flags = STEP_OVER | STEP_COND; return util::string_format("trap%-2s %s; (2+)", m_cc[(m_cpu_ir>>8)&0xf], get_imm_str_u16()); } @@ -2767,13 +2770,13 @@ std::string m68k_disassembler::d68020_trapcc_32() auto limit = limit_cpu_types(M68020_PLUS); if(limit.first) return limit.second; - m_flags = STEP_OVER; + m_flags = STEP_OVER | STEP_COND; return util::string_format("trap%-2s %s; (2+)", m_cc[(m_cpu_ir>>8)&0xf], get_imm_str_u32()); } std::string m68k_disassembler::d68000_trapv() { - m_flags = STEP_OVER; + m_flags = STEP_OVER | STEP_COND; return util::string_format("trapv"); } diff --git a/src/devices/cpu/m6805/6805dasm.cpp b/src/devices/cpu/m6805/6805dasm.cpp index 3f6b2fbb14b..f58d5d00ef7 100644 --- a/src/devices/cpu/m6805/6805dasm.cpp +++ b/src/devices/cpu/m6805/6805dasm.cpp @@ -129,6 +129,24 @@ offs_t m6805_base_disassembler::disassemble(std::ostream &stream, offs_t pc, con case op_names::rti: flags = STEP_OUT; break; + case op_names::brset: + case op_names::brclr: + case op_names::bhi: + case op_names::bls: + case op_names::bcc: + case op_names::bcs: + case op_names::bne: + case op_names::beq: + case op_names::bhcc: + case op_names::bhcs: + case op_names::bpl: + case op_names::bmi: + case op_names::bmc: + case op_names::bms: + case op_names::bil: + case op_names::bih: + flags = STEP_COND; + break; default: flags = 0; } diff --git a/src/devices/cpu/m6809/6x09dasm.cpp b/src/devices/cpu/m6809/6x09dasm.cpp index e45c1a1bc8c..16ee2e2edd8 100644 --- a/src/devices/cpu/m6809/6x09dasm.cpp +++ b/src/devices/cpu/m6809/6x09dasm.cpp @@ -323,20 +323,20 @@ const m6x09_base_disassembler::opcodeinfo m6x09_disassembler::m6x09_opcodes[] = { 0x20, 2, "BRA", REL, M6x09_GENERAL }, { 0x21, 2, "BRN", REL, M6x09_GENERAL }, - { 0x22, 2, "BHI", REL, M6x09_GENERAL }, - { 0x23, 2, "BLS", REL, M6x09_GENERAL }, - { 0x24, 2, "BCC", REL, M6x09_GENERAL }, - { 0x25, 2, "BCS", REL, M6x09_GENERAL }, - { 0x26, 2, "BNE", REL, M6x09_GENERAL }, - { 0x27, 2, "BEQ", REL, M6x09_GENERAL }, - { 0x28, 2, "BVC", REL, M6x09_GENERAL }, - { 0x29, 2, "BVS", REL, M6x09_GENERAL }, - { 0x2A, 2, "BPL", REL, M6x09_GENERAL }, - { 0x2B, 2, "BMI", REL, M6x09_GENERAL }, - { 0x2C, 2, "BGE", REL, M6x09_GENERAL }, - { 0x2D, 2, "BLT", REL, M6x09_GENERAL }, - { 0x2E, 2, "BGT", REL, M6x09_GENERAL }, - { 0x2F, 2, "BLE", REL, M6x09_GENERAL }, + { 0x22, 2, "BHI", REL, M6x09_GENERAL, STEP_COND }, + { 0x23, 2, "BLS", REL, M6x09_GENERAL, STEP_COND }, + { 0x24, 2, "BCC", REL, M6x09_GENERAL, STEP_COND }, + { 0x25, 2, "BCS", REL, M6x09_GENERAL, STEP_COND }, + { 0x26, 2, "BNE", REL, M6x09_GENERAL, STEP_COND }, + { 0x27, 2, "BEQ", REL, M6x09_GENERAL, STEP_COND }, + { 0x28, 2, "BVC", REL, M6x09_GENERAL, STEP_COND }, + { 0x29, 2, "BVS", REL, M6x09_GENERAL, STEP_COND }, + { 0x2A, 2, "BPL", REL, M6x09_GENERAL, STEP_COND }, + { 0x2B, 2, "BMI", REL, M6x09_GENERAL, STEP_COND }, + { 0x2C, 2, "BGE", REL, M6x09_GENERAL, STEP_COND }, + { 0x2D, 2, "BLT", REL, M6x09_GENERAL, STEP_COND }, + { 0x2E, 2, "BGT", REL, M6x09_GENERAL, STEP_COND }, + { 0x2F, 2, "BLE", REL, M6x09_GENERAL, STEP_COND }, { 0x30, 2, "LEAX", IND, M6x09_GENERAL }, { 0x31, 2, "LEAY", IND, M6x09_GENERAL }, @@ -1114,38 +1114,38 @@ const m6x09_base_disassembler::opcodeinfo konami_disassembler::konami_opcodes[] { 0x5C, 2, "STS", IND, M6x09_GENERAL }, { 0x60, 2, "BRA", REL, M6x09_GENERAL }, - { 0x61, 2, "BHI", REL, M6x09_GENERAL }, - { 0x62, 2, "BCC", REL, M6x09_GENERAL }, - { 0x63, 2, "BNE", REL, M6x09_GENERAL }, - { 0x64, 2, "BVC", REL, M6x09_GENERAL }, - { 0x65, 2, "BPL", REL, M6x09_GENERAL }, - { 0x66, 2, "BGE", REL, M6x09_GENERAL }, - { 0x67, 2, "BGT", REL, M6x09_GENERAL }, + { 0x61, 2, "BHI", REL, M6x09_GENERAL, STEP_COND }, + { 0x62, 2, "BCC", REL, M6x09_GENERAL, STEP_COND }, + { 0x63, 2, "BNE", REL, M6x09_GENERAL, STEP_COND }, + { 0x64, 2, "BVC", REL, M6x09_GENERAL, STEP_COND }, + { 0x65, 2, "BPL", REL, M6x09_GENERAL, STEP_COND }, + { 0x66, 2, "BGE", REL, M6x09_GENERAL, STEP_COND }, + { 0x67, 2, "BGT", REL, M6x09_GENERAL, STEP_COND }, { 0x68, 3, "LBRA", LREL, M6x09_GENERAL }, - { 0x69, 3, "LBHI", LREL, M6x09_GENERAL }, - { 0x6A, 3, "LBCC", LREL, M6x09_GENERAL }, - { 0x6B, 3, "LBNE", LREL, M6x09_GENERAL }, - { 0x6C, 3, "LBVC", LREL, M6x09_GENERAL }, - { 0x6D, 3, "LBPL", LREL, M6x09_GENERAL }, - { 0x6E, 3, "LBGE", LREL, M6x09_GENERAL }, - { 0x6F, 3, "LBGT", LREL, M6x09_GENERAL }, + { 0x69, 3, "LBHI", LREL, M6x09_GENERAL, STEP_COND }, + { 0x6A, 3, "LBCC", LREL, M6x09_GENERAL, STEP_COND }, + { 0x6B, 3, "LBNE", LREL, M6x09_GENERAL, STEP_COND }, + { 0x6C, 3, "LBVC", LREL, M6x09_GENERAL, STEP_COND }, + { 0x6D, 3, "LBPL", LREL, M6x09_GENERAL, STEP_COND }, + { 0x6E, 3, "LBGE", LREL, M6x09_GENERAL, STEP_COND }, + { 0x6F, 3, "LBGT", LREL, M6x09_GENERAL, STEP_COND }, { 0x70, 2, "BRN", REL, M6x09_GENERAL }, - { 0x71, 2, "BLS", REL, M6x09_GENERAL }, - { 0x72, 2, "BCS", REL, M6x09_GENERAL }, - { 0x73, 2, "BEQ", REL, M6x09_GENERAL }, - { 0x74, 2, "BVS", REL, M6x09_GENERAL }, - { 0x75, 2, "BMI", REL, M6x09_GENERAL }, - { 0x76, 2, "BLT", REL, M6x09_GENERAL }, - { 0x77, 2, "BLE", REL, M6x09_GENERAL }, + { 0x71, 2, "BLS", REL, M6x09_GENERAL, STEP_COND }, + { 0x72, 2, "BCS", REL, M6x09_GENERAL, STEP_COND }, + { 0x73, 2, "BEQ", REL, M6x09_GENERAL, STEP_COND }, + { 0x74, 2, "BVS", REL, M6x09_GENERAL, STEP_COND }, + { 0x75, 2, "BMI", REL, M6x09_GENERAL, STEP_COND }, + { 0x76, 2, "BLT", REL, M6x09_GENERAL, STEP_COND }, + { 0x77, 2, "BLE", REL, M6x09_GENERAL, STEP_COND }, { 0x78, 3, "LBRN", LREL, M6x09_GENERAL }, - { 0x79, 3, "LBLS", LREL, M6x09_GENERAL }, - { 0x7A, 3, "LBCS", LREL, M6x09_GENERAL }, - { 0x7B, 3, "LBEQ", LREL, M6x09_GENERAL }, - { 0x7C, 3, "LBVS", LREL, M6x09_GENERAL }, - { 0x7D, 3, "LBMI", LREL, M6x09_GENERAL }, - { 0x7E, 3, "LBLT", LREL, M6x09_GENERAL }, - { 0x7F, 3, "LBLE", LREL, M6x09_GENERAL }, + { 0x79, 3, "LBLS", LREL, M6x09_GENERAL, STEP_COND }, + { 0x7A, 3, "LBCS", LREL, M6x09_GENERAL, STEP_COND }, + { 0x7B, 3, "LBEQ", LREL, M6x09_GENERAL, STEP_COND }, + { 0x7C, 3, "LBVS", LREL, M6x09_GENERAL, STEP_COND }, + { 0x7D, 3, "LBMI", LREL, M6x09_GENERAL, STEP_COND }, + { 0x7E, 3, "LBLT", LREL, M6x09_GENERAL, STEP_COND }, + { 0x7F, 3, "LBLE", LREL, M6x09_GENERAL, STEP_COND }, { 0x80, 1, "CLRA", INH, M6x09_GENERAL }, { 0x81, 1, "CLRB", INH, M6x09_GENERAL }, diff --git a/src/devices/cpu/m68hc16/cpu16dasm.cpp b/src/devices/cpu/m68hc16/cpu16dasm.cpp index 14fa05e8b52..7523afcbc5e 100644 --- a/src/devices/cpu/m68hc16/cpu16dasm.cpp +++ b/src/devices/cpu/m68hc16/cpu16dasm.cpp @@ -38,8 +38,8 @@ const cpu16_disassembler::opcode_info cpu16_disassembler::s_opinfo[4][256] = { "", cpu16_disassembler::mode::UND, 0 }, { "bclr", cpu16_disassembler::mode::BIT, 0 }, { "bset", cpu16_disassembler::mode::BIT, 0 }, - { "brclr", cpu16_disassembler::mode::BIT, 0 }, - { "brset", cpu16_disassembler::mode::BIT, 0 }, + { "brclr", cpu16_disassembler::mode::BIT, STEP_COND }, + { "brset", cpu16_disassembler::mode::BIT, STEP_COND }, { "rol", cpu16_disassembler::mode::IND, 0 }, { "asr", cpu16_disassembler::mode::IND, 0 }, { "ror", cpu16_disassembler::mode::IND, 0 }, @@ -56,8 +56,8 @@ const cpu16_disassembler::opcode_info cpu16_disassembler::s_opinfo[4][256] = { "", cpu16_disassembler::mode::UND, 0 }, // actually prebyte for page 1 { "bclr", cpu16_disassembler::mode::BIT, 0 }, { "bset", cpu16_disassembler::mode::BIT, 0 }, - { "brclr", cpu16_disassembler::mode::BIT, 0 }, - { "brset", cpu16_disassembler::mode::BIT, 0 }, + { "brclr", cpu16_disassembler::mode::BIT, STEP_COND }, + { "brset", cpu16_disassembler::mode::BIT, STEP_COND }, { "rol", cpu16_disassembler::mode::IND, 0 }, { "asr", cpu16_disassembler::mode::IND, 0 }, { "ror", cpu16_disassembler::mode::IND, 0 }, @@ -74,8 +74,8 @@ const cpu16_disassembler::opcode_info cpu16_disassembler::s_opinfo[4][256] = { "", cpu16_disassembler::mode::UND, 0 }, // actually prebyte for page 2 { "bclr", cpu16_disassembler::mode::BIT, 0 }, { "bset", cpu16_disassembler::mode::BIT, 0 }, - { "brclr", cpu16_disassembler::mode::BIT, 0 }, - { "brset", cpu16_disassembler::mode::BIT, 0 }, + { "brclr", cpu16_disassembler::mode::BIT, STEP_COND }, + { "brset", cpu16_disassembler::mode::BIT, STEP_COND }, { "rol", cpu16_disassembler::mode::IND, 0 }, { "asr", cpu16_disassembler::mode::IND, 0 }, { "ror", cpu16_disassembler::mode::IND, 0 }, @@ -92,8 +92,8 @@ const cpu16_disassembler::opcode_info cpu16_disassembler::s_opinfo[4][256] = { "", cpu16_disassembler::mode::UND, 0 }, // actually prebyte for page 3 { "bclr", cpu16_disassembler::mode::BIT, 0 }, { "bset", cpu16_disassembler::mode::BIT, 0 }, - { "brclr", cpu16_disassembler::mode::BIT, 0 }, - { "brset", cpu16_disassembler::mode::BIT, 0 }, + { "brclr", cpu16_disassembler::mode::BIT, STEP_COND }, + { "brset", cpu16_disassembler::mode::BIT, STEP_COND }, { "aix", cpu16_disassembler::mode::IMMS, 0 }, { "aiy", cpu16_disassembler::mode::IMMS, 0 }, { "aiz", cpu16_disassembler::mode::IMMS, 0 }, @@ -183,7 +183,7 @@ const cpu16_disassembler::opcode_info cpu16_disassembler::s_opinfo[4][256] = { "cpd", cpu16_disassembler::mode::IND, 0 }, { "jsr", cpu16_disassembler::mode::IND20, STEP_OVER }, { "std", cpu16_disassembler::mode::IND, 0 }, - { "brset", cpu16_disassembler::mode::BIT, 0 }, + { "brset", cpu16_disassembler::mode::BIT, STEP_COND }, { "stx", cpu16_disassembler::mode::IND, 0 }, { "sty", cpu16_disassembler::mode::IND, 0 }, { "stz", cpu16_disassembler::mode::IND, 0 }, @@ -201,7 +201,7 @@ const cpu16_disassembler::opcode_info cpu16_disassembler::s_opinfo[4][256] = { "cpd", cpu16_disassembler::mode::IND, 0 }, { "jsr", cpu16_disassembler::mode::IND20, STEP_OVER }, { "std", cpu16_disassembler::mode::IND, 0 }, - { "brset", cpu16_disassembler::mode::BIT, 0 }, + { "brset", cpu16_disassembler::mode::BIT, STEP_COND }, { "stx", cpu16_disassembler::mode::IND, 0 }, { "sty", cpu16_disassembler::mode::IND, 0 }, { "stz", cpu16_disassembler::mode::IND, 0 }, @@ -219,7 +219,7 @@ const cpu16_disassembler::opcode_info cpu16_disassembler::s_opinfo[4][256] = { "cpd", cpu16_disassembler::mode::IND, 0 }, { "jsr", cpu16_disassembler::mode::IND20, STEP_OVER }, { "std", cpu16_disassembler::mode::IND, 0 }, - { "brset", cpu16_disassembler::mode::BIT, 0 }, + { "brset", cpu16_disassembler::mode::BIT, STEP_COND }, { "stx", cpu16_disassembler::mode::IND, 0 }, { "sty", cpu16_disassembler::mode::IND, 0 }, { "stz", cpu16_disassembler::mode::IND, 0 }, @@ -228,20 +228,20 @@ const cpu16_disassembler::opcode_info cpu16_disassembler::s_opinfo[4][256] = // BX { "bra", cpu16_disassembler::mode::REL, 0 }, { "brn", cpu16_disassembler::mode::REL, 0 }, - { "bhi", cpu16_disassembler::mode::REL, 0 }, - { "bls", cpu16_disassembler::mode::REL, 0 }, - { "bcc", cpu16_disassembler::mode::REL, 0 }, - { "bcs", cpu16_disassembler::mode::REL, 0 }, - { "bne", cpu16_disassembler::mode::REL, 0 }, - { "beq", cpu16_disassembler::mode::REL, 0 }, - { "bvc", cpu16_disassembler::mode::REL, 0 }, - { "bvs", cpu16_disassembler::mode::REL, 0 }, - { "bpl", cpu16_disassembler::mode::REL, 0 }, - { "bmi", cpu16_disassembler::mode::REL, 0 }, - { "bge", cpu16_disassembler::mode::REL, 0 }, - { "blt", cpu16_disassembler::mode::REL, 0 }, - { "bgt", cpu16_disassembler::mode::REL, 0 }, - { "ble", cpu16_disassembler::mode::REL, 0 }, + { "bhi", cpu16_disassembler::mode::REL, STEP_COND }, + { "bls", cpu16_disassembler::mode::REL, STEP_COND }, + { "bcc", cpu16_disassembler::mode::REL, STEP_COND }, + { "bcs", cpu16_disassembler::mode::REL, STEP_COND }, + { "bne", cpu16_disassembler::mode::REL, STEP_COND }, + { "beq", cpu16_disassembler::mode::REL, STEP_COND }, + { "bvc", cpu16_disassembler::mode::REL, STEP_COND }, + { "bvs", cpu16_disassembler::mode::REL, STEP_COND }, + { "bpl", cpu16_disassembler::mode::REL, STEP_COND }, + { "bmi", cpu16_disassembler::mode::REL, STEP_COND }, + { "bge", cpu16_disassembler::mode::REL, STEP_COND }, + { "blt", cpu16_disassembler::mode::REL, STEP_COND }, + { "bgt", cpu16_disassembler::mode::REL, STEP_COND }, + { "ble", cpu16_disassembler::mode::REL, STEP_COND }, // CX { "subb", cpu16_disassembler::mode::IND, 0 }, @@ -255,7 +255,7 @@ const cpu16_disassembler::opcode_info cpu16_disassembler::s_opinfo[4][256] = { "cmpb", cpu16_disassembler::mode::IND, 0 }, { "bitb", cpu16_disassembler::mode::IND, 0 }, { "stab", cpu16_disassembler::mode::IND, 0 }, - { "brclr", cpu16_disassembler::mode::BIT, 0 }, + { "brclr", cpu16_disassembler::mode::BIT, STEP_COND }, { "ldx", cpu16_disassembler::mode::IND, 0 }, { "ldy", cpu16_disassembler::mode::IND, 0 }, { "ldz", cpu16_disassembler::mode::IND, 0 }, @@ -273,7 +273,7 @@ const cpu16_disassembler::opcode_info cpu16_disassembler::s_opinfo[4][256] = { "cmpb", cpu16_disassembler::mode::IND, 0 }, { "bitb", cpu16_disassembler::mode::IND, 0 }, { "stab", cpu16_disassembler::mode::IND, 0 }, - { "brclr", cpu16_disassembler::mode::BIT, 0 }, + { "brclr", cpu16_disassembler::mode::BIT, STEP_COND }, { "ldx", cpu16_disassembler::mode::IND, 0 }, { "ldy", cpu16_disassembler::mode::IND, 0 }, { "ldz", cpu16_disassembler::mode::IND, 0 }, @@ -291,7 +291,7 @@ const cpu16_disassembler::opcode_info cpu16_disassembler::s_opinfo[4][256] = { "cmpb", cpu16_disassembler::mode::IND, 0 }, { "bitb", cpu16_disassembler::mode::IND, 0 }, { "stab", cpu16_disassembler::mode::IND, 0 }, - { "brclr", cpu16_disassembler::mode::BIT, 0 }, + { "brclr", cpu16_disassembler::mode::BIT, STEP_COND }, { "ldx", cpu16_disassembler::mode::IND, 0 }, { "ldy", cpu16_disassembler::mode::IND, 0 }, { "ldz", cpu16_disassembler::mode::IND, 0 }, diff --git a/src/devices/cpu/m88000/m88000d.cpp b/src/devices/cpu/m88000/m88000d.cpp index dec64ac757c..3ee26d53c65 100644 --- a/src/devices/cpu/m88000/m88000d.cpp +++ b/src/devices/cpu/m88000/m88000d.cpp @@ -1175,7 +1175,7 @@ offs_t m88000_disassembler::dasm_d16(std::ostream &stream, const char *mnemonic, util::stream_format(stream, ",r%d,$%08x", (inst & 0x001f0000) >> 16, pc + disp); // Set flags for optional delay slot - return 4 | SUPPORTED | (BIT(inst, 26) ? STEP_OVER | step_over_extra(1) : 0); + return 4 | SUPPORTED | STEP_COND | (BIT(inst, 26) ? step_over_extra(1) : 0); } offs_t m88000_disassembler::dasm_d26(std::ostream &stream, const char *mnemonic, u32 inst, offs_t pc) diff --git a/src/devices/cpu/mb86233/mb86233d.cpp b/src/devices/cpu/mb86233/mb86233d.cpp index 989664bebe1..ab5cf9c783d 100644 --- a/src/devices/cpu/mb86233/mb86233d.cpp +++ b/src/devices/cpu/mb86233/mb86233d.cpp @@ -259,6 +259,7 @@ std::string mb86233_disassembler::alu0_func(u32 alu) offs_t mb86233_disassembler::disassemble(std::ostream &stream, offs_t pc, const data_buffer &opcodes, const data_buffer ¶ms) { u32 opcode = opcodes.r32(pc); + offs_t flags = 0; switch((opcode >> 26) & 0x3f) { case 0x00: { // Dual move AB @@ -467,6 +468,8 @@ offs_t mb86233_disassembler::disassemble(std::ostream &stream, offs_t pc, const switch(subtype) { case 0: util::stream_format(stream, "brif %s #0x%x", condition(cond, invert), data); + if (cond != 0x16) + flags = STEP_COND; break; case 1: @@ -475,10 +478,13 @@ offs_t mb86233_disassembler::disassemble(std::ostream &stream, offs_t pc, const util::stream_format(stream, "%s", regs(opcode & 0x1f)); else util::stream_format(stream, "(%s)", memory(opcode & 0x1ff, false, false)); + if (cond != 0x16) + flags = STEP_COND; break; case 2: util::stream_format(stream, "bsif %s #0x%x", condition(cond, invert), data); + flags = STEP_OVER | (cond != 0x16 ? STEP_COND : 0); break; case 3: @@ -487,10 +493,12 @@ offs_t mb86233_disassembler::disassemble(std::ostream &stream, offs_t pc, const util::stream_format(stream, "%s", regs(opcode & 0x1f)); else util::stream_format(stream, "(%s)", memory(opcode & 0x1ff, false, false)); + flags = STEP_OVER | (cond != 0x16 ? STEP_COND : 0); break; case 5: util::stream_format(stream, "rtif %s", condition(cond, invert)); + flags = STEP_OUT | (cond != 0x16 ? STEP_COND : 0); break; case 6: @@ -499,6 +507,7 @@ offs_t mb86233_disassembler::disassemble(std::ostream &stream, offs_t pc, const case 7: util::stream_format(stream, "iret"); + flags = STEP_OUT; break; default: @@ -513,7 +522,7 @@ offs_t mb86233_disassembler::disassemble(std::ostream &stream, offs_t pc, const break; } - return 1 | SUPPORTED; + return 1 | flags | SUPPORTED; } u32 mb86233_disassembler::opcode_alignment() const diff --git a/src/devices/cpu/mb86235/mb86235d.cpp b/src/devices/cpu/mb86235/mb86235d.cpp index 7c361b44b1f..6c6d176575d 100644 --- a/src/devices/cpu/mb86235/mb86235d.cpp +++ b/src/devices/cpu/mb86235/mb86235d.cpp @@ -219,7 +219,7 @@ void mb86235_disassembler::dasm_alu_mul(std::ostream &stream, uint64_t opcode, b } } -void mb86235_disassembler::dasm_control(std::ostream &stream, uint32_t pc, uint64_t opcode) +offs_t mb86235_disassembler::dasm_control(std::ostream &stream, uint32_t pc, uint64_t opcode) { int ef1 = (opcode >> 16) & 0x3f; int ef2 = opcode & 0xffff; @@ -228,6 +228,8 @@ void mb86235_disassembler::dasm_control(std::ostream &stream, uint32_t pc, uint6 int rel12 = (opcode & 0x800) ? (0xfffff000 | (opcode & 0xfff)) : (opcode & 0xfff); + offs_t flags = 0; + switch (cop) { case 0x00: stream << "NOP"; @@ -281,12 +283,15 @@ void mb86235_disassembler::dasm_control(std::ostream &stream, uint32_t pc, uint6 break; case 0x14: util::stream_format(stream, "DBBC AR%d:%d, %04X", (uint32_t)((opcode >> 13) & 7), (uint32_t)((opcode >> 16) & 0xf), pc + rel12); + flags = STEP_COND | step_over_extra(1); break; case 0x15: util::stream_format(stream, "DBBS AR%d:%d, %04X", (uint32_t)((opcode >> 13) & 7), (uint32_t)((opcode >> 16) & 0xf), pc + rel12); + flags = STEP_COND | step_over_extra(1); break; case 0x1b: stream << "DRET"; + flags = STEP_OUT | step_over_extra(1); break; case 0x10: // DBcc @@ -297,17 +302,32 @@ void mb86235_disassembler::dasm_control(std::ostream &stream, uint32_t pc, uint6 case 0x12: // DJMP { if (cop == 0x10) + { util::stream_format(stream, "%s ", db_mnemonic[ef1]); + flags = STEP_COND | step_over_extra(1); + } else if (cop == 0x11) + { util::stream_format(stream, "%s ", dbn_mnemonic[ef1]); + flags = STEP_COND | step_over_extra(1); + } else if (cop == 0x18) + { util::stream_format(stream, "%s ", dc_mnemonic[ef1]); + flags = STEP_OVER | STEP_COND | step_over_extra(1); + } else if (cop == 0x19) + { util::stream_format(stream, "%s ", dcn_mnemonic[ef1]); + flags = STEP_OVER | STEP_COND | step_over_extra(1); + } else if (cop == 0x12) stream << "DJMP "; else if (cop == 0x1a) + { stream << "DCALL "; + flags = STEP_OVER | step_over_extra(1); + } switch ((opcode >> 12) & 0xf) { @@ -332,6 +352,8 @@ void mb86235_disassembler::dasm_control(std::ostream &stream, uint32_t pc, uint6 break; } } + + return flags; } void mb86235_disassembler::dasm_double_xfer1(std::ostream &stream, uint64_t opcode) @@ -690,8 +712,7 @@ offs_t mb86235_disassembler::disassemble(std::ostream &stream, offs_t pc, const case 2: // ALU / MUL / control dasm_alu_mul(stream, opcode, true); stream << " : "; - dasm_control(stream, pc, opcode); - break; + return 1 | dasm_control(stream, pc, opcode) | SUPPORTED; case 4: // ALU or MUL / double transfer (type 2) dasm_alu_mul(stream, opcode, false); stream << " : "; @@ -705,8 +726,7 @@ offs_t mb86235_disassembler::disassemble(std::ostream &stream, offs_t pc, const case 6: // ALU or MUL / control dasm_alu_mul(stream, opcode, false); stream << " : "; - dasm_control(stream, pc, opcode); - break; + return 1 | dasm_control(stream, pc, opcode) | SUPPORTED; case 7: // transfer (type 3) dasm_xfer3(stream, opcode); break; diff --git a/src/devices/cpu/mb86235/mb86235d.h b/src/devices/cpu/mb86235/mb86235d.h index d3f8d2150e9..8cc4b90b2db 100644 --- a/src/devices/cpu/mb86235/mb86235d.h +++ b/src/devices/cpu/mb86235/mb86235d.h @@ -29,7 +29,7 @@ private: void dasm_ea(std::ostream &stream, int md, int arx, int ary, int disp); void dasm_alu_mul(std::ostream &stream, uint64_t opcode, bool twoop); - void dasm_control(std::ostream &stream, uint32_t pc, uint64_t opcode); + offs_t dasm_control(std::ostream &stream, uint32_t pc, uint64_t opcode); void dasm_double_xfer1(std::ostream &stream, uint64_t opcode); void dasm_xfer1(std::ostream &stream, uint64_t opcode); void dasm_double_xfer2_field(std::ostream &stream, int sd, bool isbbus, uint32_t field); diff --git a/src/devices/cpu/mc68hc11/hc11dasm.cpp b/src/devices/cpu/mc68hc11/hc11dasm.cpp index 48068929b52..f5b6a16657a 100644 --- a/src/devices/cpu/mc68hc11/hc11dasm.cpp +++ b/src/devices/cpu/mc68hc11/hc11dasm.cpp @@ -1151,6 +1151,8 @@ offs_t hc11_disassembler::disassemble(std::ostream &stream, offs_t pc, const dat flags = STEP_OVER; else if (!strcmp(op_table->mnemonic, "rts") || !strcmp(op_table->mnemonic, "rti")) flags = STEP_OUT; + else if ((opcode >= 0x22 && opcode < 0x30) || !strcmp(op_table->mnemonic, "brset") || !strcmp(op_table->mnemonic, "brclr")) + flags = STEP_COND; switch(op_table->address_mode) { diff --git a/src/devices/cpu/mcs40/mcs40dasm.cpp b/src/devices/cpu/mcs40/mcs40dasm.cpp index d0afd6e99a4..c7fdb44621d 100644 --- a/src/devices/cpu/mcs40/mcs40dasm.cpp +++ b/src/devices/cpu/mcs40/mcs40dasm.cpp @@ -119,10 +119,12 @@ offs_t mcs40_disassembler::disassemble(std::ostream &stream, offs_t pc, const da offs_t flags(0U); if (format::ILL != desc.m_format) { - if (0x50U == (opcode & 0xf0U)) // JMS + if (0x50 == (opcode & 0xf0)) // JMS flags = STEP_OVER; else if ((0xc0 == (opcode & 0xf0)) || (0x02 == opcode)) // BBL/BBS flags = STEP_OUT; + else if (0x10 == (opcode & 0xf0) || 0x70 == (opcode & 0xf0)) // JCN/ISZ + flags = STEP_COND; } return (npc - pc) | flags | SUPPORTED; diff --git a/src/devices/cpu/mcs48/mcs48dsm.cpp b/src/devices/cpu/mcs48/mcs48dsm.cpp index 2f8363e3926..3434be06940 100644 --- a/src/devices/cpu/mcs48/mcs48dsm.cpp +++ b/src/devices/cpu/mcs48/mcs48dsm.cpp @@ -67,14 +67,17 @@ offs_t mcs48_disassembler::disassemble(std::ostream &stream, offs_t pc, const da case 0x10: util::stream_format(stream, "inc @r0"); break; case 0x11: util::stream_format(stream, "inc @r1"); break; case 0x12: if (!m_i802x) + { util::stream_format(stream, "jb0 $%03X", ((pc + 1) & 0x700) | params.r8(cpc++)); + flags = STEP_COND; + } else util::stream_format(stream, "illegal"); break; case 0x13: util::stream_format(stream, "addc a,#$%02X", params.r8(cpc++)); break; case 0x14: util::stream_format(stream, "call $0%02X", params.r8(cpc++)); flags = STEP_OVER; break; case 0x15: util::stream_format(stream, "dis i"); break; - case 0x16: util::stream_format(stream, "jtf $%03X", ((pc + 1) & 0x700) | params.r8(cpc++)); break; + case 0x16: util::stream_format(stream, "jtf $%03X", ((pc + 1) & 0x700) | params.r8(cpc++)); flags = STEP_COND; break; case 0x17: util::stream_format(stream, "inc a"); break; case 0x18: util::stream_format(stream, "inc r0"); break; case 0x19: util::stream_format(stream, "inc r1"); break; @@ -94,7 +97,7 @@ offs_t mcs48_disassembler::disassemble(std::ostream &stream, offs_t pc, const da case 0x23: util::stream_format(stream, "mov a,#$%02X", params.r8(cpc++)); break; case 0x24: util::stream_format(stream, "jmp $1%02X", params.r8(cpc++)); break; case 0x25: util::stream_format(stream, "en tcnti"); break; - case 0x26: util::stream_format(stream, "jnt0 $%03X", ((pc + 1) & 0x700) | params.r8(cpc++)); break; + case 0x26: util::stream_format(stream, "jnt0 $%03X", ((pc + 1) & 0x700) | params.r8(cpc++)); flags = STEP_COND; break; case 0x27: util::stream_format(stream, "clr a"); break; case 0x28: util::stream_format(stream, "xch a,r0"); break; case 0x29: util::stream_format(stream, "xch a,r1"); break; @@ -107,13 +110,16 @@ offs_t mcs48_disassembler::disassemble(std::ostream &stream, offs_t pc, const da case 0x30: util::stream_format(stream, "xchd a,@r0"); break; case 0x31: util::stream_format(stream, "xchd a,@r1"); break; case 0x32: if (!m_i802x) + { util::stream_format(stream, "jb1 $%03X", ((pc + 1) & 0x700) | params.r8(cpc++)); + flags = STEP_COND; + } else util::stream_format(stream, "illegal"); break; case 0x34: util::stream_format(stream, "call $1%02X", params.r8(cpc++)); flags = STEP_OVER; break; case 0x35: util::stream_format(stream, "dis tcnti"); break; - case 0x36: util::stream_format(stream, "jt0 $%03X", ((pc + 1) & 0x700) | params.r8(cpc++)); break; + case 0x36: util::stream_format(stream, "jt0 $%03X", ((pc + 1) & 0x700) | params.r8(cpc++)); flags = STEP_COND; break; case 0x37: util::stream_format(stream, "cpl a"); break; case 0x39: util::stream_format(stream, "outl p1,a"); break; case 0x3a: util::stream_format(stream, "outl p2,a"); break; @@ -127,7 +133,7 @@ offs_t mcs48_disassembler::disassemble(std::ostream &stream, offs_t pc, const da case 0x43: util::stream_format(stream, "orl a,#$%02X", params.r8(cpc++)); break; case 0x44: util::stream_format(stream, "jmp $2%02X", params.r8(cpc++)); break; case 0x45: util::stream_format(stream, "strt cnt"); break; - case 0x46: util::stream_format(stream, "jnt1 $%03X", ((pc + 1) & 0x700) | params.r8(cpc++)); break; + case 0x46: util::stream_format(stream, "jnt1 $%03X", ((pc + 1) & 0x700) | params.r8(cpc++)); flags = STEP_COND; break; case 0x47: util::stream_format(stream, "swap a"); break; case 0x48: util::stream_format(stream, "orl a,r0"); break; case 0x49: util::stream_format(stream, "orl a,r1"); break; @@ -140,14 +146,17 @@ offs_t mcs48_disassembler::disassemble(std::ostream &stream, offs_t pc, const da case 0x50: util::stream_format(stream, "anl a,@r0"); break; case 0x51: util::stream_format(stream, "anl a,@r1"); break; case 0x52: if (!m_i802x) + { util::stream_format(stream, "jb2 $%03X", ((pc + 1) & 0x700) | params.r8(cpc++)); + flags = STEP_COND; + } else util::stream_format(stream, "illegal"); break; case 0x53: util::stream_format(stream, "anl a,#$%02X", params.r8(cpc++)); break; case 0x54: util::stream_format(stream, "call $2%02X", params.r8(cpc++)); flags = STEP_OVER; break; case 0x55: util::stream_format(stream, "strt t"); break; - case 0x56: util::stream_format(stream, "jt1 $%03X", ((pc + 1) & 0x700) | params.r8(cpc++)); break; + case 0x56: util::stream_format(stream, "jt1 $%03X", ((pc + 1) & 0x700) | params.r8(cpc++)); flags = STEP_COND; break; case 0x57: util::stream_format(stream, "da a"); break; case 0x58: util::stream_format(stream, "anl a,r0"); break; case 0x59: util::stream_format(stream, "anl a,r1"); break; @@ -174,7 +183,10 @@ offs_t mcs48_disassembler::disassemble(std::ostream &stream, offs_t pc, const da case 0x70: util::stream_format(stream, "addc a,@r0"); break; case 0x71: util::stream_format(stream, "addc a,@r1"); break; case 0x72: if (!m_i802x) + { util::stream_format(stream, "jb3 $%03X", ((pc + 1) & 0x700) | params.r8(cpc++)); + flags = STEP_COND; + } else util::stream_format(stream, "illegal"); break; @@ -185,7 +197,10 @@ offs_t mcs48_disassembler::disassemble(std::ostream &stream, offs_t pc, const da util::stream_format(stream, "illegal"); break; case 0x76: if (!m_i802x) + { util::stream_format(stream, "jf1 $%03X", ((pc + 1) & 0x700) | params.r8(cpc++)); + flags = STEP_COND; + } else util::stream_format(stream, "illegal"); break; @@ -219,10 +234,14 @@ offs_t mcs48_disassembler::disassemble(std::ostream &stream, offs_t pc, const da break; case 0x86: if (m_i802x) util::stream_format(stream, "illegal"); - else if (!m_upi41) - util::stream_format(stream, "jni $%03X", ((pc + 1) & 0x700) | params.r8(cpc++)); else - util::stream_format(stream, "jobf $%03X", ((pc + 1) & 0x700) | params.r8(cpc++)); + { + if (!m_upi41) + util::stream_format(stream, "jni $%03X", ((pc + 1) & 0x700) | params.r8(cpc++)); + else + util::stream_format(stream, "jobf $%03X", ((pc + 1) & 0x700) | params.r8(cpc++)); + flags = STEP_COND; + } break; case 0x88: if (!m_upi41 && !m_i802x) util::stream_format(stream, "orl bus,#$%02X", params.r8(cpc++)); @@ -256,7 +275,10 @@ offs_t mcs48_disassembler::disassemble(std::ostream &stream, offs_t pc, const da util::stream_format(stream, "illegal"); break; case 0x92: if (!m_i802x) + { util::stream_format(stream, "jb4 $%03X", ((pc + 1) & 0x700) | params.r8(cpc++)); + flags = STEP_COND; + } else util::stream_format(stream, "illegal"); break; @@ -272,7 +294,7 @@ offs_t mcs48_disassembler::disassemble(std::ostream &stream, offs_t pc, const da else util::stream_format(stream, "sel an1"); break; - case 0x96: util::stream_format(stream, "jnz $%03X", ((pc + 1) & 0x700) | params.r8(cpc++)); break; + case 0x96: util::stream_format(stream, "jnz $%03X", ((pc + 1) & 0x700) | params.r8(cpc++)); flags = STEP_COND; break; case 0x97: util::stream_format(stream, "clr c"); break; case 0x98: if (!m_upi41 && !m_i802x) util::stream_format(stream, "anl bus,#$%02X", params.r8(cpc++)); @@ -314,7 +336,10 @@ offs_t mcs48_disassembler::disassemble(std::ostream &stream, offs_t pc, const da case 0xb0: util::stream_format(stream, "mov @r0,#$%02X", params.r8(cpc++)); break; case 0xb1: util::stream_format(stream, "mov @r1,#$%02X", params.r8(cpc++)); break; case 0xb2: if (!m_i802x) + { util::stream_format(stream, "jb5 $%03X", ((pc + 1) & 0x700) | params.r8(cpc++)); + flags = STEP_COND; + } else util::stream_format(stream, "illegal"); break; @@ -326,7 +351,10 @@ offs_t mcs48_disassembler::disassemble(std::ostream &stream, offs_t pc, const da util::stream_format(stream, "illegal"); break; case 0xb6: if (!m_i802x) + { util::stream_format(stream, "jf0 $%03X", ((pc + 1) & 0x700) | params.r8(cpc++)); + flags = STEP_COND; + } else util::stream_format(stream, "illegal"); break; @@ -344,7 +372,7 @@ offs_t mcs48_disassembler::disassemble(std::ostream &stream, offs_t pc, const da else util::stream_format(stream, "illegal"); break; - case 0xc6: util::stream_format(stream, "jz $%03X", ((pc + 1) & 0x700) | params.r8(cpc++)); break; + case 0xc6: util::stream_format(stream, "jz $%03X", ((pc + 1) & 0x700) | params.r8(cpc++)); flags = STEP_COND; break; case 0xc7: if (!m_i802x) util::stream_format(stream, "mov a,psw"); else @@ -393,7 +421,10 @@ offs_t mcs48_disassembler::disassemble(std::ostream &stream, offs_t pc, const da case 0xd0: util::stream_format(stream, "xrl a,@r0"); break; case 0xd1: util::stream_format(stream, "xrl a,@r1"); break; case 0xd2: if (!m_i802x) + { util::stream_format(stream, "jb6 $%03X", ((pc + 1) & 0x700) | params.r8(cpc++)); + flags = STEP_COND; + } else util::stream_format(stream, "illegal"); break; @@ -407,7 +438,10 @@ offs_t mcs48_disassembler::disassemble(std::ostream &stream, offs_t pc, const da case 0xd6: if (!m_upi41) util::stream_format(stream, "illegal"); else + { util::stream_format(stream, "jnibf $%03X", ((pc + 1) & 0x700) | params.r8(cpc++)); + flags = STEP_COND; + } break; case 0xd7: if (!m_i802x) util::stream_format(stream, "mov psw,a"); @@ -435,7 +469,7 @@ offs_t mcs48_disassembler::disassemble(std::ostream &stream, offs_t pc, const da else util::stream_format(stream, "en dma"); break; - case 0xe6: util::stream_format(stream, "jnc $%03X", ((pc + 1) & 0x700) | params.r8(cpc++)); break; + case 0xe6: util::stream_format(stream, "jnc $%03X", ((pc + 1) & 0x700) | params.r8(cpc++)); flags = STEP_COND; break; case 0xe7: util::stream_format(stream, "rl a"); break; case 0xe8: util::stream_format(stream, "djnz r0,$%03X", ((pc + 1) & 0x700) | params.r8(cpc++)); flags = STEP_OVER; break; case 0xe9: util::stream_format(stream, "djnz r1,$%03X", ((pc + 1) & 0x700) | params.r8(cpc++)); flags = STEP_OVER; break; @@ -448,7 +482,10 @@ offs_t mcs48_disassembler::disassemble(std::ostream &stream, offs_t pc, const da case 0xf0: util::stream_format(stream, "mov a,@r0"); break; case 0xf1: util::stream_format(stream, "mov a,@r1"); break; case 0xf2: if (!m_i802x) + { util::stream_format(stream, "jb7 $%03X", ((pc + 1) & 0x700) | params.r8(cpc++)); + flags = STEP_COND; + } else util::stream_format(stream, "illegal"); break; @@ -460,7 +497,7 @@ offs_t mcs48_disassembler::disassemble(std::ostream &stream, offs_t pc, const da else util::stream_format(stream, "en flags"); break; - case 0xf6: util::stream_format(stream, "jc $%03X", ((pc + 1) & 0x700) | params.r8(cpc++)); break; + case 0xf6: util::stream_format(stream, "jc $%03X", ((pc + 1) & 0x700) | params.r8(cpc++)); flags = STEP_COND; break; case 0xf7: util::stream_format(stream, "rlc a"); break; case 0xf8: util::stream_format(stream, "mov a,r0"); break; case 0xf9: util::stream_format(stream, "mov a,r1"); break; diff --git a/src/devices/cpu/mcs51/mcs51dasm.cpp b/src/devices/cpu/mcs51/mcs51dasm.cpp index 365ffe915cd..d1d8b9f2499 100644 --- a/src/devices/cpu/mcs51/mcs51dasm.cpp +++ b/src/devices/cpu/mcs51/mcs51dasm.cpp @@ -784,6 +784,7 @@ offs_t mcs51_disassembler::disassemble_op(std::ostream &stream, unsigned PC, off sym = get_bit_address(params.r8(PC++)); rel = params.r8(PC++); util::stream_format(stream, "jbc %s,$%04X", sym, PC + rel); + flags = STEP_COND; break; //ACALL code addr /* 1: aaa1 0001 */ @@ -846,6 +847,7 @@ offs_t mcs51_disassembler::disassemble_op(std::ostream &stream, unsigned PC, off sym = get_bit_address(params.r8(PC++)); rel = params.r8(PC++); util::stream_format(stream, "jb %s,$%04X", sym, (PC + rel)); + flags = STEP_COND; break; //RET @@ -894,6 +896,7 @@ offs_t mcs51_disassembler::disassemble_op(std::ostream &stream, unsigned PC, off sym = get_bit_address(params.r8(PC++)); rel = params.r8(PC++); util::stream_format(stream, "jnb %s,$%04X", sym, (PC + rel)); + flags = STEP_COND; break; //RETI @@ -940,6 +943,7 @@ offs_t mcs51_disassembler::disassemble_op(std::ostream &stream, unsigned PC, off case 0x40: /* 1: 0100 0000 */ rel = params.r8(PC++); util::stream_format(stream, "jc $%04X", PC + rel); + flags = STEP_COND; break; //ORL data addr, A @@ -988,6 +992,7 @@ offs_t mcs51_disassembler::disassemble_op(std::ostream &stream, unsigned PC, off case 0x50: /* 1: 0101 0000 */ rel = params.r8(PC++); util::stream_format(stream, "jnc $%04X", PC + rel); + flags = STEP_COND; break; //Unable to test @@ -1038,6 +1043,7 @@ offs_t mcs51_disassembler::disassemble_op(std::ostream &stream, unsigned PC, off case 0x60: /* 1: 0110 0000 */ rel = params.r8(PC++); util::stream_format(stream, "jz $%04X", PC + rel); + flags = STEP_COND; break; //Unable to test @@ -1087,6 +1093,7 @@ offs_t mcs51_disassembler::disassemble_op(std::ostream &stream, unsigned PC, off case 0x70: /* 1: 0111 0000 */ rel = params.r8(PC++); util::stream_format(stream, "jnz $%04X", PC + rel); + flags = STEP_COND; break; //Unable to test @@ -1302,6 +1309,7 @@ offs_t mcs51_disassembler::disassemble_op(std::ostream &stream, unsigned PC, off data = params.r8(PC++); rel = params.r8(PC++); util::stream_format(stream, "cjne a,#$%02X,$%04X", data, PC + rel); + flags = STEP_COND; break; //CJNE A, data addr, code addr @@ -1309,6 +1317,7 @@ offs_t mcs51_disassembler::disassemble_op(std::ostream &stream, unsigned PC, off sym = get_data_address(params.r8(PC++)); rel = params.r8(PC++); util::stream_format(stream, "cjne a,%s,$%04X", sym, PC + rel); + flags = STEP_COND; break; //Unable to test @@ -1318,6 +1327,7 @@ offs_t mcs51_disassembler::disassemble_op(std::ostream &stream, unsigned PC, off data = params.r8(PC++); rel = params.r8(PC++); util::stream_format(stream, "cjne @r%d,#$%02X,$%04X", op&1, data, PC + rel); + flags = STEP_COND; break; //CJNE R0 to R7, #data, code addr/* 1: 1011 1rrr */ @@ -1332,6 +1342,7 @@ offs_t mcs51_disassembler::disassemble_op(std::ostream &stream, unsigned PC, off data = params.r8(PC++); rel = params.r8(PC++); util::stream_format(stream, "cjne r%d,#$%02X,$%04X", op&7, data, PC + rel); + flags = STEP_COND; break; //PUSH data addr @@ -1408,7 +1419,7 @@ offs_t mcs51_disassembler::disassemble_op(std::ostream &stream, unsigned PC, off sym = get_data_address(params.r8(PC++)); rel = params.r8(PC++); util::stream_format(stream, "djnz %s,$%04X", sym, PC + rel); - flags = STEP_OVER; + flags = STEP_COND; break; //XCHD A, @R0/@R1 /* 1: 1101 011i */ @@ -1428,7 +1439,7 @@ offs_t mcs51_disassembler::disassemble_op(std::ostream &stream, unsigned PC, off case 0xdf: rel = params.r8(PC++); util::stream_format(stream, "djnz r%d,$%04X", op&7, (PC + rel)); - flags = STEP_OVER; + flags = STEP_COND; break; //MOVX A,@DPTR diff --git a/src/devices/cpu/mcs96/mcs96make.py b/src/devices/cpu/mcs96/mcs96make.py index 7a7f4a470d8..0acb3c2e638 100644 --- a/src/devices/cpu/mcs96/mcs96make.py +++ b/src/devices/cpu/mcs96/mcs96make.py @@ -129,6 +129,8 @@ class OpcodeList: flags = "STEP_OVER" elif opc.name == "rts": flags = "STEP_OUT" + elif opc.amode == "rel8" or opc.amode == "rrel8" or opc.amode == "brrel8" or opc.amode == "wrrel8": + flags = "STEP_COND" else: flags = "0" print("\t{ \"%s\", %s, DASM_%s, %s }," % (opc.name, alt, opc.amode, flags), file=f) diff --git a/src/devices/cpu/melps4/melps4d.cpp b/src/devices/cpu/melps4/melps4d.cpp index 0e048b265cf..4bbf307ac68 100644 --- a/src/devices/cpu/melps4/melps4d.cpp +++ b/src/devices/cpu/melps4/melps4d.cpp @@ -47,14 +47,14 @@ const uint32_t melps4_disassembler::em_flags[] = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, - 0, 0, 0, 0, 0, 0, - 0, 0, 0, 0, - 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, - 0, 0, 0, 0, 0, - 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, - 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, STEP_COND, STEP_COND, 0, 0, + 0, 0, STEP_COND, STEP_COND, + 0, 0, 0, STEP_COND, STEP_COND, 0, 0, STEP_COND, 0, 0, 0, + 0, 0, STEP_COND, STEP_COND, STEP_COND, + 0, 0, 0, 0, 0, 0, STEP_COND, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, STEP_COND, STEP_COND, 0, 0, 0, STEP_OVER, STEP_OUT, STEP_OUT, STEP_OUT, - 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, STEP_COND, 0, 0, 0, 0, 0, 0, 0, 0, STEP_COND, 0, 0, 0, 0, 0, 0, 0 }; @@ -115,7 +115,7 @@ offs_t melps4_disassembler::disassemble(std::ostream &stream, offs_t pc, const d util::stream_format(stream, "%d", param); } - return 1 | em_flags[instr] | SUPPORTED; + return 1 | (op == 0xa6 ? 0 : em_flags[instr]) | SUPPORTED; } u32 melps4_disassembler::opcode_alignment() const diff --git a/src/devices/cpu/minx/minxd.cpp b/src/devices/cpu/minx/minxd.cpp index 21fd398c782..23c10b38571 100644 --- a/src/devices/cpu/minx/minxd.cpp +++ b/src/devices/cpu/minx/minxd.cpp @@ -26,13 +26,13 @@ const char *const minx_disassembler::s_mnemonic[] = { }; const uint32_t minx_disassembler::s_flags[] = { - 0, 0, 0, 0, 0, 0, STEP_OVER, STEP_OVER, STEP_OVER, STEP_OVER, STEP_OVER, - STEP_OVER, STEP_OVER, STEP_OVER, STEP_OVER, STEP_OVER, STEP_OVER, STEP_OVER, STEP_OVER, - STEP_OVER, STEP_OVER, STEP_OVER, STEP_OVER, STEP_OVER, STEP_OVER, STEP_OVER, STEP_OVER, + 0, 0, 0, 0, 0, 0, STEP_OVER, STEP_OVER | STEP_COND, STEP_OVER | STEP_COND, STEP_OVER | STEP_COND, STEP_OVER | STEP_COND, + STEP_OVER | STEP_COND, STEP_OVER | STEP_COND, STEP_OVER | STEP_COND, STEP_OVER | STEP_COND, STEP_OVER | STEP_COND, STEP_OVER | STEP_COND, STEP_OVER | STEP_COND, STEP_OVER | STEP_COND, + STEP_OVER | STEP_COND, STEP_OVER | STEP_COND, STEP_OVER | STEP_COND, STEP_OVER | STEP_COND, STEP_OVER | STEP_COND, STEP_OVER | STEP_COND, STEP_OVER | STEP_COND, STEP_OVER | STEP_COND, 0, 0, 0, 0, 0, STEP_OVER, 0, STEP_OVER, - 0, 0, 0, 0, 0, 0, 0, 0, - 0, 0, 0, 0, 0, 0, 0, 0, - 0, 0, 0, 0, 0, 0, 0, 0, + STEP_COND, STEP_COND, STEP_COND, STEP_COND, STEP_COND, STEP_COND, STEP_COND, 0, + STEP_COND, STEP_COND, STEP_COND, STEP_COND, STEP_COND, STEP_COND, STEP_COND, STEP_COND, + STEP_COND, STEP_COND, STEP_COND, STEP_COND, STEP_COND, STEP_COND, STEP_COND, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, STEP_OUT, STEP_OUT, STEP_OUT, 0, 0, 0, 0, 0, 0, 0, 0, 0, diff --git a/src/devices/cpu/mips/mips1dsm.cpp b/src/devices/cpu/mips/mips1dsm.cpp index 72429ca8c03..8fd3af7b5e9 100644 --- a/src/devices/cpu/mips/mips1dsm.cpp +++ b/src/devices/cpu/mips/mips1dsm.cpp @@ -105,8 +105,8 @@ uint32_t mips1_disassembler::dasm_cop(uint32_t pc, int cop, uint32_t op, std::os case 0x08: /* BC */ switch (rt) { - case 0x00: util::stream_format(stream, "bc%df $%08x", cop, pc + 4 + ((int16_t)op << 2)); break; - case 0x01: util::stream_format(stream, "bc%dt $%08x", cop, pc + 4 + ((int16_t)op << 2)); break; + case 0x00: util::stream_format(stream, "bc%df $%08x", cop, pc + 4 + ((int16_t)op << 2)); flags = STEP_COND | step_over_extra(1); break; + case 0x01: util::stream_format(stream, "bc%dt $%08x", cop, pc + 4 + ((int16_t)op << 2)); flags = STEP_COND | step_over_extra(1); break; case 0x02: util::stream_format(stream, "bc%dfl [invalid]", cop); break; case 0x03: util::stream_format(stream, "bc%dtl [invalid]", cop); break; default: util::stream_format(stream, "dc.l $%08x [invalid]", op); break; @@ -176,10 +176,10 @@ uint32_t mips1_disassembler::dasm_cop1(uint32_t pc, uint32_t op, std::ostream &s case 0x08: /* BC */ switch (rt & 3) { - case 0x00: util::stream_format(stream, "bc1f $%08x,%d", pc + 4 + ((int16_t)op << 2), (op >> 18) & 7); break; - case 0x01: util::stream_format(stream, "bc1t $%08x,%d", pc + 4 + ((int16_t)op << 2), (op >> 18) & 7); break; - case 0x02: util::stream_format(stream, "bc1fl $%08x,%d", pc + 4 + ((int16_t)op << 2), (op >> 18) & 7); flags = STEP_OVER | step_over_extra(1); break; - case 0x03: util::stream_format(stream, "bc1tl $%08x,%d", pc + 4 + ((int16_t)op << 2), (op >> 18) & 7); flags = STEP_OVER | step_over_extra(1); break; + case 0x00: util::stream_format(stream, "bc1f $%08x,%d", pc + 4 + ((int16_t)op << 2), (op >> 18) & 7); flags = STEP_COND | step_over_extra(1); break; + case 0x01: util::stream_format(stream, "bc1t $%08x,%d", pc + 4 + ((int16_t)op << 2), (op >> 18) & 7); flags = STEP_COND | step_over_extra(1); break; + case 0x02: util::stream_format(stream, "bc1fl $%08x,%d", pc + 4 + ((int16_t)op << 2), (op >> 18) & 7); flags = STEP_COND | step_over_extra(1); break; + case 0x03: util::stream_format(stream, "bc1tl $%08x,%d", pc + 4 + ((int16_t)op << 2), (op >> 18) & 7); flags = STEP_COND | step_over_extra(1); break; } break; default: /* COP */ @@ -298,8 +298,8 @@ offs_t mips1_disassembler::disassemble(std::ostream &stream, offs_t pc, const da case 0x01: /* REGIMM */ switch ((op >> 16) & 31) { - case 0x00: util::stream_format(stream, "bltz %s,$%08x", reg[rs], pc + 4 + ((int16_t)op << 2)); break; - case 0x01: util::stream_format(stream, "bgez %s,$%08x", reg[rs], pc + 4 + ((int16_t)op << 2)); break; + case 0x00: util::stream_format(stream, "bltz %s,$%08x", reg[rs], pc + 4 + ((int16_t)op << 2)); if (rs != 0) flags = STEP_COND | step_over_extra(1); break; + case 0x01: util::stream_format(stream, "bgez %s,$%08x", reg[rs], pc + 4 + ((int16_t)op << 2)); if (rs != 0) flags = STEP_COND | step_over_extra(1); break; case 0x02: util::stream_format(stream, "bltzl [invalid]"); break; case 0x03: util::stream_format(stream, "bgezl [invalid]"); break; case 0x08: util::stream_format(stream, "tgei [invalid]"); break; @@ -308,8 +308,8 @@ offs_t mips1_disassembler::disassemble(std::ostream &stream, offs_t pc, const da case 0x0b: util::stream_format(stream, "tltiu [invalid]"); break; case 0x0c: util::stream_format(stream, "teqi [invalid]"); break; case 0x0e: util::stream_format(stream, "tnei [invalid]"); break; - case 0x10: util::stream_format(stream, "bltzal %s,$%08x", reg[rs], pc + 4 + ((int16_t)op << 2)); flags = STEP_OVER | step_over_extra(1); break; - case 0x11: util::stream_format(stream, "bgezal %s,$%08x", reg[rs], pc + 4 + ((int16_t)op << 2)); flags = STEP_OVER | step_over_extra(1); break; + case 0x10: util::stream_format(stream, "bltzal %s,$%08x", reg[rs], pc + 4 + ((int16_t)op << 2)); if (rs != 0) flags = STEP_OVER | STEP_COND | step_over_extra(1); break; + case 0x11: util::stream_format(stream, "bgezal %s,$%08x", reg[rs], pc + 4 + ((int16_t)op << 2)); flags = STEP_OVER | (rs != 0 ? STEP_COND : 0) | step_over_extra(1); break; case 0x12: util::stream_format(stream, "bltzall [invalid]"); break; case 0x13: util::stream_format(stream, "bgezall [invalid]"); break; default: util::stream_format(stream, "dc.l $%08x [invalid]", op); break; @@ -321,11 +321,14 @@ offs_t mips1_disassembler::disassemble(std::ostream &stream, offs_t pc, const da case 0x04: if (rs == 0 && rt == 0) util::stream_format(stream, "b $%08x", pc + 4 + ((int16_t)op << 2)); else + { util::stream_format(stream, "beq %s,%s,$%08x", reg[rs], reg[rt], pc + 4 + ((int16_t)op << 2)); + flags = STEP_COND | step_over_extra(1); + } break; - case 0x05: util::stream_format(stream, "bne %s,%s,$%08x", reg[rs], reg[rt], pc + 4 + ((int16_t)op << 2));break; - case 0x06: util::stream_format(stream, "blez %s,$%08x", reg[rs], pc + 4 + ((int16_t)op << 2)); break; - case 0x07: util::stream_format(stream, "bgtz %s,$%08x", reg[rs], pc + 4 + ((int16_t)op << 2)); break; + case 0x05: util::stream_format(stream, "bne %s,%s,$%08x", reg[rs], reg[rt], pc + 4 + ((int16_t)op << 2)); flags = STEP_COND | step_over_extra(1); break; + case 0x06: util::stream_format(stream, "blez %s,$%08x", reg[rs], pc + 4 + ((int16_t)op << 2)); flags = STEP_COND | step_over_extra(1); break; + case 0x07: util::stream_format(stream, "bgtz %s,$%08x", reg[rs], pc + 4 + ((int16_t)op << 2)); flags = STEP_COND | step_over_extra(1); break; case 0x08: util::stream_format(stream, "addi %s,%s,%s", reg[rt], reg[rs], signed_16bit(op)); break; case 0x09: util::stream_format(stream, "addiu %s,%s,%s", reg[rt], reg[rs], signed_16bit(op)); break; case 0x0a: util::stream_format(stream, "slti %s,%s,%s", reg[rt], reg[rs], signed_16bit(op)); break; diff --git a/src/devices/cpu/mips/mips3dsm.cpp b/src/devices/cpu/mips/mips3dsm.cpp index 9e1113819b7..82a402291ec 100644 --- a/src/devices/cpu/mips/mips3dsm.cpp +++ b/src/devices/cpu/mips/mips3dsm.cpp @@ -147,8 +147,8 @@ uint32_t mips3_disassembler::dasm_cop0(uint32_t pc, uint32_t op, std::ostream &s case 0x08: /* BC */ switch (rt) { - case 0x00: util::stream_format(stream, "bc0f $%08x", pc + 4 + ((int16_t)op << 2)); break; - case 0x01: util::stream_format(stream, "bc0t $%08x", pc + 4 + ((int16_t)op << 2)); break; + case 0x00: util::stream_format(stream, "bc0f $%08x", pc + 4 + ((int16_t)op << 2)); flags = STEP_COND | step_over_extra(1); break; + case 0x01: util::stream_format(stream, "bc0t $%08x", pc + 4 + ((int16_t)op << 2)); flags = STEP_COND | step_over_extra(1); break; case 0x02: util::stream_format(stream, "bc0fl [invalid]"); break; case 0x03: util::stream_format(stream, "bc0tl [invalid]"); break; default: util::stream_format(stream, "dc.l $%08x [invalid]", op); break; @@ -218,10 +218,10 @@ uint32_t mips3_disassembler::dasm_cop1(uint32_t pc, uint32_t op, std::ostream &s case 0x08: /* BC */ switch (rt & 3) { - case 0x00: util::stream_format(stream, "bc1f $%08x,%d", pc + 4 + ((int16_t)op << 2), (op >> 18) & 7); break; - case 0x01: util::stream_format(stream, "bc1t $%08x,%d", pc + 4 + ((int16_t)op << 2), (op >> 18) & 7); break; - case 0x02: util::stream_format(stream, "bc1fl $%08x,%d", pc + 4 + ((int16_t)op << 2), (op >> 18) & 7); flags = STEP_OVER | step_over_extra(1); break; - case 0x03: util::stream_format(stream, "bc1tl $%08x,%d", pc + 4 + ((int16_t)op << 2), (op >> 18) & 7); flags = STEP_OVER | step_over_extra(1); break; + case 0x00: util::stream_format(stream, "bc1f $%08x,%d", pc + 4 + ((int16_t)op << 2), (op >> 18) & 7); flags = STEP_COND | step_over_extra(1); break; + case 0x01: util::stream_format(stream, "bc1t $%08x,%d", pc + 4 + ((int16_t)op << 2), (op >> 18) & 7); flags = STEP_COND | step_over_extra(1); break; + case 0x02: util::stream_format(stream, "bc1fl $%08x,%d", pc + 4 + ((int16_t)op << 2), (op >> 18) & 7); flags = STEP_COND | step_over_extra(1); break; + case 0x03: util::stream_format(stream, "bc1tl $%08x,%d", pc + 4 + ((int16_t)op << 2), (op >> 18) & 7); flags = STEP_COND | step_over_extra(1); break; } break; default: /* COP */ @@ -358,8 +358,8 @@ uint32_t mips3_disassembler::dasm_cop2(uint32_t pc, uint32_t op, std::ostream &s case 0x08: /* BC */ switch (rt) { - case 0x00: util::stream_format(stream, "bc2f $%08x", pc + 4 + ((int16_t)op << 2)); break; - case 0x01: util::stream_format(stream, "bc2t $%08x", pc + 4 + ((int16_t)op << 2)); break; + case 0x00: util::stream_format(stream, "bc2f $%08x", pc + 4 + ((int16_t)op << 2)); flags = STEP_COND | step_over_extra(1); break; + case 0x01: util::stream_format(stream, "bc2t $%08x", pc + 4 + ((int16_t)op << 2)); flags = STEP_COND | step_over_extra(1); break; case 0x02: util::stream_format(stream, "bc2fl [invalid]"); break; case 0x03: util::stream_format(stream, "bc2tl [invalid]"); break; default: util::stream_format(stream, "dc.l $%08x [invalid]", op); break; @@ -954,20 +954,20 @@ offs_t mips3_disassembler::dasm_one(std::ostream &stream, offs_t pc, u32 op) case 0x01: /* REGIMM */ switch ((op >> 16) & 31) { - case 0x00: util::stream_format(stream, "bltz %s,$%08x", reg[rs], pc + 4 + ((int16_t)op << 2)); break; - case 0x01: util::stream_format(stream, "bgez %s,$%08x", reg[rs], pc + 4 + ((int16_t)op << 2)); break; - case 0x02: util::stream_format(stream, "bltzl %s,$%08x", reg[rs], pc + 4 + ((int16_t)op << 2)); break; - case 0x03: util::stream_format(stream, "bgezl %s,$%08x", reg[rs], pc + 4 + ((int16_t)op << 2)); break; - case 0x08: util::stream_format(stream, "tgei %s,%s", reg[rs], signed_16bit(op)); flags = STEP_OVER; break; - case 0x09: util::stream_format(stream, "tgeiu %s,%s", reg[rs], signed_16bit(op)); flags = STEP_OVER; break; - case 0x0a: util::stream_format(stream, "tlti %s,%s", reg[rs], signed_16bit(op)); flags = STEP_OVER; break; - case 0x0b: util::stream_format(stream, "tltiu %s,%s", reg[rs], signed_16bit(op)); flags = STEP_OVER; break; - case 0x0c: util::stream_format(stream, "teqi %s,%s", reg[rs], signed_16bit(op)); flags = STEP_OVER; break; - case 0x0e: util::stream_format(stream, "tnei %s,%s", reg[rs], signed_16bit(op)); flags = STEP_OVER; break; - case 0x10: util::stream_format(stream, "bltzal %s,$%08x", reg[rs], pc + 4 + ((int16_t)op << 2)); flags = STEP_OVER | step_over_extra(1); break; - case 0x11: util::stream_format(stream, "bgezal %s,$%08x", reg[rs], pc + 4 + ((int16_t)op << 2)); flags = STEP_OVER | step_over_extra(1); break; - case 0x12: util::stream_format(stream, "bltzall %s,$%08x", reg[rs], pc + 4 + ((int16_t)op << 2)); flags = STEP_OVER | step_over_extra(1); break; - case 0x13: util::stream_format(stream, "bgezall %s,$%08x", reg[rs], pc + 4 + ((int16_t)op << 2)); flags = STEP_OVER | step_over_extra(1); break; + case 0x00: util::stream_format(stream, "bltz %s,$%08x", reg[rs], pc + 4 + ((int16_t)op << 2)); if (rs != 0) flags = STEP_COND | step_over_extra(1); break; + case 0x01: util::stream_format(stream, "bgez %s,$%08x", reg[rs], pc + 4 + ((int16_t)op << 2)); if (rs != 0) flags = STEP_COND | step_over_extra(1); break; + case 0x02: util::stream_format(stream, "bltzl %s,$%08x", reg[rs], pc + 4 + ((int16_t)op << 2)); if (rs != 0) flags = STEP_COND | step_over_extra(1); break; + case 0x03: util::stream_format(stream, "bgezl %s,$%08x", reg[rs], pc + 4 + ((int16_t)op << 2)); if (rs != 0) flags = STEP_COND | step_over_extra(1); break; + case 0x08: util::stream_format(stream, "tgei %s,%s", reg[rs], signed_16bit(op)); flags = STEP_OVER | STEP_COND; break; + case 0x09: util::stream_format(stream, "tgeiu %s,%s", reg[rs], signed_16bit(op)); flags = STEP_OVER | STEP_COND; break; + case 0x0a: util::stream_format(stream, "tlti %s,%s", reg[rs], signed_16bit(op)); flags = STEP_OVER | STEP_COND; break; + case 0x0b: util::stream_format(stream, "tltiu %s,%s", reg[rs], signed_16bit(op)); flags = STEP_OVER | STEP_COND; break; + case 0x0c: util::stream_format(stream, "teqi %s,%s", reg[rs], signed_16bit(op)); flags = STEP_OVER | STEP_COND; break; + case 0x0e: util::stream_format(stream, "tnei %s,%s", reg[rs], signed_16bit(op)); flags = STEP_OVER | STEP_COND; break; + case 0x10: util::stream_format(stream, "bltzal %s,$%08x", reg[rs], pc + 4 + ((int16_t)op << 2)); if (rs != 0) flags = STEP_OVER | STEP_COND | step_over_extra(1); break; + case 0x11: util::stream_format(stream, "bgezal %s,$%08x", reg[rs], pc + 4 + ((int16_t)op << 2)); flags = STEP_OVER | (rs != 0 ? STEP_COND : 0) | step_over_extra(1); break; + case 0x12: util::stream_format(stream, "bltzall %s,$%08x", reg[rs], pc + 4 + ((int16_t)op << 2)); if (rs != 0) flags = STEP_OVER | STEP_COND | step_over_extra(1); break; + case 0x13: util::stream_format(stream, "bgezall %s,$%08x", reg[rs], pc + 4 + ((int16_t)op << 2)); flags = STEP_OVER | (rs != 0 ? STEP_COND : 0) | step_over_extra(1); break; default: flags = dasm_extra_regimm(pc, op, stream); break; } break; diff --git a/src/devices/cpu/mk1/mk1dasm.cpp b/src/devices/cpu/mk1/mk1dasm.cpp index 4e6c4157dec..6b190c29d84 100644 --- a/src/devices/cpu/mk1/mk1dasm.cpp +++ b/src/devices/cpu/mk1/mk1dasm.cpp @@ -48,7 +48,7 @@ offs_t mk1_disassembler::disassemble(std::ostream &stream, offs_t pc, const mk1_ // Conditional skip const u8 disp = BIT(uop, 0, 4); util::stream_format(stream, "%s %d ; $%03x", s_skips[BIT(uop, 4, 2)], disp, (pc + 1 + disp) & 0xfff); - return 1 | SUPPORTED; + return 1 | STEP_COND | SUPPORTED; } else if (uop >= 0xb0) { diff --git a/src/devices/cpu/mn10200/mn102dis.cpp b/src/devices/cpu/mn10200/mn102dis.cpp index 6f1c4890edf..f4707418708 100644 --- a/src/devices/cpu/mn10200/mn102dis.cpp +++ b/src/devices/cpu/mn10200/mn102dis.cpp @@ -157,43 +157,43 @@ offs_t mn10200_disassembler::disassemble(std::ostream &stream, offs_t pc, const case 0xe0: util::stream_format(stream, "blt $%x", (pc+2+(s8)opcodes.r8(pc+1)) & 0xffffff); - return 2 | SUPPORTED; + return 2 | STEP_COND | SUPPORTED; case 0xe1: util::stream_format(stream, "bgt $%x", (pc+2+(s8)opcodes.r8(pc+1)) & 0xffffff); - return 2 | SUPPORTED; + return 2 | STEP_COND | SUPPORTED; case 0xe2: util::stream_format(stream, "bge $%x", (pc+2+(s8)opcodes.r8(pc+1)) & 0xffffff); - return 2 | SUPPORTED; + return 2 | STEP_COND | SUPPORTED; case 0xe3: util::stream_format(stream, "ble $%x", (pc+2+(s8)opcodes.r8(pc+1)) & 0xffffff); - return 2 | SUPPORTED; + return 2 | STEP_COND | SUPPORTED; case 0xe4: util::stream_format(stream, "bcs $%x", (pc+2+(s8)opcodes.r8(pc+1)) & 0xffffff); - return 2 | SUPPORTED; + return 2 | STEP_COND | SUPPORTED; case 0xe5: util::stream_format(stream, "bhi $%x", (pc+2+(s8)opcodes.r8(pc+1)) & 0xffffff); - return 2 | SUPPORTED; + return 2 | STEP_COND | SUPPORTED; case 0xe6: util::stream_format(stream, "bcc $%x", (pc+2+(s8)opcodes.r8(pc+1)) & 0xffffff); - return 2 | SUPPORTED; + return 2 | STEP_COND | SUPPORTED; case 0xe7: util::stream_format(stream, "bls $%x", (pc+2+(s8)opcodes.r8(pc+1)) & 0xffffff); - return 2 | SUPPORTED; + return 2 | STEP_COND | SUPPORTED; case 0xe8: util::stream_format(stream, "beq $%x", (pc+2+(s8)opcodes.r8(pc+1)) & 0xffffff); - return 2 | SUPPORTED; + return 2 | STEP_COND | SUPPORTED; case 0xe9: util::stream_format(stream, "bne $%x", (pc+2+(s8)opcodes.r8(pc+1)) & 0xffffff); - return 2 | SUPPORTED; + return 2 | STEP_COND | SUPPORTED; case 0xea: util::stream_format(stream, "bra $%x", (pc+2+(s8)opcodes.r8(pc+1)) & 0xffffff); @@ -442,12 +442,12 @@ offs_t mn10200_disassembler::disassemble(std::ostream &stream, offs_t pc, const case 0xc0: case 0xc1: case 0xc2: case 0xc3: case 0xc4: case 0xc5: case 0xc6: case 0xc7: util::stream_format(stream, "tbz ($%x) %d, $%x", r24(opcodes, pc+3), opcode & 7, (pc+7+(s8)opcodes.r8(pc+6)) & 0xffffff); - return 7 | SUPPORTED; + return 7 | STEP_COND | SUPPORTED; case 0xc8: case 0xc9: case 0xca: case 0xcb: case 0xcc: case 0xcd: case 0xce: case 0xcf: util::stream_format(stream, "tbnz ($%x) %d, $%x", r24(opcodes, pc+3), opcode & 7, (pc+7+(s8)opcodes.r8(pc+6)) & 0xffffff); - return 7 | SUPPORTED; + return 7 | STEP_COND | SUPPORTED; case 0xd0: case 0xd1: case 0xd2: case 0xd3: case 0xd4: case 0xd5: case 0xd6: case 0xd7: util::stream_format(stream, "bset ($%x) %d", r24(opcodes, pc+2), opcode & 7); @@ -469,7 +469,7 @@ offs_t mn10200_disassembler::disassemble(std::ostream &stream, offs_t pc, const case 0x88: case 0x89: case 0x8a: case 0x8b: case 0x8c: case 0x8d: case 0x8e: case 0x8f: util::stream_format(stream, "tbz (%s, a%d) %d, $%x", i8str(opcodes.r8(pc+3)), 2+((opcode>>3)&1), opcode & 7, (pc+5+(s8)opcodes.r8(pc+4)) & 0xffffff); - return 5 | SUPPORTED; + return 5 | STEP_COND | SUPPORTED; case 0x90: case 0x91: case 0x92: case 0x93: case 0x94: case 0x95: case 0x96: case 0x97: case 0x98: case 0x99: case 0x9a: case 0x9b: case 0x9c: case 0x9d: case 0x9e: case 0x9f: @@ -480,7 +480,7 @@ offs_t mn10200_disassembler::disassemble(std::ostream &stream, offs_t pc, const case 0xa8: case 0xa9: case 0xaa: case 0xab: case 0xac: case 0xad: case 0xae: case 0xaf: util::stream_format(stream, "tbnz (%s, a%d) %d, $%x", i8str(opcodes.r8(pc+3)), 2+((opcode>>3)&1), opcode & 7, (pc+5+(s8)opcodes.r8(pc+4)) & 0xffffff); - return 5 | SUPPORTED; + return 5 | STEP_COND | SUPPORTED; case 0xb0: case 0xb1: case 0xb2: case 0xb3: case 0xb4: case 0xb5: case 0xb6: case 0xb7: case 0xb8: case 0xb9: case 0xba: case 0xbb: case 0xbc: case 0xbd: case 0xbe: case 0xbf: @@ -723,7 +723,7 @@ offs_t mn10200_disassembler::disassemble(std::ostream &stream, offs_t pc, const case 0x88: case 0x89: case 0x8a: case 0x8b: case 0x8c: case 0x8d: case 0x8e: case 0x8f: util::stream_format(stream, "tbz (%s, a%d) %d, $%x", i8str(opcodes.r8(pc+2)), (opcode>>3)&1, opcode & 7, (pc+4+(s8)opcodes.r8(pc+3)) & 0xffffff); - return 4 | SUPPORTED; + return 4 | STEP_COND | SUPPORTED; case 0x90: case 0x91: case 0x92: case 0x93: case 0x94: case 0x95: case 0x96: case 0x97: case 0x98: case 0x99: case 0x9a: case 0x9b: case 0x9c: case 0x9d: case 0x9e: case 0x9f: @@ -734,7 +734,7 @@ offs_t mn10200_disassembler::disassemble(std::ostream &stream, offs_t pc, const case 0xa8: case 0xa9: case 0xaa: case 0xab: case 0xac: case 0xad: case 0xae: case 0xaf: util::stream_format(stream, "tbnz (%s, a%d) %d, $%x", i8str(opcodes.r8(pc+2)), (opcode>>3)&1, opcode & 7, (pc+4+(s8)opcodes.r8(pc+3)) & 0xffffff); - return 4 | SUPPORTED; + return 4 | STEP_COND | SUPPORTED; case 0xb0: case 0xb1: case 0xb2: case 0xb3: case 0xb4: case 0xb5: case 0xb6: case 0xb7: case 0xb8: case 0xb9: case 0xba: case 0xbb: case 0xbc: case 0xbd: case 0xbe: case 0xbf: @@ -744,12 +744,12 @@ offs_t mn10200_disassembler::disassemble(std::ostream &stream, offs_t pc, const case 0xc0: case 0xc1: case 0xc2: case 0xc3: case 0xc4: case 0xc5: case 0xc6: case 0xc7: util::stream_format(stream, "tbz ($%x) %d, $%x", opcodes.r16(pc+2), opcode & 7, (pc+5+(s8)opcodes.r8(pc+4)) & 0xffffff); - return 5 | SUPPORTED; + return 5 | STEP_COND | SUPPORTED; case 0xc8: case 0xc9: case 0xca: case 0xcb: case 0xcc: case 0xcd: case 0xce: case 0xcf: util::stream_format(stream, "tbnz ($%x) %d, $%x", opcodes.r16(pc+2), opcode & 7, (pc+5+(s8)opcodes.r8(pc+4)) & 0xffffff); - return 5 | SUPPORTED; + return 5 | STEP_COND | SUPPORTED; case 0xd0: case 0xd1: case 0xd2: case 0xd3: case 0xd4: case 0xd5: case 0xd6: case 0xd7: util::stream_format(stream, "bset ($%x) %d", opcodes.r16(pc+2), opcode & 7); @@ -761,59 +761,59 @@ offs_t mn10200_disassembler::disassemble(std::ostream &stream, offs_t pc, const case 0xe0: util::stream_format(stream, "bltx $%x", (pc+3+s8(opcodes.r8(pc+2))) & 0xffffff); - return 3 | SUPPORTED; + return 3 | STEP_COND | SUPPORTED; case 0xe1: util::stream_format(stream, "bgtx $%x", (pc+3+s8(opcodes.r8(pc+2))) & 0xffffff); - return 3 | SUPPORTED; + return 3 | STEP_COND | SUPPORTED; case 0xe2: util::stream_format(stream, "bgex $%x", (pc+3+s8(opcodes.r8(pc+2))) & 0xffffff); - return 3 | SUPPORTED; + return 3 | STEP_COND | SUPPORTED; case 0xe3: util::stream_format(stream, "blex $%x", (pc+3+s8(opcodes.r8(pc+2))) & 0xffffff); - return 3 | SUPPORTED; + return 3 | STEP_COND | SUPPORTED; case 0xe4: util::stream_format(stream, "bcsx $%x", (pc+3+s8(opcodes.r8(pc+2))) & 0xffffff); - return 3 | SUPPORTED; + return 3 | STEP_COND | SUPPORTED; case 0xe5: util::stream_format(stream, "bhix $%x", (pc+3+s8(opcodes.r8(pc+2))) & 0xffffff); - return 3 | SUPPORTED; + return 3 | STEP_COND | SUPPORTED; case 0xe6: util::stream_format(stream, "bccx $%x", (pc+3+s8(opcodes.r8(pc+2))) & 0xffffff); - return 3 | SUPPORTED; + return 3 | STEP_COND | SUPPORTED; case 0xe7: util::stream_format(stream, "blsx $%x", (pc+3+s8(opcodes.r8(pc+2))) & 0xffffff); - return 3 | SUPPORTED; + return 3 | STEP_COND | SUPPORTED; case 0xe8: util::stream_format(stream, "beqx $%x", (pc+3+s8(opcodes.r8(pc+2))) & 0xffffff); - return 3 | SUPPORTED; + return 3 | STEP_COND | SUPPORTED; case 0xe9: util::stream_format(stream, "bnex $%x", (pc+3+s8(opcodes.r8(pc+2))) & 0xffffff); - return 3 | SUPPORTED; + return 3 | STEP_COND | SUPPORTED; case 0xec: util::stream_format(stream, "bvcx $%x", (pc+3+s8(opcodes.r8(pc+2))) & 0xffffff); - return 3 | SUPPORTED; + return 3 | STEP_COND | SUPPORTED; case 0xed: util::stream_format(stream, "bvsx $%x", (pc+3+s8(opcodes.r8(pc+2))) & 0xffffff); - return 3 | SUPPORTED; + return 3 | STEP_COND | SUPPORTED; case 0xee: util::stream_format(stream, "bncx $%x", (pc+3+s8(opcodes.r8(pc+2))) & 0xffffff); - return 3 | SUPPORTED; + return 3 | STEP_COND | SUPPORTED; case 0xef: util::stream_format(stream, "bnsx $%x", (pc+3+s8(opcodes.r8(pc+2))) & 0xffffff); - return 3 | SUPPORTED; + return 3 | STEP_COND | SUPPORTED; case 0xf0: case 0xf1: case 0xf2: case 0xf3: case 0xf4: case 0xf5: case 0xf6: case 0xf7: { @@ -843,19 +843,19 @@ offs_t mn10200_disassembler::disassemble(std::ostream &stream, offs_t pc, const case 0xfc: util::stream_format(stream, "bvc $%x", (pc+3+s8(opcodes.r8(pc+2))) & 0xffffff); - return 3 | SUPPORTED; + return 3 | STEP_COND | SUPPORTED; case 0xfd: util::stream_format(stream, "bvs $%x", (pc+3+s8(opcodes.r8(pc+2))) & 0xffffff); - return 3 | SUPPORTED; + return 3 | STEP_COND | SUPPORTED; case 0xfe: util::stream_format(stream, "bnc $%x", (pc+3+s8(opcodes.r8(pc+2))) & 0xffffff); - return 3 | SUPPORTED; + return 3 | STEP_COND | SUPPORTED; case 0xff: util::stream_format(stream, "bns $%x", (pc+3+s8(opcodes.r8(pc+2))) & 0xffffff); - return 3 | SUPPORTED; + return 3 | STEP_COND | SUPPORTED; default: goto illegal2; diff --git a/src/devices/cpu/mn1880/mn1880d.cpp b/src/devices/cpu/mn1880/mn1880d.cpp index 048828bb842..cd2f0fc6ebc 100644 --- a/src/devices/cpu/mn1880/mn1880d.cpp +++ b/src/devices/cpu/mn1880/mn1880d.cpp @@ -252,6 +252,7 @@ void mn1880_disassembler::dasm_operands(std::ostream &stream, u8 opcode, offs_t stream << ", "; format_rel(stream, pc + 1, opcodes.r8(pc)); ++pc; + flags |= STEP_COND; } } else if (opcode < 0x34) @@ -416,6 +417,8 @@ void mn1880_disassembler::dasm_operands(std::ostream &stream, u8 opcode, offs_t util::stream_format(stream, "%s, ", BIT(opcode, 1) ? "yp" : "xp"); format_rel(stream, pc + 1, opcodes.r8(pc)); ++pc; + if ((opcode & 0xf7) != 0x80) + flags |= STEP_COND; } } else if (opcode < 0xb0) @@ -439,6 +442,7 @@ void mn1880_disassembler::dasm_operands(std::ostream &stream, u8 opcode, offs_t stream << ", "; format_rel(stream, pc + 1, opcodes.r8(pc)); ++pc; + flags |= STEP_COND; } } else @@ -543,6 +547,7 @@ void mn1880_disassembler::dasm_operands(std::ostream &stream, u8 opcode, offs_t stream << ", "; format_rel(stream, pc + 1, opcodes.r8(pc)); ++pc; + flags |= STEP_COND; } else if ((opcode & 0xf7) == 0xf2) { diff --git a/src/devices/cpu/nanoprocessor/nanoprocessor_dasm.cpp b/src/devices/cpu/nanoprocessor/nanoprocessor_dasm.cpp index 352c8fcbcf2..ed7e4d32a38 100644 --- a/src/devices/cpu/nanoprocessor/nanoprocessor_dasm.cpp +++ b/src/devices/cpu/nanoprocessor/nanoprocessor_dasm.cpp @@ -57,23 +57,23 @@ const hp_nanoprocessor_disassembler::dis_entry_t hp_nanoprocessor_disassembler:: {0xff, 0x05, "CMA", nullptr, 1}, {0xff, 0x06, "RSA", nullptr, 1}, {0xff, 0x07, "LSA", nullptr, 1}, - {0xff, 0x08, "SGT", nullptr, 1}, - {0xff, 0x09, "SLT", nullptr, 1}, - {0xff, 0x0a, "SEQ", nullptr, 1}, - {0xff, 0x0b, "SAZ", nullptr, 1}, - {0xff, 0x0c, "SLE", nullptr, 1}, - {0xff, 0x0d, "SGE", nullptr, 1}, - {0xff, 0x0e, "SNE", nullptr, 1}, - {0xff, 0x0f, "SAN", nullptr, 1}, - {0xf8, 0x10, "SBS", &hp_nanoprocessor_disassembler::param_bitno, 1}, - {0xff, 0x1f, "SES", nullptr, 1}, - {0xf8, 0x18, "SFS", &hp_nanoprocessor_disassembler::param_bitno, 1}, - {0xf8, 0x20, "SBN", &hp_nanoprocessor_disassembler::param_bitno, 1}, + {0xff, 0x08, "SGT", nullptr, 1 | STEP_COND}, + {0xff, 0x09, "SLT", nullptr, 1 | STEP_COND}, + {0xff, 0x0a, "SEQ", nullptr, 1 | STEP_COND}, + {0xff, 0x0b, "SAZ", nullptr, 1 | STEP_COND}, + {0xff, 0x0c, "SLE", nullptr, 1 | STEP_COND}, + {0xff, 0x0d, "SGE", nullptr, 1 | STEP_COND}, + {0xff, 0x0e, "SNE", nullptr, 1 | STEP_COND}, + {0xff, 0x0f, "SAN", nullptr, 1 | STEP_COND}, + {0xf8, 0x10, "SBS", &hp_nanoprocessor_disassembler::param_bitno, 1 | STEP_COND}, + {0xff, 0x1f, "SES", nullptr, 1 | STEP_COND}, + {0xf8, 0x18, "SFS", &hp_nanoprocessor_disassembler::param_bitno, 1 | STEP_COND}, + {0xf8, 0x20, "SBN", &hp_nanoprocessor_disassembler::param_bitno, 1 | STEP_COND}, {0xff, 0x2f, "ENI", nullptr, 1}, {0xf8, 0x28, "STC", &hp_nanoprocessor_disassembler::param_bitno, 1}, - {0xf8, 0x30, "SBZ", &hp_nanoprocessor_disassembler::param_bitno, 1}, - {0xff, 0x3f, "SEZ", nullptr, 1}, - {0xf8, 0x38, "SFZ", &hp_nanoprocessor_disassembler::param_bitno, 1}, + {0xf8, 0x30, "SBZ", &hp_nanoprocessor_disassembler::param_bitno, 1 | STEP_COND}, + {0xff, 0x3f, "SEZ", nullptr, 1 | STEP_COND}, + {0xf8, 0x38, "SFZ", &hp_nanoprocessor_disassembler::param_bitno, 1 | STEP_COND}, {0xf0, 0x40, "INA", &hp_nanoprocessor_disassembler::param_ds, 1}, {0xff, 0x5f, "NOP", nullptr, 1}, {0xf0, 0x50, "OTA", &hp_nanoprocessor_disassembler::param_ds, 1}, diff --git a/src/devices/cpu/nec/necdasm.cpp b/src/devices/cpu/nec/necdasm.cpp index e09acb5118a..4267d20dd1c 100644 --- a/src/devices/cpu/nec/necdasm.cpp +++ b/src/devices/cpu/nec/necdasm.cpp @@ -132,22 +132,22 @@ const nec_disassembler::NEC_I386_OPCODE nec_disassembler::necv_opcode_table1[256 {"outmb", 0, 0, 0, 0 }, {"outmw", 0, 0, 0, 0 }, // 0x70 - {"bv", 0, PARAM_REL8, 0, 0 }, - {"bnv", 0, PARAM_REL8, 0, 0 }, - {"bc", 0, PARAM_REL8, 0, 0 }, - {"bnc", 0, PARAM_REL8, 0, 0 }, - {"be", 0, PARAM_REL8, 0, 0 }, - {"bne", 0, PARAM_REL8, 0, 0 }, - {"bnh", 0, PARAM_REL8, 0, 0 }, - {"bh", 0, PARAM_REL8, 0, 0 }, - {"bn", 0, PARAM_REL8, 0, 0 }, - {"bp", 0, PARAM_REL8, 0, 0 }, - {"bpe", 0, PARAM_REL8, 0, 0 }, - {"bpo", 0, PARAM_REL8, 0, 0 }, - {"blt", 0, PARAM_REL8, 0, 0 }, - {"bge", 0, PARAM_REL8, 0, 0 }, - {"ble", 0, PARAM_REL8, 0, 0 }, - {"bgt", 0, PARAM_REL8, 0, 0 }, + {"bv", 0, PARAM_REL8, 0, 0, STEP_COND}, + {"bnv", 0, PARAM_REL8, 0, 0, STEP_COND}, + {"bc", 0, PARAM_REL8, 0, 0, STEP_COND}, + {"bnc", 0, PARAM_REL8, 0, 0, STEP_COND}, + {"be", 0, PARAM_REL8, 0, 0, STEP_COND}, + {"bne", 0, PARAM_REL8, 0, 0, STEP_COND}, + {"bnh", 0, PARAM_REL8, 0, 0, STEP_COND}, + {"bh", 0, PARAM_REL8, 0, 0, STEP_COND}, + {"bn", 0, PARAM_REL8, 0, 0, STEP_COND}, + {"bp", 0, PARAM_REL8, 0, 0, STEP_COND}, + {"bpe", 0, PARAM_REL8, 0, 0, STEP_COND}, + {"bpo", 0, PARAM_REL8, 0, 0, STEP_COND}, + {"blt", 0, PARAM_REL8, 0, 0, STEP_COND}, + {"bge", 0, PARAM_REL8, 0, 0, STEP_COND}, + {"ble", 0, PARAM_REL8, 0, 0, STEP_COND}, + {"bgt", 0, PARAM_REL8, 0, 0, STEP_COND}, // 0x80 {"immb", GROUP, 0, 0, 0 }, {"immw", GROUP, 0, 0, 0 }, @@ -231,7 +231,7 @@ const nec_disassembler::NEC_I386_OPCODE nec_disassembler::necv_opcode_table1[256 {"retf", 0, 0, 0, 0, STEP_OUT}, {"brk 3", 0, 0, 0, 0, STEP_OVER}, {"brk", 0, PARAM_UI8, 0, 0, STEP_OVER}, - {"brkv", 0, 0, 0, 0 }, + {"brkv", 0, 0, 0, 0, STEP_OVER | STEP_COND}, {"reti", 0, 0, 0, 0, STEP_OUT}, // 0xd0 {"shiftb", GROUP, 0, 0, 0 }, @@ -251,10 +251,10 @@ const nec_disassembler::NEC_I386_OPCODE nec_disassembler::necv_opcode_table1[256 {"escape", FPU, 0, 0, 0 }, {"escape", FPU, 0, 0, 0 }, // 0xe0 - {"dbnzne", 0, PARAM_REL8, 0, 0, STEP_OVER}, - {"dbnze", 0, PARAM_REL8, 0, 0, STEP_OVER}, - {"dbnz", 0, PARAM_REL8, 0, 0, STEP_OVER}, - {"bcwz", 0, PARAM_REL8, 0, 0 }, + {"dbnzne", 0, PARAM_REL8, 0, 0, STEP_COND}, + {"dbnze", 0, PARAM_REL8, 0, 0, STEP_COND}, + {"dbnz", 0, PARAM_REL8, 0, 0, STEP_COND}, + {"bcwz", 0, PARAM_REL8, 0, 0, STEP_COND}, {"in", 0, PARAM_AL, PARAM_UI8, 0 }, {"in", 0, PARAM_AW, PARAM_UI8, 0 }, {"out", 0, PARAM_UI8, PARAM_AL, 0 }, @@ -454,7 +454,7 @@ const nec_disassembler::NEC_I386_OPCODE nec_disassembler::necv_opcode_table2[256 {"???", 0, 0, 0, 0 }, {"???", 0, 0, 0, 0 }, {"???", 0, 0, 0, 0 }, - {"btclr", 0, PARAM_SFREG, PARAM_I3, PARAM_REL8 }, /* V25/V35 only */ + {"btclr", 0, PARAM_SFREG, PARAM_I3, PARAM_REL8, STEP_COND}, /* V25/V35 only */ {"???", 0, 0, 0, 0 }, {"stop", 0, 0, 0, 0 }, /* V25/V35 only */ {"???", 0, 0, 0, 0 }, @@ -1654,51 +1654,51 @@ offs_t nec_disassembler::dis80(std::ostream &stream, offs_t pc, const data_buffe case 0xbd: util::stream_format(stream, "cmp bl"); break; case 0xbe: util::stream_format(stream, "cmp m"); break; case 0xbf: util::stream_format(stream, "cmp al"); break; - case 0xc0: util::stream_format(stream, "rnz"); flags = STEP_OUT; break; + case 0xc0: util::stream_format(stream, "rnz"); flags = STEP_OUT | STEP_COND; break; case 0xc1: util::stream_format(stream, "pop cw"); break; - case 0xc2: util::stream_format(stream, "jnz $%04x", params.r16(pc)); pc+=2; break; + case 0xc2: util::stream_format(stream, "jnz $%04x", params.r16(pc)); pc+=2; flags = STEP_COND; break; case 0xc3: util::stream_format(stream, "jmp $%04x", params.r16(pc)); pc+=2; break; case 0xc4: util::stream_format(stream, "cnz $%04x", params.r16(pc)); pc+=2; flags = STEP_OVER; break; case 0xc5: util::stream_format(stream, "push cw"); break; case 0xc6: util::stream_format(stream, "adi $%02x", params.r8(pc)); pc++; break; case 0xc7: util::stream_format(stream, "rst 0"); flags = STEP_OVER; break; - case 0xc8: util::stream_format(stream, "rz"); flags = STEP_OUT; break; + case 0xc8: util::stream_format(stream, "rz"); flags = STEP_OUT | STEP_COND; break; case 0xc9: util::stream_format(stream, "ret"); flags = STEP_OUT; break; - case 0xca: util::stream_format(stream, "jz $%04x", params.r16(pc)); pc+=2; break; + case 0xca: util::stream_format(stream, "jz $%04x", params.r16(pc)); pc+=2; flags = STEP_COND; break; case 0xcb: util::stream_format(stream, "jmp $%04x", params.r16(pc)); pc+=2; break; case 0xcc: util::stream_format(stream, "cz $%04x", params.r16(pc)); pc+=2; flags = STEP_OVER; break; case 0xcd: util::stream_format(stream, "call $%04x", params.r16(pc)); pc+=2; flags = STEP_OVER; break; case 0xce: util::stream_format(stream, "aci $%02x", params.r8(pc)); pc++; break; case 0xcf: util::stream_format(stream, "rst 1"); flags = STEP_OVER; break; - case 0xd0: util::stream_format(stream, "rnc"); flags = STEP_OUT; break; + case 0xd0: util::stream_format(stream, "rnc"); flags = STEP_OUT | STEP_COND; break; case 0xd1: util::stream_format(stream, "pop dw"); break; - case 0xd2: util::stream_format(stream, "jnc $%04x", params.r16(pc)); pc+=2; break; + case 0xd2: util::stream_format(stream, "jnc $%04x", params.r16(pc)); pc+=2; flags = STEP_COND; break; case 0xd3: util::stream_format(stream, "out $%02x", params.r8(pc)); pc++; break; case 0xd4: util::stream_format(stream, "cnc $%04x", params.r16(pc)); pc+=2; flags = STEP_OVER; break; case 0xd5: util::stream_format(stream, "push dw"); break; case 0xd6: util::stream_format(stream, "sui $%02x", params.r8(pc)); pc++; break; case 0xd7: util::stream_format(stream, "rst 2"); flags = STEP_OVER; break; - case 0xd8: util::stream_format(stream, "rc"); flags = STEP_OUT; break; + case 0xd8: util::stream_format(stream, "rc"); flags = STEP_OUT | STEP_COND; break; case 0xd9: util::stream_format(stream, "shlx d (*)"); break; - case 0xda: util::stream_format(stream, "jc $%04x", params.r16(pc)); pc+=2; break; + case 0xda: util::stream_format(stream, "jc $%04x", params.r16(pc)); pc+=2; flags = STEP_COND; break; case 0xdb: util::stream_format(stream, "in $%02x", params.r8(pc)); pc++; break; case 0xdc: util::stream_format(stream, "cc $%04x", params.r16(pc)); pc+=2; flags = STEP_OVER; break; case 0xdd: util::stream_format(stream, "call $%04x", params.r16(pc)); pc+=2; flags = STEP_OVER; break; case 0xde: util::stream_format(stream, "sbi $%02x", params.r8(pc)); pc++; break; case 0xdf: util::stream_format(stream, "rst 3"); flags = STEP_OVER; break; - case 0xe0: util::stream_format(stream, "rpo"); flags = STEP_OUT; break; + case 0xe0: util::stream_format(stream, "rpo"); flags = STEP_OUT | STEP_COND; break; case 0xe1: util::stream_format(stream, "pop bw"); break; - case 0xe2: util::stream_format(stream, "jpo $%04x", params.r16(pc)); pc+=2; break; + case 0xe2: util::stream_format(stream, "jpo $%04x", params.r16(pc)); pc+=2; flags = STEP_COND; break; case 0xe3: util::stream_format(stream, "xthl"); break; - case 0xe4: util::stream_format(stream, "cpo $%04x", params.r16(pc)); pc+=2; flags = STEP_OVER; break; + case 0xe4: util::stream_format(stream, "cpo $%04x", params.r16(pc)); pc+=2; flags = STEP_OVER | STEP_COND; break; case 0xe5: util::stream_format(stream, "push bw"); break; case 0xe6: util::stream_format(stream, "ani $%02x", params.r8(pc)); pc++; break; case 0xe7: util::stream_format(stream, "rst 4"); flags = STEP_OVER; break; - case 0xe8: util::stream_format(stream, "rpe"); flags = STEP_OUT; break; + case 0xe8: util::stream_format(stream, "rpe"); flags = STEP_OUT | STEP_COND; break; case 0xe9: util::stream_format(stream, "pchl"); break; - case 0xea: util::stream_format(stream, "jpe $%04x", params.r16(pc)); pc+=2; break; + case 0xea: util::stream_format(stream, "jpe $%04x", params.r16(pc)); pc+=2; flags = STEP_COND; break; case 0xeb: util::stream_format(stream, "xchg"); break; - case 0xec: util::stream_format(stream, "cpe $%04x", params.r16(pc)); pc+=2; flags = STEP_OVER; break; + case 0xec: util::stream_format(stream, "cpe $%04x", params.r16(pc)); pc+=2; flags = STEP_OVER | STEP_COND; break; case 0xed: switch (params.r8(pc)) { @@ -1712,19 +1712,19 @@ offs_t nec_disassembler::dis80(std::ostream &stream, offs_t pc, const data_buffe break; case 0xee: util::stream_format(stream, "xri $%02x", params.r8(pc)); pc++; break; case 0xef: util::stream_format(stream, "rst 5"); flags = STEP_OVER; break; - case 0xf0: util::stream_format(stream, "rp"); flags = STEP_OUT; break; + case 0xf0: util::stream_format(stream, "rp"); flags = STEP_OUT | STEP_COND; break; case 0xf1: util::stream_format(stream, "pop psw"); break; - case 0xf2: util::stream_format(stream, "jp $%04x", params.r16(pc)); pc+=2; break; + case 0xf2: util::stream_format(stream, "jp $%04x", params.r16(pc)); pc+=2; flags = STEP_COND; break; case 0xf3: util::stream_format(stream, "di"); break; - case 0xf4: util::stream_format(stream, "cp $%04x", params.r16(pc)); pc+=2; break; + case 0xf4: util::stream_format(stream, "cp $%04x", params.r16(pc)); pc+=2; flags = STEP_OVER | STEP_COND; break; case 0xf5: util::stream_format(stream, "push psw"); break; case 0xf6: util::stream_format(stream, "ori $%02x", params.r8(pc)); pc++; break; case 0xf7: util::stream_format(stream, "rst 6"); flags = STEP_OVER; break; - case 0xf8: util::stream_format(stream, "rm"); flags = STEP_OUT; break; + case 0xf8: util::stream_format(stream, "rm"); flags = STEP_OUT | STEP_COND; break; case 0xf9: util::stream_format(stream, "sphl"); break; case 0xfa: util::stream_format(stream, "jm $%04x", params.r16(pc)); pc+=2; break; case 0xfb: util::stream_format(stream, "ei"); break; - case 0xfc: util::stream_format(stream, "cm $%04x", params.r16(pc)); pc+=2; flags = STEP_OVER; break; + case 0xfc: util::stream_format(stream, "cm $%04x", params.r16(pc)); pc+=2; flags = STEP_OVER | STEP_COND; break; case 0xfd: util::stream_format(stream, "call $%04x", params.r16(pc)); pc+=2; flags = STEP_OVER; break; case 0xfe: util::stream_format(stream, "cpi $%02x", params.r8(pc)); pc++; break; case 0xff: util::stream_format(stream, "rst 7"); flags = STEP_OVER; break; diff --git a/src/devices/cpu/ns32000/ns32000dasm.cpp b/src/devices/cpu/ns32000/ns32000dasm.cpp index 461258cb386..9d1dd6c850a 100644 --- a/src/devices/cpu/ns32000/ns32000dasm.cpp +++ b/src/devices/cpu/ns32000/ns32000dasm.cpp @@ -207,6 +207,8 @@ offs_t ns32000_disassembler::disassemble(std::ostream &stream, offs_t pc, data_b { // format 0: cccc 1010 util::stream_format(stream, "B%-2s 0x%X", cond_code[BIT(opbyte, 4, 4)], pc + displacement(pc, opcodes, bytes)); + if (BIT(opbyte, 4, 4) < 0xe) + flags |= STEP_COND; } else if ((opbyte & 15) == 2) { @@ -258,7 +260,7 @@ offs_t ns32000_disassembler::disassemble(std::ostream &stream, offs_t pc, data_b case 1: util::stream_format(stream, "CMPQ%c %d, %s", size_char[size], s32(quick << 28) >> 28, mode[0].mode); break; case 2: util::stream_format(stream, "SPR%c %s, %s", size_char[size], procreg[quick], mode[0].mode); break; case 3: util::stream_format(stream, "S%s%c %s", cond_code[quick], size_char[size], mode[0].mode); break; - case 4: util::stream_format(stream, "ACB%c %d, %s, 0x%X", size_char[size], s32(quick << 28) >> 28, mode[0].mode, pc + displacement(pc, opcodes, bytes)); break; + case 4: util::stream_format(stream, "ACB%c %d, %s, 0x%X", size_char[size], s32(quick << 28) >> 28, mode[0].mode, pc + displacement(pc, opcodes, bytes)); flags |= STEP_COND; break; case 5: util::stream_format(stream, "MOVQ%c %d, %s", size_char[size], s32(quick << 28) >> 28, mode[0].mode); break; case 6: util::stream_format(stream, "LPR%c %s, %s", size_char[size], procreg[quick], mode[0].mode); break; case 7: diff --git a/src/devices/cpu/pace/pacedasm.cpp b/src/devices/cpu/pace/pacedasm.cpp index 6ab93f8f75d..f6c8b438813 100644 --- a/src/devices/cpu/pace/pacedasm.cpp +++ b/src/devices/cpu/pace/pacedasm.cpp @@ -111,211 +111,211 @@ offs_t pace_disassembler::disassemble(std::ostream &stream, offs_t pc, const pac { case 0x0000: stream << "HALT"; - return 1; + return 1 | SUPPORTED; case 0x0400: util::stream_format(stream, "%-8sAC%d", "CFR", (inst & 0x0300) >> 8); - return 1; + return 1 | SUPPORTED; case 0x0800: util::stream_format(stream, "%-8sAC%d", "CRF", (inst & 0x0300) >> 8); - return 1; + return 1 | SUPPORTED; case 0x0c00: stream << "PUSHF"; - return 1; + return 1 | SUPPORTED; case 0x1000: stream << "PULLF"; - return 1; + return 1 | SUPPORTED; case 0x1400: util::stream_format(stream, "%-8s", "JSR"); format_ea(stream, pc, inst); - return 1 | STEP_OVER; + return 1 | STEP_OVER | SUPPORTED; case 0x1800: util::stream_format(stream, "%-8s", "JMP"); format_ea(stream, pc, inst); - return 1; + return 1 | SUPPORTED; case 0x1c00: util::stream_format(stream, "%-8sAC%d", "XCHRS", (inst & 0x0300) >> 8); - return 1; + return 1 | SUPPORTED; case 0x2000: util::stream_format(stream, "%-8sAC%d,%d,%d", "ROL", (inst & 0x0300) >> 8, (inst & 0x00fe) >> 1, inst & 0x0001); - return 1; + return 1 | SUPPORTED; case 0x2400: util::stream_format(stream, "%-8sAC%d,%d,%d", "ROR", (inst & 0x0300) >> 8, (inst & 0x00fe) >> 1, inst & 0x0001); - return 1; + return 1 | SUPPORTED; case 0x2800: util::stream_format(stream, "%-8sAC%d,%d,%d", "SHL", (inst & 0x0300) >> 8, (inst & 0x00fe) >> 1, inst & 0x0001); - return 1; + return 1 | SUPPORTED; case 0x2c00: util::stream_format(stream, "%-8sAC%d,%d,%d", "SHR", (inst & 0x0300) >> 8, (inst & 0x00fe) >> 1, inst & 0x0001); - return 1; + return 1 | SUPPORTED; case 0x3000: case 0x3400: case 0x3800: case 0x3c00: util::stream_format(stream, "%-8s%s", BIT(inst, 7) ? "SFLG" : "PFLG", s_flags[(inst & 0x0f00) >> 8]); - return 1; + return 1 | SUPPORTED; case 0x4000: case 0x4400: case 0x4800: case 0x4c00: util::stream_format(stream, "%-8s%s,", "BOC", s_cc[(inst & 0x0f00) >> 8]); format_addr(stream, pc + 1 + s8(inst & 0x00ff)); - return 1; + return 1 | STEP_COND | SUPPORTED; case 0x5000: util::stream_format(stream, "%-8sAC%d,", "LI", (inst & 0x0300) >> 8); format_disp(stream, inst & 0x00ff); - return 1; + return 1 | SUPPORTED; case 0x5400: util::stream_format(stream, "%-8sAC%d,AC%d", "RAND", (inst & 0x00c0) >> 6, (inst & 0x0300) >> 8); - return 1; + return 1 | SUPPORTED; case 0x5800: util::stream_format(stream, "%-8sAC%d,AC%d", "RXOR", (inst & 0x00c0) >> 6, (inst & 0x0300) >> 8); - return 1; + return 1 | SUPPORTED; case 0x5c00: if ((inst & 0x0300) >> 2 == (inst & 0x00c0)) stream << "NOP"; else util::stream_format(stream, "%-8sAC%d,AC%d", "RCPY", (inst & 0x00c0) >> 6, (inst & 0x0300) >> 8); - return 1; + return 1 | SUPPORTED; case 0x6000: util::stream_format(stream, "%-8sAC%d", "PUSH", (inst & 0x0300) >> 8); - return 1; + return 1 | SUPPORTED; case 0x6400: util::stream_format(stream, "%-8sAC%d", "PULL", (inst & 0x0300) >> 8); - return 1; + return 1 | SUPPORTED; case 0x6800: util::stream_format(stream, "%-8sAC%d,AC%d", "RADD", (inst & 0x00c0) >> 6, (inst & 0x0300) >> 8); - return 1; + return 1 | SUPPORTED; case 0x6c00: util::stream_format(stream, "%-8sAC%d,AC%d", "RXCH", (inst & 0x00c0) >> 6, (inst & 0x0300) >> 8); - return 1; + return 1 | SUPPORTED; case 0x7000: util::stream_format(stream, "%-8sAC%d,", "CAI", (inst & 0x0300) >> 8); format_disp(stream, inst & 0x00ff); - return 1; + return 1 | SUPPORTED; case 0x7400: util::stream_format(stream, "%-8sAC%d,AC%d", "RADC", (inst & 0x00c0) >> 6, (inst & 0x0300) >> 8); - return 1; + return 1 | SUPPORTED; case 0x7800: util::stream_format(stream, "%-8sAC%d,", "AISZ", (inst & 0x0300) >> 8); format_disp(stream, inst & 0x00ff); - return 1 | STEP_OVER; + return 1 | STEP_COND | SUPPORTED; case 0x7c00: util::stream_format(stream, "%-8s", "RTI"); format_disp(stream, inst & 0x00ff); - return 1 | STEP_OUT; + return 1 | STEP_OUT | SUPPORTED; case 0x8000: util::stream_format(stream, "%-8s", "RTS"); format_disp(stream, inst & 0x00ff); - return 1 | STEP_OUT; + return 1 | STEP_OUT | SUPPORTED; case 0x8800: util::stream_format(stream, "%-8sAC0,", "DECA"); format_ea(stream, pc, inst); - return 1; + return 1 | SUPPORTED; case 0x8c00: util::stream_format(stream, "%-8s", "ISZ"); format_ea(stream, pc, inst); - return 1 | STEP_OVER; + return 1 | STEP_COND | SUPPORTED; case 0x9000: util::stream_format(stream, "%-8sAC0,", "SUBB"); format_ea(stream, pc, inst); - return 1; + return 1 | SUPPORTED; case 0x9400: util::stream_format(stream, "%-8s@", "JSR"); format_ea(stream, pc, inst); - return 1 | STEP_OVER; + return 1 | STEP_OVER | SUPPORTED; case 0x9800: util::stream_format(stream, "%-8s@", "JMP"); format_ea(stream, pc, inst); - return 1; + return 1 | SUPPORTED; case 0x9c00: util::stream_format(stream, "%-8sAC0,", "SKG"); format_ea(stream, pc, inst); - return 1 | STEP_OVER; + return 1 | STEP_COND | SUPPORTED; case 0xa000: util::stream_format(stream, "%-8sAC0,@", "LD"); format_ea(stream, pc, inst); - return 1; + return 1 | SUPPORTED; case 0xa400: util::stream_format(stream, "%-8sAC0,", "OR"); format_ea(stream, pc, inst); - return 1; + return 1 | SUPPORTED; case 0xa800: util::stream_format(stream, "%-8sAC0,", "AND"); format_ea(stream, pc, inst); - return 1; + return 1 | SUPPORTED; case 0xac00: util::stream_format(stream, "%-8s", "DSZ"); format_ea(stream, pc, inst); - return 1 | STEP_OVER; + return 1 | STEP_COND | SUPPORTED; case 0xb000: util::stream_format(stream, "%-8sAC0,@", "ST"); format_ea(stream, pc, inst); - return 1; + return 1 | SUPPORTED; case 0xb800: util::stream_format(stream, "%-8sAC0,", "SKAZ"); format_ea(stream, pc, inst); - return 1 | STEP_OVER; + return 1 | STEP_COND | SUPPORTED; case 0xbc00: util::stream_format(stream, "%-8sAC0,", "LSEX"); format_ea(stream, pc, inst); - return 1; + return 1 | SUPPORTED; case 0xc000: case 0xc400: case 0xc800: case 0xcc00: util::stream_format(stream, "%-8sAC%d,", "LD", (inst & 0x0c00) >> 10); format_ea(stream, pc, inst); - return 1; + return 1 | SUPPORTED; case 0xd000: case 0xd400: case 0xd800: case 0xdc00: util::stream_format(stream, "%-8sAC%d,", "ST", (inst & 0x0c00) >> 10); format_ea(stream, pc, inst); - return 1; + return 1 | SUPPORTED; case 0xe000: case 0xe400: case 0xe800: case 0xec00: util::stream_format(stream, "%-8sAC%d,", "ADD", (inst & 0x0c00) >> 10); format_ea(stream, pc, inst); - return 1; + return 1 | SUPPORTED; case 0xf000: case 0xf400: case 0xf800: case 0xfc00: util::stream_format(stream, "%-8sAC%d,", "SKNE", (inst & 0x0c00) >> 10); format_ea(stream, pc, inst); - return 1 | STEP_OVER; + return 1 | STEP_COND | SUPPORTED; default: util::stream_format(stream, "%-8s", ".WORD"); format_addr(stream, inst); - return 1; + return 1 | SUPPORTED; } } diff --git a/src/devices/cpu/pdp8/pdp8dasm.cpp b/src/devices/cpu/pdp8/pdp8dasm.cpp index dca8fadf4e2..ad7a886ff0e 100644 --- a/src/devices/cpu/pdp8/pdp8dasm.cpp +++ b/src/devices/cpu/pdp8/pdp8dasm.cpp @@ -140,7 +140,7 @@ offs_t pdp8_disassembler::dasm_iot(std::ostream &stream, u16 dev, offs_t pc) { case 000: stream << "SKON"; // PDP-8/E and up - break; + return 1 | SUPPORTED | STEP_COND; case 001: stream << "ION"; @@ -152,7 +152,7 @@ offs_t pdp8_disassembler::dasm_iot(std::ostream &stream, u16 dev, offs_t pc) case 003: stream << "SRQ"; // PDP-8/E and up - break; + return 1 | SUPPORTED | STEP_COND; case 004: stream << "GTF"; // PDP-8/E and up (used earlier by a PDP-5/Classic-8 ADC option) @@ -164,7 +164,7 @@ offs_t pdp8_disassembler::dasm_iot(std::ostream &stream, u16 dev, offs_t pc) case 006: stream << "SGT"; // KE8-E - break; + return 1 | SUPPORTED | STEP_COND; case 007: stream << "CAF"; // PDP-8/E and up @@ -176,7 +176,7 @@ offs_t pdp8_disassembler::dasm_iot(std::ostream &stream, u16 dev, offs_t pc) case 011: stream << "RSF"; // Paper tape reader - break; + return 1 | SUPPORTED | STEP_COND; case 012: case 016: stream << "RRB"; // Paper tape reader @@ -194,7 +194,7 @@ offs_t pdp8_disassembler::dasm_iot(std::ostream &stream, u16 dev, offs_t pc) case 021: stream << "PSF"; // Paper tape punch - break; + return 1 | SUPPORTED | STEP_COND; case 022: stream << "PCF"; // Paper tape punch @@ -214,7 +214,7 @@ offs_t pdp8_disassembler::dasm_iot(std::ostream &stream, u16 dev, offs_t pc) case 031: stream << "KSF"; // TTY/keyboard - break; + return 1 | SUPPORTED | STEP_COND; case 032: stream << "KCC"; // TTY/keyboard @@ -238,7 +238,7 @@ offs_t pdp8_disassembler::dasm_iot(std::ostream &stream, u16 dev, offs_t pc) case 041: stream << "TSF"; // Teleprinter - break; + return 1 | SUPPORTED | STEP_COND; case 042: stream << "TCF"; // Teleprinter @@ -250,7 +250,7 @@ offs_t pdp8_disassembler::dasm_iot(std::ostream &stream, u16 dev, offs_t pc) case 045: stream << "TSK"; // Teleprinter (KL8-E and up; SPI is a later name for this IOT) - break; + return 1 | SUPPORTED | STEP_COND; case 046: stream << "TLS"; // Teleprinter @@ -258,7 +258,7 @@ offs_t pdp8_disassembler::dasm_iot(std::ostream &stream, u16 dev, offs_t pc) case 0102: stream << "SPL"; // Automatic restart - break; + return 1 | SUPPORTED | STEP_COND; case 0201: case 0202: case 0203: case 0211: case 0212: case 0213: @@ -297,7 +297,7 @@ offs_t pdp8_disassembler::dasm_iot(std::ostream &stream, u16 dev, offs_t pc) case 0254: stream << "SINT"; // Time-sharing extension (LIF on some Intersil peripherals) - break; + return 1 | SUPPORTED | STEP_COND; case 0264: stream << "CUF"; // Time-sharing extension @@ -309,7 +309,7 @@ offs_t pdp8_disassembler::dasm_iot(std::ostream &stream, u16 dev, offs_t pc) default: util::stream_format(stream, "IOT %03o", dev); - break; + return 1 | SUPPORTED | STEP_COND; // any IOT can theoretically cause a skip } return 1 | SUPPORTED; @@ -324,7 +324,10 @@ offs_t hd6120_disassembler::dasm_iot(std::ostream &stream, u16 dev, offs_t pc) if (BIT(pc, 15)) stream << "PRS"; else + { stream << "SKON"; + return 1 | SUPPORTED | STEP_COND; + } break; case 001: @@ -339,7 +342,10 @@ offs_t hd6120_disassembler::dasm_iot(std::ostream &stream, u16 dev, offs_t pc) if (BIT(pc, 15)) stream << "PGO"; else + { stream << "SRQ"; + return 1 | SUPPORTED | STEP_COND; + } break; case 004: @@ -355,7 +361,7 @@ offs_t hd6120_disassembler::dasm_iot(std::ostream &stream, u16 dev, offs_t pc) case 006: stream << "SGT"; - break; + return 1 | SUPPORTED | STEP_COND; case 007: stream << "CAF"; @@ -432,7 +438,7 @@ offs_t hd6120_disassembler::dasm_iot(std::ostream &stream, u16 dev, offs_t pc) default: util::stream_format(stream, "IOT %03o", dev); - break; + return 1 | SUPPORTED | STEP_COND; } return 1 | SUPPORTED; @@ -592,7 +598,7 @@ void pdp8_disassembler::dasm_opr_group1(std::ostream &stream, u16 opr) // Sequence 1b: SMA, SZA, SZL (skip if any condition holds) // Sequence 2: CLA // Sequence 3: OSR, HLT -void pdp8_disassembler::dasm_opr_group2(std::ostream &stream, u16 opr) +offs_t pdp8_disassembler::dasm_opr_group2(std::ostream &stream, u16 opr) { if ((opr & 0170) != 0) { @@ -643,6 +649,14 @@ void pdp8_disassembler::dasm_opr_group2(std::ostream &stream, u16 opr) if ((opr & 0170) == 0) stream << "!400"; } + + // HACK: HLT is a software trap on HD-6120 + if (m_has_r3l && BIT(opr, 1)) + return 1 | SUPPORTED | STEP_OVER; + else if ((opr & 0160) != 0) + return 1 | SUPPORTED | STEP_COND; + else + return 1 | SUPPORTED; } // Sequence 1: CLA @@ -777,7 +791,7 @@ offs_t pdp8_disassembler::dasm_opr_group3(std::ostream &stream, u16 opr, offs_t if ((opr & 0320) != 0) stream << " "; stream << "DPSZ"; // KE8-E Mode B - break; + return 1 | SUPPORTED | STEP_COND; case 056: if ((opr & 0320) != 0) @@ -856,7 +870,7 @@ offs_t pdp8_disassembler::disassemble(std::ostream &stream, offs_t pc, const pdp case 2: stream << "ISZ"; dasm_memory_reference(stream, inst, pc); - break; + return 1 | SUPPORTED | STEP_COND; case 3: stream << "DCA"; @@ -882,13 +896,7 @@ offs_t pdp8_disassembler::disassemble(std::ostream &stream, offs_t pc, const pdp if (!BIT(inst, 8)) dasm_opr_group1(stream, inst & 0777); else if (!BIT(inst, 0)) - { - dasm_opr_group2(stream, inst & 0777); - - // HACK: HLT is a software trap on HD-6120 - if (m_has_r3l && BIT(inst, 1)) - return 1 | SUPPORTED | STEP_OVER; - } + return dasm_opr_group2(stream, inst & 0777); else return dasm_opr_group3(stream, inst & 0777, pc, opcodes); break; diff --git a/src/devices/cpu/pdp8/pdp8dasm.h b/src/devices/cpu/pdp8/pdp8dasm.h index 64821c40fc6..fd32ae9cd2e 100644 --- a/src/devices/cpu/pdp8/pdp8dasm.h +++ b/src/devices/cpu/pdp8/pdp8dasm.h @@ -19,7 +19,7 @@ protected: void dasm_memory_reference(std::ostream &stream, u16 inst, offs_t pc); virtual offs_t dasm_iot(std::ostream &stream, u16 dev, offs_t pc); void dasm_opr_group1(std::ostream &stream, u16 inst); - void dasm_opr_group2(std::ostream &stream, u16 inst); + offs_t dasm_opr_group2(std::ostream &stream, u16 inst); virtual offs_t dasm_opr_group3(std::ostream &stream, u16 inst, offs_t pc, const data_buffer &opcodes); private: diff --git a/src/devices/cpu/pic16/pic16d.cpp b/src/devices/cpu/pic16/pic16d.cpp index 281c4a69379..e0df92b2416 100644 --- a/src/devices/cpu/pic16/pic16d.cpp +++ b/src/devices/cpu/pic16/pic16d.cpp @@ -106,14 +106,14 @@ const pic16_disassembler::instruction pic16_disassembler::instructions[] { { 0x0e00, 0x3f00, [](P) -> u32 { util::stream_format(stream, "swapf %s, %c", d->freg(opcode), fw(opcode)); return 1; } }, { 0x0600, 0x3f00, [](P) -> u32 { util::stream_format(stream, "xorwf %s, %c", d->freg(opcode), fw(opcode)); return 1; } }, - { 0x0b00, 0x3f00, [](P) -> u32 { util::stream_format(stream, "decfsz %s, %c", d->freg(opcode), fw(opcode)); return 1; } }, - { 0x0f00, 0x3f00, [](P) -> u32 { util::stream_format(stream, "incfsz %s, %c", d->freg(opcode), fw(opcode)); return 1; } }, + { 0x0b00, 0x3f00, [](P) -> u32 { util::stream_format(stream, "decfsz %s, %c", d->freg(opcode), fw(opcode)); return 1 | STEP_COND; } }, + { 0x0f00, 0x3f00, [](P) -> u32 { util::stream_format(stream, "incfsz %s, %c", d->freg(opcode), fw(opcode)); return 1 | STEP_COND; } }, { 0x1000, 0x3c00, [](P) -> u32 { util::stream_format(stream, "bcf %d, %s", (opcode >> 7) & 7, d->freg(opcode)); return 1; } }, { 0x1400, 0x3c00, [](P) -> u32 { util::stream_format(stream, "bsf %d, %s", (opcode >> 7) & 7, d->freg(opcode)); return 1; } }, - { 0x1800, 0x3c00, [](P) -> u32 { util::stream_format(stream, "btfsc %d, %s", (opcode >> 7) & 7, d->freg(opcode)); return 1; } }, - { 0x1c00, 0x3c00, [](P) -> u32 { util::stream_format(stream, "btfss %d, %s", (opcode >> 7) & 7, d->freg(opcode)); return 1; } }, + { 0x1800, 0x3c00, [](P) -> u32 { util::stream_format(stream, "btfsc %d, %s", (opcode >> 7) & 7, d->freg(opcode)); return 1 | STEP_COND; } }, + { 0x1c00, 0x3c00, [](P) -> u32 { util::stream_format(stream, "btfss %d, %s", (opcode >> 7) & 7, d->freg(opcode)); return 1 | STEP_COND; } }, { 0x3e00, 0x3f00, [](P) -> u32 { util::stream_format(stream, "addlw %s", imm8(opcode)); return 1; } }, { 0x3900, 0x3f00, [](P) -> u32 { util::stream_format(stream, "andlw %s", imm8(opcode)); return 1; } }, diff --git a/src/devices/cpu/pic1670/pic1670d.cpp b/src/devices/cpu/pic1670/pic1670d.cpp index aa5b7e64795..60aaf52d429 100644 --- a/src/devices/cpu/pic1670/pic1670d.cpp +++ b/src/devices/cpu/pic1670/pic1670d.cpp @@ -53,25 +53,25 @@ const pic1670_disassembler::instruction pic1670_disassembler::instructions[] { { 0x0400, 0x1f80, [](P) -> u32 { util::stream_format(stream, "adcwf %s, %c", d->freg(opcode), fw(opcode)); return 1; } }, { 0x0480, 0x1f80, [](P) -> u32 { util::stream_format(stream, "comf %s, %c", d->freg(opcode), fw(opcode)); return 1; } }, { 0x0500, 0x1f80, [](P) -> u32 { util::stream_format(stream, "incf %s, %c", d->freg(opcode), fw(opcode)); return 1; } }, - { 0x0580, 0x1f80, [](P) -> u32 { util::stream_format(stream, "decfsz %s, %c", d->freg(opcode), fw(opcode)); return 1; } }, + { 0x0580, 0x1f80, [](P) -> u32 { util::stream_format(stream, "decfsz %s, %c", d->freg(opcode), fw(opcode)); return 1 | STEP_COND; } }, { 0x0600, 0x1f80, [](P) -> u32 { util::stream_format(stream, "rlcf %s, %c", d->freg(opcode), fw(opcode)); return 1; } }, { 0x0680, 0x1f80, [](P) -> u32 { util::stream_format(stream, "rrcf %s, %c", d->freg(opcode), fw(opcode)); return 1; } }, { 0x0700, 0x1f80, [](P) -> u32 { util::stream_format(stream, "swapf %s, %c", d->freg(opcode), fw(opcode)); return 1; } }, - { 0x0780, 0x1f80, [](P) -> u32 { util::stream_format(stream, "incfsz %s, %c", d->freg(opcode), fw(opcode)); return 1; } }, + { 0x0780, 0x1f80, [](P) -> u32 { util::stream_format(stream, "incfsz %s, %c", d->freg(opcode), fw(opcode)); return 1 | STEP_COND; } }, { 0x1000, 0x1fc0, [](P) -> u32 { util::stream_format(stream, "movfw %s", d->freg(opcode) ); return 1; } }, { 0x1040, 0x1fc0, [](P) -> u32 { util::stream_format(stream, "clrf %s", d->freg(opcode) ); return 1; } }, { 0x1080, 0x1fc0, [](P) -> u32 { util::stream_format(stream, "rrncf %s", d->freg(opcode) ); return 1; } }, { 0x10c0, 0x1fc0, [](P) -> u32 { util::stream_format(stream, "rlncf %s", d->freg(opcode) ); return 1; } }, - { 0x1100, 0x1fc0, [](P) -> u32 { util::stream_format(stream, "cpfslt %s", d->freg(opcode) ); return 1; } }, - { 0x1140, 0x1fc0, [](P) -> u32 { util::stream_format(stream, "cpfseq %s", d->freg(opcode) ); return 1; } }, - { 0x1180, 0x1fc0, [](P) -> u32 { util::stream_format(stream, "cpfsgt %s", d->freg(opcode) ); return 1; } }, + { 0x1100, 0x1fc0, [](P) -> u32 { util::stream_format(stream, "cpfslt %s", d->freg(opcode) ); return 1 | STEP_COND; } }, + { 0x1140, 0x1fc0, [](P) -> u32 { util::stream_format(stream, "cpfseq %s", d->freg(opcode) ); return 1 | STEP_COND; } }, + { 0x1180, 0x1fc0, [](P) -> u32 { util::stream_format(stream, "cpfsgt %s", d->freg(opcode) ); return 1 | STEP_COND; } }, { 0x11c0, 0x1fc0, [](P) -> u32 { util::stream_format(stream, "testf %s", d->freg(opcode) ); return 1; } }, { 0x0800, 0x1e00, [](P) -> u32 { util::stream_format(stream, "bcf %d, %s", (opcode >> 6) & 7, d->freg(opcode)); return 1; } }, { 0x0a00, 0x1e00, [](P) -> u32 { util::stream_format(stream, "bsf %d, %s", (opcode >> 6) & 7, d->freg(opcode)); return 1; } }, - { 0x0c00, 0x1e00, [](P) -> u32 { util::stream_format(stream, "btfsc %d, %s", (opcode >> 6) & 7, d->freg(opcode)); return 1; } }, - { 0x0e00, 0x1e00, [](P) -> u32 { util::stream_format(stream, "btfss %d, %s", (opcode >> 6) & 7, d->freg(opcode)); return 1; } }, + { 0x0c00, 0x1e00, [](P) -> u32 { util::stream_format(stream, "btfsc %d, %s", (opcode >> 6) & 7, d->freg(opcode)); return 1 | STEP_COND; } }, + { 0x0e00, 0x1e00, [](P) -> u32 { util::stream_format(stream, "btfss %d, %s", (opcode >> 6) & 7, d->freg(opcode)); return 1 | STEP_COND; } }, { 0x0000, 0x1fc7, [](P) -> u32 { util::stream_format(stream, "nop" ); return 1; } }, { 0x0001, 0x1fc7, [](P) -> u32 { util::stream_format(stream, "halt" ); return 1; } }, diff --git a/src/devices/cpu/pic16c5x/16c5xdsm.cpp b/src/devices/cpu/pic16c5x/16c5xdsm.cpp index 65f931df057..251aa02bf84 100644 --- a/src/devices/cpu/pic16c5x/16c5xdsm.cpp +++ b/src/devices/cpu/pic16c5x/16c5xdsm.cpp @@ -190,6 +190,8 @@ offs_t pic16c5x_disassembler::disassemble(std::ostream &stream, offs_t pc, const flags = STEP_OVER; else if (!strncmp(cp, "ret", 3)) flags = STEP_OUT; + else if (!strncmp(cp, "btfs", 4) || !strncmp(cp + 2, "cfsz", 4)) + flags = STEP_COND; while (*cp) { diff --git a/src/devices/cpu/pic16c62x/16c62xdsm.cpp b/src/devices/cpu/pic16c62x/16c62xdsm.cpp index 1e088fbb05c..1c2677002cf 100644 --- a/src/devices/cpu/pic16c62x/16c62xdsm.cpp +++ b/src/devices/cpu/pic16c62x/16c62xdsm.cpp @@ -202,6 +202,8 @@ offs_t pic16c62x_disassembler::disassemble(std::ostream &stream, offs_t pc, cons flags = STEP_OVER; else if (!strncmp(cp, "ret", 3)) flags = STEP_OUT; + else if (!strncmp(cp, "btfs", 4) || !strncmp(cp + 2, "cfsz", 4)) + flags = STEP_COND; while (*cp) { diff --git a/src/devices/cpu/pic17/pic17d.cpp b/src/devices/cpu/pic17/pic17d.cpp index faa1d666c13..139e5058631 100644 --- a/src/devices/cpu/pic17/pic17d.cpp +++ b/src/devices/cpu/pic17/pic17d.cpp @@ -161,6 +161,8 @@ offs_t pic17_disassembler::disassemble(std::ostream &stream, offs_t pc, const pi util::stream_format(stream, "%-8s", s_bit_ops[BIT(opcode, 11, 2)]); format_register(stream, opcode & 0x00ff); util::stream_format(stream, ",%d", BIT(opcode, 8, 3)); + if (BIT(opcode, 12)) + words |= STEP_COND; } else if (opcode >= 0x6000) { @@ -189,6 +191,7 @@ offs_t pic17_disassembler::disassemble(std::ostream &stream, offs_t pc, const pi { util::stream_format(stream, "%-8s", s_cp_ops[BIT(opcode, 8, 2)]); format_register(stream, opcode & 0x00ff); + words |= STEP_COND; } else if (opcode < 0x3500) { @@ -205,6 +208,8 @@ offs_t pic17_disassembler::disassemble(std::ostream &stream, offs_t pc, const pi format_register(stream, opcode & 0x00ff); if (opcode >= 0x0200) util::stream_format(stream, ",%c", BIT(opcode, 8) ? 'F' : 'W'); + if ((opcode & 0x3600) == 0x1600 || (opcode & 0x3c00) == 0x2400) + words |= STEP_COND; } else switch (opcode) { diff --git a/src/devices/cpu/powerpc/ppc_dasm.cpp b/src/devices/cpu/powerpc/ppc_dasm.cpp index d43f00cbb21..cca25897e00 100644 --- a/src/devices/cpu/powerpc/ppc_dasm.cpp +++ b/src/devices/cpu/powerpc/ppc_dasm.cpp @@ -860,6 +860,8 @@ offs_t powerpc_disassembler::dasm_one(std::ostream &stream, uint32_t pc, uint32_ oprs = util::string_format("0x%02X,%d,0x%08X", G_BO(op), G_BI(op), disp + ((op & M_AA) ? 0 : pc)); else // BI gives us the condition bit oprs = util::string_format("0x%02X,cr%d[%s],0x%08X", G_BO(op), G_BI(op) / 4, crbit[G_BI(op) & 3], disp + ((op & M_AA) ? 0 : pc)); + if ((G_BO(op) & 0x14) != 0x14) + flags |= STEP_COND; break; case F_BO_BI: @@ -867,6 +869,8 @@ offs_t powerpc_disassembler::dasm_one(std::ostream &stream, uint32_t pc, uint32_ oprs = util::string_format("0x%02X,%d", G_BO(op), G_BI(op)); else oprs = util::string_format("0x%02X,cr%d[%s]", G_BO(op), G_BI(op) / 4, crbit[G_BI(op) & 3]); + if ((G_BO(op) & 0x14) != 0x14) + flags |= STEP_COND; break; case F_CMP: diff --git a/src/devices/cpu/pps4/pps4dasm.cpp b/src/devices/cpu/pps4/pps4dasm.cpp index d14912385c8..2179c1927c0 100644 --- a/src/devices/cpu/pps4/pps4dasm.cpp +++ b/src/devices/cpu/pps4/pps4dasm.cpp @@ -66,7 +66,7 @@ char const *const pps4_disassembler::token_str[t_COUNT] = { "sag" /* special address generation */ }; -uint16_t const pps4_disassembler::table[] = { +uint32_t const pps4_disassembler::table[] = { /* 00 */ t_LBL | t_I8c, /* 01 */ t_TML | t_I4 | t_I8, /* 02 */ t_TML | t_I4 | t_I8, @@ -75,8 +75,8 @@ uint16_t const pps4_disassembler::table[] = { /* 05 */ t_RTN | t_OUT, /* 06 */ t_XS, /* 07 */ t_RTNSK | t_OUT, -/* 08 */ t_ADCSK, -/* 09 */ t_ADSK, +/* 08 */ t_ADCSK | t_COND, +/* 09 */ t_ADSK | t_COND, /* 0a */ t_ADC, /* 0b */ t_AD, /* 0c */ t_EOR, @@ -88,18 +88,18 @@ uint16_t const pps4_disassembler::table[] = { /* 11 */ t_LABL, /* 12 */ t_LAX, /* 13 */ t_SAG, -/* 14 */ t_SKF2, -/* 15 */ t_SKC, -/* 16 */ t_SKF1, -/* 17 */ t_INCB, +/* 14 */ t_SKF2 | t_COND, +/* 15 */ t_SKC | t_COND, +/* 16 */ t_SKF1 | t_COND, +/* 17 */ t_INCB | t_COND, /* 18 */ t_XBMX, /* 19 */ t_XABL, /* 1a */ t_XAX, /* 1b */ t_LXA, /* 1c */ t_IOL | t_I8, /* 1d */ t_DOA, -/* 1e */ t_SKZ, -/* 1f */ t_DECB, +/* 1e */ t_SKZ | t_COND, +/* 1f */ t_DECB | t_COND, /* 20 */ t_SC, /* 21 */ t_SF2, @@ -109,14 +109,14 @@ uint16_t const pps4_disassembler::table[] = { /* 25 */ t_RF2, /* 26 */ t_RF1, /* 27 */ t_DIA, -/* 28 */ t_EXD | t_I3c, -/* 29 */ t_EXD | t_I3c, -/* 2a */ t_EXD | t_I3c, -/* 2b */ t_EXD | t_I3c, -/* 2c */ t_EXD | t_I3c, -/* 2d */ t_EXD | t_I3c, -/* 2e */ t_EXD | t_I3c, -/* 2f */ t_EXD | t_I3c, +/* 28 */ t_EXD | t_I3c | t_COND, +/* 29 */ t_EXD | t_I3c | t_COND, +/* 2a */ t_EXD | t_I3c | t_COND, +/* 2b */ t_EXD | t_I3c | t_COND, +/* 2c */ t_EXD | t_I3c | t_COND, +/* 2d */ t_EXD | t_I3c | t_COND, +/* 2e */ t_EXD | t_I3c | t_COND, +/* 2f */ t_EXD | t_I3c | t_COND, /* 30 */ t_LD | t_I3c, /* 31 */ t_LD | t_I3c, @@ -135,22 +135,22 @@ uint16_t const pps4_disassembler::table[] = { /* 3e */ t_EX | t_I3c, /* 3f */ t_EX | t_I3c, -/* 40 */ t_SKBI | t_I4, -/* 41 */ t_SKBI | t_I4, -/* 42 */ t_SKBI | t_I4, -/* 43 */ t_SKBI | t_I4, -/* 44 */ t_SKBI | t_I4, -/* 45 */ t_SKBI | t_I4, -/* 46 */ t_SKBI | t_I4, -/* 47 */ t_SKBI | t_I4, -/* 48 */ t_SKBI | t_I4, -/* 49 */ t_SKBI | t_I4, -/* 4a */ t_SKBI | t_I4, -/* 4b */ t_SKBI | t_I4, -/* 4c */ t_SKBI | t_I4, -/* 4d */ t_SKBI | t_I4, -/* 4e */ t_SKBI | t_I4, -/* 4f */ t_SKBI | t_I4, +/* 40 */ t_SKBI | t_I4 | t_COND, +/* 41 */ t_SKBI | t_I4 | t_COND, +/* 42 */ t_SKBI | t_I4 | t_COND, +/* 43 */ t_SKBI | t_I4 | t_COND, +/* 44 */ t_SKBI | t_I4 | t_COND, +/* 45 */ t_SKBI | t_I4 | t_COND, +/* 46 */ t_SKBI | t_I4 | t_COND, +/* 47 */ t_SKBI | t_I4 | t_COND, +/* 48 */ t_SKBI | t_I4 | t_COND, +/* 49 */ t_SKBI | t_I4 | t_COND, +/* 4a */ t_SKBI | t_I4 | t_COND, +/* 4b */ t_SKBI | t_I4 | t_COND, +/* 4c */ t_SKBI | t_I4 | t_COND, +/* 4d */ t_SKBI | t_I4 | t_COND, +/* 4e */ t_SKBI | t_I4 | t_COND, +/* 4f */ t_SKBI | t_I4 | t_COND, /* 50 */ t_TL | t_I4 | t_I8 | t_OVER, /* 51 */ t_TL | t_I4 | t_I8 | t_OVER, @@ -169,21 +169,21 @@ uint16_t const pps4_disassembler::table[] = { /* 5e */ t_TL | t_I4 | t_I8 | t_OVER, /* 5f */ t_TL | t_I4 | t_I8 | t_OVER, -/* 60 */ t_ADI | t_I4c, -/* 61 */ t_ADI | t_I4c, -/* 62 */ t_ADI | t_I4c, -/* 63 */ t_ADI | t_I4c, -/* 64 */ t_ADI | t_I4c, +/* 60 */ t_ADI | t_I4c | t_COND, +/* 61 */ t_ADI | t_I4c | t_COND, +/* 62 */ t_ADI | t_I4c | t_COND, +/* 63 */ t_ADI | t_I4c | t_COND, +/* 64 */ t_ADI | t_I4c | t_COND, /* 65 */ t_DC, -/* 66 */ t_ADI | t_I4c, -/* 67 */ t_ADI | t_I4c, -/* 68 */ t_ADI | t_I4c, -/* 69 */ t_ADI | t_I4c, -/* 6a */ t_ADI | t_I4c, -/* 6b */ t_ADI | t_I4c, -/* 6c */ t_ADI | t_I4c, -/* 6d */ t_ADI | t_I4c, -/* 6e */ t_ADI | t_I4c, +/* 66 */ t_ADI | t_I4c | t_COND, +/* 67 */ t_ADI | t_I4c | t_COND, +/* 68 */ t_ADI | t_I4c | t_COND, +/* 69 */ t_ADI | t_I4c | t_COND, +/* 6a */ t_ADI | t_I4c | t_COND, +/* 6b */ t_ADI | t_I4c | t_COND, +/* 6c */ t_ADI | t_I4c | t_COND, +/* 6d */ t_ADI | t_I4c | t_COND, +/* 6e */ t_ADI | t_I4c | t_COND, /* 6f */ t_CYS, /* 70 */ t_LDI | t_I4c, diff --git a/src/devices/cpu/pps4/pps4dasm.h b/src/devices/cpu/pps4/pps4dasm.h index 04bfa732144..ee6f88568de 100644 --- a/src/devices/cpu/pps4/pps4dasm.h +++ b/src/devices/cpu/pps4/pps4dasm.h @@ -26,7 +26,7 @@ public: virtual offs_t disassemble(std::ostream &stream, offs_t pc, const data_buffer &opcodes, const data_buffer ¶ms) override; private: - typedef enum pps4_token_e { + typedef enum pps4_token_e : uint32_t { t_AD, t_ADC, t_ADSK, t_ADCSK, t_ADI, t_DC, t_AND, t_OR, t_EOR, t_COMP, t_SC, t_RC, t_SF1, t_RF1, t_SF2, @@ -48,11 +48,12 @@ private: t_I8 = 1 << 12, /* immediate 8 bit constant (I/O port number) */ t_I8c = 1 << 13, /* immediate 8 bit constant inverted */ t_OVER = 1 << 14, /* Debugger step over (CALL) */ - t_OUT = 1 << 15 /* Debugger step out (RETURN) */ + t_OUT = 1 << 15, /* Debugger step out (RETURN) */ + t_COND = 1 << 16 /* Debugger conditional branch */ } pps4_token_e; static char const *const token_str[t_COUNT]; - static uint16_t const table[]; + static uint32_t const table[]; }; diff --git a/src/devices/cpu/pps41/pps41d.cpp b/src/devices/cpu/pps41/pps41d.cpp index ddd764958bc..ef2bfbba148 100644 --- a/src/devices/cpu/pps41/pps41d.cpp +++ b/src/devices/cpu/pps41/pps41d.cpp @@ -77,17 +77,17 @@ const u32 pps41_common_disassembler::s_flags[] = // MM76 0, 0, 0, 0, 0, - 0, 0, 0, + 0, 0, STEP_COND, 0, 0, - 0, 0, 0, 0, - 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, STEP_COND, STEP_COND, + 0, 0, STEP_COND, STEP_COND, 0, 0, 0, STEP_COND, 0, STEP_COND, STEP_OUT, STEP_OUT, 0, 0, 0, STEP_OVER, STEP_OVER, 0, - 0, 0, 0, - 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + STEP_COND, STEP_COND, STEP_COND, + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, STEP_COND, STEP_COND, STEP_COND, STEP_COND, 0, 0, // MM78 - 0, 0, 0, 0, 0, - 0, 0, 0, 0, 0, 0, + STEP_COND, STEP_COND, 0, 0, 0, + STEP_COND, 0, 0, 0, 0, 0, 0, STEP_OVER }; diff --git a/src/devices/cpu/psx/psxdasm.cpp b/src/devices/cpu/psx/psxdasm.cpp index 51a62f6dc1d..bd7c3bcdcae 100644 --- a/src/devices/cpu/psx/psxdasm.cpp +++ b/src/devices/cpu/psx/psxdasm.cpp @@ -303,11 +303,14 @@ offs_t psxcpu_disassembler::disassemble(std::ostream &stream, offs_t pc, const d if( INS_RT( op ) == RT_BLTZAL ) { util::stream_format( stream, "bltzal %s,$%08x", s_cpugenreg[ INS_RS( op ) ], relative_address( pc, op ) ); - flags = STEP_OVER | step_over_extra( 1 ); + if( INS_RS( op ) != 0 ) + flags = STEP_OVER | STEP_COND | step_over_extra( 1 ); } else { util::stream_format( stream, "bltz %s,$%08x", s_cpugenreg[ INS_RS( op ) ], relative_address( pc, op ) ); + if( INS_RS( op ) != 0 ) + flags = STEP_COND | step_over_extra( 1 ); } break; case RT_BGEZ: @@ -315,10 +318,14 @@ offs_t psxcpu_disassembler::disassemble(std::ostream &stream, offs_t pc, const d { util::stream_format( stream, "bgezal %s,$%08x", s_cpugenreg[ INS_RS( op ) ], relative_address( pc, op ) ); flags = STEP_OVER | step_over_extra( 1 ); + if( INS_RS( op ) != 0 ) + flags |= STEP_COND; } else { util::stream_format( stream, "bgez %s,$%08x", s_cpugenreg[ INS_RS( op ) ], relative_address( pc, op ) ); + if( INS_RS( op ) != 0 ) + flags = STEP_COND | step_over_extra( 1 ); } break; } @@ -332,15 +339,19 @@ offs_t psxcpu_disassembler::disassemble(std::ostream &stream, offs_t pc, const d break; case OP_BEQ: util::stream_format( stream, "beq %s,%s,$%08x", s_cpugenreg[ INS_RS( op ) ], s_cpugenreg[ INS_RT( op ) ], relative_address( pc, op ) ); + flags = STEP_COND | step_over_extra( 1 ); break; case OP_BNE: util::stream_format( stream, "bne %s,%s,$%08x", s_cpugenreg[ INS_RS( op ) ], s_cpugenreg[ INS_RT( op ) ], relative_address( pc, op ) ); + flags = STEP_COND | step_over_extra( 1 ); break; case OP_BLEZ: util::stream_format( stream, "blez %s,%s,$%08x", s_cpugenreg[ INS_RS( op ) ], s_cpugenreg[ INS_RT( op ) ], relative_address( pc, op ) ); + flags = STEP_COND | step_over_extra( 1 ); break; case OP_BGTZ: util::stream_format( stream, "bgtz %s,%s,$%08x", s_cpugenreg[ INS_RS( op ) ], s_cpugenreg[ INS_RT( op ) ], relative_address( pc, op ) ); + flags = STEP_COND | step_over_extra( 1 ); break; case OP_ADDI: util::stream_format( stream, "addi %s,%s,%s", s_cpugenreg[ INS_RT( op ) ], s_cpugenreg[ INS_RS( op ) ], make_signed_hex_str_16( INS_IMMEDIATE( op ) ) ); @@ -392,6 +403,7 @@ offs_t psxcpu_disassembler::disassemble(std::ostream &stream, offs_t pc, const d util::stream_format( stream, "bc0t $%08x", relative_address( pc, op ) ); break; } + flags = STEP_COND | step_over_extra( 1 ); break; default: switch( INS_CO( op ) ) @@ -449,6 +461,7 @@ offs_t psxcpu_disassembler::disassemble(std::ostream &stream, offs_t pc, const d util::stream_format( stream, "bc1t $%08x", relative_address( pc, op ) ); break; } + flags = STEP_COND | step_over_extra( 1 ); break; default: switch( INS_CO( op ) ) @@ -486,6 +499,7 @@ offs_t psxcpu_disassembler::disassemble(std::ostream &stream, offs_t pc, const d util::stream_format( stream, "bc2t $%08x", relative_address( pc, op ) ); break; } + flags = STEP_COND | step_over_extra( 1 ); break; default: switch( INS_CO( op ) ) @@ -596,6 +610,7 @@ offs_t psxcpu_disassembler::disassemble(std::ostream &stream, offs_t pc, const d util::stream_format( stream, "bc3t $%08x", relative_address( pc, op ) ); break; } + flags = STEP_COND | step_over_extra( 1 ); break; default: switch( INS_CO( op ) ) diff --git a/src/devices/cpu/rii/riidasm.cpp b/src/devices/cpu/rii/riidasm.cpp index aa8087c6fcc..c376bbcc391 100644 --- a/src/devices/cpu/rii/riidasm.cpp +++ b/src/devices/cpu/rii/riidasm.cpp @@ -412,7 +412,7 @@ offs_t riscii_disassembler::disassemble(std::ostream &stream, offs_t pc, const r format_immediate(stream, opcode & 0x00ff); stream << ","; format_address(stream, (pc & 0x30000) | opcodes.r16(pc + 1)); - words = 2; + words = 2 | STEP_COND; break; case 0x4800: @@ -420,7 +420,7 @@ offs_t riscii_disassembler::disassemble(std::ostream &stream, offs_t pc, const r format_immediate(stream, opcode & 0x00ff); stream << ","; format_address(stream, (pc & 0x30000) | opcodes.r16(pc + 1)); - words = 2; + words = 2 | STEP_COND; break; case 0x4900: @@ -428,7 +428,7 @@ offs_t riscii_disassembler::disassemble(std::ostream &stream, offs_t pc, const r format_immediate(stream, opcode & 0x00ff); stream << ","; format_address(stream, (pc & 0x30000) | opcodes.r16(pc + 1)); - words = 2; + words = 2 | STEP_COND; break; case 0x4a00: @@ -466,7 +466,7 @@ offs_t riscii_disassembler::disassemble(std::ostream &stream, offs_t pc, const r format_register(stream, opcode & 0x00ff); stream << ","; format_address(stream, (pc & 0x30000) | opcodes.r16(pc + 1)); - words = 2; + words = 2 | STEP_COND; break; case 0x5100: @@ -474,7 +474,7 @@ offs_t riscii_disassembler::disassemble(std::ostream &stream, offs_t pc, const r format_register(stream, opcode & 0x00ff); stream << ","; format_address(stream, (pc & 0x30000) | opcodes.r16(pc + 1)); - words = 2; + words = 2 | STEP_COND; break; case 0x5200: @@ -482,7 +482,7 @@ offs_t riscii_disassembler::disassemble(std::ostream &stream, offs_t pc, const r format_register(stream, opcode & 0x00ff); stream << ","; format_address(stream, (pc & 0x30000) | opcodes.r16(pc + 1)); - words = 2; + words = 2 | STEP_COND; break; case 0x5300: @@ -490,7 +490,7 @@ offs_t riscii_disassembler::disassemble(std::ostream &stream, offs_t pc, const r format_register(stream, opcode & 0x00ff); stream << ","; format_address(stream, (pc & 0x30000) | opcodes.r16(pc + 1)); - words = 2; + words = 2 | STEP_COND; break; case 0x5500: @@ -498,7 +498,7 @@ offs_t riscii_disassembler::disassemble(std::ostream &stream, offs_t pc, const r format_register(stream, opcode & 0x00ff); stream << ","; format_address(stream, (pc & 0x30000) | opcodes.r16(pc + 1)); - words = 2; + words = 2 | STEP_COND; break; case 0x5600: @@ -506,7 +506,7 @@ offs_t riscii_disassembler::disassemble(std::ostream &stream, offs_t pc, const r format_register(stream, opcode & 0x00ff); stream << ","; format_address(stream, (pc & 0x30000) | opcodes.r16(pc + 1)); - words = 2; + words = 2 | STEP_COND; break; case 0x5700: @@ -514,7 +514,7 @@ offs_t riscii_disassembler::disassemble(std::ostream &stream, offs_t pc, const r format_register(stream, opcode & 0x00ff); stream << ","; format_address(stream, (pc & 0x30000) | opcodes.r16(pc + 1)); - words = 2; + words = 2 | STEP_COND; break; case 0x5800: case 0x5900: case 0x5a00: case 0x5b00: @@ -523,7 +523,7 @@ offs_t riscii_disassembler::disassemble(std::ostream &stream, offs_t pc, const r format_register(stream, opcode & 0x00ff); util::stream_format(stream, ",%d,", (opcode & 0x0700) >> 8); format_address(stream, (pc & 0x30000) | opcodes.r16(pc + 1)); - words = 2; + words = 2 | STEP_COND; break; case 0x6000: case 0x6100: case 0x6200: case 0x6300: @@ -532,7 +532,7 @@ offs_t riscii_disassembler::disassemble(std::ostream &stream, offs_t pc, const r format_register(stream, opcode & 0x00ff); util::stream_format(stream, ",%d,", (opcode & 0x0700) >> 8); format_address(stream, (pc & 0x30000) | opcodes.r16(pc + 1)); - words = 2; + words = 2 | STEP_COND; break; case 0x6800: case 0x6900: case 0x6a00: case 0x6b00: diff --git a/src/devices/cpu/romp/rompdasm.cpp b/src/devices/cpu/romp/rompdasm.cpp index 213c2f3aacb..9b8386729ea 100644 --- a/src/devices/cpu/romp/rompdasm.cpp +++ b/src/devices/cpu/romp/rompdasm.cpp @@ -43,7 +43,11 @@ offs_t romp_disassembler::disassemble(std::ostream &stream, offs_t pc, data_buff switch (op >> 12) { // JI format - case 0x0: util::stream_format(stream, "j%-4s 0x%x", cc[(op >> 8) & 15], pc + (s32(s8(op)) << 1)); break; // jump on [not] condition bit + case 0x0: // jump on [not] condition bit + util::stream_format(stream, "j%-4s 0x%x", cc[(op >> 8) & 15], pc + (s32(s8(op)) << 1)); + if (((op >> 8) & 7) != 0) + flags = STEP_COND; + break; // DS format case 0x1: util::stream_format(stream, "stcs %s,%s", gpr[R2], R3_0((op >> 8) & 15, R3)); break; // store character short @@ -74,8 +78,16 @@ offs_t romp_disassembler::disassemble(std::ostream &stream, offs_t pc, data_buff case 0x8b: util::stream_format(stream, "balax 0x%x", b & 0x00fffffeU); flags |= STEP_OVER | step_over_extra(1); break; // branch and link absolute with execute case 0x8c: util::stream_format(stream, "bali %s,0x%x", gpr[R2], pc + (s32(b << 12) >> 11)); flags |= STEP_OVER; break; // branch and link immediate case 0x8d: util::stream_format(stream, "balix %s,0x%x", gpr[R2], pc + (s32(b << 12) >> 11)); flags |= STEP_OVER | step_over_extra(1); break; // branch and link immediate with execute - case 0x8e: util::stream_format(stream, "b%-4s 0x%x", cc[N], pc + (s32(b << 12) >> 11)); break; // branch on condition bit immediate - case 0x8f: util::stream_format(stream, "b%-4s 0x%x", util::string_format("%sx", cc[N]), pc + (s32(b << 12) >> 11)); break; // branch on condition bit immediate with execute + case 0x8e: // branch on condition bit immediate + util::stream_format(stream, "b%-4s 0x%x", cc[N], pc + (s32(b << 12) >> 11)); + if (N != 8) + flags |= STEP_COND; + break; + case 0x8f: // branch on condition bit immediate with execute + util::stream_format(stream, "b%-4s 0x%x", util::string_format("%sx", cc[N]), pc + (s32(b << 12) >> 11)); + if (N != 8) + flags |= STEP_COND | step_over_extra(1); + break; } } break; @@ -101,7 +113,11 @@ offs_t romp_disassembler::disassemble(std::ostream &stream, offs_t pc, data_buff case 0xc9: util::stream_format(stream, "lm %s,%s", gpr[R2], R3_0(s16(i), R3)); break; // load multiple case 0xca: util::stream_format(stream, "lha %s,%s", gpr[R2], R3_0(s16(i), R3)); break; // load half algebraic case 0xcb: util::stream_format(stream, "ior %s,%s", gpr[R2], R3_0(s16(i), R3)); break; // input/output read - case 0xcc: util::stream_format(stream, "t%-4s %s,0x%x", tc[R2 & 7], gpr[R3], s16(i)); break; // trap on condition immediate + case 0xcc: // trap on condition immediate + util::stream_format(stream, "t%-4s %s,0x%x", tc[R2 & 7], gpr[R3], s16(i)); + if ((R2 & 7) != 0) + flags |= STEP_OVER | STEP_COND; + break; case 0xcd: util::stream_format(stream, "l %s,%s", gpr[R2], R3_0(s16(i), R3)); break; // load case 0xce: util::stream_format(stream, "lc %s,%s", gpr[R2], R3_0(s16(i), R3)); break; // load character case 0xcf: util::stream_format(stream, "tsh %s,%s", gpr[R2], R3_0(s16(i), R3)); break; // test and set half @@ -190,14 +206,38 @@ offs_t romp_disassembler::disassemble(std::ostream &stream, offs_t pc, data_buff case 0xe5: util::stream_format(stream, "n %s,%s", gpr[R2], gpr[R3]); break; // and case 0xe6: util::stream_format(stream, "m %s,%s", gpr[R2], gpr[R3]); break; // multiply step case 0xe7: util::stream_format(stream, "x %s,%s", gpr[R2], gpr[R3]); break; // exclusive or - case 0xe8: util::stream_format(stream, "b%-5s %s", util::string_format("%sr", cc[N - 8]), gpr[R3]); break; // branch on not condition bit - case 0xe9: util::stream_format(stream, "b%-5s %s", util::string_format("%srx", cc[N - 8]), gpr[R3]); break; // branch on not condition bit with execute + case 0xe8: // branch on not condition bit + util::stream_format(stream, "b%-5s %s", util::string_format("%sr", cc[N - 8]), gpr[R3]); + if (N != 8) + flags |= STEP_COND; + if (R3 == 15) + flags |= STEP_OUT; + break; + case 0xe9: // branch on not condition bit with execute + util::stream_format(stream, "b%-5s %s", util::string_format("%srx", cc[N - 8]), gpr[R3]); + if (N != 8) + flags |= STEP_COND | step_over_extra(1); + if (R3 == 15) + flags |= STEP_OUT | step_over_extra(1); + break; // ea case 0xeb: util::stream_format(stream, "lhs %s,0(%s)", gpr[R2], gpr[R3]); break; // load half short case 0xec: util::stream_format(stream, "balr %s,%s", gpr[R2], gpr[R3]); flags |= STEP_OVER; break; // branch and link case 0xed: util::stream_format(stream, "balrx %s,%s", gpr[R2], gpr[R3]); flags |= STEP_OVER | step_over_extra(1); break; // branch and link with execute - case 0xee: util::stream_format(stream, "b%-5s %s", util::string_format("%sr", cc[N]), gpr[R3]); break; // branch on condition bit - case 0xef: util::stream_format(stream, "b%-5s %s", util::string_format("%srx", cc[N]), gpr[R3]); break; // branch on condition bit with execute + case 0xee: // branch on condition bit + util::stream_format(stream, "b%-5s %s", util::string_format("%sr", cc[N]), gpr[R3]); break; + if (N != 8) + flags |= STEP_COND; + if (R3 == 15) + flags |= STEP_OUT; + break; + case 0xef: // branch on condition bit with execute + util::stream_format(stream, "b%-5s %s", util::string_format("%srx", cc[N]), gpr[R3]); + if (N != 8) + flags |= STEP_COND | step_over_extra(1); + if (R3 == 15) + flags |= STEP_OUT | step_over_extra(1); + break; case 0xf0: util::stream_format(stream, "wait"); break; // wait case 0xf1: util::stream_format(stream, "ae %s,%s", gpr[R2], gpr[R3]); break; // add extended diff --git a/src/devices/cpu/rsp/rsp_dasm.cpp b/src/devices/cpu/rsp/rsp_dasm.cpp index 84647274764..8c266c0df21 100644 --- a/src/devices/cpu/rsp/rsp_dasm.cpp +++ b/src/devices/cpu/rsp/rsp_dasm.cpp @@ -268,7 +268,7 @@ offs_t rsp_disassembler::dasm_one(std::ostream &stream, offs_t pc, u32 op) case 0x04: util::stream_format(stream, "sllv %s, %s, %s", reg[rd], reg[rt], reg[rs]); break; case 0x06: util::stream_format(stream, "srlv %s, %s, %s", reg[rd], reg[rt], reg[rs]); break; case 0x07: util::stream_format(stream, "srav %s, %s, %s", reg[rd], reg[rt], reg[rs]); break; - case 0x08: util::stream_format(stream, "jr %s", reg[rs]); if (rs == 31) flags = STEP_OUT; break; + case 0x08: util::stream_format(stream, "jr %s", reg[rs]); if (rs == 31) flags = STEP_OUT | step_over_extra(1); break; case 0x09: { if (rd == 31) @@ -303,10 +303,10 @@ offs_t rsp_disassembler::dasm_one(std::ostream &stream, offs_t pc, u32 op) { switch ((op >> 16) & 0x1f) { - case 0x00: util::stream_format(stream, "bltz %s, $%08X", reg[rs], pc + 4 + ((int16_t)op << 2)); break; - case 0x01: util::stream_format(stream, "bgez %s, $%08X", reg[rs], pc + 4 + ((int16_t)op << 2)); break; - case 0x10: util::stream_format(stream, "bltzal %s, $%08X", reg[rs], pc + 4 + ((int16_t)op << 2)); break; - case 0x11: util::stream_format(stream, "bgezal %s, $%08X", reg[rs], pc + 4 + ((int16_t)op << 2)); break; + case 0x00: util::stream_format(stream, "bltz %s, $%08X", reg[rs], pc + 4 + ((int16_t)op << 2)); if (rs != 0) flags = STEP_COND | step_over_extra(1); break; + case 0x01: util::stream_format(stream, "bgez %s, $%08X", reg[rs], pc + 4 + ((int16_t)op << 2)); if (rs != 0) flags = STEP_COND | step_over_extra(1); break; + case 0x10: util::stream_format(stream, "bltzal %s, $%08X", reg[rs], pc + 4 + ((int16_t)op << 2)); if (rs != 0) flags = STEP_OVER | STEP_COND | step_over_extra(1); break; + case 0x11: util::stream_format(stream, "bgezal %s, $%08X", reg[rs], pc + 4 + ((int16_t)op << 2)); flags = STEP_OVER | step_over_extra(1); if (rs != 0) flags |= STEP_COND; break; default: util::stream_format(stream, "???"); break; } @@ -315,10 +315,10 @@ offs_t rsp_disassembler::dasm_one(std::ostream &stream, offs_t pc, u32 op) case 0x02: util::stream_format(stream, "j $%08X", (op & 0x03ffffff) << 2); break; case 0x03: util::stream_format(stream, "jal $%08X", (op & 0x03ffffff) << 2); break; - case 0x04: util::stream_format(stream, "beq %s, %s, $%08X", reg[rs], reg[rt], pc + 4 + ((int16_t)(op) << 2)); break; - case 0x05: util::stream_format(stream, "bne %s, %s, $%08X", reg[rs], reg[rt], pc + 4 + ((int16_t)(op) << 2)); break; - case 0x06: util::stream_format(stream, "blez %s, $%08X", reg[rs], pc + 4 + ((int16_t)(op) << 2)); break; - case 0x07: util::stream_format(stream, "bgtz %s, $%08X", reg[rs], pc + 4 + ((int16_t)(op) << 2)); break; + case 0x04: util::stream_format(stream, "beq %s, %s, $%08X", reg[rs], reg[rt], pc + 4 + ((int16_t)(op) << 2)); if (rs != rt) flags = STEP_COND | step_over_extra(1); break; + case 0x05: util::stream_format(stream, "bne %s, %s, $%08X", reg[rs], reg[rt], pc + 4 + ((int16_t)(op) << 2)); if (rs != rt) flags = STEP_COND | step_over_extra(1); break; + case 0x06: util::stream_format(stream, "blez %s, $%08X", reg[rs], pc + 4 + ((int16_t)(op) << 2)); if (rs != 0) flags = STEP_COND | step_over_extra(1); break; + case 0x07: util::stream_format(stream, "bgtz %s, $%08X", reg[rs], pc + 4 + ((int16_t)(op) << 2)); if (rs != 0) flags = STEP_COND | step_over_extra(1); break; case 0x08: util::stream_format(stream, "addi %s, %s, %s", reg[rt], reg[rs], signed_imm16(op)); break; case 0x09: util::stream_format(stream, "addiu %s, %s, %s", reg[rt], reg[rs], signed_imm16(op)); break; case 0x0a: util::stream_format(stream, "slti %s, %s, %s", reg[rt], reg[rs], signed_imm16(op)); break; diff --git a/src/devices/cpu/rx01/rx01dasm.cpp b/src/devices/cpu/rx01/rx01dasm.cpp index 1e8d8692a66..3af1a96c688 100644 --- a/src/devices/cpu/rx01/rx01dasm.cpp +++ b/src/devices/cpu/rx01/rx01dasm.cpp @@ -4,6 +4,10 @@ DEC RX01 microcode disassembler + DEC's firmware listing is based on a modified PDP-8 cross-assembler. + The syntax used here differs slightly to improve the disassembly of + double-length instructions (which the PDP-8 generally lacks). + ***************************************************************************/ #include "emu.h" @@ -67,12 +71,12 @@ offs_t rx01_disassembler::disassemble(std::ostream &stream, offs_t pc, const rx0 if (BIT(opcode, 0)) { stream << " IND"; - return 1 | (BIT(opcode, 7) ? STEP_OVER : 0) | SUPPORTED; + return 1 | STEP_COND | SUPPORTED; } else { util::stream_format(stream, " %04o", ((pc + 2) & 07400) | opcodes.r8(pc + 1)); - return 2 | (BIT(opcode, 7) ? STEP_OVER : 0) | SUPPORTED; + return 2 | STEP_COND | SUPPORTED; } } else if (BIT(opcode, 7)) diff --git a/src/devices/cpu/s2650/2650dasm.cpp b/src/devices/cpu/s2650/2650dasm.cpp index 4947c24cdbc..6b6fdf85095 100644 --- a/src/devices/cpu/s2650/2650dasm.cpp +++ b/src/devices/cpu/s2650/2650dasm.cpp @@ -235,7 +235,7 @@ offs_t s2650_disassembler::disassemble(std::ostream &stream, offs_t pc, const da util::stream_format(stream, "ret %c", cc[rv]); } else util::stream_format(stream, "retc %c", cc[rv]); - flags = STEP_OUT; + flags = STEP_OUT | (rv != 3 ? STEP_COND : 0); break; case 0x18: case 0x19: case 0x1a: case 0x1b: if (z80) { @@ -246,6 +246,8 @@ offs_t s2650_disassembler::disassemble(std::ostream &stream, offs_t pc, const da } else util::stream_format(stream, "bctr,%c %s", cc[rv], REL(pc, params)); pc+=1; + if (rv != 3) + flags = STEP_COND; break; case 0x1c: case 0x1d: case 0x1e: case 0x1f: if (z80) { @@ -256,6 +258,8 @@ offs_t s2650_disassembler::disassemble(std::ostream &stream, offs_t pc, const da } else util::stream_format(stream, "bcta,%c %s", cc[rv], ADR(pc, params)); pc+=2; + if (rv != 3) + flags = STEP_COND; break; case 0x20: case 0x21: case 0x22: case 0x23: util::stream_format(stream, z80 ? "xor r0,r%d" : "eorz,%d", rv); @@ -283,7 +287,7 @@ offs_t s2650_disassembler::disassemble(std::ostream &stream, offs_t pc, const da util::stream_format(stream, "iret %c", cc[rv]); } else util::stream_format(stream, "rete %c", cc[rv]); - flags = STEP_OUT; + flags = STEP_OUT | (rv != 3 ? STEP_COND : 0); break; case 0x38: case 0x39: case 0x3a: case 0x3b: if (z80) { @@ -294,7 +298,7 @@ offs_t s2650_disassembler::disassemble(std::ostream &stream, offs_t pc, const da } else util::stream_format(stream, "bstr,%c %s", cc[rv], REL(pc, params)); pc+=1; - flags = STEP_OVER; + flags = STEP_OVER | (rv != 3 ? STEP_COND : 0); break; case 0x3c: case 0x3d: case 0x3e: case 0x3f: if (z80) { @@ -305,7 +309,7 @@ offs_t s2650_disassembler::disassemble(std::ostream &stream, offs_t pc, const da } else util::stream_format(stream, "bsta,%c %s", cc[rv], ADR(pc, params)); pc+=2; - flags = STEP_OVER; + flags = STEP_OVER | (rv != 3 ? STEP_COND : 0); break; case 0x40: util::stream_format(stream, "halt"); @@ -335,10 +339,12 @@ offs_t s2650_disassembler::disassemble(std::ostream &stream, offs_t pc, const da case 0x58: case 0x59: case 0x5a: case 0x5b: util::stream_format(stream, z80 ? "jrnz r%d,%s" : "brnr,%d %s", rv, REL(pc, params)); pc+=1; + flags = STEP_COND; break; case 0x5c: case 0x5d: case 0x5e: case 0x5f: util::stream_format(stream, z80 ? "jpnz r%d,%s" : "brna,%d %s", rv, ADR(pc, params)); pc+=2; + flags = STEP_COND; break; case 0x60: case 0x61: case 0x62: case 0x63: util::stream_format(stream, z80 ? "or r0,r%d" : "iorz,%d", rv); @@ -377,12 +383,12 @@ offs_t s2650_disassembler::disassemble(std::ostream &stream, offs_t pc, const da case 0x78: case 0x79: case 0x7a: case 0x7b: util::stream_format(stream, z80 ? "call r%d-nz,%s" : "bsnr,%d %s", rv, REL(pc, params)); pc+=1; - flags = STEP_OVER; + flags = STEP_OVER | STEP_COND; break; case 0x7c: case 0x7d: case 0x7e: case 0x7f: util::stream_format(stream, z80 ? "call r%d-nz,%s" : "bsna,%d %s", rv, ADR(pc, params)); pc+=2; - flags = STEP_OVER; + flags = STEP_OVER | STEP_COND; break; case 0x80: case 0x81: case 0x82: case 0x83: util::stream_format(stream, z80 ? "add r0,r%d" : "addz,%d", rv); @@ -414,6 +420,7 @@ offs_t s2650_disassembler::disassemble(std::ostream &stream, offs_t pc, const da case 0x98: case 0x99: case 0x9a: util::stream_format(stream, z80 ? "jr n%c,%s" : "bcfr,%c %s", cc[rv], REL(pc, params)); pc+=1; + flags = STEP_COND; break; case 0x9b: util::stream_format(stream, z80 ? "jr0 %s" : "zbrr %s", REL0(pc, params)); @@ -459,7 +466,7 @@ offs_t s2650_disassembler::disassemble(std::ostream &stream, offs_t pc, const da case 0xb8: case 0xb9: case 0xba: util::stream_format(stream, z80 ? "calr n%c,%s" : "bsfr,%c %s", cc[rv], REL(pc, params)); pc+=1; - flags = STEP_OVER; + flags = STEP_OVER | STEP_COND; break; case 0xbb: util::stream_format(stream, z80 ? "cal0 %s" : "zbsr %s", REL0(pc, params)); @@ -469,7 +476,7 @@ offs_t s2650_disassembler::disassemble(std::ostream &stream, offs_t pc, const da case 0xbc: case 0xbd: case 0xbe: util::stream_format(stream, z80 ? "call n%c,%s" : "bsfa,%c %s", cc[rv], ADR(pc, params)); pc+=2; - flags = STEP_OVER; + flags = STEP_OVER | STEP_COND; break; case 0xbf: util::stream_format(stream, z80 ? "call %s+r3" : "bsxa %s", ADR(pc, params)); @@ -503,12 +510,12 @@ offs_t s2650_disassembler::disassemble(std::ostream &stream, offs_t pc, const da case 0xd8: case 0xd9: case 0xda: case 0xdb: util::stream_format(stream, z80 ? "ijnz r%d,%s" : "birr,%d %s", rv, REL(pc, params)); pc+=1; - flags = STEP_OVER; + flags = STEP_COND; break; case 0xdc: case 0xdd: case 0xde: case 0xdf: util::stream_format(stream, z80 ? "ijnz r%d,%s" : "bira,%d %s", rv, ADR(pc, params)); pc+=2; - flags = STEP_OVER; + flags = STEP_COND; break; case 0xe0: case 0xe1: case 0xe2: case 0xe3: util::stream_format(stream, z80 ? "cp r0,%d" : "comz,%d", rv); @@ -535,12 +542,12 @@ offs_t s2650_disassembler::disassemble(std::ostream &stream, offs_t pc, const da case 0xf8: case 0xf9: case 0xfa: case 0xfb: util::stream_format(stream, z80 ? "djnz r%d,%s" : "bdrr,%d %s", rv, REL(pc, params)); pc+=1; - flags = STEP_OVER; + flags = STEP_COND; break; case 0xfc: case 0xfd: case 0xfe: case 0xff: util::stream_format(stream, z80 ? "djnz r%d,%s" : "bdra,%d %s", rv, ADR(pc, params)); pc+=2; - flags = STEP_OVER; + flags = STEP_COND; break; } return (pc - PC) | flags | SUPPORTED; diff --git a/src/devices/cpu/scudsp/scudsp.cpp b/src/devices/cpu/scudsp/scudsp.cpp index 7db8e88cb80..8be919433d3 100644 --- a/src/devices/cpu/scudsp/scudsp.cpp +++ b/src/devices/cpu/scudsp/scudsp.cpp @@ -453,8 +453,8 @@ void scudsp_cpu_device::scudsp_operation(uint32_t opcode) SET_V(((m_pl.si) ^ (m_acl.si)) & ((m_pl.si) ^ (i3)) & 0x80000000); break; case 0x6: /* AD2 */ - i1 = concat_64((int32_t)m_ph.si,m_pl.si); - i2 = concat_64((int32_t)m_ach.si,m_acl.si); + i1 = util::icat<int64_t>(m_ph.si,m_pl.si); + i2 = util::icat<int64_t>(m_ach.si,m_acl.si); m_alu = i1 + i2; SET_Z((m_alu & s64(0xffffffffffffU)) == 0); SET_S((m_alu & s64(0x800000000000U)) > 0); diff --git a/src/devices/cpu/se3208/se3208dis.cpp b/src/devices/cpu/se3208/se3208dis.cpp index 6a87ed1f6d7..cde334c5d3c 100644 --- a/src/devices/cpu/se3208/se3208dis.cpp +++ b/src/devices/cpu/se3208/se3208dis.cpp @@ -762,7 +762,7 @@ INST(JV) util::stream_format(stream, "JV 0x%x",PC+2+Offset2); CLRFLAG(FLAG_E); - return 0; + return STEP_COND; } INST(JNV) @@ -778,7 +778,7 @@ INST(JNV) util::stream_format(stream, "JNV 0x%x",PC+2+Offset2); CLRFLAG(FLAG_E); - return 0; + return STEP_COND; } INST(JC) @@ -794,7 +794,7 @@ INST(JC) util::stream_format(stream, "JC 0x%x",PC+2+Offset2); CLRFLAG(FLAG_E); - return 0; + return STEP_COND; } INST(JNC) @@ -810,7 +810,7 @@ INST(JNC) util::stream_format(stream, "JNC 0x%x",PC+2+Offset2); CLRFLAG(FLAG_E); - return 0; + return STEP_COND; } INST(JP) @@ -826,7 +826,7 @@ INST(JP) util::stream_format(stream, "JP 0x%x",PC+2+Offset2); CLRFLAG(FLAG_E); - return 0; + return STEP_COND; } INST(JM) @@ -842,7 +842,7 @@ INST(JM) util::stream_format(stream, "JM 0x%x",PC+2+Offset2); CLRFLAG(FLAG_E); - return 0; + return STEP_COND; } INST(JNZ) @@ -858,7 +858,7 @@ INST(JNZ) util::stream_format(stream, "JNZ 0x%x",PC+2+Offset2); CLRFLAG(FLAG_E); - return 0; + return STEP_COND; } INST(JZ) @@ -874,7 +874,7 @@ INST(JZ) util::stream_format(stream, "JZ 0x%x",PC+2+Offset2); CLRFLAG(FLAG_E); - return 0; + return STEP_COND; } INST(JGE) @@ -890,7 +890,7 @@ INST(JGE) util::stream_format(stream, "JGE 0x%x",PC+2+Offset2); CLRFLAG(FLAG_E); - return 0; + return STEP_COND; } INST(JLE) @@ -906,7 +906,7 @@ INST(JLE) util::stream_format(stream, "JLE 0x%x",PC+2+Offset2); CLRFLAG(FLAG_E); - return 0; + return STEP_COND; } INST(JHI) @@ -922,7 +922,7 @@ INST(JHI) util::stream_format(stream, "JHI 0x%x",PC+2+Offset2); CLRFLAG(FLAG_E); - return 0; + return STEP_COND; } INST(JLS) @@ -938,7 +938,7 @@ INST(JLS) util::stream_format(stream, "JLS 0x%x",PC+2+Offset2); CLRFLAG(FLAG_E); - return 0; + return STEP_COND; } INST(JGT) @@ -954,7 +954,7 @@ INST(JGT) util::stream_format(stream, "JGT 0x%x",PC+2+Offset2); CLRFLAG(FLAG_E); - return 0; + return STEP_COND; } INST(JLT) @@ -970,7 +970,7 @@ INST(JLT) util::stream_format(stream, "JLT 0x%x",PC+2+Offset2); CLRFLAG(FLAG_E); - return 0; + return STEP_COND; } diff --git a/src/devices/cpu/sh/sh_dasm.cpp b/src/devices/cpu/sh/sh_dasm.cpp index 5bed1b5c1c9..c7e972385f2 100644 --- a/src/devices/cpu/sh/sh_dasm.cpp +++ b/src/devices/cpu/sh/sh_dasm.cpp @@ -467,16 +467,16 @@ uint32_t sh_disassembler::op1000(std::ostream &stream, uint32_t pc, uint16_t opc break; case 9: util::stream_format(stream, "BT $%08X", pc + SIGNX8(opcode & 0xff) * 2 + 2); - break; + return STEP_COND; case 11: util::stream_format(stream, "BF $%08X", pc + SIGNX8(opcode & 0xff) * 2 + 2); - break; + return STEP_COND; case 13: util::stream_format(stream, "BTS $%08X", pc + SIGNX8(opcode & 0xff) * 2 + 2); - break; + return STEP_COND | step_over_extra(1); case 15: util::stream_format(stream, "BFS $%08X", pc + SIGNX8(opcode & 0xff) * 2 + 2); - break; + return STEP_COND | step_over_extra(1); default : util::stream_format(stream, "invalid $%04X", opcode); } diff --git a/src/devices/cpu/sharc/sharcdsm.cpp b/src/devices/cpu/sharc/sharcdsm.cpp index e5fd3c62f24..7f2a6756bf1 100644 --- a/src/devices/cpu/sharc/sharcdsm.cpp +++ b/src/devices/cpu/sharc/sharcdsm.cpp @@ -710,6 +710,8 @@ uint32_t sharc_disassembler::dasm_direct_jump(std::ostream &stream, uint32_t pc, { util::stream_format(stream, "JUMP"); } + if (cond != 31) + flags |= STEP_COND; if (opcode & 0x10000000000U) /* PC-relative branch */ { @@ -722,6 +724,7 @@ uint32_t sharc_disassembler::dasm_direct_jump(std::ostream &stream, uint32_t pc, if (j) { util::stream_format(stream, " (DB)"); + flags |= step_over_extra(2); } if (ci) { @@ -753,6 +756,8 @@ uint32_t sharc_disassembler::dasm_indirect_jump_compute(std::ostream &stream, ui { util::stream_format(stream, "JUMP"); } + if (cond != 31) + flags |= STEP_COND; if (opcode & 0x10000000000U) /* PC-relative branch */ { @@ -765,6 +770,7 @@ uint32_t sharc_disassembler::dasm_indirect_jump_compute(std::ostream &stream, ui if (j) { util::stream_format(stream, " (DB)"); + flags |= step_over_extra(2); } if (ci) { @@ -795,6 +801,7 @@ uint32_t sharc_disassembler::dasm_indirect_jump_compute_dregdm(std::ostream &str int reladdr = (opcode >> 27) & 0x3f; int dreg = (opcode >> 23) & 0xf; int comp = opcode & 0x7fffff; + uint32_t flags = cond != 31 ? STEP_COND : 0; get_if_condition(stream, cond); util::stream_format(stream, "JUMP"); @@ -822,7 +829,7 @@ uint32_t sharc_disassembler::dasm_indirect_jump_compute_dregdm(std::ostream &str { util::stream_format(stream, "DM(%s, %s) = %s", GET_DAG1_I(dmi), GET_DAG1_M(dmm), GET_DREG(dreg)); } - return 0; + return flags; } uint32_t sharc_disassembler::dasm_rts_compute(std::ostream &stream, uint32_t pc, uint64_t opcode) @@ -832,8 +839,11 @@ uint32_t sharc_disassembler::dasm_rts_compute(std::ostream &stream, uint32_t pc, int lr = (opcode >> 24) & 0x1; int cond = (opcode >> 33) & 0x1f; int comp = opcode & 0x7fffff; + uint32_t flags = STEP_OUT; get_if_condition(stream, cond); + if (cond != 31) + flags |= STEP_COND; if (opcode & 0x10000000000U) { @@ -847,6 +857,7 @@ uint32_t sharc_disassembler::dasm_rts_compute(std::ostream &stream, uint32_t pc, if (j) { util::stream_format(stream, " (DB)"); + flags |= step_over_extra(2); } if (lr) { @@ -863,7 +874,7 @@ uint32_t sharc_disassembler::dasm_rts_compute(std::ostream &stream, uint32_t pc, compute(stream, comp); } - return STEP_OUT; + return flags; } uint32_t sharc_disassembler::dasm_do_until_counter(std::ostream &stream, uint32_t pc, uint64_t opcode) diff --git a/src/devices/cpu/sm510/sm510d.cpp b/src/devices/cpu/sm510/sm510d.cpp index f9234f707e9..9e02a4227ef 100644 --- a/src/devices/cpu/sm510/sm510d.cpp +++ b/src/devices/cpu/sm510/sm510d.cpp @@ -115,31 +115,31 @@ const u32 sm510_common_disassembler::s_flags[] = { // SM510 0, 0, - 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, STEP_COND, STEP_COND, 0, STEP_OUT, STEP_OUT, 0, STEP_OVER, STEP_OVER, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, - 0, 0, 0, 0, 0, 0, 0, - 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 0, STEP_COND, STEP_COND, 0, 0, 0, 0, + STEP_COND, STEP_COND, STEP_COND, STEP_COND, STEP_COND, STEP_COND, STEP_COND, STEP_COND, STEP_COND, STEP_COND, 0, 0, 0, 0, 0, 0, 0, STEP_OVER, 0, 0, 0, 0, 0, // SM500 0, STEP_OUT, STEP_OUT, 0, 0, STEP_OVER, 0, - 0, 0, 0, 0, - 0, 0, 0, + STEP_COND, 0, 0, 0, 0, 0, 0, 0, 0, 0, + STEP_COND, STEP_COND, STEP_COND, // SM530 0, 0, 0, - 0, 0, + STEP_COND, STEP_COND, 0, 0, 0, 0, 0, // SM590 - 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, STEP_OVER, + STEP_COND, 0, 0, 0, 0, 0, 0, 0, 0, STEP_COND, 0, 0, 0, STEP_OVER, 0, 0, 0, 0, 0, 0, STEP_OVER }; diff --git a/src/devices/cpu/sm8500/sm8500d.cpp b/src/devices/cpu/sm8500/sm8500d.cpp index c509e2edd81..4c6a5188312 100644 --- a/src/devices/cpu/sm8500/sm8500d.cpp +++ b/src/devices/cpu/sm8500/sm8500d.cpp @@ -30,9 +30,9 @@ const char *const sm8500_disassembler::s_mnemonic[] = }; const uint32_t sm8500_disassembler::s_flags[] = { - 0, 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, STEP_COND, STEP_COND, 0, 0, 0, 0, 0, 0, 0, 0, STEP_OVER, STEP_OVER, 0, - 0, 0, 0, 0, 0, 0, STEP_OVER, 0, + 0, 0, 0, 0, 0, 0, STEP_COND, 0, 0, 0, 0, 0, 0, STEP_OVER, 0, 0, STEP_OUT, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, STEP_OUT, 0, 0, @@ -576,5 +576,5 @@ offs_t sm8500_disassembler::disassemble(std::ostream &stream, offs_t pc, const d util::stream_format(stream, "%s", s_mnemonic[ instr->mnemonic ]); } - return (pos - pc) | s_flags[instr->mnemonic] | SUPPORTED; + return (pos - pc) | (instr->arguments == AM_cjp && (op & 0x07) != 0 ? STEP_COND : s_flags[instr->mnemonic]) | SUPPORTED; } diff --git a/src/devices/cpu/sparc/sparcdasm.cpp b/src/devices/cpu/sparc/sparcdasm.cpp index ef72969370e..9164c8152af 100644 --- a/src/devices/cpu/sparc/sparcdasm.cpp +++ b/src/devices/cpu/sparc/sparcdasm.cpp @@ -1117,7 +1117,10 @@ offs_t sparc_disassembler::dasm_branch(std::ostream &stream, offs_t pc, uint32_t //const char * const comment(desc.get_comment ? desc.get_comment(m_config, desc.use_cc, pc, op) : nullptr); //if (comment) util::stream_format(stream, " - %s", comment); - return 4 | SUPPORTED; + if ((COND & 7) != 0) + return 4 | STEP_COND | step_over_extra(1) | SUPPORTED; + else + return 4 | SUPPORTED; // branch never or always } diff --git a/src/devices/cpu/spc700/spc700ds.cpp b/src/devices/cpu/spc700/spc700ds.cpp index 9f220b02e26..2d99819e1b4 100644 --- a/src/devices/cpu/spc700/spc700ds.cpp +++ b/src/devices/cpu/spc700/spc700ds.cpp @@ -321,6 +321,8 @@ offs_t spc700_disassembler::disassemble(std::ostream &stream, offs_t pc, const d flags = STEP_OVER; else if (opcode->name == RET || opcode->name == RETI) flags = STEP_OUT; + else if ((opcode->args[0] == REL || opcode->args[1] == REL) && opcode->name != BRA) + flags = STEP_COND; if (opcode->args[0] == DP && (opcode->args[1] == DP || opcode->args[1] == IMM)) { diff --git a/src/devices/cpu/ssem/ssemdasm.cpp b/src/devices/cpu/ssem/ssemdasm.cpp index 43adb44510b..c29f0ae594b 100644 --- a/src/devices/cpu/ssem/ssemdasm.cpp +++ b/src/devices/cpu/ssem/ssemdasm.cpp @@ -66,5 +66,5 @@ offs_t ssem_disassembler::disassemble(std::ostream &stream, offs_t pc, const dat break; } - return 4 | SUPPORTED; + return 4 | (instr == 6 ? STEP_COND : 0) | SUPPORTED; } diff --git a/src/devices/cpu/ssp1601/ssp1601d.cpp b/src/devices/cpu/ssp1601/ssp1601d.cpp index 5b9f3c6ac27..1abe3d61ba8 100644 --- a/src/devices/cpu/ssp1601/ssp1601d.cpp +++ b/src/devices/cpu/ssp1601/ssp1601d.cpp @@ -243,6 +243,8 @@ offs_t ssp1601_disassembler::disassemble(std::ostream &stream, offs_t pc, const case 0x24: util::stream_format(stream, "call %s, %X", get_cond(op), opcodes.r16(pc+1)); flags |= STEP_OVER; + if (((op >> 4) & 0xf) != 0) + flags |= STEP_COND; size = 2; break; @@ -254,6 +256,8 @@ offs_t ssp1601_disassembler::disassemble(std::ostream &stream, offs_t pc, const // bra cond, addr case 0x26: util::stream_format(stream, "bra %s, %X", get_cond(op), opcodes.r16(pc+1)); + if (((op >> 4) & 0xf) != 0) + flags |= STEP_COND; size = 2; break; diff --git a/src/devices/cpu/st62xx/st62xx_dasm.cpp b/src/devices/cpu/st62xx/st62xx_dasm.cpp index 6905a918611..471b56303ea 100644 --- a/src/devices/cpu/st62xx/st62xx_dasm.cpp +++ b/src/devices/cpu/st62xx/st62xx_dasm.cpp @@ -51,6 +51,7 @@ std::string st62xx_disassembler::reg_name(const uint8_t reg) offs_t st62xx_disassembler::disassemble(std::ostream &stream, offs_t pc, const data_buffer &opcodes, const data_buffer ¶ms) { offs_t base_pc = pc; + offs_t flags = 0; const uint8_t op = opcodes.r8(pc); pc++; @@ -63,6 +64,7 @@ offs_t st62xx_disassembler::disassemble(std::ostream &stream, offs_t pc, const d { const int8_t e = ((int8_t)op) >> 3; util::stream_format(stream, "JRNZ $%d", e); + flags = STEP_COND; break; } case 0x01: case 0x11: case 0x21: case 0x31: case 0x41: case 0x51: case 0x61: case 0x71: @@ -72,6 +74,7 @@ offs_t st62xx_disassembler::disassemble(std::ostream &stream, offs_t pc, const d pc++; const uint16_t abc = ((op & 0xf0) >> 4) | (ab << 4); util::stream_format(stream, "CALL %Xh", abc); + flags = STEP_OVER; break; } case 0x09: case 0x19: case 0x29: case 0x39: case 0x49: case 0x59: case 0x69: case 0x79: @@ -90,6 +93,7 @@ offs_t st62xx_disassembler::disassemble(std::ostream &stream, offs_t pc, const d { const int8_t e = ((int8_t)op) >> 3; util::stream_format(stream, "JRNC $%d", e); + flags = STEP_COND; break; } case 0x03: case 0x23: case 0x43: case 0x63: case 0x83: case 0xa3: case 0xc3: case 0xe3: @@ -100,6 +104,7 @@ offs_t st62xx_disassembler::disassemble(std::ostream &stream, offs_t pc, const d const int8_t ee = (int8_t)opcodes.r8(pc); pc++; util::stream_format(stream, "JRR %d,%s,$%Xh", b, reg_name(rr), ee); + flags = STEP_COND; break; } case 0x13: case 0x33: case 0x53: case 0x73: case 0x93: case 0xb3: case 0xd3: case 0xf3: @@ -110,6 +115,7 @@ offs_t st62xx_disassembler::disassemble(std::ostream &stream, offs_t pc, const d const int8_t ee = (int8_t)opcodes.r8(pc); pc++; util::stream_format(stream, "JRS %d,%s,$%Xh", b, reg_name(rr), ee); + flags = STEP_COND; break; } case 0x0b: case 0x2b: case 0x4b: case 0x6b: case 0x8b: case 0xab: case 0xcb: case 0xeb: @@ -135,6 +141,7 @@ offs_t st62xx_disassembler::disassemble(std::ostream &stream, offs_t pc, const d { const int8_t e = ((int8_t)op) >> 3; util::stream_format(stream, "JRZ $%d", e); + flags = STEP_COND; break; } case 0x06: case 0x16: case 0x26: case 0x36: case 0x46: case 0x56: case 0x66: case 0x76: @@ -144,6 +151,7 @@ offs_t st62xx_disassembler::disassemble(std::ostream &stream, offs_t pc, const d { const int8_t e = ((int8_t)op) >> 3; util::stream_format(stream, "JRC $%d", e); + flags = STEP_COND; break; } case 0x15: @@ -193,6 +201,7 @@ offs_t st62xx_disassembler::disassemble(std::ostream &stream, offs_t pc, const d break; case 0x4d: util::stream_format(stream, "RETI"); + flags = STEP_OUT; break; case 0x5d: util::stream_format(stream, "DEC Y"); // y @@ -214,6 +223,7 @@ offs_t st62xx_disassembler::disassemble(std::ostream &stream, offs_t pc, const d break; case 0xcd: util::stream_format(stream, "RET"); + flags = STEP_OUT; break; case 0xdd: util::stream_format(stream, "DEC W"); // w @@ -374,5 +384,5 @@ offs_t st62xx_disassembler::disassemble(std::ostream &stream, offs_t pc, const d break; } - return (pc - base_pc) | SUPPORTED; + return (pc - base_pc) | flags | SUPPORTED; } diff --git a/src/devices/cpu/superfx/sfx_dasm.cpp b/src/devices/cpu/superfx/sfx_dasm.cpp index 48277cc765b..fe7cab98bea 100644 --- a/src/devices/cpu/superfx/sfx_dasm.cpp +++ b/src/devices/cpu/superfx/sfx_dasm.cpp @@ -20,6 +20,7 @@ offs_t superfx_disassembler::disassemble(std::ostream &stream, offs_t pc, const uint16_t alt = m_config->get_alt(); uint8_t bytes_consumed = 1; + offs_t flags = 0; switch(op) { @@ -45,42 +46,52 @@ offs_t superfx_disassembler::disassemble(std::ostream &stream, offs_t pc, const case 0x06: // BLT util::stream_format(stream, "BLT %d", (int)(int8_t)param0); bytes_consumed = 2; + flags = STEP_COND; break; case 0x07: // BGE util::stream_format(stream, "BGE %d", (int)(int8_t)param0); bytes_consumed = 2; + flags = STEP_COND; break; case 0x08: // BNE util::stream_format(stream, "BNE %d", (int)(int8_t)param0); bytes_consumed = 2; + flags = STEP_COND; break; case 0x09: // BEQ util::stream_format(stream, "BEQ %d", (int)(int8_t)param0); bytes_consumed = 2; + flags = STEP_COND; break; case 0x0a: // BPL util::stream_format(stream, "BPL %d", (int)(int8_t)param0); bytes_consumed = 2; + flags = STEP_COND; break; case 0x0b: // BMI util::stream_format(stream, "BMI %d", (int)(int8_t)param0); bytes_consumed = 2; + flags = STEP_COND; break; case 0x0c: // BCC util::stream_format(stream, "BCC %d", (int)(int8_t)param0); bytes_consumed = 2; + flags = STEP_COND; break; case 0x0d: // BCS util::stream_format(stream, "BCS %d", (int)(int8_t)param0); bytes_consumed = 2; + flags = STEP_COND; break; case 0x0e: // BVC util::stream_format(stream, "BVC %d", (int)(int8_t)param0); bytes_consumed = 2; + flags = STEP_COND; break; case 0x0f: // BVS util::stream_format(stream, "BVS %d", (int)(int8_t)param0); bytes_consumed = 2; + flags = STEP_COND; break; case 0x10: case 0x11: case 0x12: case 0x13: case 0x14: case 0x15: case 0x16: case 0x17: @@ -423,5 +434,5 @@ offs_t superfx_disassembler::disassemble(std::ostream &stream, offs_t pc, const break; } - return bytes_consumed | SUPPORTED; + return bytes_consumed | flags | SUPPORTED; } diff --git a/src/devices/cpu/t11/t11dasm.cpp b/src/devices/cpu/t11/t11dasm.cpp index 13705f53477..519916c1a2b 100644 --- a/src/devices/cpu/t11/t11dasm.cpp +++ b/src/devices/cpu/t11/t11dasm.cpp @@ -184,26 +184,32 @@ offs_t t11_disassembler::disassemble(std::ostream &stream, offs_t pc, const data case 0001000: case 0001100: case 0001200: case 0001300: offset = 2 * (int8_t)(op & 0377); util::stream_format(stream, "BNE %06o", (pc + offset) & 0177777); + flags = STEP_COND; break; case 0001400: case 0001500: case 0001600: case 0001700: offset = 2 * (int8_t)(op & 0377); util::stream_format(stream, "BEQ %06o", (pc + offset) & 0177777); + flags = STEP_COND; break; case 0002000: case 0002100: case 0002200: case 0002300: offset = 2 * (int8_t)(op & 0377); util::stream_format(stream, "BGE %06o", (pc + offset) & 0177777); + flags = STEP_COND; break; case 0002400: case 0002500: case 0002600: case 0002700: offset = 2 * (int8_t)(op & 0377); util::stream_format(stream, "BLT %06o", (pc + offset) & 0177777); + flags = STEP_COND; break; case 0003000: case 0003100: case 0003200: case 0003300: offset = 2 * (int8_t)(op & 0377); util::stream_format(stream, "BGT %06o", (pc + offset) & 0177777); + flags = STEP_COND; break; case 0003400: case 0003500: case 0003600: case 0003700: offset = 2 * (int8_t)(op & 0377); util::stream_format(stream, "BLE %06o", (pc + offset) & 0177777); + flags = STEP_COND; break; case 0004000: case 0004100: case 0004200: case 0004300: case 0004400: case 0004500: case 0004600: case 0004700: @@ -359,39 +365,48 @@ offs_t t11_disassembler::disassemble(std::ostream &stream, offs_t pc, const data case 0077000: case 0077100: case 0077200: case 0077300: case 0077400: case 0077500: case 0077600: case 0077700: addr = (pc - 2 * lo) & 0177777; util::stream_format(stream, "SOB %s,%06o", regs[hi & 7], addr); + flags = STEP_COND; break; case 0100000: case 0100100: case 0100200: case 0100300: offset = 2 * (int8_t)(op & 0377); util::stream_format(stream, "BPL %06o", (pc + offset) & 0177777); + flags = STEP_COND; break; case 0100400: case 0100500: case 0100600: case 0100700: offset = 2 * (int8_t)(op & 0377); util::stream_format(stream, "BMI %06o", (pc + offset) & 0177777); + flags = STEP_COND; break; case 0101000: case 0101100: case 0101200: case 0101300: offset = 2 * (int8_t)(op & 0377); util::stream_format(stream, "BHI %06o", (pc + offset) & 0177777); + flags = STEP_COND; break; case 0101400: case 0101500: case 0101600: case 0101700: offset = 2 * (int8_t)(op & 0377); util::stream_format(stream, "BLOS %06o", (pc + offset) & 0177777); + flags = STEP_COND; break; case 0102000: case 0102100: case 0102200: case 0102300: offset = 2 * (int8_t)(op & 0377); util::stream_format(stream, "BVC %06o", (pc + offset) & 0177777); + flags = STEP_COND; break; case 0102400: case 0102500: case 0102600: case 0102700: offset = 2 * (int8_t)(op & 0377); util::stream_format(stream, "BVS %06o", (pc + offset) & 0177777); + flags = STEP_COND; break; case 0103000: case 0103100: case 0103200: case 0103300: offset = 2 * (int8_t)(op & 0377); util::stream_format(stream, "BCC %06o", (pc + offset) & 0177777); + flags = STEP_COND; break; case 0103400: case 0103500: case 0103600: case 0103700: offset = 2 * (int8_t)(op & 0377); util::stream_format(stream, "BCS %06o", (pc + offset) & 0177777); + flags = STEP_COND; break; case 0104000: case 0104100: case 0104200: case 0104300: util::stream_format(stream, "EMT %03o", op & 0377); diff --git a/src/devices/cpu/tlcs870/tlcs870d.cpp b/src/devices/cpu/tlcs870/tlcs870d.cpp index 7900e764158..d4042d43cb5 100644 --- a/src/devices/cpu/tlcs870/tlcs870d.cpp +++ b/src/devices/cpu/tlcs870/tlcs870d.cpp @@ -2268,9 +2268,16 @@ offs_t tlcs870_disassembler::disassemble(std::ostream &stream, offs_t pc, const util::stream_format (stream, "%-5s", op_names[ m_op ] ); + offs_t flags = 0; if (m_param1_type) { disassemble_param(stream, pc, opcodes, params, m_param1_type, m_param1); + if ((m_param1_type & MODE_MASK) == CONDITIONAL) + flags = STEP_COND; + else if (m_op == CALL || m_op == CALLP || m_op == CALLV || m_op == SWI) + flags = STEP_OVER; + else if (m_op == RET || m_op == RETI || m_op == RETN) + flags = STEP_OUT; } if (m_param2_type) @@ -2281,5 +2288,5 @@ offs_t tlcs870_disassembler::disassemble(std::ostream &stream, offs_t pc, const } - return (m_addr - pc) | SUPPORTED; + return (m_addr - pc) | flags | SUPPORTED; } diff --git a/src/devices/cpu/tlcs900/dasm900.cpp b/src/devices/cpu/tlcs900/dasm900.cpp index 71e51273225..af78c98b8e5 100644 --- a/src/devices/cpu/tlcs900/dasm900.cpp +++ b/src/devices/cpu/tlcs900/dasm900.cpp @@ -1822,6 +1822,9 @@ offs_t tlcs900_disassembler::disassemble(std::ostream &stream, offs_t pc, const case M_RETI: flags = STEP_OUT; break; + case M_DJNZ: + flags = STEP_COND; + break; } switch( dasm->operand1 ) @@ -1851,6 +1854,8 @@ offs_t tlcs900_disassembler::disassemble(std::ostream &stream, offs_t pc, const case O_CC: util::stream_format(stream, " %s", s_cond[op & 0x0F]); + if ((op & 0x07) != 0 && dasm->mnemonic != M_SCC) + flags |= STEP_COND; break; case O_CR8: @@ -2037,6 +2042,8 @@ offs_t tlcs900_disassembler::disassemble(std::ostream &stream, offs_t pc, const case O_CC: util::stream_format(stream, ",%s", s_cond[op & 0x0F]); + if ((op & 0x07) != 0 && dasm->mnemonic != M_SCC) + flags |= STEP_COND; break; case O_CR8: diff --git a/src/devices/cpu/tms1000/tms1k_dasm.cpp b/src/devices/cpu/tms1000/tms1k_dasm.cpp index d199ed5ba74..95f2e36e5f1 100644 --- a/src/devices/cpu/tms1000/tms1k_dasm.cpp +++ b/src/devices/cpu/tms1000/tms1k_dasm.cpp @@ -83,7 +83,7 @@ const char *const tms1000_base_disassembler::s_mnemonic[] = const u32 tms1000_base_disassembler::s_flags[] = { 0, - 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, STEP_OVER, 0, + 0, 0, 0, 0, 0, 0, 0, 0, 0, STEP_COND, STEP_OVER | STEP_COND, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, STEP_OUT, 0, 0, 0, 0, diff --git a/src/devices/cpu/tms32010/32010dsm.cpp b/src/devices/cpu/tms32010/32010dsm.cpp index 0f385274f25..087c3613884 100644 --- a/src/devices/cpu/tms32010/32010dsm.cpp +++ b/src/devices/cpu/tms32010/32010dsm.cpp @@ -282,7 +282,11 @@ offs_t tms32010_disassembler::disassemble(std::ostream &stream, offs_t pc, const switch (*cp++) { case 'A': sprintf(num,"%02Xh",a); break; // was $%02X - case 'B': sprintf(num,"%04Xh",b); break; // was $%04X + case 'B': + if (strncmp(cp, "b ", 3) && strncmp(cp, "cal", 3)) + flags = STEP_COND; + sprintf(num,"%04Xh",b); // was $%04X + break; case 'D': sprintf(num,"%02Xh",d); break; case 'K': sprintf(num,"%d",k); break; case 'N': sprintf(num,"%s",nextar[n]); break; diff --git a/src/devices/cpu/tms32025/32025dsm.cpp b/src/devices/cpu/tms32025/32025dsm.cpp index 99640020341..595628e283c 100644 --- a/src/devices/cpu/tms32025/32025dsm.cpp +++ b/src/devices/cpu/tms32025/32025dsm.cpp @@ -440,6 +440,8 @@ offs_t tms32025_disassembler::disassemble(std::ostream &stream, offs_t pc, const flags = STEP_OVER; else if (!strncmp(cp, "ret", 3)) flags = STEP_OUT; + else if ((code & 0xfe000000) == 0x5e000000 || (code >= 0xf0000000 && code < 0xfc000000)) + flags = STEP_COND; while (*cp) { diff --git a/src/devices/cpu/tms32031/dis32031.cpp b/src/devices/cpu/tms32031/dis32031.cpp index 9967e6b8829..b157f437b90 100644 --- a/src/devices/cpu/tms32031/dis32031.cpp +++ b/src/devices/cpu/tms32031/dis32031.cpp @@ -477,6 +477,8 @@ offs_t tms32031_disassembler::disassemble(std::ostream &stream, offs_t pc, const char temp[10]; sprintf(temp, "B%s%s", condition[(op >> 16) & 31], ((op >> 21) & 1) ? "D" : ""); util::stream_format(stream, "%-6s%s", temp, regname[op & 31]); + if (((op >> 16) & 31) != 0) + flags = STEP_COND | ((op >> 21) & 1 ? step_over_extra(1) : 0); break; } @@ -485,6 +487,8 @@ offs_t tms32031_disassembler::disassemble(std::ostream &stream, offs_t pc, const char temp[10]; sprintf(temp, "B%s%s", condition[(op >> 16) & 31], ((op >> 21) & 1) ? "D" : ""); util::stream_format(stream, "%-6s$%06X", temp, (pc + (((op >> 21) & 1) ? 3 : 1) + (int16_t)op) & 0xffffff); + if (((op >> 16) & 31) != 0) + flags = STEP_COND | ((op >> 21) & 1 ? step_over_extra(1) : 0); break; } @@ -494,6 +498,7 @@ offs_t tms32031_disassembler::disassemble(std::ostream &stream, offs_t pc, const char temp[10]; sprintf(temp, "DB%s%s", condition[(op >> 16) & 31], ((op >> 21) & 1) ? "D" : ""); util::stream_format(stream, "%-6sAR%d,%s", temp, (op >> 22) & 7, regname[op & 31]); + flags = STEP_COND | ((op >> 21) & 1 ? step_over_extra(1) : 0); break; } @@ -502,6 +507,7 @@ offs_t tms32031_disassembler::disassemble(std::ostream &stream, offs_t pc, const char temp[10]; sprintf(temp, "DB%s%s", condition[(op >> 16) & 31], ((op >> 21) & 1) ? "D" : ""); util::stream_format(stream, "%-6sAR%d,$%06X", temp, (op >> 22) & 7, (pc + (((op >> 21) & 1) ? 3 : 1) + (int16_t)op) & 0xffffff); + flags = STEP_COND | ((op >> 21) & 1 ? step_over_extra(1) : 0); break; } @@ -537,12 +543,12 @@ offs_t tms32031_disassembler::disassemble(std::ostream &stream, offs_t pc, const case 0x0f0: util::stream_format(stream, "RETI%s", condition[(op >> 16) & 31]); - flags = STEP_OUT; + flags = STEP_OUT | (((op >> 16) & 31) != 0 ? STEP_COND : 0); break; case 0x0f1: util::stream_format(stream, "RETS%s", condition[(op >> 16) & 31]); - flags = STEP_OUT; + flags = STEP_OUT | (((op >> 16) & 31) != 0 ? STEP_COND : 0); break; diff --git a/src/devices/cpu/tms32051/dis32051.cpp b/src/devices/cpu/tms32051/dis32051.cpp index d634ebd37c4..16872495e5d 100644 --- a/src/devices/cpu/tms32051/dis32051.cpp +++ b/src/devices/cpu/tms32051/dis32051.cpp @@ -128,9 +128,10 @@ void tms32051_disassembler::print_condition_codes(bool pp, int zl, int cv, int t } } -void tms32051_disassembler::dasm_group_be(uint16_t opcode, offs_t &npc, const data_buffer &opcodes) +uint32_t tms32051_disassembler::dasm_group_be(uint16_t opcode, offs_t &npc, const data_buffer &opcodes) { int subop = opcode & 0xff; + uint32_t flags = 0; switch (subop) { @@ -186,8 +187,8 @@ void tms32051_disassembler::dasm_group_be(uint16_t opcode, offs_t &npc, const da case 0x4d: util::stream_format(*output, "setc xf"); break; case 0x4e: util::stream_format(*output, "clrc carry"); break; case 0x4f: util::stream_format(*output, "setc carry"); break; - case 0x51: util::stream_format(*output, "trap"); break; - case 0x52: util::stream_format(*output, "nmi"); break; + case 0x51: util::stream_format(*output, "trap"); flags = STEP_OVER; break; + case 0x52: util::stream_format(*output, "nmi"); flags = STEP_OVER; break; case 0x58: util::stream_format(*output, "zpr"); break; case 0x59: util::stream_format(*output, "zap"); break; case 0x5a: util::stream_format(*output, "sath"); break; @@ -200,7 +201,7 @@ void tms32051_disassembler::dasm_group_be(uint16_t opcode, offs_t &npc, const da case 0x74: case 0x75: case 0x76: case 0x77: case 0x78: case 0x79: case 0x7a: case 0x7b: case 0x7c: case 0x7d: case 0x7e: case 0x7f: - util::stream_format(*output, "intr %d", opcode & 0x1f); break; + util::stream_format(*output, "intr %d", opcode & 0x1f); flags = STEP_OVER; break; case 0x80: util::stream_format(*output, "mpy #%04X", FETCH(npc, opcodes)); break; case 0x81: util::stream_format(*output, "and #%04X", FETCH(npc, opcodes) << 16); break; @@ -212,6 +213,7 @@ void tms32051_disassembler::dasm_group_be(uint16_t opcode, offs_t &npc, const da default: util::stream_format(*output, "??? (group be)"); break; } + return flags; } void tms32051_disassembler::dasm_group_bf(uint16_t opcode, offs_t &npc, const data_buffer &opcodes) @@ -376,11 +378,11 @@ offs_t tms32051_disassembler::disassemble(std::ostream &stream, offs_t pc, const case 0x78: util::stream_format(*output, "adrk #%02X", opcode & 0xff); break; case 0x79: util::stream_format(*output, "b %04X, %s", FETCH(npc, opcodes), GET_ADDRESS(1, address)); break; case 0x7a: util::stream_format(*output, "call %04X, %s", FETCH(npc, opcodes), GET_ADDRESS(1, address)); flags = STEP_OVER; break; - case 0x7b: util::stream_format(*output, "banz %04X, %s", FETCH(npc, opcodes), GET_ADDRESS(1, address)); break; + case 0x7b: util::stream_format(*output, "banz %04X, %s", FETCH(npc, opcodes), GET_ADDRESS(1, address)); flags = STEP_COND; break; case 0x7c: util::stream_format(*output, "sbrk #%02X", opcode & 0xff); break; case 0x7d: util::stream_format(*output, "bd %04X, %s", FETCH(npc, opcodes), GET_ADDRESS(1, address)); break; - case 0x7e: util::stream_format(*output, "calld %04X, %s", FETCH(npc, opcodes), GET_ADDRESS(1, address)); flags = STEP_OVER; break; - case 0x7f: util::stream_format(*output, "banzd %04X, %s", FETCH(npc, opcodes), GET_ADDRESS(1, address)); break; + case 0x7e: util::stream_format(*output, "calld %04X, %s", FETCH(npc, opcodes), GET_ADDRESS(1, address)); flags = STEP_OVER | step_over_extra(1); break; + case 0x7f: util::stream_format(*output, "banzd %04X, %s", FETCH(npc, opcodes), GET_ADDRESS(1, address)); flags = STEP_COND | step_over_extra(1); break; case 0x80: case 0x81: case 0x82: case 0x83: case 0x84: case 0x85: case 0x86: case 0x87: @@ -454,7 +456,7 @@ offs_t tms32051_disassembler::disassemble(std::ostream &stream, offs_t pc, const util::stream_format(*output, "ldp #%03X", opcode & 0x1ff); break; } - case 0xbe: dasm_group_be(opcode, npc, opcodes); break; + case 0xbe: flags = dasm_group_be(opcode, npc, opcodes); break; case 0xbf: dasm_group_bf(opcode, npc, opcodes); break; case 0xe0: case 0xe1: case 0xe2: case 0xe3: @@ -467,6 +469,7 @@ offs_t tms32051_disassembler::disassemble(std::ostream &stream, offs_t pc, const util::stream_format(*output, "bcnd %04X", FETCH(npc, opcodes)); print_condition_codes(true, zl, cv, tp); + flags = STEP_COND; break; } @@ -482,6 +485,7 @@ offs_t tms32051_disassembler::disassemble(std::ostream &stream, offs_t pc, const util::stream_format(*output, "xc %d", n); print_condition_codes(true, zl, cv, tp); + flags = STEP_COND; break; } @@ -495,6 +499,7 @@ offs_t tms32051_disassembler::disassemble(std::ostream &stream, offs_t pc, const util::stream_format(*output, "cc %04X", FETCH(npc, opcodes)); print_condition_codes(true, zl, cv, tp); + flags = STEP_OVER | STEP_COND; break; } @@ -509,13 +514,14 @@ offs_t tms32051_disassembler::disassemble(std::ostream &stream, offs_t pc, const if (opcode == 0xef00) { util::stream_format(*output, "ret"); + flags = STEP_OUT; } else { util::stream_format(*output, "retc "); print_condition_codes(false, zl, cv, tp); + flags = STEP_OUT | STEP_COND; } - flags = STEP_OUT; break; } @@ -529,6 +535,7 @@ offs_t tms32051_disassembler::disassemble(std::ostream &stream, offs_t pc, const util::stream_format(*output, "bcndd %04X", FETCH(npc, opcodes)); print_condition_codes(true, zl, cv, tp); + flags = STEP_COND | step_over_extra(1); break; } @@ -542,6 +549,7 @@ offs_t tms32051_disassembler::disassemble(std::ostream &stream, offs_t pc, const util::stream_format(*output, "ccd %04X", FETCH(npc, opcodes)); print_condition_codes(true, zl, cv, tp); + flags = STEP_OVER | STEP_COND | step_over_extra(1); break; } @@ -556,13 +564,14 @@ offs_t tms32051_disassembler::disassemble(std::ostream &stream, offs_t pc, const if (opcode == 0xff00) { util::stream_format(*output, "retd"); + flags = STEP_OUT | step_over_extra(1); } else { util::stream_format(*output, "retcd "); print_condition_codes(false, zl, cv, tp); + flags = STEP_OUT | STEP_COND | step_over_extra(1); } - flags = STEP_OUT; break; } diff --git a/src/devices/cpu/tms32051/dis32051.h b/src/devices/cpu/tms32051/dis32051.h index dd170859bf3..50292afa90e 100644 --- a/src/devices/cpu/tms32051/dis32051.h +++ b/src/devices/cpu/tms32051/dis32051.h @@ -23,7 +23,7 @@ private: std::string GET_ADDRESS(int addr_mode, int address); std::string GET_SHIFT(int shift); void print_condition_codes(bool pp, int zl, int cv, int tp); - void dasm_group_be(uint16_t opcode, offs_t &npc, const data_buffer &opcodes); + uint32_t dasm_group_be(uint16_t opcode, offs_t &npc, const data_buffer &opcodes); void dasm_group_bf(uint16_t opcode, offs_t &npc, const data_buffer &opcodes); std::ostream *output; diff --git a/src/devices/cpu/tms34010/34010dsm.cpp b/src/devices/cpu/tms34010/34010dsm.cpp index cb2fd0ffe4e..c9a580d8528 100644 --- a/src/devices/cpu/tms34010/34010dsm.cpp +++ b/src/devices/cpu/tms34010/34010dsm.cpp @@ -861,7 +861,7 @@ offs_t tms34010_disassembler::disassemble(std::ostream &stream, offs_t pc, const print_des_reg(stream); stream << ","; print_relative(stream, pc, pos, params); - flags = STEP_OVER; + flags = STEP_COND; break; case 0x01a0: @@ -869,7 +869,7 @@ offs_t tms34010_disassembler::disassemble(std::ostream &stream, offs_t pc, const print_des_reg(stream); stream << ","; print_relative(stream, pc, pos, params); - flags = STEP_OVER; + flags = STEP_COND; break; case 0x01c0: @@ -877,7 +877,7 @@ offs_t tms34010_disassembler::disassemble(std::ostream &stream, offs_t pc, const print_des_reg(stream); stream << ","; print_relative(stream, pc, pos, params); - flags = STEP_OVER; + flags = STEP_COND; break; case 0x01e0: @@ -1063,7 +1063,7 @@ offs_t tms34010_disassembler::disassemble(std::ostream &stream, offs_t pc, const print_des_reg(stream); stream << ","; print_relative_5bit(stream, pc); - flags = STEP_OVER; + flags = STEP_COND; break; @@ -1465,6 +1465,8 @@ offs_t tms34010_disassembler::disassemble(std::ostream &stream, offs_t pc, const util::stream_format(stream, "JR"); } + if ((op & 0x0f00) != 0) + flags = STEP_COND; print_condition_code(stream); stream << " "; diff --git a/src/devices/cpu/tms7000/7000dasm.cpp b/src/devices/cpu/tms7000/7000dasm.cpp index a55b95feeda..f38643c38d5 100644 --- a/src/devices/cpu/tms7000/7000dasm.cpp +++ b/src/devices/cpu/tms7000/7000dasm.cpp @@ -102,29 +102,29 @@ const tms7000_disassembler::tms7000_opcodeinfo tms7000_disassembler::opcs[] = { {0x9C, "BR", 45, 0 }, {0xAC, "BR", 12, 0 }, - {0x66, "BTJO", 13, 0 }, - {0x16, "BTJO", 14, 0 }, - {0x36, "BTJO", 15, 0 }, - {0x46, "BTJO", 16, 0 }, - {0x26, "BTJO", 17, 0 }, - {0x56, "BTJO", 18, 0 }, - {0x76, "BTJO", 19, 0 }, - - {0x86, "BTJOP", 20, 0 }, - {0x96, "BTJOP", 21, 0 }, - {0xA6, "BTJOP", 22, 0 }, - - {0x67, "BTJZ", 13, 0 }, - {0x17, "BTJZ", 14, 0 }, - {0x37, "BTJZ", 15, 0 }, - {0x47, "BTJZ", 16, 0 }, - {0x27, "BTJZ", 17, 0 }, - {0x57, "BTJZ", 18, 0 }, - {0x77, "BTJZ", 19, 0 }, - - {0x87, "BTJZP", 20, 0 }, - {0x97, "BTJZP", 21, 0 }, - {0xA7, "BTJZP", 22, 0 }, + {0x66, "BTJO", 13, STEP_COND }, + {0x16, "BTJO", 14, STEP_COND }, + {0x36, "BTJO", 15, STEP_COND }, + {0x46, "BTJO", 16, STEP_COND }, + {0x26, "BTJO", 17, STEP_COND }, + {0x56, "BTJO", 18, STEP_COND }, + {0x76, "BTJO", 19, STEP_COND }, + + {0x86, "BTJOP", 20, STEP_COND }, + {0x96, "BTJOP", 21, STEP_COND }, + {0xA6, "BTJOP", 22, STEP_COND }, + + {0x67, "BTJZ", 13, STEP_COND }, + {0x17, "BTJZ", 14, STEP_COND }, + {0x37, "BTJZ", 15, STEP_COND }, + {0x47, "BTJZ", 16, STEP_COND }, + {0x27, "BTJZ", 17, STEP_COND }, + {0x57, "BTJZ", 18, STEP_COND }, + {0x77, "BTJZ", 19, STEP_COND }, + + {0x87, "BTJZP", 20, STEP_COND }, + {0x97, "BTJZP", 21, STEP_COND }, + {0xA7, "BTJZP", 22, STEP_COND }, {0x8E, "CALL", 43, STEP_OVER }, {0x9E, "CALL", 45, STEP_OVER }, @@ -166,9 +166,9 @@ const tms7000_disassembler::tms7000_opcodeinfo tms7000_disassembler::opcs[] = { {0x06, "DINT", 23, 0 }, - {0xBA, "DJNZ", 25, 0 }, - {0xCA, "DJNZ", 26, 0 }, - {0xDA, "DJNZ", 27, 0 }, + {0xBA, "DJNZ", 25, STEP_COND }, + {0xCA, "DJNZ", 26, STEP_COND }, + {0xDA, "DJNZ", 27, STEP_COND }, {0x6F, "DSB", 0, 0 }, {0x1F, "DSB", 1, 0 }, @@ -190,14 +190,14 @@ const tms7000_disassembler::tms7000_opcodeinfo tms7000_disassembler::opcs[] = { {0xC4, "INV B", 23, 0 }, {0xD4, "INV", 24, 0 }, - {0xE2, "JEQ", 28, 0 }, - {0xE3, "JHS", 28, 0 }, - {0xE7, "JL", 28, 0 }, + {0xE2, "JEQ", 28, STEP_COND }, + {0xE3, "JHS", 28, STEP_COND }, + {0xE7, "JL", 28, STEP_COND }, {0xE0, "JMP", 28, 0 }, - {0xE1, "JN", 28, 0 }, - {0xE6, "JNZ", 28, 0 }, - {0xE4, "JP", 28, 0 }, - {0xE5, "JPZ", 28, 0 }, + {0xE1, "JN", 28, STEP_COND }, + {0xE6, "JNZ", 28, STEP_COND }, + {0xE4, "JP", 28, STEP_COND }, + {0xE5, "JPZ", 28, STEP_COND }, {0x8A, "LDA", 10, 0 }, {0x9A, "LDA", 45, 0 }, diff --git a/src/devices/cpu/tms9900/9900dasm.cpp b/src/devices/cpu/tms9900/9900dasm.cpp index 633e1abe690..556eead78c3 100644 --- a/src/devices/cpu/tms9900/9900dasm.cpp +++ b/src/devices/cpu/tms9900/9900dasm.cpp @@ -412,6 +412,8 @@ offs_t tms9900_disassembler::disassemble(std::ostream &stream, offs_t pc, const case format_2a: /* jump instructions */ displacement = (signed char)BITS(OP,8,15); util::stream_format(stream, "%-4s >%04x", mnemonic, 0xffff & (PC + displacement * 2)); + if (opc != _jmp) + dasmflags |= STEP_COND; break; case format_2b: /* bit I/O instructions */ diff --git a/src/devices/cpu/tx0/tx0dasm.cpp b/src/devices/cpu/tx0/tx0dasm.cpp index 1c6ca3e5d7c..fedef573ce7 100644 --- a/src/devices/cpu/tx0/tx0dasm.cpp +++ b/src/devices/cpu/tx0/tx0dasm.cpp @@ -118,6 +118,8 @@ offs_t tx0_64kw_disassembler::disassemble(std::ostream &stream, offs_t pc, const { // Addressable instructions (only 3 in this version) util::stream_format(stream, "%s %06o", s_addressable_insts[(inst & 0600000) >> 13], inst & 0177777); + if (inst >= 0400000) // trn + return 1 | STEP_COND | SUPPORTED; } else dasm_opr(stream, inst); @@ -301,6 +303,8 @@ offs_t tx0_8kwo_disassembler::disassemble(std::ostream &stream, offs_t pc, const util::stream_format(stream, "%06o", inst); else util::stream_format(stream, "%s %05o", s_addressable_insts[(inst & 0700000) >> 13], inst & 017777); + if ((inst & 0700000) == 0400000) // trn + return 1 | STEP_COND | SUPPORTED; } else switch (inst) { @@ -346,10 +350,15 @@ offs_t tx0_8kw_disassembler::disassemble(std::ostream &stream, offs_t pc, const { util::stream_format(stream, "%s %05o", str, inst & 017777); - if ((inst & 0760000) == 0440000) // tsx - return 1 | STEP_OVER | SUPPORTED; - else if ((inst & 0760000) == 0520000) // trx - return 1 | STEP_OUT | SUPPORTED; + if (inst >= 0400000) + { + if ((inst & 0760000) == 0440000) // tsx + return 1 | STEP_OVER | SUPPORTED; + else if ((inst & 0760000) == 0520000) // trx + return 1 | STEP_OUT | SUPPORTED; + else if ((inst & 0760000) != 0500000) // trn, tze, tix, tlv + return 1 | STEP_COND | SUPPORTED; + } } } else if ((inst & 037000) == 004000) diff --git a/src/devices/cpu/ucom4/ucom4d.cpp b/src/devices/cpu/ucom4/ucom4d.cpp index 659cee45cab..43488f82241 100644 --- a/src/devices/cpu/ucom4/ucom4d.cpp +++ b/src/devices/cpu/ucom4/ucom4d.cpp @@ -40,13 +40,13 @@ const u32 ucom4_disassembler::s_flags[] = { 0, 0, 0, 0, 0, 0, 0, 0, 0, - 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, - 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 0, STEP_COND, STEP_COND, 0, STEP_COND, STEP_COND, STEP_COND, 0, STEP_COND, 0, 0, + 0, 0, 0, 0, 0, 0, STEP_COND, STEP_COND, STEP_COND, STEP_COND, STEP_COND, 0, 0, 0, 0, 0, 0, 0, 0, 0, STEP_OVER, STEP_OVER, STEP_OUT, STEP_OUT, - 0, 0, 0, 0, 0, 0, 0, 0, - 0, 0, 0, 0, 0, 0, 0, + STEP_COND, STEP_COND, STEP_COND, STEP_COND, STEP_COND, STEP_COND, STEP_COND, STEP_COND, + STEP_COND, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, - 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 + 0, 0, STEP_COND, STEP_COND, 0, STEP_COND, STEP_COND, 0, STEP_COND, 0, 0 }; diff --git a/src/devices/cpu/upd7725/dasm7725.cpp b/src/devices/cpu/upd7725/dasm7725.cpp index 4298b5d3930..12d6b0e36e8 100644 --- a/src/devices/cpu/upd7725/dasm7725.cpp +++ b/src/devices/cpu/upd7725/dasm7725.cpp @@ -21,6 +21,7 @@ offs_t necdsp_disassembler::disassemble(std::ostream &stream, offs_t pc, const d { uint32_t opcode = opcodes.r32(pc) >> 8; uint32_t type = (opcode >> 22); + offs_t flags = 0; // printf("dasm: PC %x opcode %08x\n", pc, opcode); @@ -145,6 +146,7 @@ offs_t necdsp_disassembler::disassemble(std::ostream &stream, offs_t pc, const d if(type == 1) { stream << " | ret"; + flags = STEP_OUT; } } @@ -154,44 +156,44 @@ offs_t necdsp_disassembler::disassemble(std::ostream &stream, offs_t pc, const d switch(brch) { case 0x000: stream << "jmpso "; break; - case 0x080: stream << "jnca "; break; - case 0x082: stream << "jca "; break; - case 0x084: stream << "jncb "; break; - case 0x086: stream << "jcb "; break; - case 0x088: stream << "jnza "; break; - case 0x08a: stream << "jza "; break; - case 0x08c: stream << "jnzb "; break; - case 0x08e: stream << "jzb "; break; - case 0x090: stream << "jnova0 "; break; - case 0x092: stream << "jova0 "; break; - case 0x094: stream << "jnovb0 "; break; - case 0x096: stream << "jovb0 "; break; - case 0x098: stream << "jnova1 "; break; - case 0x09a: stream << "jova1 "; break; - case 0x09c: stream << "jnovb1 "; break; - case 0x09e: stream << "jovb1 "; break; - case 0x0a0: stream << "jnsa0 "; break; - case 0x0a2: stream << "jsa0 "; break; - case 0x0a4: stream << "jnsb0 "; break; - case 0x0a6: stream << "jsb0 "; break; - case 0x0a8: stream << "jnsa1 "; break; - case 0x0aa: stream << "jsa1 "; break; - case 0x0ac: stream << "jnsb1 "; break; - case 0x0ae: stream << "jsb1 "; break; - case 0x0b0: stream << "jdpl0 "; break; - case 0x0b1: stream << "jdpln0 "; break; - case 0x0b2: stream << "jdplf "; break; - case 0x0b3: stream << "jdplnf "; break; - case 0x0b4: stream << "jnsiak "; break; - case 0x0b6: stream << "jsiak "; break; - case 0x0b8: stream << "jnsoak "; break; - case 0x0ba: stream << "jsoak "; break; - case 0x0bc: stream << "jnrqm "; break; - case 0x0be: stream << "jrqm "; break; + case 0x080: stream << "jnca "; flags = STEP_COND; break; + case 0x082: stream << "jca "; flags = STEP_COND; break; + case 0x084: stream << "jncb "; flags = STEP_COND; break; + case 0x086: stream << "jcb "; flags = STEP_COND; break; + case 0x088: stream << "jnza "; flags = STEP_COND; break; + case 0x08a: stream << "jza "; flags = STEP_COND; break; + case 0x08c: stream << "jnzb "; flags = STEP_COND; break; + case 0x08e: stream << "jzb "; flags = STEP_COND; break; + case 0x090: stream << "jnova0 "; flags = STEP_COND; break; + case 0x092: stream << "jova0 "; flags = STEP_COND; break; + case 0x094: stream << "jnovb0 "; flags = STEP_COND; break; + case 0x096: stream << "jovb0 "; flags = STEP_COND; break; + case 0x098: stream << "jnova1 "; flags = STEP_COND; break; + case 0x09a: stream << "jova1 "; flags = STEP_COND; break; + case 0x09c: stream << "jnovb1 "; flags = STEP_COND; break; + case 0x09e: stream << "jovb1 "; flags = STEP_COND; break; + case 0x0a0: stream << "jnsa0 "; flags = STEP_COND; break; + case 0x0a2: stream << "jsa0 "; flags = STEP_COND; break; + case 0x0a4: stream << "jnsb0 "; flags = STEP_COND; break; + case 0x0a6: stream << "jsb0 "; flags = STEP_COND; break; + case 0x0a8: stream << "jnsa1 "; flags = STEP_COND; break; + case 0x0aa: stream << "jsa1 "; flags = STEP_COND; break; + case 0x0ac: stream << "jnsb1 "; flags = STEP_COND; break; + case 0x0ae: stream << "jsb1 "; flags = STEP_COND; break; + case 0x0b0: stream << "jdpl0 "; flags = STEP_COND; break; + case 0x0b1: stream << "jdpln0 "; flags = STEP_COND; break; + case 0x0b2: stream << "jdplf "; flags = STEP_COND; break; + case 0x0b3: stream << "jdplnf "; flags = STEP_COND; break; + case 0x0b4: stream << "jnsiak "; flags = STEP_COND; break; + case 0x0b6: stream << "jsiak "; flags = STEP_COND; break; + case 0x0b8: stream << "jnsoak "; flags = STEP_COND; break; + case 0x0ba: stream << "jsoak "; flags = STEP_COND; break; + case 0x0bc: stream << "jnrqm "; flags = STEP_COND; break; + case 0x0be: stream << "jrqm "; flags = STEP_COND; break; case 0x100: stream << "ljmp "; break; case 0x101: stream << "hjmp "; break; - case 0x140: stream << "lcall "; break; - case 0x141: stream << "hcall "; break; + case 0x140: stream << "lcall "; flags = STEP_OVER; break; + case 0x141: stream << "hcall "; flags = STEP_OVER; break; default: stream << "?????? "; break; } @@ -225,5 +227,5 @@ offs_t necdsp_disassembler::disassemble(std::ostream &stream, offs_t pc, const d } } - return 1 | SUPPORTED; + return 1 | flags | SUPPORTED; } diff --git a/src/devices/cpu/upd78k/upd78k0d.cpp b/src/devices/cpu/upd78k/upd78k0d.cpp index 233b5fbdd50..b13050c1d85 100644 --- a/src/devices/cpu/upd78k/upd78k0d.cpp +++ b/src/devices/cpu/upd78k/upd78k0d.cpp @@ -48,7 +48,7 @@ offs_t upd78k0_disassembler::dasm_31(std::ostream &stream, offs_t pc, const upd7 util::stream_format(stream, ".%d,", (op2 & 0x70) >> 4); } format_jdisp8(stream, pc + 4, opcodes.r8(pc + 3)); - return 4 | SUPPORTED; + return 4 | STEP_COND | SUPPORTED; } else switch (op2 & 0x0f) { @@ -57,36 +57,36 @@ offs_t upd78k0_disassembler::dasm_31(std::ostream &stream, offs_t pc, const upd7 format_sfr(stream, opcodes.r8(pc + 2)); util::stream_format(stream, ".%d,", (op2 & 0x70) >> 4); format_jdisp8(stream, pc + 4, opcodes.r8(pc + 3)); - return 4 | SUPPORTED; + return 4 | STEP_COND | SUPPORTED; case 0x06: util::stream_format(stream, "%-8s", "BT"); format_sfr(stream, opcodes.r8(pc + 2)); util::stream_format(stream, ".%d,", (op2 & 0x70) >> 4); format_jdisp8(stream, pc + 4, opcodes.r8(pc + 3)); - return 4 | SUPPORTED; + return 4 | STEP_COND | SUPPORTED; case 0x07: util::stream_format(stream, "%-8s", "BF"); format_sfr(stream, opcodes.r8(pc + 2)); util::stream_format(stream, ".%d,", (op2 & 0x70) >> 4); format_jdisp8(stream, pc + 4, opcodes.r8(pc + 3)); - return 4 | SUPPORTED; + return 4 | STEP_COND | SUPPORTED; case 0x0d: util::stream_format(stream, "%-8sA.%d,", "BTCLR", (op2 & 0x70) >> 4); format_jdisp8(stream, pc + 3, opcodes.r8(pc + 2)); - return 3 | SUPPORTED; + return 3 | STEP_COND | SUPPORTED; case 0x0e: util::stream_format(stream, "%-8sA.%d,", "BT", (op2 & 0x70) >> 4); format_jdisp8(stream, pc + 3, opcodes.r8(pc + 2)); - return 3 | SUPPORTED; + return 3 | STEP_COND | SUPPORTED; case 0x0f: util::stream_format(stream, "%-8sA.%d,", "BF", (op2 & 0x70) >> 4); format_jdisp8(stream, pc + 3, opcodes.r8(pc + 2)); - return 3 | SUPPORTED; + return 3 | STEP_COND | SUPPORTED; default: return dasm_illegal2(stream, 0x31, op2); @@ -117,17 +117,17 @@ offs_t upd78k0_disassembler::dasm_31(std::ostream &stream, offs_t pc, const upd7 case 0x05: util::stream_format(stream, "%-8s[HL].%d,", "BTCLR", (op2 & 0x70) >> 4); format_jdisp8(stream, pc + 3, opcodes.r8(pc + 2)); - return 3 | SUPPORTED; + return 3 | STEP_COND | SUPPORTED; case 0x06: util::stream_format(stream, "%-8s[HL].%d,", "BT", (op2 & 0x70) >> 4); format_jdisp8(stream, pc + 3, opcodes.r8(pc + 2)); - return 3 | SUPPORTED; + return 3 | STEP_COND | SUPPORTED; case 0x07: util::stream_format(stream, "%-8s[HL].%d,", "BF", (op2 & 0x70) >> 4); format_jdisp8(stream, pc + 3, opcodes.r8(pc + 2)); - return 3 | SUPPORTED; + return 3 | STEP_COND | SUPPORTED; case 0x0a: case 0x0b: if (op2 < 0x90) @@ -305,7 +305,7 @@ offs_t upd78k0_disassembler::disassemble(std::ostream &stream, offs_t pc, const format_saddr(stream, opcodes.r8(pc + 1)); stream << ","; format_jdisp8(stream, pc + 3, opcodes.r8(pc + 2)); - return 3 | SUPPORTED; + return 3 | STEP_COND | SUPPORTED; case 0x05: case 0x07: util::stream_format(stream, "%-8sA,[%s]", "XCH", s_rp_names[(op & 0x06) >> 1]); @@ -470,7 +470,7 @@ offs_t upd78k0_disassembler::disassemble(std::ostream &stream, offs_t pc, const case 0x8a: case 0x8b: util::stream_format(stream, "%-8s%s,", "DBNZ", s_r_names[op & 0x07]); format_jdisp8(stream, pc + 2, opcodes.r8(pc + 1)); - return 2 | SUPPORTED; + return 2 | STEP_COND | SUPPORTED; case 0x8c: case 0x9c: case 0xac: case 0xbc: case 0xcc: case 0xdc: case 0xec: case 0xfc: { @@ -484,13 +484,13 @@ offs_t upd78k0_disassembler::disassemble(std::ostream &stream, offs_t pc, const util::stream_format(stream, ".%d,", (op & 0x70) >> 4); } format_jdisp8(stream, pc + 3, opcodes.r8(pc + 2)); - return 3 | SUPPORTED; + return 3 | STEP_COND | SUPPORTED; } case 0x8d: case 0x9d: util::stream_format(stream, "%-8s", BIT(op, 4) ? "BNC" : "BC"); format_jdisp8(stream, pc + 2, opcodes.r8(pc + 1)); - return 2 | SUPPORTED; + return 2 | STEP_COND | SUPPORTED; case 0x8e: util::stream_format(stream, "%-8sA,", "MOV"); @@ -550,7 +550,7 @@ offs_t upd78k0_disassembler::disassemble(std::ostream &stream, offs_t pc, const case 0xad: case 0xbd: util::stream_format(stream, "%-8s", BIT(op, 4) ? "BNZ" : "BZ"); format_jdisp8(stream, pc + 2, opcodes.r8(pc + 1)); - return 2 | SUPPORTED; + return 2 | STEP_COND | SUPPORTED; case 0xae: util::stream_format(stream, "%-8sA,", "MOV"); diff --git a/src/devices/cpu/upd78k/upd78k1d.cpp b/src/devices/cpu/upd78k/upd78k1d.cpp index e3c8dc80625..e43a09d71f5 100644 --- a/src/devices/cpu/upd78k/upd78k1d.cpp +++ b/src/devices/cpu/upd78k/upd78k1d.cpp @@ -123,7 +123,7 @@ offs_t upd78k1_disassembler::dasm_02xx(std::ostream &stream, u8 op1, u8 op2, off else util::stream_format(stream, "%s,", s_psw_bits[op2 & 0x07]); format_jdisp8(stream, pc + 3, opcodes.r8(pc + 2)); - return 3 | SUPPORTED; + return 3 | STEP_COND | SUPPORTED; } else return dasm_illegal2(stream, op1, op2); @@ -211,7 +211,7 @@ offs_t upd78k1_disassembler::dasm_08xx(std::ostream &stream, u8 op2, offs_t pc, format_saddr(stream, opcodes.r8(pc + 2)); util::stream_format(stream, ".%d,", op2 & 0x07); format_jdisp8(stream, pc + 4, opcodes.r8(pc + 3)); - return 4 | SUPPORTED; + return 4 | STEP_COND | SUPPORTED; } else return dasm_illegal2(stream, 0x08, op2); @@ -546,7 +546,7 @@ offs_t upd78k1_disassembler::disassemble(std::ostream &stream, offs_t pc, const { util::stream_format(stream, "%-8s%s,", "DBNZ", s_r_names[op & 0x07]); format_jdisp8(stream, pc + 2, opcodes.r8(pc + 1)); - return 2 | SUPPORTED; + return 2 | STEP_COND | SUPPORTED; } else { @@ -577,10 +577,15 @@ offs_t upd78k1_disassembler::disassemble(std::ostream &stream, offs_t pc, const format_saddr(stream, opcodes.r8(pc + 1)); stream << ","; if (BIT(op, 0)) + { format_jdisp8(stream, pc + 3, opcodes.r8(pc + 2)); + return 3 | STEP_COND | SUPPORTED; + } else + { format_imm8(stream, opcodes.r8(pc + 2)); - return 3 | SUPPORTED; + return 3 | SUPPORTED; + } } else return dasm_38(stream, op, pc, opcodes); @@ -641,7 +646,7 @@ offs_t upd78k1_disassembler::disassemble(std::ostream &stream, offs_t pc, const format_saddr(stream, opcodes.r8(pc + 1)); util::stream_format(stream, ".%d,", op & 0x07); format_jdisp8(stream, pc + 3, opcodes.r8(pc + 2)); - return 3 | SUPPORTED; + return 3 | STEP_COND | SUPPORTED; case 0x78: return dasm_78(stream, op, pc, opcodes); @@ -653,7 +658,7 @@ offs_t upd78k1_disassembler::disassemble(std::ostream &stream, offs_t pc, const { util::stream_format(stream, "%-8s", s_bcond[op & 0x03]); format_jdisp8(stream, pc + 2, opcodes.r8(pc + 1)); - return 2 | SUPPORTED; + return 2 | STEP_COND | SUPPORTED; } case 0x88: diff --git a/src/devices/cpu/upd78k/upd78k3d.cpp b/src/devices/cpu/upd78k/upd78k3d.cpp index 0adfd848cfd..e209e213d06 100644 --- a/src/devices/cpu/upd78k/upd78k3d.cpp +++ b/src/devices/cpu/upd78k/upd78k3d.cpp @@ -235,7 +235,7 @@ offs_t upd78k3_disassembler::dasm_02xx(std::ostream &stream, u8 op1, u8 op2, off else util::stream_format(stream, "%s,", m_psw_bits[op2 & 0x0f]); format_jdisp8(stream, pc + 3, opcodes.r8(pc + 2)); - return 3 | SUPPORTED; + return 3 | STEP_COND | SUPPORTED; } else return dasm_illegal2(stream, op1, op2); @@ -332,7 +332,7 @@ offs_t upd78k3_disassembler::dasm_07xx(std::ostream &stream, u8 op2, offs_t pc, { util::stream_format(stream, "%-8s", s_bcond_07f8[op2 & 0x07]); format_jdisp8(stream, pc + 3, opcodes.r8(pc + 2)); - return 3 | SUPPORTED; + return 3 | STEP_COND | SUPPORTED; } else if ((op2 & 0xce) == 0xc8) { @@ -409,7 +409,7 @@ offs_t upd78k3_disassembler::dasm_08xx(std::ostream &stream, u8 op2, offs_t pc, format_saddr(stream, opcodes.r8(pc + 2)); util::stream_format(stream, ".%d,", op2 & 0x07); format_jdisp8(stream, pc + 4, opcodes.r8(pc + 3)); - return 4 | SUPPORTED; + return 4 | STEP_COND | SUPPORTED; } else return dasm_illegal2(stream, 0x08, op2); @@ -937,7 +937,7 @@ offs_t upd78k3_disassembler::disassemble(std::ostream &stream, offs_t pc, const { util::stream_format(stream, "%-8s%c,", "DBNZ", BIT(op, 0) ? 'B' : 'C'); format_jdisp8(stream, pc + 2, opcodes.r8(pc + 1)); - return 2 | SUPPORTED; + return 2 | STEP_COND | SUPPORTED; } else { @@ -960,10 +960,15 @@ offs_t upd78k3_disassembler::disassemble(std::ostream &stream, offs_t pc, const format_saddr(stream, opcodes.r8(pc + 1)); stream << ","; if (BIT(op, 0)) + { format_jdisp8(stream, pc + 3, opcodes.r8(pc + 2)); + return 3 | STEP_COND | SUPPORTED; + } else + { format_imm8(stream, opcodes.r8(pc + 2)); - return 3 | SUPPORTED; + return 3 | SUPPORTED; + } } else return dasm_38(stream, op, pc, opcodes); @@ -1019,7 +1024,7 @@ offs_t upd78k3_disassembler::disassemble(std::ostream &stream, offs_t pc, const format_saddr(stream, opcodes.r8(pc + 1)); util::stream_format(stream, ".%d,", op & 0x07); format_jdisp8(stream, pc + 3, opcodes.r8(pc + 2)); - return 3 | SUPPORTED; + return 3 | STEP_COND | SUPPORTED; case 0x78: return dasm_78(stream, op, pc, opcodes); @@ -1027,7 +1032,7 @@ offs_t upd78k3_disassembler::disassemble(std::ostream &stream, offs_t pc, const case 0x80: util::stream_format(stream, "%-8s", s_bcond[op & 0x07]); format_jdisp8(stream, pc + 2, opcodes.r8(pc + 1)); - return 2 | SUPPORTED; + return 2 | STEP_COND | SUPPORTED; case 0x88: return dasm_88xx(stream, op, opcodes.r8(pc + 1)); diff --git a/src/devices/cpu/upd78k/upd78k4d.cpp b/src/devices/cpu/upd78k/upd78k4d.cpp index 7a45cfefadb..9ac9ce998be 100644 --- a/src/devices/cpu/upd78k/upd78k4d.cpp +++ b/src/devices/cpu/upd78k/upd78k4d.cpp @@ -670,7 +670,7 @@ offs_t upd78k4_disassembler::dasm_3c(std::ostream &stream, u8 op, offs_t pc, con util::stream_format(stream, "%-8s", BIT(op2, 4) ? "BT" : "BF"); util::stream_format(stream, "[%s].%d", s_rg_names[BIT(op2, 3) ? 3 : 2], op2 & 0x07); format_jdisp8(stream, pc + 3, opcodes.r8(pc + 2)); - return 3 | SUPPORTED; + return 3 | STEP_COND | SUPPORTED; } else return dasm_illegal2(stream, 0x3d, op2); @@ -783,7 +783,7 @@ offs_t upd78k4_disassembler::dasm_3c(std::ostream &stream, u8 op, offs_t pc, con format_saddr1(stream, opcodes.r8(pc + 3)); util::stream_format(stream, ".%d,", op3 & 0x07); format_jdisp8(stream, pc + 5, opcodes.r8(pc + 4)); - return 5 | SUPPORTED; + return 5 | STEP_COND | SUPPORTED; } else return dasm_illegal3(stream, 0x3c, 0x08, op3); diff --git a/src/devices/cpu/v60/v60d.cpp b/src/devices/cpu/v60/v60d.cpp index c611122724c..6271f779e54 100644 --- a/src/devices/cpu/v60/v60d.cpp +++ b/src/devices/cpu/v60/v60d.cpp @@ -640,38 +640,38 @@ DEFINE_EASY_OPCODE(ANDBSU, "andbsu", F7b, 0x80, 0x80) DEFINE_EASY_OPCODE(ANDBSD, "andbsd", F7b, 0x80, 0x80) DEFINE_EASY_OPCODE(ANDNBSU, "andnbsu", F7b, 0x80, 0x80) DEFINE_EASY_OPCODE(ANDNBSD, "andnbsd", F7b, 0x80, 0x80) -DEFINE_EASY_OPCODE(BGT8, "bgt", F4a, 0, 0) -DEFINE_EASY_OPCODE(BGT16, "bgt", F4b, 0, 0) -DEFINE_EASY_OPCODE(BGE8, "bge", F4a, 0, 0) -DEFINE_EASY_OPCODE(BGE16, "bge", F4b, 0, 0) -DEFINE_EASY_OPCODE(BLT8, "blt", F4a, 0, 0) -DEFINE_EASY_OPCODE(BLT16, "blt", F4b, 0, 0) -DEFINE_EASY_OPCODE(BLE8, "ble", F4a, 0, 0) -DEFINE_EASY_OPCODE(BLE16, "ble", F4b, 0, 0) -DEFINE_EASY_OPCODE(BH8, "bh", F4a, 0, 0) -DEFINE_EASY_OPCODE(BH16, "bh", F4b, 0, 0) -DEFINE_EASY_OPCODE(BNL8, "bnl", F4a, 0, 0) -DEFINE_EASY_OPCODE(BNL16, "bnl", F4b, 0, 0) -DEFINE_EASY_OPCODE(BL8, "bl", F4a, 0, 0) -DEFINE_EASY_OPCODE(BL16, "bl", F4b, 0, 0) -DEFINE_EASY_OPCODE(BNH8, "bnh", F4a, 0, 0) -DEFINE_EASY_OPCODE(BNH16, "bnh", F4b, 0, 0) -DEFINE_EASY_OPCODE(BE8, "be", F4a, 0, 0) -DEFINE_EASY_OPCODE(BE16, "be", F4b, 0, 0) -DEFINE_EASY_OPCODE(BNE8, "bne", F4a, 0, 0) -DEFINE_EASY_OPCODE(BNE16, "bne", F4b, 0, 0) -DEFINE_EASY_OPCODE(BV8, "bv", F4a, 0, 0) -DEFINE_EASY_OPCODE(BV16, "bv", F4b, 0, 0) -DEFINE_EASY_OPCODE(BNV8, "bnv", F4a, 0, 0) -DEFINE_EASY_OPCODE(BNV16, "bnv", F4b, 0, 0) -DEFINE_EASY_OPCODE(BN8, "bn", F4a, 0, 0) -DEFINE_EASY_OPCODE(BN16, "bn", F4b, 0, 0) -DEFINE_EASY_OPCODE(BP8, "bp", F4a, 0, 0) -DEFINE_EASY_OPCODE(BP16, "bp", F4b, 0, 0) +DEFINE_EASY_OPCODE_EX(BGT8, "bgt", F4a, 0, 0, STEP_COND) +DEFINE_EASY_OPCODE_EX(BGT16, "bgt", F4b, 0, 0, STEP_COND) +DEFINE_EASY_OPCODE_EX(BGE8, "bge", F4a, 0, 0, STEP_COND) +DEFINE_EASY_OPCODE_EX(BGE16, "bge", F4b, 0, 0, STEP_COND) +DEFINE_EASY_OPCODE_EX(BLT8, "blt", F4a, 0, 0, STEP_COND) +DEFINE_EASY_OPCODE_EX(BLT16, "blt", F4b, 0, 0, STEP_COND) +DEFINE_EASY_OPCODE_EX(BLE8, "ble", F4a, 0, 0, STEP_COND) +DEFINE_EASY_OPCODE_EX(BLE16, "ble", F4b, 0, 0, STEP_COND) +DEFINE_EASY_OPCODE_EX(BH8, "bh", F4a, 0, 0, STEP_COND) +DEFINE_EASY_OPCODE_EX(BH16, "bh", F4b, 0, 0, STEP_COND) +DEFINE_EASY_OPCODE_EX(BNL8, "bnl", F4a, 0, 0, STEP_COND) +DEFINE_EASY_OPCODE_EX(BNL16, "bnl", F4b, 0, 0, STEP_COND) +DEFINE_EASY_OPCODE_EX(BL8, "bl", F4a, 0, 0, STEP_COND) +DEFINE_EASY_OPCODE_EX(BL16, "bl", F4b, 0, 0, STEP_COND) +DEFINE_EASY_OPCODE_EX(BNH8, "bnh", F4a, 0, 0, STEP_COND) +DEFINE_EASY_OPCODE_EX(BNH16, "bnh", F4b, 0, 0, STEP_COND) +DEFINE_EASY_OPCODE_EX(BE8, "be", F4a, 0, 0, STEP_COND) +DEFINE_EASY_OPCODE_EX(BE16, "be", F4b, 0, 0, STEP_COND) +DEFINE_EASY_OPCODE_EX(BNE8, "bne", F4a, 0, 0, STEP_COND) +DEFINE_EASY_OPCODE_EX(BNE16, "bne", F4b, 0, 0, STEP_COND) +DEFINE_EASY_OPCODE_EX(BV8, "bv", F4a, 0, 0, STEP_COND) +DEFINE_EASY_OPCODE_EX(BV16, "bv", F4b, 0, 0, STEP_COND) +DEFINE_EASY_OPCODE_EX(BNV8, "bnv", F4a, 0, 0, STEP_COND) +DEFINE_EASY_OPCODE_EX(BNV16, "bnv", F4b, 0, 0, STEP_COND) +DEFINE_EASY_OPCODE_EX(BN8, "bn", F4a, 0, 0, STEP_COND) +DEFINE_EASY_OPCODE_EX(BN16, "bn", F4b, 0, 0, STEP_COND) +DEFINE_EASY_OPCODE_EX(BP8, "bp", F4a, 0, 0, STEP_COND) +DEFINE_EASY_OPCODE_EX(BP16, "bp", F4b, 0, 0, STEP_COND) DEFINE_EASY_OPCODE(BR8, "br", F4a, 0, 0) DEFINE_EASY_OPCODE(BR16, "br", F4b, 0, 0) -DEFINE_EASY_OPCODE(BRK, "brk", F5, 0, 0) -DEFINE_EASY_OPCODE(BRKV, "brkv", F5, 0, 0) +DEFINE_EASY_OPCODE_EX(BRK, "brk", F5, 0, 0, STEP_OVER) +DEFINE_EASY_OPCODE_EX(BRKV, "brkv", F5, 0, 0, STEP_OVER | STEP_COND) DEFINE_EASY_OPCODE_EX(BSR, "bsr", F4b, 0, 0, STEP_OVER) DEFINE_EASY_OPCODE_EX(CALL, "call", F1F2, 0, 2, STEP_OVER) DEFINE_EASY_OPCODE(CAXI, "caxi", F1, 2, 2) @@ -698,21 +698,21 @@ DEFINE_EASY_OPCODE(CVTSW, "cvt.sw", F2, 0, 2) DEFINE_EASY_OPCODE(CVTLW, "cvt.lw", F2, 1, 2) DEFINE_EASY_OPCODE(CVTDPZ, "cvtd.pz", F7c, 0, 1) DEFINE_EASY_OPCODE(CVTDZP, "cvtd.zp", F7c, 1, 0) -DEFINE_EASY_OPCODE_EX(DBGT, "dbgt", F6, 0, 0, STEP_OVER) -DEFINE_EASY_OPCODE_EX(DBGE, "dbge", F6, 0, 0, STEP_OVER) -DEFINE_EASY_OPCODE_EX(DBLT, "dbgt", F6, 0, 0, STEP_OVER) -DEFINE_EASY_OPCODE_EX(DBLE, "dbge", F6, 0, 0, STEP_OVER) -DEFINE_EASY_OPCODE_EX(DBH, "dbh", F6, 0, 0, STEP_OVER) -DEFINE_EASY_OPCODE_EX(DBNL, "dbnl", F6, 0, 0, STEP_OVER) -DEFINE_EASY_OPCODE_EX(DBL, "dbl", F6, 0, 0, STEP_OVER) -DEFINE_EASY_OPCODE_EX(DBNH, "dbnh", F6, 0, 0, STEP_OVER) -DEFINE_EASY_OPCODE_EX(DBE, "dbe", F6, 0, 0, STEP_OVER) -DEFINE_EASY_OPCODE_EX(DBNE, "dbne", F6, 0, 0, STEP_OVER) -DEFINE_EASY_OPCODE_EX(DBV, "dbe", F6, 0, 0, STEP_OVER) -DEFINE_EASY_OPCODE_EX(DBNV, "dbne", F6, 0, 0, STEP_OVER) -DEFINE_EASY_OPCODE_EX(DBN, "dbn", F6, 0, 0, STEP_OVER) -DEFINE_EASY_OPCODE_EX(DBP, "dbp", F6, 0, 0, STEP_OVER) -DEFINE_EASY_OPCODE_EX(DBR, "dbr", F6, 0, 0, STEP_OVER) +DEFINE_EASY_OPCODE_EX(DBGT, "dbgt", F6, 0, 0, STEP_COND) +DEFINE_EASY_OPCODE_EX(DBGE, "dbge", F6, 0, 0, STEP_COND) +DEFINE_EASY_OPCODE_EX(DBLT, "dbgt", F6, 0, 0, STEP_COND) +DEFINE_EASY_OPCODE_EX(DBLE, "dbge", F6, 0, 0, STEP_COND) +DEFINE_EASY_OPCODE_EX(DBH, "dbh", F6, 0, 0, STEP_COND) +DEFINE_EASY_OPCODE_EX(DBNL, "dbnl", F6, 0, 0, STEP_COND) +DEFINE_EASY_OPCODE_EX(DBL, "dbl", F6, 0, 0, STEP_COND) +DEFINE_EASY_OPCODE_EX(DBNH, "dbnh", F6, 0, 0, STEP_COND) +DEFINE_EASY_OPCODE_EX(DBE, "dbe", F6, 0, 0, STEP_COND) +DEFINE_EASY_OPCODE_EX(DBNE, "dbne", F6, 0, 0, STEP_COND) +DEFINE_EASY_OPCODE_EX(DBV, "dbe", F6, 0, 0, STEP_COND) +DEFINE_EASY_OPCODE_EX(DBNV, "dbne", F6, 0, 0, STEP_COND) +DEFINE_EASY_OPCODE_EX(DBN, "dbn", F6, 0, 0, STEP_COND) +DEFINE_EASY_OPCODE_EX(DBP, "dbp", F6, 0, 0, STEP_COND) +DEFINE_EASY_OPCODE_EX(DBR, "dbr", F6, 0, 0, STEP_COND) DEFINE_TRIPLE_OPCODE(DEC, "dec", F3) DEFINE_EASY_OPCODE(DISPOSE, "dispose", F5, 0, 0) DEFINE_TRIPLE_OPCODE(DIV, "div", F1F2) @@ -825,7 +825,7 @@ DEFINE_EASY_OPCODE(SUBDC, "subdc", F7c, 0, 0) DEFINE_EASY_OPCODE(SUBRDC, "subrdc", F7c, 0, 0) DEFINE_FPU_OPCODE(SUBF, "subf", F2) DEFINE_EASY_OPCODE(TASI, "tasi", F3, 0, 0) -DEFINE_EASY_OPCODE(TB, "tb", F6, 0, 0) +DEFINE_EASY_OPCODE_EX(TB, "tb", F6, 0, 0, STEP_COND) DEFINE_TRIPLE_OPCODE(TEST, "test", F3) DEFINE_EASY_OPCODE(TEST1, "test1", F1F2, 2, 2) DEFINE_EASY_OPCODE_EX(TRAP, "trap", F3, 0, 0, STEP_OVER) diff --git a/src/devices/cpu/v810/v810dasm.cpp b/src/devices/cpu/v810/v810dasm.cpp index a3590a6f583..c03fe532d4a 100644 --- a/src/devices/cpu/v810/v810dasm.cpp +++ b/src/devices/cpu/v810/v810dasm.cpp @@ -115,22 +115,22 @@ offs_t v810_disassembler::disassemble(std::ostream &stream, offs_t pc, const dat case 0x26: case 0x27: switch( (opc>>9) &0xf) { - case 0x0: util::stream_format(stream,"BV %X",pc+D9(opc)); break; - case 0x1: util::stream_format(stream,"BL %X",pc+D9(opc)); break; - case 0x2: util::stream_format(stream,"BE %X",pc+D9(opc)); break; - case 0x3: util::stream_format(stream,"BNH %X",pc+D9(opc)); break; - case 0x4: util::stream_format(stream,"BN %X",pc+D9(opc)); break; + case 0x0: util::stream_format(stream,"BV %X",pc+D9(opc)); flags = STEP_COND; break; + case 0x1: util::stream_format(stream,"BL %X",pc+D9(opc)); flags = STEP_COND; break; + case 0x2: util::stream_format(stream,"BE %X",pc+D9(opc)); flags = STEP_COND; break; + case 0x3: util::stream_format(stream,"BNH %X",pc+D9(opc)); flags = STEP_COND; break; + case 0x4: util::stream_format(stream,"BN %X",pc+D9(opc)); flags = STEP_COND; break; case 0x5: util::stream_format(stream,"BR %X",pc+D9(opc)); break; - case 0x6: util::stream_format(stream,"BLT %X",pc+D9(opc)); break; - case 0x7: util::stream_format(stream,"BLE %X",pc+D9(opc)); break; - case 0x8: util::stream_format(stream,"BNV %X",pc+D9(opc)); break; - case 0x9: util::stream_format(stream,"BNL %X",pc+D9(opc)); break; - case 0xa: util::stream_format(stream,"BNE %X",pc+D9(opc)); break; - case 0xb: util::stream_format(stream,"BH %X",pc+D9(opc)); break; - case 0xc: util::stream_format(stream,"BP %X",pc+D9(opc)); break; + case 0x6: util::stream_format(stream,"BLT %X",pc+D9(opc)); flags = STEP_COND; break; + case 0x7: util::stream_format(stream,"BLE %X",pc+D9(opc)); flags = STEP_COND; break; + case 0x8: util::stream_format(stream,"BNV %X",pc+D9(opc)); flags = STEP_COND; break; + case 0x9: util::stream_format(stream,"BNL %X",pc+D9(opc)); flags = STEP_COND; break; + case 0xa: util::stream_format(stream,"BNE %X",pc+D9(opc)); flags = STEP_COND; break; + case 0xb: util::stream_format(stream,"BH %X",pc+D9(opc)); flags = STEP_COND; break; + case 0xc: util::stream_format(stream,"BP %X",pc+D9(opc)); flags = STEP_COND; break; case 0xd: util::stream_format(stream,"NOP"); break; - case 0xe: util::stream_format(stream,"BGE %X",pc+D9(opc)); break; - case 0xf: util::stream_format(stream,"BGT %X",pc+D9(opc)); break; + case 0xe: util::stream_format(stream,"BGE %X",pc+D9(opc)); flags = STEP_COND; break; + case 0xf: util::stream_format(stream,"BGT %X",pc+D9(opc)); flags = STEP_COND; break; } size=2; break; diff --git a/src/devices/cpu/v850/v850dasm.cpp b/src/devices/cpu/v850/v850dasm.cpp index 90630aed35b..204684d6a88 100644 --- a/src/devices/cpu/v850/v850dasm.cpp +++ b/src/devices/cpu/v850/v850dasm.cpp @@ -991,7 +991,7 @@ offs_t v850_disassembler::disassemble(std::ostream &stream, offs_t pc, const v85 { s16 disp9 = s8((opcode & 0xf800) >> 8 | (opcode & 0x0070) >> 4) * 2; util::stream_format(stream, "%-8s0x%08X", s_bconds[BIT(opcode, 0, 4)], pc + disp9); - return 2 | SUPPORTED; + return 2 | (BIT(opcode, 0, 4) != 0b0101 ? STEP_COND : 0) | SUPPORTED; } case 0b1100: diff --git a/src/devices/cpu/vax/vaxdasm.cpp b/src/devices/cpu/vax/vaxdasm.cpp index d016901692c..9919e171f14 100644 --- a/src/devices/cpu/vax/vaxdasm.cpp +++ b/src/devices/cpu/vax/vaxdasm.cpp @@ -355,20 +355,20 @@ static const vax_disassembler::opdef s_nonprefix_ops[0x100 - 3] = { "BSBB"sv, { mode::bb, mode::none, mode::none, mode::none, mode::none, mode::none }, vax_disassembler::STEP_OUT }, { "BRB"sv, { mode::bb, mode::none, mode::none, mode::none, mode::none, mode::none }, 0 }, - { "BNEQ"sv, { mode::bb, mode::none, mode::none, mode::none, mode::none, mode::none }, 0 }, // or BNEQU - { "BEQL"sv, { mode::bb, mode::none, mode::none, mode::none, mode::none, mode::none }, 0 }, // or BEQLU - { "BGTR"sv, { mode::bb, mode::none, mode::none, mode::none, mode::none, mode::none }, 0 }, - { "BLEQ"sv, { mode::bb, mode::none, mode::none, mode::none, mode::none, mode::none }, 0 }, + { "BNEQ"sv, { mode::bb, mode::none, mode::none, mode::none, mode::none, mode::none }, vax_disassembler::STEP_COND }, // or BNEQU + { "BEQL"sv, { mode::bb, mode::none, mode::none, mode::none, mode::none, mode::none }, vax_disassembler::STEP_COND }, // or BEQLU + { "BGTR"sv, { mode::bb, mode::none, mode::none, mode::none, mode::none, mode::none }, vax_disassembler::STEP_COND }, + { "BLEQ"sv, { mode::bb, mode::none, mode::none, mode::none, mode::none, mode::none }, vax_disassembler::STEP_COND }, { "JSB"sv, { mode::ab, mode::none, mode::none, mode::none, mode::none, mode::none }, vax_disassembler::STEP_OVER }, { "JMP"sv, { mode::ab, mode::none, mode::none, mode::none, mode::none, mode::none }, 0 }, - { "BGEQ"sv, { mode::bb, mode::none, mode::none, mode::none, mode::none, mode::none }, 0 }, - { "BLSS"sv, { mode::bb, mode::none, mode::none, mode::none, mode::none, mode::none }, 0 }, - { "BGTRU"sv, { mode::bb, mode::none, mode::none, mode::none, mode::none, mode::none }, 0 }, - { "BLEQU"sv, { mode::bb, mode::none, mode::none, mode::none, mode::none, mode::none }, 0 }, - { "BVC"sv, { mode::bb, mode::none, mode::none, mode::none, mode::none, mode::none }, 0 }, - { "BVS"sv, { mode::bb, mode::none, mode::none, mode::none, mode::none, mode::none }, 0 }, - { "BCC"sv, { mode::bb, mode::none, mode::none, mode::none, mode::none, mode::none }, 0 }, // or BGEQU - { "BCS"sv, { mode::bb, mode::none, mode::none, mode::none, mode::none, mode::none }, 0 }, // or BLSSU + { "BGEQ"sv, { mode::bb, mode::none, mode::none, mode::none, mode::none, mode::none }, vax_disassembler::STEP_COND }, + { "BLSS"sv, { mode::bb, mode::none, mode::none, mode::none, mode::none, mode::none }, vax_disassembler::STEP_COND }, + { "BGTRU"sv, { mode::bb, mode::none, mode::none, mode::none, mode::none, mode::none }, vax_disassembler::STEP_COND }, + { "BLEQU"sv, { mode::bb, mode::none, mode::none, mode::none, mode::none, mode::none }, vax_disassembler::STEP_COND }, + { "BVC"sv, { mode::bb, mode::none, mode::none, mode::none, mode::none, mode::none }, vax_disassembler::STEP_COND }, + { "BVS"sv, { mode::bb, mode::none, mode::none, mode::none, mode::none, mode::none }, vax_disassembler::STEP_COND }, + { "BCC"sv, { mode::bb, mode::none, mode::none, mode::none, mode::none, mode::none }, vax_disassembler::STEP_COND }, // or BGEQU + { "BCS"sv, { mode::bb, mode::none, mode::none, mode::none, mode::none, mode::none }, vax_disassembler::STEP_COND }, // or BLSSU { "ADDP4"sv, { mode::rw, mode::ab, mode::rw, mode::ab, mode::none, mode::none }, 0 }, { "ADDP6"sv, { mode::rw, mode::ab, mode::rw, mode::ab, mode::rw, mode::ab }, 0 }, @@ -400,7 +400,7 @@ static const vax_disassembler::opdef s_nonprefix_ops[0x100 - 3] = { "LOCC"sv, { mode::rb, mode::rw, mode::ab, mode::none, mode::none, mode::none }, 0 }, { "SKPC"sv, { mode::rb, mode::rw, mode::ab, mode::none, mode::none, mode::none }, 0 }, { "MOVZWL"sv, { mode::rw, mode::wl, mode::none, mode::none, mode::none, mode::none }, 0 }, - { "ACBW"sv, { mode::srw, mode::srw, mode::mw, mode::bw, mode::none, mode::none }, 0 }, + { "ACBW"sv, { mode::srw, mode::srw, mode::mw, mode::bw, mode::none, mode::none }, vax_disassembler::STEP_COND }, { "MOVAW"sv, { mode::aw, mode::wl, mode::none, mode::none, mode::none, mode::none }, 0 }, { "PUSHAW"sv, { mode::aw, mode::none, mode::none, mode::none, mode::none, mode::none }, 0 }, @@ -419,7 +419,7 @@ static const vax_disassembler::opdef s_nonprefix_ops[0x100 - 3] = { "CVTBF"sv, { mode::srb, mode::wl, mode::none, mode::none, mode::none, mode::none }, 0 }, { "CVTWF"sv, { mode::srw, mode::wl, mode::none, mode::none, mode::none, mode::none }, 0 }, { "CVTLF"sv, { mode::srl, mode::wl, mode::none, mode::none, mode::none, mode::none }, 0 }, - { "ACBF"sv, { mode::rl, mode::rl, mode::ml, mode::bw, mode::none, mode::none }, 0 }, + { "ACBF"sv, { mode::rl, mode::rl, mode::ml, mode::bw, mode::none, mode::none }, vax_disassembler::STEP_COND }, { "MOVF"sv, { mode::rl, mode::wl, mode::none, mode::none, mode::none, mode::none }, 0 }, { "CMPF"sv, { mode::rl, mode::rl, mode::none, mode::none, mode::none, mode::none }, 0 }, @@ -453,7 +453,7 @@ static const vax_disassembler::opdef s_nonprefix_ops[0x100 - 3] = { "CVTBD"sv, { mode::srb, mode::wq, mode::none, mode::none, mode::none, mode::none }, 0 }, { "CVTWD"sv, { mode::srw, mode::wq, mode::none, mode::none, mode::none, mode::none }, 0 }, { "CVTLD"sv, { mode::srl, mode::wq, mode::none, mode::none, mode::none, mode::none }, 0 }, - { "ACBD"sv, { mode::rq, mode::rq, mode::mq, mode::bw, mode::none, mode::none }, 0 }, + { "ACBD"sv, { mode::rq, mode::rq, mode::mq, mode::bw, mode::none, mode::none }, vax_disassembler::STEP_COND }, { "MOVD"sv, { mode::rq, mode::wq, mode::none, mode::none, mode::none, mode::none }, 0 }, { "CMPD"sv, { mode::rq, mode::rq, mode::none, mode::none, mode::none, mode::none }, 0 }, @@ -502,7 +502,7 @@ static const vax_disassembler::opdef s_nonprefix_ops[0x100 - 3] = { "MOVZBL"sv, { mode::rb, mode::wl, mode::none, mode::none, mode::none, mode::none }, 0 }, { "MOVZBW"sv, { mode::rb, mode::ww, mode::none, mode::none, mode::none, mode::none }, 0 }, { "ROTL"sv, { mode::cntb, mode::rl, mode::wl, mode::none, mode::none, mode::none }, 0 }, - { "ACBB"sv, { mode::srb, mode::srb, mode::mb, mode::bw, mode::none, mode::none }, 0 }, + { "ACBB"sv, { mode::srb, mode::srb, mode::mb, mode::bw, mode::none, mode::none }, vax_disassembler::STEP_COND }, { "MOVAB"sv, { mode::ab, mode::wl, mode::none, mode::none, mode::none, mode::none }, 0 }, { "PUSHAB"sv, { mode::ab, mode::none, mode::none, mode::none, mode::none, mode::none }, 0 }, @@ -574,16 +574,16 @@ static const vax_disassembler::opdef s_nonprefix_ops[0x100 - 3] = { "MOVAL"sv, { mode::al, mode::wl, mode::none, mode::none, mode::none, mode::none }, 0 }, // or MOVAF { "PUSHAL"sv, { mode::al, mode::none, mode::none, mode::none, mode::none, mode::none }, 0 }, // or PUSHAF - { "BBS"sv, { mode::posl, mode::vb, mode::bb, mode::none, mode::none, mode::none }, 0 }, - { "BBC"sv, { mode::posl, mode::vb, mode::bb, mode::none, mode::none, mode::none }, 0 }, - { "BBSS"sv, { mode::posl, mode::vb, mode::bb, mode::none, mode::none, mode::none }, 0 }, - { "BBCS"sv, { mode::posl, mode::vb, mode::bb, mode::none, mode::none, mode::none }, 0 }, - { "BBSC"sv, { mode::posl, mode::vb, mode::bb, mode::none, mode::none, mode::none }, 0 }, - { "BBCC"sv, { mode::posl, mode::vb, mode::bb, mode::none, mode::none, mode::none }, 0 }, - { "BBSSI"sv, { mode::posl, mode::vb, mode::bb, mode::none, mode::none, mode::none }, 0 }, - { "BBCCI"sv, { mode::posl, mode::vb, mode::bb, mode::none, mode::none, mode::none }, 0 }, - { "BLBS"sv, { mode::posl, mode::bb, mode::none, mode::none, mode::none, mode::none }, 0 }, - { "BLBC"sv, { mode::posl, mode::bb, mode::none, mode::none, mode::none, mode::none }, 0 }, + { "BBS"sv, { mode::posl, mode::vb, mode::bb, mode::none, mode::none, mode::none }, vax_disassembler::STEP_COND }, + { "BBC"sv, { mode::posl, mode::vb, mode::bb, mode::none, mode::none, mode::none }, vax_disassembler::STEP_COND }, + { "BBSS"sv, { mode::posl, mode::vb, mode::bb, mode::none, mode::none, mode::none }, vax_disassembler::STEP_COND }, + { "BBCS"sv, { mode::posl, mode::vb, mode::bb, mode::none, mode::none, mode::none }, vax_disassembler::STEP_COND }, + { "BBSC"sv, { mode::posl, mode::vb, mode::bb, mode::none, mode::none, mode::none }, vax_disassembler::STEP_COND }, + { "BBCC"sv, { mode::posl, mode::vb, mode::bb, mode::none, mode::none, mode::none }, vax_disassembler::STEP_COND }, + { "BBSSI"sv, { mode::posl, mode::vb, mode::bb, mode::none, mode::none, mode::none }, vax_disassembler::STEP_COND }, + { "BBCCI"sv, { mode::posl, mode::vb, mode::bb, mode::none, mode::none, mode::none }, vax_disassembler::STEP_COND }, + { "BLBS"sv, { mode::posl, mode::bb, mode::none, mode::none, mode::none, mode::none }, vax_disassembler::STEP_COND }, + { "BLBC"sv, { mode::posl, mode::bb, mode::none, mode::none, mode::none, mode::none }, vax_disassembler::STEP_COND }, { "FFS"sv, { mode::posl, mode::cntb, mode::vb, mode::wl, mode::none, mode::none }, 0 }, { "FFC"sv, { mode::posl, mode::cntb, mode::vb, mode::wl, mode::none, mode::none }, 0 }, { "CMPV"sv, { mode::posl, mode::cntb, mode::vb, mode::rl, mode::none, mode::none }, 0 }, @@ -592,11 +592,11 @@ static const vax_disassembler::opdef s_nonprefix_ops[0x100 - 3] = { "EXTZV"sv, { mode::posl, mode::cntb, mode::vb, mode::wl, mode::none, mode::none }, 0 }, { "INSV"sv, { mode::rl, mode::posl, mode::cntb, mode::vb, mode::none, mode::none }, 0 }, - { "ACBL"sv, { mode::srl, mode::srl, mode::ml, mode::bw, mode::none, mode::none }, 0 }, - { "AOBLSS"sv, { mode::srl, mode::ml, mode::bb, mode::none, mode::none, mode::none }, 0 }, - { "AOBLEQ"sv, { mode::srl, mode::ml, mode::bb, mode::none, mode::none, mode::none }, 0 }, - { "SOBGEQ"sv, { mode::ml, mode::bb, mode::none, mode::none, mode::none, mode::none }, 0 }, - { "SOBGTR"sv, { mode::ml, mode::bb, mode::none, mode::none, mode::none, mode::none }, 0 }, + { "ACBL"sv, { mode::srl, mode::srl, mode::ml, mode::bw, mode::none, mode::none }, vax_disassembler::STEP_COND }, + { "AOBLSS"sv, { mode::srl, mode::ml, mode::bb, mode::none, mode::none, mode::none }, vax_disassembler::STEP_COND }, + { "AOBLEQ"sv, { mode::srl, mode::ml, mode::bb, mode::none, mode::none, mode::none }, vax_disassembler::STEP_COND }, + { "SOBGEQ"sv, { mode::ml, mode::bb, mode::none, mode::none, mode::none, mode::none }, vax_disassembler::STEP_COND }, + { "SOBGTR"sv, { mode::ml, mode::bb, mode::none, mode::none, mode::none, mode::none }, vax_disassembler::STEP_COND }, { "CVTLB"sv, { mode::srl, mode::wb, mode::none, mode::none, mode::none, mode::none }, 0 }, { "CVTLW"sv, { mode::srl, mode::ww, mode::none, mode::none, mode::none, mode::none }, 0 }, { "ASHP"sv, { mode::cntb, mode::rw, mode::ab, mode::rb, mode::rw, mode::ab }, 0 }, @@ -639,7 +639,7 @@ static const vax_disassembler::opdef s_fdprefix_ops[0x100 - 0x31] = { "CVTBG"sv, { mode::srb, mode::wq, mode::none, mode::none, mode::none, mode::none }, 0 }, { "CVTWG"sv, { mode::srw, mode::wq, mode::none, mode::none, mode::none, mode::none }, 0 }, { "CVTLG"sv, { mode::srl, mode::wq, mode::none, mode::none, mode::none, mode::none }, 0 }, - { "ACBG"sv, { mode::rq, mode::rq, mode::mq, mode::bw, mode::none, mode::none }, 0 }, + { "ACBG"sv, { mode::rq, mode::rq, mode::mq, mode::bw, mode::none, mode::none }, vax_disassembler::STEP_COND }, { "MOVG"sv, { mode::rq, mode::wq, mode::none, mode::none, mode::none, mode::none }, 0 }, { "CMPG"sv, { mode::rq, mode::rq, mode::none, mode::none, mode::none, mode::none }, 0 }, @@ -673,7 +673,7 @@ static const vax_disassembler::opdef s_fdprefix_ops[0x100 - 0x31] = { "CVTBH"sv, { mode::srb, mode::wo, mode::none, mode::none, mode::none, mode::none }, 0 }, { "CVTWH"sv, { mode::srw, mode::wo, mode::none, mode::none, mode::none, mode::none }, 0 }, { "CVTLH"sv, { mode::srl, mode::wo, mode::none, mode::none, mode::none, mode::none }, 0 }, - { "ACBH"sv, { mode::ro, mode::ro, mode::mq, mode::bw, mode::none, mode::none }, 0 }, + { "ACBH"sv, { mode::ro, mode::ro, mode::mq, mode::bw, mode::none, mode::none }, vax_disassembler::STEP_COND }, { "MOVH"sv, { mode::ro, mode::wo, mode::none, mode::none, mode::none, mode::none }, 0 }, { "CMPH"sv, { mode::ro, mode::ro, mode::none, mode::none, mode::none, mode::none }, 0 }, diff --git a/src/devices/cpu/vt50/vt50dasm.cpp b/src/devices/cpu/vt50/vt50dasm.cpp index 8339cc476f9..c7e3e10ead8 100644 --- a/src/devices/cpu/vt50/vt50dasm.cpp +++ b/src/devices/cpu/vt50/vt50dasm.cpp @@ -71,12 +71,12 @@ offs_t vt5x_disassembler::disassemble(std::ostream &stream, offs_t pc, const vt5 if (BIT(opcode, 7)) { util::stream_format(stream, "LD %03o", opcode & 0177); // execution varies by mode - return 1; + return 1 | SUPPORTED; } else if ((opcode & 0017) == 0) { stream << m_opcodes_w[(opcode & 0160) >> 4]; - return 1; + return 1 | SUPPORTED; } else { @@ -121,9 +121,9 @@ offs_t vt5x_disassembler::disassemble(std::ostream &stream, offs_t pc, const vt5 if ((opcode & 0164) == 0124) // IROM adjustment nextpc += 0400; util::stream_format(stream, " %04o", (nextpc & 01400) | opcodes.r8(pc + 1)); - return 2; + return 2 | ((opcode & 0170) != 0130 ? STEP_COND : 0) | SUPPORTED; } else - return 1; + return 1 | SUPPORTED; } } diff --git a/src/devices/cpu/vt61/vt61dasm.cpp b/src/devices/cpu/vt61/vt61dasm.cpp index 7c89354b3e3..8657be1ab11 100644 --- a/src/devices/cpu/vt61/vt61dasm.cpp +++ b/src/devices/cpu/vt61/vt61dasm.cpp @@ -90,13 +90,13 @@ const char *const vt61_disassembler::s_conditions[32][2] = { { "T", "F" }, // TRUE H { "NVSR", "VSR" }, // VID SERV REQ L { "?H", "?L" }, - { "?H", "?L" }, - { "?H", "?L" }, - { "?H", "?L" }, - { "?H", "?L" }, - { "?H", "?L" }, - { "?H", "?L" }, - { "?H", "?L" } + { "?H", "?L" }, + { "?H", "?L" }, + { "?H", "?L" }, + { "?H", "?L" }, + { "?H", "?L" }, + { "?H", "?L" }, + { "?H", "?L" } }; u32 vt61_disassembler::opcode_alignment() const @@ -196,6 +196,8 @@ offs_t vt61_disassembler::disassemble(std::ostream &stream, offs_t pc, const vt6 else if (BIT(inst, 14)) { util::stream_format(stream, "JMP %s,%03o", s_conditions[(inst & 017400) >> 8][BIT(inst, 13)], inst & 000377); + if ((inst & 017400) != 013000) + flags |= STEP_COND; } else if (BIT(inst, 13)) { diff --git a/src/devices/cpu/we32000/we32100d.cpp b/src/devices/cpu/we32000/we32100d.cpp index c91a760239f..4f5715a3d8e 100644 --- a/src/devices/cpu/we32000/we32100d.cpp +++ b/src/devices/cpu/we32000/we32100d.cpp @@ -252,7 +252,7 @@ void we32100_disassembler::dasm_ea(std::ostream &stream, offs_t &pc, offs_t ppc, pc += 4; } format_signed(stream, disp); - util::stream_format(stream, "(%%%s) <%x>", s_rnames[15], u32(ppc + disp)); + util::stream_format(stream, "(%%%s) /*0x%x*/", s_rnames[15], u32(ppc + disp)); } else dasm_am(stream, pc, opcodes, n, false, true); @@ -284,7 +284,7 @@ void we32100_disassembler::dasm_bdisp(std::ostream &stream, offs_t &pc, const we pc += 2; } format_signed(stream, disp); - util::stream_format(stream, " <%x>", u32(ppc + disp)); + util::stream_format(stream, " /*0x%x*/", u32(ppc + disp)); } offs_t we32100_disassembler::dasm_30xx(std::ostream &stream, offs_t &pc, const we32100_disassembler::data_buffer &opcodes) @@ -557,6 +557,7 @@ offs_t we32100_disassembler::disassemble(std::ostream &stream, offs_t pc, const util::stream_format(stream, "%-8s", BIT(op, 0) ? "BGEB" : "BGEH"); dasm_bdisp(stream, pc, opcodes, BIT(op, 0)); } + flags |= STEP_COND; break; case 0x44: case 0x54: @@ -575,6 +576,7 @@ offs_t we32100_disassembler::disassemble(std::ostream &stream, offs_t pc, const util::stream_format(stream, "%-8s", BIT(op, 0) ? "BGB" : "BGH"); dasm_bdisp(stream, pc, opcodes, BIT(op, 0)); } + flags |= STEP_COND; break; case 0x48: @@ -588,6 +590,7 @@ offs_t we32100_disassembler::disassemble(std::ostream &stream, offs_t pc, const util::stream_format(stream, "%-8s", BIT(op, 0) ? "BLB" : "BLH"); dasm_bdisp(stream, pc, opcodes, BIT(op, 0)); } + flags |= STEP_COND; break; case 0x4c: case 0x5c: @@ -606,6 +609,7 @@ offs_t we32100_disassembler::disassemble(std::ostream &stream, offs_t pc, const util::stream_format(stream, "%-8s", BIT(op, 0) ? "BLEB" : "BLEH"); dasm_bdisp(stream, pc, opcodes, BIT(op, 0)); } + flags |= STEP_COND; break; case 0x50: @@ -619,6 +623,7 @@ offs_t we32100_disassembler::disassemble(std::ostream &stream, offs_t pc, const util::stream_format(stream, "%-8s", BIT(op, 0) ? "BCC" : "BCC"); dasm_bdisp(stream, pc, opcodes, BIT(op, 0)); } + flags |= STEP_COND; break; case 0x58: @@ -632,6 +637,7 @@ offs_t we32100_disassembler::disassemble(std::ostream &stream, offs_t pc, const util::stream_format(stream, "%-8s", BIT(op, 0) ? "BCSB" : "BCSH"); dasm_bdisp(stream, pc, opcodes, BIT(op, 0)); } + flags |= STEP_COND; break; case 0x60: @@ -645,6 +651,7 @@ offs_t we32100_disassembler::disassemble(std::ostream &stream, offs_t pc, const util::stream_format(stream, "%-8s", BIT(op, 0) ? "BVCB" : "BVCH"); dasm_bdisp(stream, pc, opcodes, BIT(op, 0)); } + flags |= STEP_COND; break; case 0x64: case 0x74: @@ -660,6 +667,7 @@ offs_t we32100_disassembler::disassemble(std::ostream &stream, offs_t pc, const util::stream_format(stream, "%-8s", BIT(op, 0) ? "BNEB" : "BNEH"); dasm_bdisp(stream, pc, opcodes, BIT(op, 0)); } + flags |= STEP_COND; break; case 0x68: @@ -673,6 +681,7 @@ offs_t we32100_disassembler::disassemble(std::ostream &stream, offs_t pc, const util::stream_format(stream, "%-8s", BIT(op, 0) ? "BVSB" : "BVSH"); dasm_bdisp(stream, pc, opcodes, BIT(op, 0)); } + flags |= STEP_COND; break; case 0x6c: case 0x7c: @@ -688,6 +697,7 @@ offs_t we32100_disassembler::disassemble(std::ostream &stream, offs_t pc, const util::stream_format(stream, "%-8s", BIT(op, 0) ? "BEB" : "BEH"); dasm_bdisp(stream, pc, opcodes, BIT(op, 0)); } + flags |= STEP_COND; break; case 0x70: diff --git a/src/devices/cpu/xavix2/xavix2d.cpp b/src/devices/cpu/xavix2/xavix2d.cpp index 8b3290a8f6e..3c1c87bf503 100644 --- a/src/devices/cpu/xavix2/xavix2d.cpp +++ b/src/devices/cpu/xavix2/xavix2d.cpp @@ -319,22 +319,22 @@ offs_t xavix2_disassembler::disassemble(std::ostream &stream, offs_t pc, const d case 0xca: case 0xcb: util::stream_format(stream, "hreg[%s] = %s", val6u(), r1()); break; // cc-cf - case 0xd0: util::stream_format(stream, "bvs %s", rel8()); break; - case 0xd1: util::stream_format(stream, "bltu %s", rel8()); break; - case 0xd2: util::stream_format(stream, "beq %s", rel8()); break; - case 0xd3: util::stream_format(stream, "bleu %s", rel8()); break; - case 0xd4: util::stream_format(stream, "bmi %s", rel8()); break; - case 0xd5: util::stream_format(stream, "bra %s", rel8()); break; - case 0xd6: util::stream_format(stream, "blts %s", rel8()); break; - case 0xd7: util::stream_format(stream, "bles %s", rel8()); break; - case 0xd8: util::stream_format(stream, "bvc %s", rel8()); break; - case 0xd9: util::stream_format(stream, "bgeu %s", rel8()); break; - case 0xda: util::stream_format(stream, "bne %s", rel8()); break; - case 0xdb: util::stream_format(stream, "bgtu %s", rel8()); break; - case 0xdc: util::stream_format(stream, "bpl %s", rel8()); break; - case 0xdd: util::stream_format(stream, "bnv %s", rel8()); break; - case 0xde: util::stream_format(stream, "bges %s", rel8()); break; - case 0xdf: util::stream_format(stream, "bgts %s", rel8()); break; + case 0xd0: util::stream_format(stream, "bvs %s", rel8()); flags = STEP_COND; break; + case 0xd1: util::stream_format(stream, "bltu %s", rel8()); flags = STEP_COND; break; + case 0xd2: util::stream_format(stream, "beq %s", rel8()); flags = STEP_COND; break; + case 0xd3: util::stream_format(stream, "bleu %s", rel8()); flags = STEP_COND; break; + case 0xd4: util::stream_format(stream, "bmi %s", rel8()); flags = STEP_COND; break; + case 0xd5: util::stream_format(stream, "bra %s", rel8()); flags = STEP_COND; break; + case 0xd6: util::stream_format(stream, "blts %s", rel8()); flags = STEP_COND; break; + case 0xd7: util::stream_format(stream, "bles %s", rel8()); flags = STEP_COND; break; + case 0xd8: util::stream_format(stream, "bvc %s", rel8()); flags = STEP_COND; break; + case 0xd9: util::stream_format(stream, "bgeu %s", rel8()); flags = STEP_COND; break; + case 0xda: util::stream_format(stream, "bne %s", rel8()); flags = STEP_COND; break; + case 0xdb: util::stream_format(stream, "bgtu %s", rel8()); flags = STEP_COND; break; + case 0xdc: util::stream_format(stream, "bpl %s", rel8()); flags = STEP_COND; break; + case 0xdd: util::stream_format(stream, "bnv %s", rel8()); flags = STEP_COND; break; + case 0xde: util::stream_format(stream, "bges %s", rel8()); flags = STEP_COND; break; + case 0xdf: util::stream_format(stream, "bgts %s", rel8()); flags = STEP_COND; break; case 0xe0: util::stream_format(stream, "jmp lr"); flags = STEP_OUT; break; case 0xe1: util::stream_format(stream, "rti1"); flags = STEP_OUT; break; diff --git a/src/devices/cpu/z180/z180dasm.cpp b/src/devices/cpu/z180/z180dasm.cpp index 4c47711b852..393f9a51946 100644 --- a/src/devices/cpu/z180/z180dasm.cpp +++ b/src/devices/cpu/z180/z180dasm.cpp @@ -423,6 +423,7 @@ offs_t z180_disassembler::disassemble(std::ostream &stream, offs_t pc, const dat break; } + bool comma = false; if( d->arguments ) { util::stream_format(stream, "%-5s ", s_mnemonic[d->mnemonic]); @@ -474,6 +475,9 @@ offs_t z180_disassembler::disassemble(std::ostream &stream, offs_t pc, const dat case 'I': util::stream_format(stream, "%s", ixy); break; + case ',': + comma = true; + [[fallthrough]]; default: stream << *src; } @@ -485,12 +489,16 @@ offs_t z180_disassembler::disassemble(std::ostream &stream, offs_t pc, const dat util::stream_format(stream, "%s", s_mnemonic[d->mnemonic]); } - if (d->mnemonic == zCALL || d->mnemonic == zCPDR || d->mnemonic == zCPIR || d->mnemonic == zDJNZ || - d->mnemonic == zHLT || d->mnemonic == zINDR || d->mnemonic == zINIR || d->mnemonic == zLDDR || - d->mnemonic == zLDIR || d->mnemonic == zOTDR || d->mnemonic == zOTIR || d->mnemonic == zRST) + if (d->mnemonic == zCALL || d->mnemonic == zHLT || d->mnemonic == zRST) flags = STEP_OVER; else if (d->mnemonic == zRETN || d->mnemonic == zRET || d->mnemonic == zRETI) flags = STEP_OUT; + if (d->mnemonic == zCPDR || d->mnemonic == zCPIR || d->mnemonic == zDJNZ || d->mnemonic == zINDR || + d->mnemonic == zINIR || d->mnemonic == zLDDR || d->mnemonic == zLDIR || d->mnemonic == zOTDR || + d->mnemonic == zOTDMR || d->mnemonic == zOTIR || d->mnemonic == zOTIMR || + ((d->mnemonic == zCALL || d->mnemonic == zJP || d->mnemonic == zJR) && comma) || + (d->mnemonic == zRET && d->arguments)) + flags = STEP_COND; return (pos - pc) | flags | SUPPORTED; } diff --git a/src/devices/cpu/z8/z8dasm.cpp b/src/devices/cpu/z8/z8dasm.cpp index 08e50ca1eae..beef0da436a 100644 --- a/src/devices/cpu/z8/z8dasm.cpp +++ b/src/devices/cpu/z8/z8dasm.cpp @@ -60,7 +60,7 @@ const char *const z8_disassembler::CONDITION_CODE[16] = #define ARG(_formatting, _value) { if (argc) util::stream_format(stream, ", "); util::stream_format(stream, _formatting, _value); argc++; } #define arg_name(_value) ARG("%s", REGISTER_NAME[_value]) -#define arg_cc ARG("%s", CONDITION_CODE[OPH]) +#define arg_cc { ARG("%s", CONDITION_CODE[OPH]); if (OPH & 0x0e) step_cond; } #define arg_r(_value) ARG(r, _value) #define arg_Ir(_value) ARG(Ir, _value) #define arg_Irr(_value) ARG(Irr, _value & 0x0f) @@ -78,6 +78,7 @@ const char *const z8_disassembler::CONDITION_CODE[16] = #define bytes(_count) pos += (_count - 1) #define step_over flags = STEP_OVER #define step_out flags = STEP_OUT +#define step_cond flags = STEP_COND /*************************************************************************** DISASSEMBLER @@ -117,7 +118,7 @@ offs_t z8_disassembler::disassemble(std::ostream &stream, offs_t pc, const data_ case 0x07: mnemonic("ADD"); arg_IR(B0); arg_IM(B1); bytes(3); break; case 0x08: mnemonic("LD"); arg_r(OPH); arg_R(B0); bytes(2); break; case 0x09: mnemonic("LD"); arg_R(B0); arg_r(OPH); bytes(2); break; - case 0x0a: mnemonic("DJNZ"); arg_r(OPH); arg_RA; bytes(2); step_over; break; + case 0x0a: mnemonic("DJNZ"); arg_r(OPH); arg_RA; bytes(2); step_cond; break; case 0x0b: mnemonic("JR"); arg_cc; arg_RA; bytes(2); break; case 0x0c: mnemonic("LD"); arg_r(OPH); arg_IM(B0); bytes(2); break; case 0x0d: mnemonic("JP"); arg_cc; arg_DA; bytes(3); break; @@ -134,7 +135,7 @@ offs_t z8_disassembler::disassemble(std::ostream &stream, offs_t pc, const data_ case 0x17: mnemonic("ADC"); arg_IR(B0); arg_IM(B1); bytes(3); break; case 0x18: mnemonic("LD"); arg_r(OPH); arg_R(B0); bytes(2); break; case 0x19: mnemonic("LD"); arg_R(B0); arg_r(OPH); bytes(2); break; - case 0x1a: mnemonic("DJNZ"); arg_r(OPH); arg_RA; bytes(2); step_over; break; + case 0x1a: mnemonic("DJNZ"); arg_r(OPH); arg_RA; bytes(2); step_cond; break; case 0x1b: mnemonic("JR"); arg_cc; arg_RA; bytes(2); break; case 0x1c: mnemonic("LD"); arg_r(OPH); arg_IM(B0); bytes(2); break; case 0x1d: mnemonic("JP"); arg_cc; arg_DA; bytes(3); break; @@ -151,7 +152,7 @@ offs_t z8_disassembler::disassemble(std::ostream &stream, offs_t pc, const data_ case 0x27: mnemonic("SUB"); arg_IR(B0); arg_IM(B1); bytes(3); break; case 0x28: mnemonic("LD"); arg_r(OPH); arg_R(B0); bytes(2); break; case 0x29: mnemonic("LD"); arg_R(B0); arg_r(OPH); bytes(2); break; - case 0x2a: mnemonic("DJNZ"); arg_r(OPH); arg_RA; bytes(2); step_over; break; + case 0x2a: mnemonic("DJNZ"); arg_r(OPH); arg_RA; bytes(2); step_cond; break; case 0x2b: mnemonic("JR"); arg_cc; arg_RA; bytes(2); break; case 0x2c: mnemonic("LD"); arg_r(OPH); arg_IM(B0); bytes(2); break; case 0x2d: mnemonic("JP"); arg_cc; arg_DA; bytes(3); break; @@ -168,7 +169,7 @@ offs_t z8_disassembler::disassemble(std::ostream &stream, offs_t pc, const data_ case 0x37: mnemonic("SBC"); arg_IR(B0); arg_IM(B1); bytes(3); break; case 0x38: mnemonic("LD"); arg_r(OPH); arg_R(B0); bytes(2); break; case 0x39: mnemonic("LD"); arg_R(B0); arg_r(OPH); bytes(2); break; - case 0x3a: mnemonic("DJNZ"); arg_r(OPH); arg_RA; bytes(2); step_over; break; + case 0x3a: mnemonic("DJNZ"); arg_r(OPH); arg_RA; bytes(2); step_cond; break; case 0x3b: mnemonic("JR"); arg_cc; arg_RA; bytes(2); break; case 0x3c: mnemonic("LD"); arg_r(OPH); arg_IM(B0); bytes(2); break; case 0x3d: mnemonic("JP"); arg_cc; arg_DA; bytes(3); break; @@ -185,7 +186,7 @@ offs_t z8_disassembler::disassemble(std::ostream &stream, offs_t pc, const data_ case 0x47: mnemonic("OR"); arg_IR(B0); arg_IM(B1); bytes(3); break; case 0x48: mnemonic("LD"); arg_r(OPH); arg_R(B0); bytes(2); break; case 0x49: mnemonic("LD"); arg_R(B0); arg_r(OPH); bytes(2); break; - case 0x4a: mnemonic("DJNZ"); arg_r(OPH); arg_RA; bytes(2); step_over; break; + case 0x4a: mnemonic("DJNZ"); arg_r(OPH); arg_RA; bytes(2); step_cond; break; case 0x4b: mnemonic("JR"); arg_cc; arg_RA; bytes(2); break; case 0x4c: mnemonic("LD"); arg_r(OPH); arg_IM(B0); bytes(2); break; case 0x4d: mnemonic("JP"); arg_cc; arg_DA; bytes(3); break; @@ -202,7 +203,7 @@ offs_t z8_disassembler::disassemble(std::ostream &stream, offs_t pc, const data_ case 0x57: mnemonic("AND"); arg_IR(B0); arg_IM(B1); bytes(3); break; case 0x58: mnemonic("LD"); arg_r(OPH); arg_R(B0); bytes(2); break; case 0x59: mnemonic("LD"); arg_R(B0); arg_r(OPH); bytes(2); break; - case 0x5a: mnemonic("DJNZ"); arg_r(OPH); arg_RA; bytes(2); step_over; break; + case 0x5a: mnemonic("DJNZ"); arg_r(OPH); arg_RA; bytes(2); step_cond; break; case 0x5b: mnemonic("JR"); arg_cc; arg_RA; bytes(2); break; case 0x5c: mnemonic("LD"); arg_r(OPH); arg_IM(B0); bytes(2); break; case 0x5d: mnemonic("JP"); arg_cc; arg_DA; bytes(3); break; @@ -219,7 +220,7 @@ offs_t z8_disassembler::disassemble(std::ostream &stream, offs_t pc, const data_ case 0x67: mnemonic("TCM"); arg_IR(B0); arg_IM(B1); bytes(3); break; case 0x68: mnemonic("LD"); arg_r(OPH); arg_R(B0); bytes(2); break; case 0x69: mnemonic("LD"); arg_R(B0); arg_r(OPH); bytes(2); break; - case 0x6a: mnemonic("DJNZ"); arg_r(OPH); arg_RA; bytes(2); step_over; break; + case 0x6a: mnemonic("DJNZ"); arg_r(OPH); arg_RA; bytes(2); step_cond; break; case 0x6b: mnemonic("JR"); arg_cc; arg_RA; bytes(2); break; case 0x6c: mnemonic("LD"); arg_r(OPH); arg_IM(B0); bytes(2); break; case 0x6d: mnemonic("JP"); arg_cc; arg_DA; bytes(3); break; @@ -236,7 +237,7 @@ offs_t z8_disassembler::disassemble(std::ostream &stream, offs_t pc, const data_ case 0x77: mnemonic("TM"); arg_IR(B0); arg_IM(B1); bytes(3); break; case 0x78: mnemonic("LD"); arg_r(OPH); arg_R(B0); bytes(2); break; case 0x79: mnemonic("LD"); arg_R(B0); arg_r(OPH); bytes(2); break; - case 0x7a: mnemonic("DJNZ"); arg_r(OPH); arg_RA; bytes(2); step_over; break; + case 0x7a: mnemonic("DJNZ"); arg_r(OPH); arg_RA; bytes(2); step_cond; break; case 0x7b: mnemonic("JR"); arg_cc; arg_RA; bytes(2); break; case 0x7c: mnemonic("LD"); arg_r(OPH); arg_IM(B0); bytes(2); break; case 0x7d: mnemonic("JP"); arg_cc; arg_DA; bytes(3); break; @@ -253,7 +254,7 @@ offs_t z8_disassembler::disassemble(std::ostream &stream, offs_t pc, const data_ case 0x87: illegal; break; case 0x88: mnemonic("LD"); arg_r(OPH); arg_R(B0); bytes(2); break; case 0x89: mnemonic("LD"); arg_R(B0); arg_r(OPH); bytes(2); break; - case 0x8a: mnemonic("DJNZ"); arg_r(OPH); arg_RA; bytes(2); step_over; break; + case 0x8a: mnemonic("DJNZ"); arg_r(OPH); arg_RA; bytes(2); step_cond; break; case 0x8b: mnemonic("JR"); arg_RA; bytes(2); break; case 0x8c: mnemonic("LD"); arg_r(OPH); arg_IM(B0); bytes(2); break; case 0x8d: mnemonic("JP"); arg_DA; bytes(3); break; @@ -270,7 +271,7 @@ offs_t z8_disassembler::disassemble(std::ostream &stream, offs_t pc, const data_ case 0x97: illegal; break; case 0x98: mnemonic("LD"); arg_r(OPH); arg_R(B0); bytes(2); break; case 0x99: mnemonic("LD"); arg_R(B0); arg_r(OPH); bytes(2); break; - case 0x9a: mnemonic("DJNZ"); arg_r(OPH); arg_RA; bytes(2); step_over; break; + case 0x9a: mnemonic("DJNZ"); arg_r(OPH); arg_RA; bytes(2); step_cond; break; case 0x9b: mnemonic("JR"); arg_cc; arg_RA; bytes(2); break; case 0x9c: mnemonic("LD"); arg_r(OPH); arg_IM(B0); bytes(2); break; case 0x9d: mnemonic("JP"); arg_cc; arg_DA; bytes(3); break; @@ -287,7 +288,7 @@ offs_t z8_disassembler::disassemble(std::ostream &stream, offs_t pc, const data_ case 0xa7: mnemonic("CP"); arg_IR(B0); arg_IM(B1); bytes(3); break; case 0xa8: mnemonic("LD"); arg_r(OPH); arg_R(B0); bytes(2); break; case 0xa9: mnemonic("LD"); arg_R(B0); arg_r(OPH); bytes(2); break; - case 0xaa: mnemonic("DJNZ"); arg_r(OPH); arg_RA; bytes(2); step_over; break; + case 0xaa: mnemonic("DJNZ"); arg_r(OPH); arg_RA; bytes(2); step_cond; break; case 0xab: mnemonic("JR"); arg_cc; arg_RA; bytes(2); break; case 0xac: mnemonic("LD"); arg_r(OPH); arg_IM(B0); bytes(2); break; case 0xad: mnemonic("JP"); arg_cc; arg_DA; bytes(3); break; @@ -304,7 +305,7 @@ offs_t z8_disassembler::disassemble(std::ostream &stream, offs_t pc, const data_ case 0xb7: mnemonic("XOR"); arg_IR(B0); arg_IM(B1); bytes(3); break; case 0xb8: mnemonic("LD"); arg_r(OPH); arg_R(B0); bytes(2); break; case 0xb9: mnemonic("LD"); arg_R(B0); arg_r(OPH); bytes(2); break; - case 0xba: mnemonic("DJNZ"); arg_r(OPH); arg_RA; bytes(2); step_over; break; + case 0xba: mnemonic("DJNZ"); arg_r(OPH); arg_RA; bytes(2); step_cond; break; case 0xbb: mnemonic("JR"); arg_cc; arg_RA; bytes(2); break; case 0xbc: mnemonic("LD"); arg_r(OPH); arg_IM(B0); bytes(2); break; case 0xbd: mnemonic("JP"); arg_cc; arg_DA; bytes(3); break; @@ -321,7 +322,7 @@ offs_t z8_disassembler::disassemble(std::ostream &stream, offs_t pc, const data_ case 0xc7: mnemonic("LD"); arg_r(B0H); arg_X(B1, B0L); bytes(3); break; case 0xc8: mnemonic("LD"); arg_r(OPH); arg_R(B0); bytes(2); break; case 0xc9: mnemonic("LD"); arg_R(B0); arg_r(OPH); bytes(2); break; - case 0xca: mnemonic("DJNZ"); arg_r(OPH); arg_RA; bytes(2); step_over; break; + case 0xca: mnemonic("DJNZ"); arg_r(OPH); arg_RA; bytes(2); step_cond; break; case 0xcb: mnemonic("JR"); arg_cc; arg_RA; bytes(2); break; case 0xcc: mnemonic("LD"); arg_r(OPH); arg_IM(B0); bytes(2); break; case 0xcd: mnemonic("JP"); arg_cc; arg_DA; bytes(3); break; @@ -338,7 +339,7 @@ offs_t z8_disassembler::disassemble(std::ostream &stream, offs_t pc, const data_ case 0xd7: mnemonic("LD"); arg_r(B0L); arg_X(B1, B0H); bytes(3); break; case 0xd8: mnemonic("LD"); arg_r(OPH); arg_R(B0); bytes(2); break; case 0xd9: mnemonic("LD"); arg_R(B0); arg_r(OPH); bytes(2); break; - case 0xda: mnemonic("DJNZ"); arg_r(OPH); arg_RA; bytes(2); step_over; break; + case 0xda: mnemonic("DJNZ"); arg_r(OPH); arg_RA; bytes(2); step_cond; break; case 0xdb: mnemonic("JR"); arg_cc; arg_RA; bytes(2); break; case 0xdc: mnemonic("LD"); arg_r(OPH); arg_IM(B0); bytes(2); break; case 0xdd: mnemonic("JP"); arg_cc; arg_DA; bytes(3); break; @@ -355,7 +356,7 @@ offs_t z8_disassembler::disassemble(std::ostream &stream, offs_t pc, const data_ case 0xe7: mnemonic("LD"); arg_IR(B0); arg_IM(B1); bytes(3); break; case 0xe8: mnemonic("LD"); arg_r(OPH); arg_R(B0); bytes(2); break; case 0xe9: mnemonic("LD"); arg_R(B0); arg_r(OPH); bytes(2); break; - case 0xea: mnemonic("DJNZ"); arg_r(OPH); arg_RA; bytes(2); step_over; break; + case 0xea: mnemonic("DJNZ"); arg_r(OPH); arg_RA; bytes(2); step_cond; break; case 0xeb: mnemonic("JR"); arg_cc; arg_RA; bytes(2); break; case 0xec: mnemonic("LD"); arg_r(OPH); arg_IM(B0); bytes(2); break; case 0xed: mnemonic("JP"); arg_cc; arg_DA; bytes(3); break; @@ -372,7 +373,7 @@ offs_t z8_disassembler::disassemble(std::ostream &stream, offs_t pc, const data_ case 0xf7: illegal; break; case 0xf8: mnemonic("LD"); arg_r(OPH); arg_R(B0); bytes(2); break; case 0xf9: mnemonic("LD"); arg_R(B0); arg_r(OPH); bytes(2); break; - case 0xfa: mnemonic("DJNZ"); arg_r(OPH); arg_RA; bytes(2); step_over; break; + case 0xfa: mnemonic("DJNZ"); arg_r(OPH); arg_RA; bytes(2); step_cond; break; case 0xfb: mnemonic("JR"); arg_cc; arg_RA; bytes(2); break; case 0xfc: mnemonic("LD"); arg_r(OPH); arg_IM(B0); bytes(2); break; case 0xfd: mnemonic("JP"); arg_cc; arg_DA; bytes(3); break; diff --git a/src/devices/cpu/z80/z80dasm.cpp b/src/devices/cpu/z80/z80dasm.cpp index 5357f86f661..7ad69a20e5a 100644 --- a/src/devices/cpu/z80/z80dasm.cpp +++ b/src/devices/cpu/z80/z80dasm.cpp @@ -28,10 +28,10 @@ static const char *const s_mnemonic[] = const u32 z80_disassembler::s_flags[] = { 0 ,0 ,0 ,0 ,STEP_OVER,0 ,0 ,0 , - STEP_OVER,0 ,STEP_OVER,0 ,0 ,0 ,0 ,0 , - STEP_OVER,0 ,0 ,0 ,STEP_OVER,0 ,0 ,0 , - 0 ,STEP_OVER,0 ,STEP_OVER,0 ,0 ,0 ,0 , - STEP_OVER,0 ,STEP_OVER,0 ,0 ,0 ,STEP_OVER,STEP_OVER, + STEP_COND,0 ,STEP_COND,0 ,0 ,0 ,0 ,0 , + STEP_COND,0 ,0 ,0 ,STEP_OVER,0 ,0 ,0 , + 0 ,STEP_COND,0 ,STEP_COND,0 ,0 ,0 ,0 , + STEP_COND,0 ,STEP_COND,0 ,0 ,0 ,STEP_COND,STEP_COND, 0 ,0 ,0 ,0 ,0 ,0 ,STEP_OUT ,STEP_OUT , STEP_OUT ,0 ,0 ,0 ,0 ,0 ,0 ,0 , 0 ,0 ,0 ,STEP_OVER,0 ,0 ,0 ,0 , @@ -460,6 +460,7 @@ offs_t z80_disassembler::disassemble(std::ostream &stream, offs_t pc, const data break; } + uint32_t flags = s_flags[d->mnemonic]; if( d->arguments ) { util::stream_format(stream, "%-4s ", s_mnemonic[d->mnemonic]); @@ -474,6 +475,8 @@ offs_t z80_disassembler::disassemble(std::ostream &stream, offs_t pc, const data case 'A': util::stream_format(stream, "$%04X", params.r16(pos) ); pos += 2; + if (src != d->arguments) + flags |= STEP_COND; break; case 'B': /* Byte op arg */ util::stream_format(stream, "$%02X", params.r8(pos++) ); @@ -484,6 +487,8 @@ offs_t z80_disassembler::disassemble(std::ostream &stream, offs_t pc, const data break; case 'O': /* Offset relative to PC */ util::stream_format(stream, "$%04X", (pc + s8(params.r8(pos++)) + 2) & 0xffff); + if (src != d->arguments) + flags |= STEP_COND; break; case 'P': /* Port number */ util::stream_format(stream, "$%02X", params.r8(pos++) ); @@ -509,11 +514,13 @@ offs_t z80_disassembler::disassemble(std::ostream &stream, offs_t pc, const data } src++; } + if (d->mnemonic == zRET) + flags |= STEP_COND; } else { util::stream_format(stream, "%s", s_mnemonic[d->mnemonic]); } - return (pos - pc) | s_flags[d->mnemonic] | SUPPORTED; + return (pos - pc) | flags | SUPPORTED; } diff --git a/src/devices/cpu/z8000/8000dasm.cpp b/src/devices/cpu/z8000/8000dasm.cpp index 42a7d0abeb3..b42df93bf35 100644 --- a/src/devices/cpu/z8000/8000dasm.cpp +++ b/src/devices/cpu/z8000/8000dasm.cpp @@ -79,7 +79,7 @@ const z8000_disassembler::opcode z8000_disassembler::table[] = { { 0x1c18, 0x1cf8, 16, 1, "testl @%rw2", 0 }, { 0x1c19, 0x1cf9, 16, 2, "ldm @%rw2,%rw5,#%n", 0 }, { 0x1d10, 0x1dff, 1, 1, "ldl @%rw2,%rl3", 0 }, - { 0x1e10, 0x1eff, 1, 1, "jp %c3,@%rl2", 0 }, + { 0x1e10, 0x1eff, 1, 1, "jp %c3,@%rl2", STEP_COND }, { 0x1f10, 0x1ff0, 16, 1, "call %rw2", STEP_OVER }, { 0x2000, 0x200f, 1, 2, "ldb %rb3,%#b3", 0 }, { 0x2010, 0x20ff, 1, 1, "ldb %rb3,@%rw2", 0 }, @@ -292,8 +292,8 @@ const z8000_disassembler::opcode z8000_disassembler::table[] = { { 0x5c19, 0x5cf9, 16, 3, "ldm %a2(%rw2),%rw5,#%n", 0 }, { 0x5d00, 0x5d0f, 1, 2, "ldl %a1,%rl3", 0 }, { 0x5d10, 0x5dff, 1, 2, "ldl %a1(%rw2),%rl3", 0 }, - { 0x5e00, 0x5e0f, 1, 2, "jp %c3,%a1", 0 }, - { 0x5e10, 0x5eff, 1, 2, "jp %c3,%a1(%rw2)", 0 }, + { 0x5e00, 0x5e0f, 1, 2, "jp %c3,%a1", STEP_COND }, + { 0x5e10, 0x5eff, 1, 2, "jp %c3,%a1(%rw2)", STEP_COND }, { 0x5f00, 0x5f00, 1, 2, "call %a1", STEP_OVER }, { 0x5f10, 0x5ff0, 16, 2, "call %a1(%rw2)", STEP_OVER }, { 0x6000, 0x600f, 1, 2, "ldb %rb3,%a1", 0 }, @@ -410,7 +410,7 @@ const z8000_disassembler::opcode z8000_disassembler::table[] = { { 0x9b00, 0x9bff, 1, 1, "div %rl3,%rw2", 0 }, { 0x9c00, 0x9cf8, 8, 1, "testl %rl2", 0 }, { 0x9d00, 0x9dff, 1, 1, "rsvd9d", 0 }, - { 0x9e00, 0x9e0f, 1, 1, "ret %c3", STEP_OUT }, + { 0x9e00, 0x9e0f, 1, 1, "ret %c3", STEP_OUT | STEP_COND }, { 0x9f00, 0x9fff, 1, 1, "rsvd9f", 0 }, { 0xa000, 0xa0ff, 1, 1, "ldb %rb3,%rb2", 0 }, { 0xa100, 0xa1ff, 1, 1, "ld %rw3,%rw2", 0 }, @@ -474,64 +474,64 @@ const z8000_disassembler::opcode z8000_disassembler::table[] = { { 0xb81e, 0xb8fe, 16, 2, "trtdrb @%rw2,@%rw6,%rb5", 0 }, { 0xb900, 0xb9ff, 16, 1, "rsvdb9", 0 }, { 0xba10, 0xbaf0, 16, 2, "cpib %rb6,@%rw2,%rw5,%c7", 0 }, - { 0xba11, 0xbaf1, 16, 2, "ldirb @%rw6,@%rw2,%rw5", STEP_OVER }, + { 0xba11, 0xbaf1, 16, 2, "ldirb @%rw6,@%rw2,%rw5", STEP_COND }, { 0xba12, 0xbaf2, 16, 2, "cpsib @%rw6,@%rw2,%rw5,%c7", 0 }, - { 0xba14, 0xbaf4, 16, 2, "cpirb %rb6,@%rw2,%rw5,%c7", STEP_OVER }, - { 0xba16, 0xbaf6, 16, 2, "cpsirb @%rw6,@%rw2,%rw5,%c7", STEP_OVER }, + { 0xba14, 0xbaf4, 16, 2, "cpirb %rb6,@%rw2,%rw5,%c7", STEP_COND }, + { 0xba16, 0xbaf6, 16, 2, "cpsirb @%rw6,@%rw2,%rw5,%c7", STEP_COND }, { 0xba18, 0xbaf8, 16, 2, "cpdb %rb6,@%rw2,%rw5,%c7", 0 }, - { 0xba19, 0xbaf9, 16, 2, "lddrb @%rw2,@%rw6,%rw5", STEP_OVER }, + { 0xba19, 0xbaf9, 16, 2, "lddrb @%rw2,@%rw6,%rw5", STEP_COND }, { 0xba1a, 0xbafa, 16, 2, "cpsdb @%rw6,@%rw2,%rw5,%c7", 0 }, - { 0xba1c, 0xbafc, 16, 2, "cpdrb %rb6,@%rw2,%rw5,%c7", STEP_OVER }, - { 0xba1e, 0xbafe, 16, 2, "cpsdrb @%rw6,@%rw2,%rw5,%c7", STEP_OVER }, + { 0xba1c, 0xbafc, 16, 2, "cpdrb %rb6,@%rw2,%rw5,%c7", STEP_COND }, + { 0xba1e, 0xbafe, 16, 2, "cpsdrb @%rw6,@%rw2,%rw5,%c7", STEP_COND }, { 0xbb10, 0xbbf0, 16, 2, "cpi %rw6,@%rw2,%rw5,%c7", 0 }, - { 0xbb11, 0xbbf1, 16, 2, "ldir @%rw6,@%rw2,%rw5", STEP_OVER }, + { 0xbb11, 0xbbf1, 16, 2, "ldir @%rw6,@%rw2,%rw5", STEP_COND }, { 0xbb12, 0xbbf2, 16, 2, "cpsi @%rw6,@%rw2,%rw5,%c7", 0 }, - { 0xbb14, 0xbbf4, 16, 2, "cpir %rw6,@%rw2,%rw5,%c7", STEP_OVER }, - { 0xbb16, 0xbbf6, 16, 2, "cpsir @%rw6,@%rw2,%rw5,%c7", STEP_OVER }, + { 0xbb14, 0xbbf4, 16, 2, "cpir %rw6,@%rw2,%rw5,%c7", STEP_COND }, + { 0xbb16, 0xbbf6, 16, 2, "cpsir @%rw6,@%rw2,%rw5,%c7", STEP_COND }, { 0xbb18, 0xbbf8, 16, 2, "cpd %rw6,@%rw2,%rw5,%c7", 0 }, - { 0xbb19, 0xbbf9, 16, 2, "lddr @%rw2,@%rw6,%rw5", STEP_OVER }, + { 0xbb19, 0xbbf9, 16, 2, "lddr @%rw2,@%rw6,%rw5", STEP_COND }, { 0xbb1a, 0xbbfa, 16, 2, "cpsd @%rw6,@%rw2,%rw5,%c7", 0 }, - { 0xbb1c, 0xbbfc, 16, 2, "cpdr %rw6,@%rw2,%rw5,%c7", STEP_OVER }, - { 0xbb1e, 0xbbfe, 16, 2, "cpsdr @%rw6,@%rw2,%rw5,%c7", STEP_OVER }, + { 0xbb1c, 0xbbfc, 16, 2, "cpdr %rw6,@%rw2,%rw5,%c7", STEP_COND }, + { 0xbb1e, 0xbbfe, 16, 2, "cpsdr @%rw6,@%rw2,%rw5,%c7", STEP_COND }, { 0xbc00, 0xbcff, 1, 1, "rrdb %rb3,%rb2", 0 }, { 0xbd00, 0xbdff, 1, 1, "ldk %rw2,%3", 0 }, { 0xbe00, 0xbeff, 1, 1, "rldb %rb3,%rb2", 0 }, { 0xbf00, 0xbfff, 1, 1, "rsvdbf", 0 }, { 0xc000, 0xcfff, 1, 1, "ldb %rb1,%#b1", 0 }, { 0xd000, 0xdfff, 1, 1, "calr %d2", STEP_OVER }, - { 0xe000, 0xefff, 1, 1, "jr %c1,%d1", 0 }, - { 0xf000, 0xf07f, 1, 1, "dbjnz %rb1,%d0", STEP_OVER }, - { 0xf100, 0xf17f, 1, 1, "dbjnz %rb1,%d0", STEP_OVER }, - { 0xf200, 0xf27f, 1, 1, "dbjnz %rb1,%d0", STEP_OVER }, - { 0xf300, 0xf37f, 1, 1, "dbjnz %rb1,%d0", STEP_OVER }, - { 0xf400, 0xf47f, 1, 1, "dbjnz %rb1,%d0", STEP_OVER }, - { 0xf500, 0xf57f, 1, 1, "dbjnz %rb1,%d0", STEP_OVER }, - { 0xf600, 0xf67f, 1, 1, "dbjnz %rb1,%d0", STEP_OVER }, - { 0xf700, 0xf77f, 1, 1, "dbjnz %rb1,%d0", STEP_OVER }, - { 0xf800, 0xf87f, 1, 1, "dbjnz %rb1,%d0", STEP_OVER }, - { 0xf900, 0xf97f, 1, 1, "dbjnz %rb1,%d0", STEP_OVER }, - { 0xfa00, 0xfa7f, 1, 1, "dbjnz %rb1,%d0", STEP_OVER }, - { 0xfb00, 0xfb7f, 1, 1, "dbjnz %rb1,%d0", STEP_OVER }, - { 0xfc00, 0xfc7f, 1, 1, "dbjnz %rb1,%d0", STEP_OVER }, - { 0xfd00, 0xfd7f, 1, 1, "dbjnz %rb1,%d0", STEP_OVER }, - { 0xfe00, 0xfe7f, 1, 1, "dbjnz %rb1,%d0", STEP_OVER }, - { 0xff00, 0xff7f, 1, 1, "dbjnz %rb1,%d0", STEP_OVER }, - { 0xf080, 0xf0ff, 1, 1, "djnz %rw1,%d0", STEP_OVER }, - { 0xf180, 0xf1ff, 1, 1, "djnz %rw1,%d0", STEP_OVER }, - { 0xf280, 0xf2ff, 1, 1, "djnz %rw1,%d0", STEP_OVER }, - { 0xf380, 0xf3ff, 1, 1, "djnz %rw1,%d0", STEP_OVER }, - { 0xf480, 0xf4ff, 1, 1, "djnz %rw1,%d0", STEP_OVER }, - { 0xf580, 0xf5ff, 1, 1, "djnz %rw1,%d0", STEP_OVER }, - { 0xf680, 0xf6ff, 1, 1, "djnz %rw1,%d0", STEP_OVER }, - { 0xf780, 0xf7ff, 1, 1, "djnz %rw1,%d0", STEP_OVER }, - { 0xf880, 0xf8ff, 1, 1, "djnz %rw1,%d0", STEP_OVER }, - { 0xf980, 0xf9ff, 1, 1, "djnz %rw1,%d0", STEP_OVER }, - { 0xfa80, 0xfaff, 1, 1, "djnz %rw1,%d0", STEP_OVER }, - { 0xfb80, 0xfbff, 1, 1, "djnz %rw1,%d0", STEP_OVER }, - { 0xfc80, 0xfcff, 1, 1, "djnz %rw1,%d0", STEP_OVER }, - { 0xfd80, 0xfdff, 1, 1, "djnz %rw1,%d0", STEP_OVER }, - { 0xfe80, 0xfeff, 1, 1, "djnz %rw1,%d0", STEP_OVER }, - { 0xff80, 0xffff, 1, 1, "djnz %rw1,%d0", STEP_OVER }, + { 0xe000, 0xefff, 1, 1, "jr %c1,%d1", STEP_COND }, + { 0xf000, 0xf07f, 1, 1, "dbjnz %rb1,%d0", STEP_COND }, + { 0xf100, 0xf17f, 1, 1, "dbjnz %rb1,%d0", STEP_COND }, + { 0xf200, 0xf27f, 1, 1, "dbjnz %rb1,%d0", STEP_COND }, + { 0xf300, 0xf37f, 1, 1, "dbjnz %rb1,%d0", STEP_COND }, + { 0xf400, 0xf47f, 1, 1, "dbjnz %rb1,%d0", STEP_COND }, + { 0xf500, 0xf57f, 1, 1, "dbjnz %rb1,%d0", STEP_COND }, + { 0xf600, 0xf67f, 1, 1, "dbjnz %rb1,%d0", STEP_COND }, + { 0xf700, 0xf77f, 1, 1, "dbjnz %rb1,%d0", STEP_COND }, + { 0xf800, 0xf87f, 1, 1, "dbjnz %rb1,%d0", STEP_COND }, + { 0xf900, 0xf97f, 1, 1, "dbjnz %rb1,%d0", STEP_COND }, + { 0xfa00, 0xfa7f, 1, 1, "dbjnz %rb1,%d0", STEP_COND }, + { 0xfb00, 0xfb7f, 1, 1, "dbjnz %rb1,%d0", STEP_COND }, + { 0xfc00, 0xfc7f, 1, 1, "dbjnz %rb1,%d0", STEP_COND }, + { 0xfd00, 0xfd7f, 1, 1, "dbjnz %rb1,%d0", STEP_COND }, + { 0xfe00, 0xfe7f, 1, 1, "dbjnz %rb1,%d0", STEP_COND }, + { 0xff00, 0xff7f, 1, 1, "dbjnz %rb1,%d0", STEP_COND }, + { 0xf080, 0xf0ff, 1, 1, "djnz %rw1,%d0", STEP_COND }, + { 0xf180, 0xf1ff, 1, 1, "djnz %rw1,%d0", STEP_COND }, + { 0xf280, 0xf2ff, 1, 1, "djnz %rw1,%d0", STEP_COND }, + { 0xf380, 0xf3ff, 1, 1, "djnz %rw1,%d0", STEP_COND }, + { 0xf480, 0xf4ff, 1, 1, "djnz %rw1,%d0", STEP_COND }, + { 0xf580, 0xf5ff, 1, 1, "djnz %rw1,%d0", STEP_COND }, + { 0xf680, 0xf6ff, 1, 1, "djnz %rw1,%d0", STEP_COND }, + { 0xf780, 0xf7ff, 1, 1, "djnz %rw1,%d0", STEP_COND }, + { 0xf880, 0xf8ff, 1, 1, "djnz %rw1,%d0", STEP_COND }, + { 0xf980, 0xf9ff, 1, 1, "djnz %rw1,%d0", STEP_COND }, + { 0xfa80, 0xfaff, 1, 1, "djnz %rw1,%d0", STEP_COND }, + { 0xfb80, 0xfbff, 1, 1, "djnz %rw1,%d0", STEP_COND }, + { 0xfc80, 0xfcff, 1, 1, "djnz %rw1,%d0", STEP_COND }, + { 0xfd80, 0xfdff, 1, 1, "djnz %rw1,%d0", STEP_COND }, + { 0xfe80, 0xfeff, 1, 1, "djnz %rw1,%d0", STEP_COND }, + { 0xff80, 0xffff, 1, 1, "djnz %rw1,%d0", STEP_COND }, { 0, 0, 0, 0, nullptr, 0} }; @@ -667,14 +667,14 @@ offs_t z8000_disassembler::disassemble(std::ostream &stream, offs_t pc, const da tmp = ((n[1] & 0x01) << 8) + (n[3] << 4) + (n[7] & 0x08); switch (tmp) { - case 0x000: util::stream_format(stream, "inirb "); flags = STEP_OVER; break; + case 0x000: util::stream_format(stream, "inirb "); flags = STEP_COND; break; case 0x008: util::stream_format(stream, "inib "); break; - case 0x010: util::stream_format(stream, "sinirb"); flags = STEP_OVER; break; + case 0x010: util::stream_format(stream, "sinirb"); flags = STEP_COND; break; case 0x018: util::stream_format(stream, "sinib "); break; - case 0x020: util::stream_format(stream, "otirb "); flags = STEP_OVER; break; + case 0x020: util::stream_format(stream, "otirb "); flags = STEP_COND; break; case 0x028: util::stream_format(stream, "outib "); break; case 0x030: util::stream_format(stream, "soutib"); break; - case 0x038: util::stream_format(stream, "sotirb"); flags = STEP_OVER; break; + case 0x038: util::stream_format(stream, "sotirb"); flags = STEP_COND; break; case 0x040: util::stream_format(stream, "inb "); break; case 0x048: util::stream_format(stream, "inb "); break; case 0x050: util::stream_format(stream, "sinb "); break; @@ -683,22 +683,22 @@ offs_t z8000_disassembler::disassemble(std::ostream &stream, offs_t pc, const da case 0x068: util::stream_format(stream, "outb "); break; case 0x070: util::stream_format(stream, "soutb "); break; case 0x078: util::stream_format(stream, "soutb "); break; - case 0x080: util::stream_format(stream, "indrb "); flags = STEP_OVER; break; + case 0x080: util::stream_format(stream, "indrb "); flags = STEP_COND; break; case 0x088: util::stream_format(stream, "indb "); break; - case 0x090: util::stream_format(stream, "sindrb"); flags = STEP_OVER; break; + case 0x090: util::stream_format(stream, "sindrb"); flags = STEP_COND; break; case 0x098: util::stream_format(stream, "sindb "); break; - case 0x0a0: util::stream_format(stream, "otdrb "); flags = STEP_OVER; break; + case 0x0a0: util::stream_format(stream, "otdrb "); flags = STEP_COND; break; case 0x0a8: util::stream_format(stream, "outdb "); break; case 0x0b0: util::stream_format(stream, "soutdb"); break; - case 0x0b8: util::stream_format(stream, "sotdrb"); flags = STEP_OVER; break; - case 0x100: util::stream_format(stream, "inir "); flags = STEP_OVER; break; + case 0x0b8: util::stream_format(stream, "sotdrb"); flags = STEP_COND; break; + case 0x100: util::stream_format(stream, "inir "); flags = STEP_COND; break; case 0x108: util::stream_format(stream, "ini "); break; - case 0x110: util::stream_format(stream, "sinir "); flags = STEP_OVER; break; + case 0x110: util::stream_format(stream, "sinir "); flags = STEP_COND; break; case 0x118: util::stream_format(stream, "sini "); break; - case 0x120: util::stream_format(stream, "otir "); flags = STEP_OVER; break; + case 0x120: util::stream_format(stream, "otir "); flags = STEP_COND; break; case 0x128: util::stream_format(stream, "outi "); break; case 0x130: util::stream_format(stream, "souti "); break; - case 0x138: util::stream_format(stream, "sotir "); flags = STEP_OVER; break; + case 0x138: util::stream_format(stream, "sotir "); flags = STEP_COND; break; case 0x140: util::stream_format(stream, "in "); break; case 0x148: util::stream_format(stream, "in "); break; case 0x150: util::stream_format(stream, "sin "); break; @@ -707,14 +707,14 @@ offs_t z8000_disassembler::disassemble(std::ostream &stream, offs_t pc, const da case 0x168: util::stream_format(stream, "out "); break; case 0x170: util::stream_format(stream, "sout "); break; case 0x178: util::stream_format(stream, "sout "); break; - case 0x180: util::stream_format(stream, "indr "); flags = STEP_OVER; break; + case 0x180: util::stream_format(stream, "indr "); flags = STEP_COND; break; case 0x188: util::stream_format(stream, "ind "); break; - case 0x190: util::stream_format(stream, "sindr "); flags = STEP_OVER; break; + case 0x190: util::stream_format(stream, "sindr "); flags = STEP_COND; break; case 0x198: util::stream_format(stream, "sind "); break; - case 0x1a0: util::stream_format(stream, "otdr "); flags = STEP_OVER; break; + case 0x1a0: util::stream_format(stream, "otdr "); flags = STEP_COND; break; case 0x1a8: util::stream_format(stream, "outd "); break; case 0x1b0: util::stream_format(stream, "soutd "); break; - case 0x1b8: util::stream_format(stream, "sotdr "); flags = STEP_OVER; break; + case 0x1b8: util::stream_format(stream, "sotdr "); flags = STEP_COND; break; default: util::stream_format(stream, "unk(0x%x)", tmp); } @@ -747,8 +747,10 @@ offs_t z8000_disassembler::disassemble(std::ostream &stream, offs_t pc, const da /* skip following comma */ if (*src == ',') src++; + flags &= ~STEP_COND; } - else util::stream_format(stream, "%s", cc[n[i]]); + else + util::stream_format(stream, "%s", cc[n[i]]); break; case 'd': /* displacement */ diff --git a/src/emu/debug/debugcmd.cpp b/src/emu/debug/debugcmd.cpp index bb93f050c95..21d143c7f1d 100644 --- a/src/emu/debug/debugcmd.cpp +++ b/src/emu/debug/debugcmd.cpp @@ -234,6 +234,9 @@ debugger_commands::debugger_commands(running_machine& machine, debugger_cpu& cpu m_console.register_command("gtime", CMDFLAG_NONE, 0, 1, std::bind(&debugger_commands::execute_go_time, this, _1)); m_console.register_command("gt", CMDFLAG_NONE, 0, 1, std::bind(&debugger_commands::execute_go_time, this, _1)); m_console.register_command("gp", CMDFLAG_NONE, 0, 1, std::bind(&debugger_commands::execute_go_privilege, this, _1)); + m_console.register_command("gbt", CMDFLAG_NONE, 0, 1, std::bind(&debugger_commands::execute_go_branch, this, true, _1)); + m_console.register_command("gbf", CMDFLAG_NONE, 0, 1, std::bind(&debugger_commands::execute_go_branch, this, false, _1)); + m_console.register_command("gni", CMDFLAG_NONE, 0, 1, std::bind(&debugger_commands::execute_go_next_instruction, this, _1)); m_console.register_command("next", CMDFLAG_NONE, 0, 0, std::bind(&debugger_commands::execute_next, this, _1)); m_console.register_command("n", CMDFLAG_NONE, 0, 0, std::bind(&debugger_commands::execute_next, this, _1)); m_console.register_command("focus", CMDFLAG_NONE, 1, 1, std::bind(&debugger_commands::execute_focus, this, _1)); @@ -1356,6 +1359,56 @@ void debugger_commands::execute_go_privilege(const std::vector<std::string> &par m_console.get_visible_cpu()->debug()->go_privilege((condition.is_empty()) ? "1" : condition.original_string()); } + +/*------------------------------------------------- + execute_go_branch - execute gbt or gbf command +-------------------------------------------------*/ + +void debugger_commands::execute_go_branch(bool sense, const std::vector<std::string> ¶ms) +{ + parsed_expression condition(m_console.visible_symtable()); + if (params.size() > 0 && !debug_command_parameter_expression(params[0], condition)) + return; + + m_console.get_visible_cpu()->debug()->go_branch(sense, (condition.is_empty()) ? "1" : condition.original_string()); +} + + +/*------------------------------------------------- + execute_go_next_instruction - execute gni command +-------------------------------------------------*/ + +void debugger_commands::execute_go_next_instruction(const std::vector<std::string> ¶ms) +{ + u64 count = 1; + + // if we have a parameter, use it instead */ + if (params.size() > 0 && !validate_number_parameter(params[0], count)) + return; + if (count == 0) + return; + + device_state_interface *stateintf; + device_t *cpu = m_machine.debugger().console().get_visible_cpu(); + if (!cpu->interface(stateintf)) + { + m_console.printf("No state interface available for %s\n", cpu->name()); + return; + } + u32 pc = stateintf->pcbase(); + + debug_disasm_buffer buffer(*cpu); + while (count-- != 0) + { + // disassemble the current instruction and get the length + u32 result = buffer.disassemble_info(pc); + pc = buffer.next_pc_wrap(pc, result & util::disasm_interface::LENGTHMASK); + } + + cpu->debug()->go(pc); +} + + /*------------------------------------------------- execute_next - execute the next command -------------------------------------------------*/ diff --git a/src/emu/debug/debugcmd.h b/src/emu/debug/debugcmd.h index b50c07bd634..88ae785e643 100644 --- a/src/emu/debug/debugcmd.h +++ b/src/emu/debug/debugcmd.h @@ -121,6 +121,8 @@ private: void execute_go_exception(const std::vector<std::string> ¶ms); void execute_go_time(const std::vector<std::string> ¶ms); void execute_go_privilege(const std::vector<std::string> ¶ms); + void execute_go_branch(bool sense, const std::vector<std::string> ¶ms); + void execute_go_next_instruction(const std::vector<std::string> ¶ms); void execute_focus(const std::vector<std::string> ¶ms); void execute_ignore(const std::vector<std::string> ¶ms); void execute_observe(const std::vector<std::string> ¶ms); diff --git a/src/emu/debug/debugcpu.cpp b/src/emu/debug/debugcpu.cpp index 978702094b9..820d9e72688 100644 --- a/src/emu/debug/debugcpu.cpp +++ b/src/emu/debug/debugcpu.cpp @@ -427,6 +427,7 @@ device_debug::device_debug(device_t &device) , m_instrhook(nullptr) , m_stepaddr(0) , m_stepsleft(0) + , m_delay_steps(0) , m_stopaddr(0) , m_stoptime(attotime::zero) , m_stopirq(0) @@ -688,11 +689,11 @@ void device_debug::privilege_hook() if ((m_flags & DEBUG_FLAG_STOP_PRIVILEGE) != 0) { bool matched = true; - if (m_privilege_condition && !m_privilege_condition->is_empty()) + if (m_stop_condition && !m_stop_condition->is_empty()) { try { - matched = m_privilege_condition->execute(); + matched = m_stop_condition->execute(); } catch (expression_error &) { @@ -750,19 +751,53 @@ void device_debug::instruction_hook(offs_t curpc) // handle single stepping if (!debugcpu.is_stopped() && (m_flags & DEBUG_FLAG_STEPPING_ANY) != 0) { + bool do_step = true; + if ((m_flags & (DEBUG_FLAG_CALL_IN_PROGRESS | DEBUG_FLAG_TEST_IN_PROGRESS)) != 0) + { + if (curpc == m_stepaddr) + { + if ((~m_flags & (DEBUG_FLAG_TEST_IN_PROGRESS | DEBUG_FLAG_STEPPING_BRANCH_FALSE)) == 0) + { + debugcpu.set_execution_stopped(); + do_step = false; + } + + // reset the breakpoint + m_flags &= ~(DEBUG_FLAG_CALL_IN_PROGRESS | DEBUG_FLAG_TEST_IN_PROGRESS); + m_delay_steps = 0; + } + else if (m_delay_steps != 0) + { + m_delay_steps--; + if (m_delay_steps == 0) + { + // branch taken or subroutine entered (TODO: interrupt acknowledgment or interleaved multithreading can falsely trigger this) + if ((m_flags & DEBUG_FLAG_TEST_IN_PROGRESS) != 0 && (m_flags & (DEBUG_FLAG_STEPPING_OUT | DEBUG_FLAG_STEPPING_BRANCH_TRUE)) != 0) + { + debugcpu.set_execution_stopped(); + do_step = false; + } + if ((m_flags & DEBUG_FLAG_CALL_IN_PROGRESS) != 0) + do_step = false; + m_flags &= ~DEBUG_FLAG_TEST_IN_PROGRESS; + } + } + else + do_step = false; + } + // is this an actual step? - if (m_stepaddr == ~0 || curpc == m_stepaddr) + if (do_step) { - // decrement the count and reset the breakpoint + // decrement the count m_stepsleft--; - m_stepaddr = ~0; // if we hit 0, stop if (m_stepsleft == 0) debugcpu.set_execution_stopped(); // update every 100 steps until we are within 200 of the end - else if ((m_flags & DEBUG_FLAG_STEPPING_OUT) == 0 && (m_stepsleft < 200 || m_stepsleft % 100 == 0)) + else if ((m_flags & (DEBUG_FLAG_STEPPING_OUT | DEBUG_FLAG_STEPPING_BRANCH_TRUE | DEBUG_FLAG_STEPPING_BRANCH_FALSE)) == 0 && (m_stepsleft < 200 || m_stepsleft % 100 == 0)) { machine.debug_view().update_all(); machine.debug_view().flush_osd_updates(); @@ -849,7 +884,7 @@ void device_debug::instruction_hook(offs_t curpc) } // handle step out/over on the instruction we are about to execute - if ((m_flags & (DEBUG_FLAG_STEPPING_OVER | DEBUG_FLAG_STEPPING_OUT)) != 0 && m_stepaddr == ~0) + if ((m_flags & (DEBUG_FLAG_STEPPING_OVER | DEBUG_FLAG_STEPPING_OUT | DEBUG_FLAG_STEPPING_BRANCH)) != 0 && (m_flags & (DEBUG_FLAG_CALL_IN_PROGRESS | DEBUG_FLAG_TEST_IN_PROGRESS)) == 0) prepare_for_step_overout(m_state->pcbase()); // no longer in debugger code @@ -928,7 +963,7 @@ void device_debug::single_step(int numsteps) m_device.machine().rewind_capture(); m_stepsleft = numsteps; - m_stepaddr = ~0; + m_delay_steps = 0; m_flags |= DEBUG_FLAG_STEPPING; m_device.machine().debugger().cpu().set_execution_running(); } @@ -945,7 +980,7 @@ void device_debug::single_step_over(int numsteps) m_device.machine().rewind_capture(); m_stepsleft = numsteps; - m_stepaddr = ~0; + m_delay_steps = 0; m_flags |= DEBUG_FLAG_STEPPING_OVER; m_device.machine().debugger().cpu().set_execution_running(); } @@ -961,8 +996,9 @@ void device_debug::single_step_out() assert(m_exec != nullptr); m_device.machine().rewind_capture(); + m_stop_condition.reset(); m_stepsleft = 100; - m_stepaddr = ~0; + m_delay_steps = 0; m_flags |= DEBUG_FLAG_STEPPING_OUT; m_device.machine().debugger().cpu().set_execution_running(); } @@ -1060,13 +1096,30 @@ void device_debug::go_privilege(const char *condition) { assert(m_exec != nullptr); m_device.machine().rewind_invalidate(); - m_privilege_condition = std::make_unique<parsed_expression>(*m_symtable, condition); + m_stop_condition = std::make_unique<parsed_expression>(*m_symtable, condition); m_flags |= DEBUG_FLAG_STOP_PRIVILEGE; m_device.machine().debugger().cpu().set_execution_running(); } //------------------------------------------------- +// go_branch - execute until branch taken or +// not taken +//------------------------------------------------- + +void device_debug::go_branch(bool sense, const char *condition) +{ + assert(m_exec != nullptr); + m_device.machine().rewind_invalidate(); + m_stop_condition = std::make_unique<parsed_expression>(*m_symtable, condition); + m_stepsleft = 100; + m_delay_steps = 0; + m_flags |= sense ? DEBUG_FLAG_STEPPING_BRANCH_TRUE : DEBUG_FLAG_STEPPING_BRANCH_FALSE; + m_device.machine().debugger().cpu().set_execution_running(); +} + + +//------------------------------------------------- // halt_on_next_instruction_impl - halt in the // debugger on the next instruction, internal // implementation which is necessary solely due @@ -1385,7 +1438,6 @@ void device_debug::set_track_pc(bool value) // track_pc_visited - returns a boolean stating // if this PC has been visited or not. CRC32 is // done in this function on currently active CPU. -// TODO: Take a CPU context as input //------------------------------------------------- bool device_debug::track_pc_visited(offs_t pc) const @@ -1399,7 +1451,6 @@ bool device_debug::track_pc_visited(offs_t pc) const //------------------------------------------------- // set_track_pc_visited - set this pc as visited. -// TODO: Take a CPU context as input //------------------------------------------------- void device_debug::set_track_pc_visited(offs_t pc) @@ -1625,12 +1676,32 @@ void device_debug::prepare_for_step_overout(offs_t pc) // disassemble the current instruction and get the flags u32 dasmresult = buffer.disassemble_info(pc); + if ((dasmresult & util::disasm_interface::SUPPORTED) == 0) + return; + + bool step_out = (m_flags & DEBUG_FLAG_STEPPING_OUT) != 0 && (dasmresult & util::disasm_interface::STEP_OUT) != 0; + bool test_cond = (dasmresult & util::disasm_interface::STEP_COND) != 0 && ((m_flags & (DEBUG_FLAG_STEPPING_BRANCH_TRUE | DEBUG_FLAG_STEPPING_BRANCH_FALSE)) != 0 || step_out); + if (test_cond && m_stop_condition && !m_stop_condition->is_empty()) + { + try + { + test_cond = m_stop_condition->execute(); + } + catch (expression_error &) + { + test_cond = false; + } + } // if flags are supported and it's a call-style opcode, set a temp breakpoint after that instruction - if ((dasmresult & util::disasm_interface::SUPPORTED) != 0 && (dasmresult & util::disasm_interface::STEP_OVER) != 0) + // (TODO: this completely fails for subroutines that consume inline operands or use alternate returns) + if ((dasmresult & util::disasm_interface::STEP_OVER) != 0 || test_cond) { int extraskip = (dasmresult & util::disasm_interface::OVERINSTMASK) >> util::disasm_interface::OVERINSTSHIFT; pc = buffer.next_pc_wrap(pc, dasmresult & util::disasm_interface::LENGTHMASK); + m_delay_steps = extraskip + 1; + if (m_stepsleft < m_delay_steps) + m_stepsleft = m_delay_steps; // if we need to skip additional instructions, advance as requested while (extraskip-- > 0) { @@ -1638,13 +1709,17 @@ void device_debug::prepare_for_step_overout(offs_t pc) pc = buffer.next_pc_wrap(pc, result & util::disasm_interface::LENGTHMASK); } m_stepaddr = pc; + if ((dasmresult & util::disasm_interface::STEP_OVER) != 0) + m_flags |= DEBUG_FLAG_CALL_IN_PROGRESS; + if (test_cond) + m_flags |= DEBUG_FLAG_TEST_IN_PROGRESS; } // if we're stepping out and this isn't a step out instruction, reset the steps until stop to a high number - // (TODO: this doesn't work with conditional return instructions) - if ((m_flags & DEBUG_FLAG_STEPPING_OUT) != 0) + if ((m_flags & (DEBUG_FLAG_STEPPING_OUT | DEBUG_FLAG_STEPPING_BRANCH_TRUE | DEBUG_FLAG_STEPPING_BRANCH_FALSE)) != 0) { - if ((dasmresult & util::disasm_interface::SUPPORTED) != 0 && (dasmresult & util::disasm_interface::STEP_OUT) == 0) + // make sure to also reset the number of steps for conditionals that may be single-instruction loops + if (test_cond || !step_out) m_stepsleft = 100; else { diff --git a/src/emu/debug/debugcpu.h b/src/emu/debug/debugcpu.h index a7d266df1e8..d9fc3f64eae 100644 --- a/src/emu/debug/debugcpu.h +++ b/src/emu/debug/debugcpu.h @@ -82,6 +82,7 @@ public: void go_exception(int exception, const char *condition); void go_milliseconds(u64 milliseconds); void go_privilege(const char *condition); + void go_branch(bool sense, const char *condition); void go_next_device(); template <typename Format, typename... Params> @@ -184,15 +185,16 @@ private: debug_instruction_hook_func m_instrhook; // per-instruction callback hook // stepping information - offs_t m_stepaddr; // step target address for DEBUG_FLAG_STEPPING_OVER + offs_t m_stepaddr; // step target address for DEBUG_FLAG_STEPPING_OVER or DEBUG_FLAG_STEPPING_BRANCH int m_stepsleft; // number of steps left until done + int m_delay_steps; // number of steps until target address check // execution information offs_t m_stopaddr; // stop address for DEBUG_FLAG_STOP_PC attotime m_stoptime; // stop time for DEBUG_FLAG_STOP_TIME int m_stopirq; // stop IRQ number for DEBUG_FLAG_STOP_INTERRUPT int m_stopexception; // stop exception number for DEBUG_FLAG_STOP_EXCEPTION - std::unique_ptr<parsed_expression> m_privilege_condition; // expression to evaluate on privilege change + std::unique_ptr<parsed_expression> m_stop_condition; // expression to evaluate on privilege change std::unique_ptr<parsed_expression> m_exception_condition; // expression to evaluate on exception hit attotime m_endexectime; // ending time of the current execution u64 m_total_cycles; // current total cycles @@ -322,12 +324,17 @@ private: static constexpr u32 DEBUG_FLAG_SUSPENDED = 0x00004000; // CPU currently suspended static constexpr u32 DEBUG_FLAG_LIVE_BP = 0x00010000; // there are live breakpoints for this CPU static constexpr u32 DEBUG_FLAG_STOP_PRIVILEGE = 0x00020000; // run until execution level changes + static constexpr u32 DEBUG_FLAG_STEPPING_BRANCH_TRUE = 0x0040000; // run until true branch + static constexpr u32 DEBUG_FLAG_STEPPING_BRANCH_FALSE = 0x0080000; // run until false branch + static constexpr u32 DEBUG_FLAG_CALL_IN_PROGRESS = 0x01000000; // CPU is in the middle of a subroutine call + static constexpr u32 DEBUG_FLAG_TEST_IN_PROGRESS = 0x02000000; // CPU is performing a conditional test and branch - static constexpr u32 DEBUG_FLAG_STEPPING_ANY = DEBUG_FLAG_STEPPING | DEBUG_FLAG_STEPPING_OVER | DEBUG_FLAG_STEPPING_OUT; + static constexpr u32 DEBUG_FLAG_STEPPING_BRANCH = DEBUG_FLAG_STEPPING_BRANCH_TRUE | DEBUG_FLAG_STEPPING_BRANCH_FALSE; + static constexpr u32 DEBUG_FLAG_STEPPING_ANY = DEBUG_FLAG_STEPPING | DEBUG_FLAG_STEPPING_OVER | DEBUG_FLAG_STEPPING_OUT | DEBUG_FLAG_STEPPING_BRANCH; static constexpr u32 DEBUG_FLAG_TRACING_ANY = DEBUG_FLAG_TRACING | DEBUG_FLAG_TRACING_OVER; static constexpr u32 DEBUG_FLAG_TRANSIENT = DEBUG_FLAG_STEPPING_ANY | DEBUG_FLAG_STOP_PC | DEBUG_FLAG_STOP_INTERRUPT | DEBUG_FLAG_STOP_EXCEPTION | DEBUG_FLAG_STOP_VBLANK | - DEBUG_FLAG_STOP_TIME | DEBUG_FLAG_STOP_PRIVILEGE; + DEBUG_FLAG_STOP_TIME | DEBUG_FLAG_STOP_PRIVILEGE | DEBUG_FLAG_CALL_IN_PROGRESS | DEBUG_FLAG_TEST_IN_PROGRESS; }; //************************************************************************** diff --git a/src/emu/debug/debughlp.cpp b/src/emu/debug/debughlp.cpp index 87bf8f0f18f..869167e96e8 100644 --- a/src/emu/debug/debughlp.cpp +++ b/src/emu/debug/debughlp.cpp @@ -132,6 +132,9 @@ const help_item f_static_help_list[] = " o[ver] [<count>=1] -- single steps over <count> instructions (F10)\n" " out -- single steps until the current subroutine/exception handler is exited (Shift-F11)\n" " g[o] [<address>] -- resumes execution, sets temp breakpoint at <address> (F5)\n" + " gbf [<condition>] -- resumes execution until next false branch\n" + " gbt [<condition>] -- resumes execution until next true branch\n" + " gn[i] [<count>] -- resumes execution, sets temp breakpoint <count> instructions ahead\n" " ge[x] [<exception>[,<condition>]] -- resumes execution, setting temp breakpoint if <exception> is raised\n" " gi[nt] [<irqline>] -- resumes execution, setting temp breakpoint if <irqline> is taken (F7)\n" " gt[ime] <milliseconds> -- resumes execution until the given delay has elapsed\n" @@ -920,6 +923,65 @@ const help_item f_static_help_list[] = " Resume execution, stopping at address 1234 unless something else stops us first.\n" }, { + "gbf", + "\n" + " gbf [<condition>]\n" + "\n" + "The gbf command resumes execution of the current code. Control will not be returned to the " + "debugger until a conditional branch or skip instruction tests false and falls through to the " + "next instruction, or the instruction that follows its delay slot. The optional conditional " + "expression, if provided, will be evaluated at (not after) each conditional branch; execution " + "will not halt regardless of consequent program flow unless its result is true (non-zero).\n" + "\n" + "Examples:\n" + "\n" + "gbf\n" + " Resume execution until the next break/watchpoint or until the next false branch.\n" + "\n" + "gbf {pc != 1234}\n" + " Resume execution until the next false branch, disregarding the instruction at address 1234.\n" + }, + { + "gbt", + "\n" + " gbt [<condition>]\n" + "\n" + "The gbt command resumes execution of the current code. Control will not be returned to the " + "debugger until a conditional branch or skip instruction tests true and program flow transfers " + "to any instruction other than the next one following the delay slot (if any). The optional " + "conditional expression, if provided, will be evaluated at (not after) each conditional " + "branch; execution will not halt regardless of consequent program flow unless its result is " + "true (non-zero).\n" + "\n" + "Examples:\n" + "\n" + "gbt\n" + " Resume execution until the next break/watchpoint or until the next true branch.\n" + "\n" + "gbt {pc != 1234}\n" + " Resume execution until the next true branch, disregarding the instruction at address 1234.\n" + }, + { + "gni", + "\n" + " gn[i] [<count>]\n" + "\n" + "The gni command resumes execution of the current code. Control will not be returned to the " + "debugger until a breakpoint or watchpoint is hit, or until you manually break in using the " + "assigned key. Before executing, the gni command sets a temporary unconditional breakpoint " + "<count> instructions sequentially past the current one, which is automatically removed when " + "hit. If <count> is omitted, its default value is 1." + "\n" + "Examples:\n" + "\n" + "gni\n" + " Resume execution, stopping at the address of the next instruction unless something else " + "stops us first.\n" + "\n" + "gni 2\n" + " Resume execution, stopping at two instructions past the current one.\n" + }, + { "gex", "\n" " ge[x] [<exception>,[<condition>]]\n" diff --git a/src/lib/util/disasmintf.h b/src/lib/util/disasmintf.h index c1365d9d185..562ba5de00a 100644 --- a/src/lib/util/disasmintf.h +++ b/src/lib/util/disasmintf.h @@ -39,8 +39,9 @@ public: static constexpr u32 SUPPORTED = 0x80000000; // are disassembly flags supported? static constexpr u32 STEP_OUT = 0x40000000; // this instruction should be the end of a step out sequence static constexpr u32 STEP_OVER = 0x20000000; // this instruction should be stepped over by setting a breakpoint afterwards - static constexpr u32 OVERINSTMASK = 0x18000000; // number of extra instructions to skip when stepping over - static constexpr u32 OVERINSTSHIFT = 27; // bits to shift after masking to get the value + static constexpr u32 STEP_COND = 0x10000000; // this instruction may conditionally result in a program transfer or short skip + static constexpr u32 OVERINSTMASK = 0x0c000000; // number of extra instructions to skip when stepping over + static constexpr u32 OVERINSTSHIFT = 26; // bits to shift after masking to get the value static constexpr u32 LENGTHMASK = 0x0000ffff; // the low 16-bits contain the actual length static inline u32 step_over_extra(u32 x) { |