diff options
Diffstat (limited to 'src')
-rw-r--r-- | src/devices/bus/ss50/mps2.cpp | 40 | ||||
-rw-r--r-- | src/devices/video/md4330b.cpp | 104 | ||||
-rw-r--r-- | src/devices/video/md4330b.h | 91 | ||||
-rw-r--r-- | src/emu/save.h | 20 | ||||
-rw-r--r-- | src/mame/drivers/4enlinea.cpp | 29 | ||||
-rw-r--r-- | src/mame/drivers/fidel_elite.cpp | 1 | ||||
-rw-r--r-- | src/mame/drivers/mindset.cpp | 564 | ||||
-rw-r--r-- | src/mame/drivers/saitek_ssystem3.cpp | 6 | ||||
-rw-r--r-- | src/mame/drivers/swtpc09.cpp | 526 | ||||
-rw-r--r-- | src/mame/includes/swtpc09.h | 117 | ||||
-rw-r--r-- | src/mame/machine/swtpc09.cpp | 530 |
11 files changed, 1479 insertions, 549 deletions
diff --git a/src/devices/bus/ss50/mps2.cpp b/src/devices/bus/ss50/mps2.cpp index 98441500009..68d0807071c 100644 --- a/src/devices/bus/ss50/mps2.cpp +++ b/src/devices/bus/ss50/mps2.cpp @@ -64,35 +64,35 @@ private: static INPUT_PORTS_START( mps2 ) PORT_START("tx_baud_upper") PORT_DIPNAME(0x1f, 0x1d, "Upper TX Baud Rate") - PORT_DIPSETTING(0x1d, "9600") - PORT_DIPSETTING(0x17, "4800") - PORT_DIPSETTING(0x0f, "1200") - PORT_DIPSETTING(0x1b, "300") - PORT_DIPSETTING(0x1e, "110") + PORT_DIPSETTING(0x1d, "9600 / 38400") + PORT_DIPSETTING(0x17, "4800 / 9600") + PORT_DIPSETTING(0x0f, "1200 / 2400") + PORT_DIPSETTING(0x1b, "300 / 600") + PORT_DIPSETTING(0x1e, "110 / 220") PORT_START("rx_baud_upper") PORT_DIPNAME(0x1f, 0x1d, "Upper RX Baud Rate") - PORT_DIPSETTING(0x1d, "9600") - PORT_DIPSETTING(0x17, "4800") - PORT_DIPSETTING(0x0f, "1200") - PORT_DIPSETTING(0x1b, "300") - PORT_DIPSETTING(0x1e, "110") + PORT_DIPSETTING(0x1d, "9600 / 38400") + PORT_DIPSETTING(0x17, "4800 / 9600") + PORT_DIPSETTING(0x0f, "1200 / 2400") + PORT_DIPSETTING(0x1b, "300 / 600") + PORT_DIPSETTING(0x1e, "110 / 220") PORT_START("tx_baud_lower") PORT_DIPNAME(0x1f, 0x1d, "Lower TX Baud Rate") - PORT_DIPSETTING(0x1d, "9600") - PORT_DIPSETTING(0x17, "4800") - PORT_DIPSETTING(0x0f, "1200") - PORT_DIPSETTING(0x1b, "300") - PORT_DIPSETTING(0x1e, "110") + PORT_DIPSETTING(0x1d, "9600 / 38400") + PORT_DIPSETTING(0x17, "4800 / 9600") + PORT_DIPSETTING(0x0f, "1200 / 2400") + PORT_DIPSETTING(0x1b, "300 / 600") + PORT_DIPSETTING(0x1e, "110 / 220") PORT_START("rx_baud_lower") PORT_DIPNAME(0x1f, 0x1d, "Lower RX Baud Rate") - PORT_DIPSETTING(0x1d, "9600") - PORT_DIPSETTING(0x17, "4800") - PORT_DIPSETTING(0x0f, "1200") - PORT_DIPSETTING(0x1b, "300") - PORT_DIPSETTING(0x1e, "110") + PORT_DIPSETTING(0x1d, "9600 / 38400") + PORT_DIPSETTING(0x17, "4800 / 9600") + PORT_DIPSETTING(0x0f, "1200 / 2400") + PORT_DIPSETTING(0x1b, "300 / 600") + PORT_DIPSETTING(0x1e, "110 / 220") INPUT_PORTS_END diff --git a/src/devices/video/md4330b.cpp b/src/devices/video/md4330b.cpp new file mode 100644 index 00000000000..de3b2e49c4a --- /dev/null +++ b/src/devices/video/md4330b.cpp @@ -0,0 +1,104 @@ +// license:BSD-3-Clause +// copyright-holders:hap +/* + +Mitel MD4330B / MD4332B LCD Driver + +It's a simple shift register CMOS LCD driver. +'30 has 30 segments, '32 has 32. The "C" versions are ceramic chips, the "E" are epoxy. + +TODO: +- RST pin (asynchronous on MD4332B) + +*/ + +#include "emu.h" +#include "video/md4330b.h" + + +DEFINE_DEVICE_TYPE(MD4330B, md4330b_device, "md4330b", "Mitel MD4330B LCD Driver") +DEFINE_DEVICE_TYPE(MD4332B, md4332b_device, "md4332b", "Mitel MD4332B LCD Driver") + +//------------------------------------------------- +// constructor +//------------------------------------------------- + +md4330b_device::md4330b_device(const machine_config &mconfig, device_type type, const char *tag, device_t *owner, u32 clock, u8 qmax) : + device_t(mconfig, type, tag, owner, clock), + m_qmax(qmax), m_write_q(*this), m_write_do(*this) +{ } + +md4330b_device::md4330b_device(const machine_config &mconfig, const char *tag, device_t *owner, u32 clock) : + md4330b_device(mconfig, MD4330B, tag, owner, clock, 30) +{ } + +md4332b_device::md4332b_device(const machine_config &mconfig, const char *tag, device_t *owner, u32 clock) : + md4330b_device(mconfig, MD4332B, tag, owner, clock, 32) +{ } + + + +//------------------------------------------------- +// device_start - device-specific startup +//------------------------------------------------- + +void md4330b_device::device_start() +{ + // resolve callbacks + m_write_q.resolve_safe(); + m_write_do.resolve_safe(); + + // zerofill + m_shift = 0; + m_clk = 0; + m_di = 0; + m_do = 0; + m_rst = 0; + m_tc = 0; + + // register for savestates + save_item(NAME(m_shift)); + save_item(NAME(m_clk)); + save_item(NAME(m_di)); + save_item(NAME(m_do)); + save_item(NAME(m_rst)); + save_item(NAME(m_tc)); +} + + +//------------------------------------------------- +// handlers +//------------------------------------------------- + +void md4330b_device::update_q() +{ + u32 out = m_shift; + if (m_tc) + out = ~out; + out &= (1 << m_qmax) - 1; + + m_write_q(0, out); +} + +WRITE_LINE_MEMBER(md4330b_device::clk_w) +{ + state = (state) ? 1 : 0; + + // shift on rising edge + if (state && !m_clk) + { + // DO pin follows carry out + m_do = (m_rst) ? 0 : BIT(m_shift, m_qmax-1); + + if (m_rst) + m_shift = 0; + else + m_shift = (m_shift << 1) | m_di; + + // output + update_q(); + m_write_do(m_do); + } + + m_clk = state; +} diff --git a/src/devices/video/md4330b.h b/src/devices/video/md4330b.h new file mode 100644 index 00000000000..d372f2b88de --- /dev/null +++ b/src/devices/video/md4330b.h @@ -0,0 +1,91 @@ +// license:BSD-3-Clause +// copyright-holders:hap +/* + + Mitel MD4330B / MD4332B LCD Driver + +*/ + +#ifndef MAME_VIDEO_MD4330B_H +#define MAME_VIDEO_MD4330B_H + +#pragma once + +// pinout reference + +/* + ____ ____ ____ ____ + _T/C 1 |* \_/ | 40 VDD _T/C 1 |* \_/ | 40 VDD + DI 2 | | 39 CLK DI 2 | | 39 CLK + NC 3 | | 38 RST NC 3 | | 38 RST + NC 4 | | 37 DO Q1 4 | | 37 DO + Q1 5 | | 36 Q30 Q2 5 | | 36 Q32 + Q2 6 | | 35 Q29 Q3 6 | | 35 Q31 + Q3 7 | | 34 Q28 Q4 7 | | 34 Q30 + Q4 8 | | 33 Q27 Q5 8 | | 33 Q29 + Q5 9 | | 32 Q26 Q6 9 | | 32 Q28 + Q6 10 | MD4330BC | 31 Q25 Q7 10 | MD4332BC | 31 Q27 + Q7 11 | MD4330BE | 30 Q24 Q8 11 | MD4332BE | 30 Q26 + Q8 12 | | 29 Q23 Q9 12 | | 29 Q25 + Q9 13 | | 28 Q22 Q10 13 | | 28 Q24 + Q10 14 | | 27 Q21 Q11 14 | | 27 Q23 + Q11 15 | | 26 Q20 Q12 15 | | 26 Q22 + Q12 16 | | 25 Q19 Q13 16 | | 25 Q21 + Q13 17 | | 24 Q18 Q14 17 | | 24 Q20 + Q14 18 | | 23 Q17 Q15 18 | | 23 Q19 + Q15 19 | | 22 Q16 Q16 19 | | 22 Q18 + VSS 20 |___________| 21 NC VSS 20 |___________| 21 Q17 + +*/ + + +class md4330b_device : public device_t +{ +public: + md4330b_device(const machine_config &mconfig, const char *tag, device_t *owner, u32 clock = 0); + + // configuration helpers + auto write_q() { return m_write_q.bind(); } + auto write_do() { return m_write_do.bind(); } + + DECLARE_WRITE_LINE_MEMBER(clk_w); + DECLARE_WRITE_LINE_MEMBER(tc_w) { m_tc = (state) ? 1 : 0; update_q(); } + DECLARE_WRITE_LINE_MEMBER(di_w) { m_di = (state) ? 1 : 0; } + DECLARE_WRITE_LINE_MEMBER(rst_w) { m_rst = (state) ? 1 : 0; } + DECLARE_READ_LINE_MEMBER(do_r) { return m_do; } + +protected: + md4330b_device(const machine_config &mconfig, device_type type, const char *tag, device_t *owner, u32 clock, u8 qmax); + + // device-level overrides + virtual void device_start() override; + + void update_q(); + + const u8 m_qmax; // number of Q pins + u32 m_shift; + + // pin state + int m_clk; + int m_di; + int m_do; + int m_rst; + int m_tc; + + // callbacks + devcb_write32 m_write_q; + devcb_write_line m_write_do; +}; + + +class md4332b_device : public md4330b_device +{ +public: + md4332b_device(const machine_config &mconfig, const char *tag, device_t *owner, u32 clock = 0); +}; + + +DECLARE_DEVICE_TYPE(MD4330B, md4330b_device) +DECLARE_DEVICE_TYPE(MD4332B, md4332b_device) + +#endif // MAME_VIDEO_MD4330B_H diff --git a/src/emu/save.h b/src/emu/save.h index 66fba6777a7..2b4798b9d4c 100644 --- a/src/emu/save.h +++ b/src/emu/save.h @@ -267,18 +267,14 @@ public: // template specializations to enumerate the fundamental atomic types you are allowed to save ALLOW_SAVE_TYPE_AND_ARRAY(char) ALLOW_SAVE_TYPE (bool); // std::vector<bool> may be packed internally -#ifdef __sun -ALLOW_SAVE_TYPE_AND_ARRAY(signed char) -#else -ALLOW_SAVE_TYPE_AND_ARRAY(s8) -#endif -ALLOW_SAVE_TYPE_AND_ARRAY(u8) -ALLOW_SAVE_TYPE_AND_ARRAY(s16) -ALLOW_SAVE_TYPE_AND_ARRAY(u16) -ALLOW_SAVE_TYPE_AND_ARRAY(s32) -ALLOW_SAVE_TYPE_AND_ARRAY(u32) -ALLOW_SAVE_TYPE_AND_ARRAY(s64) -ALLOW_SAVE_TYPE_AND_ARRAY(u64) +ALLOW_SAVE_TYPE_AND_ARRAY(osd::s8) +ALLOW_SAVE_TYPE_AND_ARRAY(osd::u8) +ALLOW_SAVE_TYPE_AND_ARRAY(osd::s16) +ALLOW_SAVE_TYPE_AND_ARRAY(osd::u16) +ALLOW_SAVE_TYPE_AND_ARRAY(osd::s32) +ALLOW_SAVE_TYPE_AND_ARRAY(osd::u32) +ALLOW_SAVE_TYPE_AND_ARRAY(osd::s64) +ALLOW_SAVE_TYPE_AND_ARRAY(osd::u64) ALLOW_SAVE_TYPE_AND_ARRAY(PAIR) ALLOW_SAVE_TYPE_AND_ARRAY(PAIR64) ALLOW_SAVE_TYPE_AND_ARRAY(float) diff --git a/src/mame/drivers/4enlinea.cpp b/src/mame/drivers/4enlinea.cpp index 1b1c7cbd677..050d44bf2e7 100644 --- a/src/mame/drivers/4enlinea.cpp +++ b/src/mame/drivers/4enlinea.cpp @@ -684,6 +684,35 @@ ROM_START( 4enlinea ) ROM_LOAD( "cuatro_en_linea_gal16v8as__nosticker.ic04", 0x0000, 0x0117, CRC(094edf29) SHA1(428a2f6568ac1032833ee0c65fa8304967a58607) ) ROM_END +/* Kursaal K7 Olympic Darts PCB + __________________________________________________ SUBBOARD CM3080 + | ________ __ ______ ______________ | ________________ + | _______ | DB9 | |_| |_CN8__| |____CN7______|| |___ __________ | + | |______| |_______| CN9 |__ || ||HEF4020BP|| + | ________ __| ||A | _________ | + | |D41464C| __| || | |________|| + | ________ _____ __| ||__| _________ | + | |D41464C| DA741CN __| | |TC4011BP|| + | ________ _______ ___ __| | __________ | + IC4->|GAL16V8| _______ HCF4069UBE XT5 __| | |__EMPTY__|| + | ________ |UMC | ________ _______________ __| | __________ | +IC11->|GAL16V8| |UM487F| 74HC273AP |WF19054 | __| | |HEF4020BP|| + | |______| ________ |______________| __| |_______________| + | ________ 74HC273AP _______________ __| A=74LS368ANA + | |74LS04N| ___________ |Z84C00BB6 | __| + | _____ | SUBBOARD ||______________| __| + | |XT2_|<-14.31818MHz| CM3080 |____________ __| + | ________ | ||M27C512 ROM| __| + | HCF4069UBE | ||___________| __| + | | |____________ __| + | | ||D4464C-15L | __| + | |__________||___________| __| + | 7808CT ________ ________ _____ _____ | + | |_______| 74LS541B1 X24C16P |BATT| | + | _____ ___________ _____________ |____| | + | |CN1_| |__CN5_____| |__CN4_______| | + |_________________________________________________| +*/ ROM_START( k7_olym ) ROM_REGION( 0x10000, "maincpu", 0 ) ROM_LOAD( "odk7_v3.11_27c512.ic18", 0x00000, 0x10000, CRC(063d24fe) SHA1(ad4509438d2028ede779f5aa9a918d1020c1db41) ) diff --git a/src/mame/drivers/fidel_elite.cpp b/src/mame/drivers/fidel_elite.cpp index 3de497d08ac..5b89505f194 100644 --- a/src/mame/drivers/fidel_elite.cpp +++ b/src/mame/drivers/fidel_elite.cpp @@ -512,6 +512,7 @@ void eag_state::eag2100(machine_config &config) eag(config); /* basic machine hardware */ + m_maincpu->set_clock(6_MHz_XTAL); m_mainmap->set_addrmap(AS_PROGRAM, &eag_state::eag2100_map); } diff --git a/src/mame/drivers/mindset.cpp b/src/mame/drivers/mindset.cpp index 22bb020e444..d8fafdf6f8f 100644 --- a/src/mame/drivers/mindset.cpp +++ b/src/mame/drivers/mindset.cpp @@ -7,12 +7,172 @@ #include "imagedev/floppy.h" #include "machine/upd765.h" #include "formats/pc_dsk.h" +#include "sound/dac.h" +#include "sound/volt_reg.h" #include "screen.h" #include "speaker.h" #include "mindset.lh" + +class mindset_module_interface: public device_t { +public: + virtual void map(address_map &map) = 0; + +protected: + mindset_module_interface(const machine_config &mconfig, device_type type, const char *tag, device_t *owner, uint32_t clock); +}; + +mindset_module_interface::mindset_module_interface(const machine_config &mconfig, device_type type, const char *tag, device_t *owner, uint32_t clock) : + device_t(mconfig, type, tag, owner, clock) +{ +} + +class mindset_module: public device_t, + public device_slot_interface +{ +public: + template <typename T> + mindset_module(const machine_config &mconfig, const char *tag, device_t *owner, T &&opts, const char *dflt, bool fixed = false) + : mindset_module(mconfig, tag, owner, 0) + { + option_reset(); + opts(*this); + set_default_option(dflt); + set_fixed(fixed); + } + mindset_module(const machine_config &mconfig, const char *tag, device_t *owner, uint32_t clock = 0); + virtual ~mindset_module() = default; + + void map(address_space &space, offs_t base); + +protected: + virtual void device_validity_check(validity_checker &valid) const override; + virtual void device_start() override; +}; + +DEFINE_DEVICE_TYPE(MINDSET_MODULE, mindset_module, "mindset_module", "MINDSET module") + +mindset_module::mindset_module(const machine_config &mconfig, const char *tag, device_t *owner, uint32_t clock) : + device_t(mconfig, MINDSET_MODULE, tag, owner, clock), + device_slot_interface(mconfig, *this) +{ +} + +void mindset_module::device_validity_check(validity_checker &valid) const +{ + device_t *const carddev = get_card_device(); + if (carddev && !dynamic_cast<mindset_module_interface *>(carddev)) + osd_printf_error("Card device %s (%s) does not implement mindset_module_interface\n", carddev->tag(), carddev->name()); +} + +void mindset_module::device_start() +{ +} + +void mindset_module::map(address_space &space, offs_t base) +{ + mindset_module_interface *module = dynamic_cast<mindset_module_interface *>(get_card_device()); + if(module) + space.install_device(base, base+0x3f, *module, &mindset_module_interface::map); +} + + +class mindset_sound_module: public mindset_module_interface { +public: + mindset_sound_module(const machine_config &mconfig, const char *tag, device_t *owner, uint32_t clock = 0); + virtual ~mindset_sound_module() = default; + + virtual void map(address_map &map) override; + +protected: + virtual const tiny_rom_entry *device_rom_region() const override; + virtual void device_add_mconfig(machine_config &config) override; + virtual void device_start() override; + virtual void device_reset() override; + +private: + u8 m_p1, m_p2; + + required_device<i8042_device> m_soundcpu; + required_device<dac_byte_interface> m_dac; + + void p1_w(u8 data); + void p2_w(u8 data); + void update_dac(); +}; + +DEFINE_DEVICE_TYPE(MINDSET_SOUND_MODULE, mindset_sound_module, "mindset_sound_module", "MINDSET stereo sound module") + +mindset_sound_module::mindset_sound_module(const machine_config &mconfig, const char *tag, device_t *owner, uint32_t clock) : + mindset_module_interface(mconfig, MINDSET_SOUND_MODULE, tag, owner, clock), + m_soundcpu(*this, "soundcpu"), + m_dac(*this, "dac") +{ +} + +void mindset_sound_module::device_start() +{ + save_item(NAME(m_p1)); + save_item(NAME(m_p2)); +} + +void mindset_sound_module::device_reset() +{ + m_p1 = 0x80; + m_p2 = 0; + m_dac->write(0x80); +} + +void mindset_sound_module::update_dac() +{ + // The p1 dac has the waveform (idle at 0x80), while the p2 one is used for the global volume (mute at 0x00, max at 0xff) + m_dac->write((s8(m_p1-0x80)*m_p2/255 + 0x80) & 0xff); +} + +void mindset_sound_module::p1_w(u8 data) +{ + m_p1 = data; + update_dac(); +} + +void mindset_sound_module::p2_w(u8 data) +{ + m_p2 = data; + update_dac(); +} + +void mindset_sound_module::map(address_map &map) +{ + map(0x00, 0x03).rw(m_soundcpu, FUNC(i8042_device::upi41_master_r), FUNC(i8042_device::upi41_master_w)).umask16(0x00ff); + map(0x00, 0x00).lr8("id", []() -> u8 { return 0x13; }); +} + +ROM_START(mindset_sound_module) + ROM_REGION(0x0800, "soundcpu", 0) + ROM_LOAD("253006-001.u16", 0, 0x800, CRC(7bea5edd) SHA1(30cdc0dedaa5246f4952df452a99ca22e3cd0636)) +ROM_END + +const tiny_rom_entry *mindset_sound_module::device_rom_region() const +{ + return ROM_NAME(mindset_sound_module); +} + +void mindset_sound_module::device_add_mconfig(machine_config &config) +{ + I8042(config, m_soundcpu, 12_MHz_XTAL/2); + m_soundcpu->p1_out_cb().set(FUNC(mindset_sound_module::p1_w)); + m_soundcpu->p2_out_cb().set(FUNC(mindset_sound_module::p2_w)); + + SPEAKER(config, "rspeaker").front_right(); + DAC_8BIT_R2R(config, m_dac, 0).add_route(ALL_OUTPUTS, "rspeaker", 0.5); + voltage_regulator_device &vref(VOLTAGE_REGULATOR(config, "vref")); + vref.add_route(0, m_dac, 1.0, DAC_VREF_POS_INPUT); + vref.add_route(0, m_dac, -1.0, DAC_VREF_NEG_INPUT); +} + + class mindset_state: public driver_device { public: @@ -36,30 +196,32 @@ protected: output_finder<> m_red_led; output_finder<> m_yellow_led; output_finder<> m_green_led; + required_device<dac_byte_interface> m_dac; + required_device_array<mindset_module, 6> m_modules; - memory_access_cache<1, 0, ENDIANNESS_LITTLE> *m_gcos; + memory_access_cache<1, 0, ENDIANNESS_LITTLE> *m_gcps; floppy_image_device *m_floppy[2]; u32 m_palette[16]; bool m_genlock[16]; u16 m_dispctrl, m_screenpos, m_intpos, m_intaddr, m_fdc_dma_count; - u8 m_kbd_p1, m_kbd_p2, m_borderidx; + u8 m_kbd_p1, m_kbd_p2, m_borderidx, m_snd_p1, m_snd_p2; u8 m_mouse_last_read[2], m_mouse_counter[2]; bool m_fdc_intext, m_fdc_int, m_fdc_drq, m_trap_int, m_trap_drq; u16 m_trap_data[8]; u32 m_trap_pos, m_trap_len; - static u16 gco_blend_0(u16, u16); - static u16 gco_blend_1(u16, u16); - static u16 gco_blend_2(u16, u16); - static u16 gco_blend_3(u16, u16); - static u16 gco_blend_4(u16, u16); - static u16 gco_blend_5(u16, u16); - static u16 gco_blend_6(u16, u16); - static u16 gco_blend_7(u16, u16); + static u16 gcp_blend_0(u16, u16); + static u16 gcp_blend_1(u16, u16); + static u16 gcp_blend_2(u16, u16); + static u16 gcp_blend_3(u16, u16); + static u16 gcp_blend_4(u16, u16); + static u16 gcp_blend_5(u16, u16); + static u16 gcp_blend_6(u16, u16); + static u16 gcp_blend_7(u16, u16); - static u16 (*const gco_blend[8])(u16, u16); + static u16 (*const gcp_blend[8])(u16, u16); static inline u16 msk(int bit) { return (1U << bit) - 1; } static inline u16 sw(u16 data) { return (data >> 8) | (data << 8); } @@ -70,7 +232,7 @@ protected: void display_mode(); void blit(u16 packet_seg, u16 packet_adr); - void gco_w(u16); + void gcp_w(u16); u16 dispctrl_r(); void dispctrl_w(u16 data); u16 dispreg_r(); @@ -106,6 +268,7 @@ protected: template<int floppy> void floppy_led_cb(floppy_image_device *, int state); u16 keyscan(); + void update_dac(); u32 screen_update(screen_device &screen, bitmap_rgb32 &bitmap, const rectangle &cliprect); @@ -137,7 +300,9 @@ mindset_state::mindset_state(const machine_config &mconfig, device_type type, co m_floppy_leds(*this, "drive%u_led", 0U), m_red_led(*this, "red_led"), m_yellow_led(*this, "yellow_led"), - m_green_led(*this, "green_led") + m_green_led(*this, "green_led"), + m_dac(*this, "dac"), + m_modules(*this, "m%d", 0U) { } @@ -153,7 +318,7 @@ void mindset_state::machine_start() m_yellow_led.resolve(); m_green_led.resolve(); - m_gcos = m_maincpu->space(AS_PROGRAM).cache<1, 0, ENDIANNESS_LITTLE>(); + m_gcps = m_maincpu->space(AS_PROGRAM).cache<1, 0, ENDIANNESS_LITTLE>(); for(int i=0; i<2; i++) m_floppy[i] = m_fdco[i]->get_device(); @@ -182,10 +347,17 @@ void mindset_state::machine_start() save_item(NAME(m_borderidx)); save_item(NAME(m_mouse_last_read)); save_item(NAME(m_mouse_counter)); + save_item(NAME(m_snd_p1)); + save_item(NAME(m_snd_p2)); } void mindset_state::machine_reset() { + auto &space = m_maincpu->space(AS_IO); + space.unmap_readwrite(0x8080, 0x81ff); + for(int i=0; i<6; i++) + m_modules[i]->map(space, 0x8080 + 0x40*i); + m_fdc_intext = m_fdc_int = m_trap_int = m_fdc_drq = m_trap_drq = false; m_trap_pos = m_trap_len = 0; memset(m_trap_data, 0, sizeof(m_trap_data)); @@ -195,6 +367,9 @@ void mindset_state::machine_reset() m_kbd_p1 = m_kbd_p2 = m_borderidx = 0; memset(m_mouse_last_read, 0, sizeof(m_mouse_last_read)); memset(m_mouse_counter, 0, sizeof(m_mouse_counter)); + m_snd_p1 = 0x80; + m_snd_p2 = 0; + m_dac->write(0x80); } int mindset_state::sys_t0_r() @@ -231,10 +406,10 @@ void mindset_state::sys_p2_w(u8 data) { m_maincpu->int3_w(!(data & 0x80)); m_red_led = !BIT(data, 2); - m_yellow_led = !BIT(data, 1); - m_green_led = !BIT(data, 0); + m_yellow_led = !BIT(data, 0); + m_green_led = !BIT(data, 1); // logerror("power %s\n", data & 0x40 ? - // logerror("SYS: write p2 %02x\n", data); + logerror("SYS: write p2 %02x\n", data); } void mindset_state::kbd_p1_w(u8 data) @@ -259,15 +434,22 @@ int mindset_state::kbd_t1_r() return keyscan() & 0x100; } +void mindset_state::update_dac() +{ + // The p1 dac has the waveform (idle at 0x80), while the p2 one is used for the global volume (mute at 0x00, max at 0xff) + m_dac->write((s8(m_snd_p1-0x80)*m_snd_p2/255 + 0x80) & 0xff); +} + void mindset_state::snd_p1_w(u8 data) { - if(data != 0x80) - logerror("snd p1 %02x\n", data); + m_snd_p1 = data; + update_dac(); } void mindset_state::snd_p2_w(u8 data) { - // logerror("snd p2 %02x\n", data); + m_snd_p2 = data; + update_dac(); } u16 mindset_state::keyscan() @@ -425,7 +607,6 @@ u32 mindset_state::screen_update(screen_device &screen, bitmap_rgb32 &bitmap, co int dx = ((m_screenpos >> 8) & 15) * (751 - 640) / 15; int dy = ((m_screenpos >> 12) & 15) * (480 - 400) / 15; - if(ibm_mode) { if(large_pixels) { static int palind[4] = { 0, 1, 4, 5 }; @@ -470,17 +651,18 @@ u32 mindset_state::screen_update(screen_device &screen, bitmap_rgb32 &bitmap, co if(!interleave) { switch(pixels_per_byte_order) { case 0: { - for(int field=0; field<2; field++) { - const u16 *src = bank; - for(u32 y=0; y<200; y++) { - u32 *dest = &bitmap.pix32(2*y+field+dy, dx); - for(u32 x=0; x<320; x+=4) { - u16 sv = sw(*src++); - for(u32 xx=0; xx<4; xx++) { - u32 color = m_palette[(sv >> (12-4*xx)) & 15]; - *dest++ = color; - *dest++ = color; - } + const u16 *src = bank; + for(u32 y=0; y<200; y++) { + u32 *dest0 = &bitmap.pix32(2*y+dy, dx); + u32 *dest1 = &bitmap.pix32(2*y+1+dy, dx); + for(u32 x=0; x<320; x+=4) { + u16 sv = sw(*src++); + for(u32 xx=0; xx<4; xx++) { + u32 color = m_palette[(sv >> (12-4*xx)) & 15]; + *dest0++ = color; + *dest0++ = color; + *dest1++ = color; + *dest1++ = color; } } } @@ -488,34 +670,70 @@ u32 mindset_state::screen_update(screen_device &screen, bitmap_rgb32 &bitmap, co } case 1: { static int palind[4] = { 0, 1, 4, 5 }; - for(int field=0; field<2; field++) { - const u16 *src = bank; - for(u32 y=0; y<200; y++) { - u32 *dest = &bitmap.pix32(2*y+field+dy, dx); - for(u32 x=0; x<320; x+=8) { - u16 sv = sw(*src++); - for(u32 xx=0; xx<8; xx++) { - u32 color = m_palette[palind[(sv >> (14-2*xx)) & 3]]; - *dest++ = color; - *dest++ = color; - } + const u16 *src = bank; + for(u32 y=0; y<200; y++) { + u32 *dest0 = &bitmap.pix32(2*y+dy, dx); + u32 *dest1 = &bitmap.pix32(2*y+1+dy, dx); + for(u32 x=0; x<320; x+=8) { + u16 sv = sw(*src++); + for(u32 xx=0; xx<8; xx++) { + u32 color = m_palette[palind[(sv >> (14-2*xx)) & 3]]; + *dest0++ = color; + *dest0++ = color; + *dest1++ = color; + *dest1++ = color; } } } return 0; } case 2: { - for(int field=0; field<2; field++) { - const u16 *src = bank; - for(u32 y=0; y<200; y++) { - u32 *dest = &bitmap.pix32(2*y+field+dy, dx); - for(u32 x=0; x<320; x+=16) { - u16 sv = sw(*src++); - for(u32 xx=0; xx<16; xx++) { - u32 color = m_palette[(sv >> (15-xx)) & 1]; - *dest++ = color; - *dest++ = color; - } + const u16 *src = bank; + for(u32 y=0; y<200; y++) { + u32 *dest0 = &bitmap.pix32(2*y+dy, dx); + u32 *dest1 = &bitmap.pix32(2*y+1+dy, dx); + for(u32 x=0; x<320; x+=16) { + u16 sv = sw(*src++); + for(u32 xx=0; xx<16; xx++) { + u32 color = m_palette[(sv >> (15-xx)) & 1]; + *dest0++ = color; + *dest0++ = color; + *dest1++ = color; + *dest1++ = color; + } + } + } + return 0; + } + } + } else { + switch(pixels_per_byte_order) { + case 0: { + const u16 *src = bank; + for(u32 y=0; y<400; y++) { + u32 *dest = &bitmap.pix32(y+dy, dx); + for(u32 x=0; x<320; x+=4) { + u16 sv = sw(*src++); + for(u32 xx=0; xx<4; xx++) { + u32 color = m_palette[(sv >> (12-4*xx)) & 15]; + *dest++ = color; + *dest++ = color; + } + } + } + return 0; + } + case 1: { + static int palind[4] = { 0, 1, 4, 5 }; + const u16 *src = bank; + for(u32 y=0; y<400; y++) { + u32 *dest = &bitmap.pix32(y+dy, dx); + for(u32 x=0; x<320; x+=8) { + u16 sv = sw(*src++); + for(u32 xx=0; xx<8; xx++) { + u32 color = m_palette[palind[(sv >> (14-2*xx)) & 3]]; + *dest++ = color; + *dest++ = color; } } } @@ -528,17 +746,16 @@ u32 mindset_state::screen_update(screen_device &screen, bitmap_rgb32 &bitmap, co switch(pixels_per_byte_order) { case 0: { static int palind[4] = { 0, 4, 8, 12 }; - for(int field=0; field<2; field++) { - m_palette[1] = 0xffffff; - const u16 *src = bank; - for(u32 y=0; y<200; y++) { - u32 *dest = &bitmap.pix32(2*y+field+dy, dx); - for(u32 x=0; x<640; x+=8) { - u16 sv = sw(*src++); - for(u32 xx=0; xx<8; xx++) { - u32 color = m_palette[palind[(sv >> (14-2*xx)) & 3]]; - *dest++ = color; - } + const u16 *src = bank; + for(u32 y=0; y<200; y++) { + u32 *dest0 = &bitmap.pix32(2*y+dy, dx); + u32 *dest1 = &bitmap.pix32(2*y+1+dy, dx); + for(u32 x=0; x<640; x+=8) { + u16 sv = sw(*src++); + for(u32 xx=0; xx<8; xx++) { + u32 color = m_palette[palind[(sv >> (14-2*xx)) & 3]]; + *dest0++ = color; + *dest1++ = color; } } } @@ -546,22 +763,36 @@ u32 mindset_state::screen_update(screen_device &screen, bitmap_rgb32 &bitmap, co } case 1: { static int palind[4] = { 0, 4 }; - for(int field=0; field<2; field++) { - const u16 *src = bank; - for(u32 y=0; y<200; y++) { - u32 *dest = &bitmap.pix32(2*y+field+dy, dx); - for(u32 x=0; x<640; x+=16) { - u16 sv = sw(*src++); - for(u32 xx=0; xx<16; xx++) { - u32 color = m_palette[palind[(sv >> (15-xx)) & 1]]; - *dest++ = color; - } + const u16 *src = bank; + for(u32 y=0; y<200; y++) { + u32 *dest0 = &bitmap.pix32(2*y+dy, dx); + u32 *dest1 = &bitmap.pix32(2*y+1+dy, dx); + for(u32 x=0; x<640; x+=16) { + u16 sv = sw(*src++); + for(u32 xx=0; xx<16; xx++) { + u32 color = m_palette[palind[(sv >> (15-xx)) & 1]]; + *dest0++ = color; + *dest1++ = color; } } } return 0; } } + } else { + static int palind[4] = { 0, 4 }; + const u16 *src = bank; + for(u32 y=0; y<400; y++) { + u32 *dest = &bitmap.pix32(y+dy, dx); + for(u32 x=0; x<640; x+=16) { + u16 sv = sw(*src++); + for(u32 xx=0; xx<16; xx++) { + u32 color = m_palette[palind[(sv >> (15-xx)) & 1]]; + *dest++ = color; + } + } + } + return 0; } } @@ -573,104 +804,123 @@ u32 mindset_state::screen_update(screen_device &screen, bitmap_rgb32 &bitmap, co return 0; } -u16 mindset_state::gco_blend_0(u16 src, u16) +u16 mindset_state::gcp_blend_0(u16 src, u16) { return src; } -u16 mindset_state::gco_blend_1(u16 src, u16 dst) +u16 mindset_state::gcp_blend_1(u16 src, u16 dst) { return src & dst; } -u16 mindset_state::gco_blend_2(u16 src, u16 dst) +u16 mindset_state::gcp_blend_2(u16 src, u16 dst) { return src | dst; } -u16 mindset_state::gco_blend_3(u16 src, u16 dst) +u16 mindset_state::gcp_blend_3(u16 src, u16 dst) { return src ^ dst; } -u16 mindset_state::gco_blend_4(u16 src, u16) +u16 mindset_state::gcp_blend_4(u16 src, u16) { return ~src; } -u16 mindset_state::gco_blend_5(u16 src, u16 dst) +u16 mindset_state::gcp_blend_5(u16 src, u16 dst) { return (~src) & dst; } -u16 mindset_state::gco_blend_6(u16 src, u16 dst) +u16 mindset_state::gcp_blend_6(u16 src, u16 dst) { return (~src) | dst; } -u16 mindset_state::gco_blend_7(u16 src, u16 dst) +u16 mindset_state::gcp_blend_7(u16 src, u16 dst) { return (~src) ^ dst; } -u16 (*const mindset_state::gco_blend[8])(u16, u16) = { - gco_blend_0, - gco_blend_1, - gco_blend_2, - gco_blend_3, - gco_blend_4, - gco_blend_5, - gco_blend_6, - gco_blend_7 +u16 (*const mindset_state::gcp_blend[8])(u16, u16) = { + gcp_blend_0, + gcp_blend_1, + gcp_blend_2, + gcp_blend_3, + gcp_blend_4, + gcp_blend_5, + gcp_blend_6, + gcp_blend_7 }; void mindset_state::blit(u16 packet_seg, u16 packet_adr) { - u16 mode = sw(m_gcos->read_word((packet_seg << 4) + ((packet_adr + 0) & 0xffff))); - u16 src_adr = sw(m_gcos->read_word((packet_seg << 4) + ((packet_adr + 2) & 0xffff))); - u16 src_sft = sw(m_gcos->read_word((packet_seg << 4) + ((packet_adr + 4) & 0xffff))); - u16 dst_adr = sw(m_gcos->read_word((packet_seg << 4) + ((packet_adr + 6) & 0xffff))); - u16 dst_sft = sw(m_gcos->read_word((packet_seg << 4) + ((packet_adr + 8) & 0xffff))); - u16 width = sw(m_gcos->read_word((packet_seg << 4) + ((packet_adr + 10) & 0xffff))); - u16 height = sw(m_gcos->read_word((packet_seg << 4) + ((packet_adr + 12) & 0xffff))); - u16 sy = sw(m_gcos->read_word((packet_seg << 4) + ((packet_adr + 14) & 0xffff))); - u16 dy = sw(m_gcos->read_word((packet_seg << 4) + ((packet_adr + 16) & 0xffff))); - u16 rmask = sw(m_gcos->read_word((packet_seg << 4) + ((packet_adr + 18) & 0xffff))); - u16 src_seg = sw(m_gcos->read_word((packet_seg << 4) + ((packet_adr + 20) & 0xffff))); - u16 dst_seg = sw(m_gcos->read_word((packet_seg << 4) + ((packet_adr + 22) & 0xffff))); - u16 wmask = sw(m_gcos->read_word((packet_seg << 4) + ((packet_adr + 24) & 0xffff))); - u16 kmask = sw(m_gcos->read_word((packet_seg << 4) + ((packet_adr + 26) & 0xffff))); + u16 mode = sw(m_gcps->read_word((packet_seg << 4) + ((packet_adr + 0) & 0xffff))); + u16 src_adr = sw(m_gcps->read_word((packet_seg << 4) + ((packet_adr + 2) & 0xffff))); + u16 src_sft = sw(m_gcps->read_word((packet_seg << 4) + ((packet_adr + 4) & 0xffff))); + u16 dst_adr = sw(m_gcps->read_word((packet_seg << 4) + ((packet_adr + 6) & 0xffff))); + u16 dst_sft = sw(m_gcps->read_word((packet_seg << 4) + ((packet_adr + 8) & 0xffff))); + u16 width = sw(m_gcps->read_word((packet_seg << 4) + ((packet_adr + 10) & 0xffff))); + u16 height = sw(m_gcps->read_word((packet_seg << 4) + ((packet_adr + 12) & 0xffff))); + u16 sy = sw(m_gcps->read_word((packet_seg << 4) + ((packet_adr + 14) & 0xffff))); + u16 dy = sw(m_gcps->read_word((packet_seg << 4) + ((packet_adr + 16) & 0xffff))); + u16 rmask = sw(m_gcps->read_word((packet_seg << 4) + ((packet_adr + 18) & 0xffff))); + u16 src_seg = sw(m_gcps->read_word((packet_seg << 4) + ((packet_adr + 20) & 0xffff))); + u16 dst_seg = sw(m_gcps->read_word((packet_seg << 4) + ((packet_adr + 22) & 0xffff))); + u16 wmask = sw(m_gcps->read_word((packet_seg << 4) + ((packet_adr + 24) & 0xffff))); + u16 kmask = sw(m_gcps->read_word((packet_seg << 4) + ((packet_adr + 26) & 0xffff))); + + // -f-w wnpi ktxm mm-- + // f = fast (pure word copy) + // w = pixel width (1/2/4/8 bits) + // n = invert collision flag (unimplemented) + // p = pattern fill (used by fill_dest_buffer) + // i/f = increment source / don't (used by blt_copy_word) + // t/o = transparent/opaque + // k = detect collision (unimplemented) + // x = go right to left (unimplemented) + // m = blending mode + if(1) - logerror("GCO: p src %04x:%04x.%x dst %04x:%04x.%x sz %xx%x step %x:%x mask %04x:%04x k %x:%x mode %c%c%c%d%c%d%c%c%c\n", src_seg, src_adr, src_sft, dst_seg, dst_adr, dst_sft, width, height, sy, dy, rmask, wmask, (kmask >> 8) & 15, kmask & 15, - mode & 0x80 ? 'k' : '-', - mode & 0x40 ? 't' : 'o', - mode & 0x20 ? 'x' : '-', - (mode >> 2) & 7, + logerror("GCP: p src %04x:%04x.%x dst %04x:%04x.%x sz %xx%x step %x:%x mask %04x:%04x k %x:%x mode %c%d%c%c%c%c%c%c%d\n", src_seg, src_adr, src_sft, dst_seg, dst_adr, dst_sft, width, height, sy, dy, rmask, wmask, (kmask >> 8) & 15, kmask & 15, mode & 0x4000 ? 'f' : '-', (mode >> 11) & 3, mode & 0x400 ? 'n' : '-', mode & 0x200 ? 'p' : '-', - mode & 0x100 ? 'i' : 'f'); - - // k = detect collision (unimplemented) - // t/o = transparent/opaque - // x = go right to left (unimplemented) - // f = fast (no idea what it means) - // n = invert collision flag (unimplemented) - // p = pattern fill (used by fill_dest_buffer) - // i/f = increment source / don't (used by blt_copy_word) + mode & 0x100 ? 'i' : 'f', + mode & 0x80 ? 'k' : '-', + mode & 0x40 ? 't' : 'o', + mode & 0x20 ? 'x' : '-', + (mode >> 2) & 7); if(mode & 0x200) { // pattern fill - u16 src = m_gcos->read_word((src_seg << 4) + src_adr); + u16 src = m_gcps->read_word((src_seg << 4) + src_adr); for(u16 w=0; w != width/2; w++) { - m_gcos->write_word((dst_seg << 4) + dst_adr, src); + m_gcps->write_word((dst_seg << 4) + dst_adr, src); dst_adr += 2; } + } else if(mode & 0x4000) { + // fast mode + u32 nw = (width+15) >> 4; + for(u32 y=0; y<height; y++) { + u16 src_cadr = src_adr; + u16 dst_cadr = dst_adr; + for(u32 w=0; w!=nw; w++) { + m_gcps->write_word((dst_seg << 4) + dst_cadr, m_gcps->read_word((src_seg << 4) + src_cadr)); + src_cadr += 2; + dst_cadr += 2; + } + src_adr += sy; + dst_adr += dy; + } + } else { - auto blend = gco_blend[(mode >> 2) & 7]; + auto blend = gcp_blend[(mode >> 2) & 7]; // Need to rotate rmask depending on the shifts too u16 awmask = ((wmask << 16) | wmask) >> (15 - dst_sft); @@ -703,43 +953,43 @@ void mindset_state::blit(u16 packet_seg, u16 packet_adr) u16 nw1 = nw; u32 srcs = 0; if(preload) { - srcs = sw(m_gcos->read_word((src_seg << 4) + src_cadr)) << src_do_sft; + srcs = sw(m_gcps->read_word((src_seg << 4) + src_cadr)) << src_do_sft; if(mode & 0x100) src_cadr += 2; } do { - srcs = (srcs << 16) | (sw(m_gcos->read_word((src_seg << 4) + src_cadr)) << src_do_sft); + srcs = (srcs << 16) | (sw(m_gcps->read_word((src_seg << 4) + src_cadr)) << src_do_sft); u16 src = (srcs >> dst_do_sft) & rmask; - u16 dst = sw(m_gcos->read_word((dst_seg << 4) + dst_cadr)); + u16 dst = sw(m_gcps->read_word((dst_seg << 4) + dst_cadr)); u16 res = blend(src, dst); if(mode & 0x40) { u16 tmask; - switch((mode >> 10) & 3) { + switch((mode >> 11) & 3) { case 0: - tmask = dst; + tmask = src; break; case 1: - tmask = ((dst & 0xaaaa) >> 1) | (dst & 0x5555); - tmask = tmask * 0x3; + tmask = (src >> 1) | src; + tmask = (tmask & 0x5555) * 0x3; break; case 2: - tmask = ((dst & 0xcccc) >> 2) | (dst & 0x3333); - tmask = ((dst & 0x2222) >> 1) | (dst & 0x1111); - tmask = tmask * 0xf; + tmask = (src >> 2) | src; + tmask = (tmask >> 1) | tmask; + tmask = (tmask & 0x1111) * 0xf; break; case 3: - tmask = ((dst & 0xf0f0) >> 4) | (dst & 0x0f0f); - tmask = ((dst & 0x0c0c) >> 2) | (dst & 0x0303); - tmask = ((dst & 0x0202) >> 1) | (dst & 0x0101); - tmask = tmask * 0xff; + tmask = (src >> 4) | src; + tmask = (tmask >> 2) | tmask; + tmask = (tmask >> 1) | tmask; + tmask = (tmask & 0x0101) * 0xff; break; } - cmask &= ~tmask; + cmask &= tmask; } res = (dst & ~cmask) | (res & cmask); - m_gcos->write_word((dst_seg << 4) + dst_cadr, sw(res)); + m_gcps->write_word((dst_seg << 4) + dst_cadr, sw(res)); if(mode & 0x100) src_cadr += 2; dst_cadr += 2; @@ -756,14 +1006,14 @@ void mindset_state::blit(u16 packet_seg, u16 packet_adr) } } -void mindset_state::gco_w(u16) +void mindset_state::gcp_w(u16) { - u16 packet_seg = sw(m_gcos->read_word(0xbfd7a)); - u16 packet_adr = sw(m_gcos->read_word(0xbfd78)); - u16 global_mode = sw(m_gcos->read_word(0xbfd76)); + u16 packet_seg = sw(m_gcps->read_word(0xbfd7a)); + u16 packet_adr = sw(m_gcps->read_word(0xbfd78)); + u16 global_mode = sw(m_gcps->read_word(0xbfd76)); if(0) - logerror("GCO: start %04x:%04x mode %04x (%05x)\n", packet_seg, packet_adr, global_mode, m_maincpu->pc()); + logerror("GCP: start %04x:%04x mode %04x (%05x)\n", packet_seg, packet_adr, global_mode, m_maincpu->pc()); switch(global_mode) { case 0x0005: @@ -773,7 +1023,7 @@ void mindset_state::gco_w(u16) } // 100 = done, 200 = done too???, 400 = collision? - m_gcos->write_word(0xbfd74, m_gcos->read_word(0xbfd74) | 0x0700); + m_gcps->write_word(0xbfd74, m_gcps->read_word(0xbfd74) | 0x0700); // Can trigger an irq, on mode & 2 (or is it 200?) (0x40 on 8282, ack on 0x41, which means the system 8042...) } @@ -891,15 +1141,17 @@ void mindset_state::maincpu_io(address_map &map) map(0x8060, 0x8060).r(m_fdc, FUNC(i8272a_device::msr_r)); map(0x8062, 0x8062).rw(m_fdc, FUNC(i8272a_device::fifo_r), FUNC(i8272a_device::fifo_w)); +#if 0 map(0x8080, 0x8080).lr8("id13", []() -> u8 { return 0x13; }); // sound map(0x80c0, 0x80c0).lr8("id3f", []() -> u8 { return 0x3f; }); // serial type 1, maybe? map(0x8100, 0x8100).lr8("id5f", []() -> u8 { return 0x5f; }); // serial type 2 map(0x8140, 0x8140).lr8("id70", []() -> u8 { return 0x70; }); // parallel printer, init writes 0x82 at +6 map(0x8180, 0x8180).lr8("rs232-id", []() -> u8 { return 0x73; }); // rs232 +#endif map(0x8280, 0x8283).rw(m_syscpu, FUNC(i8042_device::upi41_master_r), FUNC(i8042_device::upi41_master_w)).umask16(0x00ff); map(0x82a0, 0x82a3).rw(m_soundcpu, FUNC(i8042_device::upi41_master_r), FUNC(i8042_device::upi41_master_w)).umask16(0x00ff); - map(0x8300, 0x8301).w(FUNC(mindset_state::gco_w)); + map(0x8300, 0x8301).w(FUNC(mindset_state::gcp_w)); map(0x8320, 0x8321).rw(FUNC(mindset_state::dispreg_r), FUNC(mindset_state::dispreg_w)); map(0x8322, 0x8323).rw(FUNC(mindset_state::dispctrl_r), FUNC(mindset_state::dispctrl_w)); } @@ -909,6 +1161,11 @@ static void pc_dd_floppies(device_slot_interface &device) device.option_add("525dd", FLOPPY_525_DD); } +static void mindset_modules(device_slot_interface &device) +{ + device.option_add("stereo", MINDSET_SOUND_MODULE); +} + void mindset_state::mindset(machine_config &config) { config.m_perfect_cpu_quantum = ":syscpu"; @@ -955,6 +1212,19 @@ void mindset_state::mindset(machine_config &config) m_fdc->set_ready_line_connected(false); FLOPPY_CONNECTOR(config, m_fdco[0], pc_dd_floppies, "525dd", mindset_state::floppy_formats); FLOPPY_CONNECTOR(config, m_fdco[1], pc_dd_floppies, "525dd", mindset_state::floppy_formats); + + SPEAKER(config, "lspeaker").front_left(); + DAC_8BIT_R2R(config, m_dac, 0).add_route(ALL_OUTPUTS, "lspeaker", 0.5); + voltage_regulator_device &vref(VOLTAGE_REGULATOR(config, "vref")); + vref.add_route(0, m_dac, 1.0, DAC_VREF_POS_INPUT); + vref.add_route(0, m_dac, -1.0, DAC_VREF_NEG_INPUT); + + MINDSET_MODULE(config, "m0", mindset_modules, "stereo", false); + MINDSET_MODULE(config, "m1", mindset_modules, nullptr, false); + MINDSET_MODULE(config, "m2", mindset_modules, nullptr, false); + MINDSET_MODULE(config, "m3", mindset_modules, nullptr, false); + MINDSET_MODULE(config, "m4", mindset_modules, nullptr, false); + MINDSET_MODULE(config, "m5", mindset_modules, nullptr, false); } static INPUT_PORTS_START(mindset) @@ -1115,5 +1385,5 @@ ROM_START(mindset) ROM_LOAD("kbd_v3.0.bin", 0, 0x800, CRC(1c6aa433) SHA1(1d01dbda4730f26125ba2564a608c2f8ddfc05b3)) ROM_END -COMP( 1984, mindset, 0, 0, mindset, mindset, mindset_state, empty_init, "Mindset Corporation", "Mindset Video Production System", MACHINE_NOT_WORKING|MACHINE_NO_SOUND) +COMP( 1984, mindset, 0, 0, mindset, mindset, mindset_state, empty_init, "Mindset Corporation", "Mindset Video Production System", MACHINE_NOT_WORKING) diff --git a/src/mame/drivers/saitek_ssystem3.cpp b/src/mame/drivers/saitek_ssystem3.cpp index 3f17aed354d..406cee8981a 100644 --- a/src/mame/drivers/saitek_ssystem3.cpp +++ b/src/mame/drivers/saitek_ssystem3.cpp @@ -15,6 +15,7 @@ TODO: #include "machine/timer.h" #include "sound/dac.h" #include "sound/volt_reg.h" +#include "video/md4330b.h" #include "video/pwm.h" #include "screen.h" @@ -32,6 +33,7 @@ public: ssystem3_state(const machine_config &mconfig, device_type type, const char *tag) : driver_device(mconfig, type, tag), m_maincpu(*this, "maincpu"), + m_lcd(*this, "lcd"), m_display(*this, "display"), m_dac(*this, "dac"), m_inputs(*this, "IN.%u", 0) @@ -46,8 +48,9 @@ protected: private: // devices/pointers required_device<cpu_device> m_maincpu; + required_device<md4332b_device> m_lcd; required_device<pwm_display_device> m_display; - optional_device<dac_bit_interface> m_dac; + required_device<dac_bit_interface> m_dac; required_ioport_array<4> m_inputs; // address maps @@ -129,6 +132,7 @@ void ssystem3_state::ssystem3(machine_config &config) //NVRAM(config, "nvram", nvram_device::DEFAULT_ALL_0); /* video hardware */ + MD4332B(config, m_lcd); PWM_DISPLAY(config, m_display).set_size(4, 4); //config.set_default_layout(layout_saitek_ssystem3); diff --git a/src/mame/drivers/swtpc09.cpp b/src/mame/drivers/swtpc09.cpp index 5e7f3fd0c72..9760351c7f4 100644 --- a/src/mame/drivers/swtpc09.cpp +++ b/src/mame/drivers/swtpc09.cpp @@ -1,5 +1,5 @@ // license:BSD-3-Clause -// copyright-holders:Robert Justice +// copyright-holders:Robert Justice,68bit /************************************************************************** SWTPC S/09 Mess driver @@ -7,25 +7,28 @@ Emulates four different fixed combinations of hardware 1. swtpc09 - MP-09 with SBUG rom, MP-ID, MP-S2, DMF2. + MP-09 with SBUG rom, MP-ID, MP-S2, MP-T, DMAF2. Will boot Flex operating system 2. swtpc09i - MP-09 with SBUG rom + HDrom, MP-ID, MP-S2, DMF2, PIAIDE. + MP-09 with SBUG rom + HDrom, MP-ID, MP-S2, MP-T, DMAF2, PIAIDE. Will boot Flex operating system TODO: finish ide part and get this one working. 3. swtpc09u - MP-09 with UniBUG rom, MP-ID, MP-S2, DMF2. + MP-09 with UniBUG rom, MP-ID, MP-S2, DMAF2. Will boot UniFlex operating system 4. swtpc09d3 - MP-09 with UniBUG U3 rom, MP-ID, MP-S2, DMF3. + MP-09 with UniBUG U3 rom, MP-ID, MP-S2, DMAF3. Will boot UniFlex operating system - TODO: add Harddisk support, DMF3 has WD1000 interface + TODO: add Harddisk support, DMAF3 has WD1000 interface ***************************************************************************/ #include "emu.h" #include "includes/swtpc09.h" +#include "bus/ss50/interface.h" +#include "machine/input_merger.h" #include "formats/flex_dsk.h" +#include "formats/uniflex_dsk.h" /************************************************************************** @@ -36,24 +39,29 @@ E000 - E003 S2 MC6850 ACIA1 (used for UniFlex console) E004 - E007 S2 MC6850 ACIA2 (used for Flex console) + E014 - E015 DC5 Control reg. + E016 - E017 DC5 Control reg. 2 + E018 - E01B DC5 WD2797 FDC + E040 - E043 MPT MC6821 PIA + MK5009 timer/counter E080 - E08F MPID MC6821 PIA E090 - E09F MPID MC6840 PTM - F000 - F01F DMF2 MC6844 DMAC - F020 - F023 DMF2 WD1791 FDC - F024 - F03F DMF2 Drive select register - F040 - F041 DMF2 DMA Address register + F000 - F01F DMAF2 MC6844 DMAC + F020 - F023 DMAF2 WD1791 FDC + F024 - F03F DMAF2 Drive select register + F040 - F041 DMAF2 DMA Address register F800 - FFFF ROM FFF0 - FFFF DAT RAM (only for writes) - for DMF3 version - F000 - F01F DMF3 MC6844 DMAC - F020 - F023 DMF3 WD1791 FDC - F024 - F024 DMF3 Drive select register - F025 - F025 DMF3 DMA Address register - F040 - F04F DMF3 6522 VIA + for DMAF3 version + F000 - F01F DMAF3 MC6844 DMAC + F020 - F023 DMAF3 WD1791 FDC + F024 - F024 DMAF3 Drive select register + F025 - F025 DMAF3 DMA Address register + F030 - F03F DMAF3 WD1000 + F040 - F04F DMAF3 6522 VIA ***************************************************************************/ @@ -62,225 +70,477 @@ void swtpc09_state::mp09_mem(address_map &map) { - map(0x0000, 0xfeff).rw(FUNC(swtpc09_state::main_r), FUNC(swtpc09_state::main_w)); - map(0xff00, 0xffff).rom().region("maincpu", 0xff00); + map(0x0000, 0xffff).rw(FUNC(swtpc09_state::main_r), FUNC(swtpc09_state::main_w)); map(0xff00, 0xff0f).mirror(0xf0).writeonly().share("dat"); } -void swtpc09_state::flex_dmf2_mem(address_map &map) +void swtpc09_state::flex_dmaf2_mem(address_map &map) { map(0x00000, 0xfffff).ram(); // by default everything is ram, 1MB ram emulated - map(0xe000, 0xe003).mirror(0xf0000).noprw(); - map(0xe004, 0xe005).mirror(0xf0000).rw(m_acia, FUNC(acia6850_device::read), FUNC(acia6850_device::write)); - map(0xe080, 0xe083).mirror(0xf000c).rw(m_pia, FUNC(pia6821_device::read), FUNC(pia6821_device::write)); - map(0xe090, 0xe097).mirror(0xf0008).rw(m_ptm, FUNC(ptm6840_device::read), FUNC(ptm6840_device::write)); - map(0xe0a0, 0xefff).mirror(0xf0000).noprw(); - map(0xf000, 0xf01f).mirror(0xf0000).rw(FUNC(swtpc09_state::m6844_r), FUNC(swtpc09_state::m6844_w)); - map(0xf020, 0xf023).mirror(0xf0000).rw(m_fdc, FUNC(fd1793_device::read), FUNC(fd1793_device::write)); - map(0xf024, 0xf03f).mirror(0xf0000).rw(FUNC(swtpc09_state::dmf2_control_reg_r), FUNC(swtpc09_state::dmf2_control_reg_w)); - //AM_RANGE(0xf042, 0xf7ff) AM_MIRROR(0xf0000) AM_NOP - map(0xf800, 0xffff).mirror(0xf0000).rom().region("maincpu", 0xf800); + map(0xfe000, 0xfe7ff).rw(FUNC(swtpc09_state::unmapped_r), FUNC(swtpc09_state::unmapped_w)); + + // 0xfe004, 0xfe005 ACIA + map(0xfe000, 0xfe00f).rw("io0", FUNC(ss50_interface_port_device::read), FUNC(ss50_interface_port_device::write)); + map(0xfe010, 0xfe01f).rw("io1", FUNC(ss50_interface_port_device::read), FUNC(ss50_interface_port_device::write)); + map(0xfe020, 0xfe02f).rw("io2", FUNC(ss50_interface_port_device::read), FUNC(ss50_interface_port_device::write)); + map(0xfe030, 0xfe03f).rw("io3", FUNC(ss50_interface_port_device::read), FUNC(ss50_interface_port_device::write)); + map(0xfe040, 0xfe04f).rw("io4", FUNC(ss50_interface_port_device::read), FUNC(ss50_interface_port_device::write)); + map(0xfe050, 0xfe05f).rw("io5", FUNC(ss50_interface_port_device::read), FUNC(ss50_interface_port_device::write)); + map(0xfe060, 0xfe06f).rw("io6", FUNC(ss50_interface_port_device::read), FUNC(ss50_interface_port_device::write)); + map(0xfe070, 0xfe07f).rw("io7", FUNC(ss50_interface_port_device::read), FUNC(ss50_interface_port_device::write)); + + // MPID + map(0xfe080, 0xfe083).mirror(0xc).rw(m_pia, FUNC(pia6821_device::read), FUNC(pia6821_device::write)); + map(0xfe090, 0xfe097).mirror(0x8).rw(m_ptm, FUNC(ptm6840_device::read), FUNC(ptm6840_device::write)); + // DMAF2 + map(0xff000, 0xff01f).rw(FUNC(swtpc09_state::m6844_r), FUNC(swtpc09_state::m6844_w)); + map(0xff020, 0xff023).rw(FUNC(swtpc09_state::dmaf2_fdc_r), FUNC(swtpc09_state::dmaf2_fdc_w)); + map(0xff024, 0xff03f).rw(FUNC(swtpc09_state::dmaf2_control_reg_r), FUNC(swtpc09_state::dmaf2_control_reg_w)); + + map(0xff800, 0xfffff).rom().region("bankdev", 0xff800); } -void swtpc09_state::flex_dc4_piaide_mem(address_map &map) +void swtpc09_state::flex_dc5_piaide_mem(address_map &map) { - map(0x00000, 0x0efff).ram(); // by default everything is ram, 1MB ram emulated - map(0x10000, 0x1efff).ram(); // avoid the s09ram though - map(0xe000, 0xe003).mirror(0xf0000).noprw(); - map(0xe004, 0xe005).mirror(0xf0000).rw(m_acia, FUNC(acia6850_device::read), FUNC(acia6850_device::write)); - map(0xe014, 0xe014).mirror(0xf0000).w(FUNC(swtpc09_state::dc4_control_reg_w)); - map(0xe018, 0xe01b).mirror(0xf0000).rw(m_fdc, FUNC(fd1793_device::read), FUNC(fd1793_device::write)); - //AM_RANGE(0xe01c, 0xe05f) AM_MIRROR(0xf0000) AM_NOP - map(0xe060, 0xe063).mirror(0xf000c).rw(m_piaide, FUNC(pia6821_device::read), FUNC(pia6821_device::write)); - //AM_RANGE(0xe070, 0xe07f) AM_MIRROR(0xf0000) AM_NOP - map(0xe080, 0xe083).mirror(0xf000c).rw(m_pia, FUNC(pia6821_device::read), FUNC(pia6821_device::write)); - map(0xe090, 0xe097).mirror(0xf0008).rw(m_ptm, FUNC(ptm6840_device::read), FUNC(ptm6840_device::write)); - //AM_RANGE(0xe0a0, 0xe7ff) AM_MIRROR(0xf0000) AM_NOP - map(0xe800, 0xefff).mirror(0xf0000).rom().region("maincpu", 0xe800); //piaide rom - //AM_RANGE(0xf000, 0xf01f) AM_MIRROR(0xf0000) AM_READWRITE(m6844_r, m6844_w) - //AM_RANGE(0xf020, 0xf023) AM_MIRROR(0xf0000) AM_DEVREADWRITE("fdc", fd1793_device, read, write) - //AM_RANGE(0xf024, 0xf03f) AM_MIRROR(0xf0000) AM_READWRITE(dmf2_control_reg_r, dmf2_control_reg_w) - //AM_RANGE(0xf040, 0xf041) AM_MIRROR(0xf0000) AM_READWRITE(dmf2_dma_address_reg_r, dmf2_dma_address_reg_w) - map(0xf000, 0xf7ff).mirror(0xf0000).ram().share("s09ram"); // 2k ram for piaide on s09 board - map(0xf800, 0xffff).mirror(0xf0000).rom().region("maincpu", 0xf800); + map(0x00000, 0xfffff).ram(); // by default everything is ram, 1MB ram emulated + map(0xfe000, 0xfe7ff).rw(FUNC(swtpc09_state::unmapped_r), FUNC(swtpc09_state::unmapped_w)); + + // 0xfe004, 0xfe005 ACIA + map(0xfe000, 0xfe00f).rw("io0", FUNC(ss50_interface_port_device::read), FUNC(ss50_interface_port_device::write)); + // 0xfe014 0xfe018-0xfe01b DC5 FDC + map(0xfe010, 0xfe01f).rw("io1", FUNC(ss50_interface_port_device::read), FUNC(ss50_interface_port_device::write)); + map(0xfe020, 0xfe02f).rw("io2", FUNC(ss50_interface_port_device::read), FUNC(ss50_interface_port_device::write)); + map(0xfe030, 0xfe03f).rw("io3", FUNC(ss50_interface_port_device::read), FUNC(ss50_interface_port_device::write)); + map(0xfe040, 0xfe04f).rw("io4", FUNC(ss50_interface_port_device::read), FUNC(ss50_interface_port_device::write)); + map(0xfe050, 0xfe05f).rw("io5", FUNC(ss50_interface_port_device::read), FUNC(ss50_interface_port_device::write)); + // PIA IDE + map(0xfe060, 0xfe06f).rw("io6", FUNC(ss50_interface_port_device::read), FUNC(ss50_interface_port_device::write)); + map(0xfe070, 0xfe07f).rw("io7", FUNC(ss50_interface_port_device::read), FUNC(ss50_interface_port_device::write)); + + // MPID + map(0xfe080, 0xfe083).mirror(0xc).rw(m_pia, FUNC(pia6821_device::read), FUNC(pia6821_device::write)); + map(0xfe090, 0xfe097).mirror(0x8).rw(m_ptm, FUNC(ptm6840_device::read), FUNC(ptm6840_device::write)); + + // TODO How does this mapping change with the bank changes? + map(0xfe800, 0xfefff).rom().region("bankdev", 0xfe800); //piaide rom + + map(0xff800, 0xfffff).rom().region("bankdev", 0xff800); } -void swtpc09_state::uniflex_dmf2_mem(address_map &map) +void swtpc09_state::uniflex_dmaf2_mem(address_map &map) { map(0x00000, 0xfffff).ram(); // by default everything is ram, 1MB ram emulated - map(0xe000, 0xe001).mirror(0xf0000).rw(m_acia, FUNC(acia6850_device::read), FUNC(acia6850_device::write)); - map(0xe002, 0xe07f).mirror(0xf0000).noprw(); - map(0xe080, 0xe083).mirror(0xf000c).rw(m_pia, FUNC(pia6821_device::read), FUNC(pia6821_device::write)); - map(0xe090, 0xe097).mirror(0xf0008).rw(m_ptm, FUNC(ptm6840_device::read), FUNC(ptm6840_device::write)); - map(0xe0a0, 0xefff).mirror(0xf0000).noprw(); - map(0xf000, 0xf01f).mirror(0xf0000).rw(FUNC(swtpc09_state::m6844_r), FUNC(swtpc09_state::m6844_w)); - map(0xf020, 0xf023).mirror(0xf0000).rw(m_fdc, FUNC(fd1793_device::read), FUNC(fd1793_device::write)); - map(0xf024, 0xf03f).mirror(0xf0000).rw(FUNC(swtpc09_state::dmf2_control_reg_r), FUNC(swtpc09_state::dmf2_control_reg_w)); - //AM_RANGE(0xf042, 0xf7ff) AM_MIRROR(0xf0000) AM_NOP - map(0xf800, 0xffff).mirror(0xf0000).rom().region("maincpu", 0xf800); + map(0xfe000, 0xfffff).rw(FUNC(swtpc09_state::unmapped_r), FUNC(swtpc09_state::unmapped_w)); + + // 0xfe000, 0xfe001 ACIA + map(0xfe000, 0xfe00f).rw("io0", FUNC(ss50_interface_port_device::read), FUNC(ss50_interface_port_device::write)); + map(0xfe010, 0xfe01f).rw("io1", FUNC(ss50_interface_port_device::read), FUNC(ss50_interface_port_device::write)); + map(0xfe020, 0xfe02f).rw("io2", FUNC(ss50_interface_port_device::read), FUNC(ss50_interface_port_device::write)); + map(0xfe030, 0xfe03f).rw("io3", FUNC(ss50_interface_port_device::read), FUNC(ss50_interface_port_device::write)); + map(0xfe040, 0xfe04f).rw("io4", FUNC(ss50_interface_port_device::read), FUNC(ss50_interface_port_device::write)); + map(0xfe050, 0xfe05f).rw("io5", FUNC(ss50_interface_port_device::read), FUNC(ss50_interface_port_device::write)); + map(0xfe060, 0xfe06f).rw("io6", FUNC(ss50_interface_port_device::read), FUNC(ss50_interface_port_device::write)); + map(0xfe070, 0xfe07f).rw("io7", FUNC(ss50_interface_port_device::read), FUNC(ss50_interface_port_device::write)); + + // MPID + map(0xfe080, 0xfe083).mirror(0xc).rw(m_pia, FUNC(pia6821_device::read), FUNC(pia6821_device::write)); + map(0xfe090, 0xfe097).mirror(0x8).rw(m_ptm, FUNC(ptm6840_device::read), FUNC(ptm6840_device::write)); + + // DMAF2 + map(0xff000, 0xff01f).rw(FUNC(swtpc09_state::m6844_r), FUNC(swtpc09_state::m6844_w)); + map(0xff020, 0xff023).rw(FUNC(swtpc09_state::dmaf2_fdc_r), FUNC(swtpc09_state::dmaf2_fdc_w)); + map(0xff024, 0xff03f).rw(FUNC(swtpc09_state::dmaf2_control_reg_r), FUNC(swtpc09_state::dmaf2_control_reg_w)); + + map(0xff800, 0xfffff).rom().region("bankdev", 0xff800); } -void swtpc09_state::uniflex_dmf3_mem(address_map &map) +void swtpc09_state::uniflex_dmaf3_mem(address_map &map) { map(0x00000, 0xfffff).ram(); // by default everything is ram, 1MB ram emulated - map(0xe000, 0xe001).mirror(0xf0000).rw(m_acia, FUNC(acia6850_device::read), FUNC(acia6850_device::write)); - map(0xe002, 0xe07f).mirror(0xf0000).noprw(); - map(0xe080, 0xe083).mirror(0xf000c).rw(m_pia, FUNC(pia6821_device::read), FUNC(pia6821_device::write)); - map(0xe090, 0xe097).mirror(0xf0008).rw(m_ptm, FUNC(ptm6840_device::read), FUNC(ptm6840_device::write)); - map(0xe0a0, 0xefff).mirror(0xf0000).noprw(); - map(0xf000, 0xf01f).mirror(0xf0000).rw(FUNC(swtpc09_state::m6844_r), FUNC(swtpc09_state::m6844_w)); - map(0xf020, 0xf023).mirror(0xf0000).rw(m_fdc, FUNC(fd1793_device::read), FUNC(fd1793_device::write)); - map(0xf024, 0xf024).mirror(0xf0000).rw(FUNC(swtpc09_state::dmf3_control_reg_r), FUNC(swtpc09_state::dmf3_control_reg_w)); - map(0xf025, 0xf025).mirror(0xf0000).rw(FUNC(swtpc09_state::dmf3_dma_address_reg_r), FUNC(swtpc09_state::dmf3_dma_address_reg_w)); - //AM_RANGE(0xf030, 0xf03f) AM_MIRROR(0xf0000) AM_NOP - map(0xf040, 0xf04f).mirror(0xf0000).m(m_via, FUNC(via6522_device::map)); - //AM_RANGE(0xf050, 0xf7ff) AM_MIRROR(0xf0000) AM_NOP - map(0xf800, 0xffff).mirror(0xf0000).rom().region("maincpu", 0xf800); + map(0xfe000, 0xfffff).rw(FUNC(swtpc09_state::unmapped_r), FUNC(swtpc09_state::unmapped_w)); + + // 0xfe000, 0xfe001 ACIA + map(0xfe000, 0xfe00f).rw("io0", FUNC(ss50_interface_port_device::read), FUNC(ss50_interface_port_device::write)); + map(0xfe010, 0xfe01f).rw("io1", FUNC(ss50_interface_port_device::read), FUNC(ss50_interface_port_device::write)); + map(0xfe020, 0xfe02f).rw("io2", FUNC(ss50_interface_port_device::read), FUNC(ss50_interface_port_device::write)); + map(0xfe030, 0xfe03f).rw("io3", FUNC(ss50_interface_port_device::read), FUNC(ss50_interface_port_device::write)); + map(0xfe040, 0xfe04f).rw("io4", FUNC(ss50_interface_port_device::read), FUNC(ss50_interface_port_device::write)); + map(0xfe050, 0xfe05f).rw("io5", FUNC(ss50_interface_port_device::read), FUNC(ss50_interface_port_device::write)); + map(0xfe060, 0xfe06f).rw("io6", FUNC(ss50_interface_port_device::read), FUNC(ss50_interface_port_device::write)); + map(0xfe070, 0xfe07f).rw("io7", FUNC(ss50_interface_port_device::read), FUNC(ss50_interface_port_device::write)); + + // MPID + map(0xfe080, 0xfe083).mirror(0xc).rw(m_pia, FUNC(pia6821_device::read), FUNC(pia6821_device::write)); + map(0xfe090, 0xfe097).mirror(0x8).rw(m_ptm, FUNC(ptm6840_device::read), FUNC(ptm6840_device::write)); + + // DMAF3 + map(0xff000, 0xff01f).rw(FUNC(swtpc09_state::m6844_r), FUNC(swtpc09_state::m6844_w)); + map(0xff020, 0xff023).rw(FUNC(swtpc09_state::dmaf3_fdc_r), FUNC(swtpc09_state::dmaf3_fdc_w)); + map(0xff024, 0xff024).rw(FUNC(swtpc09_state::dmaf3_control_reg_r), FUNC(swtpc09_state::dmaf3_control_reg_w)); + map(0xff025, 0xff025).rw(FUNC(swtpc09_state::dmaf3_dma_address_reg_r), FUNC(swtpc09_state::dmaf3_dma_address_reg_w)); + map(0xff040, 0xff04f).m(m_via, FUNC(via6522_device::map)); + + // DMAF3 WD1000 + map(0xff030, 0xff03f).rw(FUNC(swtpc09_state::dmaf3_wd_r), FUNC(swtpc09_state::dmaf3_wd_w)); + + map(0xff800, 0xfffff).rom().region("bankdev", 0xff800); } /* Input ports */ static INPUT_PORTS_START( swtpc09 ) + // The MP09 was available in 4MHz or 8MHz XTALs, running the 6809 at + // 1MHz or 2MHz respectively. Also allow an overclock option. + // + // Run the 6809 at 2MHz (an 8MHz XTAL) so that manual polling of FDC can + // keep up with higher rate operation. The MPU09 did have the option of + // 1MHz or 2MHz operation. + PORT_START("maincpu_clock") + PORT_CONFNAME(0xffffff, 2000000, "CPU clock") + PORT_CONFSETTING(1000000, "1.0 MHz") + PORT_CONFSETTING(2000000, "2.0 MHz") + PORT_CONFSETTING(4000000, "4.0 MHz") + + // The DMAF2/3 clock can be jumpered selected for 1 or 2MHz, for 5.24" + // and 8" drives. Some other options are also provided here. + // + // single or double density 5.24" - 1.0MHz + // 'standard' 3.5" - 1.2MHz + // 3.5" hd - 2.0MHz + // 8" 360rpm - 2.4MHz + PORT_START("fdc_clock") + PORT_DIPNAME(0xffffff, 2000000, "DMAF2/3 FDC clock") + PORT_DIPSETTING(1000000, "1.0 MHz") + PORT_DIPSETTING(1200000, "1.2 MHz") + PORT_DIPSETTING(2000000, "2.0 MHz") + PORT_DIPSETTING(2400000, "2.4 MHz") + + // The MP-ID board has jumpers to vary the baud rates generated. The + // most useful is the Low/High rate jumper that provide a four times + // rate increase. + PORT_START("baud_rate_high") + PORT_DIPNAME(0x1, 0, "High baud rate") + PORT_DIPSETTING(0, "Low (x1)") + PORT_DIPSETTING(1, "High (x4)") + + // Debug aid to hard code the density. The FLEX format uses single + // density for track zero. Many virtual disks 'fix' the format to be + // purely double density and often without properly implementing + // driver support for that. This setting is an aid to report + // unexpected usage, and it attempts to correct that. It is possible + // to patch the software to work with these pure double density disks. + PORT_START("floppy_expected_density") + PORT_CONFNAME(0xff, 0, "DMAF2/3 expected density") + PORT_CONFSETTING(0, "-") + PORT_CONFSETTING(1, "single density") + PORT_CONFSETTING(2, "double density, with single density track zero") + PORT_CONFSETTING(3, "double density") + + // Debug aid, to check that the sector head or side is set as expected + // for the sector ID being read for the FLEX floppy disk format. Many + // FLEX disk images were developed for vitural machines that have + // little regard for the actual head and can work off the sector ID + // and their drivers can set the head incorrectly. E.g. a disk with 18 + // sectors per side might have a drive set to switch heads for sectors + // above 10. Another issue is that double density disk images are + // often 'fixed' so that they are pure double density without being + // single density onthe first track, and the drivers might still set + // the head based track zero being single density. This aid is not + // intended to be a substitute for fixing the drivers but it does help + // work through the issues while patching the disks. + PORT_START("floppy_expected_sectors") + PORT_CONFNAME(0xff, 0, "DMAF2/3 expected sectors per side") + PORT_CONFSETTING(0, "-") + PORT_CONFSETTING(10, "10") // 5 1/4" single density 256B + PORT_CONFSETTING(15, "15") // 8" single density 256B + PORT_CONFSETTING(18, "18") // 5 1/4" double density 256B + PORT_CONFSETTING(26, "26") // 8" double density 256B + PORT_CONFSETTING(36, "36") // 3.5" 1.4M QD 256B + // The track zero expected sectors if different from the above. FLEX + // 6800 disks did format track zero in single density and if the + // driver sticks to that and if using a double density disk then set a + // single density size here. + PORT_START("floppy_track_zero_expected_sectors") + PORT_CONFNAME(0xff, 0, "DMAF2/3 track zero expected sectors per side") + PORT_CONFSETTING(0, "-") + PORT_CONFSETTING(10, "10") // 5 1/4" single density 256B + PORT_CONFSETTING(15, "15") // 8" single density 256B + PORT_CONFSETTING(18, "18") // 5 1/4" double density 256B + PORT_CONFSETTING(26, "26") // 8" double density 256B + PORT_CONFSETTING(36, "36") // 3.5" 1.4M QD 256B + + PORT_START("sbug_double_density") + PORT_CONFNAME(0x1, 0, "SBUG patch for double density (SSO) disk boot") + PORT_CONFSETTING(0, "No - single density") + PORT_CONFSETTING(1, "Yes - double density") + + // The PIA IDE PROM includes initialization code that patches FLEX + // after the disk boot code has loaded FLEX, and then it jumps to + // 0xc850 to cold start FLEX. Have seen 0xcd00 being the cold start + // address, so add an option to patch the PROM for that. + PORT_START("piaide_flex_boot_cd00") + PORT_CONFNAME(0x1, 0, "PIA IDE PROM patch FLEX entry to 0xcd00") + PORT_CONFSETTING(0, "No - FLEX entry 0xc850") + PORT_CONFSETTING(1, "Yes - FLEX entry 0xcd00") + INPUT_PORTS_END -FLOPPY_FORMATS_MEMBER( swtpc09_state::floppy_formats ) + +static DEVICE_INPUT_DEFAULTS_START( dc5 ) + DEVICE_INPUT_DEFAULTS("address_mode", 0xf, 1) +DEVICE_INPUT_DEFAULTS_END + + +FLOPPY_FORMATS_MEMBER( swtpc09_state::floppy_flex_formats ) + FLOPPY_MFI_FORMAT, FLOPPY_FLEX_FORMAT FLOPPY_FORMATS_END +FLOPPY_FORMATS_MEMBER( swtpc09_state::floppy_uniflex_formats ) + FLOPPY_MFI_FORMAT, + FLOPPY_UNIFLEX_FORMAT +FLOPPY_FORMATS_END + + // todo: implement floppy controller cards as slot devices and do this properly -static void swtpc09_floppies(device_slot_interface &device) +static void swtpc09_flex_floppies(device_slot_interface &device) { - device.option_add("sssd", FLOPPY_525_SSSD); // flex 40 trks ss sd 5.25 - device.option_add("sssd35", FLOPPY_525_SSSD_35T); // flex 35 trks ss sd 5.25 - device.option_add("ssdd", FLOPPY_525_SSDD); // flex 40 trks ss dd 5.25 - device.option_add("dd", FLOPPY_525_DD); // flex 40 trks ds dd 5.25 - device.option_add("8dssd", FLOPPY_8_DSSD); // UNIFlex 8 inch ds sd - device.option_add("8dsdd", FLOPPY_8_DSDD); // UNIFlex 8 inch ds dd - device.option_add("35hd", FLOPPY_35_HD); // flex 1.44mb disk from swtpc emu (emulator only?) + device.option_add("sssd35", FLOPPY_525_SSSD_35T); // 35 trks ss sd 5.25 + device.option_add("sssd", FLOPPY_525_SSSD); // 40 trks ss sd 5.25 + device.option_add("dssd35", FLOPPY_525_SD_35T); // 35 trks ds sd 5.25 + device.option_add("dssd", FLOPPY_525_SD); // 40 trks ds sd 5.25 + device.option_add("ssdd", FLOPPY_525_SSDD); // 40 trks ss dd 5.25 + device.option_add("dd", FLOPPY_525_DD); // 40 trks ds dd 5.25 + device.option_add("ssqd", FLOPPY_525_SSQD); // 80 trks ss dd 5.25 + device.option_add("qd", FLOPPY_525_QD); // 80 trks ds dd 5.25 + device.option_add("8sssd", FLOPPY_8_SSSD); // 77 trks ss sd 8" + device.option_add("8dssd", FLOPPY_8_DSSD); // 77 trks ds sd 8" + device.option_add("8ssdd", FLOPPY_8_SSDD); // 77 trks ss dd 8" + device.option_add("8dsdd", FLOPPY_8_DSDD); // 77 trks ds dd 8" + device.option_add("35hd", FLOPPY_35_HD); // 1.44mb disk } +static void swtpc09_uniflex_floppies(device_slot_interface &device) +{ + device.option_add("8dssd", FLOPPY_8_DSSD); // 8 inch ds sd + device.option_add("8dsdd", FLOPPY_8_DSDD); // 8 inch ds dd + } + /*************************************************************************** Machine definitions ****************************************************************************/ /* Machine driver */ -/* MPU09, MPID, MPS2 DMF2 */ +/* MPU09, MPID, MPS2 */ void swtpc09_state::swtpc09_base(machine_config &config) { /* basic machine hardware */ - MC6809(config, m_maincpu, 4_MHz_XTAL); + MC6809(config, m_maincpu, 8_MHz_XTAL); m_maincpu->set_addrmap(AS_PROGRAM, &swtpc09_state::mp09_mem); ADDRESS_MAP_BANK(config, m_bankdev, 0); m_bankdev->set_endianness(ENDIANNESS_BIG); m_bankdev->set_data_width(8); m_bankdev->set_addr_width(20); - m_bankdev->set_addrmap(AS_PROGRAM, &swtpc09_state::flex_dmf2_mem); - + m_bankdev->set_addrmap(AS_PROGRAM, &swtpc09_state::flex_dmaf2_mem); + + // IO0 at 0xe000 is used for the MP-S2 ACIA. + ss50_interface_port_device &io0(SS50_INTERFACE(config, "io0", ss50_default_2rs_devices, nullptr)); + io0.irq_cb().set("mainirq", FUNC(input_merger_device::in_w<0>)); + io0.firq_cb().set("mainfirq", FUNC(input_merger_device::in_w<0>)); + // IO1 at 0xe010 is used for the DC5 FDC. + ss50_interface_port_device &io1(SS50_INTERFACE(config, "io1", ss50_default_2rs_devices, nullptr)); + io1.irq_cb().set("mainirq", FUNC(input_merger_device::in_w<1>)); + io1.firq_cb().set("mainfirq", FUNC(input_merger_device::in_w<1>)); + ss50_interface_port_device &io2(SS50_INTERFACE(config, "io2", ss50_default_2rs_devices, nullptr)); + io2.irq_cb().set("mainirq", FUNC(input_merger_device::in_w<2>)); + io2.firq_cb().set("mainfirq", FUNC(input_merger_device::in_w<2>)); + ss50_interface_port_device &io3(SS50_INTERFACE(config, "io3", ss50_default_2rs_devices, nullptr)); + io3.irq_cb().set("mainirq", FUNC(input_merger_device::in_w<3>)); + io3.firq_cb().set("mainfirq", FUNC(input_merger_device::in_w<3>)); + ss50_interface_port_device &io4(SS50_INTERFACE(config, "io4", ss50_default_2rs_devices, nullptr)); + io4.irq_cb().set("mainirq", FUNC(input_merger_device::in_w<4>)); + io4.firq_cb().set("mainfirq", FUNC(input_merger_device::in_w<4>)); + ss50_interface_port_device &io5(SS50_INTERFACE(config, "io5", ss50_default_2rs_devices, nullptr)); + io5.irq_cb().set("mainirq", FUNC(input_merger_device::in_w<5>)); + io5.firq_cb().set("mainfirq", FUNC(input_merger_device::in_w<5>)); + // IO6 at 0xe060 is used for PIA-IDE + ss50_interface_port_device &io6(SS50_INTERFACE(config, "io6", ss50_default_2rs_devices, nullptr)); + io6.irq_cb().set("mainirq", FUNC(input_merger_device::in_w<6>)); + io6.firq_cb().set("mainfirq", FUNC(input_merger_device::in_w<6>)); + ss50_interface_port_device &io7(SS50_INTERFACE(config, "io7", ss50_default_2rs_devices, nullptr)); + io7.irq_cb().set("mainirq", FUNC(input_merger_device::in_w<7>)); + io7.firq_cb().set("mainfirq", FUNC(input_merger_device::in_w<7>)); + + // IO8 at 0xe080 is used internally by the MPID board PIA. PIA6821(config, m_pia, 0); m_pia->readpa_handler().set(FUNC(swtpc09_state::pia0_a_r)); m_pia->readca1_handler().set(FUNC(swtpc09_state::pia0_ca1_r)); m_pia->irqa_handler().set(FUNC(swtpc09_state::pia0_irq_a)); + // IO9 at 0xe090 is used internally by the MPID board 6840 timer. PTM6840(config, m_ptm, 2000000); m_ptm->set_external_clocks(50, 0, 50); m_ptm->o1_callback().set(FUNC(swtpc09_state::ptm_o1_callback)); m_ptm->o3_callback().set(FUNC(swtpc09_state::ptm_o3_callback)); m_ptm->irq_callback().set(FUNC(swtpc09_state::ptm_irq)); - rs232_port_device &rs232(RS232_PORT(config, "rs232", default_rs232_devices, "terminal")); - rs232.rxd_handler().set(m_acia, FUNC(acia6850_device::write_rxd)); - rs232.cts_handler().set(m_acia, FUNC(acia6850_device::write_cts)); - - ACIA6850(config, m_acia, 0); - m_acia->txd_handler().set("rs232", FUNC(rs232_port_device::write_txd)); - m_acia->rts_handler().set("rs232", FUNC(rs232_port_device::write_rts)); - m_acia->irq_handler().set(FUNC(swtpc09_state::acia_interrupt)); - + // MP-ID baud rate generator MC14411(config, m_brg, 1.8432_MHz_XTAL); - m_brg->out_f<1>().set(m_acia, FUNC(acia6850_device::write_txc)); - m_brg->out_f<1>().append(m_acia, FUNC(acia6850_device::write_rxc)); - - FD1793(config, m_fdc, 1_MHz_XTAL); - FLOPPY_CONNECTOR(config, "fdc:0", swtpc09_floppies, "dd", swtpc09_state::floppy_formats); - FLOPPY_CONNECTOR(config, "fdc:1", swtpc09_floppies, "dd", swtpc09_state::floppy_formats); - FLOPPY_CONNECTOR(config, "fdc:2", swtpc09_floppies, "dd", swtpc09_state::floppy_formats); - FLOPPY_CONNECTOR(config, "fdc:3", swtpc09_floppies, "dd", swtpc09_state::floppy_formats); + // 9600b / 38400b + m_brg->out_f<1>().set("io0", FUNC(ss50_interface_port_device::f150_9600_w)); + m_brg->out_f<1>().append("io1", FUNC(ss50_interface_port_device::f150_9600_w)); + m_brg->out_f<1>().append("io2", FUNC(ss50_interface_port_device::f150_9600_w)); + m_brg->out_f<1>().append("io3", FUNC(ss50_interface_port_device::f150_9600_w)); + m_brg->out_f<1>().append("io4", FUNC(ss50_interface_port_device::f150_9600_w)); + m_brg->out_f<1>().append("io5", FUNC(ss50_interface_port_device::f150_9600_w)); + m_brg->out_f<1>().append("io6", FUNC(ss50_interface_port_device::f150_9600_w)); + m_brg->out_f<1>().append("io7", FUNC(ss50_interface_port_device::f150_9600_w)); + // 4800b / 19200b + m_brg->out_f<3>().set("io0", FUNC(ss50_interface_port_device::f600_4800_w)); + m_brg->out_f<3>().append("io1", FUNC(ss50_interface_port_device::f600_4800_w)); + m_brg->out_f<3>().append("io2", FUNC(ss50_interface_port_device::f600_4800_w)); + m_brg->out_f<3>().append("io3", FUNC(ss50_interface_port_device::f600_4800_w)); + m_brg->out_f<3>().append("io4", FUNC(ss50_interface_port_device::f600_4800_w)); + m_brg->out_f<3>().append("io5", FUNC(ss50_interface_port_device::f600_4800_w)); + m_brg->out_f<3>().append("io6", FUNC(ss50_interface_port_device::f600_4800_w)); + m_brg->out_f<3>().append("io7", FUNC(ss50_interface_port_device::f600_4800_w)); + // 1200b / 4800b + m_brg->out_f<7>().set("io0", FUNC(ss50_interface_port_device::f600_1200_w)); + m_brg->out_f<7>().append("io1", FUNC(ss50_interface_port_device::f600_1200_w)); + m_brg->out_f<7>().append("io2", FUNC(ss50_interface_port_device::f600_1200_w)); + m_brg->out_f<7>().append("io3", FUNC(ss50_interface_port_device::f600_1200_w)); + m_brg->out_f<7>().append("io4", FUNC(ss50_interface_port_device::f600_1200_w)); + m_brg->out_f<7>().append("io5", FUNC(ss50_interface_port_device::f600_1200_w)); + m_brg->out_f<7>().append("io6", FUNC(ss50_interface_port_device::f600_1200_w)); + m_brg->out_f<7>().append("io7", FUNC(ss50_interface_port_device::f600_1200_w)); + // 300b / 1200b + m_brg->out_f<9>().set("io0", FUNC(ss50_interface_port_device::f300_w)); + m_brg->out_f<9>().append("io1", FUNC(ss50_interface_port_device::f300_w)); + m_brg->out_f<9>().append("io2", FUNC(ss50_interface_port_device::f300_w)); + m_brg->out_f<9>().append("io3", FUNC(ss50_interface_port_device::f300_w)); + m_brg->out_f<9>().append("io4", FUNC(ss50_interface_port_device::f300_w)); + m_brg->out_f<9>().append("io5", FUNC(ss50_interface_port_device::f300_w)); + m_brg->out_f<9>().append("io6", FUNC(ss50_interface_port_device::f300_w)); + m_brg->out_f<9>().append("io7", FUNC(ss50_interface_port_device::f300_w)); + // 110b / 440b + m_brg->out_f<13>().set("io0", FUNC(ss50_interface_port_device::f110_w)); + m_brg->out_f<13>().append("io1", FUNC(ss50_interface_port_device::f110_w)); + m_brg->out_f<13>().append("io2", FUNC(ss50_interface_port_device::f110_w)); + m_brg->out_f<13>().append("io3", FUNC(ss50_interface_port_device::f110_w)); + m_brg->out_f<13>().append("io4", FUNC(ss50_interface_port_device::f110_w)); + m_brg->out_f<13>().append("io5", FUNC(ss50_interface_port_device::f110_w)); + m_brg->out_f<13>().append("io6", FUNC(ss50_interface_port_device::f110_w)); + m_brg->out_f<13>().append("io7", FUNC(ss50_interface_port_device::f110_w)); + + INPUT_MERGER_ANY_HIGH(config, "mainirq").output_handler().set(FUNC(swtpc09_state::io_irq_w)); + INPUT_MERGER_ANY_HIGH(config, "mainfirq").output_handler().set_inputline(m_maincpu, M6809_FIRQ_LINE); + + subdevice<ss50_interface_port_device>("io0")->set_default_option("mps2"); } +/* MPU09, MPID, MPS2, DMAF2 */ void swtpc09_state::swtpc09(machine_config &config) { swtpc09_base(config); + + // DMAF2 + FD1797(config, m_fdc, 2000000); + FLOPPY_CONNECTOR(config, "fdc:0", swtpc09_flex_floppies, "dd", swtpc09_state::floppy_flex_formats).enable_sound(true); + FLOPPY_CONNECTOR(config, "fdc:1", swtpc09_flex_floppies, "dd", swtpc09_state::floppy_flex_formats).enable_sound(true); + FLOPPY_CONNECTOR(config, "fdc:2", swtpc09_flex_floppies, "dd", swtpc09_state::floppy_flex_formats).enable_sound(true); + FLOPPY_CONNECTOR(config, "fdc:3", swtpc09_flex_floppies, "dd", swtpc09_state::floppy_flex_formats).enable_sound(true); + m_fdc->intrq_wr_callback().set(FUNC(swtpc09_state::fdc_intrq_w)); m_fdc->drq_wr_callback().set(FUNC(swtpc09_state::fdc_drq_w)); + m_fdc->sso_wr_callback().set(FUNC(swtpc09_state::fdc_sso_w)); } -/* MPU09, MPID, MPS2 DC4 PIAIDE*/ +/* MPU09, MPID, MPS2, DC5, MPT, PIAIDE*/ void swtpc09_state::swtpc09i(machine_config &config) { swtpc09_base(config); - m_bankdev->set_addrmap(AS_PROGRAM, &swtpc09_state::flex_dc4_piaide_mem); + m_bankdev->set_addrmap(AS_PROGRAM, &swtpc09_state::flex_dc5_piaide_mem); - PIA6821(config, "piaide", 0); - - /* TODO: add ide support, via add-on card driving IDE from a PIA */ + subdevice<ss50_interface_port_device>("io1")->set_default_option("dc5"); + subdevice<ss50_interface_port_device>("io1")->set_option_device_input_defaults("dc5", DEVICE_INPUT_DEFAULTS_NAME(dc5)); + subdevice<ss50_interface_port_device>("io4")->set_default_option("mpt"); + subdevice<ss50_interface_port_device>("io6")->set_default_option("piaide"); } void swtpc09_state::swtpc09u(machine_config &config) { - swtpc09(config); - m_bankdev->set_addrmap(AS_PROGRAM, &swtpc09_state::uniflex_dmf2_mem); + swtpc09_base(config); + m_bankdev->set_addrmap(AS_PROGRAM, &swtpc09_state::uniflex_dmaf2_mem); + + // DMAF2 + FD1797(config, m_fdc, 2400000); + FLOPPY_CONNECTOR(config, "fdc:0", swtpc09_uniflex_floppies, "8dsdd", swtpc09_state::floppy_uniflex_formats).enable_sound(true); + FLOPPY_CONNECTOR(config, "fdc:1", swtpc09_uniflex_floppies, "8dsdd", swtpc09_state::floppy_uniflex_formats).enable_sound(true); + FLOPPY_CONNECTOR(config, "fdc:2", swtpc09_uniflex_floppies, "8dsdd", swtpc09_state::floppy_uniflex_formats).enable_sound(true); + FLOPPY_CONNECTOR(config, "fdc:3", swtpc09_uniflex_floppies, "8dsdd", swtpc09_state::floppy_uniflex_formats).enable_sound(true); + + m_fdc->intrq_wr_callback().set(FUNC(swtpc09_state::fdc_intrq_w)); + m_fdc->drq_wr_callback().set(FUNC(swtpc09_state::fdc_drq_w)); + m_fdc->sso_wr_callback().set(FUNC(swtpc09_state::fdc_sso_w)); } -/* MPU09, MPID, MPS2 DMF3 */ +/* MPU09, MPID, MPS2 DMAF3 */ void swtpc09_state::swtpc09d3(machine_config &config) { swtpc09_base(config); - m_maincpu->set_clock(8_MHz_XTAL); m_pia->set_clock(2000000); - m_bankdev->set_addrmap(AS_PROGRAM, &swtpc09_state::uniflex_dmf3_mem); + m_bankdev->set_addrmap(AS_PROGRAM, &swtpc09_state::uniflex_dmaf3_mem); - /* video hardware */ - m_acia->irq_handler().set_inputline(m_maincpu, M6809_IRQ_LINE); + // DMAF3 + FD1797(config, m_fdc, 2400000); + FLOPPY_CONNECTOR(config, "fdc:0", swtpc09_uniflex_floppies, "8dsdd", swtpc09_state::floppy_uniflex_formats).enable_sound(true); + FLOPPY_CONNECTOR(config, "fdc:1", swtpc09_uniflex_floppies, "8dsdd", swtpc09_state::floppy_uniflex_formats).enable_sound(true); + FLOPPY_CONNECTOR(config, "fdc:2", swtpc09_uniflex_floppies, "8dsdd", swtpc09_state::floppy_uniflex_formats).enable_sound(true); + FLOPPY_CONNECTOR(config, "fdc:3", swtpc09_uniflex_floppies, "8dsdd", swtpc09_state::floppy_uniflex_formats).enable_sound(true); + + m_fdc->intrq_wr_callback().set(FUNC(swtpc09_state::fdc_intrq_w)); + m_fdc->drq_wr_callback().set(FUNC(swtpc09_state::fdc_drq_w)); + m_fdc->sso_wr_callback().set(FUNC(swtpc09_state::fdc_sso_w)); via6522_device &via(VIA6522(config, "via", 4_MHz_XTAL / 4)); - via.readpa_handler().set(FUNC(swtpc09_state::dmf3_via_read_porta)); - via.readpb_handler().set(FUNC(swtpc09_state::dmf3_via_read_portb)); - via.writepa_handler().set(FUNC(swtpc09_state::dmf3_via_write_porta)); - //via.ca1_handler().set(FUNC(swtpc09_state::dmf3_via_write_ca1)); - via.irq_handler().set(FUNC(swtpc09_state::dmf3_via_irq)); + via.readpa_handler().set(FUNC(swtpc09_state::dmaf3_via_read_porta)); + via.readpb_handler().set(FUNC(swtpc09_state::dmaf3_via_read_portb)); + via.writepa_handler().set(FUNC(swtpc09_state::dmaf3_via_write_porta)); + //via.ca1_handler().set(FUNC(swtpc09_state::dmaf3_via_write_ca1)); + via.irq_handler().set(FUNC(swtpc09_state::dmaf3_via_irq)); } /* ROM definition */ ROM_START( swtpc09 ) - ROM_REGION( 0x100000, "maincpu", 0 ) - ROM_LOAD ( "sbugh1-8.bin", 0xf800, 0x0800, CRC(10a045a7) SHA1(de547b77653951c7424a069520d52c5b0432e98d) ) + ROM_REGION( 0x100000, "bankdev", 0 ) + ROM_LOAD ( "sbugh1-8.bin", 0xff800, 0x0800, CRC(10a045a7) SHA1(de547b77653951c7424a069520d52c5b0432e98d) ) ROM_END ROM_START( swtpc09i ) - ROM_REGION( 0x100000, "maincpu", 0 ) - ROM_LOAD ( "hd-rom.bin", 0xe800, 0x0800, CRC(b898b4d7) SHA1(2806633eda7da4e9a243fc534f15526ee928b6bc) ) - ROM_LOAD ( "sbugh1-8.bin", 0xf800, 0x0800, CRC(10a045a7) SHA1(de547b77653951c7424a069520d52c5b0432e98d) ) + ROM_REGION( 0x100000, "bankdev", 0 ) + ROM_LOAD ( "hd-rom.bin", 0xfe800, 0x0800, CRC(b898b4d7) SHA1(2806633eda7da4e9a243fc534f15526ee928b6bc) ) + ROM_LOAD ( "sbugh1-8.bin", 0xff800, 0x0800, CRC(10a045a7) SHA1(de547b77653951c7424a069520d52c5b0432e98d) ) ROM_END ROM_START( swtpc09u ) - ROM_REGION( 0x100000, "maincpu", 0 ) - ROM_LOAD ( "unibug.bin", 0xf800, 0x0800, CRC(92e1cbf2) SHA1(db00f17ee9accdbfa1775fe0162d3556159b8e70) ) + ROM_REGION( 0x100000, "bankdev", 0 ) + ROM_LOAD ( "unibug.bin", 0xff800, 0x00800, CRC(92e1cbf2) SHA1(db00f17ee9accdbfa1775fe0162d3556159b8e70) ) ROM_END ROM_START( swtpc09d3 ) - ROM_REGION( 0x100000, "maincpu", 0 ) - ROM_LOAD ( "uos3.bin", 0xf800, 0x0800, CRC(e95eb3e0) SHA1(3e971d3b7e143bc87e4b506e18a8c928c089c25a) ) + ROM_REGION( 0x100000, "bankdev", 0 ) + ROM_LOAD ( "uos3.bin", 0xff800, 0x00800, CRC(e95eb3e0) SHA1(3e971d3b7e143bc87e4b506e18a8c928c089c25a) ) ROM_END /* Driver */ // YEAR NAME PARENT COMPAT MACHINE INPUT CLASS INIT COMPANY FULLNAME FLAGS COMP( 1980, swtpc09, 0, 0, swtpc09, swtpc09, swtpc09_state, init_swtpc09, "SWTPC", "swtpc S/09 Sbug", MACHINE_NO_SOUND_HW ) -COMP( 1980, swtpc09i, swtpc09, 0, swtpc09i, swtpc09, swtpc09_state, init_swtpc09i, "SWTPC", "swtpc S/09 Sbug + piaide", MACHINE_NOT_WORKING | MACHINE_NO_SOUND_HW ) -COMP( 1980, swtpc09u, swtpc09, 0, swtpc09u, swtpc09, swtpc09_state, init_swtpc09u, "SWTPC", "swtpc S/09 UNIBug + DMF2", MACHINE_NO_SOUND_HW ) -COMP( 1980, swtpc09d3, swtpc09, 0, swtpc09d3, swtpc09, swtpc09_state, init_swtpc09d3, "SWTPC", "swtpc S/09 UNIBug + DMF3", MACHINE_NO_SOUND_HW ) +COMP( 1980, swtpc09i, swtpc09, 0, swtpc09i, swtpc09, swtpc09_state, init_swtpc09i, "SWTPC", "swtpc S/09 Sbug + piaide", MACHINE_NO_SOUND_HW ) +COMP( 1980, swtpc09u, swtpc09, 0, swtpc09u, swtpc09, swtpc09_state, init_swtpc09u, "SWTPC", "swtpc S/09 UNIBug + DMAF2", MACHINE_NO_SOUND_HW ) +COMP( 1980, swtpc09d3, swtpc09, 0, swtpc09d3, swtpc09, swtpc09_state, init_swtpc09d3, "SWTPC", "swtpc S/09 UNIBug + DMAF3", MACHINE_NO_SOUND_HW ) diff --git a/src/mame/includes/swtpc09.h b/src/mame/includes/swtpc09.h index 17178c7434c..8dc3b9169e7 100644 --- a/src/mame/includes/swtpc09.h +++ b/src/mame/includes/swtpc09.h @@ -1,5 +1,5 @@ // license:BSD-3-Clause -// copyright-holders:Robert Justice +// copyright-holders:Robert Justice,68bit /*************************************************************************** swtpc09 include file Robert Justice ,2009-2014 @@ -17,14 +17,10 @@ #include "imagedev/floppy.h" #include "machine/6840ptm.h" #include "machine/6821pia.h" -#include "machine/6850acia.h" #include "machine/6522via.h" #include "imagedev/harddriv.h" -#include "machine/idectrl.h" #include "machine/bankdev.h" #include "machine/mc14411.h" -#include "bus/rs232/rs232.h" - class swtpc09_state : public driver_device @@ -36,18 +32,22 @@ public: , m_brg(*this, "brg") , m_pia(*this, "pia") , m_ptm(*this, "ptm") - , m_acia(*this, "acia") , m_fdc(*this, "fdc") , m_floppy0(*this, "fdc:0") , m_floppy1(*this, "fdc:1") , m_floppy2(*this, "fdc:2") , m_floppy3(*this, "fdc:3") , m_via(*this, "via") - , m_piaide(*this, "piaide") - , m_harddisk(*this, "harddisk") - , m_ide(*this, "ide") , m_dat(*this, "dat") , m_bankdev(*this, "bankdev") + , m_maincpu_clock(*this, "maincpu_clock") + , m_fdc_clock(*this, "fdc_clock") + , m_baud_rate_high(*this, "baud_rate_high") + , m_floppy_expected_density(*this, "floppy_expected_density") + , m_floppy_expected_sectors(*this, "floppy_expected_sectors") + , m_floppy_track_zero_expected_sectors(*this, "floppy_track_zero_expected_sectors") + , m_sbug_double_density(*this, "sbug_double_density") + , m_piaide_flex_boot_cd00(*this, "piaide_flex_boot_cd00") { } void swtpc09_base(machine_config &config); @@ -62,42 +62,46 @@ public: void init_swtpc09d3(); private: - DECLARE_FLOPPY_FORMATS(floppy_formats); + DECLARE_FLOPPY_FORMATS(floppy_flex_formats); + DECLARE_FLOPPY_FORMATS(floppy_uniflex_formats); DECLARE_READ8_MEMBER(pia0_a_r); DECLARE_READ8_MEMBER(pia0_ca1_r); DECLARE_WRITE_LINE_MEMBER( pia0_irq_a ); + DECLARE_WRITE_LINE_MEMBER(io_irq_w); + DECLARE_WRITE_LINE_MEMBER( ptm_o1_callback ); DECLARE_WRITE_LINE_MEMBER( ptm_o3_callback ); DECLARE_WRITE_LINE_MEMBER( ptm_irq ); - DECLARE_WRITE_LINE_MEMBER( acia_interrupt ); - DECLARE_WRITE_LINE_MEMBER( fdc_intrq_w ); DECLARE_WRITE_LINE_MEMBER( fdc_drq_w ); + DECLARE_WRITE_LINE_MEMBER( fdc_sso_w ); - DECLARE_READ8_MEMBER( dmf3_via_read_porta ); - DECLARE_READ8_MEMBER( dmf3_via_read_portb ); - DECLARE_WRITE8_MEMBER( dmf3_via_write_porta ); - DECLARE_WRITE_LINE_MEMBER( dmf3_via_irq ); + DECLARE_READ8_MEMBER( dmaf3_via_read_porta ); + DECLARE_READ8_MEMBER( dmaf3_via_read_portb ); + DECLARE_WRITE8_MEMBER( dmaf3_via_write_porta ); + DECLARE_WRITE_LINE_MEMBER( dmaf3_via_irq ); - DECLARE_READ8_MEMBER(piaide_a_r); - DECLARE_READ8_MEMBER(piaide_b_r); - DECLARE_WRITE8_MEMBER(piaide_a_w); - DECLARE_WRITE8_MEMBER(piaide_b_w); + TIMER_CALLBACK_MEMBER(floppy_motor_callback); - DECLARE_READ8_MEMBER ( dmf2_dma_address_reg_r ); - DECLARE_WRITE8_MEMBER ( dmf2_dma_address_reg_w ); - DECLARE_READ8_MEMBER ( dmf2_control_reg_r ); - DECLARE_WRITE8_MEMBER ( dmf2_control_reg_w ); + DECLARE_READ8_MEMBER( dmaf2_fdc_r ); + DECLARE_WRITE8_MEMBER( dmaf2_fdc_w ); + DECLARE_READ8_MEMBER ( dmaf2_dma_address_reg_r ); + DECLARE_WRITE8_MEMBER ( dmaf2_dma_address_reg_w ); + DECLARE_READ8_MEMBER ( dmaf2_control_reg_r ); + DECLARE_WRITE8_MEMBER ( dmaf2_control_reg_w ); - DECLARE_READ8_MEMBER ( dmf3_dma_address_reg_r ); - DECLARE_WRITE8_MEMBER ( dmf3_dma_address_reg_w ); - DECLARE_READ8_MEMBER ( dmf3_control_reg_r ); - DECLARE_WRITE8_MEMBER ( dmf3_control_reg_w ); + DECLARE_READ8_MEMBER( dmaf3_fdc_r ); + DECLARE_WRITE8_MEMBER( dmaf3_fdc_w ); + DECLARE_READ8_MEMBER ( dmaf3_dma_address_reg_r ); + DECLARE_WRITE8_MEMBER ( dmaf3_dma_address_reg_w ); + DECLARE_READ8_MEMBER ( dmaf3_control_reg_r ); + DECLARE_WRITE8_MEMBER ( dmaf3_control_reg_w ); - DECLARE_WRITE8_MEMBER ( dc4_control_reg_w ); + DECLARE_READ8_MEMBER( dmaf3_wd_r ); + DECLARE_WRITE8_MEMBER( dmaf3_wd_w ); DECLARE_WRITE8_MEMBER(dat_w); DECLARE_READ8_MEMBER(main_r); @@ -106,44 +110,63 @@ private: DECLARE_READ8_MEMBER ( m6844_r ); DECLARE_WRITE8_MEMBER ( m6844_w ); - void flex_dc4_piaide_mem(address_map &map); - void flex_dmf2_mem(address_map &map); + DECLARE_READ8_MEMBER ( unmapped_r ); + DECLARE_WRITE8_MEMBER ( unmapped_w ); + + void flex_dc5_piaide_mem(address_map &map); + void flex_dmaf2_mem(address_map &map); void mp09_mem(address_map &map); - void uniflex_dmf2_mem(address_map &map); - void uniflex_dmf3_mem(address_map &map); + void uniflex_dmaf2_mem(address_map &map); + void uniflex_dmaf3_mem(address_map &map); virtual void machine_start() override; + virtual void machine_reset() override; void swtpc09_fdc_dma_transfer(); void swtpc09_irq_handler(uint8_t peripheral, uint8_t state); + void floppy_motor_trigger(); + + void validate_floppy_side(uint8_t cmd); + uint8_t validate_fdc_sector_size(uint8_t cmd); + uint8_t validate_fdc_dden(uint8_t dden); + offs_t dat_translate(offs_t offset) const; required_device<mc6809_device> m_maincpu; required_device<mc14411_device> m_brg; required_device<pia6821_device> m_pia; required_device<ptm6840_device> m_ptm; - required_device<acia6850_device> m_acia; - required_device<fd1793_device> m_fdc; - required_device<floppy_connector> m_floppy0; - required_device<floppy_connector> m_floppy1; - required_device<floppy_connector> m_floppy2; - required_device<floppy_connector> m_floppy3; + + optional_device<fd1797_device> m_fdc; + optional_device<floppy_connector> m_floppy0; + optional_device<floppy_connector> m_floppy1; + optional_device<floppy_connector> m_floppy2; + optional_device<floppy_connector> m_floppy3; + optional_device<via6522_device> m_via; - optional_device<pia6821_device> m_piaide; - optional_device<device_t> m_harddisk; - optional_device<ide_controller_device> m_ide; required_shared_ptr<uint8_t> m_dat; required_device<address_map_bank_device> m_bankdev; + required_ioport m_maincpu_clock; + required_ioport m_fdc_clock; + required_ioport m_baud_rate_high; + required_ioport m_floppy_expected_density; + required_ioport m_floppy_expected_sectors; + required_ioport m_floppy_track_zero_expected_sectors; + required_ioport m_sbug_double_density; + required_ioport m_piaide_flex_boot_cd00; uint8_t m_pia_counter; // this is the counter on pia porta - uint8_t m_fdc_dma_address_reg; // dmf2 or dmf3 dma extended address reg + + uint8_t m_fdc_dma_address_reg; // dmaf2 or dmaf3 dma extended address reg uint8_t m_system_type; // flag to indicate hw and rom combination uint8_t m_fdc_status; // for floppy controller - uint8_t m_via_ca1_input; // dmf3 fdc interrupt is connected here - uint8_t m_dmf3_via_porta; - uint8_t m_piaide_porta; - uint8_t m_piaide_portb; + int m_floppy_motor_on; + emu_timer *m_floppy_motor_timer; + floppy_image_device *m_fdc_floppy; // Current selected floppy. + uint8_t m_fdc_side; // Current floppy side. + uint8_t m_via_ca1_input; // dmaf3 fdc interrupt is connected here + uint8_t m_dmaf3_via_porta; uint8_t m_active_interrupt; uint8_t m_interrupt; diff --git a/src/mame/machine/swtpc09.cpp b/src/mame/machine/swtpc09.cpp index 64ddd7703aa..2f6643e4878 100644 --- a/src/mame/machine/swtpc09.cpp +++ b/src/mame/machine/swtpc09.cpp @@ -1,5 +1,5 @@ // license:BSD-3-Clause -// copyright-holders:Robert Justice +// copyright-holders:Robert Justice,68bit /*************************************************************************** swtpc09 machine file Robert Justice ,2009-2014 @@ -10,21 +10,38 @@ #include "includes/swtpc09.h" #define DMAC_IRQ 0x01 // interrupt handler IDs -#define ACIA_IRQ 0x02 #define PTM_IRQ 0x04 #define PIA_IRQ 0x08 #define FDC_IRQ 0x10 #define VIA_IRQ 0x20 +#define IO_IRQ 0x40 -#define FLEX_DMF2 1 // system type flags -#define UNIFLEX_DMF2 2 -#define UNIFLEX_DMF3 3 -#define FLEX_DC4_PIAIDE 4 +#define FLEX_DMAF2 1 // system type flags +#define UNIFLEX_DMAF2 2 +#define UNIFLEX_DMAF3 3 +#define FLEX_DC5_PIAIDE 4 -#define VERBOSE 0 -#define LOG(x) do { if (VERBOSE) logerror x; } while (0) +READ8_MEMBER(swtpc09_state::unmapped_r) +{ + if (!machine().side_effects_disabled()) { + logerror("%s Unmapped read from addr %04x\n", machine().describe_context(), offset); + } + return 0; +} +WRITE8_MEMBER(swtpc09_state::unmapped_w) +{ + logerror("%s Unmapped write to addr %04x with data %02x\n", machine().describe_context(), offset, data); +} + +WRITE_LINE_MEMBER(swtpc09_state::io_irq_w) +{ + if (state) + swtpc09_irq_handler(IO_IRQ, ASSERT_LINE); + else + swtpc09_irq_handler(IO_IRQ, CLEAR_LINE); +} /******* MC6840 PTM on MPID Board *******/ @@ -72,70 +89,203 @@ WRITE_LINE_MEMBER( swtpc09_state::pia0_irq_a ) } -/******* MC6850 ACIA on MPS2 *******/ +/* Shared floppy support. */ -WRITE_LINE_MEMBER( swtpc09_state::acia_interrupt ) +void swtpc09_state::floppy_motor_trigger() { - if (state) + m_floppy0->get_device()->mon_w(CLEAR_LINE); + m_floppy1->get_device()->mon_w(CLEAR_LINE); + m_floppy2->get_device()->mon_w(CLEAR_LINE); + m_floppy3->get_device()->mon_w(CLEAR_LINE); + m_floppy_motor_timer->adjust(attotime::from_msec(30000)); + m_floppy_motor_on = 1; +} + +TIMER_CALLBACK_MEMBER(swtpc09_state::floppy_motor_callback) +{ + m_floppy0->get_device()->mon_w(ASSERT_LINE); + m_floppy1->get_device()->mon_w(ASSERT_LINE); + m_floppy2->get_device()->mon_w(ASSERT_LINE); + m_floppy3->get_device()->mon_w(ASSERT_LINE); + m_floppy_motor_on = 0; +} + +// Hack On a FDC command write, check that the floppy side is as expected +// given the track and sector. This check is performed for the type II and III +// commands. The floppy side is modified if necessary. +void swtpc09_state::validate_floppy_side(uint8_t cmd) +{ + if ((cmd & 0xe1) == 0x80 || (cmd & 0xe0) == 0xa0 || + (cmd & 0xf9) == 0xc0 || (cmd & 0xf9) == 0xe0 || + (cmd & 0xf9) == 0xf0) { - swtpc09_irq_handler(ACIA_IRQ, ASSERT_LINE); - logerror("swtpc09_acia_irq_assert\n"); + uint32_t expected_sectors = m_floppy_expected_sectors->read(); + uint32_t track_zero_expected_sectors = m_floppy_track_zero_expected_sectors->read(); + uint8_t sector = m_fdc->sector_r(); + uint8_t track = m_fdc->track_r(); + + if (track_zero_expected_sectors && track == 0) + { + uint8_t expected_side = sector > track_zero_expected_sectors ? 1 : 0; + + if (m_fdc_side != expected_side) + { + logerror("%s Unexpected size %d for track %d sector %d expected side %d\n", machine().describe_context(), m_fdc_side, track, sector, expected_side); + if (m_fdc_floppy) + { + m_fdc_floppy->ss_w(expected_side); + m_fdc_side = expected_side; + } + } + } + + if (expected_sectors) + { + uint8_t expected_side = sector > expected_sectors ? 1 : 0; + + if (m_fdc_side != expected_side) + { + logerror("%s Unexpected side %d for track %d sector %d expected side %d\n", machine().describe_context(), m_fdc_side, track, sector, expected_side); + if (m_fdc_floppy) + { + m_fdc_floppy->ss_w(expected_side); + m_fdc_side = expected_side; + } + } + } } - else +} + +// Note the dden line is low for double density. +uint8_t swtpc09_state::validate_fdc_dden(uint8_t dden) +{ + uint8_t expected_density = m_floppy_expected_density->read(); + switch (expected_density) { - swtpc09_irq_handler(ACIA_IRQ, CLEAR_LINE); - logerror("swtpc09_acia_irq_clear\n"); + case 1: + // Single density. + if (!dden) + logerror("%s Unexpected DDEN %d for single density\n", machine().describe_context(), dden); + return 1; + case 2: + { + // Double density with track zero single density. + uint8_t track = m_fdc->track_r(); + + if (track == 0) + { + if (!dden) + logerror("%s Unexpected DDEN %d for single density trak 0\n", machine().describe_context(), dden); + return 1; + } + if (dden) + logerror("%s Unexpected DDEN %d for double density\n", machine().describe_context(), dden); + return 0; + } + case 3: + // Pure double density. + if (dden) + logerror("%s Unexpected DDEN %d for double density\n", machine().describe_context(), dden); + return 0; + default: + return dden; } } +// The WD2797 supports an alternate interpretation of the sector size. Check +// that the flag is as expected and return the corrected command if necessary. +uint8_t swtpc09_state::validate_fdc_sector_size(uint8_t cmd) +{ + if ((cmd & 0xe1) == 0x80 || (cmd & 0xe0) == 0xa0) + { + // Check that the sector length flag is set as expected. + uint8_t sector_length_default = cmd & 0x08; + if (sector_length_default != 0x08) + { + logerror("%s Unexpected sector length default %02x\n", machine().describe_context(), sector_length_default); + // Patch the sector length flag. + cmd |= 0x08; + } + } + return cmd; +} + /*********************************************************************/ -/* DMF2 Floppy Controller Board */ +/* DMAF2 Floppy Controller Board */ /*********************************************************************/ -/* DMF2 dma extended address register */ -READ8_MEMBER ( swtpc09_state::dmf2_dma_address_reg_r ) +READ8_MEMBER( swtpc09_state::dmaf2_fdc_r ) +{ + // TODO Does access to the dmaf2 fdc also trigger the motor timer? + if (!machine().side_effects_disabled()) + floppy_motor_trigger(); + return m_fdc->fd1797_device::read(offset); +} + +WRITE8_MEMBER ( swtpc09_state::dmaf2_fdc_w ) +{ + // TODO Does access to the dmaf2 fdc also trigger the motor timer. + floppy_motor_trigger(); + + // TODO how does the DMAF2 use the FDC SSO output? + + if (offset == 0) { + validate_floppy_side(data); + data = validate_fdc_sector_size(data); + } + + m_fdc->fd1797_device::write(offset, data); +} + +/* DMAF2 dma extended address register */ +READ8_MEMBER ( swtpc09_state::dmaf2_dma_address_reg_r ) { return m_fdc_dma_address_reg; } -WRITE8_MEMBER ( swtpc09_state::dmf2_dma_address_reg_w ) +WRITE8_MEMBER ( swtpc09_state::dmaf2_dma_address_reg_w ) { m_fdc_dma_address_reg = data; - // bit 4 controls a gate enable/disable for DMF2 fdc irq line - if ((m_fdc_dma_address_reg & 0x10) && (m_system_type == UNIFLEX_DMF2 || m_system_type == FLEX_DMF2)) + // bit 4 controls a gate enable/disable for DMAF2 fdc irq line + if ((m_fdc_dma_address_reg & 0x10) && (m_system_type == UNIFLEX_DMAF2 || m_system_type == FLEX_DMAF2)) swtpc09_irq_handler(FDC_IRQ, CLEAR_LINE); //then clear the irq to cpu - - logerror("swtpc09_dmf2_dma_address_reg_w %02X\n", data); } -/* DMF2 fdc control register */ -READ8_MEMBER ( swtpc09_state::dmf2_control_reg_r ) +/* DMAF2 fdc control register */ +READ8_MEMBER ( swtpc09_state::dmaf2_control_reg_r ) { - //logerror("swtpc09_dmf2_control_reg_r $%02X\n", m_fdc_status); return m_fdc_status; } -WRITE8_MEMBER ( swtpc09_state::dmf2_control_reg_w ) +WRITE8_MEMBER ( swtpc09_state::dmaf2_control_reg_w ) { - logerror("swtpc09_dmf2_control_reg_w $%02X\n", data); - floppy_image_device *floppy = nullptr; + // TODO what to do if multiple drives are selected? + if (!BIT(data, 0) + !BIT(data, 1) + !BIT(data, 2) + !BIT(data, 3) > 1) + { + logerror("%s Unexpected DMAF2 has multiple drives selected: %d %d %d %d\n", machine().describe_context(), !BIT(data, 0), !BIT(data, 1), !BIT(data, 2), !BIT(data, 3)); + } + if (!BIT(data, 0)) floppy = m_floppy0->get_device(); if (!BIT(data, 1)) floppy = m_floppy1->get_device(); if (!BIT(data, 2)) floppy = m_floppy2->get_device(); if (!BIT(data, 3)) floppy = m_floppy3->get_device(); m_fdc->set_floppy(floppy); + m_fdc_floppy = floppy; if (floppy) { - floppy->mon_w(0); - floppy->ss_w(!BIT(data, 4)); + uint8_t side = !BIT(data, 4); + floppy->ss_w(side); + m_fdc_side = side; } - m_fdc->dden_w(!BIT(data, 5)); + uint8_t dden = !BIT(data, 5); + dden = validate_fdc_dden(dden); + m_fdc->dden_w(dden); } /* FDC controller dma transfer */ @@ -152,7 +302,6 @@ void swtpc09_state::swtpc09_fdc_dma_transfer() { uint8_t data = m_fdc->data_r(); - logerror("swtpc09_dma_write_mem %05X %02X\n", m_m6844_channel[0].address + offset, data); space.write_byte(m_m6844_channel[0].address + offset, data); } else @@ -160,7 +309,6 @@ void swtpc09_state::swtpc09_fdc_dma_transfer() uint8_t data = space.read_byte(m_m6844_channel[0].address + offset); m_fdc->data_w(data); - //logerror("swtpc09_dma_read_mem %04X %02X\n", m_m6844_channel[0].address, data); } m_m6844_channel[0].address++; @@ -182,8 +330,6 @@ void swtpc09_state::swtpc09_fdc_dma_transfer() /* common interrupt handler */ void swtpc09_state::swtpc09_irq_handler(uint8_t peripheral, uint8_t state) { - logerror("swtpc09_irq_handler peripheral:%02X state:%02X\n", peripheral, state); - switch (state) { case ASSERT_LINE: @@ -191,20 +337,18 @@ void swtpc09_state::swtpc09_irq_handler(uint8_t peripheral, uint8_t state) break; case CLEAR_LINE: - m_interrupt &= (~peripheral & 0x3f); + m_interrupt &= (~peripheral & 0x7f); break; } if (!m_active_interrupt && m_interrupt) //no active interrupt and it needs to be asserted { - m_maincpu->set_input_line(INPUT_LINE_IRQ0, ASSERT_LINE); + m_maincpu->set_input_line(M6809_IRQ_LINE, ASSERT_LINE); m_active_interrupt=true; - logerror("swtpc09_irq_assert %02X\n", peripheral); } else if (m_active_interrupt && !m_interrupt) //active interrupt and it needs to be cleared { - m_maincpu->set_input_line(INPUT_LINE_IRQ0, CLEAR_LINE); - logerror("swtpc09_irq_clear %02X\n", peripheral); + m_maincpu->set_input_line(M6809_IRQ_LINE, CLEAR_LINE); m_active_interrupt=false; } } @@ -212,54 +356,40 @@ void swtpc09_state::swtpc09_irq_handler(uint8_t peripheral, uint8_t state) /* handlers for fdc */ WRITE_LINE_MEMBER( swtpc09_state::fdc_intrq_w ) { - logerror("swtpc09_fdc_intrq_w %02X\n", state); - if ( m_system_type == UNIFLEX_DMF3 ) //IRQ from 1791 is connect into VIA ca2 + if ( m_system_type == UNIFLEX_DMAF3 ) //IRQ from 1791 is connect into VIA ca2 { if (state) { m_fdc_status |= 0x40; m_via->write_cb2(0); //fdc interrupt is connected to CA1 - m_dmf3_via_porta &= 0xfb; //clear pa3 - //m_via->write_porta(m_dmf3_via_porta); //and connected to PA3 + m_dmaf3_via_porta &= 0xfb; //clear pa3 + //m_via->write_porta(m_dmaf3_via_porta); //and connected to PA3 //swtpc09_irq_handler(FDC_IRQ, ASSERT_LINE); } else { m_fdc_status &= ~0x40; m_via->write_cb2(1); - m_dmf3_via_porta |= 0x04; //and connected to PA3 - //m_via->write_porta(m_dmf3_via_porta); //and connected to PA3 + m_dmaf3_via_porta |= 0x04; //and connected to PA3 + //m_via->write_porta(m_dmaf3_via_porta); //and connected to PA3 //swtpc09_irq_handler(FDC_IRQ, CLEAR_LINE); } } - else if ( m_system_type == FLEX_DC4_PIAIDE ) //for dc4 emulate irq jumper out + else //for dmaf2 it is connected directly to cpu via a gate { if (state) { m_fdc_status |= 0x40; - } - else - { - m_fdc_status &= ~0x40; - } - } - else //for dmf2 it is connected directly to cpu via a gate - { - if (state) - { - m_fdc_status |= 0x40; - if (!(m_fdc_dma_address_reg & 0x10)) // is dmf2 fdc irq enabled + if (!(m_fdc_dma_address_reg & 0x10)) // is dmaf2 fdc irq enabled { - logerror("swtpc09_fdc_int ** assert\n"); swtpc09_irq_handler(FDC_IRQ, ASSERT_LINE); } } else { m_fdc_status &= ~0x40; - if (!(m_fdc_dma_address_reg & 0x10)) // is dmf2 fdc irq enabled + if (!(m_fdc_dma_address_reg & 0x10)) // is dmaf2 fdc irq enabled { - logerror("swtpc09_fdc_int ** clear\n"); swtpc09_irq_handler(FDC_IRQ, CLEAR_LINE); } } @@ -268,55 +398,69 @@ WRITE_LINE_MEMBER( swtpc09_state::fdc_intrq_w ) WRITE_LINE_MEMBER( swtpc09_state::fdc_drq_w ) { - if (m_system_type == FLEX_DC4_PIAIDE) //for dc4 no dma + if (state) { - if (state) - { - m_fdc_status |= 0x80; - } - else - m_fdc_status &= 0x7f; + m_fdc_status |= 0x80; + swtpc09_fdc_dma_transfer(); } else - { - if (state) - { - m_fdc_status |= 0x80; - swtpc09_fdc_dma_transfer(); - } - else - m_fdc_status &= 0x7f; - } + m_fdc_status &= 0x7f; +} + +WRITE_LINE_MEMBER( swtpc09_state::fdc_sso_w ) +{ + // Doese the DMAF2 or DMAF3 use the SSO output? } /*********************************************************************/ -/* DMF3 Board */ +/* DMAF3 Board */ /*********************************************************************/ -/* via on dmf3 board */ -READ8_MEMBER( swtpc09_state::dmf3_via_read_porta ) +READ8_MEMBER( swtpc09_state::dmaf3_fdc_r ) { - return m_dmf3_via_porta; + // TODO Does access to the fdc also trigger the motor timer. + if (!machine().side_effects_disabled()) + floppy_motor_trigger(); + return m_fdc->fd1797_device::read(offset); +} + +WRITE8_MEMBER ( swtpc09_state::dmaf3_fdc_w ) +{ + // TODO Does access to the fdc also trigger the motor timer. + floppy_motor_trigger(); + + if (offset == 0) { + validate_floppy_side(data); + data = validate_fdc_sector_size(data); + } + + m_fdc->fd1797_device::write(offset, data); } -READ8_MEMBER( swtpc09_state::dmf3_via_read_portb ) +/* via on dmaf3 board */ +READ8_MEMBER( swtpc09_state::dmaf3_via_read_porta ) +{ + return m_dmaf3_via_porta; +} + +READ8_MEMBER( swtpc09_state::dmaf3_via_read_portb ) { return 0xff; } -WRITE8_MEMBER( swtpc09_state::dmf3_via_write_porta ) +WRITE8_MEMBER( swtpc09_state::dmaf3_via_write_porta ) { - m_dmf3_via_porta &= data; + m_dmaf3_via_porta &= data; } -//WRITE_LINE_MEMBER( swtpc09_state::dmf3_via_write_ca1 ) +//WRITE_LINE_MEMBER( swtpc09_state::dmaf3_via_write_ca1 ) //{ // return m_via_ca1_input; -// logerror("swtpc09_dmf3_via_write_ca1 %02X\n", state); +// logerror("swtpc09_dmaf3_via_write_ca1 %02X\n", state); //} -WRITE_LINE_MEMBER( swtpc09_state::dmf3_via_irq ) +WRITE_LINE_MEMBER( swtpc09_state::dmaf3_via_irq ) { if (state) swtpc09_irq_handler(VIA_IRQ, ASSERT_LINE); @@ -324,117 +468,64 @@ WRITE_LINE_MEMBER( swtpc09_state::dmf3_via_irq ) swtpc09_irq_handler(VIA_IRQ, CLEAR_LINE); } -/* DMF3 dma extended address register */ -READ8_MEMBER ( swtpc09_state::dmf3_dma_address_reg_r ) +/* DMAF3 dma extended address register */ +READ8_MEMBER ( swtpc09_state::dmaf3_dma_address_reg_r ) { return m_fdc_dma_address_reg; } -WRITE8_MEMBER ( swtpc09_state::dmf3_dma_address_reg_w ) +WRITE8_MEMBER ( swtpc09_state::dmaf3_dma_address_reg_w ) { m_fdc_dma_address_reg = data; - logerror("swtpc09_dmf3_dma_address_reg_w %02X\n", data); } -/* DMF3 fdc control register */ -READ8_MEMBER ( swtpc09_state::dmf3_control_reg_r ) +/* DMAF3 fdc control register */ +READ8_MEMBER ( swtpc09_state::dmaf3_control_reg_r ) { - //logerror("swtpc09_dmf3_control_reg_r $%02X\n", m_fdc_status); return m_fdc_status; } -WRITE8_MEMBER ( swtpc09_state::dmf3_control_reg_w ) +WRITE8_MEMBER ( swtpc09_state::dmaf3_control_reg_w ) { - logerror("swtpc09_dmf3_control_reg_w $%02X\n", data); - floppy_image_device *floppy = nullptr; - if (BIT(data, 0)) floppy = m_floppy0->get_device(); - if (BIT(data, 1)) floppy = m_floppy1->get_device(); - if (BIT(data, 2)) floppy = m_floppy2->get_device(); - if (BIT(data, 3)) floppy = m_floppy3->get_device(); - - m_fdc->set_floppy(floppy); - - if (floppy) + // TODO multiple selected? + if (BIT(data, 0) + BIT(data, 1) + BIT(data, 2) + BIT(data, 3) > 1) { - floppy->mon_w(0); - floppy->ss_w(BIT(data, 4)); + logerror("%s Unexpected DMAF3 has multiple drives selected: %d %d %d %d\n", machine().describe_context(), !BIT(data, 0), !BIT(data, 1), !BIT(data, 2), !BIT(data, 3)); } - m_fdc->dden_w(BIT(data, 5)); -} - -// DC4 drive select - -WRITE8_MEMBER ( swtpc09_state::dc4_control_reg_w ) -{ - logerror("swtpc09_dc4_control_reg_w $%02X\n", data); - - floppy_image_device *floppy = nullptr; - if (BIT(data, 0)) floppy = m_floppy0->get_device(); if (BIT(data, 1)) floppy = m_floppy1->get_device(); if (BIT(data, 2)) floppy = m_floppy2->get_device(); if (BIT(data, 3)) floppy = m_floppy3->get_device(); m_fdc->set_floppy(floppy); -} - + m_fdc_floppy = floppy; -/******* MC6821 PIA on IDE Board *******/ -/* Read/Write handlers for pia ide */ -/* TODO: update and finish this off */ + if (floppy) + { + uint8_t side = BIT(data, 4); + floppy->ss_w(side); + m_fdc_side = side; + } -READ8_MEMBER( swtpc09_state::piaide_a_r ) -{ - return m_piaide_porta; + uint8_t dden = BIT(data, 5); + dden = validate_fdc_dden(dden); + m_fdc->dden_w(dden); } -READ8_MEMBER( swtpc09_state::piaide_b_r ) -{ - return m_piaide_portb; -} +// DMAF3 WD1000 +// TODO. The following might help: +// http://www.bitsavers.org/pdf/westernDigital/WD100x/WD1000_OEM_Manual.pdf -WRITE8_MEMBER( swtpc09_state::piaide_a_w ) +READ8_MEMBER( swtpc09_state::dmaf3_wd_r ) { - m_piaide_porta = data; + return 0x00; } -WRITE8_MEMBER( swtpc09_state::piaide_b_w ) +WRITE8_MEMBER ( swtpc09_state::dmaf3_wd_w ) { - int tempidedata; - - m_piaide_portb = data; - - if ((data & 0x40)&&(!(data&0x20))) //cs0=0 cs1=1 bit 5&6 - { - if (!(data & 0x02)) //rd line bit 1 - { - tempidedata = m_ide->read_cs0((data&0x1c)>>2); - logerror("swtpc09_ide_bus_r: offset $%02X data %04X\n", (data&0x1c)>>2, tempidedata); - m_piaide_porta = tempidedata & 0x00ff; - } - else if (!(data & 0x01)) //wr line bit 0 - { - m_ide->write_cs0((data&0x1c)>>2, m_piaide_porta); - logerror("swtpc09_ide_bus_w: offset $%02X data %04X\n", (data&0x1c)>>2, m_piaide_porta); - } - } - else if ((data & 0x20)&&(!(data&0x40))) //cs0=1 cs1=0 bit 5&6 - { - if (!(data & 0x02)) //rd line bit 1 - { - tempidedata = m_ide->read_cs1((data&0x1c)>>2); - logerror("swtpc09_ide_bus_r: offset $%02X data %04X\n", (data&0x1c)>>2, tempidedata); - m_piaide_porta = tempidedata & 0x00ff; - } - else if (!(data & 0x01)) //wr line bit 0 - { - m_ide->write_cs1((data&0x1c)>>2, m_piaide_porta); - logerror("swtpc09_ide_bus_w: offset $%02X data %04X\n", (data&0x1c)>>2, m_piaide_porta); - } - } } @@ -451,12 +542,26 @@ offs_t swtpc09_state::dat_translate(offs_t offset) const READ8_MEMBER(swtpc09_state::main_r) { - return m_banked_space->read_byte(dat_translate(offset)); + if (offset < 0xff00) + { + return m_banked_space->read_byte(dat_translate(offset)); + } + else + { + return m_banked_space->read_byte(offset | 0xfff00); + } } WRITE8_MEMBER(swtpc09_state::main_w) { - m_banked_space->write_byte(dat_translate(offset), data); + if (offset < 0xff00) + { + m_banked_space->write_byte(dat_translate(offset), data); + } + else + { + m_banked_space->write_byte(offset | 0xfff00, data); + } } /* MC6844 DMA controller I/O */ @@ -465,7 +570,6 @@ READ8_MEMBER( swtpc09_state::m6844_r ) { uint8_t result = 0; - /* switch off the offset we were given */ switch (offset) { @@ -509,12 +613,14 @@ READ8_MEMBER( swtpc09_state::m6844_r ) result = m_m6844_channel[offset - 0x10].control; /* a read here clears the DMA end flag */ - m_m6844_channel[offset - 0x10].control &= ~0x80; - if (m_m6844_interrupt & 0x80) // if interrupt is active, then clear + if (!machine().side_effects_disabled()) { - swtpc09_irq_handler(0x01, CLEAR_LINE); - m_m6844_interrupt &= 0x7f; // clear interrupt indication bit 7 - logerror("swtpc09_6844_r interrupt cleared \n"); + m_m6844_channel[offset - 0x10].control &= ~0x80; + if (m_m6844_interrupt & 0x80) // if interrupt is active, then clear + { + swtpc09_irq_handler(0x01, CLEAR_LINE); + m_m6844_interrupt &= 0x7f; // clear interrupt indication bit 7 + } } break; @@ -536,9 +642,8 @@ READ8_MEMBER( swtpc09_state::m6844_r ) /* 0x17-0x1f not used */ default: break; } - //logerror("swtpc09_6844_r %02X %02X\n", offset, result & 0xff); - if (m_system_type == UNIFLEX_DMF2 || m_system_type == FLEX_DMF2) // if DMF2 controller data bus is inverted to 6844 + if (m_system_type == UNIFLEX_DMAF2 || m_system_type == FLEX_DMAF2) // if DMAF2 controller data bus is inverted to 6844 { return ~result & 0xff; } @@ -553,10 +658,9 @@ WRITE8_MEMBER( swtpc09_state::m6844_w ) { int i; - if (m_system_type == UNIFLEX_DMF2 || m_system_type == FLEX_DMF2) // if DMF2 controller data bus is inverted to 6844 + if (m_system_type == UNIFLEX_DMAF2 || m_system_type == FLEX_DMAF2) // if DMAF2 controller data bus is inverted to 6844 data = ~data & 0xff; - logerror("swtpc09_6844_w %02X %02X\n", offset, data); /* switch off the offset we were given */ switch (offset) { @@ -612,7 +716,6 @@ WRITE8_MEMBER( swtpc09_state::m6844_w ) { /* mark us active */ m_m6844_channel[i].active = 1; - logerror("swtpc09_dma_channel active %02X\n", i); /* set the DMA busy bit and clear the DMA end bit */ m_m6844_channel[i].control |= 0x40; @@ -639,7 +742,6 @@ WRITE8_MEMBER( swtpc09_state::m6844_w ) /* interrupt control */ case 0x15: m_m6844_interrupt = (m_m6844_interrupt & 0x80) | (data & 0x7f); - logerror("swtpc09_m_m6844_interrupt_w %02X\n", m_m6844_interrupt); break; /* chaining control */ @@ -652,6 +754,51 @@ WRITE8_MEMBER( swtpc09_state::m6844_w ) } } +void swtpc09_state::machine_reset() +{ + uint32_t maincpu_clock = m_maincpu_clock->read(); + m_maincpu->set_clock(maincpu_clock * 4); + + if (m_system_type == FLEX_DMAF2 || + m_system_type == UNIFLEX_DMAF2 || + m_system_type == UNIFLEX_DMAF3) + { + uint32_t fdc_clock = m_fdc_clock->read(); + m_fdc->set_unscaled_clock(fdc_clock); + } + + // Divider select X64 is the default Low baud rate setting. A High + // baud rate setting is also available that selects a X16 divider, so + // gives rate four times as high. Note the schematic appears to have + // mislabeled the this setting. + uint8_t baud_rate_high = m_baud_rate_high->read(); + m_brg->rsa_w(baud_rate_high); + m_brg->rsb_w(1); + + // Note UNIBUG has a smarter boot loader in ROM and will toggle the + // density on failure so this is not necessary for UniFLEX. + if ((m_system_type == FLEX_DMAF2 || + m_system_type == FLEX_DC5_PIAIDE) && + m_sbug_double_density->read()) + { + // Patch the boot ROM to load the boot sector in double density. + uint8_t* sbug = memregion("bankdev")->base(); + sbug[0xffaf8] = 0xfe; // 'D' DMAF2 boot path + sbug[0xffb78] = 0xfe; + sbug[0xffbe1] = 0x8e; // 'U' mini boot path + } + + if (m_system_type == FLEX_DC5_PIAIDE && + m_piaide_flex_boot_cd00->read()) + { + // Patch the PIA-IDE boot rom to use IO1 + uint8_t* rom = memregion("bankdev")->base(); + + // Patch the FLEX entry point. + rom[0xfe979] = 0xcd; + rom[0xfe97a] = 0x00; + } +} void swtpc09_state::machine_start() { @@ -660,6 +807,14 @@ void swtpc09_state::machine_start() m_interrupt = 0; m_active_interrupt = false; + m_fdc_side = 0; + + // Start with the IRQ disabled? + m_fdc_dma_address_reg = 0x10; + + m_floppy_motor_timer = machine().scheduler().timer_alloc(timer_expired_delegate(FUNC(swtpc09_state::floppy_motor_callback),this)); + m_floppy_motor_on = 0; + // reset the 6844 for (int i = 0; i < 4; i++) { @@ -671,28 +826,25 @@ void swtpc09_state::machine_start() m_m6844_chain = 0x00; m_banked_space = &subdevice<address_map_bank_device>("bankdev")->space(AS_PROGRAM); - - m_brg->rsa_w(0); - m_brg->rsb_w(1); } void swtpc09_state::init_swtpc09() { - m_system_type = FLEX_DMF2; + m_system_type = FLEX_DMAF2; } void swtpc09_state::init_swtpc09i() { - m_system_type = FLEX_DC4_PIAIDE; + m_system_type = FLEX_DC5_PIAIDE; } void swtpc09_state::init_swtpc09u() { - m_system_type = UNIFLEX_DMF2; + m_system_type = UNIFLEX_DMAF2; } void swtpc09_state::init_swtpc09d3() { m_via_ca1_input = 0; - m_system_type = UNIFLEX_DMF3; + m_system_type = UNIFLEX_DMAF3; } |