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Diffstat (limited to 'src/mame/drivers/namcofl.cpp')
-rw-r--r--src/mame/drivers/namcofl.cpp77
1 files changed, 40 insertions, 37 deletions
diff --git a/src/mame/drivers/namcofl.cpp b/src/mame/drivers/namcofl.cpp
index 10927e5a7e1..a376a201612 100644
--- a/src/mame/drivers/namcofl.cpp
+++ b/src/mame/drivers/namcofl.cpp
@@ -214,25 +214,26 @@ WRITE8_MEMBER(namcofl_state::namcofl_c116_w)
}
}
-ADDRESS_MAP_START(namcofl_state::namcofl_mem)
- AM_RANGE(0x00000000, 0x000fffff) AM_RAMBANK("bank1")
- AM_RANGE(0x10000000, 0x100fffff) AM_RAMBANK("bank2")
- AM_RANGE(0x20000000, 0x201fffff) AM_ROM AM_REGION("data", 0)
- AM_RANGE(0x30000000, 0x30001fff) AM_RAM AM_SHARE("nvram") /* nvram */
- AM_RANGE(0x30100000, 0x30100003) AM_WRITE(namcofl_spritebank_w)
- AM_RANGE(0x30284000, 0x3028bfff) AM_RAM AM_SHARE("shareram")
- AM_RANGE(0x30300000, 0x30303fff) AM_RAM /* COMRAM */
- AM_RANGE(0x30380000, 0x303800ff) AM_READ(fl_network_r ) /* network registers */
- AM_RANGE(0x30400000, 0x30407fff) AM_DEVREAD8("c116", namco_c116_device,read,0xffffffff) AM_WRITE8(namcofl_c116_w,0xffffffff)
- AM_RANGE(0x30800000, 0x3080ffff) AM_READWRITE16(c123_tilemap_videoram_r,c123_tilemap_videoram_w,0xffffffff)
- AM_RANGE(0x30a00000, 0x30a0003f) AM_READWRITE16(c123_tilemap_control_r,c123_tilemap_control_w,0xffffffff)
- AM_RANGE(0x30c00000, 0x30c1ffff) AM_READWRITE16(c169_roz_videoram_r,c169_roz_videoram_w,0xffffffff) AM_SHARE("rozvideoram")
- AM_RANGE(0x30d00000, 0x30d0001f) AM_READWRITE16(c169_roz_control_r,c169_roz_control_w,0xffffffff)
- AM_RANGE(0x30e00000, 0x30e1ffff) AM_READWRITE16(c355_obj_ram_r,c355_obj_ram_w,0xffffffff) AM_SHARE("objram")
- AM_RANGE(0x30f00000, 0x30f0000f) AM_RAM /* NebulaM2 code says this is int enable at 0000, int request at 0004, but doesn't do much about it */
- AM_RANGE(0x40000000, 0x4000005f) AM_READWRITE(namcofl_sysreg_r, namcofl_sysreg_w )
- AM_RANGE(0xfffffffc, 0xffffffff) AM_READ(fl_unk1_r )
-ADDRESS_MAP_END
+void namcofl_state::namcofl_mem(address_map &map)
+{
+ map(0x00000000, 0x000fffff).bankrw("bank1");
+ map(0x10000000, 0x100fffff).bankrw("bank2");
+ map(0x20000000, 0x201fffff).rom().region("data", 0);
+ map(0x30000000, 0x30001fff).ram().share("nvram"); /* nvram */
+ map(0x30100000, 0x30100003).w(this, FUNC(namcofl_state::namcofl_spritebank_w));
+ map(0x30284000, 0x3028bfff).ram().share("shareram");
+ map(0x30300000, 0x30303fff).ram(); /* COMRAM */
+ map(0x30380000, 0x303800ff).r(this, FUNC(namcofl_state::fl_network_r)); /* network registers */
+ map(0x30400000, 0x30407fff).r(m_c116, FUNC(namco_c116_device::read)).w(this, FUNC(namcofl_state::namcofl_c116_w));
+ map(0x30800000, 0x3080ffff).rw(this, FUNC(namcofl_state::c123_tilemap_videoram_r), FUNC(namcofl_state::c123_tilemap_videoram_w));
+ map(0x30a00000, 0x30a0003f).rw(this, FUNC(namcofl_state::c123_tilemap_control_r), FUNC(namcofl_state::c123_tilemap_control_w));
+ map(0x30c00000, 0x30c1ffff).rw(this, FUNC(namcofl_state::c169_roz_videoram_r), FUNC(namcofl_state::c169_roz_videoram_w)).share("rozvideoram");
+ map(0x30d00000, 0x30d0001f).rw(this, FUNC(namcofl_state::c169_roz_control_r), FUNC(namcofl_state::c169_roz_control_w));
+ map(0x30e00000, 0x30e1ffff).rw(this, FUNC(namcofl_state::c355_obj_ram_r), FUNC(namcofl_state::c355_obj_ram_w)).share("objram");
+ map(0x30f00000, 0x30f0000f).ram(); /* NebulaM2 code says this is int enable at 0000, int request at 0004, but doesn't do much about it */
+ map(0x40000000, 0x4000005f).rw(this, FUNC(namcofl_state::namcofl_sysreg_r), FUNC(namcofl_state::namcofl_sysreg_w));
+ map(0xfffffffc, 0xffffffff).r(this, FUNC(namcofl_state::fl_unk1_r));
+}
WRITE16_MEMBER(namcofl_state::mcu_shared_w)
@@ -311,24 +312,26 @@ READ8_MEMBER(namcofl_state::dac2_r){ return 0xff; }
READ8_MEMBER(namcofl_state::dac1_r){ return 0xff; }
READ8_MEMBER(namcofl_state::dac0_r){ return 0xff; }
-ADDRESS_MAP_START(namcofl_state::namcoc75_am)
- AM_RANGE(0x002000, 0x002fff) AM_DEVREADWRITE("c352", c352_device, read, write)
- AM_RANGE(0x004000, 0x00bfff) AM_RAM_WRITE(mcu_shared_w) AM_SHARE("shareram")
- AM_RANGE(0x200000, 0x27ffff) AM_ROM AM_REGION("c75data", 0)
-ADDRESS_MAP_END
-
-ADDRESS_MAP_START(namcofl_state::namcoc75_io)
- AM_RANGE(M37710_PORT6, M37710_PORT6) AM_READWRITE(port6_r, port6_w)
- AM_RANGE(M37710_PORT7, M37710_PORT7) AM_READ(port7_r)
- AM_RANGE(M37710_ADC7_L, M37710_ADC7_L) AM_READ(dac7_r)
- AM_RANGE(M37710_ADC6_L, M37710_ADC6_L) AM_READ(dac6_r)
- AM_RANGE(M37710_ADC5_L, M37710_ADC5_L) AM_READ(dac5_r)
- AM_RANGE(M37710_ADC4_L, M37710_ADC4_L) AM_READ(dac4_r)
- AM_RANGE(M37710_ADC3_L, M37710_ADC3_L) AM_READ(dac3_r)
- AM_RANGE(M37710_ADC2_L, M37710_ADC2_L) AM_READ(dac2_r)
- AM_RANGE(M37710_ADC1_L, M37710_ADC1_L) AM_READ(dac1_r)
- AM_RANGE(M37710_ADC0_L, M37710_ADC0_L) AM_READ(dac0_r)
-ADDRESS_MAP_END
+void namcofl_state::namcoc75_am(address_map &map)
+{
+ map(0x002000, 0x002fff).rw("c352", FUNC(c352_device::read), FUNC(c352_device::write));
+ map(0x004000, 0x00bfff).ram().w(this, FUNC(namcofl_state::mcu_shared_w)).share("shareram");
+ map(0x200000, 0x27ffff).rom().region("c75data", 0);
+}
+
+void namcofl_state::namcoc75_io(address_map &map)
+{
+ map(M37710_PORT6, M37710_PORT6).rw(this, FUNC(namcofl_state::port6_r), FUNC(namcofl_state::port6_w));
+ map(M37710_PORT7, M37710_PORT7).r(this, FUNC(namcofl_state::port7_r));
+ map(M37710_ADC7_L, M37710_ADC7_L).r(this, FUNC(namcofl_state::dac7_r));
+ map(M37710_ADC6_L, M37710_ADC6_L).r(this, FUNC(namcofl_state::dac6_r));
+ map(M37710_ADC5_L, M37710_ADC5_L).r(this, FUNC(namcofl_state::dac5_r));
+ map(M37710_ADC4_L, M37710_ADC4_L).r(this, FUNC(namcofl_state::dac4_r));
+ map(M37710_ADC3_L, M37710_ADC3_L).r(this, FUNC(namcofl_state::dac3_r));
+ map(M37710_ADC2_L, M37710_ADC2_L).r(this, FUNC(namcofl_state::dac2_r));
+ map(M37710_ADC1_L, M37710_ADC1_L).r(this, FUNC(namcofl_state::dac1_r));
+ map(M37710_ADC0_L, M37710_ADC0_L).r(this, FUNC(namcofl_state::dac0_r));
+}
static INPUT_PORTS_START( speedrcr )