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Diffstat (limited to 'src/mame/drivers/bigevglf.cpp')
-rw-r--r--src/mame/drivers/bigevglf.cpp127
1 files changed, 66 insertions, 61 deletions
diff --git a/src/mame/drivers/bigevglf.cpp b/src/mame/drivers/bigevglf.cpp
index f0198bd7f03..e5fc7fc70c0 100644
--- a/src/mame/drivers/bigevglf.cpp
+++ b/src/mame/drivers/bigevglf.cpp
@@ -233,37 +233,40 @@ INPUT_PORTS_END
/*****************************************************************************/
/* Main CPU */
-ADDRESS_MAP_START(bigevglf_state::main_map)
- AM_RANGE(0x0000, 0xbfff) AM_ROM
- AM_RANGE(0xc000, 0xcfff) AM_RAM
- AM_RANGE(0xd000, 0xd7ff) AM_ROMBANK("bank1")
- AM_RANGE(0xd800, 0xdbff) AM_RAM AM_SHARE("share1") /* only half of the RAM is accessible, line a10 of IC73 (6116) is GNDed */
- AM_RANGE(0xe000, 0xe7ff) AM_WRITE(bigevglf_palette_w) AM_SHARE("paletteram")
- AM_RANGE(0xe800, 0xefff) AM_WRITEONLY AM_SHARE("spriteram1") /* sprite 'templates' */
- AM_RANGE(0xf000, 0xf0ff) AM_READWRITE(bigevglf_vidram_r, bigevglf_vidram_w) /* 41464 (64kB * 8 chips), addressed using ports 1 and 5 */
- AM_RANGE(0xf840, 0xf8ff) AM_RAM AM_SHARE("spriteram2") /* spriteram (x,y,offset in spriteram1,palette) */
-ADDRESS_MAP_END
-
-ADDRESS_MAP_START(bigevglf_state::bigevglf_portmap)
- ADDRESS_MAP_GLOBAL_MASK(0xff)
- AM_RANGE(0x00, 0x00) AM_WRITENOP /* video ram enable ???*/
- AM_RANGE(0x01, 0x01) AM_WRITE(bigevglf_gfxcontrol_w) /* plane select */
- AM_RANGE(0x02, 0x02) AM_WRITE(beg_banking_w)
- AM_RANGE(0x03, 0x03) AM_WRITE(beg13_a_set_w)
- AM_RANGE(0x04, 0x04) AM_WRITE(beg13_b_clr_w)
- AM_RANGE(0x05, 0x05) AM_WRITE(bigevglf_vidram_addr_w) /* video banking (256 banks) for f000-f0ff area */
- AM_RANGE(0x06, 0x06) AM_READ(beg_status_r)
-ADDRESS_MAP_END
+void bigevglf_state::main_map(address_map &map)
+{
+ map(0x0000, 0xbfff).rom();
+ map(0xc000, 0xcfff).ram();
+ map(0xd000, 0xd7ff).bankr("bank1");
+ map(0xd800, 0xdbff).ram().share("share1"); /* only half of the RAM is accessible, line a10 of IC73 (6116) is GNDed */
+ map(0xe000, 0xe7ff).w(this, FUNC(bigevglf_state::bigevglf_palette_w)).share("paletteram");
+ map(0xe800, 0xefff).writeonly().share("spriteram1"); /* sprite 'templates' */
+ map(0xf000, 0xf0ff).rw(this, FUNC(bigevglf_state::bigevglf_vidram_r), FUNC(bigevglf_state::bigevglf_vidram_w)); /* 41464 (64kB * 8 chips), addressed using ports 1 and 5 */
+ map(0xf840, 0xf8ff).ram().share("spriteram2"); /* spriteram (x,y,offset in spriteram1,palette) */
+}
+
+void bigevglf_state::bigevglf_portmap(address_map &map)
+{
+ map.global_mask(0xff);
+ map(0x00, 0x00).nopw(); /* video ram enable ???*/
+ map(0x01, 0x01).w(this, FUNC(bigevglf_state::bigevglf_gfxcontrol_w)); /* plane select */
+ map(0x02, 0x02).w(this, FUNC(bigevglf_state::beg_banking_w));
+ map(0x03, 0x03).w(this, FUNC(bigevglf_state::beg13_a_set_w));
+ map(0x04, 0x04).w(this, FUNC(bigevglf_state::beg13_b_clr_w));
+ map(0x05, 0x05).w(this, FUNC(bigevglf_state::bigevglf_vidram_addr_w)); /* video banking (256 banks) for f000-f0ff area */
+ map(0x06, 0x06).r(this, FUNC(bigevglf_state::beg_status_r));
+}
/*********************************************************************************/
/* Sub CPU */
-ADDRESS_MAP_START(bigevglf_state::sub_map)
- AM_RANGE(0x0000, 0x3fff) AM_ROM
- AM_RANGE(0x4000, 0x47ff) AM_RAM
- AM_RANGE(0x8000, 0x83ff) AM_RAM AM_SHARE("share1") /* shared with main CPU */
-ADDRESS_MAP_END
+void bigevglf_state::sub_map(address_map &map)
+{
+ map(0x0000, 0x3fff).rom();
+ map(0x4000, 0x47ff).ram();
+ map(0x8000, 0x83ff).ram().share("share1"); /* shared with main CPU */
+}
READ8_MEMBER(bigevglf_state::sub_cpu_mcu_coin_port_r)
@@ -282,26 +285,27 @@ READ8_MEMBER(bigevglf_state::sub_cpu_mcu_coin_port_r)
m_mcu_coin_bit5; /* bit 0 and bit 1 - coin inputs */
}
-ADDRESS_MAP_START(bigevglf_state::bigevglf_sub_portmap)
- ADDRESS_MAP_GLOBAL_MASK(0xff)
- AM_RANGE(0x00, 0x00) AM_READ_PORT("PORT00")
- AM_RANGE(0x01, 0x01) AM_READNOP
- AM_RANGE(0x02, 0x02) AM_READ(beg_trackball_x_r)
- AM_RANGE(0x03, 0x03) AM_READ(beg_trackball_y_r)
- AM_RANGE(0x04, 0x04) AM_READ(sub_cpu_mcu_coin_port_r)
- AM_RANGE(0x05, 0x05) AM_READ_PORT("DSW1")
- AM_RANGE(0x06, 0x06) AM_READ_PORT("DSW2")
- AM_RANGE(0x07, 0x07) AM_READNOP
- AM_RANGE(0x08, 0x08) AM_WRITE(beg_port08_w) /* muxed port select + other unknown stuff */
- AM_RANGE(0x0b, 0x0b) AM_DEVREAD("bmcu", taito68705_mcu_device, data_r)
- AM_RANGE(0x0c, 0x0c) AM_DEVWRITE("bmcu", taito68705_mcu_device, data_w)
- AM_RANGE(0x0e, 0x0e) AM_WRITENOP /* 0-enable MCU, 1-keep reset line ASSERTED; D0 goes to the input of ls74 and the /Q of this ls74 goes to reset line on 68705 */
- AM_RANGE(0x10, 0x17) AM_WRITE(beg13_a_clr_w)
- AM_RANGE(0x18, 0x1f) AM_WRITE(beg13_b_set_w)
- AM_RANGE(0x20, 0x20) AM_DEVREAD("soundlatch2", generic_latch_8_device, read)
- AM_RANGE(0x20, 0x20) AM_DEVWRITE("soundlatch1", generic_latch_8_device, write)
- AM_RANGE(0x21, 0x21) AM_READ(soundstate_r)
-ADDRESS_MAP_END
+void bigevglf_state::bigevglf_sub_portmap(address_map &map)
+{
+ map.global_mask(0xff);
+ map(0x00, 0x00).portr("PORT00");
+ map(0x01, 0x01).nopr();
+ map(0x02, 0x02).r(this, FUNC(bigevglf_state::beg_trackball_x_r));
+ map(0x03, 0x03).r(this, FUNC(bigevglf_state::beg_trackball_y_r));
+ map(0x04, 0x04).r(this, FUNC(bigevglf_state::sub_cpu_mcu_coin_port_r));
+ map(0x05, 0x05).portr("DSW1");
+ map(0x06, 0x06).portr("DSW2");
+ map(0x07, 0x07).nopr();
+ map(0x08, 0x08).w(this, FUNC(bigevglf_state::beg_port08_w)); /* muxed port select + other unknown stuff */
+ map(0x0b, 0x0b).r(m_bmcu, FUNC(taito68705_mcu_device::data_r));
+ map(0x0c, 0x0c).w(m_bmcu, FUNC(taito68705_mcu_device::data_w));
+ map(0x0e, 0x0e).nopw(); /* 0-enable MCU, 1-keep reset line ASSERTED; D0 goes to the input of ls74 and the /Q of this ls74 goes to reset line on 68705 */
+ map(0x10, 0x17).w(this, FUNC(bigevglf_state::beg13_a_clr_w));
+ map(0x18, 0x1f).w(this, FUNC(bigevglf_state::beg13_b_set_w));
+ map(0x20, 0x20).r("soundlatch2", FUNC(generic_latch_8_device::read));
+ map(0x20, 0x20).w("soundlatch1", FUNC(generic_latch_8_device::write));
+ map(0x21, 0x21).r(this, FUNC(bigevglf_state::soundstate_r));
+}
@@ -309,21 +313,22 @@ ADDRESS_MAP_END
/*********************************************************************************/
/* Sound CPU */
-ADDRESS_MAP_START(bigevglf_state::sound_map)
- AM_RANGE(0x0000, 0xbfff) AM_ROM
- AM_RANGE(0xc000, 0xc7ff) AM_RAM
- AM_RANGE(0xc800, 0xc801) AM_DEVWRITE("aysnd", ym2149_device, address_data_w)
- AM_RANGE(0xca00, 0xca0d) AM_DEVWRITE("msm", msm5232_device, write)
- AM_RANGE(0xcc00, 0xcc00) AM_WRITENOP
- AM_RANGE(0xce00, 0xce00) AM_WRITENOP
- AM_RANGE(0xd800, 0xd800) AM_DEVREAD("soundlatch1", generic_latch_8_device, read)
- AM_RANGE(0xd800, 0xd800) AM_DEVWRITE("soundlatch2", generic_latch_8_device, write) /* write to D800 sets bit 1 in status */
- AM_RANGE(0xda00, 0xda00) AM_READ(soundstate_r)
- AM_RANGE(0xda00, 0xda00) AM_DEVWRITE("soundnmi", input_merger_device, in_set<1>) // enable NMI
- AM_RANGE(0xdc00, 0xdc00) AM_DEVWRITE("soundnmi", input_merger_device, in_clear<1>) // disable NMI
- AM_RANGE(0xde00, 0xde00) AM_READNOP AM_DEVWRITE("dac", dac_byte_interface, write) /* signed 8-bit DAC & unknown read */
- AM_RANGE(0xe000, 0xefff) AM_READNOP /* space for diagnostics ROM */
-ADDRESS_MAP_END
+void bigevglf_state::sound_map(address_map &map)
+{
+ map(0x0000, 0xbfff).rom();
+ map(0xc000, 0xc7ff).ram();
+ map(0xc800, 0xc801).w("aysnd", FUNC(ym2149_device::address_data_w));
+ map(0xca00, 0xca0d).w(m_msm, FUNC(msm5232_device::write));
+ map(0xcc00, 0xcc00).nopw();
+ map(0xce00, 0xce00).nopw();
+ map(0xd800, 0xd800).r("soundlatch1", FUNC(generic_latch_8_device::read));
+ map(0xd800, 0xd800).w("soundlatch2", FUNC(generic_latch_8_device::write)); /* write to D800 sets bit 1 in status */
+ map(0xda00, 0xda00).r(this, FUNC(bigevglf_state::soundstate_r));
+ map(0xda00, 0xda00).w("soundnmi", FUNC(input_merger_device::in_set<1>)); // enable NMI
+ map(0xdc00, 0xdc00).w("soundnmi", FUNC(input_merger_device::in_clear<1>)); // disable NMI
+ map(0xde00, 0xde00).nopr().w("dac", FUNC(dac_byte_interface::write)); /* signed 8-bit DAC & unknown read */
+ map(0xe000, 0xefff).nopr(); /* space for diagnostics ROM */
+}