diff options
author | 2018-03-13 07:36:43 +0100 | |
---|---|---|
committer | 2018-03-14 14:07:14 +0100 | |
commit | 115bb9936c5cd3faf955d7eb1e251a94e4744b7b (patch) | |
tree | f0230f547f6c750f9974c61479eef28cbe4ad571 /src/mame/drivers/ddribble.cpp | |
parent | f155992daab88ad024cec995428a67108218b51d (diff) |
Address maps macros removal, pass 1 [O. Galibert]
Diffstat (limited to 'src/mame/drivers/ddribble.cpp')
-rw-r--r-- | src/mame/drivers/ddribble.cpp | 80 |
1 files changed, 42 insertions, 38 deletions
diff --git a/src/mame/drivers/ddribble.cpp b/src/mame/drivers/ddribble.cpp index d68fff3d3fb..4e090881c2e 100644 --- a/src/mame/drivers/ddribble.cpp +++ b/src/mame/drivers/ddribble.cpp @@ -108,44 +108,48 @@ WRITE8_MEMBER(ddribble_state::ddribble_vlm5030_ctrl_w) } -ADDRESS_MAP_START(ddribble_state::cpu0_map) - AM_RANGE(0x0000, 0x0004) AM_WRITE(K005885_0_w) /* video registers (005885 #1) */ - AM_RANGE(0x0800, 0x0804) AM_WRITE(K005885_1_w) /* video registers (005885 #2) */ - AM_RANGE(0x1800, 0x187f) AM_RAM_DEVWRITE("palette", palette_device, write_indirect) AM_SHARE("palette") /* palette */ - AM_RANGE(0x2000, 0x2fff) AM_RAM_WRITE(ddribble_fg_videoram_w) AM_SHARE("fg_videoram") /* Video RAM 1 */ - AM_RANGE(0x3000, 0x3fff) AM_RAM AM_SHARE("spriteram_1") /* Object RAM 1 */ - AM_RANGE(0x4000, 0x5fff) AM_RAM AM_SHARE("sharedram") /* shared RAM with CPU #1 */ - AM_RANGE(0x6000, 0x6fff) AM_RAM_WRITE(ddribble_bg_videoram_w) AM_SHARE("bg_videoram") /* Video RAM 2 */ - AM_RANGE(0x7000, 0x7fff) AM_RAM AM_SHARE("spriteram_2") /* Object RAM 2 */ - AM_RANGE(0x8000, 0x8000) AM_WRITE(ddribble_bankswitch_w) /* bankswitch control */ - AM_RANGE(0x8000, 0x9fff) AM_ROMBANK("bank1") /* banked ROM */ - AM_RANGE(0xa000, 0xffff) AM_ROM /* ROM */ -ADDRESS_MAP_END - -ADDRESS_MAP_START(ddribble_state::cpu1_map) - AM_RANGE(0x0000, 0x1fff) AM_READWRITE(ddribble_sharedram_r, ddribble_sharedram_w) /* shared RAM with CPU #0 */ - AM_RANGE(0x2000, 0x27ff) AM_READWRITE(ddribble_snd_sharedram_r, ddribble_snd_sharedram_w) /* shared RAM with CPU #2 */ - AM_RANGE(0x2800, 0x2800) AM_READ_PORT("DSW1") - AM_RANGE(0x2801, 0x2801) AM_READ_PORT("P1") - AM_RANGE(0x2802, 0x2802) AM_READ_PORT("P2") - AM_RANGE(0x2803, 0x2803) AM_READ_PORT("SYSTEM") /* coinsw & start */ - AM_RANGE(0x2c00, 0x2c00) AM_READ_PORT("DSW2") - AM_RANGE(0x3000, 0x3000) AM_READ_PORT("DSW3") - AM_RANGE(0x3400, 0x3400) AM_WRITE(ddribble_coin_counter_w) /* coin counters */ - AM_RANGE(0x3c00, 0x3c00) AM_DEVWRITE("watchdog", watchdog_timer_device, reset_w) /* watchdog reset */ - AM_RANGE(0x8000, 0xffff) AM_ROM /* ROM */ -ADDRESS_MAP_END - -ADDRESS_MAP_START(ddribble_state::cpu2_map) - AM_RANGE(0x0000, 0x07ff) AM_RAM AM_SHARE("snd_sharedram") /* shared RAM with CPU #1 */ - AM_RANGE(0x1000, 0x1001) AM_DEVREADWRITE("ymsnd", ym2203_device, read, write) /* YM2203 */ - AM_RANGE(0x3000, 0x3000) AM_DEVWRITE("vlm", vlm5030_device, data_w) /* Speech data */ - AM_RANGE(0x8000, 0xffff) AM_ROM /* ROM */ -ADDRESS_MAP_END - -ADDRESS_MAP_START(ddribble_state::vlm_map) - AM_RANGE(0x0000, 0xffff) AM_ROMBANK("vlmbank") -ADDRESS_MAP_END +void ddribble_state::cpu0_map(address_map &map) +{ + map(0x0000, 0x0004).w(this, FUNC(ddribble_state::K005885_0_w)); /* video registers (005885 #1) */ + map(0x0800, 0x0804).w(this, FUNC(ddribble_state::K005885_1_w)); /* video registers (005885 #2) */ + map(0x1800, 0x187f).ram().w("palette", FUNC(palette_device::write_indirect)).share("palette"); /* palette */ + map(0x2000, 0x2fff).ram().w(this, FUNC(ddribble_state::ddribble_fg_videoram_w)).share("fg_videoram"); /* Video RAM 1 */ + map(0x3000, 0x3fff).ram().share("spriteram_1"); /* Object RAM 1 */ + map(0x4000, 0x5fff).ram().share("sharedram"); /* shared RAM with CPU #1 */ + map(0x6000, 0x6fff).ram().w(this, FUNC(ddribble_state::ddribble_bg_videoram_w)).share("bg_videoram"); /* Video RAM 2 */ + map(0x7000, 0x7fff).ram().share("spriteram_2"); /* Object RAM 2 */ + map(0x8000, 0x8000).w(this, FUNC(ddribble_state::ddribble_bankswitch_w)); /* bankswitch control */ + map(0x8000, 0x9fff).bankr("bank1"); /* banked ROM */ + map(0xa000, 0xffff).rom(); /* ROM */ +} + +void ddribble_state::cpu1_map(address_map &map) +{ + map(0x0000, 0x1fff).rw(this, FUNC(ddribble_state::ddribble_sharedram_r), FUNC(ddribble_state::ddribble_sharedram_w)); /* shared RAM with CPU #0 */ + map(0x2000, 0x27ff).rw(this, FUNC(ddribble_state::ddribble_snd_sharedram_r), FUNC(ddribble_state::ddribble_snd_sharedram_w)); /* shared RAM with CPU #2 */ + map(0x2800, 0x2800).portr("DSW1"); + map(0x2801, 0x2801).portr("P1"); + map(0x2802, 0x2802).portr("P2"); + map(0x2803, 0x2803).portr("SYSTEM"); /* coinsw & start */ + map(0x2c00, 0x2c00).portr("DSW2"); + map(0x3000, 0x3000).portr("DSW3"); + map(0x3400, 0x3400).w(this, FUNC(ddribble_state::ddribble_coin_counter_w)); /* coin counters */ + map(0x3c00, 0x3c00).w("watchdog", FUNC(watchdog_timer_device::reset_w)); /* watchdog reset */ + map(0x8000, 0xffff).rom(); /* ROM */ +} + +void ddribble_state::cpu2_map(address_map &map) +{ + map(0x0000, 0x07ff).ram().share("snd_sharedram"); /* shared RAM with CPU #1 */ + map(0x1000, 0x1001).rw("ymsnd", FUNC(ym2203_device::read), FUNC(ym2203_device::write)); /* YM2203 */ + map(0x3000, 0x3000).w(m_vlm, FUNC(vlm5030_device::data_w)); /* Speech data */ + map(0x8000, 0xffff).rom(); /* ROM */ +} + +void ddribble_state::vlm_map(address_map &map) +{ + map(0x0000, 0xffff).bankr("vlmbank"); +} static INPUT_PORTS_START( ddribble ) PORT_START("P1") |