From fab82e4048d8f30c3a726a098fe0ff1c9e5be297 Mon Sep 17 00:00:00 2001 From: cracyc Date: Thu, 9 Jun 2022 12:58:39 -0500 Subject: pwrview: display and sio wip --- src/devices/cpu/i86/i186.cpp | 7 +++++++ src/devices/cpu/i86/i186.h | 2 ++ src/mame/drivers/pwrview.cpp | 44 +++++++++++++++++++++++++++++++------------- 3 files changed, 40 insertions(+), 13 deletions(-) diff --git a/src/devices/cpu/i86/i186.cpp b/src/devices/cpu/i86/i186.cpp index 477d53c3ad1..735421dba6c 100644 --- a/src/devices/cpu/i86/i186.cpp +++ b/src/devices/cpu/i86/i186.cpp @@ -152,6 +152,7 @@ i80186_cpu_device::i80186_cpu_device(const machine_config &mconfig, device_type , m_out_tmrout0_func(*this) , m_out_tmrout1_func(*this) , m_irmx_irq_cb(*this) + , m_irqa_cb(*this) , m_irmx_irq_ack(*this) { } @@ -724,6 +725,7 @@ void i80186_cpu_device::device_start() m_read_slave_ack_func.resolve_safe(0); m_out_chip_select_func.resolve_safe(); m_irmx_irq_cb.resolve_safe(); + m_irqa_cb.resolve_safe(); m_irmx_irq_ack.resolve(); } @@ -886,6 +888,11 @@ void i80186_cpu_device::write_word(uint32_t addr, uint16_t data) *************************************/ IRQ_CALLBACK_MEMBER(i80186_cpu_device::inta_callback) { + if (!m_irqa_cb.isnull()) // s-state 0 is irqack + { + m_irqa_cb(ASSERT_LINE); + m_irqa_cb(CLEAR_LINE); + } if (BIT(m_reloc, 14)) { if (!m_irmx_irq_ack.isnull()) diff --git a/src/devices/cpu/i86/i186.h b/src/devices/cpu/i86/i186.h index 47f258f74e4..481bc659161 100644 --- a/src/devices/cpu/i86/i186.h +++ b/src/devices/cpu/i86/i186.h @@ -21,6 +21,7 @@ public: auto tmrout0_handler() { return m_out_tmrout0_func.bind(); } auto tmrout1_handler() { return m_out_tmrout1_func.bind(); } auto irmx_irq_cb() { return m_irmx_irq_cb.bind(); } + auto irqa_cb() { return m_irqa_cb.bind(); } template void set_irmx_irq_ack(T &&... args) { m_irmx_irq_ack.set(std::forward(args)...); } IRQ_CALLBACK_MEMBER(int_callback); @@ -157,6 +158,7 @@ private: devcb_write_line m_out_tmrout0_func; devcb_write_line m_out_tmrout1_func; devcb_write_line m_irmx_irq_cb; + devcb_write_line m_irqa_cb; device_irq_acknowledge_delegate m_irmx_irq_ack; }; diff --git a/src/mame/drivers/pwrview.cpp b/src/mame/drivers/pwrview.cpp index 75a02aa778c..77648b5bb18 100644 --- a/src/mame/drivers/pwrview.cpp +++ b/src/mame/drivers/pwrview.cpp @@ -26,6 +26,7 @@ public: m_maincpu(*this, "maincpu"), m_pit(*this, "pit"), m_uart(*this, "uart"), + m_sio(*this, "sio"), m_bios(*this, "bios"), m_ram(*this, "ram"), m_biosbank(*this, "bios_bank"), @@ -58,9 +59,9 @@ private: void nmiio_w(offs_t offset, u16 data); void nmimem_w(offs_t offset, u16 data); u16 vram1_r(); - void vram1_w(u16 data); + void vram1_w(offs_t offset, u16 data, u16 mem_mask); u16 vram2_r(); - void vram2_w(u16 data); + void vram2_w(offs_t offset, u16 data, u16 mem_mask); u16 fbios_r(offs_t offset); u8 rotary_r(); u8 err_r(); @@ -74,6 +75,7 @@ private: required_device m_maincpu; required_device m_pit; required_device m_uart; + required_device m_sio; required_memory_region m_bios; required_shared_ptr m_ram; required_device m_biosbank; @@ -85,7 +87,7 @@ private: u8 m_c280; u8 m_c080; u8 m_errcode; - u8 m_vramwin[2]; + u16 m_vramwin[2]; bool m_dtr; bool m_rts; emu_timer *m_tmr0ext; @@ -131,7 +133,15 @@ TIMER_CALLBACK_MEMBER(pwrview_state::update_kbd) MC6845_UPDATE_ROW(pwrview_state::update_row) { - + for(int c = 0; c < x_count; c++) + { + for(int p = 0; p < 62; p++) + { + int x = c * 62 + p; + rgb_t pix = BIT(m_vram[(y * 64) + (x / 16)], x & 15) ? rgb_t::white() : rgb_t::black(); + bitmap.pix(y, x) = pix; + } + } } u8 pwrview_state::rotary_r() @@ -219,11 +229,11 @@ u16 pwrview_state::vram1_r() return m_vramwin[0]; } -void pwrview_state::vram1_w(u16 data) +void pwrview_state::vram1_w(offs_t offset, u16 data, u16 mem_mask) { data &= 0x3ff; - membank("vram1")->set_entry(data); - m_vramwin[0] = data; + COMBINE_DATA(&m_vramwin[0]); + membank("vram1")->set_entry(m_vramwin[0]); } u16 pwrview_state::vram2_r() @@ -231,11 +241,11 @@ u16 pwrview_state::vram2_r() return m_vramwin[1]; } -void pwrview_state::vram2_w(u16 data) +void pwrview_state::vram2_w(offs_t offset, u16 data, u16 mem_mask) { data &= 0x3ff; - membank("vram2")->set_entry(data); - m_vramwin[1] = data; + COMBINE_DATA(&m_vramwin[1]); + membank("vram2")->set_entry(m_vramwin[1]); } u8 pwrview_state::unk1_r() @@ -473,15 +483,21 @@ void pwrview_state::pwrview(machine_config &config) m_maincpu->set_addrmap(AS_PROGRAM, &pwrview_state::pwrview_map); m_maincpu->set_addrmap(AS_OPCODES, &pwrview_state::pwrview_fetch_map); m_maincpu->set_addrmap(AS_IO, &pwrview_state::pwrview_io); + m_maincpu->irqa_cb().set([this] (int state) { if(state) m_sio->m1_r(); }); screen_device &screen(SCREEN(config, "screen", SCREEN_TYPE_RASTER)); - screen.set_raw(XTAL(64'000'000)/8, 480, 0, 384, 1040, 0, 960); // clock unknown + screen.set_physical_aspect(3, 4); // Portrait CRT + screen.set_raw(XTAL(64'000'000)/8, 992, 0, 744, 1040, 0, 960); // clock unknown screen.set_screen_update("crtc", FUNC(hd6845s_device::screen_update)); PIT8253(config, m_pit, 0); m_pit->set_clk<0>(XTAL(16'000'000)/16); // clocks unknown, fix above when found m_pit->set_clk<1>(XTAL(16'000'000)/16); m_pit->set_clk<2>(XTAL(16'000'000)/16); + m_pit->out_handler<1>().set(m_sio, FUNC(z80sio_device::rxca_w)); + m_pit->out_handler<1>().append(m_sio, FUNC(z80sio_device::rxcb_w)); + m_pit->out_handler<1>().append(m_sio, FUNC(z80sio_device::txca_w)); + m_pit->out_handler<1>().append(m_sio, FUNC(z80sio_device::txcb_w)); // floppy disk controller UPD765A(config, "fdc", 8'000'000, true, true); // Rockwell R7675P @@ -496,11 +512,13 @@ void pwrview_state::pwrview(machine_config &config) m_uart->dtr_handler().set([this](bool state){ m_dtr = state; }); m_uart->rts_handler().set([this](bool state){ m_rts = state; }); - Z80SIO(config, "sio", 4000000); // Z8442BPS (SIO/2) + Z80SIO(config, m_sio, 4000000); // Z8442BPS (SIO/2) + m_sio->out_int_callback().set(m_maincpu, FUNC(i80186_cpu_device::int2_w)); hd6845s_device &crtc(HD6845S(config, "crtc", XTAL(64'000'000)/64)); // clock unknown - crtc.set_char_width(32); /* ? */ + crtc.set_char_width(62); crtc.set_update_row_callback(FUNC(pwrview_state::update_row)); + crtc.set_show_border_area(false); ADDRESS_MAP_BANK(config, "bios_bank").set_map(&pwrview_state::bios_bank).set_options(ENDIANNESS_LITTLE, 16, 17, 0x8000); } -- cgit v1.2.3