From f448fa7c54fdb20b6cb03b78172433db1d923793 Mon Sep 17 00:00:00 2001 From: arbee Date: Thu, 22 Dec 2016 23:02:20 -0500 Subject: i960: Preliminary support for CALLS instruction and WIP on FAULTx instructions. [R. Belmont] --- src/devices/cpu/i960/i960.cpp | 60 ++++++++++++++++++++++++++++++++++++++++ src/devices/cpu/i960/i960.h | 1 + src/devices/cpu/i960/i960dis.cpp | 2 +- 3 files changed, 62 insertions(+), 1 deletion(-) diff --git a/src/devices/cpu/i960/i960.cpp b/src/devices/cpu/i960/i960.cpp index 07e908ceb2b..83ebbe93797 100644 --- a/src/devices/cpu/i960/i960.cpp +++ b/src/devices/cpu/i960/i960.cpp @@ -368,6 +368,13 @@ void i960_cpu_device::bxx(uint32_t opcode, int mask) } } +void i960_cpu_device::fxx(uint32_t opcode, int mask) +{ + if(m_AC & mask) { + fatalerror("Taking the fault on a FAULT insn not yet supported\n"); + } +} + void i960_cpu_device::bxx_s(uint32_t opcode, int mask) { if(m_AC & mask) { @@ -650,6 +657,48 @@ void i960_cpu_device::execute_op(uint32_t opcode) m_icount--; bxx(opcode, 7); break; + + case 0x18: // faultno + m_icount--; + if(!(m_AC & 7)) { + m_IP += get_disp(opcode); + } + break; + + case 0x19: // faultg + m_icount--; + fxx(opcode, 1); + break; + + case 0x1a: // faulte + m_icount--; + fxx(opcode, 2); + break; + + case 0x1b: // faultge + m_icount--; + fxx(opcode, 3); + break; + + case 0x1c: // faultl + m_icount--; + fxx(opcode, 4); + break; + + case 0x1d: // faultne + m_icount--; + fxx(opcode, 5); + break; + + case 0x1e: // faultle + m_icount--; + fxx(opcode, 6); + break; + + case 0x1f: // faulto + m_icount--; + fxx(opcode, 7); + break; case 0x20: // testno m_icount--; @@ -1328,6 +1377,17 @@ void i960_cpu_device::execute_op(uint32_t opcode) case 0x66: switch((opcode >> 7) & 0xf) { + case 0x0: // calls + t1 = get_1_ri(opcode); + t2 = m_program->read_dword(m_SAT + 152); // get pointer to system procedure table + t2 = m_program->read_dword(t2 + 48 + (t1 * 4)); + if ((t2 & 3) != 0) + { + fatalerror("I960: system calls that jump into supervisor mode aren't yet supported\n"); + } + do_call(t2, 0, m_r[I960_SP]); + break; + case 0xd: // flushreg if (m_rcache_pos > 4) { diff --git a/src/devices/cpu/i960/i960.h b/src/devices/cpu/i960/i960.h index 12de144357c..64c1eb4cb98 100644 --- a/src/devices/cpu/i960/i960.h +++ b/src/devices/cpu/i960/i960.h @@ -161,6 +161,7 @@ private: void cmp_d(double v1, double v2); void bxx(uint32_t opcode, int mask); void bxx_s(uint32_t opcode, int mask); + void fxx(uint32_t opcode, int mask); void test(uint32_t opcode, int mask); void execute_op(uint32_t opcode); void take_interrupt(int vector, int lvl); diff --git a/src/devices/cpu/i960/i960dis.cpp b/src/devices/cpu/i960/i960dis.cpp index 4def96dad4d..43f81015240 100644 --- a/src/devices/cpu/i960/i960dis.cpp +++ b/src/devices/cpu/i960/i960dis.cpp @@ -22,7 +22,7 @@ static const mnemonic_t mnemonic[256] = { { "b", 8 }, { "call", 8 }, { "ret", 9 }, { "bal", 8 }, { "?", 0 }, { "?", 0 }, { "?", 0 }, { "?", 0 }, { "bno", 8 }, { "bg", 8 }, { "be", 8 }, { "bge", 8 }, { "bl", 8 }, { "bne", 8 }, { "ble", 8 }, { "bo", 8 }, // 10 - { "?", 0 }, { "?", 0 }, { "?", 0 }, { "?", 0 }, { "?", 0 }, { "?", 0 }, { "?", 0 }, { "?", 0 }, + { "faultno", 0 }, { "faultg", 0 }, { "faulte", 0 }, { "faultge", 0 }, { "faultl", 0 }, { "faultne", 0 }, { "faultle", 0 }, { "faulto", 0 }, { "testno", 10 }, { "testg", 10 }, { "teste", 10 }, { "testge", 10 }, { "testl", 10 }, { "testne", 10 }, { "testle", 10 }, { "testo", 10 }, // 20 { "?", 0 }, { "?", 0 }, { "?", 0 }, { "?", 0 }, { "?", 0 }, { "?", 0 }, { "?", 0 }, { "?", 0 }, -- cgit v1.2.3