From e652bc413e96a4581b49ffa5c92e5a373b23336c Mon Sep 17 00:00:00 2001 From: Olivier Galibert Date: Sun, 28 May 2023 20:32:33 +0200 Subject: h8: m_ify --- src/devices/cpu/h8/gt913.cpp | 62 +- src/devices/cpu/h8/gt913.h | 2 +- src/devices/cpu/h8/gt913.lst | 128 +- src/devices/cpu/h8/h8.cpp | 1059 +++++++------- src/devices/cpu/h8/h8.h | 76 +- src/devices/cpu/h8/h8.lst | 2650 ++++++++++++++++++------------------ src/devices/cpu/h8/h83002.cpp | 120 +- src/devices/cpu/h8/h83002.h | 60 +- src/devices/cpu/h8/h83003.cpp | 122 +- src/devices/cpu/h8/h83003.h | 66 +- src/devices/cpu/h8/h83006.cpp | 114 +- src/devices/cpu/h8/h83006.h | 52 +- src/devices/cpu/h8/h83008.cpp | 106 +- src/devices/cpu/h8/h83008.h | 48 +- src/devices/cpu/h8/h83032.cpp | 108 +- src/devices/cpu/h8/h83032.h | 48 +- src/devices/cpu/h8/h83042.cpp | 106 +- src/devices/cpu/h8/h83042.h | 48 +- src/devices/cpu/h8/h83048.cpp | 110 +- src/devices/cpu/h8/h83048.h | 54 +- src/devices/cpu/h8/h83337.cpp | 78 +- src/devices/cpu/h8/h83337.h | 42 +- src/devices/cpu/h8/h8_adc.cpp | 380 +++--- src/devices/cpu/h8/h8_adc.h | 26 +- src/devices/cpu/h8/h8_dma.cpp | 506 +++---- src/devices/cpu/h8/h8_dma.h | 52 +- src/devices/cpu/h8/h8_dtc.cpp | 190 +-- src/devices/cpu/h8/h8_dtc.h | 30 +- src/devices/cpu/h8/h8_intc.cpp | 183 ++- src/devices/cpu/h8/h8_intc.h | 28 +- src/devices/cpu/h8/h8_port.cpp | 66 +- src/devices/cpu/h8/h8_port.h | 16 +- src/devices/cpu/h8/h8_sci.cpp | 624 ++++----- src/devices/cpu/h8/h8_sci.h | 32 +- src/devices/cpu/h8/h8_timer16.cpp | 486 +++---- src/devices/cpu/h8/h8_timer16.h | 44 +- src/devices/cpu/h8/h8_timer8.cpp | 304 ++--- src/devices/cpu/h8/h8_timer8.h | 22 +- src/devices/cpu/h8/h8_watchdog.cpp | 86 +- src/devices/cpu/h8/h8_watchdog.h | 14 +- src/devices/cpu/h8/h8d.cpp | 32 +- src/devices/cpu/h8/h8d.h | 18 +- src/devices/cpu/h8/h8h.cpp | 4 +- src/devices/cpu/h8/h8h.h | 4 +- src/devices/cpu/h8/h8make.py | 42 +- src/devices/cpu/h8/h8s2000.cpp | 2 +- src/devices/cpu/h8/h8s2245.cpp | 142 +- src/devices/cpu/h8/h8s2245.h | 58 +- src/devices/cpu/h8/h8s2320.cpp | 156 +-- src/devices/cpu/h8/h8s2320.h | 78 +- src/devices/cpu/h8/h8s2357.cpp | 132 +- src/devices/cpu/h8/h8s2357.h | 62 +- src/devices/cpu/h8/h8s2600.cpp | 2 +- src/devices/cpu/h8/h8s2655.cpp | 170 +-- src/devices/cpu/h8/h8s2655.h | 60 +- 55 files changed, 4654 insertions(+), 4656 deletions(-) diff --git a/src/devices/cpu/h8/gt913.cpp b/src/devices/cpu/h8/gt913.cpp index ca2430a1f6f..b88e58fe56b 100644 --- a/src/devices/cpu/h8/gt913.cpp +++ b/src/devices/cpu/h8/gt913.cpp @@ -29,7 +29,7 @@ gt913_device::gt913_device(const machine_config &mconfig, const char *tag, devic h8_device(mconfig, GT913, tag, owner, clock, address_map_constructor(FUNC(gt913_device::map), this)), device_mixer_interface(mconfig, *this, 2), m_rom(*this, DEVICE_SELF), - data_config("data", ENDIANNESS_BIG, 16, 22, 0), + m_data_config("data", ENDIANNESS_BIG, 16, 22, 0), m_intc(*this, "intc"), m_sound(*this, "gt_sound"), m_kbd(*this, "kbd"), @@ -37,7 +37,7 @@ gt913_device::gt913_device(const machine_config &mconfig, const char *tag, devic m_sci(*this, "sci%u", 0), m_port(*this, "port%u", 1) { - has_hc = false; + m_has_hc = false; } std::unique_ptr gt913_device::create_disassembler() @@ -54,7 +54,7 @@ void gt913_device::map(address_map &map) /* ctk530 writes here to latch LED matrix data, which generates an active high strobe on pin 99 (PLE/P16) there's otherwise no external address decoding (or the usual read/write strobes) used for the LED latches. just treat as a 16-bit write-only port for now */ - map(0xe000, 0xe001).lw16(NAME([this](uint16_t data) { io.write_word(h8_device::PORT_4, data); })); + map(0xe000, 0xe001).lw16(NAME([this](uint16_t data) { m_io.write_word(h8_device::PORT_4, data); })); map(0xfac0, 0xffbf).ram(); @@ -105,13 +105,12 @@ void gt913_device::device_add_mconfig(machine_config &config) m_sound->add_route(1, *this, 1.0, AUTO_ALLOC_INPUT, 1); GT913_KBD_HLE(config, m_kbd, 0); - m_kbd->irq_cb().set([this] (int val) - { - if (val) - m_intc->internal_interrupt(5); - else - m_intc->clear_interrupt(5); - }); + m_kbd->irq_cb().set([this] (int val) { + if(val) + m_intc->internal_interrupt(5); + else + m_intc->clear_interrupt(5); + }); GT913_IO_HLE(config, m_io_hle, "intc", 6, 7); H8_SCI(config, m_sci[0], "intc", 8, 9, 10, 0); H8_SCI(config, m_sci[1], "intc", 11, 12, 13, 0); @@ -149,7 +148,7 @@ uint8_t gt913_device::uart_control_r(offs_t offset) void gt913_device::syscr_w(uint8_t data) { - if (BIT(m_syscr ^ data, 2)) + if(BIT(m_syscr ^ data, 2)) // NMI active edge has changed m_intc->set_input(INPUT_LINE_NMI, CLEAR_LINE); @@ -173,10 +172,10 @@ uint8_t gt913_device::data_r(offs_t offset) uint8_t gt913_device::read8ib(uint32_t adr) { - if (BIT(m_syscr, 0)) + if(BIT(m_syscr, 0)) // indirect bank disabled - return program.read_byte(adr); - else if ((IR[0] & 0x0070) == 0) + return m_program.read_byte(adr); + else if((m_IR[0] & 0x0070) == 0) // indirect bank enabled, using bankh for r0 return m_data.read_byte(adr | ((m_banknum >> 6) << 16)); else @@ -186,10 +185,10 @@ uint8_t gt913_device::read8ib(uint32_t adr) void gt913_device::write8ib(uint32_t adr, uint8_t data) { - if (BIT(m_syscr, 0)) + if(BIT(m_syscr, 0)) // indirect bank disabled - program.write_byte(adr, data); - else if ((IR[0] & 0x0070) == 0) + m_program.write_byte(adr, data); + else if((m_IR[0] & 0x0070) == 0) // indirect bank enabled, using bankh for r0 m_data.write_byte(adr | ((m_banknum >> 6) << 16), data); else @@ -201,10 +200,10 @@ uint16_t gt913_device::read16ib(uint32_t adr) { adr &= ~1; - if (BIT(m_syscr, 0)) + if(BIT(m_syscr, 0)) // indirect bank disabled - return program.read_word(adr); - else if ((IR[0] & 0x0070) == 0) + return m_program.read_word(adr); + else if((m_IR[0] & 0x0070) == 0) // indirect bank enabled, using bankh for r0 return m_data.read_word(adr | ((m_banknum >> 6) << 16)); else @@ -216,10 +215,10 @@ void gt913_device::write16ib(uint32_t adr, uint16_t data) { adr &= ~1; - if (BIT(m_syscr, 0)) + if(BIT(m_syscr, 0)) // indirect bank disabled - program.write_word(adr, data); - else if ((IR[0] & 0x0070) == 0) + m_program.write_word(adr, data); + else if((m_IR[0] & 0x0070) == 0) // indirect bank enabled, using bankh for r0 m_data.write_word(adr | ((m_banknum >> 6) << 16), data); else @@ -229,12 +228,12 @@ void gt913_device::write16ib(uint32_t adr, uint16_t data) void gt913_device::irq_setup() { - CCR |= F_H; + m_CCR |= F_H; } void gt913_device::update_irq_filter() { - if (CCR & F_H) + if(m_CCR & F_H) m_intc->set_filter(2, -1); else m_intc->set_filter(0, -1); @@ -242,7 +241,7 @@ void gt913_device::update_irq_filter() void gt913_device::interrupt_taken() { - standard_irq_callback(m_intc->interrupt_taken(taken_irq_vector), NPC); + standard_irq_callback(m_intc->interrupt_taken(m_taken_irq_vector), m_NPC); } void gt913_device::internal_update(uint64_t current_time) @@ -257,9 +256,8 @@ void gt913_device::internal_update(uint64_t current_time) void gt913_device::execute_set_input(int inputnum, int state) { - if (inputnum == INPUT_LINE_NMI) - { - if (BIT(m_syscr, 2)) + if(inputnum == INPUT_LINE_NMI) { + if(BIT(m_syscr, 2)) state ^= ASSERT_LINE; } @@ -269,9 +267,9 @@ void gt913_device::execute_set_input(int inputnum, int state) device_memory_interface::space_config_vector gt913_device::memory_space_config() const { return space_config_vector{ - std::make_pair(AS_PROGRAM, &program_config), - std::make_pair(AS_IO, &io_config), - std::make_pair(AS_DATA, &data_config) + std::make_pair(AS_PROGRAM, &m_program_config), + std::make_pair(AS_IO, &m_io_config), + std::make_pair(AS_DATA, &m_data_config) }; } diff --git a/src/devices/cpu/h8/gt913.h b/src/devices/cpu/h8/gt913.h index 4ba89661abb..ce278fcefb6 100644 --- a/src/devices/cpu/h8/gt913.h +++ b/src/devices/cpu/h8/gt913.h @@ -79,7 +79,7 @@ protected: required_memory_region m_rom; - address_space_config data_config; + address_space_config m_data_config; memory_access<32, 1, 0, ENDIANNESS_BIG>::specific m_data; uint16_t m_banknum; uint8_t m_syscr; diff --git a/src/devices/cpu/h8/gt913.lst b/src/devices/cpu/h8/gt913.lst index 9489496c0cf..6587d86babc 100644 --- a/src/devices/cpu/h8/gt913.lst +++ b/src/devices/cpu/h8/gt913.lst @@ -2,9 +2,9 @@ # copyright-holders:Olivier Galibert, Devin Acker macro prefetch_start - NPC = PC & 0xffffff; - PIR = read16i(PC); - PC += 2; + m_NPC = m_PC & 0xffffff; + m_PIR = read16i(m_PC); + m_PC += 2; macro prefetch prefetch_start @@ -23,13 +23,13 @@ macro prefetch_noirq 0340 fff0 0 ldc r8l ccr 0380 fff0 0 ldbank r8l bankl g - TMP1 = r8_r(IR[0]) & 0x3f; - m_banknum = (m_banknum & 0xffc0) | TMP1; + m_TMP1 = r8_r(m_IR[0]) & 0x3f; + m_banknum = (m_banknum & 0xffc0) | m_TMP1; prefetch 03c0 fff0 0 ldbank r8l bankh g - TMP1 = r8_r(IR[0]) & 0x3f; - m_banknum = (TMP1 << 6) | (m_banknum & 0x3f); + m_TMP1 = r8_r(m_IR[0]) & 0x3f; + m_banknum = (m_TMP1 << 6) | (m_banknum & 0x3f); prefetch 0400 ff00 0 orc imm8 ccr @@ -37,16 +37,16 @@ macro prefetch_noirq 0600 ff00 0 andc imm8 ccr 0740 ffc0 0 ldc imm6l ccr g - CCR = IR[0] & 0x3f; + m_CCR = m_IR[0] & 0x3f; update_irq_filter(); prefetch_noirq 0780 ffc0 0 ldbank imm6l bankl g - m_banknum = (m_banknum & 0xffc0) | (IR[0] & 0x3f); + m_banknum = (m_banknum & 0xffc0) | (m_IR[0] & 0x3f); prefetch 07c0 ffc0 0 ldbank imm6l bankh g - m_banknum = ((IR[0] & 0x3f) << 6) | (m_banknum & 0x3f); + m_banknum = ((m_IR[0] & 0x3f) << 6) | (m_banknum & 0x3f); prefetch 0800 ff00 0 add.b r8h r8l @@ -125,8 +125,8 @@ macro prefetch_noirq # (the NMI from the power switch will get things going afterwards). 5b80 ffc0 0 jmp abs22e - g internal(1); - m_banknum = ((IR[0] & 0x3f) << 2) | (IR[1] >> 14); - PC = 0x8000 | (IR[1] & 0x3fff); + m_banknum = ((m_IR[0] & 0x3f) << 2) | (m_IR[1] >> 14); + m_PC = 0x8000 | (m_IR[1] & 0x3fff); prefetch 5c00 ff8f 0 jsr r16h - @@ -146,39 +146,39 @@ macro prefetch_noirq 6800 ff80 0 mov.b r16ih r8l g prefetch_start internal(1); - TMP1 = read8ib(r16_r(IR[0] >> 4)); - set_nzv8(TMP1); - r8_w(IR[0], TMP1); + m_TMP1 = read8ib(r16_r(m_IR[0] >> 4)); + set_nzv8(m_TMP1); + r8_w(m_IR[0], m_TMP1); prefetch_done(); 6900 ff88 0 mov.w r16ih r16l g prefetch_start internal(1); - TMP1 = read16ib(r16_r(IR[0] >> 4)); - set_nzv16(TMP1); - r16_w(IR[0], TMP1); + m_TMP1 = read16ib(r16_r(m_IR[0] >> 4)); + set_nzv16(m_TMP1); + r16_w(m_IR[0], m_TMP1); prefetch_done(); 6a00 ff80 0 mov.b r16ph r8l g - TMP2 = r16_r(IR[0] >> 4); + m_TMP2 = r16_r(m_IR[0] >> 4); prefetch_start internal(2); - TMP1 = read8ib(TMP2); - TMP2 += 1; - r16_w(IR[0] >> 4, TMP2); - set_nzv8(TMP1); - r8_w(IR[0], TMP1); + m_TMP1 = read8ib(m_TMP2); + m_TMP2 += 1; + r16_w(m_IR[0] >> 4, m_TMP2); + set_nzv8(m_TMP1); + r8_w(m_IR[0], m_TMP1); prefetch_done(); 6b00 ff88 0 mov.w r16ph r16l g - TMP2 = r16_r(IR[0] >> 4); + m_TMP2 = r16_r(m_IR[0] >> 4); prefetch_start internal(2); - TMP1 = read16ib(TMP2); - TMP2 += 2; - r16_w(IR[0] >> 4, TMP2); - set_nzv16(TMP1); - r16_w(IR[0], TMP1); + m_TMP1 = read16ib(m_TMP2); + m_TMP2 += 2; + r16_w(m_IR[0] >> 4, m_TMP2); + set_nzv16(m_TMP1); + r16_w(m_IR[0], m_TMP1); prefetch_done(); 6c00 fff0 0 mov.b abs16 r8l @@ -186,20 +186,20 @@ macro prefetch_noirq 6e00 ff80 0 mov.b r16d16h r8l g prefetch_start - TMP1 = uint16_t(r16_r(IR[0] >> 4) + IR[1]); + m_TMP1 = uint16_t(r16_r(m_IR[0] >> 4) + m_IR[1]); internal(1); - TMP2 = read8ib(TMP1); - set_nzv8(TMP2); - r8_w(IR[0], TMP2); + m_TMP2 = read8ib(m_TMP1); + set_nzv8(m_TMP2); + r8_w(m_IR[0], m_TMP2); prefetch_done(); 6f00 ff80 0 mov.w r16d16h r16l g prefetch_start - TMP1 = uint16_t(r16_r(IR[0] >> 4) + IR[1]); + m_TMP1 = uint16_t(r16_r(m_IR[0] >> 4) + m_IR[1]); internal(1); - TMP2 = read16ib(TMP1); - set_nzv16(TMP2); - r16_w(IR[0], TMP2); + m_TMP2 = read16ib(m_TMP1); + set_nzv16(m_TMP2); + r16_w(m_IR[0], m_TMP2); prefetch_done(); 70000000 ff00ff8f 0 bset imm3 abs8 @@ -213,42 +213,42 @@ macro prefetch_noirq 7800 ff80 0 mov.b r8l r16ih g prefetch_start - TMP1 = r8_r(IR[0]); - set_nzv8(TMP1); + m_TMP1 = r8_r(m_IR[0]); + set_nzv8(m_TMP1); internal(1); - write8ib(r16_r(IR[0] >> 4), TMP1); + write8ib(r16_r(m_IR[0] >> 4), m_TMP1); prefetch_done(); 7900 ff88 0 mov.w r16l r16ih g prefetch_start - TMP1 = r16_r(IR[0]); - set_nzv16(TMP1); + m_TMP1 = r16_r(m_IR[0]); + set_nzv16(m_TMP1); internal(1); - write16ib(r16_r(IR[0] >> 4), TMP1); + write16ib(r16_r(m_IR[0] >> 4), m_TMP1); prefetch_done(); 7a00 ff80 0 mov.b r8l pr16h g - TMP1 = r8_r(IR[0]); - TMP2 = r16_r(IR[0] >> 4); + m_TMP1 = r8_r(m_IR[0]); + m_TMP2 = r16_r(m_IR[0] >> 4); prefetch_start internal(1); - TMP2 -= 1; - r16_w(IR[0] >> 4, TMP2); - set_nzv8(TMP1); + m_TMP2 -= 1; + r16_w(m_IR[0] >> 4, m_TMP2); + set_nzv8(m_TMP1); internal(1); - write8ib(TMP2, TMP1); + write8ib(m_TMP2, m_TMP1); prefetch_done(); 7b00 ff88 0 mov.w r16l pr16h g - TMP1 = r16_r(IR[0]); - TMP2 = r16_r(IR[0] >> 4); + m_TMP1 = r16_r(m_IR[0]); + m_TMP2 = r16_r(m_IR[0] >> 4); prefetch_start internal(1); - TMP2 -= 2; - r16_w(IR[0] >> 4, TMP2); - set_nzv16(TMP1); + m_TMP2 -= 2; + r16_w(m_IR[0] >> 4, m_TMP2); + set_nzv16(m_TMP1); internal(1); - write16ib(TMP2, TMP1); + write16ib(m_TMP2, m_TMP1); prefetch_done(); 7c00 fff0 0 mov.b r8l abs16 @@ -256,20 +256,20 @@ macro prefetch_noirq 7e00 ff80 0 mov.b r8l r16d16h g prefetch_start - TMP1 = uint16_t(r16_r(IR[0] >> 4) + IR[1]); - TMP2 = r8_r(IR[0]); - set_nzv8(TMP2); + m_TMP1 = uint16_t(r16_r(m_IR[0] >> 4) + m_IR[1]); + m_TMP2 = r8_r(m_IR[0]); + set_nzv8(m_TMP2); internal(1); - write8ib(TMP1, TMP2); + write8ib(m_TMP1, m_TMP2); prefetch_done(); 7f00 ff80 0 mov.w r16l r16d16h g prefetch_start - TMP1 = uint16_t(r16_r(IR[0] >> 4) + IR[1]); - TMP2 = r16_r(IR[0]); - set_nzv16(TMP2); + m_TMP1 = uint16_t(r16_r(m_IR[0] >> 4) + m_IR[1]); + m_TMP2 = r16_r(m_IR[0]); + set_nzv16(m_TMP2); internal(1); - write16ib(TMP1, TMP2); + write16ib(m_TMP1, m_TMP2); prefetch_done(); 8000 f000 0 add.b imm8 r8u diff --git a/src/devices/cpu/h8/h8.cpp b/src/devices/cpu/h8/h8.cpp index 32526652b1c..3cc5a687ee3 100644 --- a/src/devices/cpu/h8/h8.cpp +++ b/src/devices/cpu/h8/h8.cpp @@ -17,164 +17,165 @@ h8_device::h8_device(const machine_config &mconfig, device_type type, const char *tag, device_t *owner, uint32_t clock, address_map_constructor map_delegate) : cpu_device(mconfig, type, tag, owner, clock), - program_config("program", ENDIANNESS_BIG, 16, 16, 0, map_delegate), - io_config("io", ENDIANNESS_BIG, 16, 16, -1), PPC(0), NPC(0), PC(0), PIR(0), EXR(0), CCR(0), MAC(0), MACF(0), - TMP1(0), TMP2(0), TMPR(0), inst_state(0), inst_substate(0), icount(0), bcount(0), irq_vector(0), taken_irq_vector(0), irq_level(0), taken_irq_level(0), irq_required(false), irq_nmi(false) + m_program_config("program", ENDIANNESS_BIG, 16, 16, 0, map_delegate), + m_io_config("io", ENDIANNESS_BIG, 16, 16, -1), + m_PPC(0), m_NPC(0), m_PC(0), m_PIR(0), m_EXR(0), m_CCR(0), m_MAC(0), m_MACF(0), + m_TMP1(0), m_TMP2(0), m_TMPR(0), m_inst_state(0), m_inst_substate(0), m_icount(0), m_bcount(0), m_irq_vector(0), m_taken_irq_vector(0), m_irq_level(0), m_taken_irq_level(0), m_irq_required(false), m_irq_nmi(false) { - supports_advanced = false; - mode_advanced = false; - mode_a20 = false; - has_exr = false; - has_mac = false; - mac_saturating = false; - has_trace = false; - has_hc = true; + m_supports_advanced = false; + m_mode_advanced = false; + m_mode_a20 = false; + m_has_exr = false; + m_has_mac = false; + m_mac_saturating = false; + m_has_trace = false; + m_has_hc = true; } void h8_device::device_config_complete() { - uint8_t addrbits = mode_advanced ? (mode_a20 ? 20 : 24) : 16; - program_config.m_addr_width = program_config.m_logaddr_width = addrbits; + uint8_t addrbits = m_mode_advanced ? (m_mode_a20 ? 20 : 24) : 16; + m_program_config.m_addr_width = m_program_config.m_logaddr_width = addrbits; } void h8_device::device_start() { - space(AS_PROGRAM).cache(cache); - space(AS_PROGRAM).specific(program); - space(AS_IO).specific(io); + space(AS_PROGRAM).cache(m_cache); + space(AS_PROGRAM).specific(m_program); + space(AS_IO).specific(m_io); - uint32_t pcmask = mode_advanced ? 0xffffff : 0xffff; + uint32_t pcmask = m_mode_advanced ? 0xffffff : 0xffff; state_add(H8_PC, "PC", - [this]() { return NPC; }, - [this](uint32_t pc) { PC = PPC = NPC = pc; PIR = read16i(PC); PC += 2; prefetch_done_noirq_notrace(); } + [this]() { return m_NPC; }, + [this](uint32_t pc) { m_PC = m_PPC = m_NPC = pc; m_PIR = read16i(m_PC); m_PC += 2; prefetch_done_noirq_notrace(); } ).mask(pcmask); state_add(STATE_GENPC, "GENPC", - [this]() { return NPC; }, - [this](uint32_t pc) { PC = PPC = NPC = pc; PIR = read16i(PC); PC += 2; prefetch_done_noirq_notrace(); } + [this]() { return m_NPC; }, + [this](uint32_t pc) { m_PC = m_PPC = m_NPC = pc; m_PIR = read16i(m_PC); m_PC += 2; prefetch_done_noirq_notrace(); } ).mask(pcmask).noshow(); - state_add(STATE_GENPCBASE, "CURPC", PPC).mask(pcmask).noshow(); - state_add(H8_CCR, "CCR", CCR); - if(has_exr) - state_add(STATE_GENFLAGS, "GENFLAGS", CCR).formatstr("%11s").noshow(); + state_add(STATE_GENPCBASE, "CURPC", m_PPC).mask(pcmask).noshow(); + state_add(H8_CCR, "CCR", m_CCR); + if(m_has_exr) + state_add(STATE_GENFLAGS, "GENFLAGS", m_CCR).formatstr("%11s").noshow(); else - state_add(STATE_GENFLAGS, "GENFLAGS", CCR).formatstr("%8s").noshow(); - - if(has_exr) - state_add(H8_EXR, "EXR", EXR); - if(!supports_advanced) { - state_add(H8_R0, "R0", R[0]); - state_add(H8_R1, "R1", R[1]); - state_add(H8_R2, "R2", R[2]); - state_add(H8_R3, "R3", R[3]); - state_add(H8_R4, "R4", R[4]); - state_add(H8_R5, "R5", R[5]); - state_add(H8_R6, "R6", R[6]); - state_add(H8_R7, "R7", R[7]); + state_add(STATE_GENFLAGS, "GENFLAGS", m_CCR).formatstr("%8s").noshow(); + + if(m_has_exr) + state_add(H8_EXR, "EXR", m_EXR); + if(!m_supports_advanced) { + state_add(H8_R0, "R0", m_R[0]); + state_add(H8_R1, "R1", m_R[1]); + state_add(H8_R2, "R2", m_R[2]); + state_add(H8_R3, "R3", m_R[3]); + state_add(H8_R4, "R4", m_R[4]); + state_add(H8_R5, "R5", m_R[5]); + state_add(H8_R6, "R6", m_R[6]); + state_add(H8_R7, "R7", m_R[7]); } else { - state_add(H8_R0, "R0", R[0]).noshow(); - state_add(H8_R1, "R1", R[1]).noshow(); - state_add(H8_R2, "R2", R[2]).noshow(); - state_add(H8_R3, "R3", R[3]).noshow(); - state_add(H8_R4, "R4", R[4]).noshow(); - state_add(H8_R5, "R5", R[5]).noshow(); - state_add(H8_R6, "R6", R[6]).noshow(); - state_add(H8_R7, "R7", R[7]).noshow(); - state_add(H8_E0, "E0", R[8]).noshow(); - state_add(H8_E1, "E1", R[9]).noshow(); - state_add(H8_E2, "E2", R[10]).noshow(); - state_add(H8_E3, "E3", R[11]).noshow(); - state_add(H8_E4, "E4", R[12]).noshow(); - state_add(H8_E5, "E5", R[13]).noshow(); - state_add(H8_E6, "E6", R[14]).noshow(); - state_add(H8_E7, "E7", R[15]).noshow(); - state_add(H8_R0, "ER0", TMPR).callimport().callexport().formatstr("%9s"); - state_add(H8_R1, "ER1", TMPR).callimport().callexport().formatstr("%9s"); - state_add(H8_R2, "ER2", TMPR).callimport().callexport().formatstr("%9s"); - state_add(H8_R3, "ER3", TMPR).callimport().callexport().formatstr("%9s"); - state_add(H8_R4, "ER4", TMPR).callimport().callexport().formatstr("%9s"); - state_add(H8_R5, "ER5", TMPR).callimport().callexport().formatstr("%9s"); - state_add(H8_R6, "ER6", TMPR).callimport().callexport().formatstr("%9s"); - state_add(H8_R7, "ER7", TMPR).callimport().callexport().formatstr("%9s"); + state_add(H8_R0, "R0", m_R[0]).noshow(); + state_add(H8_R1, "R1", m_R[1]).noshow(); + state_add(H8_R2, "R2", m_R[2]).noshow(); + state_add(H8_R3, "R3", m_R[3]).noshow(); + state_add(H8_R4, "R4", m_R[4]).noshow(); + state_add(H8_R5, "R5", m_R[5]).noshow(); + state_add(H8_R6, "R6", m_R[6]).noshow(); + state_add(H8_R7, "R7", m_R[7]).noshow(); + state_add(H8_E0, "E0", m_R[8]).noshow(); + state_add(H8_E1, "E1", m_R[9]).noshow(); + state_add(H8_E2, "E2", m_R[10]).noshow(); + state_add(H8_E3, "E3", m_R[11]).noshow(); + state_add(H8_E4, "E4", m_R[12]).noshow(); + state_add(H8_E5, "E5", m_R[13]).noshow(); + state_add(H8_E6, "E6", m_R[14]).noshow(); + state_add(H8_E7, "E7", m_R[15]).noshow(); + state_add(H8_R0, "ER0", m_TMPR).callimport().callexport().formatstr("%9s"); + state_add(H8_R1, "ER1", m_TMPR).callimport().callexport().formatstr("%9s"); + state_add(H8_R2, "ER2", m_TMPR).callimport().callexport().formatstr("%9s"); + state_add(H8_R3, "ER3", m_TMPR).callimport().callexport().formatstr("%9s"); + state_add(H8_R4, "ER4", m_TMPR).callimport().callexport().formatstr("%9s"); + state_add(H8_R5, "ER5", m_TMPR).callimport().callexport().formatstr("%9s"); + state_add(H8_R6, "ER6", m_TMPR).callimport().callexport().formatstr("%9s"); + state_add(H8_R7, "ER7", m_TMPR).callimport().callexport().formatstr("%9s"); } - save_item(NAME(PPC)); - save_item(NAME(NPC)); - save_item(NAME(PC)); - save_item(NAME(PIR)); - save_item(NAME(IR)); - save_item(NAME(R)); - save_item(NAME(EXR)); - save_item(NAME(CCR)); - save_item(NAME(TMP1)); - save_item(NAME(TMP2)); - save_item(NAME(inst_state)); - save_item(NAME(inst_substate)); - save_item(NAME(irq_vector)); - save_item(NAME(taken_irq_vector)); - save_item(NAME(irq_level)); - save_item(NAME(taken_irq_level)); - save_item(NAME(irq_nmi)); - - set_icountptr(icount); - - PC = 0; - PPC = 0; - NPC = 0; - memset(IR, 0, sizeof(IR)); - memset(R, 0, sizeof(R)); - EXR = 0; - CCR = 0; - MAC = 0; - MACF = 0; - inst_state = STATE_RESET; - inst_substate = 0; - count_before_instruction_step = 0; - requested_state = -1; - dma_device = nullptr; - dtc_device = nullptr; + save_item(NAME(m_PPC)); + save_item(NAME(m_NPC)); + save_item(NAME(m_PC)); + save_item(NAME(m_PIR)); + save_item(NAME(m_IR)); + save_item(NAME(m_R)); + save_item(NAME(m_EXR)); + save_item(NAME(m_CCR)); + save_item(NAME(m_TMP1)); + save_item(NAME(m_TMP2)); + save_item(NAME(m_inst_state)); + save_item(NAME(m_inst_substate)); + save_item(NAME(m_irq_vector)); + save_item(NAME(m_taken_irq_vector)); + save_item(NAME(m_irq_level)); + save_item(NAME(m_taken_irq_level)); + save_item(NAME(m_irq_nmi)); + + set_icountptr(m_icount); + + m_PC = 0; + m_PPC = 0; + m_NPC = 0; + memset(m_IR, 0, sizeof(m_IR)); + memset(m_R, 0, sizeof(m_R)); + m_EXR = 0; + m_CCR = 0; + m_MAC = 0; + m_MACF = 0; + m_inst_state = STATE_RESET; + m_inst_substate = 0; + m_count_before_instruction_step = 0; + m_requested_state = -1; + m_dma_device = nullptr; + m_dtc_device = nullptr; } void h8_device::device_reset() { - inst_state = STATE_RESET; - inst_substate = 0; - count_before_instruction_step = 0; - requested_state = -1; + m_inst_state = STATE_RESET; + m_inst_substate = 0; + m_count_before_instruction_step = 0; + m_requested_state = -1; - irq_vector = 0; - irq_level = -1; - irq_nmi = false; - taken_irq_vector = 0; - taken_irq_level = -1; - current_dma = nullptr; - current_dtc = nullptr; + m_irq_vector = 0; + m_irq_level = -1; + m_irq_nmi = false; + m_taken_irq_vector = 0; + m_taken_irq_level = -1; + m_current_dma = nullptr; + m_current_dtc = nullptr; } bool h8_device::trigger_dma(int vector) { - return (dma_device && dma_device->trigger_dma(vector)) || (dtc_device && dtc_device->trigger_dtc(vector)); + return (m_dma_device && m_dma_device->trigger_dma(vector)) || (m_dtc_device && m_dtc_device->trigger_dtc(vector)); } void h8_device::set_current_dma(h8_dma_state *state) { - current_dma = state; + m_current_dma = state; if(!state) logerror("DMA done\n"); else { logerror("New current dma s=%x d=%x is=%d id=%d count=%x m=%d autoreq=%d\n", - state->source, state->dest, state->incs, state->incd, - state->count, state->mode_16 ? 16 : 8, state->autoreq); + state->m_source, state->m_dest, state->m_incs, state->m_incd, + state->m_count, state->m_mode_16 ? 16 : 8, state->m_autoreq); } } void h8_device::set_current_dtc(h8_dtc_state *state) { - current_dtc = state; + m_current_dtc = state; } void h8_device::request_state(int state) { - requested_state = state; + m_requested_state = state; } uint32_t h8_device::execute_min_cycles() const noexcept @@ -199,48 +200,48 @@ bool h8_device::execute_input_edge_triggered(int inputnum) const noexcept void h8_device::recompute_bcount(uint64_t event_time) { - if(!event_time || event_time >= total_cycles() + icount) { - bcount = 0; + if(!event_time || event_time >= total_cycles() + m_icount) { + m_bcount = 0; return; } - bcount = total_cycles() + icount - event_time; + m_bcount = total_cycles() + m_icount - event_time; } void h8_device::execute_run() { internal_update(total_cycles()); - icount -= count_before_instruction_step; - if(icount < 0) { - count_before_instruction_step = -icount; - icount = 0; + m_icount -= m_count_before_instruction_step; + if(m_icount < 0) { + m_count_before_instruction_step = -m_icount; + m_icount = 0; } else - count_before_instruction_step = 0; + m_count_before_instruction_step = 0; - while(bcount && icount <= bcount) - internal_update(total_cycles() + icount - bcount); + while(m_bcount && m_icount <= m_bcount) + internal_update(total_cycles() + m_icount - m_bcount); - if(icount > 0 && inst_substate) + if(m_icount > 0 && m_inst_substate) do_exec_partial(); - while(icount > 0) { - while(icount > bcount) { - if(inst_state < 0x10000) { - PPC = NPC; + while(m_icount > 0) { + while(m_icount > m_bcount) { + if(m_inst_state < 0x10000) { + m_PPC = m_NPC; if(machine().debug_flags & DEBUG_FLAG_ENABLED) - debugger_instruction_hook(NPC); + debugger_instruction_hook(m_NPC); } do_exec_full(); } - if(icount > 0) - while(bcount && icount <= bcount) - internal_update(total_cycles() + icount - bcount); - if(icount > 0 && inst_substate) + if(m_icount > 0) + while(m_bcount && m_icount <= m_bcount) + internal_update(total_cycles() + m_icount - m_bcount); + if(m_icount > 0 && m_inst_substate) do_exec_partial(); } - if(icount < 0) { - count_before_instruction_step = -icount; - icount = 0; + if(m_icount < 0) { + m_count_before_instruction_step = -m_icount; + m_icount = 0; } } @@ -260,8 +261,8 @@ void h8_device::internal_update() device_memory_interface::space_config_vector h8_device::memory_space_config() const { return space_config_vector { - std::make_pair(AS_PROGRAM, &program_config), - std::make_pair(AS_IO, &io_config) + std::make_pair(AS_PROGRAM, &m_program_config), + std::make_pair(AS_IO, &m_io_config) }; } @@ -278,8 +279,8 @@ void h8_device::state_import(const device_state_entry &entry) case H8_R6: case H8_R7: { int r = entry.index() - H8_R0; - R[r + 8] = TMPR >> 16; - R[r] = TMPR; + m_R[r + 8] = m_TMPR >> 16; + m_R[r] = m_TMPR; break; } } @@ -297,7 +298,7 @@ void h8_device::state_export(const device_state_entry &entry) case H8_R6: case H8_R7: { int r = entry.index() - H8_R0; - TMPR = (R[r + 8] << 16) | R[r]; + m_TMPR = (m_R[r + 8] << 16) | m_R[r]; break; } } @@ -307,38 +308,38 @@ void h8_device::state_string_export(const device_state_entry &entry, std::string { switch(entry.index()) { case STATE_GENFLAGS: - if(has_exr) + if(m_has_exr) str = string_format("%c%c %c%c%c%c%c%c%c%c", - (EXR & EXR_T) ? 'T' : '-', - '0' + (EXR & EXR_I), - (CCR & F_I) ? 'I' : '-', - (CCR & F_UI) ? 'u' : '-', - (CCR & F_H) ? 'H' : '-', - (CCR & F_U) ? 'U' : '-', - (CCR & F_N) ? 'N' : '-', - (CCR & F_Z) ? 'Z' : '-', - (CCR & F_V) ? 'V' : '-', - (CCR & F_C) ? 'C' : '-'); - else if(has_hc) + (m_EXR & EXR_T) ? 'T' : '-', + '0' + (m_EXR & EXR_I), + (m_CCR & F_I) ? 'I' : '-', + (m_CCR & F_UI) ? 'u' : '-', + (m_CCR & F_H) ? 'H' : '-', + (m_CCR & F_U) ? 'U' : '-', + (m_CCR & F_N) ? 'N' : '-', + (m_CCR & F_Z) ? 'Z' : '-', + (m_CCR & F_V) ? 'V' : '-', + (m_CCR & F_C) ? 'C' : '-'); + else if(m_has_hc) str = string_format("%c%c%c%c%c%c%c%c", - (CCR & F_I) ? 'I' : '-', - (CCR & F_UI) ? 'u' : '-', - (CCR & F_H) ? 'H' : '-', - (CCR & F_U) ? 'U' : '-', - (CCR & F_N) ? 'N' : '-', - (CCR & F_Z) ? 'Z' : '-', - (CCR & F_V) ? 'V' : '-', - (CCR & F_C) ? 'C' : '-'); + (m_CCR & F_I) ? 'I' : '-', + (m_CCR & F_UI) ? 'u' : '-', + (m_CCR & F_H) ? 'H' : '-', + (m_CCR & F_U) ? 'U' : '-', + (m_CCR & F_N) ? 'N' : '-', + (m_CCR & F_Z) ? 'Z' : '-', + (m_CCR & F_V) ? 'V' : '-', + (m_CCR & F_C) ? 'C' : '-'); else str = string_format("%c%c%c%c%c%c%c%c", - (CCR & F_I) ? '?' : '-', - (CCR & F_UI) ? 'u' : '-', - (CCR & F_H) ? 'I' : '-', - (CCR & F_U) ? 'U' : '-', - (CCR & F_N) ? 'N' : '-', - (CCR & F_Z) ? 'Z' : '-', - (CCR & F_V) ? 'V' : '-', - (CCR & F_C) ? 'C' : '-'); + (m_CCR & F_I) ? '?' : '-', + (m_CCR & F_UI) ? 'u' : '-', + (m_CCR & F_H) ? 'I' : '-', + (m_CCR & F_U) ? 'U' : '-', + (m_CCR & F_N) ? 'N' : '-', + (m_CCR & F_Z) ? 'Z' : '-', + (m_CCR & F_V) ? 'V' : '-', + (m_CCR & F_C) ? 'C' : '-'); break; case H8_R0: case H8_R1: @@ -349,7 +350,7 @@ void h8_device::state_string_export(const device_state_entry &entry, std::string case H8_R6: case H8_R7: { int r = entry.index() - H8_R0; - str = string_format("%04X %04X", R[r + 8], R[r]); + str = string_format("%04X %04X", m_R[r + 8], m_R[r]); break; } } @@ -357,32 +358,32 @@ void h8_device::state_string_export(const device_state_entry &entry, std::string uint16_t h8_device::read16i(uint32_t adr) { - icount--; - return cache.read_word(adr & ~1); + m_icount--; + return m_cache.read_word(adr & ~1); } uint8_t h8_device::read8(uint32_t adr) { - icount--; - return program.read_byte(adr); + m_icount--; + return m_program.read_byte(adr); } void h8_device::write8(uint32_t adr, uint8_t data) { - icount--; - program.write_byte(adr, data); + m_icount--; + m_program.write_byte(adr, data); } uint16_t h8_device::read16(uint32_t adr) { - icount--; - return program.read_word(adr & ~1); + m_icount--; + return m_program.read_word(adr & ~1); } void h8_device::write16(uint32_t adr, uint16_t data) { - icount--; - program.write_word(adr & ~1, data); + m_icount--; + m_program.write_word(adr & ~1, data); } bool h8_device::exr_in_stack() const @@ -392,52 +393,52 @@ bool h8_device::exr_in_stack() const void h8_device::prefetch_done() { - if(requested_state != -1) { - inst_state = requested_state; - requested_state = -1; - } else if(current_dma && !current_dma->suspended) - inst_state = STATE_DMA; - else if(current_dtc) - inst_state = STATE_DTC; - else if(irq_vector) { - inst_state = STATE_IRQ; - taken_irq_vector = irq_vector; - taken_irq_level = irq_level; - } else if(has_trace && (EXR & EXR_T) && exr_in_stack()) - inst_state = STATE_TRACE; + if(m_requested_state != -1) { + m_inst_state = m_requested_state; + m_requested_state = -1; + } else if(m_current_dma && !m_current_dma->m_suspended) + m_inst_state = STATE_DMA; + else if(m_current_dtc) + m_inst_state = STATE_DTC; + else if(m_irq_vector) { + m_inst_state = STATE_IRQ; + m_taken_irq_vector = m_irq_vector; + m_taken_irq_level = m_irq_level; + } else if(m_has_trace && (m_EXR & EXR_T) && exr_in_stack()) + m_inst_state = STATE_TRACE; else - inst_state = IR[0] = PIR; + m_inst_state = m_IR[0] = m_PIR; } void h8_device::prefetch_done_noirq() { - if(has_trace && (EXR & EXR_T) && exr_in_stack()) - inst_state = STATE_TRACE; + if(m_has_trace && (m_EXR & EXR_T) && exr_in_stack()) + m_inst_state = STATE_TRACE; else - inst_state = IR[0] = PIR; + m_inst_state = m_IR[0] = m_PIR; } void h8_device::prefetch_done_noirq_notrace() { - inst_state = IR[0] = PIR; + m_inst_state = m_IR[0] = m_PIR; } -void h8_device::set_irq(int _irq_vector, int _irq_level, bool _irq_nmi) +void h8_device::set_irq(int irq_vector, int irq_level, bool irq_nmi) { - irq_vector = _irq_vector; - irq_level = _irq_level; - irq_nmi = _irq_nmi; + m_irq_vector = irq_vector; + m_irq_level = irq_level; + m_irq_nmi = irq_nmi; } void h8_device::internal(int cycles) { - icount -= cycles; + m_icount -= cycles; } void h8_device::illegal() { - logerror("Illegal instruction at address %x\n", PPC); - icount = -10000000; + logerror("Illegal instruction at address %x\n", m_PPC); + m_icount = -10000000; } int h8_device::trace_setup() @@ -452,44 +453,44 @@ int h8_device::trapa_setup() uint8_t h8_device::do_addx8(uint8_t v1, uint8_t v2) { - uint16_t res = v1 + v2 + (CCR & F_C ? 1 : 0); - CCR &= ~(F_N|F_V|F_Z|F_C); - if (has_hc) + uint16_t res = v1 + v2 + (m_CCR & F_C ? 1 : 0); + m_CCR &= ~(F_N|F_V|F_Z|F_C); + if(m_has_hc) { - CCR &= ~F_H; - if(((v1 & 0xf) + (v2 & 0xf) + (CCR & F_C ? 1 : 0)) & 0x10) - CCR |= F_H; + m_CCR &= ~F_H; + if(((v1 & 0xf) + (v2 & 0xf) + (m_CCR & F_C ? 1 : 0)) & 0x10) + m_CCR |= F_H; } if(!uint8_t(res)) - CCR |= F_Z; + m_CCR |= F_Z; else if(int8_t(res) < 0) - CCR |= F_N; + m_CCR |= F_N; if(~(v1^v2) & (v1^res) & 0x80) - CCR |= F_V; + m_CCR |= F_V; if(res & 0x100) - CCR |= F_C; + m_CCR |= F_C; return res; } uint8_t h8_device::do_subx8(uint8_t v1, uint8_t v2) { - uint16_t res = v1 - v2 - (CCR & F_C ? 1 : 0); - CCR &= ~(F_N|F_V|F_C); - if (has_hc) + uint16_t res = v1 - v2 - (m_CCR & F_C ? 1 : 0); + m_CCR &= ~(F_N|F_V|F_C); + if(m_has_hc) { - CCR &= ~F_H; - if (((v1 & 0xf) - (v2 & 0xf) - (CCR & F_C ? 1 : 0)) & 0x10) - CCR |= F_H; + m_CCR &= ~F_H; + if(((v1 & 0xf) - (v2 & 0xf) - (m_CCR & F_C ? 1 : 0)) & 0x10) + m_CCR |= F_H; } if(uint8_t(res)) - CCR &= ~F_Z; + m_CCR &= ~F_Z; if(int8_t(res) < 0) - CCR |= F_N; + m_CCR |= F_N; if((v1^v2) & (v1^res) & 0x80) - CCR |= F_V; + m_CCR |= F_V; if(res & 0x100) - CCR |= F_C; + m_CCR |= F_C; return res; } @@ -497,60 +498,60 @@ uint8_t h8_device::do_subx8(uint8_t v1, uint8_t v2) uint8_t h8_device::do_inc8(uint8_t v1, uint8_t v2) { uint8_t res = v1 + v2; - CCR &= ~(F_N|F_V|F_Z); + m_CCR &= ~(F_N|F_V|F_Z); if(!res) - CCR |= F_Z; + m_CCR |= F_Z; else if(int8_t(res) < 0) - CCR |= F_N; + m_CCR |= F_N; if((v1^v2) & (v1^res) & 0x80) - CCR |= F_V; + m_CCR |= F_V; return res; } uint16_t h8_device::do_inc16(uint16_t v1, uint16_t v2) { uint16_t res = v1 + v2; - CCR &= ~(F_N|F_V|F_Z); + m_CCR &= ~(F_N|F_V|F_Z); if(!res) - CCR |= F_Z; + m_CCR |= F_Z; else if(int16_t(res) < 0) - CCR |= F_N; + m_CCR |= F_N; if((v1^v2) & (v1^res) & 0x8000) - CCR |= F_V; + m_CCR |= F_V; return res; } uint32_t h8_device::do_inc32(uint32_t v1, uint32_t v2) { uint32_t res = v1 + v2; - CCR &= ~(F_N|F_V|F_Z); + m_CCR &= ~(F_N|F_V|F_Z); if(!res) - CCR |= F_Z; + m_CCR |= F_Z; else if(int32_t(res) < 0) - CCR |= F_N; + m_CCR |= F_N; if((v1^v2) & (v1^res) & 0x80000000) - CCR |= F_V; + m_CCR |= F_V; return res; } uint8_t h8_device::do_add8(uint8_t v1, uint8_t v2) { uint16_t res = v1 + v2; - CCR &= ~(F_N|F_V|F_Z|F_C); - if (has_hc) + m_CCR &= ~(F_N|F_V|F_Z|F_C); + if(m_has_hc) { - CCR &= ~F_H; - if (((v1 & 0xf) + (v2 & 0xf)) & 0x10) - CCR |= F_H; + m_CCR &= ~F_H; + if(((v1 & 0xf) + (v2 & 0xf)) & 0x10) + m_CCR |= F_H; } if(!uint8_t(res)) - CCR |= F_Z; + m_CCR |= F_Z; else if(int8_t(res) < 0) - CCR |= F_N; + m_CCR |= F_N; if(~(v1^v2) & (v1^res) & 0x80) - CCR |= F_V; + m_CCR |= F_V; if(res & 0x100) - CCR |= F_C; + m_CCR |= F_C; return res; } @@ -558,21 +559,21 @@ uint8_t h8_device::do_add8(uint8_t v1, uint8_t v2) uint16_t h8_device::do_add16(uint16_t v1, uint16_t v2) { uint32_t res = v1 + v2; - CCR &= ~(F_N|F_V|F_Z|F_C); - if (has_hc) + m_CCR &= ~(F_N|F_V|F_Z|F_C); + if(m_has_hc) { - CCR &= ~F_H; - if (((v1 & 0xfff) + (v2 & 0xffff)) & 0x1000) - CCR |= F_H; + m_CCR &= ~F_H; + if(((v1 & 0xfff) + (v2 & 0xffff)) & 0x1000) + m_CCR |= F_H; } if(!uint16_t(res)) - CCR |= F_Z; + m_CCR |= F_Z; else if(int16_t(res) < 0) - CCR |= F_N; + m_CCR |= F_N; if(~(v1^v2) & (v1^res) & 0x8000) - CCR |= F_V; + m_CCR |= F_V; if(res & 0x10000) - CCR |= F_C; + m_CCR |= F_C; return res; } @@ -580,81 +581,81 @@ uint16_t h8_device::do_add16(uint16_t v1, uint16_t v2) uint32_t h8_device::do_add32(uint32_t v1, uint32_t v2) { uint64_t res = uint64_t(v1) + uint64_t(v2); - CCR &= ~(F_N|F_V|F_Z|F_C); - if (has_hc) + m_CCR &= ~(F_N|F_V|F_Z|F_C); + if(m_has_hc) { - CCR &= ~F_H; - if (((v1 & 0xfffffff) + (v2 & 0xfffffff)) & 0x10000000) - CCR |= F_H; + m_CCR &= ~F_H; + if(((v1 & 0xfffffff) + (v2 & 0xfffffff)) & 0x10000000) + m_CCR |= F_H; } if(!uint32_t(res)) - CCR |= F_Z; + m_CCR |= F_Z; else if(int32_t(res) < 0) - CCR |= F_N; + m_CCR |= F_N; if(~(v1^v2) & (v1^res) & 0x80000000) - CCR |= F_V; + m_CCR |= F_V; if(res & 0x100000000U) - CCR |= F_C; + m_CCR |= F_C; return res; } uint8_t h8_device::do_dec8(uint8_t v1, uint8_t v2) { uint8_t res = v1 - v2; - CCR &= ~(F_N|F_V|F_Z); + m_CCR &= ~(F_N|F_V|F_Z); if(!res) - CCR |= F_Z; + m_CCR |= F_Z; else if(int8_t(res) < 0) - CCR |= F_N; + m_CCR |= F_N; if((v1^v2) & (v1^res) & 0x80) - CCR |= F_V; + m_CCR |= F_V; return res; } uint16_t h8_device::do_dec16(uint16_t v1, uint16_t v2) { uint16_t res = v1 - v2; - CCR &= ~(F_N|F_V|F_Z); + m_CCR &= ~(F_N|F_V|F_Z); if(!res) - CCR |= F_Z; + m_CCR |= F_Z; else if(int16_t(res) < 0) - CCR |= F_N; + m_CCR |= F_N; if((v1^v2) & (v1^res) & 0x8000) - CCR |= F_V; + m_CCR |= F_V; return res; } uint32_t h8_device::do_dec32(uint32_t v1, uint32_t v2) { uint32_t res = v1 - v2; - CCR &= ~(F_N|F_V|F_Z); + m_CCR &= ~(F_N|F_V|F_Z); if(!res) - CCR |= F_Z; + m_CCR |= F_Z; else if(int32_t(res) < 0) - CCR |= F_N; + m_CCR |= F_N; if((v1^v2) & (v1^res) & 0x80000000) - CCR |= F_V; + m_CCR |= F_V; return res; } uint8_t h8_device::do_sub8(uint8_t v1, uint8_t v2) { uint16_t res = v1 - v2; - CCR &= ~(F_N|F_V|F_Z|F_C); - if (has_hc) + m_CCR &= ~(F_N|F_V|F_Z|F_C); + if(m_has_hc) { - CCR &= ~F_H; - if (((v1 & 0xf) - (v2 & 0xf)) & 0x10) - CCR |= F_H; + m_CCR &= ~F_H; + if(((v1 & 0xf) - (v2 & 0xf)) & 0x10) + m_CCR |= F_H; } if(!uint8_t(res)) - CCR |= F_Z; + m_CCR |= F_Z; else if(int8_t(res) < 0) - CCR |= F_N; + m_CCR |= F_N; if((v1^v2) & (v1^res) & 0x80) - CCR |= F_V; + m_CCR |= F_V; if(res & 0x100) - CCR |= F_C; + m_CCR |= F_C; return res; } @@ -662,21 +663,21 @@ uint8_t h8_device::do_sub8(uint8_t v1, uint8_t v2) uint16_t h8_device::do_sub16(uint16_t v1, uint16_t v2) { uint32_t res = v1 - v2; - CCR &= ~(F_N|F_V|F_Z|F_C); - if (has_hc) + m_CCR &= ~(F_N|F_V|F_Z|F_C); + if(m_has_hc) { - CCR &= ~F_H; - if (((v1 & 0xfff) - (v2 & 0xffff)) & 0x1000) - CCR |= F_H; + m_CCR &= ~F_H; + if(((v1 & 0xfff) - (v2 & 0xffff)) & 0x1000) + m_CCR |= F_H; } if(!uint16_t(res)) - CCR |= F_Z; + m_CCR |= F_Z; else if(int16_t(res) < 0) - CCR |= F_N; + m_CCR |= F_N; if((v1^v2) & (v1^res) & 0x8000) - CCR |= F_V; + m_CCR |= F_V; if(res & 0x10000) - CCR |= F_C; + m_CCR |= F_C; return res; } @@ -684,718 +685,718 @@ uint16_t h8_device::do_sub16(uint16_t v1, uint16_t v2) uint32_t h8_device::do_sub32(uint32_t v1, uint32_t v2) { uint64_t res = uint64_t(v1) - uint64_t(v2); - CCR &= ~(F_N|F_V|F_Z|F_C); - if (has_hc) + m_CCR &= ~(F_N|F_V|F_Z|F_C); + if(m_has_hc) { - CCR &= ~F_H; - if (((v1 & 0xfffffff) - (v2 & 0xfffffff)) & 0x10000000) - CCR |= F_H; + m_CCR &= ~F_H; + if(((v1 & 0xfffffff) - (v2 & 0xfffffff)) & 0x10000000) + m_CCR |= F_H; } if(!uint32_t(res)) - CCR |= F_Z; + m_CCR |= F_Z; else if(int32_t(res) < 0) - CCR |= F_N; + m_CCR |= F_N; if((v1^v2) & (v1^res) & 0x80000000) - CCR |= F_V; + m_CCR |= F_V; if(res & 0x100000000U) - CCR |= F_C; + m_CCR |= F_C; return res; } uint8_t h8_device::do_shal8(uint8_t v) { - CCR &= ~(F_N|F_V|F_Z|F_C); + m_CCR &= ~(F_N|F_V|F_Z|F_C); if(v & 0x80) - CCR |= F_C; + m_CCR |= F_C; if((v & 0xc0) == 0x40 || (v & 0xc0) == 0x80) - CCR |= F_V; + m_CCR |= F_V; v <<= 1; if(!v) - CCR |= F_Z; + m_CCR |= F_Z; else if(int8_t(v) < 0) - CCR |= F_N; + m_CCR |= F_N; return v; } uint16_t h8_device::do_shal16(uint16_t v) { - CCR &= ~(F_N|F_V|F_Z|F_C); + m_CCR &= ~(F_N|F_V|F_Z|F_C); if(v & 0x8000) - CCR |= F_C; + m_CCR |= F_C; if((v & 0xc000) == 0x4000 || (v & 0xc000) == 0x8000) - CCR |= F_V; + m_CCR |= F_V; v <<= 1; if(!v) - CCR |= F_Z; + m_CCR |= F_Z; else if(int16_t(v) < 0) - CCR |= F_N; + m_CCR |= F_N; return v; } uint32_t h8_device::do_shal32(uint32_t v) { - CCR &= ~(F_N|F_V|F_Z|F_C); + m_CCR &= ~(F_N|F_V|F_Z|F_C); if(v & 0x80000000) - CCR |= F_C; + m_CCR |= F_C; if((v & 0xc0000000) == 0x40000000 || (v & 0xc0000000) == 0x80000000) - CCR |= F_V; + m_CCR |= F_V; v <<= 1; if(!v) - CCR |= F_Z; + m_CCR |= F_Z; else if(int32_t(v) < 0) - CCR |= F_N; + m_CCR |= F_N; return v; } uint8_t h8_device::do_shar8(uint8_t v) { - CCR &= ~(F_N|F_V|F_Z|F_C); + m_CCR &= ~(F_N|F_V|F_Z|F_C); if(v & 1) - CCR |= F_C; + m_CCR |= F_C; v >>= 1; if(!v) - CCR |= F_Z; - else if (v & 0x40) { + m_CCR |= F_Z; + else if(v & 0x40) { v |= 0x80; - CCR |= F_N; + m_CCR |= F_N; } return v; } uint16_t h8_device::do_shar16(uint16_t v) { - CCR &= ~(F_N|F_V|F_Z|F_C); + m_CCR &= ~(F_N|F_V|F_Z|F_C); if(v & 1) - CCR |= F_C; + m_CCR |= F_C; v >>= 1; if(!v) - CCR |= F_Z; - else if (v & 0x4000) { + m_CCR |= F_Z; + else if(v & 0x4000) { v |= 0x8000; - CCR |= F_N; + m_CCR |= F_N; } return v; } uint32_t h8_device::do_shar32(uint32_t v) { - CCR &= ~(F_N|F_V|F_Z|F_C); + m_CCR &= ~(F_N|F_V|F_Z|F_C); if(v & 1) - CCR |= F_C; + m_CCR |= F_C; v >>= 1; if(!v) - CCR |= F_Z; - else if (v & 0x40000000) { + m_CCR |= F_Z; + else if(v & 0x40000000) { v |= 0x80000000; - CCR |= F_N; + m_CCR |= F_N; } return v; } uint8_t h8_device::do_shll8(uint8_t v) { - CCR &= ~(F_N|F_V|F_Z|F_C); + m_CCR &= ~(F_N|F_V|F_Z|F_C); if(v & 0x80) - CCR |= F_C; + m_CCR |= F_C; v <<= 1; if(!v) - CCR |= F_Z; + m_CCR |= F_Z; else if(int8_t(v) < 0) - CCR |= F_N; + m_CCR |= F_N; return v; } uint16_t h8_device::do_shll16(uint16_t v) { - CCR &= ~(F_N|F_V|F_Z|F_C); + m_CCR &= ~(F_N|F_V|F_Z|F_C); if(v & 0x8000) - CCR |= F_C; + m_CCR |= F_C; v <<= 1; if(!v) - CCR |= F_Z; + m_CCR |= F_Z; else if(int16_t(v) < 0) - CCR |= F_N; + m_CCR |= F_N; return v; } uint32_t h8_device::do_shll32(uint32_t v) { - CCR &= ~(F_N|F_V|F_Z|F_C); + m_CCR &= ~(F_N|F_V|F_Z|F_C); if(v & 0x80000000) - CCR |= F_C; + m_CCR |= F_C; v <<= 1; if(!v) - CCR |= F_Z; + m_CCR |= F_Z; else if(int32_t(v) < 0) - CCR |= F_N; + m_CCR |= F_N; return v; } uint8_t h8_device::do_shlr8(uint8_t v) { - CCR &= ~(F_N|F_V|F_Z|F_C); + m_CCR &= ~(F_N|F_V|F_Z|F_C); if(v & 1) - CCR |= F_C; + m_CCR |= F_C; v >>= 1; if(!v) - CCR |= F_Z; + m_CCR |= F_Z; return v; } uint16_t h8_device::do_shlr16(uint16_t v) { - CCR &= ~(F_N|F_V|F_Z|F_C); + m_CCR &= ~(F_N|F_V|F_Z|F_C); if(v & 1) - CCR |= F_C; + m_CCR |= F_C; v >>= 1; if(!v) - CCR |= F_Z; + m_CCR |= F_Z; return v; } uint32_t h8_device::do_shlr32(uint32_t v) { - CCR &= ~(F_N|F_V|F_Z|F_C); + m_CCR &= ~(F_N|F_V|F_Z|F_C); if(v & 1) - CCR |= F_C; + m_CCR |= F_C; v >>= 1; if(!v) - CCR |= F_Z; + m_CCR |= F_Z; return v; } uint8_t h8_device::do_shal2_8(uint8_t v) { - CCR &= ~(F_N|F_V|F_Z|F_C); + m_CCR &= ~(F_N|F_V|F_Z|F_C); if(v & 0x40) - CCR |= F_C; + m_CCR |= F_C; if((v & 0xc0) == 0x40 || (v & 0xc0) == 0x80 || (v & 0x60) == 0x20 || (v & 0x60) == 0x40) - CCR |= F_V; + m_CCR |= F_V; v <<= 2; if(!v) - CCR |= F_Z; + m_CCR |= F_Z; else if(int8_t(v) < 0) - CCR |= F_N; + m_CCR |= F_N; return v; } uint16_t h8_device::do_shal2_16(uint16_t v) { - CCR &= ~(F_N|F_V|F_Z|F_C); + m_CCR &= ~(F_N|F_V|F_Z|F_C); if(v & 0x4000) - CCR |= F_C; + m_CCR |= F_C; if((v & 0xc000) == 0x4000 || (v & 0xc000) == 0x8000 || (v & 0x6000) == 0x2000 || (v & 0x6000) == 0x4000) - CCR |= F_V; + m_CCR |= F_V; v <<= 2; if(!v) - CCR |= F_Z; + m_CCR |= F_Z; else if(int16_t(v) < 0) - CCR |= F_N; + m_CCR |= F_N; return v; } uint32_t h8_device::do_shal2_32(uint32_t v) { - CCR &= ~(F_N|F_V|F_Z|F_C); + m_CCR &= ~(F_N|F_V|F_Z|F_C); if(v & 0x40000000) - CCR |= F_C; + m_CCR |= F_C; if((v & 0xc0000000) == 0x40000000 || (v & 0xc0000000) == 0x80000000 || (v & 0x60000000) == 0x20000000 || (v & 0x60000000) == 0x40000000) - CCR |= F_V; + m_CCR |= F_V; v <<= 2; if(!v) - CCR |= F_Z; + m_CCR |= F_Z; else if(int32_t(v) < 0) - CCR |= F_N; + m_CCR |= F_N; return v; } uint8_t h8_device::do_shar2_8(uint8_t v) { - CCR &= ~(F_N|F_V|F_Z|F_C); + m_CCR &= ~(F_N|F_V|F_Z|F_C); if(v & 2) - CCR |= F_C; + m_CCR |= F_C; v >>= 2; if(!v) - CCR |= F_Z; - else if (v & 0x20) { + m_CCR |= F_Z; + else if(v & 0x20) { v |= 0xc0; - CCR |= F_N; + m_CCR |= F_N; } return v; } uint16_t h8_device::do_shar2_16(uint16_t v) { - CCR &= ~(F_N|F_V|F_Z|F_C); + m_CCR &= ~(F_N|F_V|F_Z|F_C); if(v & 2) - CCR |= F_C; + m_CCR |= F_C; v >>= 2; if(!v) - CCR |= F_Z; - else if (v & 0x2000) { + m_CCR |= F_Z; + else if(v & 0x2000) { v |= 0xc000; - CCR |= F_N; + m_CCR |= F_N; } return v; } uint32_t h8_device::do_shar2_32(uint32_t v) { - CCR &= ~(F_N|F_V|F_Z|F_C); + m_CCR &= ~(F_N|F_V|F_Z|F_C); if(v & 2) - CCR |= F_C; + m_CCR |= F_C; v >>= 2; if(!v) - CCR |= F_Z; - else if (v & 0x20000000) { + m_CCR |= F_Z; + else if(v & 0x20000000) { v |= 0xc0000000; - CCR |= F_N; + m_CCR |= F_N; } return v; } uint8_t h8_device::do_shll2_8(uint8_t v) { - CCR &= ~(F_N|F_V|F_Z|F_C); + m_CCR &= ~(F_N|F_V|F_Z|F_C); if(v & 0x40) - CCR |= F_C; + m_CCR |= F_C; v <<= 2; if(!v) - CCR |= F_Z; + m_CCR |= F_Z; else if(int8_t(v) < 0) - CCR |= F_N; + m_CCR |= F_N; return v; } uint16_t h8_device::do_shll2_16(uint16_t v) { - CCR &= ~(F_N|F_V|F_Z|F_C); + m_CCR &= ~(F_N|F_V|F_Z|F_C); if(v & 0x4000) - CCR |= F_C; + m_CCR |= F_C; v <<= 2; if(!v) - CCR |= F_Z; + m_CCR |= F_Z; else if(int16_t(v) < 0) - CCR |= F_N; + m_CCR |= F_N; return v; } uint32_t h8_device::do_shll2_32(uint32_t v) { - CCR &= ~(F_N|F_V|F_Z|F_C); + m_CCR &= ~(F_N|F_V|F_Z|F_C); if(v & 0x40000000) - CCR |= F_C; + m_CCR |= F_C; v <<= 2; if(!v) - CCR |= F_Z; + m_CCR |= F_Z; else if(int32_t(v) < 0) - CCR |= F_N; + m_CCR |= F_N; return v; } uint8_t h8_device::do_shlr2_8(uint8_t v) { - CCR &= ~(F_N|F_V|F_Z|F_C); + m_CCR &= ~(F_N|F_V|F_Z|F_C); if(v & 2) - CCR |= F_C; + m_CCR |= F_C; v >>= 2; if(!v) - CCR |= F_Z; + m_CCR |= F_Z; return v; } uint16_t h8_device::do_shlr2_16(uint16_t v) { - CCR &= ~(F_N|F_V|F_Z|F_C); + m_CCR &= ~(F_N|F_V|F_Z|F_C); if(v & 2) - CCR |= F_C; + m_CCR |= F_C; v >>= 2; if(!v) - CCR |= F_Z; + m_CCR |= F_Z; return v; } uint32_t h8_device::do_shlr2_32(uint32_t v) { - CCR &= ~(F_N|F_V|F_Z|F_C); + m_CCR &= ~(F_N|F_V|F_Z|F_C); if(v & 2) - CCR |= F_C; + m_CCR |= F_C; v >>= 2; if(!v) - CCR |= F_Z; + m_CCR |= F_Z; return v; } uint8_t h8_device::do_rotl8(uint8_t v) { - CCR &= ~(F_N|F_V|F_Z|F_C); + m_CCR &= ~(F_N|F_V|F_Z|F_C); if(v & 0x80) - CCR |= F_C; + m_CCR |= F_C; v = (v << 1) | (v >> 7); if(!v) - CCR |= F_Z; + m_CCR |= F_Z; else if(int8_t(v) < 0) - CCR |= F_N; + m_CCR |= F_N; return v; } uint16_t h8_device::do_rotl16(uint16_t v) { - CCR &= ~(F_N|F_V|F_Z|F_C); + m_CCR &= ~(F_N|F_V|F_Z|F_C); if(v & 0x8000) - CCR |= F_C; + m_CCR |= F_C; v = (v << 1) | (v >> 15); if(!v) - CCR |= F_Z; + m_CCR |= F_Z; else if(int16_t(v) < 0) - CCR |= F_N; + m_CCR |= F_N; return v; } uint32_t h8_device::do_rotl32(uint32_t v) { - CCR &= ~(F_N|F_V|F_Z|F_C); + m_CCR &= ~(F_N|F_V|F_Z|F_C); if(v & 0x80000000) - CCR |= F_C; + m_CCR |= F_C; v = (v << 1) | (v >> 31); if(!v) - CCR |= F_Z; + m_CCR |= F_Z; else if(int32_t(v) < 0) - CCR |= F_N; + m_CCR |= F_N; return v; } uint8_t h8_device::do_rotr8(uint8_t v) { - CCR &= ~(F_N|F_V|F_Z|F_C); + m_CCR &= ~(F_N|F_V|F_Z|F_C); if(v & 0x01) - CCR |= F_C; + m_CCR |= F_C; v = (v << 7) | (v >> 1); if(!v) - CCR |= F_Z; + m_CCR |= F_Z; else if(int8_t(v) < 0) - CCR |= F_N; + m_CCR |= F_N; return v; } uint16_t h8_device::do_rotr16(uint16_t v) { - CCR &= ~(F_N|F_V|F_Z|F_C); + m_CCR &= ~(F_N|F_V|F_Z|F_C); if(v & 0x0001) - CCR |= F_C; + m_CCR |= F_C; v = (v << 15) | (v >> 1); if(!v) - CCR |= F_Z; + m_CCR |= F_Z; else if(int16_t(v) < 0) - CCR |= F_N; + m_CCR |= F_N; return v; } uint32_t h8_device::do_rotr32(uint32_t v) { - CCR &= ~(F_N|F_V|F_Z|F_C); + m_CCR &= ~(F_N|F_V|F_Z|F_C); if(v & 0x00000001) - CCR |= F_C; + m_CCR |= F_C; v = (v << 31) | (v >> 1); if(!v) - CCR |= F_Z; + m_CCR |= F_Z; else if(int32_t(v) < 0) - CCR |= F_N; + m_CCR |= F_N; return v; } uint8_t h8_device::do_rotxl8(uint8_t v) { - uint8_t c = CCR & F_C ? 1 : 0; - CCR &= ~(F_N|F_V|F_Z|F_C); + uint8_t c = m_CCR & F_C ? 1 : 0; + m_CCR &= ~(F_N|F_V|F_Z|F_C); if(v & 0x80) - CCR |= F_C; + m_CCR |= F_C; v = (v << 1) | c; if(!v) - CCR |= F_Z; + m_CCR |= F_Z; else if(int8_t(v) < 0) - CCR |= F_N; + m_CCR |= F_N; return v; } uint16_t h8_device::do_rotxl16(uint16_t v) { - uint16_t c = CCR & F_C ? 1 : 0; - CCR &= ~(F_N|F_V|F_Z|F_C); + uint16_t c = m_CCR & F_C ? 1 : 0; + m_CCR &= ~(F_N|F_V|F_Z|F_C); if(v & 0x8000) - CCR |= F_C; + m_CCR |= F_C; v = (v << 1) | c; if(!v) - CCR |= F_Z; + m_CCR |= F_Z; else if(int16_t(v) < 0) - CCR |= F_N; + m_CCR |= F_N; return v; } uint32_t h8_device::do_rotxl32(uint32_t v) { - uint32_t c = CCR & F_C ? 1 : 0; - CCR &= ~(F_N|F_V|F_Z|F_C); + uint32_t c = m_CCR & F_C ? 1 : 0; + m_CCR &= ~(F_N|F_V|F_Z|F_C); if(v & 0x80000000) - CCR |= F_C; + m_CCR |= F_C; v = (v << 1) | c; if(!v) - CCR |= F_Z; + m_CCR |= F_Z; else if(int32_t(v) < 0) - CCR |= F_N; + m_CCR |= F_N; return v; } uint8_t h8_device::do_rotxr8(uint8_t v) { - uint8_t c = CCR & F_C ? 1 : 0; - CCR &= ~(F_N|F_V|F_Z|F_C); + uint8_t c = m_CCR & F_C ? 1 : 0; + m_CCR &= ~(F_N|F_V|F_Z|F_C); if(v & 0x01) - CCR |= F_C; + m_CCR |= F_C; v = (v >> 1) | (c << 7); if(!v) - CCR |= F_Z; + m_CCR |= F_Z; else if(int8_t(v) < 0) - CCR |= F_N; + m_CCR |= F_N; return v; } uint16_t h8_device::do_rotxr16(uint16_t v) { - uint8_t c = CCR & F_C ? 1 : 0; - CCR &= ~(F_N|F_V|F_Z|F_C); + uint8_t c = m_CCR & F_C ? 1 : 0; + m_CCR &= ~(F_N|F_V|F_Z|F_C); if(v & 0x0001) - CCR |= F_C; + m_CCR |= F_C; v = (v >> 1) | (c << 15); if(!v) - CCR |= F_Z; + m_CCR |= F_Z; else if(int16_t(v) < 0) - CCR |= F_N; + m_CCR |= F_N; return v; } uint32_t h8_device::do_rotxr32(uint32_t v) { - uint8_t c = CCR & F_C ? 1 : 0; - CCR &= ~(F_N|F_V|F_Z|F_C); + uint8_t c = m_CCR & F_C ? 1 : 0; + m_CCR &= ~(F_N|F_V|F_Z|F_C); if(v & 0x00000001) - CCR |= F_C; + m_CCR |= F_C; v = (v >> 1) | (c << 31); if(!v) - CCR |= F_Z; + m_CCR |= F_Z; else if(int32_t(v) < 0) - CCR |= F_N; + m_CCR |= F_N; return v; } uint8_t h8_device::do_rotl2_8(uint8_t v) { - CCR &= ~(F_N|F_V|F_Z|F_C); + m_CCR &= ~(F_N|F_V|F_Z|F_C); if(v & 0x40) - CCR |= F_C; + m_CCR |= F_C; v = (v << 2) | (v >> 6); if(!v) - CCR |= F_Z; + m_CCR |= F_Z; else if(int8_t(v) < 0) - CCR |= F_N; + m_CCR |= F_N; return v; } uint16_t h8_device::do_rotl2_16(uint16_t v) { - CCR &= ~(F_N|F_V|F_Z|F_C); + m_CCR &= ~(F_N|F_V|F_Z|F_C); if(v & 0x4000) - CCR |= F_C; + m_CCR |= F_C; v = (v << 2) | (v >> 14); if(!v) - CCR |= F_Z; + m_CCR |= F_Z; else if(int16_t(v) < 0) - CCR |= F_N; + m_CCR |= F_N; return v; } uint32_t h8_device::do_rotl2_32(uint32_t v) { - CCR &= ~(F_N|F_V|F_Z|F_C); + m_CCR &= ~(F_N|F_V|F_Z|F_C); if(v & 0x40000000) - CCR |= F_C; + m_CCR |= F_C; v = (v << 2) | (v >> 30); if(!v) - CCR |= F_Z; + m_CCR |= F_Z; else if(int32_t(v) < 0) - CCR |= F_N; + m_CCR |= F_N; return v; } uint8_t h8_device::do_rotr2_8(uint8_t v) { - CCR &= ~(F_N|F_V|F_Z|F_C); + m_CCR &= ~(F_N|F_V|F_Z|F_C); if(v & 0x02) - CCR |= F_C; + m_CCR |= F_C; v = (v << 6) | (v >> 2); if(!v) - CCR |= F_Z; + m_CCR |= F_Z; else if(int8_t(v) < 0) - CCR |= F_N; + m_CCR |= F_N; return v; } uint16_t h8_device::do_rotr2_16(uint16_t v) { - CCR &= ~(F_N|F_V|F_Z|F_C); + m_CCR &= ~(F_N|F_V|F_Z|F_C); if(v & 0x0002) - CCR |= F_C; + m_CCR |= F_C; v = (v << 14) | (v >> 2); if(!v) - CCR |= F_Z; + m_CCR |= F_Z; else if(int16_t(v) < 0) - CCR |= F_N; + m_CCR |= F_N; return v; } uint32_t h8_device::do_rotr2_32(uint32_t v) { - CCR &= ~(F_N|F_V|F_Z|F_C); + m_CCR &= ~(F_N|F_V|F_Z|F_C); if(v & 0x00000002) - CCR |= F_C; + m_CCR |= F_C; v = (v << 30) | (v >> 2); if(!v) - CCR |= F_Z; + m_CCR |= F_Z; else if(int32_t(v) < 0) - CCR |= F_N; + m_CCR |= F_N; return v; } uint8_t h8_device::do_rotxl2_8(uint8_t v) { - uint8_t c = CCR & F_C ? 1 : 0; - CCR &= ~(F_N|F_V|F_Z|F_C); + uint8_t c = m_CCR & F_C ? 1 : 0; + m_CCR &= ~(F_N|F_V|F_Z|F_C); if(v & 0x40) - CCR |= F_C; + m_CCR |= F_C; v = (v << 2) | (c << 1) | ((v >> 6) & 0x01); if(!v) - CCR |= F_Z; + m_CCR |= F_Z; else if(int8_t(v) < 0) - CCR |= F_N; + m_CCR |= F_N; return v; } uint16_t h8_device::do_rotxl2_16(uint16_t v) { - uint16_t c = CCR & F_C ? 1 : 0; - CCR &= ~(F_N|F_V|F_Z|F_C); + uint16_t c = m_CCR & F_C ? 1 : 0; + m_CCR &= ~(F_N|F_V|F_Z|F_C); if(v & 0x4000) - CCR |= F_C; + m_CCR |= F_C; v = (v << 2) | (c << 1) | ((v >> 14) & 0x0001); if(!v) - CCR |= F_Z; + m_CCR |= F_Z; else if(int16_t(v) < 0) - CCR |= F_N; + m_CCR |= F_N; return v; } uint32_t h8_device::do_rotxl2_32(uint32_t v) { - uint32_t c = CCR & F_C ? 1 : 0; - CCR &= ~(F_N|F_V|F_Z|F_C); + uint32_t c = m_CCR & F_C ? 1 : 0; + m_CCR &= ~(F_N|F_V|F_Z|F_C); if(v & 0x40000000) - CCR |= F_C; + m_CCR |= F_C; v = (v << 2) | (c << 1) | ((v >> 30) & 0x00000001); if(!v) - CCR |= F_Z; + m_CCR |= F_Z; else if(int32_t(v) < 0) - CCR |= F_N; + m_CCR |= F_N; return v; } uint8_t h8_device::do_rotxr2_8(uint8_t v) { - uint8_t c = CCR & F_C ? 1 : 0; - CCR &= ~(F_N|F_V|F_Z|F_C); + uint8_t c = m_CCR & F_C ? 1 : 0; + m_CCR &= ~(F_N|F_V|F_Z|F_C); if(v & 0x02) - CCR |= F_C; + m_CCR |= F_C; v = (v >> 2) | (c << 6) | (v << 7); if(!v) - CCR |= F_Z; + m_CCR |= F_Z; else if(int8_t(v) < 0) - CCR |= F_N; + m_CCR |= F_N; return v; } uint16_t h8_device::do_rotxr2_16(uint16_t v) { - uint16_t c = CCR & F_C ? 1 : 0; - CCR &= ~(F_N|F_V|F_Z|F_C); + uint16_t c = m_CCR & F_C ? 1 : 0; + m_CCR &= ~(F_N|F_V|F_Z|F_C); if(v & 0x0002) - CCR |= F_C; + m_CCR |= F_C; v = (v >> 2) | (c << 14) | (v << 15); if(!v) - CCR |= F_Z; + m_CCR |= F_Z; else if(int16_t(v) < 0) - CCR |= F_N; + m_CCR |= F_N; return v; } uint32_t h8_device::do_rotxr2_32(uint32_t v) { - uint32_t c = CCR & F_C ? 1 : 0; - CCR &= ~(F_N|F_V|F_Z|F_C); + uint32_t c = m_CCR & F_C ? 1 : 0; + m_CCR &= ~(F_N|F_V|F_Z|F_C); if(v & 0x00000002) - CCR |= F_C; + m_CCR |= F_C; v = (v >> 2) | (c << 30) | (v << 31); if(!v) - CCR |= F_Z; + m_CCR |= F_Z; else if(int32_t(v) < 0) - CCR |= F_N; + m_CCR |= F_N; return v; } void h8_device::set_nzv8(uint8_t v) { - CCR &= ~(F_N|F_V|F_Z); + m_CCR &= ~(F_N|F_V|F_Z); if(!v) - CCR |= F_Z; + m_CCR |= F_Z; else if(int8_t(v) < 0) - CCR |= F_N; + m_CCR |= F_N; } void h8_device::set_nzv16(uint16_t v) { - CCR &= ~(F_N|F_V|F_Z); + m_CCR &= ~(F_N|F_V|F_Z); if(!v) - CCR |= F_Z; + m_CCR |= F_Z; else if(int16_t(v) < 0) - CCR |= F_N; + m_CCR |= F_N; } void h8_device::set_nzv32(uint32_t v) { - CCR &= ~(F_N|F_V|F_Z); + m_CCR &= ~(F_N|F_V|F_Z); if(!v) - CCR |= F_Z; + m_CCR |= F_Z; else if(int32_t(v) < 0) - CCR |= F_N; + m_CCR |= F_N; } void h8_device::set_nz16(uint16_t v) { - CCR &= ~(F_N|F_Z); + m_CCR &= ~(F_N|F_Z); if(!v) - CCR |= F_Z; + m_CCR |= F_Z; else if(int16_t(v) < 0) - CCR |= F_N; + m_CCR |= F_N; } void h8_device::set_nz32(uint32_t v) { - CCR &= ~(F_N|F_Z); + m_CCR &= ~(F_N|F_Z); if(!v) - CCR |= F_Z; + m_CCR |= F_Z; else if(int32_t(v) < 0) - CCR |= F_N; + m_CCR |= F_N; } std::unique_ptr h8_device::create_disassembler() diff --git a/src/devices/cpu/h8/h8.h b/src/devices/cpu/h8/h8.h index 773867a5802..ac8e7de259b 100644 --- a/src/devices/cpu/h8/h8.h +++ b/src/devices/cpu/h8/h8.h @@ -69,7 +69,7 @@ public: void set_current_dma(h8_dma_state *state); void set_current_dtc(h8_dtc_state *state); void request_state(int state); - bool access_is_dma() const { return inst_state == STATE_DMA || inst_state == STATE_DTC; } + bool access_is_dma() const { return m_inst_state == STATE_DMA || m_inst_state == STATE_DTC; } protected: enum { @@ -113,36 +113,36 @@ protected: // device_disasm_interface overrides virtual std::unique_ptr create_disassembler() override; - address_space_config program_config, io_config; - memory_access<32, 1, 0, ENDIANNESS_BIG>::cache cache; - memory_access<32, 1, 0, ENDIANNESS_BIG>::specific program; - memory_access<16, 1, -1, ENDIANNESS_BIG>::specific io; - h8_dma_device *dma_device; - h8_dtc_device *dtc_device; - h8_dma_state *current_dma; - h8_dtc_state *current_dtc; - - uint32_t PPC; /* previous program counter */ - uint32_t NPC; /* next start-of-instruction program counter */ - uint32_t PC; /* program counter */ - uint16_t PIR; /* Prefetched word */ - uint16_t IR[5]; /* Fetched instruction */ - uint16_t R[16]; /* Rn (0-7), En (8-15, h8-300h+) */ - uint8_t EXR; /* Interrupt/trace register (h8s/2000+) */ - uint8_t CCR; /* Condition-code register */ - int64_t MAC; /* Multiply accumulator (h8s/2600+) */ - uint8_t MACF; /* MAC flags (h8s/2600+) */ - uint32_t TMP1, TMP2; - uint32_t TMPR; /* For debugger ER register import */ - - bool has_exr, has_mac, has_trace, supports_advanced, mode_advanced, mode_a20, mac_saturating; - bool has_hc; // GT913's CCR bit 5 is I, not H - - int inst_state, inst_substate, requested_state; - int icount, bcount, count_before_instruction_step; - int irq_vector, taken_irq_vector; - int irq_level, taken_irq_level; - bool irq_required, irq_nmi; + address_space_config m_program_config, m_io_config; + memory_access<32, 1, 0, ENDIANNESS_BIG>::cache m_cache; + memory_access<32, 1, 0, ENDIANNESS_BIG>::specific m_program; + memory_access<16, 1, -1, ENDIANNESS_BIG>::specific m_io; + h8_dma_device *m_dma_device; + h8_dtc_device *m_dtc_device; + h8_dma_state *m_current_dma; + h8_dtc_state *m_current_dtc; + + uint32_t m_PPC; /* previous program counter */ + uint32_t m_NPC; /* next start-of-instruction program counter */ + uint32_t m_PC; /* program counter */ + uint16_t m_PIR; /* Prefetched word */ + uint16_t m_IR[5]; /* Fetched instruction */ + uint16_t m_R[16]; /* Rn (0-7), En (8-15, h8-300h+) */ + uint8_t m_EXR; /* Interrupt/trace register (h8s/2000+) */ + uint8_t m_CCR; /* Condition-code register */ + int64_t m_MAC; /* Multiply accumulator (h8s/2600+) */ + uint8_t m_MACF; /* MAC flags (h8s/2600+) */ + uint32_t m_TMP1, m_TMP2; + uint32_t m_TMPR; /* For debugger ER register import */ + + bool m_has_exr, m_has_mac, m_has_trace, m_supports_advanced, m_mode_advanced, m_mode_a20, m_mac_saturating; + bool m_has_hc; // GT913's CCR bit 5 is I, not H + + int m_inst_state, m_inst_substate, m_requested_state; + int m_icount, m_bcount, m_count_before_instruction_step; + int m_irq_vector, m_taken_irq_vector; + int m_irq_level, m_taken_irq_level; + bool m_irq_required, m_irq_nmi; virtual void do_exec_full(); virtual void do_exec_partial(); @@ -162,7 +162,7 @@ protected: uint16_t read16(uint32_t adr); void write16(uint32_t adr, uint16_t data); void internal(int cycles); - void prefetch_switch(uint32_t pc, uint16_t ir) { NPC = pc & 0xffffff; PC = pc+2; PIR = ir; } + void prefetch_switch(uint32_t pc, uint16_t ir) { m_NPC = pc & 0xffffff; m_PC = pc+2; m_PIR = ir; } void prefetch_done(); void prefetch_done_noirq(); void prefetch_done_noirq_notrace(); @@ -260,16 +260,16 @@ protected: inline void r8_w(int reg, uint8_t val) { if(reg & 8) - R[reg & 7] = (R[reg & 7] & 0xff00) | val; + m_R[reg & 7] = (m_R[reg & 7] & 0xff00) | val; else - R[reg & 7] = (R[reg & 7] & 0xff) | (val << 8); + m_R[reg & 7] = (m_R[reg & 7] & 0xff) | (val << 8); } inline uint8_t r8_r(int reg) { if(reg & 8) - return R[reg & 7]; + return m_R[reg & 7]; else - return R[reg & 7] >> 8; + return m_R[reg & 7] >> 8; } // Note that the decode is so that there's no risk of a h8-300 @@ -280,8 +280,8 @@ protected: // and the h8-300h is r32 of course, we have to be careful to mask // in h8.lst there if the top bit is 1. - inline void r16_w(int reg, uint16_t val) { R[reg & 0xf] = val; } - inline uint16_t r16_r(int reg) { return R[reg & 0xf]; } + inline void r16_w(int reg, uint16_t val) { m_R[reg & 0xf] = val; } + inline uint16_t r16_r(int reg) { return m_R[reg & 0xf]; } #define O(o) void o ## _full(); void o ## _partial() O(add_b_imm8_r8u); O(add_b_r8h_r8l); O(add_w_imm16_r16l); O(add_w_r16h_r16l); diff --git a/src/devices/cpu/h8/h8.lst b/src/devices/cpu/h8/h8.lst index 9e2a67f0cc9..681463691bb 100644 --- a/src/devices/cpu/h8/h8.lst +++ b/src/devices/cpu/h8/h8.lst @@ -2,11 +2,11 @@ # copyright-holders:Olivier Galibert macro fetch - PIR = read16i(PC); - PC += 2; + m_PIR = read16i(m_PC); + m_PC += 2; macro prefetch_start - NPC = PC & 0xffffff; + m_NPC = m_PC & 0xffffff; fetch macro prefetch @@ -23,81 +23,81 @@ macro prefetch_noirq_notrace macro bxx_any %cond prefetch_start - TMP2 = read16i(TMP1); + m_TMP2 = read16i(m_TMP1); if(%cond) - prefetch_switch(TMP1, TMP2); + prefetch_switch(m_TMP1, m_TMP2); prefetch_done(); macro bxx_8 %cond - TMP1 = PC + int8_t(IR[0]); + m_TMP1 = m_PC + int8_t(m_IR[0]); bxx_any %cond macro bxx_16 %cond - TMP1 = PC + int16_t(IR[1]); + m_TMP1 = m_PC + int16_t(m_IR[1]); bxx_any %cond macro bset %bit - TMP1 |= 1 << ((%bit) & 7); + m_TMP1 |= 1 << ((%bit) & 7); macro bnot %bit - TMP1 ^= 1 << ((%bit) & 7); + m_TMP1 ^= 1 << ((%bit) & 7); macro bclr %bit - TMP1 &= ~(1 << ((%bit) & 7)); + m_TMP1 &= ~(1 << ((%bit) & 7)); macro btst %bit - if(TMP1 & (1 << ((%bit) & 7))) - CCR &= ~F_Z; + if(m_TMP1 & (1 << ((%bit) & 7))) + m_CCR &= ~F_Z; else - CCR |= F_Z; + m_CCR |= F_Z; macro bor %bit - if(TMP1 & (1 << ((%bit) & 7))) - CCR |= F_C; + if(m_TMP1 & (1 << ((%bit) & 7))) + m_CCR |= F_C; macro bior %bit - if(!(TMP1 & (1 << ((%bit) & 7)))) - CCR |= F_C; + if(!(m_TMP1 & (1 << ((%bit) & 7)))) + m_CCR |= F_C; macro bxor %bit - if(TMP1 & (1 << ((%bit) & 7))) - CCR ^= F_C; + if(m_TMP1 & (1 << ((%bit) & 7))) + m_CCR ^= F_C; macro bixor %bit - if(!(TMP1 & (1 << ((%bit) & 7)))) - CCR ^= F_C; + if(!(m_TMP1 & (1 << ((%bit) & 7)))) + m_CCR ^= F_C; macro band %bit - if(!(TMP1 & (1 << ((%bit) & 7)))) - CCR &= ~F_C; + if(!(m_TMP1 & (1 << ((%bit) & 7)))) + m_CCR &= ~F_C; macro biand %bit - if(TMP1 & (1 << ((%bit) & 7))) - CCR &= ~F_C; + if(m_TMP1 & (1 << ((%bit) & 7))) + m_CCR &= ~F_C; macro bld %bit - if(TMP1 & (1 << ((%bit) & 7))) - CCR |= F_C; + if(m_TMP1 & (1 << ((%bit) & 7))) + m_CCR |= F_C; else - CCR &= ~F_C; + m_CCR &= ~F_C; macro bild %bit - if(!(TMP1 & (1 << ((%bit) & 7)))) - CCR |= F_C; + if(!(m_TMP1 & (1 << ((%bit) & 7)))) + m_CCR |= F_C; else - CCR &= ~F_C; + m_CCR &= ~F_C; macro bst %bit - if(CCR & F_C) - TMP1 |= 1 << ((%bit) & 7); + if(m_CCR & F_C) + m_TMP1 |= 1 << ((%bit) & 7); else - TMP1 &= ~(1 << ((%bit) & 7)); + m_TMP1 &= ~(1 << ((%bit) & 7)); macro bist %bit - if(!(CCR & F_C)) - TMP1 |= 1 << ((%bit) & 7); + if(!(m_CCR & F_C)) + m_TMP1 |= 1 << ((%bit) & 7); else - TMP1 &= ~(1 << ((%bit) & 7)); + m_TMP1 &= ~(1 << ((%bit) & 7)); macro jsr16 %opc %spreg prefetch_start @@ -108,7 +108,7 @@ macro jsr16 %opc %spreg macro jsr32 %opc %spreg prefetch_start - if(mode_advanced) { + if(m_mode_advanced) { %spreg = r32_r(7) - 4; r32_w(7, %spreg); write16(%spreg, %opc >> 16); @@ -121,28 +121,28 @@ macro jsr32 %opc %spreg prefetch_done(); 10000 reset - CCR |= (has_hc ? F_I : F_H); - EXR = EXR_I | EXR_NC; - if(mode_advanced) { - IR[0] = read16i(0); - IR[1] = read16i(2); - PC = (IR[0] << 16) | IR[1]; + m_CCR |= (m_has_hc ? F_I : F_H); + m_EXR = EXR_I | EXR_NC; + if(m_mode_advanced) { + m_IR[0] = read16i(0); + m_IR[1] = read16i(2); + m_PC = (m_IR[0] << 16) | m_IR[1]; } else { - PC = read16i(0); + m_PC = read16i(0); } update_irq_filter(); prefetch_noirq 10001 irq o internal(1); - TMP1 = r16_r(7) - 2; - r16_w(7, TMP1); - write16(TMP1, NPC); - TMP1 = r16_r(7) - 2; - r16_w(7, TMP1); - write16(TMP1, (CCR << 8) | ((PC >> 16) & 0xff)); - debugger_exception_hook(taken_irq_vector); - PC = read16i(2*taken_irq_vector); + m_TMP1 = r16_r(7) - 2; + r16_w(7, m_TMP1); + write16(m_TMP1, m_NPC); + m_TMP1 = r16_r(7) - 2; + r16_w(7, m_TMP1); + write16(m_TMP1, (m_CCR << 8) | ((m_PC >> 16) & 0xff)); + debugger_exception_hook(m_taken_irq_vector); + m_PC = read16i(2*m_taken_irq_vector); internal(1); irq_setup(); update_irq_filter(); @@ -151,24 +151,24 @@ macro jsr32 %opc %spreg 10001 irq h internal(1); - TMP1 = r32_r(7) - 2; - r32_w(7, TMP1); - write16(TMP1, NPC); - TMP1 = r32_r(7) - 2; - r32_w(7, TMP1); - write16(TMP1, (CCR << 8) | ((NPC >> 16) & 0xff)); + m_TMP1 = r32_r(7) - 2; + r32_w(7, m_TMP1); + write16(m_TMP1, m_NPC); + m_TMP1 = r32_r(7) - 2; + r32_w(7, m_TMP1); + write16(m_TMP1, (m_CCR << 8) | ((m_NPC >> 16) & 0xff)); if(exr_in_stack()) { - TMP1 = r32_r(7) - 2; - r32_w(7, TMP1); - write16(TMP1, EXR << 8); + m_TMP1 = r32_r(7) - 2; + r32_w(7, m_TMP1); + write16(m_TMP1, m_EXR << 8); } - debugger_exception_hook(taken_irq_vector); - if(mode_advanced) { - IR[0] = read16i(4*taken_irq_vector); - IR[1] = read16i(4*taken_irq_vector+2); - PC = (IR[0] << 16) | IR[1]; + debugger_exception_hook(m_taken_irq_vector); + if(m_mode_advanced) { + m_IR[0] = read16i(4*m_taken_irq_vector); + m_IR[1] = read16i(4*m_taken_irq_vector+2); + m_PC = (m_IR[0] << 16) | m_IR[1]; } else { - PC = read16i(2*taken_irq_vector); + m_PC = read16i(2*m_taken_irq_vector); } internal(1); irq_setup(); @@ -178,98 +178,98 @@ macro jsr32 %opc %spreg 10002 trace s20 internal(1); - TMP1 = r32_r(7) - 2; - r32_w(7, TMP1); - write16(TMP1, NPC); - TMP1 = r32_r(7) - 2; - r32_w(7, TMP1); - write16(TMP1, (CCR << 8) | ((NPC >> 16) & 0xff)); - TMP1 = r32_r(7) - 2; - r32_w(7, TMP1); - write16(TMP1, EXR << 8); - taken_irq_vector = trace_setup(); - debugger_exception_hook(taken_irq_vector); - if(mode_advanced) { - IR[0] = read16i(4*taken_irq_vector); - IR[1] = read16i(4*taken_irq_vector+2); - PC = (IR[0] << 16) | IR[1]; + m_TMP1 = r32_r(7) - 2; + r32_w(7, m_TMP1); + write16(m_TMP1, m_NPC); + m_TMP1 = r32_r(7) - 2; + r32_w(7, m_TMP1); + write16(m_TMP1, (m_CCR << 8) | ((m_NPC >> 16) & 0xff)); + m_TMP1 = r32_r(7) - 2; + r32_w(7, m_TMP1); + write16(m_TMP1, m_EXR << 8); + m_taken_irq_vector = trace_setup(); + debugger_exception_hook(m_taken_irq_vector); + if(m_mode_advanced) { + m_IR[0] = read16i(4*m_taken_irq_vector); + m_IR[1] = read16i(4*m_taken_irq_vector+2); + m_PC = (m_IR[0] << 16) | m_IR[1]; } else { - PC = read16i(2*taken_irq_vector); + m_PC = read16i(2*m_taken_irq_vector); } internal(1); prefetch_noirq 10003 dma - if(current_dma->count == 1) - dma_device->count_last(current_dma->id); - if(current_dma->mode_16) { - TMP1 = read16(current_dma->source); - write16(current_dma->dest, TMP1); + if(m_current_dma->m_count == 1) + m_dma_device->count_last(m_current_dma->m_id); + if(m_current_dma->m_mode_16) { + m_TMP1 = read16(m_current_dma->m_source); + write16(m_current_dma->m_dest, m_TMP1); } else { - TMP1 = read8(current_dma->source); - write8(current_dma->dest, TMP1); + m_TMP1 = read8(m_current_dma->m_source); + write8(m_current_dma->m_dest, m_TMP1); } - current_dma->source += current_dma->incs; - current_dma->dest += current_dma->incd; - current_dma->count--; - if(!current_dma->autoreq) - current_dma->suspended = true; - if(!current_dma->count) { - uint8_t id = current_dma->id; - current_dma = nullptr; - dma_device->count_done(id); + m_current_dma->m_source += m_current_dma->m_incs; + m_current_dma->m_dest += m_current_dma->m_incd; + m_current_dma->m_count--; + if(!m_current_dma->m_autoreq) + m_current_dma->m_suspended = true; + if(!m_current_dma->m_count) { + uint8_t id = m_current_dma->m_id; + m_current_dma = nullptr; + m_dma_device->count_done(id); } prefetch_done(); 10004 dtc s20 - if(current_dtc->sra & 0x01000000) { - TMP1 = read16(current_dtc->sra & 0xffffff); - write16(current_dtc->dar & 0xffffff, TMP1); + if(m_current_dtc->m_sra & 0x01000000) { + m_TMP1 = read16(m_current_dtc->m_sra & 0xffffff); + write16(m_current_dtc->m_dar & 0xffffff, m_TMP1); } else { - TMP1 = read8(current_dtc->sra & 0xffffff); - write8(current_dtc->dar & 0xffffff, TMP1); + m_TMP1 = read8(m_current_dtc->m_sra & 0xffffff); + write8(m_current_dtc->m_dar & 0xffffff, m_TMP1); } - current_dtc->sra = (current_dtc->sra & 0xff000000) | ((current_dtc->sra + current_dtc->incs) & 0x00ffffff); - current_dtc->dar = (current_dtc->dar & 0xff000000) | ((current_dtc->dar + current_dtc->incd) & 0x00ffffff); - current_dtc->count--; - if(!current_dtc->count) { - uint8_t id = current_dtc->id; - current_dtc = nullptr; - dtc_device->count_done(id); + m_current_dtc->m_sra = (m_current_dtc->m_sra & 0xff000000) | ((m_current_dtc->m_sra + m_current_dtc->m_incs) & 0x00ffffff); + m_current_dtc->m_dar = (m_current_dtc->m_dar & 0xff000000) | ((m_current_dtc->m_dar + m_current_dtc->m_incd) & 0x00ffffff); + m_current_dtc->m_count--; + if(!m_current_dtc->m_count) { + uint8_t id = m_current_dtc->m_id; + m_current_dtc = nullptr; + m_dtc_device->count_done(id); } prefetch_done(); 10005 dtc_vector s20 - TMP1 = dtc_device->get_waiting_vector(); - if(TMP1 < h8_dtc_device::DTC_CHAINED) { - TMP2 = dtc_device->get_vector_address(TMP1); - TMP2 = read16(TMP2); - TMP2 |= 0xff0000; + m_TMP1 = m_dtc_device->get_waiting_vector(); + if(m_TMP1 < h8_dtc_device::DTC_CHAINED) { + m_TMP2 = m_dtc_device->get_vector_address(m_TMP1); + m_TMP2 = read16(m_TMP2); + m_TMP2 |= 0xff0000; } else { - TMP1 -= h8_dtc_device::DTC_CHAINED; - TMP2 = dtc_device->get_object(TMP1)->base + 12; + m_TMP1 -= h8_dtc_device::DTC_CHAINED; + m_TMP2 = m_dtc_device->get_object(m_TMP1)->m_base + 12; } - dtc_device->get_object(TMP1)->base = TMP2; - dtc_device->get_object(TMP1)->sra = read16(TMP2) << 16; - dtc_device->get_object(TMP1)->sra |= read16(TMP2+2); - dtc_device->get_object(TMP1)->dar = read16(TMP2+4) << 16; - dtc_device->get_object(TMP1)->dar |= read16(TMP2+6); - dtc_device->get_object(TMP1)->cr = read16(TMP2+8) << 16; - dtc_device->get_object(TMP1)->cr |= read16(TMP2+10); - dtc_device->vector_done(TMP1); + m_dtc_device->get_object(m_TMP1)->m_base = m_TMP2; + m_dtc_device->get_object(m_TMP1)->m_sra = read16(m_TMP2) << 16; + m_dtc_device->get_object(m_TMP1)->m_sra |= read16(m_TMP2+2); + m_dtc_device->get_object(m_TMP1)->m_dar = read16(m_TMP2+4) << 16; + m_dtc_device->get_object(m_TMP1)->m_dar |= read16(m_TMP2+6); + m_dtc_device->get_object(m_TMP1)->m_cr = read16(m_TMP2+8) << 16; + m_dtc_device->get_object(m_TMP1)->m_cr |= read16(m_TMP2+10); + m_dtc_device->vector_done(m_TMP1); prefetch_done(); 10006 dtc_writeback s20 - TMP1 = dtc_device->get_waiting_writeback(); - TMP2 = dtc_device->get_object(TMP1)->base; - write16(TMP2, dtc_device->get_object(TMP1)->sra >> 16); - write16(TMP2+2, dtc_device->get_object(TMP1)->sra); - write16(TMP2+4, dtc_device->get_object(TMP1)->dar >> 16); - write16(TMP2+6, dtc_device->get_object(TMP1)->dar); - write16(TMP2+8, dtc_device->get_object(TMP1)->cr >> 16); - write16(TMP2+10, dtc_device->get_object(TMP1)->cr); - dtc_device->writeback_done(TMP1); + m_TMP1 = m_dtc_device->get_waiting_writeback(); + m_TMP2 = m_dtc_device->get_object(m_TMP1)->m_base; + write16(m_TMP2, m_dtc_device->get_object(m_TMP1)->m_sra >> 16); + write16(m_TMP2+2, m_dtc_device->get_object(m_TMP1)->m_sra); + write16(m_TMP2+4, m_dtc_device->get_object(m_TMP1)->m_dar >> 16); + write16(m_TMP2+6, m_dtc_device->get_object(m_TMP1)->m_dar); + write16(m_TMP2+8, m_dtc_device->get_object(m_TMP1)->m_cr >> 16); + write16(m_TMP2+10, m_dtc_device->get_object(m_TMP1)->m_cr); + m_dtc_device->writeback_done(m_TMP1); prefetch_done(); 0000 ffff 0 nop - - @@ -277,466 +277,466 @@ macro jsr32 %opc %spreg 01006900 ffffff88 0 mov.l r32ih r32l h prefetch_start - TMP2 = r32_r(IR[1] >> 4); - TMP1 = read16(TMP2) << 16; - TMP1 |= read16(TMP2+2); - set_nzv32(TMP1); - r32_w(IR[1], TMP1); + m_TMP2 = r32_r(m_IR[1] >> 4); + m_TMP1 = read16(m_TMP2) << 16; + m_TMP1 |= read16(m_TMP2+2); + set_nzv32(m_TMP1); + r32_w(m_IR[1], m_TMP1); prefetch_done(); 01006980 ffffff88 0 mov.l r32l r32ih h prefetch_start - TMP2 = r32_r(IR[1] >> 4); - TMP1 = r32_r(IR[1]); - set_nzv32(TMP1); - write16(TMP2, TMP1 >> 16); - write16(TMP2+2, TMP1); + m_TMP2 = r32_r(m_IR[1] >> 4); + m_TMP1 = r32_r(m_IR[1]); + set_nzv32(m_TMP1); + write16(m_TMP2, m_TMP1 >> 16); + write16(m_TMP2+2, m_TMP1); prefetch_done(); 01006b00 fffffff8 0 mov.l abs16 r32l h prefetch_start - TMP2 = int16_t(IR[2]); - TMP1 = read16(TMP2) << 16; - TMP1 |= read16(TMP2+2); - set_nzv32(TMP1); - r32_w(IR[1], TMP1); + m_TMP2 = int16_t(m_IR[2]); + m_TMP1 = read16(m_TMP2) << 16; + m_TMP1 |= read16(m_TMP2+2); + set_nzv32(m_TMP1); + r32_w(m_IR[1], m_TMP1); prefetch_done(); 01006b20 fffffff8 0 mov.l abs32 r32l h prefetch_start - TMP2 = (IR[2] << 16) | IR[3]; - TMP1 = read16(TMP2) << 16; - TMP1 |= read16(TMP2+2); - set_nzv32(TMP1); - r32_w(IR[1], TMP1); + m_TMP2 = (m_IR[2] << 16) | m_IR[3]; + m_TMP1 = read16(m_TMP2) << 16; + m_TMP1 |= read16(m_TMP2+2); + set_nzv32(m_TMP1); + r32_w(m_IR[1], m_TMP1); prefetch_done(); 01006b80 fffffff8 0 mov.l r32l abs16 h prefetch_start - TMP1 = r32_r(IR[1]); - TMP2 = int16_t(IR[2]); - set_nzv32(TMP1); - write16(TMP2, TMP1 >> 16); - write16(TMP2+2, TMP1); + m_TMP1 = r32_r(m_IR[1]); + m_TMP2 = int16_t(m_IR[2]); + set_nzv32(m_TMP1); + write16(m_TMP2, m_TMP1 >> 16); + write16(m_TMP2+2, m_TMP1); prefetch_done(); 01006ba0 fffffff8 0 mov.l r32l abs32 h prefetch_start - TMP1 = r32_r(IR[1]); - TMP2 = (IR[2] << 16) | IR[3]; - set_nzv32(TMP1); - write16(TMP2, TMP1 >> 16); - write16(TMP2+2, TMP1); + m_TMP1 = r32_r(m_IR[1]); + m_TMP2 = (m_IR[2] << 16) | m_IR[3]; + set_nzv32(m_TMP1); + write16(m_TMP2, m_TMP1 >> 16); + write16(m_TMP2+2, m_TMP1); prefetch_done(); 01006d00 ffffff88 0 mov.l r32ph r32l h prefetch_start internal(1); - TMP2 = r32_r(IR[1] >> 4); - TMP1 = read16(TMP2) << 16; - TMP1 |= read16(TMP2+2); - TMP2 += 4; - r32_w(IR[1] >> 4, TMP2); - set_nzv32(TMP1); - r32_w(IR[1], TMP1); + m_TMP2 = r32_r(m_IR[1] >> 4); + m_TMP1 = read16(m_TMP2) << 16; + m_TMP1 |= read16(m_TMP2+2); + m_TMP2 += 4; + r32_w(m_IR[1] >> 4, m_TMP2); + set_nzv32(m_TMP1); + r32_w(m_IR[1], m_TMP1); prefetch_done(); 01006d80 ffffff88 0 mov.l r32l pr32h h prefetch_start internal(1); - TMP1 = r32_r(IR[1]); - TMP2 = r32_r(IR[1] >> 4); - TMP2 -= 4; - r32_w(IR[1] >> 4, TMP2); - write16(TMP2, TMP1 >> 16); - write16(TMP2+2, TMP1); - set_nzv32(TMP1); + m_TMP1 = r32_r(m_IR[1]); + m_TMP2 = r32_r(m_IR[1] >> 4); + m_TMP2 -= 4; + r32_w(m_IR[1] >> 4, m_TMP2); + write16(m_TMP2, m_TMP1 >> 16); + write16(m_TMP2+2, m_TMP1); + set_nzv32(m_TMP1); prefetch_done(); 01006f00 ffffff88 0 mov.l r32d16h r32l h prefetch_start - TMP1 = r32_r(IR[1] >> 4) + int16_t(IR[2]); - TMP2 = read16(TMP1) << 16; - TMP2 |= read16(TMP1+2); - set_nzv32(TMP2); - r32_w(IR[1], TMP2); + m_TMP1 = r32_r(m_IR[1] >> 4) + int16_t(m_IR[2]); + m_TMP2 = read16(m_TMP1) << 16; + m_TMP2 |= read16(m_TMP1+2); + set_nzv32(m_TMP2); + r32_w(m_IR[1], m_TMP2); prefetch_done(); 01006f80 ffffff88 0 mov.l r32l r32d16h h prefetch_start - TMP1 = r32_r(IR[1] >> 4) + int16_t(IR[2]); - TMP2 = r32_r(IR[1]); - set_nzv32(TMP2); - write16(TMP1, TMP2 >> 16); - write16(TMP1+2, TMP2); + m_TMP1 = r32_r(m_IR[1] >> 4) + int16_t(m_IR[2]); + m_TMP2 = r32_r(m_IR[1]); + set_nzv32(m_TMP2); + write16(m_TMP1, m_TMP2 >> 16); + write16(m_TMP1+2, m_TMP2); prefetch_done(); 010078006b20 ffffff0ffff8 0 mov.l r32d32hh r32l h prefetch_start - TMP1 = r32_r(IR[1] >> 4) + (IR[3] << 16) + IR[4]; - TMP2 = read16(TMP1) << 16; - TMP2 |= read16(TMP1+2); - set_nzv32(TMP2); - r32_w(IR[2], TMP2); + m_TMP1 = r32_r(m_IR[1] >> 4) + (m_IR[3] << 16) + m_IR[4]; + m_TMP2 = read16(m_TMP1) << 16; + m_TMP2 |= read16(m_TMP1+2); + set_nzv32(m_TMP2); + r32_w(m_IR[2], m_TMP2); prefetch_done(); 010078006ba0 ffffff0ffff8 0 mov.l r32l r32d32hh h prefetch_start - TMP1 = r32_r(IR[1] >> 4) + (IR[3] << 16) + IR[4]; - TMP2 = r32_r(IR[2]); - set_nzv32(TMP2); - write16(TMP1, TMP2 >> 16); - write16(TMP1+2, TMP2); + m_TMP1 = r32_r(m_IR[1] >> 4) + (m_IR[3] << 16) + m_IR[4]; + m_TMP2 = r32_r(m_IR[2]); + set_nzv32(m_TMP2); + write16(m_TMP1, m_TMP2 >> 16); + write16(m_TMP1+2, m_TMP2); prefetch_done(); 01106d71 fffffff9 0 ldm.l spp r32n2l s20 prefetch_start internal(1); - TMP1 = r32_r(7); - TMP2 = read16(TMP1) << 16; - TMP2 |= read16(TMP1+2); - r32_w(IR[1], TMP2); - if((IR[1] & 7) == 7) - TMP1 = TMP2; - TMP1 += 4; - r32_w(7, TMP1); - TMP2 = read16(TMP1) << 16; - TMP2 |= read16(TMP1+2); - r32_w(IR[1]-1, TMP2); - TMP1 += 4; - r32_w(7, TMP1); + m_TMP1 = r32_r(7); + m_TMP2 = read16(m_TMP1) << 16; + m_TMP2 |= read16(m_TMP1+2); + r32_w(m_IR[1], m_TMP2); + if((m_IR[1] & 7) == 7) + m_TMP1 = m_TMP2; + m_TMP1 += 4; + r32_w(7, m_TMP1); + m_TMP2 = read16(m_TMP1) << 16; + m_TMP2 |= read16(m_TMP1+2); + r32_w(m_IR[1]-1, m_TMP2); + m_TMP1 += 4; + r32_w(7, m_TMP1); prefetch_done(); 01106df0 fffffff9 0 stm.l r32n2l psp s20 prefetch_start internal(1); - TMP1 = r32_r(7); - TMP1 -= 4; - r32_w(7, TMP1); - TMP2 = r32_r(IR[1]); - write16(TMP1, TMP2 >> 16); - write16(TMP1+2, TMP2); - TMP1 -= 4; - r32_w(7, TMP1); - TMP2 = r32_r(IR[1]+1); - write16(TMP1, TMP2 >> 16); - write16(TMP1+2, TMP2); + m_TMP1 = r32_r(7); + m_TMP1 -= 4; + r32_w(7, m_TMP1); + m_TMP2 = r32_r(m_IR[1]); + write16(m_TMP1, m_TMP2 >> 16); + write16(m_TMP1+2, m_TMP2); + m_TMP1 -= 4; + r32_w(7, m_TMP1); + m_TMP2 = r32_r(m_IR[1]+1); + write16(m_TMP1, m_TMP2 >> 16); + write16(m_TMP1+2, m_TMP2); prefetch_done(); 01206d72 fffffffb 0 ldm.l spp r32n3l s20 prefetch_start internal(1); - TMP1 = r32_r(7); - TMP2 = read16(TMP1) << 16; - TMP2 |= read16(TMP1+2); - r32_w(IR[1], TMP2); - TMP1 += 4; - r32_w(7, TMP1); - TMP2 = read16(TMP1) << 16; - TMP2 |= read16(TMP1+2); - r32_w(IR[1]-1, TMP2); - TMP1 += 4; - r32_w(7, TMP1); - TMP2 = read16(TMP1) << 16; - TMP2 |= read16(TMP1+2); - r32_w(IR[1]-2, TMP2); - TMP1 += 4; - r32_w(7, TMP1); + m_TMP1 = r32_r(7); + m_TMP2 = read16(m_TMP1) << 16; + m_TMP2 |= read16(m_TMP1+2); + r32_w(m_IR[1], m_TMP2); + m_TMP1 += 4; + r32_w(7, m_TMP1); + m_TMP2 = read16(m_TMP1) << 16; + m_TMP2 |= read16(m_TMP1+2); + r32_w(m_IR[1]-1, m_TMP2); + m_TMP1 += 4; + r32_w(7, m_TMP1); + m_TMP2 = read16(m_TMP1) << 16; + m_TMP2 |= read16(m_TMP1+2); + r32_w(m_IR[1]-2, m_TMP2); + m_TMP1 += 4; + r32_w(7, m_TMP1); prefetch_done(); 01206df0 fffffffb 0 stm.l r32n3l psp s20 prefetch_start internal(1); - TMP1 = r32_r(7); - TMP1 -= 4; - r32_w(7, TMP1); - TMP2 = r32_r(IR[1]); - write16(TMP1, TMP2 >> 16); - write16(TMP1+2, TMP2); - TMP1 -= 4; - r32_w(7, TMP1); - TMP2 = r32_r(IR[1]+1); - write16(TMP1, TMP2 >> 16); - write16(TMP1+2, TMP2); - TMP1 -= 4; - r32_w(7, TMP1); - TMP2 = r32_r(IR[1]+2); - write16(TMP1, TMP2 >> 16); - write16(TMP1+2, TMP2); + m_TMP1 = r32_r(7); + m_TMP1 -= 4; + r32_w(7, m_TMP1); + m_TMP2 = r32_r(m_IR[1]); + write16(m_TMP1, m_TMP2 >> 16); + write16(m_TMP1+2, m_TMP2); + m_TMP1 -= 4; + r32_w(7, m_TMP1); + m_TMP2 = r32_r(m_IR[1]+1); + write16(m_TMP1, m_TMP2 >> 16); + write16(m_TMP1+2, m_TMP2); + m_TMP1 -= 4; + r32_w(7, m_TMP1); + m_TMP2 = r32_r(m_IR[1]+2); + write16(m_TMP1, m_TMP2 >> 16); + write16(m_TMP1+2, m_TMP2); prefetch_done(); 01306d73 fffffffb 0 ldm.l spp r32n4l s20 prefetch_start internal(1); - TMP1 = r32_r(7); - TMP2 = read16(TMP1) << 16; - TMP2 |= read16(TMP1+2); - r32_w(IR[1], TMP2); - if((IR[1] & 7) == 7) - TMP1 = TMP2; - TMP1 += 4; - r32_w(7, TMP1); - TMP2 = read16(TMP1) << 16; - TMP2 |= read16(TMP1+2); - r32_w(IR[1]-1, TMP2); - TMP1 += 4; - r32_w(7, TMP1); - TMP2 = read16(TMP1) << 16; - TMP2 |= read16(TMP1+2); - r32_w(IR[1]-2, TMP2); - TMP1 += 4; - r32_w(7, TMP1); - TMP2 = read16(TMP1) << 16; - TMP2 |= read16(TMP1+2); - r32_w(IR[1]-3, TMP2); - TMP1 += 4; - r32_w(7, TMP1); + m_TMP1 = r32_r(7); + m_TMP2 = read16(m_TMP1) << 16; + m_TMP2 |= read16(m_TMP1+2); + r32_w(m_IR[1], m_TMP2); + if((m_IR[1] & 7) == 7) + m_TMP1 = m_TMP2; + m_TMP1 += 4; + r32_w(7, m_TMP1); + m_TMP2 = read16(m_TMP1) << 16; + m_TMP2 |= read16(m_TMP1+2); + r32_w(m_IR[1]-1, m_TMP2); + m_TMP1 += 4; + r32_w(7, m_TMP1); + m_TMP2 = read16(m_TMP1) << 16; + m_TMP2 |= read16(m_TMP1+2); + r32_w(m_IR[1]-2, m_TMP2); + m_TMP1 += 4; + r32_w(7, m_TMP1); + m_TMP2 = read16(m_TMP1) << 16; + m_TMP2 |= read16(m_TMP1+2); + r32_w(m_IR[1]-3, m_TMP2); + m_TMP1 += 4; + r32_w(7, m_TMP1); prefetch_done(); 01306df0 fffffffb 0 stm.l r32n4l psp s20 prefetch_start internal(1); - TMP1 = r32_r(7); - TMP1 -= 4; - r32_w(7, TMP1); - TMP2 = r32_r(IR[1]); - write16(TMP1, TMP2 >> 16); - write16(TMP1+2, TMP2); - TMP1 -= 4; - r32_w(7, TMP1); - TMP2 = r32_r(IR[1]+1); - write16(TMP1, TMP2 >> 16); - write16(TMP1+2, TMP2); - TMP1 -= 4; - r32_w(7, TMP1); - TMP2 = r32_r(IR[1]+2); - write16(TMP1, TMP2 >> 16); - write16(TMP1+2, TMP2); - TMP1 -= 4; - r32_w(7, TMP1); - TMP2 = r32_r(IR[1]+3); - write16(TMP1, TMP2 >> 16); - write16(TMP1+2, TMP2); + m_TMP1 = r32_r(7); + m_TMP1 -= 4; + r32_w(7, m_TMP1); + m_TMP2 = r32_r(m_IR[1]); + write16(m_TMP1, m_TMP2 >> 16); + write16(m_TMP1+2, m_TMP2); + m_TMP1 -= 4; + r32_w(7, m_TMP1); + m_TMP2 = r32_r(m_IR[1]+1); + write16(m_TMP1, m_TMP2 >> 16); + write16(m_TMP1+2, m_TMP2); + m_TMP1 -= 4; + r32_w(7, m_TMP1); + m_TMP2 = r32_r(m_IR[1]+2); + write16(m_TMP1, m_TMP2 >> 16); + write16(m_TMP1+2, m_TMP2); + m_TMP1 -= 4; + r32_w(7, m_TMP1); + m_TMP2 = r32_r(m_IR[1]+3); + write16(m_TMP1, m_TMP2 >> 16); + write16(m_TMP1+2, m_TMP2); prefetch_done(); 01406900 ffffff8f 0 ldc.w r32ih ccr h prefetch_start - TMP1 = r32_r(IR[1] >> 4); - CCR = read16(TMP1) >> 8; + m_TMP1 = r32_r(m_IR[1] >> 4); + m_CCR = read16(m_TMP1) >> 8; update_irq_filter(); prefetch_done_noirq(); 01406980 ffffff8f 0 stc.w ccr r32ih h prefetch_start - TMP1 = r32_r(IR[1] >> 4); - write16(TMP1, (CCR << 8) | CCR); + m_TMP1 = r32_r(m_IR[1] >> 4); + write16(m_TMP1, (m_CCR << 8) | m_CCR); prefetch_done(); 01406b00 ffffffff 0 ldc.w abs16 ccr h prefetch_start - TMP1 = int16_t(IR[2]); - CCR = read16(TMP1) >> 8; + m_TMP1 = int16_t(m_IR[2]); + m_CCR = read16(m_TMP1) >> 8; update_irq_filter(); prefetch_done_noirq(); 01406b20 ffffffff 0 ldc.w abs32 ccr h prefetch_start - TMP1 = (IR[2] << 16) | IR[3]; - CCR = read16(TMP1) >> 8; + m_TMP1 = (m_IR[2] << 16) | m_IR[3]; + m_CCR = read16(m_TMP1) >> 8; update_irq_filter(); prefetch_done_noirq(); 01406b80 ffffffff 0 stc.w ccr abs16 h prefetch_start - TMP1 = int16_t(IR[2]); - write16(TMP1, (CCR << 8) | CCR); + m_TMP1 = int16_t(m_IR[2]); + write16(m_TMP1, (m_CCR << 8) | m_CCR); prefetch_done(); 01406ba0 ffffffff 0 stc.w ccr abs32 h prefetch_start - TMP1 = (IR[2] << 16) | IR[3]; - write16(TMP1, (CCR << 8) | CCR); + m_TMP1 = (m_IR[2] << 16) | m_IR[3]; + write16(m_TMP1, (m_CCR << 8) | m_CCR); prefetch_done(); 01406d00 ffffff8f 0 ldc.w r32ph ccr h prefetch_start internal(1); - TMP1 = r32_r(IR[1] >> 4); - r32_w(IR[1] >> 4, TMP1+2); - CCR = read16(TMP1) >> 8; + m_TMP1 = r32_r(m_IR[1] >> 4); + r32_w(m_IR[1] >> 4, m_TMP1+2); + m_CCR = read16(m_TMP1) >> 8; update_irq_filter(); prefetch_done_noirq(); 01406d80 ffffff8f 0 stc.w ccr pr32h h prefetch_start internal(1); - TMP1 = r32_r(IR[1] >> 4) - 2; - r32_w(IR[1] >> 4, TMP1); - write16(TMP1, (CCR << 8) | CCR); + m_TMP1 = r32_r(m_IR[1] >> 4) - 2; + r32_w(m_IR[1] >> 4, m_TMP1); + write16(m_TMP1, (m_CCR << 8) | m_CCR); prefetch_done(); 01406f00 ffffff8f 0 ldc.w r32d16h ccr h prefetch_start - TMP1 = r32_r(IR[1] >> 4) + int16_t(IR[2]); - CCR = read16(TMP1) >> 8; + m_TMP1 = r32_r(m_IR[1] >> 4) + int16_t(m_IR[2]); + m_CCR = read16(m_TMP1) >> 8; update_irq_filter(); prefetch_done_noirq(); 01406f80 ffffff8f 0 stc.w ccr r32d16h h prefetch_start - TMP1 = r32_r(IR[1] >> 4) + int16_t(IR[2]); - write16(TMP1, (CCR << 8) | CCR); + m_TMP1 = r32_r(m_IR[1] >> 4) + int16_t(m_IR[2]); + write16(m_TMP1, (m_CCR << 8) | m_CCR); prefetch_done(); 014078006b20 ffffff8fffff 0 ldc.w r32d32hh ccr h prefetch_start - TMP1 = r32_r(IR[1] >> 4) + (IR[3] << 16) + IR[4]; - CCR = read16(TMP1) >> 8; + m_TMP1 = r32_r(m_IR[1] >> 4) + (m_IR[3] << 16) + m_IR[4]; + m_CCR = read16(m_TMP1) >> 8; update_irq_filter(); prefetch_done_noirq(); 014078806ba0 ffffff8fffff 0 stc.w ccr r32d32hh h prefetch_start - TMP1 = r32_r(IR[1] >> 4) + (IR[3] << 16) + IR[4]; - write16(TMP1, (CCR << 8) | CCR); + m_TMP1 = r32_r(m_IR[1] >> 4) + (m_IR[3] << 16) + m_IR[4]; + write16(m_TMP1, (m_CCR << 8) | m_CCR); prefetch_done(); 01410400 ffffff00 0 orc imm8 exr s20 - EXR |= IR[1]; + m_EXR |= m_IR[1]; update_irq_filter(); prefetch_noirq 01410500 ffffff00 0 xorc imm8 exr s20 - EXR ^= IR[1] & ~EXR_NC; + m_EXR ^= m_IR[1] & ~EXR_NC; update_irq_filter(); prefetch_noirq 01410600 ffffff00 0 andc imm8 exr s20 - EXR &= IR[1] | EXR_NC; + m_EXR &= m_IR[1] | EXR_NC; update_irq_filter(); prefetch_noirq 01410700 ffffff00 0 ldc imm8 exr s20 - EXR = IR[1] | EXR_NC; + m_EXR = m_IR[1] | EXR_NC; update_irq_filter(); prefetch_noirq 01416900 ffffff8f 0 ldc.w r32ih exr s20 prefetch_start - TMP1 = r32_r(IR[1] >> 4); - EXR = (read16(TMP1) >> 8) | EXR_NC; + m_TMP1 = r32_r(m_IR[1] >> 4); + m_EXR = (read16(m_TMP1) >> 8) | EXR_NC; update_irq_filter(); prefetch_done_noirq(); 01416980 ffffff8f 0 stc.w exr r32ih s20 prefetch_start - TMP1 = r32_r(IR[1] >> 4); - write16(TMP1, (EXR << 8) | EXR); + m_TMP1 = r32_r(m_IR[1] >> 4); + write16(m_TMP1, (m_EXR << 8) | m_EXR); prefetch_done(); 01416b00 ffffffff 0 ldc.w abs16 exr s20 prefetch_start - TMP1 = int16_t(IR[2]); - EXR = (read16(TMP1) >> 8) | EXR_NC; + m_TMP1 = int16_t(m_IR[2]); + m_EXR = (read16(m_TMP1) >> 8) | EXR_NC; update_irq_filter(); prefetch_done_noirq(); 01416b20 ffffffff 0 ldc.w abs32 exr s20 prefetch_start - TMP1 = (IR[2] << 16) | IR[3]; - EXR = (read16(TMP1) >> 8) | EXR_NC; + m_TMP1 = (m_IR[2] << 16) | m_IR[3]; + m_EXR = (read16(m_TMP1) >> 8) | EXR_NC; update_irq_filter(); prefetch_done_noirq(); 01416b80 ffffffff 0 stc.w exr abs16 s20 prefetch_start - TMP1 = int16_t(IR[2]); - write16(TMP1, (EXR << 8) | EXR); + m_TMP1 = int16_t(m_IR[2]); + write16(m_TMP1, (m_EXR << 8) | m_EXR); prefetch_done(); 01416ba0 ffffffff 0 stc.w exr abs32 s20 prefetch_start - TMP1 = (IR[2] << 16) | IR[3]; - write16(TMP1, (EXR << 8) | EXR); + m_TMP1 = (m_IR[2] << 16) | m_IR[3]; + write16(m_TMP1, (m_EXR << 8) | m_EXR); prefetch_done(); 01416d00 ffffff8f 0 ldc.w r32ph exr s20 prefetch_start internal(1); - TMP1 = r32_r(IR[1] >> 4); - r32_w(IR[1] >> 4, TMP1+2); - EXR = (read16(TMP1) >> 8) | EXR_NC; + m_TMP1 = r32_r(m_IR[1] >> 4); + r32_w(m_IR[1] >> 4, m_TMP1+2); + m_EXR = (read16(m_TMP1) >> 8) | EXR_NC; update_irq_filter(); prefetch_done_noirq(); 01416d80 ffffff8f 0 stc.w exr pr32h s20 prefetch_start internal(1); - TMP1 = r32_r(IR[1] >> 4) - 2; - r32_w(IR[1] >> 4, TMP1); - write16(TMP1, (EXR << 8) | EXR); + m_TMP1 = r32_r(m_IR[1] >> 4) - 2; + r32_w(m_IR[1] >> 4, m_TMP1); + write16(m_TMP1, (m_EXR << 8) | m_EXR); prefetch_done(); 01416f00 ffffff8f 0 ldc.w r32d16h exr s20 prefetch_start - TMP1 = r32_r(IR[1] >> 4) + int16_t(IR[2]); - EXR = (read16(TMP1) >> 8) | EXR_NC; + m_TMP1 = r32_r(m_IR[1] >> 4) + int16_t(m_IR[2]); + m_EXR = (read16(m_TMP1) >> 8) | EXR_NC; update_irq_filter(); prefetch_done_noirq(); 01416f80 ffffff8f 0 stc.w exr r32d16h s20 prefetch_start - TMP1 = r32_r(IR[1] >> 4) + int16_t(IR[2]); - write16(TMP1, (EXR << 8) | EXR); + m_TMP1 = r32_r(m_IR[1] >> 4) + int16_t(m_IR[2]); + write16(m_TMP1, (m_EXR << 8) | m_EXR); prefetch_done(); 014178006b20 ffffff8fffff 0 ldc.w r32d32hh exr s20 prefetch_start - TMP1 = r32_r(IR[1] >> 4) + (IR[3] << 16) + IR[4]; - EXR = (read16(TMP1) >> 8) | EXR_NC; + m_TMP1 = r32_r(m_IR[1] >> 4) + (m_IR[3] << 16) + m_IR[4]; + m_EXR = (read16(m_TMP1) >> 8) | EXR_NC; update_irq_filter(); prefetch_done_noirq(); 014178806ba0 ffffff8fffff 0 stc.w exr r32d32hh s20 prefetch_start - TMP1 = r32_r(IR[1] >> 4) + (IR[3] << 16) + IR[4]; - write16(TMP1, (EXR << 8) | EXR); + m_TMP1 = r32_r(m_IR[1] >> 4) + (m_IR[3] << 16) + m_IR[4]; + write16(m_TMP1, (m_EXR << 8) | m_EXR); prefetch_done(); 01606d00 ffffff88 0 mac r32ph r32pl s26 prefetch_start - TMP1 = read16(r32_r(IR[1])); - r32_w(IR[1], r32_r(IR[1]) + 2); - TMP2 = read16(r32_r(IR[1] >> 4)); - r32_w(IR[1] >> 4, r32_r(IR[1] >> 4) + 2); - MAC += int16_t(TMP1)*int16_t(TMP2); - MACF &= ~(F_Z|F_N); - if(MAC) - MACF |= F_Z; - else if(MAC < 0) - MACF |= F_N; - if(mac_saturating) { - if(MAC < -0x80000000LL) { - MAC = -0x80000000LL; - MACF |= F_V; - } else if(MAC > 0x7fffffffLL) { - MAC = 0x7fffffffLL; - MACF |= F_V; + m_TMP1 = read16(r32_r(m_IR[1])); + r32_w(m_IR[1], r32_r(m_IR[1]) + 2); + m_TMP2 = read16(r32_r(m_IR[1] >> 4)); + r32_w(m_IR[1] >> 4, r32_r(m_IR[1] >> 4) + 2); + m_MAC += int16_t(m_TMP1)*int16_t(m_TMP2); + m_MACF &= ~(F_Z|F_N); + if(m_MAC) + m_MACF |= F_Z; + else if(m_MAC < 0) + m_MACF |= F_N; + if(m_mac_saturating) { + if(m_MAC < -0x80000000LL) { + m_MAC = -0x80000000LL; + m_MACF |= F_V; + } else if(m_MAC > 0x7fffffffLL) { + m_MAC = 0x7fffffffLL; + m_MACF |= F_V; } } else { - if(MAC < -0x20000000000LL) { - MAC = -0x20000000000LL; - MACF |= F_V; - } else if(MAC > 0x1ffffffffffLL) { - MAC = 0x1ffffffffffLL; - MACF |= F_V; + if(m_MAC < -0x20000000000LL) { + m_MAC = -0x20000000000LL; + m_MACF |= F_V; + } else if(m_MAC > 0x1ffffffffffLL) { + m_MAC = 0x1ffffffffffLL; + m_MACF |= F_V; } } prefetch_done(); 0180 ffff 0 sleep - - prefetch_start - while(!irq_vector) { + while(!m_irq_vector) { eat-all-cycles; } prefetch_done(); @@ -744,34 +744,34 @@ macro jsr32 %opc %spreg 01a0 ffff 0 clrmac - - s26 prefetch_start internal(1); - MAC = 0; - MACF &= ~F_V; + m_MAC = 0; + m_MACF &= ~F_V; prefetch_done(); 01c05000 ffffff00 0 mulxs.b r8h r16l h prefetch_start - TMP1 = int8_t(r16_r(IR[1])) * int8_t(r8_r(IR[1] >> 4)); - set_nz16(TMP1); - r16_w(IR[1], TMP1); - internal(has_mac ? 2 : 11); + m_TMP1 = int8_t(r16_r(m_IR[1])) * int8_t(r8_r(m_IR[1] >> 4)); + set_nz16(m_TMP1); + r16_w(m_IR[1], m_TMP1); + internal(m_has_mac ? 2 : 11); prefetch_done(); 01c05200 ffffff08 0 mulxs.w r16h r32l h prefetch_start - TMP1 = int16_t(r32_r(IR[1])) * int16_t(r16_r(IR[1] >> 4)); - set_nz32(TMP1); - r32_w(IR[1], TMP1); - internal(has_mac ? 3 : 19); + m_TMP1 = int16_t(r32_r(m_IR[1])) * int16_t(r16_r(m_IR[1] >> 4)); + set_nz32(m_TMP1); + r32_w(m_IR[1], m_TMP1); + internal(m_has_mac ? 3 : 19); prefetch_done(); 01d05100 ffffff00 0 divxs.b r8h r16l h prefetch_start internal(11); - TMP1 = int16_t(r16_r(IR[1])); - TMP2 = int8_t(r8_r(IR[1] >> 4)); - CCR &= ~(F_Z|F_N); - if(!TMP2) { - CCR |= F_Z; + m_TMP1 = int16_t(r16_r(m_IR[1])); + m_TMP2 = int8_t(r8_r(m_IR[1] >> 4)); + m_CCR &= ~(F_Z|F_N); + if(!m_TMP2) { + m_CCR |= F_Z; } else { // Conditions: // p = q*d + r @@ -782,45 +782,45 @@ macro jsr32 %opc %spreg // p = -20, d = +3 -> q = -7, r = 1 // p = -20, d = -3 -> q = 7, r = -1 int q, r; - if(TMP2 < 0) { - if(TMP1 < 0) { // - - - q = (-TMP1) / (-TMP2); - r = (-TMP1) % (-TMP2); + if(m_TMP2 < 0) { + if(m_TMP1 < 0) { // - - + q = (-m_TMP1) / (-m_TMP2); + r = (-m_TMP1) % (-m_TMP2); if(r) { - r = r + TMP2; + r = r + m_TMP2; q++; } } else { // + - - CCR |= F_N; - q = -(TMP1 / (-TMP2)); - r = -(TMP1 % (-TMP2)); + m_CCR |= F_N; + q = -(m_TMP1 / (-m_TMP2)); + r = -(m_TMP1 % (-m_TMP2)); } } else { - if(TMP1 < 0) { // - + - CCR |= F_N; - q = -((-TMP1) / TMP2); - r = (-TMP1) % TMP2; + if(m_TMP1 < 0) { // - + + m_CCR |= F_N; + q = -((-m_TMP1) / m_TMP2); + r = (-m_TMP1) % m_TMP2; if(r) { - r = TMP2 - r; + r = m_TMP2 - r; q--; } } else { // + + - q = TMP1 / TMP2; - r = TMP1 % TMP2; + q = m_TMP1 / m_TMP2; + r = m_TMP1 % m_TMP2; } } - r16_w(IR[1], (q & 0xff) | ((r & 0xff) << 8)); + r16_w(m_IR[1], (q & 0xff) | ((r & 0xff) << 8)); } prefetch_done(); 01d05300 ffffff08 0 divxs.w r16h r32l h prefetch_start internal(19); - TMP1 = r32_r(IR[1]); - TMP2 = int16_t(r16_r(IR[1] >> 4)); - CCR &= ~(F_Z|F_N); - if(!TMP2) { - CCR |= F_Z; + m_TMP1 = r32_r(m_IR[1]); + m_TMP2 = int16_t(r16_r(m_IR[1] >> 4)); + m_CCR &= ~(F_Z|F_N); + if(!m_TMP2) { + m_CCR |= F_Z; } else { // Conditions: // p = q*d + r @@ -831,609 +831,609 @@ macro jsr32 %opc %spreg // p = -20, d = +3 -> q = -7, r = 1 // p = -20, d = -3 -> q = 7, r = -1 int q, r; - if(TMP2 < 0) { - if(TMP1 < 0) { // - - - q = (-TMP1) / (-TMP2); - r = (-TMP1) % (-TMP2); + if(m_TMP2 < 0) { + if(m_TMP1 < 0) { // - - + q = (-m_TMP1) / (-m_TMP2); + r = (-m_TMP1) % (-m_TMP2); if(r) { - r = r + TMP2; + r = r + m_TMP2; q++; } } else { // + - - CCR |= F_N; - q = -(TMP1 / (-TMP2)); - r = -(TMP1 % (-TMP2)); + m_CCR |= F_N; + q = -(m_TMP1 / (-m_TMP2)); + r = -(m_TMP1 % (-m_TMP2)); } } else { - if(TMP1 < 0) { // - + - CCR |= F_N; - q = -((-TMP1) / TMP2); - r = (-TMP1) % TMP2; + if(m_TMP1 < 0) { // - + + m_CCR |= F_N; + q = -((-m_TMP1) / m_TMP2); + r = (-m_TMP1) % m_TMP2; if(r) { - r = TMP2 - r; + r = m_TMP2 - r; q--; } } else { // + + - q = TMP1 / TMP2; - r = TMP1 % TMP2; + q = m_TMP1 / m_TMP2; + r = m_TMP1 % m_TMP2; } } - r32_w(IR[1], (q & 0xffff) | ((r & 0xffff) << 16)); + r32_w(m_IR[1], (q & 0xffff) | ((r & 0xffff) << 16)); } prefetch_done(); 01e07b0c ffffffaf 0 tas r32ih - s20 prefetch_start - TMP1 = r32_r(IR[1] >> 4); - TMP2 = read8(TMP1); - set_nzv8(TMP2); - write8(TMP1, TMP2 | 0x80); + m_TMP1 = r32_r(m_IR[1] >> 4); + m_TMP2 = read8(m_TMP1); + set_nzv8(m_TMP2); + write8(m_TMP1, m_TMP2 | 0x80); prefetch_done(); 01f06400 ffffff88 0 or.l r32h r32l h - TMP1 = r32_r(IR[1] >> 4) | r32_r(IR[1]); - set_nzv32(TMP1); - r32_w(IR[1], TMP1); + m_TMP1 = r32_r(m_IR[1] >> 4) | r32_r(m_IR[1]); + set_nzv32(m_TMP1); + r32_w(m_IR[1], m_TMP1); prefetch 01f06500 ffffff88 0 xor.l r32h r32l h - TMP1 = r32_r(IR[1] >> 4) ^ r32_r(IR[1]); - set_nzv32(TMP1); - r32_w(IR[1], TMP1); + m_TMP1 = r32_r(m_IR[1] >> 4) ^ r32_r(m_IR[1]); + set_nzv32(m_TMP1); + r32_w(m_IR[1], m_TMP1); prefetch 01f06600 ffffff88 0 and.l r32h r32l h - TMP1 = r32_r(IR[1] >> 4) & r32_r(IR[1]); - set_nzv32(TMP1); - r32_w(IR[1], TMP1); + m_TMP1 = r32_r(m_IR[1] >> 4) & r32_r(m_IR[1]); + set_nzv32(m_TMP1); + r32_w(m_IR[1], m_TMP1); prefetch 0200 fff0 0 stc ccr r8l - r8_w(IR[0], CCR); + r8_w(m_IR[0], m_CCR); prefetch 0210 fff0 0 stc exr r8l s20 - r8_w(IR[0], EXR); + r8_w(m_IR[0], m_EXR); prefetch 0220 fff8 0 stmac mach r32l s26 - r32_w(IR[0], MAC >> 32); - CCR = (CCR & ~(F_V|F_N|F_Z)) | MACF; + r32_w(m_IR[0], m_MAC >> 32); + m_CCR = (m_CCR & ~(F_V|F_N|F_Z)) | m_MACF; prefetch 0230 fff8 0 stmac macl r32l s26 - r32_w(IR[0], MAC); - CCR = (CCR & ~(F_V|F_N|F_Z)) | MACF; + r32_w(m_IR[0], m_MAC); + m_CCR = (m_CCR & ~(F_V|F_N|F_Z)) | m_MACF; prefetch 0300 fff0 0 ldc r8l ccr - CCR = r8_r(IR[0]); + m_CCR = r8_r(m_IR[0]); update_irq_filter(); prefetch_noirq 0310 fff0 0 ldc r8l exr s20 - EXR = r8_r(IR[0]) | EXR_NC; + m_EXR = r8_r(m_IR[0]) | EXR_NC; update_irq_filter(); prefetch_noirq 0320 fff8 0 ldmac r32l mach s26 prefetch_start internal(1); - TMP1 = r32_r(IR[0]); - if(TMP1 & 0x200) - TMP1 |= 0xfffffc00; + m_TMP1 = r32_r(m_IR[0]); + if(m_TMP1 & 0x200) + m_TMP1 |= 0xfffffc00; else - TMP1 &= ~0xfffffc00; - MAC = (MAC & 0x00000000ffffffffULL) | (uint64_t(TMP1) << 32); - MACF &= ~F_V; + m_TMP1 &= ~0xfffffc00; + m_MAC = (m_MAC & 0x00000000ffffffffULL) | (uint64_t(m_TMP1) << 32); + m_MACF &= ~F_V; prefetch_done(); 0330 fff8 0 ldmac r32l macl s26 prefetch_start internal(1); - MAC = (MAC & 0xffffffff00000000ULL) | r32_r(IR[0]); - MACF &= ~F_V; + m_MAC = (m_MAC & 0xffffffff00000000ULL) | r32_r(m_IR[0]); + m_MACF &= ~F_V; prefetch_done(); 0400 ff00 0 orc imm8 ccr - CCR |= IR[0]; + m_CCR |= m_IR[0]; update_irq_filter(); prefetch_noirq 0500 ff00 0 xorc imm8 ccr - CCR ^= IR[0]; + m_CCR ^= m_IR[0]; update_irq_filter(); prefetch_noirq 0600 ff00 0 andc imm8 ccr - CCR &= IR[0]; + m_CCR &= m_IR[0]; update_irq_filter(); prefetch_noirq 0700 ff00 0 ldc imm8 ccr - CCR = IR[0]; + m_CCR = m_IR[0]; update_irq_filter(); prefetch_noirq 0800 ff00 0 add.b r8h r8l - r8_w(IR[0], do_add8(r8_r(IR[0]), r8_r(IR[0] >> 4))); + r8_w(m_IR[0], do_add8(r8_r(m_IR[0]), r8_r(m_IR[0] >> 4))); prefetch 0900 ff00 0 add.w r16h r16l - r16_w(IR[0], do_add16(r16_r(IR[0]), r16_r(IR[0] >> 4))); + r16_w(m_IR[0], do_add16(r16_r(m_IR[0]), r16_r(m_IR[0] >> 4))); prefetch 0a00 fff0 0 inc.b one r8l - r8_w(IR[0], do_inc8(r8_r(IR[0]), 1)); + r8_w(m_IR[0], do_inc8(r8_r(m_IR[0]), 1)); prefetch 0a80 ff88 0 add.l r32h r32l h - r32_w(IR[0], do_add32(r32_r(IR[0]), r32_r(IR[0] >> 4))); + r32_w(m_IR[0], do_add32(r32_r(m_IR[0]), r32_r(m_IR[0] >> 4))); prefetch 0b00 fff8 0 adds.l one r16l o - r16_w(IR[0], r16_r(IR[0])+1); + r16_w(m_IR[0], r16_r(m_IR[0])+1); prefetch 0b00 fff8 0 adds.l one r32l h - r32_w(IR[0], r32_r(IR[0])+1); + r32_w(m_IR[0], r32_r(m_IR[0])+1); prefetch 0b50 fff0 0 inc.w one r16l h - r16_w(IR[0], do_inc16(r16_r(IR[0]), 1)); + r16_w(m_IR[0], do_inc16(r16_r(m_IR[0]), 1)); prefetch 0b70 fff8 0 inc.l one r32l h - r32_w(IR[0], do_inc32(r32_r(IR[0]), 1)); + r32_w(m_IR[0], do_inc32(r32_r(m_IR[0]), 1)); prefetch 0b80 fff8 0 adds.l two r16l o - r16_w(IR[0], r16_r(IR[0])+2); + r16_w(m_IR[0], r16_r(m_IR[0])+2); prefetch 0b80 fff8 0 adds.l two r32l h - r32_w(IR[0], r32_r(IR[0])+2); + r32_w(m_IR[0], r32_r(m_IR[0])+2); prefetch 0b90 fff8 0 adds.l four r16l o - r16_w(IR[0], r16_r(IR[0])+4); + r16_w(m_IR[0], r16_r(m_IR[0])+4); prefetch 0b90 fff8 0 adds.l four r32l h - r32_w(IR[0], r32_r(IR[0])+4); + r32_w(m_IR[0], r32_r(m_IR[0])+4); prefetch 0bd0 fff0 0 inc.w two r16l h - r16_w(IR[0], do_inc16(r16_r(IR[0]), 2)); + r16_w(m_IR[0], do_inc16(r16_r(m_IR[0]), 2)); prefetch 0bf0 fff8 0 inc.l two r32l h - r32_w(IR[0], do_inc32(r32_r(IR[0]), 2)); + r32_w(m_IR[0], do_inc32(r32_r(m_IR[0]), 2)); prefetch 0c00 ff00 0 mov.b r8h r8l - TMP1 = r8_r(IR[0] >> 4); - set_nzv8(TMP1); - r8_w(IR[0], TMP1); + m_TMP1 = r8_r(m_IR[0] >> 4); + set_nzv8(m_TMP1); + r8_w(m_IR[0], m_TMP1); prefetch 0d00 ff00 0 mov.w r16h r16l - TMP1 = r16_r(IR[0] >> 4); - set_nzv16(TMP1); - r16_w(IR[0], TMP1); + m_TMP1 = r16_r(m_IR[0] >> 4); + set_nzv16(m_TMP1); + r16_w(m_IR[0], m_TMP1); prefetch 0e00 ff00 0 addx.b r8h r8l - r8_w(IR[0], do_addx8(r8_r(IR[0]), r8_r(IR[0] >> 4))); + r8_w(m_IR[0], do_addx8(r8_r(m_IR[0]), r8_r(m_IR[0] >> 4))); prefetch 0f00 fff0 0 daa.b r8l - - TMP1 = r8_r(IR[0]); - TMP2 = 0; - if(CCR & F_C) { - if(has_hc && (CCR & F_H)) { - if((TMP1 & 0xf0) <= 0x30 && (TMP1 & 0x0f) <= 3) - TMP2 = 0x66; + m_TMP1 = r8_r(m_IR[0]); + m_TMP2 = 0; + if(m_CCR & F_C) { + if(m_has_hc && (m_CCR & F_H)) { + if((m_TMP1 & 0xf0) <= 0x30 && (m_TMP1 & 0x0f) <= 3) + m_TMP2 = 0x66; } else { - if((TMP1 & 0xf0) <= 0x20) - TMP2 = (TMP1 & 0x0f) <= 9 ? 0x60 : 0x66; + if((m_TMP1 & 0xf0) <= 0x20) + m_TMP2 = (m_TMP1 & 0x0f) <= 9 ? 0x60 : 0x66; } } else { - if(has_hc && (CCR & F_H)) { - if((TMP1 & 0x0f) <= 3) - TMP2 = (TMP1 & 0xf0) <= 0x90 ? 0x06 : 0x66; + if(m_has_hc && (m_CCR & F_H)) { + if((m_TMP1 & 0x0f) <= 3) + m_TMP2 = (m_TMP1 & 0xf0) <= 0x90 ? 0x06 : 0x66; } else { - if((TMP1 & 0x0f) <= 9) - TMP2 = (TMP1 & 0xf0) <= 0x90 ? 0x00 : 0x60; + if((m_TMP1 & 0x0f) <= 9) + m_TMP2 = (m_TMP1 & 0xf0) <= 0x90 ? 0x00 : 0x60; else - TMP2 = (TMP1 & 0xf0) <= 0x80 ? 0x06 : 0x66; + m_TMP2 = (m_TMP1 & 0xf0) <= 0x80 ? 0x06 : 0x66; } } - r8_w(IR[0], do_add8(TMP1, TMP2)); + r8_w(m_IR[0], do_add8(m_TMP1, m_TMP2)); prefetch 0f80 ff88 0 mov.l r32h r32l h - TMP1 = r32_r(IR[0] >> 4); - set_nzv32(TMP1); - r32_w(IR[0], TMP1); + m_TMP1 = r32_r(m_IR[0] >> 4); + set_nzv32(m_TMP1); + r32_w(m_IR[0], m_TMP1); prefetch 1000 fff0 0 shll.b r8l - - r8_w(IR[0], do_shll8(r8_r(IR[0]))); + r8_w(m_IR[0], do_shll8(r8_r(m_IR[0]))); prefetch 1010 fff0 0 shll.w r16l - h - r16_w(IR[0], do_shll16(r16_r(IR[0]))); + r16_w(m_IR[0], do_shll16(r16_r(m_IR[0]))); prefetch 1030 fff8 0 shll.l r32l - h - r32_w(IR[0], do_shll32(r32_r(IR[0]))); + r32_w(m_IR[0], do_shll32(r32_r(m_IR[0]))); prefetch 1040 fff0 0 shll.b two r8l s20 - r8_w(IR[0], do_shll2_8(r8_r(IR[0]))); + r8_w(m_IR[0], do_shll2_8(r8_r(m_IR[0]))); prefetch 1050 fff0 0 shll.w two r16l s20 - r16_w(IR[0], do_shll2_16(r16_r(IR[0]))); + r16_w(m_IR[0], do_shll2_16(r16_r(m_IR[0]))); prefetch 1070 fff8 0 shll.l two r32l s20 - r32_w(IR[0], do_shll2_32(r32_r(IR[0]))); + r32_w(m_IR[0], do_shll2_32(r32_r(m_IR[0]))); prefetch 1080 fff0 0 shal.b r8l - - r8_w(IR[0], do_shal8(r8_r(IR[0]))); + r8_w(m_IR[0], do_shal8(r8_r(m_IR[0]))); prefetch 1090 fff0 0 shal.w r16l - h - r16_w(IR[0], do_shal16(r16_r(IR[0]))); + r16_w(m_IR[0], do_shal16(r16_r(m_IR[0]))); prefetch 10b0 fff8 0 shal.l r32l - h - r32_w(IR[0], do_shal32(r32_r(IR[0]))); + r32_w(m_IR[0], do_shal32(r32_r(m_IR[0]))); prefetch 10c0 fff0 0 shal.b two r8l s20 - r8_w(IR[0], do_shal2_8(r8_r(IR[0]))); + r8_w(m_IR[0], do_shal2_8(r8_r(m_IR[0]))); prefetch 10d0 fff0 0 shal.w two r16l s20 - r16_w(IR[0], do_shal2_16(r16_r(IR[0]))); + r16_w(m_IR[0], do_shal2_16(r16_r(m_IR[0]))); prefetch 10f0 fff8 0 shal.l two r32l s20 - r32_w(IR[0], do_shal2_32(r32_r(IR[0]))); + r32_w(m_IR[0], do_shal2_32(r32_r(m_IR[0]))); prefetch 1100 fff0 0 shlr.b r8l - - r8_w(IR[0], do_shlr8(r8_r(IR[0]))); + r8_w(m_IR[0], do_shlr8(r8_r(m_IR[0]))); prefetch 1110 fff0 0 shlr.w r16l - h - r16_w(IR[0], do_shlr16(r16_r(IR[0]))); + r16_w(m_IR[0], do_shlr16(r16_r(m_IR[0]))); prefetch 1130 fff8 0 shlr.l r32l - h - r32_w(IR[0], do_shlr32(r32_r(IR[0]))); + r32_w(m_IR[0], do_shlr32(r32_r(m_IR[0]))); prefetch 1140 fff0 0 shlr.b two r8l s20 - r8_w(IR[0], do_shlr2_8(r8_r(IR[0]))); + r8_w(m_IR[0], do_shlr2_8(r8_r(m_IR[0]))); prefetch 1150 fff0 0 shlr.w two r16l s20 - r16_w(IR[0], do_shlr2_16(r16_r(IR[0]))); + r16_w(m_IR[0], do_shlr2_16(r16_r(m_IR[0]))); prefetch 1170 fff8 0 shlr.l two r32l s20 - r32_w(IR[0], do_shlr2_32(r32_r(IR[0]))); + r32_w(m_IR[0], do_shlr2_32(r32_r(m_IR[0]))); prefetch 1180 fff0 0 shar.b r8l - - r8_w(IR[0], do_shar8(r8_r(IR[0]))); + r8_w(m_IR[0], do_shar8(r8_r(m_IR[0]))); prefetch 1190 fff0 0 shar.w r16l - h - r16_w(IR[0], do_shar16(r16_r(IR[0]))); + r16_w(m_IR[0], do_shar16(r16_r(m_IR[0]))); prefetch 11b0 fff8 0 shar.l r32l - h - r32_w(IR[0], do_shar32(r32_r(IR[0]))); + r32_w(m_IR[0], do_shar32(r32_r(m_IR[0]))); prefetch 11c0 fff0 0 shar.b two r8l s20 - r8_w(IR[0], do_shar2_8(r8_r(IR[0]))); + r8_w(m_IR[0], do_shar2_8(r8_r(m_IR[0]))); prefetch 11d0 fff0 0 shar.w two r16l s20 - r16_w(IR[0], do_shar2_16(r16_r(IR[0]))); + r16_w(m_IR[0], do_shar2_16(r16_r(m_IR[0]))); prefetch 11f0 fff8 0 shar.l two r32l s20 - r32_w(IR[0], do_shar2_32(r32_r(IR[0]))); + r32_w(m_IR[0], do_shar2_32(r32_r(m_IR[0]))); prefetch 1200 fff0 0 rotxl.b r8l - - r8_w(IR[0], do_rotxl8(r8_r(IR[0]))); + r8_w(m_IR[0], do_rotxl8(r8_r(m_IR[0]))); prefetch 1210 fff0 0 rotxl.w r16l - h - r16_w(IR[0], do_rotxl16(r16_r(IR[0]))); + r16_w(m_IR[0], do_rotxl16(r16_r(m_IR[0]))); prefetch 1230 fff8 0 rotxl.l r32l - h - r32_w(IR[0], do_rotxl32(r32_r(IR[0]))); + r32_w(m_IR[0], do_rotxl32(r32_r(m_IR[0]))); prefetch 1240 fff0 0 rotxl.b two r8l s20 - r8_w(IR[0], do_rotxl2_8(r8_r(IR[0]))); + r8_w(m_IR[0], do_rotxl2_8(r8_r(m_IR[0]))); prefetch 1250 fff0 0 rotxl.w two r16l s20 - r16_w(IR[0], do_rotxl2_16(r16_r(IR[0]))); + r16_w(m_IR[0], do_rotxl2_16(r16_r(m_IR[0]))); prefetch 1270 fff8 0 rotxl.l two r32l s20 - r32_w(IR[0], do_rotxl2_32(r32_r(IR[0]))); + r32_w(m_IR[0], do_rotxl2_32(r32_r(m_IR[0]))); prefetch 1280 fff0 0 rotl.b r8l - - r8_w(IR[0], do_rotl8(r8_r(IR[0]))); + r8_w(m_IR[0], do_rotl8(r8_r(m_IR[0]))); prefetch 1290 fff0 0 rotl.w r16l - h - r16_w(IR[0], do_rotl16(r16_r(IR[0]))); + r16_w(m_IR[0], do_rotl16(r16_r(m_IR[0]))); prefetch 12b0 fff8 0 rotl.l r32l - h - r32_w(IR[0], do_rotl32(r32_r(IR[0]))); + r32_w(m_IR[0], do_rotl32(r32_r(m_IR[0]))); prefetch 12c0 fff0 0 rotl.b two r8l s20 - r8_w(IR[0], do_rotl2_8(r8_r(IR[0]))); + r8_w(m_IR[0], do_rotl2_8(r8_r(m_IR[0]))); prefetch 12d0 fff0 0 rotl.w two r16l s20 - r16_w(IR[0], do_rotl2_16(r16_r(IR[0]))); + r16_w(m_IR[0], do_rotl2_16(r16_r(m_IR[0]))); prefetch 12f0 fff8 0 rotl.l two r32l s20 - r32_w(IR[0], do_rotl2_32(r32_r(IR[0]))); + r32_w(m_IR[0], do_rotl2_32(r32_r(m_IR[0]))); prefetch 1300 fff0 0 rotxr.b r8l - - r8_w(IR[0], do_rotxr8(r8_r(IR[0]))); + r8_w(m_IR[0], do_rotxr8(r8_r(m_IR[0]))); prefetch 1310 fff0 0 rotxr.w r16l - h - r16_w(IR[0], do_rotxr16(r16_r(IR[0]))); + r16_w(m_IR[0], do_rotxr16(r16_r(m_IR[0]))); prefetch 1330 fff8 0 rotxr.l r32l - h - r32_w(IR[0], do_rotxr32(r32_r(IR[0]))); + r32_w(m_IR[0], do_rotxr32(r32_r(m_IR[0]))); prefetch 1340 fff0 0 rotxr.b two r8l s20 - r8_w(IR[0], do_rotxr2_8(r8_r(IR[0]))); + r8_w(m_IR[0], do_rotxr2_8(r8_r(m_IR[0]))); prefetch 1350 fff0 0 rotxr.w two r16l s20 - r16_w(IR[0], do_rotxr2_16(r16_r(IR[0]))); + r16_w(m_IR[0], do_rotxr2_16(r16_r(m_IR[0]))); prefetch 1370 fff8 0 rotxr.l two r32l s20 - r32_w(IR[0], do_rotxr2_32(r32_r(IR[0]))); + r32_w(m_IR[0], do_rotxr2_32(r32_r(m_IR[0]))); prefetch 1380 fff0 0 rotr.b r8l - - r8_w(IR[0], do_rotr8(r8_r(IR[0]))); + r8_w(m_IR[0], do_rotr8(r8_r(m_IR[0]))); prefetch 1390 fff0 0 rotr.w r16l - h - r16_w(IR[0], do_rotr16(r16_r(IR[0]))); + r16_w(m_IR[0], do_rotr16(r16_r(m_IR[0]))); prefetch 13b0 fff8 0 rotr.l r32l - h - r32_w(IR[0], do_rotr32(r32_r(IR[0]))); + r32_w(m_IR[0], do_rotr32(r32_r(m_IR[0]))); prefetch 13c0 fff0 0 rotr.b two r8l s20 - r8_w(IR[0], do_rotr2_8(r8_r(IR[0]))); + r8_w(m_IR[0], do_rotr2_8(r8_r(m_IR[0]))); prefetch 13d0 fff0 0 rotr.w two r16l s20 - r16_w(IR[0], do_rotr2_16(r16_r(IR[0]))); + r16_w(m_IR[0], do_rotr2_16(r16_r(m_IR[0]))); prefetch 13f0 fff8 0 rotr.l two r32l s20 - r32_w(IR[0], do_rotr2_32(r32_r(IR[0]))); + r32_w(m_IR[0], do_rotr2_32(r32_r(m_IR[0]))); prefetch 1400 ff00 0 or.b r8h r8l - TMP1 = r8_r(IR[0] >> 4) | r8_r(IR[0]); - set_nzv8(TMP1); - r8_w(IR[0], TMP1); + m_TMP1 = r8_r(m_IR[0] >> 4) | r8_r(m_IR[0]); + set_nzv8(m_TMP1); + r8_w(m_IR[0], m_TMP1); prefetch 1500 ff00 0 xor.b r8h r8l - TMP1 = r8_r(IR[0] >> 4) ^ r8_r(IR[0]); - set_nzv8(TMP1); - r8_w(IR[0], TMP1); + m_TMP1 = r8_r(m_IR[0] >> 4) ^ r8_r(m_IR[0]); + set_nzv8(m_TMP1); + r8_w(m_IR[0], m_TMP1); prefetch 1600 ff00 0 and.b r8h r8l - TMP1 = r8_r(IR[0] >> 4) & r8_r(IR[0]); - set_nzv8(TMP1); - r8_w(IR[0], TMP1); + m_TMP1 = r8_r(m_IR[0] >> 4) & r8_r(m_IR[0]); + set_nzv8(m_TMP1); + r8_w(m_IR[0], m_TMP1); prefetch 1700 fff0 0 not.b r8l - - TMP1 = ~r8_r(IR[0]); - set_nzv8(TMP1); - r8_w(IR[0], TMP1); + m_TMP1 = ~r8_r(m_IR[0]); + set_nzv8(m_TMP1); + r8_w(m_IR[0], m_TMP1); prefetch 1710 fff0 0 not.w r16l - h - TMP1 = ~r16_r(IR[0]); - set_nzv16(TMP1); - r16_w(IR[0], TMP1); + m_TMP1 = ~r16_r(m_IR[0]); + set_nzv16(m_TMP1); + r16_w(m_IR[0], m_TMP1); prefetch 1730 fff8 0 not.l r32l - h - TMP1 = ~r32_r(IR[0]); - set_nzv32(TMP1); - r32_w(IR[0], TMP1); + m_TMP1 = ~r32_r(m_IR[0]); + set_nzv32(m_TMP1); + r32_w(m_IR[0], m_TMP1); prefetch 1750 fff0 0 extu.w r16l - h - CCR &= ~(F_N|F_Z|F_V); - TMP1 = uint8_t(r16_r(IR[0])); - if(!TMP1) - CCR |= F_Z; - r16_w(IR[0], TMP1); + m_CCR &= ~(F_N|F_Z|F_V); + m_TMP1 = uint8_t(r16_r(m_IR[0])); + if(!m_TMP1) + m_CCR |= F_Z; + r16_w(m_IR[0], m_TMP1); prefetch 1770 fff8 0 extu.l r32l - h - CCR &= ~(F_N|F_Z|F_V); - TMP1 = uint16_t(r32_r(IR[0])); - if(!TMP1) - CCR |= F_Z; - r32_w(IR[0], TMP1); + m_CCR &= ~(F_N|F_Z|F_V); + m_TMP1 = uint16_t(r32_r(m_IR[0])); + if(!m_TMP1) + m_CCR |= F_Z; + r32_w(m_IR[0], m_TMP1); prefetch 1780 fff0 0 neg.b r8l - - r8_w(IR[0], do_sub8(0, r8_r(IR[0]))); + r8_w(m_IR[0], do_sub8(0, r8_r(m_IR[0]))); prefetch 1790 fff0 0 neg.w r16l - h - r16_w(IR[0], do_sub16(0, r16_r(IR[0]))); + r16_w(m_IR[0], do_sub16(0, r16_r(m_IR[0]))); prefetch 17b0 fff8 0 neg.l r32l - h - r32_w(IR[0], do_sub32(0, r32_r(IR[0]))); + r32_w(m_IR[0], do_sub32(0, r32_r(m_IR[0]))); prefetch 17d0 fff0 0 exts.w r16l - h - CCR &= ~(F_N|F_Z|F_V); - TMP1 = int8_t(r16_r(IR[0])); - if(!TMP1) - CCR |= F_Z; - r16_w(IR[0], TMP1); + m_CCR &= ~(F_N|F_Z|F_V); + m_TMP1 = int8_t(r16_r(m_IR[0])); + if(!m_TMP1) + m_CCR |= F_Z; + r16_w(m_IR[0], m_TMP1); prefetch 17f0 fff8 0 exts.l r32l - h - CCR &= ~(F_N|F_Z|F_V); - TMP1 = int16_t(r32_r(IR[0])); - if(!TMP1) - CCR |= F_Z; - r32_w(IR[0], TMP1); + m_CCR &= ~(F_N|F_Z|F_V); + m_TMP1 = int16_t(r32_r(m_IR[0])); + if(!m_TMP1) + m_CCR |= F_Z; + r32_w(m_IR[0], m_TMP1); prefetch 1800 ff00 0 sub.b r8h r8l - r8_w(IR[0], do_sub8(r8_r(IR[0]), r8_r(IR[0] >> 4))); + r8_w(m_IR[0], do_sub8(r8_r(m_IR[0]), r8_r(m_IR[0] >> 4))); prefetch 1900 ff00 0 sub.w r16h r16l - r16_w(IR[0], do_sub16(r16_r(IR[0]), r16_r(IR[0] >> 4))); + r16_w(m_IR[0], do_sub16(r16_r(m_IR[0]), r16_r(m_IR[0] >> 4))); prefetch 1a00 fff0 0 dec.b one r8l - r8_w(IR[0], do_dec8(r8_r(IR[0]), 1)); + r8_w(m_IR[0], do_dec8(r8_r(m_IR[0]), 1)); prefetch 1a80 ff88 0 sub.l r32h r32l h - r32_w(IR[0], do_sub32(r32_r(IR[0]), r32_r(IR[0] >> 4))); + r32_w(m_IR[0], do_sub32(r32_r(m_IR[0]), r32_r(m_IR[0] >> 4))); prefetch 1b00 fff8 0 subs.l one r16l o - r16_w(IR[0], r16_r(IR[0])-1); + r16_w(m_IR[0], r16_r(m_IR[0])-1); prefetch 1b00 fff8 0 subs.l one r32l h - r32_w(IR[0], r32_r(IR[0])-1); + r32_w(m_IR[0], r32_r(m_IR[0])-1); prefetch 1b50 fff0 0 dec.w one r16l - r16_w(IR[0], do_dec16(r16_r(IR[0]), 1)); + r16_w(m_IR[0], do_dec16(r16_r(m_IR[0]), 1)); prefetch 1b70 fff8 0 dec.l one r32l h - r32_w(IR[0], do_dec32(r32_r(IR[0]), 1)); + r32_w(m_IR[0], do_dec32(r32_r(m_IR[0]), 1)); prefetch 1b80 fff8 0 subs.l two r16l o - r16_w(IR[0], r16_r(IR[0])-2); + r16_w(m_IR[0], r16_r(m_IR[0])-2); prefetch 1b80 fff8 0 subs.l two r32l h - r32_w(IR[0], r32_r(IR[0])-2); + r32_w(m_IR[0], r32_r(m_IR[0])-2); prefetch 1b90 fff8 0 subs.l four r16l o - r16_w(IR[0], r16_r(IR[0])-4); + r16_w(m_IR[0], r16_r(m_IR[0])-4); prefetch 1b90 fff8 0 subs.l four r32l h - r32_w(IR[0], r32_r(IR[0])-4); + r32_w(m_IR[0], r32_r(m_IR[0])-4); prefetch 1bd0 fff0 0 dec.w two r16l - r16_w(IR[0], do_dec16(r16_r(IR[0]), 2)); + r16_w(m_IR[0], do_dec16(r16_r(m_IR[0]), 2)); prefetch 1bf0 fff8 0 dec.l two r32l h - r32_w(IR[0], do_dec32(r32_r(IR[0]), 2)); + r32_w(m_IR[0], do_dec32(r32_r(m_IR[0]), 2)); prefetch 1c00 ff00 0 cmp.b r8h r8l - do_sub8(r8_r(IR[0]), r8_r(IR[0] >> 4)); + do_sub8(r8_r(m_IR[0]), r8_r(m_IR[0] >> 4)); prefetch 1d00 ff00 0 cmp.w r16h r16l - do_sub16(r16_r(IR[0]), r16_r(IR[0] >> 4)); + do_sub16(r16_r(m_IR[0]), r16_r(m_IR[0] >> 4)); prefetch 1e00 ff00 0 subx.b r8h r8l - r8_w(IR[0], do_subx8(r8_r(IR[0]), r8_r(IR[0] >> 4))); + r8_w(m_IR[0], do_subx8(r8_r(m_IR[0]), r8_r(m_IR[0] >> 4))); prefetch 1f00 fff0 0 das.b r8l - - TMP1 = r8_r(IR[0]); - TMP2 = 0; - if(CCR & F_C) { - if(has_hc && (CCR & F_H)) { - if((TMP1 & 0xf0) >= 0x60 && (TMP1 & 0x0f) >= 6) - TMP2 = 0x9a; + m_TMP1 = r8_r(m_IR[0]); + m_TMP2 = 0; + if(m_CCR & F_C) { + if(m_has_hc && (m_CCR & F_H)) { + if((m_TMP1 & 0xf0) >= 0x60 && (m_TMP1 & 0x0f) >= 6) + m_TMP2 = 0x9a; } else { - if((TMP1 & 0xf0) >= 0x70 && (TMP1 & 0x0f) <= 9) - TMP2 = 0xa0; + if((m_TMP1 & 0xf0) >= 0x70 && (m_TMP1 & 0x0f) <= 9) + m_TMP2 = 0xa0; } } else { - if(has_hc && (CCR & F_H)) { - if((TMP1 & 0xf0) <= 0x80 && (TMP1 & 0x0f) >= 6) - TMP2 = 0xfa; + if(m_has_hc && (m_CCR & F_H)) { + if((m_TMP1 & 0xf0) <= 0x80 && (m_TMP1 & 0x0f) >= 6) + m_TMP2 = 0xfa; } } - r8_w(IR[0], do_add8(TMP1, TMP2)); + r8_w(m_IR[0], do_add8(m_TMP1, m_TMP2)); prefetch 1f80 ff88 0 cmp.l r32h r32l h - do_sub32(r32_r(IR[0]), r32_r(IR[0] >> 4)); + do_sub32(r32_r(m_IR[0]), r32_r(m_IR[0] >> 4)); prefetch 2000 f000 0 mov.b abs8 r8u prefetch_start - TMP1 = read8(0xffffff00 | IR[0]); - set_nzv8(TMP1); - r8_w(IR[0] >> 8, TMP1); + m_TMP1 = read8(0xffffff00 | m_IR[0]); + set_nzv8(m_TMP1); + r8_w(m_IR[0] >> 8, m_TMP1); prefetch_done(); 3000 f000 0 mov.b r8u abs8 prefetch_start - TMP1 = r8_r(IR[0] >> 8); - set_nzv8(TMP1); - write8(0xffffff00 | IR[0], TMP1); + m_TMP1 = r8_r(m_IR[0] >> 8); + set_nzv8(m_TMP1); + write8(0xffffff00 | m_IR[0], m_TMP1); prefetch_done(); 4000 ff00 0 bt rel8 - @@ -1443,182 +1443,182 @@ macro jsr32 %opc %spreg bxx_8 false 4200 ff00 0 bhi rel8 - - bxx_8 !(CCR & (F_C|F_Z)) + bxx_8 !(m_CCR & (F_C|F_Z)) 4300 ff00 0 bls rel8 - - bxx_8 CCR & (F_C|F_Z) + bxx_8 m_CCR & (F_C|F_Z) 4400 ff00 0 bcc rel8 - - bxx_8 !(CCR & F_C) + bxx_8 !(m_CCR & F_C) 4500 ff00 0 bcs rel8 - - bxx_8 CCR & F_C + bxx_8 m_CCR & F_C 4600 ff00 0 bne rel8 - - bxx_8 !(CCR & F_Z) + bxx_8 !(m_CCR & F_Z) 4700 ff00 0 beq rel8 - - bxx_8 CCR & F_Z + bxx_8 m_CCR & F_Z 4800 ff00 0 bvc rel8 - - bxx_8 !(CCR & F_V) + bxx_8 !(m_CCR & F_V) 4900 ff00 0 bvs rel8 - - bxx_8 CCR & F_V + bxx_8 m_CCR & F_V 4a00 ff00 0 bpl rel8 - - bxx_8 !(CCR & F_N) + bxx_8 !(m_CCR & F_N) 4b00 ff00 0 bmi rel8 - - bxx_8 CCR & F_N + bxx_8 m_CCR & F_N 4c00 ff00 0 bge rel8 - - bxx_8 !((CCR & (F_N|F_V)) == F_N || (CCR & (F_N|F_V)) == F_V) + bxx_8 !((m_CCR & (F_N|F_V)) == F_N || (m_CCR & (F_N|F_V)) == F_V) 4d00 ff00 0 blt rel8 - - bxx_8 (CCR & (F_N|F_V)) == F_N || (CCR & (F_N|F_V)) == F_V + bxx_8 (m_CCR & (F_N|F_V)) == F_N || (m_CCR & (F_N|F_V)) == F_V 4e00 ff00 0 bgt rel8 - - bxx_8 !((CCR & F_Z) || (CCR & (F_N|F_V)) == F_N || (CCR & (F_N|F_V)) == F_V) + bxx_8 !((m_CCR & F_Z) || (m_CCR & (F_N|F_V)) == F_N || (m_CCR & (F_N|F_V)) == F_V) 4f00 ff00 0 ble rel8 - - bxx_8 (CCR & F_Z) || (CCR & (F_N|F_V)) == F_N || (CCR & (F_N|F_V)) == F_V + bxx_8 (m_CCR & F_Z) || (m_CCR & (F_N|F_V)) == F_N || (m_CCR & (F_N|F_V)) == F_V 5000 ff00 0 mulxu.b r8h r16l prefetch_start - r16_w(IR[0], uint8_t(r16_r(IR[0])) * r8_r(IR[0] >> 4)); - internal(has_mac ? 2 : 11); + r16_w(m_IR[0], uint8_t(r16_r(m_IR[0])) * r8_r(m_IR[0] >> 4)); + internal(m_has_mac ? 2 : 11); prefetch_done(); 5100 ff00 0 divxu.b r8h r16l prefetch_start internal(11); - TMP1 = r16_r(IR[0]); - TMP2 = r8_r(IR[0] >> 4); - CCR &= ~(F_Z|F_N); - if(TMP2 & 0x80) - CCR |= F_N; - if(!TMP2) { - CCR |= F_Z; + m_TMP1 = r16_r(m_IR[0]); + m_TMP2 = r8_r(m_IR[0] >> 4); + m_CCR &= ~(F_Z|F_N); + if(m_TMP2 & 0x80) + m_CCR |= F_N; + if(!m_TMP2) { + m_CCR |= F_Z; } else { - int q = TMP1 / TMP2; - int r = TMP1 % TMP2; - r16_w(IR[0], (q & 0xff) | ((r & 0xff) << 8)); + int q = m_TMP1 / m_TMP2; + int r = m_TMP1 % m_TMP2; + r16_w(m_IR[0], (q & 0xff) | ((r & 0xff) << 8)); } prefetch_done(); 5200 ff08 0 mulxu.w r16h r32l h prefetch_start - r32_w(IR[0], uint16_t(r32_r(IR[0])) * r16_r(IR[0] >> 4)); - internal(has_mac ? 3 : 19); + r32_w(m_IR[0], uint16_t(r32_r(m_IR[0])) * r16_r(m_IR[0] >> 4)); + internal(m_has_mac ? 3 : 19); prefetch_done(); 5300 ff08 0 divxu.w r16h r32l h prefetch_start internal(11); - TMP1 = r32_r(IR[0]); - TMP2 = r16_r(IR[0] >> 4); - CCR &= ~(F_Z|F_N); - if(TMP2 & 0x80) - CCR |= F_N; - if(!TMP2) { - CCR |= F_Z; + m_TMP1 = r32_r(m_IR[0]); + m_TMP2 = r16_r(m_IR[0] >> 4); + m_CCR &= ~(F_Z|F_N); + if(m_TMP2 & 0x80) + m_CCR |= F_N; + if(!m_TMP2) { + m_CCR |= F_Z; } else { - int q = TMP1 / TMP2; - int r = TMP1 % TMP2; - r32_w(IR[0], (q & 0xffff) | ((r & 0xffff) << 16)); + int q = m_TMP1 / m_TMP2; + int r = m_TMP1 % m_TMP2; + r32_w(m_IR[0], (q & 0xffff) | ((r & 0xffff) << 16)); } prefetch_done(); 5470 ffff 0 rts - - o fetch - TMP1 = r16_r(7); - TMP2 = read16(TMP1); - r16_w(7, TMP1+2); + m_TMP1 = r16_r(7); + m_TMP2 = read16(m_TMP1); + r16_w(7, m_TMP1+2); internal(1); - PC = TMP2; + m_PC = m_TMP2; prefetch 5470 ffff 0 rts - - h fetch - TMP1 = r32_r(7); - if(mode_advanced) { - TMP2 = read16(TMP1) << 16; - TMP2 |= read16(TMP1+2); - r32_w(7, TMP1+4); + m_TMP1 = r32_r(7); + if(m_mode_advanced) { + m_TMP2 = read16(m_TMP1) << 16; + m_TMP2 |= read16(m_TMP1+2); + r32_w(7, m_TMP1+4); } else { - TMP2 = read16(TMP1); - r32_w(7, TMP1+2); + m_TMP2 = read16(m_TMP1); + r32_w(7, m_TMP1+2); } internal(1); - PC = TMP2; + m_PC = m_TMP2; prefetch 5500 ff00 0 bsr rel8 - o - TMP2 = PC; - PC += int8_t(IR[0]); - jsr16 TMP2 TMP1 + m_TMP2 = m_PC; + m_PC += int8_t(m_IR[0]); + jsr16 m_TMP2 m_TMP1 5500 ff00 0 bsr rel8 - h - TMP2 = PC; - PC += int8_t(IR[0]); - jsr32 TMP2 TMP1 + m_TMP2 = m_PC; + m_PC += int8_t(m_IR[0]); + jsr32 m_TMP2 m_TMP1 5670 ffff 0 rte - - o fetch - TMP1 = r16_r(7); - CCR = read16(TMP1) >> 8; - TMP1 = r16_r(7); - TMP2 = read16(TMP1+2); - r16_w(7, TMP1+4); + m_TMP1 = r16_r(7); + m_CCR = read16(m_TMP1) >> 8; + m_TMP1 = r16_r(7); + m_TMP2 = read16(m_TMP1+2); + r16_w(7, m_TMP1+4); internal(1); - PC = TMP2; + m_PC = m_TMP2; update_irq_filter(); prefetch_noirq_notrace 5670 ffff 0 rte - - h fetch - TMP1 = r32_r(7); - if(mode_advanced) { + m_TMP1 = r32_r(7); + if(m_mode_advanced) { if(exr_in_stack()) { - EXR = (read16(TMP1) >> 8) | EXR_NC; - TMP1 += 2; + m_EXR = (read16(m_TMP1) >> 8) | EXR_NC; + m_TMP1 += 2; } - TMP2 = read16(TMP1); - CCR = TMP2 >> 8; - TMP2 = (TMP2 & 0xff) << 16; - TMP2 |= read16(TMP1+2); - r32_w(7, TMP1+4); + m_TMP2 = read16(m_TMP1); + m_CCR = m_TMP2 >> 8; + m_TMP2 = (m_TMP2 & 0xff) << 16; + m_TMP2 |= read16(m_TMP1+2); + r32_w(7, m_TMP1+4); } else { - TMP2 = read16(TMP1); - r32_w(7, TMP1+2); + m_TMP2 = read16(m_TMP1); + r32_w(7, m_TMP1+2); } internal(1); - PC = TMP2; + m_PC = m_TMP2; update_irq_filter(); prefetch_noirq_notrace 5700 ffcf 0 trapa imm2 - h internal(1); - TMP1 = r32_r(7) - 2; - r32_w(7, TMP1); - write16(TMP1, NPC); - TMP1 = r32_r(7) - 2; - r32_w(7, TMP1); - write16(TMP1, (CCR << 8) | ((NPC >> 16) & 0xff)); + m_TMP1 = r32_r(7) - 2; + r32_w(7, m_TMP1); + write16(m_TMP1, m_NPC); + m_TMP1 = r32_r(7) - 2; + r32_w(7, m_TMP1); + write16(m_TMP1, (m_CCR << 8) | ((m_NPC >> 16) & 0xff)); if(exr_in_stack()) { - TMP1 = r32_r(7) - 2; - r32_w(7, TMP1); - write16(TMP1, EXR << 8); + m_TMP1 = r32_r(7) - 2; + r32_w(7, m_TMP1); + write16(m_TMP1, m_EXR << 8); } - taken_irq_vector = trapa_setup() + ((IR[0] >> 4) & 3); - debugger_exception_hook(taken_irq_vector); - if(mode_advanced) { - IR[0] = read16i(4*taken_irq_vector); - IR[1] = read16i(4*taken_irq_vector+2); - PC = (IR[0] << 16) | IR[1]; + m_taken_irq_vector = trapa_setup() + ((m_IR[0] >> 4) & 3); + debugger_exception_hook(m_taken_irq_vector); + if(m_mode_advanced) { + m_IR[0] = read16i(4*m_taken_irq_vector); + m_IR[1] = read16i(4*m_taken_irq_vector+2); + m_PC = (m_IR[0] << 16) | m_IR[1]; } else { - PC = read16i(2*taken_irq_vector); + m_PC = read16i(2*m_taken_irq_vector); } internal(1); update_irq_filter(); @@ -1631,868 +1631,868 @@ macro jsr32 %opc %spreg bxx_16 false 5820 ffff 0 bhi rel16 - h - bxx_16 !(CCR & (F_C|F_Z)) + bxx_16 !(m_CCR & (F_C|F_Z)) 5830 ffff 0 bls rel16 - h - bxx_16 CCR & (F_C|F_Z) + bxx_16 m_CCR & (F_C|F_Z) 5840 ffff 0 bcc rel16 - h - bxx_16 !(CCR & F_C) + bxx_16 !(m_CCR & F_C) 5850 ffff 0 bcs rel16 - h - bxx_16 CCR & F_C + bxx_16 m_CCR & F_C 5860 ffff 0 bne rel16 - h - bxx_16 !(CCR & F_Z) + bxx_16 !(m_CCR & F_Z) 5870 ffff 0 beq rel16 - h - bxx_16 CCR & F_Z + bxx_16 m_CCR & F_Z 5880 ffff 0 bvc rel16 - h - bxx_16 !(CCR & F_V) + bxx_16 !(m_CCR & F_V) 5890 ffff 0 bvs rel16 - h - bxx_16 CCR & F_V + bxx_16 m_CCR & F_V 58a0 ffff 0 bpl rel16 - h - bxx_16 !(CCR & F_N) + bxx_16 !(m_CCR & F_N) 58b0 ffff 0 bmi rel16 - h - bxx_16 CCR & F_N + bxx_16 m_CCR & F_N 58c0 ffff 0 bge rel16 - h - bxx_16 !((CCR & (F_N|F_V)) == F_N || (CCR & (F_N|F_V)) == F_V) + bxx_16 !((m_CCR & (F_N|F_V)) == F_N || (m_CCR & (F_N|F_V)) == F_V) 58d0 ffff 0 blt rel16 - h - bxx_16 (CCR & (F_N|F_V)) == F_N || (CCR & (F_N|F_V)) == F_V + bxx_16 (m_CCR & (F_N|F_V)) == F_N || (m_CCR & (F_N|F_V)) == F_V 58e0 ffff 0 bgt rel16 - h - bxx_16 !((CCR & F_Z) || (CCR & (F_N|F_V)) == F_N || (CCR & (F_N|F_V)) == F_V) + bxx_16 !((m_CCR & F_Z) || (m_CCR & (F_N|F_V)) == F_N || (m_CCR & (F_N|F_V)) == F_V) 58f0 ffff 0 ble rel16 - h - bxx_16 (CCR & F_Z) || (CCR & (F_N|F_V)) == F_N || (CCR & (F_N|F_V)) == F_V + bxx_16 (m_CCR & F_Z) || (m_CCR & (F_N|F_V)) == F_N || (m_CCR & (F_N|F_V)) == F_V 5900 ff8f 0 jmp r16h - o fetch - PC = r16_r(IR[0] >> 4); + m_PC = r16_r(m_IR[0] >> 4); prefetch 5900 ff8f 0 jmp r32h - h fetch - PC = r32_r(IR[0] >> 4); + m_PC = r32_r(m_IR[0] >> 4); prefetch 5a00 ffff 0 jmp abs16e - o internal(1); - PC = IR[1]; + m_PC = m_IR[1]; prefetch 5a00 ff00 0 jmp abs24e - h internal(1); - PC = ((IR[0] & 0xff) << 16) | IR[1]; + m_PC = ((m_IR[0] & 0xff) << 16) | m_IR[1]; prefetch 5b00 ff00 0 jmp abs8i - o fetch - PC = read16(IR[0] & 0xff); + m_PC = read16(m_IR[0] & 0xff); internal(1); prefetch 5b00 ff00 0 jmp abs8i - h fetch - if(mode_advanced) { - TMP1 = read16(IR[0] & 0xff) << 16; - TMP1 |= read16((IR[0] & 0xff) + 2); - PC = TMP1; + if(m_mode_advanced) { + m_TMP1 = read16(m_IR[0] & 0xff) << 16; + m_TMP1 |= read16((m_IR[0] & 0xff) + 2); + m_PC = m_TMP1; } else { - PC = read16(IR[0] & 0xff); + m_PC = read16(m_IR[0] & 0xff); } internal(1); prefetch 5c00 ffff 0 bsr rel16 - h internal(1); - TMP2 = PC; - PC += int16_t(IR[1]); - jsr32 TMP2 TMP1 + m_TMP2 = m_PC; + m_PC += int16_t(m_IR[1]); + jsr32 m_TMP2 m_TMP1 5d00 ff8f 0 jsr r16h - o - TMP2 = PC; - PC = r16_r(IR[0] >> 4); - jsr16 TMP2 TMP1 + m_TMP2 = m_PC; + m_PC = r16_r(m_IR[0] >> 4); + jsr16 m_TMP2 m_TMP1 5d00 ff8f 0 jsr r32h - h - TMP2 = PC; - PC = r32_r(IR[0] >> 4); - jsr32 TMP2 TMP1 + m_TMP2 = m_PC; + m_PC = r32_r(m_IR[0] >> 4); + jsr32 m_TMP2 m_TMP1 5e00 ffff 0 jsr abs16e - o internal(1); - TMP2 = PC; - PC = IR[1]; - jsr16 TMP2 TMP1 + m_TMP2 = m_PC; + m_PC = m_IR[1]; + jsr16 m_TMP2 m_TMP1 5e00 ff00 0 jsr abs24e - h internal(1); - TMP2 = PC; - PC = ((IR[0] & 0xff) << 16) | IR[1]; - jsr32 TMP2 TMP1 + m_TMP2 = m_PC; + m_PC = ((m_IR[0] & 0xff) << 16) | m_IR[1]; + jsr32 m_TMP2 m_TMP1 5f00 ff00 0 jsr abs8i - o fetch - TMP2 = PC; - PC = read16(IR[0] & 0xff); - jsr16 TMP2 TMP1 + m_TMP2 = m_PC; + m_PC = read16(m_IR[0] & 0xff); + jsr16 m_TMP2 m_TMP1 5f00 ff00 0 jsr abs8i - h fetch - TMP2 = PC; - if(mode_advanced) { - TMP1 = read16(IR[0] & 0xff) << 16; - TMP1 |= read16((IR[0] & 0xff) + 2); - PC = TMP1; + m_TMP2 = m_PC; + if(m_mode_advanced) { + m_TMP1 = read16(m_IR[0] & 0xff) << 16; + m_TMP1 |= read16((m_IR[0] & 0xff) + 2); + m_PC = m_TMP1; } else { - PC = read16(IR[0] & 0xff); + m_PC = read16(m_IR[0] & 0xff); } - jsr32 TMP2 TMP1 + jsr32 m_TMP2 m_TMP1 6000 ff00 0 bset r8h r8l - TMP1 = r8_r(IR[0]); - bset r8_r(IR[0] >> 4) - r8_w(IR[0], TMP1); + m_TMP1 = r8_r(m_IR[0]); + bset r8_r(m_IR[0] >> 4) + r8_w(m_IR[0], m_TMP1); prefetch 6100 ff00 0 bnot r8h r8l - TMP1 = r8_r(IR[0]); - bnot r8_r(IR[0] >> 4) - r8_w(IR[0], TMP1); + m_TMP1 = r8_r(m_IR[0]); + bnot r8_r(m_IR[0] >> 4) + r8_w(m_IR[0], m_TMP1); prefetch 6200 ff00 0 bclr r8h r8l - TMP1 = r8_r(IR[0]); - bclr r8_r(IR[0] >> 4) - r8_w(IR[0], TMP1); + m_TMP1 = r8_r(m_IR[0]); + bclr r8_r(m_IR[0] >> 4) + r8_w(m_IR[0], m_TMP1); prefetch 6300 ff00 0 btst r8h r8l - TMP1 = r8_r(IR[0]); - btst r8_r(IR[0] >> 4) + m_TMP1 = r8_r(m_IR[0]); + btst r8_r(m_IR[0] >> 4) prefetch 6400 ff00 0 or.w r16h r16l h - TMP1 = r16_r(IR[0] >> 4) | r16_r(IR[0]); - set_nzv16(TMP1); - r16_w(IR[0], TMP1); + m_TMP1 = r16_r(m_IR[0] >> 4) | r16_r(m_IR[0]); + set_nzv16(m_TMP1); + r16_w(m_IR[0], m_TMP1); prefetch 6500 ff00 0 xor.w r16h r16l h - TMP1 = r16_r(IR[0] >> 4) ^ r16_r(IR[0]); - set_nzv16(TMP1); - r16_w(IR[0], TMP1); + m_TMP1 = r16_r(m_IR[0] >> 4) ^ r16_r(m_IR[0]); + set_nzv16(m_TMP1); + r16_w(m_IR[0], m_TMP1); prefetch 6600 ff00 0 and.w r16h r16l h - TMP1 = r16_r(IR[0] >> 4) & r16_r(IR[0]); - set_nzv16(TMP1); - r16_w(IR[0], TMP1); + m_TMP1 = r16_r(m_IR[0] >> 4) & r16_r(m_IR[0]); + set_nzv16(m_TMP1); + r16_w(m_IR[0], m_TMP1); prefetch 6700 ff80 0 bst imm3 r8l - TMP1 = r8_r(IR[0]); - bst IR[0] >> 4 - r8_w(IR[0], TMP1); + m_TMP1 = r8_r(m_IR[0]); + bst m_IR[0] >> 4 + r8_w(m_IR[0], m_TMP1); prefetch 6780 ff80 0 bist imm3 r8l - TMP1 = r8_r(IR[0]); - bist IR[0] >> 4 - r8_w(IR[0], TMP1); + m_TMP1 = r8_r(m_IR[0]); + bist m_IR[0] >> 4 + r8_w(m_IR[0], m_TMP1); prefetch 6800 ff80 0 mov.b r16ih r8l o prefetch_start - TMP1 = read8(r16_r(IR[0] >> 4)); - set_nzv8(TMP1); - r8_w(IR[0], TMP1); + m_TMP1 = read8(r16_r(m_IR[0] >> 4)); + set_nzv8(m_TMP1); + r8_w(m_IR[0], m_TMP1); prefetch_done(); 6800 ff80 0 mov.b r32ih r8l h prefetch_start - TMP1 = read8(r32_r(IR[0] >> 4)); - set_nzv8(TMP1); - r8_w(IR[0], TMP1); + m_TMP1 = read8(r32_r(m_IR[0] >> 4)); + set_nzv8(m_TMP1); + r8_w(m_IR[0], m_TMP1); prefetch_done(); 6880 ff80 0 mov.b r8l r16ih o prefetch_start - TMP1 = r8_r(IR[0]); - set_nzv8(TMP1); - write8(r16_r((IR[0] >> 4) & 7), TMP1); + m_TMP1 = r8_r(m_IR[0]); + set_nzv8(m_TMP1); + write8(r16_r((m_IR[0] >> 4) & 7), m_TMP1); prefetch_done(); 6880 ff80 0 mov.b r8l r32ih h prefetch_start - TMP1 = r8_r(IR[0]); - set_nzv8(TMP1); - write8(r32_r(IR[0] >> 4), TMP1); + m_TMP1 = r8_r(m_IR[0]); + set_nzv8(m_TMP1); + write8(r32_r(m_IR[0] >> 4), m_TMP1); prefetch_done(); 6900 ff88 0 mov.w r16ih r16l o prefetch_start - TMP1 = read16(r16_r(IR[0] >> 4)); - set_nzv16(TMP1); - r16_w(IR[0], TMP1); + m_TMP1 = read16(r16_r(m_IR[0] >> 4)); + set_nzv16(m_TMP1); + r16_w(m_IR[0], m_TMP1); prefetch_done(); 6900 ff80 0 mov.w r32ih r16l h prefetch_start - TMP1 = read16(r32_r(IR[0] >> 4)); - set_nzv16(TMP1); - r16_w(IR[0], TMP1); + m_TMP1 = read16(r32_r(m_IR[0] >> 4)); + set_nzv16(m_TMP1); + r16_w(m_IR[0], m_TMP1); prefetch_done(); 6980 ff88 0 mov.w r16l r16ih o prefetch_start - TMP1 = r16_r(IR[0]); - set_nzv16(TMP1); - write16(r16_r((IR[0] >> 4) & 7), TMP1); + m_TMP1 = r16_r(m_IR[0]); + set_nzv16(m_TMP1); + write16(r16_r((m_IR[0] >> 4) & 7), m_TMP1); prefetch_done(); 6980 ff80 0 mov.w r16l r32ih h prefetch_start - TMP1 = r16_r(IR[0]); - set_nzv16(TMP1); - write16(r32_r(IR[0] >> 4), TMP1); + m_TMP1 = r16_r(m_IR[0]); + set_nzv16(m_TMP1); + write16(r32_r(m_IR[0] >> 4), m_TMP1); prefetch_done(); 6a00 fff0 0 mov.b abs16 r8l prefetch_start - TMP1 = read8(int16_t(IR[1])); - set_nzv8(TMP1); - r8_w(IR[0], TMP1); + m_TMP1 = read8(int16_t(m_IR[1])); + set_nzv8(m_TMP1); + r8_w(m_IR[0], m_TMP1); prefetch_done(); 6a106300 ffffff0f 1 btst r8h abs16 - TMP2 = int16_t(IR[1]); - TMP1 = read8(TMP2); - btst r8_r(IR[2] >> 4) + m_TMP2 = int16_t(m_IR[1]); + m_TMP1 = read8(m_TMP2); + btst r8_r(m_IR[2] >> 4) prefetch 6a107300 ffffff8f 1 btst imm3 abs16 - TMP2 = int16_t(IR[1]); - TMP1 = read8(TMP2); - btst IR[2] >> 4 + m_TMP2 = int16_t(m_IR[1]); + m_TMP1 = read8(m_TMP2); + btst m_IR[2] >> 4 prefetch 6a107400 ffffff8f 1 bor imm3 abs16 - TMP2 = int16_t(IR[1]); - TMP1 = read8(TMP2); - bor IR[2] >> 4 + m_TMP2 = int16_t(m_IR[1]); + m_TMP1 = read8(m_TMP2); + bor m_IR[2] >> 4 prefetch 6a107480 ffffff8f 1 bior imm3 abs16 - TMP2 = int16_t(IR[1]); - TMP1 = read8(TMP2); - bior IR[2] >> 4 + m_TMP2 = int16_t(m_IR[1]); + m_TMP1 = read8(m_TMP2); + bior m_IR[2] >> 4 prefetch 6a107500 ffffff8f 1 bxor imm3 abs16 - TMP2 = int16_t(IR[1]); - TMP1 = read8(TMP2); - bxor IR[2] >> 4 + m_TMP2 = int16_t(m_IR[1]); + m_TMP1 = read8(m_TMP2); + bxor m_IR[2] >> 4 prefetch 6a107580 ffffff8f 1 bixor imm3 abs16 - TMP2 = int16_t(IR[1]); - TMP1 = read8(TMP2); - bixor IR[2] >> 4 + m_TMP2 = int16_t(m_IR[1]); + m_TMP1 = read8(m_TMP2); + bixor m_IR[2] >> 4 prefetch 6a107600 ffffff8f 1 band imm3 abs16 - TMP2 = int16_t(IR[1]); - TMP1 = read8(TMP2); - band IR[2] >> 4 + m_TMP2 = int16_t(m_IR[1]); + m_TMP1 = read8(m_TMP2); + band m_IR[2] >> 4 prefetch 6a107680 ffffff8f 1 biand imm3 abs16 - TMP2 = int16_t(IR[1]); - TMP1 = read8(TMP2); - biand IR[2] >> 4 + m_TMP2 = int16_t(m_IR[1]); + m_TMP1 = read8(m_TMP2); + biand m_IR[2] >> 4 prefetch 6a107700 ffffff8f 1 bld imm3 abs16 - TMP2 = int16_t(IR[1]); - TMP1 = read8(TMP2); - bld IR[2] >> 4 + m_TMP2 = int16_t(m_IR[1]); + m_TMP1 = read8(m_TMP2); + bld m_IR[2] >> 4 prefetch 6a107780 ffffff8f 1 bild imm3 abs16 - TMP2 = int16_t(IR[1]); - TMP1 = read8(TMP2); - bild IR[2] >> 4 + m_TMP2 = int16_t(m_IR[1]); + m_TMP1 = read8(m_TMP2); + bild m_IR[2] >> 4 prefetch 6a186000 ffffff0f 1 bset r8h abs16 - TMP2 = int16_t(IR[1]); - TMP1 = read8(TMP2); + m_TMP2 = int16_t(m_IR[1]); + m_TMP1 = read8(m_TMP2); prefetch_start - bset r8_r(IR[2] >> 4) - write8(TMP2, TMP1); + bset r8_r(m_IR[2] >> 4) + write8(m_TMP2, m_TMP1); prefetch_done(); 6a186100 ffffff0f 1 bnot r8h abs16 - TMP2 = int16_t(IR[1]); - TMP1 = read8(TMP2); + m_TMP2 = int16_t(m_IR[1]); + m_TMP1 = read8(m_TMP2); prefetch_start - bnot r8_r(IR[2] >> 4) - write8(TMP2, TMP1); + bnot r8_r(m_IR[2] >> 4) + write8(m_TMP2, m_TMP1); prefetch_done(); 6a186200 ffffff0f 1 bclr r8h abs16 - TMP2 = int16_t(IR[1]); - TMP1 = read8(TMP2); + m_TMP2 = int16_t(m_IR[1]); + m_TMP1 = read8(m_TMP2); prefetch_start - bclr r8_r(IR[2] >> 4) - write8(TMP2, TMP1); + bclr r8_r(m_IR[2] >> 4) + write8(m_TMP2, m_TMP1); prefetch_done(); 6a186700 ffffff8f 1 bst imm3 abs16 - TMP2 = int16_t(IR[2]); - TMP1 = read8(TMP2); + m_TMP2 = int16_t(m_IR[2]); + m_TMP1 = read8(m_TMP2); prefetch_start - bst IR[2] >> 4 - write8(TMP2, TMP1); + bst m_IR[2] >> 4 + write8(m_TMP2, m_TMP1); prefetch_done(); 6a186780 ffffff8f 1 bist imm3 abs16 - TMP2 = int16_t(IR[1]); - TMP1 = read8(TMP2); + m_TMP2 = int16_t(m_IR[1]); + m_TMP1 = read8(m_TMP2); prefetch_start - bist IR[2] >> 4 - write8(TMP2, TMP1); + bist m_IR[2] >> 4 + write8(m_TMP2, m_TMP1); prefetch_done(); 6a187000 ffffff8f 1 bset imm3 abs16 - TMP2 = int16_t(IR[1]); - TMP1 = read8(TMP2); + m_TMP2 = int16_t(m_IR[1]); + m_TMP1 = read8(m_TMP2); prefetch_start - bset IR[2] >> 4 - write8(TMP2, TMP1); + bset m_IR[2] >> 4 + write8(m_TMP2, m_TMP1); prefetch_done(); 6a187100 ffffff8f 1 bnot imm3 abs16 - TMP2 = int16_t(IR[1]); - TMP1 = read8(TMP2); + m_TMP2 = int16_t(m_IR[1]); + m_TMP1 = read8(m_TMP2); prefetch_start - bnot IR[2] >> 4 - write8(TMP2, TMP1); + bnot m_IR[2] >> 4 + write8(m_TMP2, m_TMP1); prefetch_done(); 6a187200 ffffff8f 1 bclr imm3 abs16 - TMP2 = int16_t(IR[1]); - TMP1 = read8(TMP2); + m_TMP2 = int16_t(m_IR[1]); + m_TMP1 = read8(m_TMP2); prefetch_start - bclr IR[2] >> 4 - write8(TMP2, TMP1); + bclr m_IR[2] >> 4 + write8(m_TMP2, m_TMP1); prefetch_done(); 6a20 fff0 0 mov.b abs32 r8l h prefetch_start - TMP1 = read8((IR[1] << 16) | IR[2]); - set_nzv8(TMP1); - r8_w(IR[0], TMP1); + m_TMP1 = read8((m_IR[1] << 16) | m_IR[2]); + set_nzv8(m_TMP1); + r8_w(m_IR[0], m_TMP1); prefetch_done(); 6a306300 ffffff0f 2 btst r8h abs32 h - TMP2 = (IR[1] << 16) | IR[2]; - TMP1 = read8(TMP2); - btst r8_r(IR[3] >> 4) + m_TMP2 = (m_IR[1] << 16) | m_IR[2]; + m_TMP1 = read8(m_TMP2); + btst r8_r(m_IR[3] >> 4) prefetch 6a307300 ffffff8f 2 btst imm3 abs32 h - TMP2 = (IR[1] << 16) | IR[2]; - TMP1 = read8(TMP2); - btst IR[3] >> 4 + m_TMP2 = (m_IR[1] << 16) | m_IR[2]; + m_TMP1 = read8(m_TMP2); + btst m_IR[3] >> 4 prefetch 6a307400 ffffff8f 2 bor imm3 abs32 h - TMP2 = (IR[1] << 16) | IR[2]; - TMP1 = read8(TMP2); - bor IR[3] >> 4 + m_TMP2 = (m_IR[1] << 16) | m_IR[2]; + m_TMP1 = read8(m_TMP2); + bor m_IR[3] >> 4 prefetch 6a307480 ffffff8f 2 bior imm3 abs32 h - TMP2 = (IR[1] << 16) | IR[2]; - TMP1 = read8(TMP2); - bior IR[3] >> 4 + m_TMP2 = (m_IR[1] << 16) | m_IR[2]; + m_TMP1 = read8(m_TMP2); + bior m_IR[3] >> 4 prefetch 6a307500 ffffff8f 2 bxor imm3 abs32 h - TMP2 = (IR[1] << 16) | IR[2]; - TMP1 = read8(TMP2); - bxor IR[3] >> 4 + m_TMP2 = (m_IR[1] << 16) | m_IR[2]; + m_TMP1 = read8(m_TMP2); + bxor m_IR[3] >> 4 prefetch 6a307580 ffffff8f 2 bixor imm3 abs32 h - TMP2 = (IR[1] << 16) | IR[2]; - TMP1 = read8(TMP2); - bixor IR[3] >> 4 + m_TMP2 = (m_IR[1] << 16) | m_IR[2]; + m_TMP1 = read8(m_TMP2); + bixor m_IR[3] >> 4 prefetch 6a307600 ffffff8f 2 band imm3 abs32 h - TMP2 = (IR[1] << 16) | IR[2]; - TMP1 = read8(TMP2); - band IR[3] >> 4 + m_TMP2 = (m_IR[1] << 16) | m_IR[2]; + m_TMP1 = read8(m_TMP2); + band m_IR[3] >> 4 prefetch 6a307680 ffffff8f 2 biand imm3 abs32 h - TMP2 = (IR[1] << 16) | IR[2]; - TMP1 = read8(TMP2); - biand IR[3] >> 4 + m_TMP2 = (m_IR[1] << 16) | m_IR[2]; + m_TMP1 = read8(m_TMP2); + biand m_IR[3] >> 4 prefetch 6a307700 ffffff8f 2 bld imm3 abs32 h - TMP2 = (IR[1] << 16) | IR[2]; - TMP1 = read8(TMP2); - bld IR[3] >> 4 + m_TMP2 = (m_IR[1] << 16) | m_IR[2]; + m_TMP1 = read8(m_TMP2); + bld m_IR[3] >> 4 prefetch 6a307780 ffffff8f 2 bild imm3 abs32 h - TMP2 = (IR[1] << 16) | IR[2]; - TMP1 = read8(TMP2); - bild IR[3] >> 4 + m_TMP2 = (m_IR[1] << 16) | m_IR[2]; + m_TMP1 = read8(m_TMP2); + bild m_IR[3] >> 4 prefetch 6a386000 ffffff0f 2 bset r8h abs32 h - TMP2 = (IR[1] << 16) | IR[2]; - TMP1 = read8(TMP2); + m_TMP2 = (m_IR[1] << 16) | m_IR[2]; + m_TMP1 = read8(m_TMP2); prefetch_start - bset r8_r(IR[3] >> 4) - write8(TMP2, TMP1); + bset r8_r(m_IR[3] >> 4) + write8(m_TMP2, m_TMP1); prefetch_done(); 6a386100 ffffff0f 2 bnot r8h abs32 h - TMP2 = (IR[1] << 16) | IR[2]; - TMP1 = read8(TMP2); + m_TMP2 = (m_IR[1] << 16) | m_IR[2]; + m_TMP1 = read8(m_TMP2); prefetch_start - bnot r8_r(IR[3] >> 4) - write8(TMP2, TMP1); + bnot r8_r(m_IR[3] >> 4) + write8(m_TMP2, m_TMP1); prefetch_done(); 6a386200 ffffff0f 2 bclr r8h abs32 h - TMP2 = (IR[1] << 16) | IR[2]; - TMP1 = read8(TMP2); + m_TMP2 = (m_IR[1] << 16) | m_IR[2]; + m_TMP1 = read8(m_TMP2); prefetch_start - bclr r8_r(IR[3] >> 4) - write8(TMP2, TMP1); + bclr r8_r(m_IR[3] >> 4) + write8(m_TMP2, m_TMP1); prefetch_done(); 6a386700 ffffff8f 2 bst imm3 abs32 h - TMP2 = (IR[1] << 16) | IR[2]; - TMP1 = read8(TMP2); + m_TMP2 = (m_IR[1] << 16) | m_IR[2]; + m_TMP1 = read8(m_TMP2); prefetch_start - bst IR[3] >> 4 - write8(TMP2, TMP1); + bst m_IR[3] >> 4 + write8(m_TMP2, m_TMP1); prefetch_done(); 6a386780 ffffff8f 2 bist imm3 abs32 h - TMP2 = (IR[1] << 16) | IR[2]; - TMP1 = read8(TMP2); + m_TMP2 = (m_IR[1] << 16) | m_IR[2]; + m_TMP1 = read8(m_TMP2); prefetch_start - bist IR[3] >> 4 - write8(TMP2, TMP1); + bist m_IR[3] >> 4 + write8(m_TMP2, m_TMP1); prefetch_done(); 6a387000 ffffff8f 2 bset imm3 abs32 h - TMP2 = (IR[1] << 16) | IR[2]; - TMP1 = read8(TMP2); + m_TMP2 = (m_IR[1] << 16) | m_IR[2]; + m_TMP1 = read8(m_TMP2); prefetch_start - bset IR[3] >> 4 - write8(TMP2, TMP1); + bset m_IR[3] >> 4 + write8(m_TMP2, m_TMP1); prefetch_done(); 6a387100 ffffff8f 2 bnot imm3 abs32 h - TMP2 = (IR[1] << 16) | IR[2]; - TMP1 = read8(TMP2); + m_TMP2 = (m_IR[1] << 16) | m_IR[2]; + m_TMP1 = read8(m_TMP2); prefetch_start - bnot IR[3] >> 4 - write8(TMP2, TMP1); + bnot m_IR[3] >> 4 + write8(m_TMP2, m_TMP1); prefetch_done(); 6a387200 ffffff8f 2 bclr imm3 abs32 h - TMP2 = (IR[1] << 16) | IR[2]; - TMP1 = read8(TMP2); + m_TMP2 = (m_IR[1] << 16) | m_IR[2]; + m_TMP1 = read8(m_TMP2); prefetch_start - bclr IR[3] >> 4 - write8(TMP2, TMP1); + bclr m_IR[3] >> 4 + write8(m_TMP2, m_TMP1); prefetch_done(); 6a40 fff0 0 movfpe abs16 r8l 6a80 fff0 0 mov.b r8l abs16 prefetch_start - TMP1 = r8_r(IR[0]); - set_nzv8(TMP1); - write8(int16_t(IR[1]), TMP1); + m_TMP1 = r8_r(m_IR[0]); + set_nzv8(m_TMP1); + write8(int16_t(m_IR[1]), m_TMP1); prefetch_done(); 6aa0 fff0 0 mov.b r8l abs32 h prefetch_start - TMP1 = r8_r(IR[0]); - set_nzv8(TMP1); - write8((IR[1] << 16) | IR[2], TMP1); + m_TMP1 = r8_r(m_IR[0]); + set_nzv8(m_TMP1); + write8((m_IR[1] << 16) | m_IR[2], m_TMP1); prefetch_done(); 6ac0 fff0 0 movtpe r8l abs16 6b00 fff0 0 mov.w abs16 r16l prefetch_start - TMP1 = read16(int16_t(IR[1])); - set_nzv16(TMP1); - r16_w(IR[0], TMP1); + m_TMP1 = read16(int16_t(m_IR[1])); + set_nzv16(m_TMP1); + r16_w(m_IR[0], m_TMP1); prefetch_done(); 6b20 fff0 0 mov.w abs32 r16l h prefetch_start - TMP1 = read16((IR[1] << 16) | IR[2]); - set_nzv16(TMP1); - r16_w(IR[0], TMP1); + m_TMP1 = read16((m_IR[1] << 16) | m_IR[2]); + set_nzv16(m_TMP1); + r16_w(m_IR[0], m_TMP1); prefetch_done(); 6b80 fff0 0 mov.w r16l abs16 prefetch_start - TMP1 = r16_r(IR[0]); - set_nzv16(TMP1); - write16(int16_t(IR[1]), TMP1); + m_TMP1 = r16_r(m_IR[0]); + set_nzv16(m_TMP1); + write16(int16_t(m_IR[1]), m_TMP1); prefetch_done(); 6ba0 fff0 0 mov.w r16l abs32 h prefetch_start - TMP1 = r16_r(IR[0]); - set_nzv16(TMP1); - write16((IR[1] << 16) | IR[2], TMP1); + m_TMP1 = r16_r(m_IR[0]); + set_nzv16(m_TMP1); + write16((m_IR[1] << 16) | m_IR[2], m_TMP1); prefetch_done(); 6c00 ff80 0 mov.b r16ph r8l o - TMP2 = r16_r(IR[0] >> 4); + m_TMP2 = r16_r(m_IR[0] >> 4); prefetch_start internal(1); - TMP1 = read8(TMP2); - TMP2 += 1; - r16_w(IR[0] >> 4, TMP2); - set_nzv8(TMP1); - r8_w(IR[0], TMP1); + m_TMP1 = read8(m_TMP2); + m_TMP2 += 1; + r16_w(m_IR[0] >> 4, m_TMP2); + set_nzv8(m_TMP1); + r8_w(m_IR[0], m_TMP1); prefetch_done(); 6c00 ff80 0 mov.b r32ph r8l h - TMP2 = r32_r(IR[0] >> 4); + m_TMP2 = r32_r(m_IR[0] >> 4); prefetch_start internal(1); - TMP1 = read8(TMP2); - TMP2 += 1; - r32_w(IR[0] >> 4, TMP2); - set_nzv8(TMP1); - r8_w(IR[0], TMP1); + m_TMP1 = read8(m_TMP2); + m_TMP2 += 1; + r32_w(m_IR[0] >> 4, m_TMP2); + set_nzv8(m_TMP1); + r8_w(m_IR[0], m_TMP1); prefetch_done(); 6c80 ff80 0 mov.b r8l pr16h o - TMP1 = r8_r(IR[0]); - TMP2 = r16_r((IR[0] >> 4) & 7); + m_TMP1 = r8_r(m_IR[0]); + m_TMP2 = r16_r((m_IR[0] >> 4) & 7); prefetch_start internal(1); - TMP2 -= 1; - r16_w((IR[0] >> 4) & 7, TMP2); - set_nzv8(TMP1); - write8(TMP2, TMP1); + m_TMP2 -= 1; + r16_w((m_IR[0] >> 4) & 7, m_TMP2); + set_nzv8(m_TMP1); + write8(m_TMP2, m_TMP1); prefetch_done(); 6c80 ff80 0 mov.b r8l pr32h h - TMP1 = r8_r(IR[0]); - TMP2 = r32_r(IR[0] >> 4); + m_TMP1 = r8_r(m_IR[0]); + m_TMP2 = r32_r(m_IR[0] >> 4); prefetch_start internal(1); - TMP2 -= 1; - r32_w(IR[0] >> 4, TMP2); - set_nzv8(TMP1); - write8(TMP2, TMP1); + m_TMP2 -= 1; + r32_w(m_IR[0] >> 4, m_TMP2); + set_nzv8(m_TMP1); + write8(m_TMP2, m_TMP1); prefetch_done(); 6d00 ff88 0 mov.w r16ph r16l o - TMP2 = r16_r(IR[0] >> 4); + m_TMP2 = r16_r(m_IR[0] >> 4); prefetch_start internal(1); - TMP1 = read16(TMP2); - TMP2 += 2; - r16_w(IR[0] >> 4, TMP2); - set_nzv16(TMP1); - r16_w(IR[0], TMP1); + m_TMP1 = read16(m_TMP2); + m_TMP2 += 2; + r16_w(m_IR[0] >> 4, m_TMP2); + set_nzv16(m_TMP1); + r16_w(m_IR[0], m_TMP1); prefetch_done(); 6d00 ff80 0 mov.w r32ph r16l h - TMP2 = r32_r(IR[0] >> 4); + m_TMP2 = r32_r(m_IR[0] >> 4); prefetch_start internal(1); - TMP1 = read16(TMP2); - TMP2 += 2; - r32_w(IR[0] >> 4, TMP2); - set_nzv16(TMP1); - r16_w(IR[0], TMP1); + m_TMP1 = read16(m_TMP2); + m_TMP2 += 2; + r32_w(m_IR[0] >> 4, m_TMP2); + set_nzv16(m_TMP1); + r16_w(m_IR[0], m_TMP1); prefetch_done(); 6d80 ff88 0 mov.w r16l pr16h o - TMP1 = r16_r(IR[0]); - TMP2 = r16_r((IR[0] >> 4) & 7); + m_TMP1 = r16_r(m_IR[0]); + m_TMP2 = r16_r((m_IR[0] >> 4) & 7); prefetch_start internal(1); - TMP2 -= 2; - r16_w((IR[0] >> 4) & 7, TMP2); - set_nzv16(TMP1); - write16(TMP2, TMP1); + m_TMP2 -= 2; + r16_w((m_IR[0] >> 4) & 7, m_TMP2); + set_nzv16(m_TMP1); + write16(m_TMP2, m_TMP1); prefetch_done(); 6d80 ff80 0 mov.w r16l pr32h h - TMP1 = r16_r(IR[0]); - TMP2 = r32_r(IR[0] >> 4); + m_TMP1 = r16_r(m_IR[0]); + m_TMP2 = r32_r(m_IR[0] >> 4); prefetch_start internal(1); - TMP2 -= 2; - r32_w(IR[0] >> 4, TMP2); - set_nzv16(TMP1); - write16(TMP2, TMP1); + m_TMP2 -= 2; + r32_w(m_IR[0] >> 4, m_TMP2); + set_nzv16(m_TMP1); + write16(m_TMP2, m_TMP1); prefetch_done(); 6e00 ff80 0 mov.b r16d16h r8l o prefetch_start - TMP1 = uint16_t(r16_r(IR[0] >> 4) + IR[1]); - TMP2 = read8(TMP1); - set_nzv8(TMP2); - r8_w(IR[0], TMP2); + m_TMP1 = uint16_t(r16_r(m_IR[0] >> 4) + m_IR[1]); + m_TMP2 = read8(m_TMP1); + set_nzv8(m_TMP2); + r8_w(m_IR[0], m_TMP2); prefetch_done(); 6e00 ff80 0 mov.b r32d16h r8l h prefetch_start - TMP1 = r32_r(IR[0] >> 4) + int16_t(IR[1]); - TMP2 = read8(TMP1); - set_nzv8(TMP2); - r8_w(IR[0], TMP2); + m_TMP1 = r32_r(m_IR[0] >> 4) + int16_t(m_IR[1]); + m_TMP2 = read8(m_TMP1); + set_nzv8(m_TMP2); + r8_w(m_IR[0], m_TMP2); prefetch_done(); 6e80 ff80 0 mov.b r8l r16d16h o prefetch_start - TMP1 = uint16_t(r16_r((IR[0] >> 4) & 7) + IR[1]); - TMP2 = r8_r(IR[0]); - set_nzv8(TMP2); - write8(TMP1, TMP2); + m_TMP1 = uint16_t(r16_r((m_IR[0] >> 4) & 7) + m_IR[1]); + m_TMP2 = r8_r(m_IR[0]); + set_nzv8(m_TMP2); + write8(m_TMP1, m_TMP2); prefetch_done(); 6e80 ff80 0 mov.b r8l r32d16h h prefetch_start - TMP1 = r32_r(IR[0] >> 4) + int16_t(IR[1]); - TMP2 = r8_r(IR[0]); - set_nzv8(TMP2); - write8(TMP1, TMP2); + m_TMP1 = r32_r(m_IR[0] >> 4) + int16_t(m_IR[1]); + m_TMP2 = r8_r(m_IR[0]); + set_nzv8(m_TMP2); + write8(m_TMP1, m_TMP2); prefetch_done(); 6f00 ff80 0 mov.w r16d16h r16l o prefetch_start - TMP1 = uint16_t(r16_r(IR[0] >> 4) + IR[1]); - TMP2 = read16(TMP1); - set_nzv16(TMP2); - r16_w(IR[0], TMP2); + m_TMP1 = uint16_t(r16_r(m_IR[0] >> 4) + m_IR[1]); + m_TMP2 = read16(m_TMP1); + set_nzv16(m_TMP2); + r16_w(m_IR[0], m_TMP2); prefetch_done(); 6f00 ff80 0 mov.w r32d16h r16l h prefetch_start - TMP1 = r32_r(IR[0] >> 4) + int16_t(IR[1]); - TMP2 = read16(TMP1); - set_nzv16(TMP2); - r16_w(IR[0], TMP2); + m_TMP1 = r32_r(m_IR[0] >> 4) + int16_t(m_IR[1]); + m_TMP2 = read16(m_TMP1); + set_nzv16(m_TMP2); + r16_w(m_IR[0], m_TMP2); prefetch_done(); 6f80 ff80 0 mov.w r16l r16d16h o prefetch_start - TMP1 = uint16_t(r16_r((IR[0] >> 4) & 7) + IR[1]); - TMP2 = r16_r(IR[0]); - set_nzv16(TMP2); - write16(TMP1, TMP2); + m_TMP1 = uint16_t(r16_r((m_IR[0] >> 4) & 7) + m_IR[1]); + m_TMP2 = r16_r(m_IR[0]); + set_nzv16(m_TMP2); + write16(m_TMP1, m_TMP2); prefetch_done(); 6f80 ff80 0 mov.w r16l r32d16h h prefetch_start - TMP1 = r32_r(IR[0] >> 4) + int16_t(IR[1]); - TMP2 = r16_r(IR[0]); - set_nzv16(TMP2); - write16(TMP1, TMP2); + m_TMP1 = r32_r(m_IR[0] >> 4) + int16_t(m_IR[1]); + m_TMP2 = r16_r(m_IR[0]); + set_nzv16(m_TMP2); + write16(m_TMP1, m_TMP2); prefetch_done(); 7000 ff80 0 bset imm3 r8l - TMP1 = r8_r(IR[0]); - bset IR[0] >> 4 - r8_w(IR[0], TMP1); + m_TMP1 = r8_r(m_IR[0]); + bset m_IR[0] >> 4 + r8_w(m_IR[0], m_TMP1); prefetch 7100 ff80 0 bnot imm3 r8l - TMP1 = r8_r(IR[0]); - bnot IR[0] >> 4 - r8_w(IR[0], TMP1); + m_TMP1 = r8_r(m_IR[0]); + bnot m_IR[0] >> 4 + r8_w(m_IR[0], m_TMP1); prefetch 7200 ff80 0 bclr imm3 r8l - TMP1 = r8_r(IR[0]); - bclr IR[0] >> 4 - r8_w(IR[0], TMP1); + m_TMP1 = r8_r(m_IR[0]); + bclr m_IR[0] >> 4 + r8_w(m_IR[0], m_TMP1); prefetch 7300 ff80 0 btst imm3 r8l - TMP1 = r8_r(IR[0]); - btst IR[0] >> 4 + m_TMP1 = r8_r(m_IR[0]); + btst m_IR[0] >> 4 prefetch 7400 ff80 0 bor imm3 r8l - TMP1 = r8_r(IR[0]); - bor IR[0] >> 4 + m_TMP1 = r8_r(m_IR[0]); + bor m_IR[0] >> 4 prefetch 7480 ff80 0 bior imm3 r8l - TMP1 = r8_r(IR[0]); - bior IR[0] >> 4 + m_TMP1 = r8_r(m_IR[0]); + bior m_IR[0] >> 4 prefetch 7500 ff80 0 bxor imm3 r8l - TMP1 = r8_r(IR[0]); - bxor IR[0] >> 4 + m_TMP1 = r8_r(m_IR[0]); + bxor m_IR[0] >> 4 prefetch 7580 ff80 0 bixor imm3 r8l - TMP1 = r8_r(IR[0]); - bixor IR[0] >> 4 + m_TMP1 = r8_r(m_IR[0]); + bixor m_IR[0] >> 4 prefetch 7600 ff80 0 band imm3 r8l - TMP1 = r8_r(IR[0]); - band IR[0] >> 4 + m_TMP1 = r8_r(m_IR[0]); + band m_IR[0] >> 4 prefetch 7680 ff80 0 biand imm3 r8l - TMP1 = r8_r(IR[0]); - biand IR[0] >> 4 + m_TMP1 = r8_r(m_IR[0]); + biand m_IR[0] >> 4 prefetch 7700 ff80 0 bld imm3 r8l - TMP1 = r8_r(IR[0]); - bld IR[0] >> 4 + m_TMP1 = r8_r(m_IR[0]); + bld m_IR[0] >> 4 prefetch 7780 ff80 0 bild imm3 r8l - TMP1 = r8_r(IR[0]); - bild IR[0] >> 4 + m_TMP1 = r8_r(m_IR[0]); + bild m_IR[0] >> 4 prefetch 78006a20 ff8ffff0 0 mov.b r32d32hh r8l h prefetch_start - TMP1 = r32_r(IR[0] >> 4) + (IR[2] << 16) + IR[3]; - TMP2 = read8(TMP1); - set_nzv8(TMP2); - r8_w(IR[1], TMP2); + m_TMP1 = r32_r(m_IR[0] >> 4) + (m_IR[2] << 16) + m_IR[3]; + m_TMP2 = read8(m_TMP1); + set_nzv8(m_TMP2); + r8_w(m_IR[1], m_TMP2); prefetch_done(); 78006aa0 ff8ffff0 0 mov.b r8l r32d32hh h prefetch_start - TMP1 = r32_r(IR[0] >> 4) + (IR[2] << 16) + IR[3]; - TMP2 = r8_r(IR[1]); - set_nzv8(TMP2); - write8(TMP1, TMP2); + m_TMP1 = r32_r(m_IR[0] >> 4) + (m_IR[2] << 16) + m_IR[3]; + m_TMP2 = r8_r(m_IR[1]); + set_nzv8(m_TMP2); + write8(m_TMP1, m_TMP2); prefetch_done(); 78006b20 ff8ffff0 0 mov.w r32d32hh r16l h prefetch_start - TMP1 = r32_r(IR[0] >> 4) + (IR[2] << 16) + IR[3]; - TMP2 = read16(TMP1); - set_nzv16(TMP2); - r16_w(IR[1], TMP2); + m_TMP1 = r32_r(m_IR[0] >> 4) + (m_IR[2] << 16) + m_IR[3]; + m_TMP2 = read16(m_TMP1); + set_nzv16(m_TMP2); + r16_w(m_IR[1], m_TMP2); prefetch_done(); 78006ba0 ff8ffff0 0 mov.w r16l r32d32hh h prefetch_start - TMP1 = r32_r(IR[0] >> 4) + (IR[2] << 16) + IR[3]; - TMP2 = r16_r(IR[1]); - set_nzv16(TMP2); - write16(TMP1, TMP2); + m_TMP1 = r32_r(m_IR[0] >> 4) + (m_IR[2] << 16) + m_IR[3]; + m_TMP2 = r16_r(m_IR[1]); + set_nzv16(m_TMP2); + write16(m_TMP1, m_TMP2); prefetch_done(); 7900 fff0 0 mov.w imm16 r16l - set_nzv16(IR[1]); - r16_w(IR[0], IR[1]); + set_nzv16(m_IR[1]); + r16_w(m_IR[0], m_IR[1]); prefetch 7910 fff0 0 add.w imm16 r16l - r16_w(IR[0], do_add16(r16_r(IR[0]), IR[1])); + r16_w(m_IR[0], do_add16(r16_r(m_IR[0]), m_IR[1])); prefetch 7920 fff0 0 cmp.w imm16 r16l - do_sub16(r16_r(IR[0]), IR[1]); + do_sub16(r16_r(m_IR[0]), m_IR[1]); prefetch 7930 fff0 0 sub.w imm16 r16l - r16_w(IR[0], do_sub16(r16_r(IR[0]), IR[1])); + r16_w(m_IR[0], do_sub16(r16_r(m_IR[0]), m_IR[1])); prefetch 7940 fff0 0 or.w imm16 r16l - TMP1 = IR[1] | r16_r(IR[0]); - set_nzv16(TMP1); - r16_w(IR[0], TMP1); + m_TMP1 = m_IR[1] | r16_r(m_IR[0]); + set_nzv16(m_TMP1); + r16_w(m_IR[0], m_TMP1); prefetch 7950 fff0 0 xor.w imm16 r16l - TMP1 = IR[1] ^ r16_r(IR[0]); - set_nzv16(TMP1); - r16_w(IR[0], TMP1); + m_TMP1 = m_IR[1] ^ r16_r(m_IR[0]); + set_nzv16(m_TMP1); + r16_w(m_IR[0], m_TMP1); prefetch 7960 fff0 0 and.w imm16 r16l - TMP1 = IR[1] & r16_r(IR[0]); - set_nzv16(TMP1); - r16_w(IR[0], TMP1); + m_TMP1 = m_IR[1] & r16_r(m_IR[0]); + set_nzv16(m_TMP1); + r16_w(m_IR[0], m_TMP1); prefetch 7a00 fff8 0 mov.l imm32 r32l h - TMP1 = (IR[1] << 16) | IR[2]; - set_nzv32(TMP1); - r32_w(IR[0], TMP1); + m_TMP1 = (m_IR[1] << 16) | m_IR[2]; + set_nzv32(m_TMP1); + r32_w(m_IR[0], m_TMP1); prefetch 7a10 fff8 0 add.l imm32 r32l h - r32_w(IR[0], do_add32(r32_r(IR[0]), (IR[1] << 16) | IR[2])); + r32_w(m_IR[0], do_add32(r32_r(m_IR[0]), (m_IR[1] << 16) | m_IR[2])); prefetch 7a20 fff8 0 cmp.l imm32 r32l h - do_sub32(r32_r(IR[0]), (IR[1] << 16) | IR[2]); + do_sub32(r32_r(m_IR[0]), (m_IR[1] << 16) | m_IR[2]); prefetch 7a30 fff8 0 sub.l imm32 r32l h - r32_w(IR[0], do_sub32(r32_r(IR[0]), (IR[1] << 16) | IR[2])); + r32_w(m_IR[0], do_sub32(r32_r(m_IR[0]), (m_IR[1] << 16) | m_IR[2])); prefetch 7a40 fff8 0 or.l imm32 r32l h - TMP1 = r32_r(IR[0]) | ((IR[1] << 16) | IR[2]); - set_nzv32(TMP1); - r32_w(IR[0], TMP1); + m_TMP1 = r32_r(m_IR[0]) | ((m_IR[1] << 16) | m_IR[2]); + set_nzv32(m_TMP1); + r32_w(m_IR[0], m_TMP1); prefetch 7a50 fff8 0 xor.l imm32 r32l h - TMP1 = r32_r(IR[0]) ^ ((IR[1] << 16) | IR[2]); - set_nzv32(TMP1); - r32_w(IR[0], TMP1); + m_TMP1 = r32_r(m_IR[0]) ^ ((m_IR[1] << 16) | m_IR[2]); + set_nzv32(m_TMP1); + r32_w(m_IR[0], m_TMP1); prefetch 7a60 fff8 0 and.l imm32 r32l h - TMP1 = r32_r(IR[0]) & ((IR[1] << 16) | IR[2]); - set_nzv32(TMP1); - r32_w(IR[0], TMP1); + m_TMP1 = r32_r(m_IR[0]) & ((m_IR[1] << 16) | m_IR[2]); + set_nzv32(m_TMP1); + r32_w(m_IR[0], m_TMP1); prefetch 7b5c598f ffffffff 0 eepmov.b - - o while(r8_r(4+8)) { - TMP1 = read8(r16_r(5)); - write8(r16_r(6), TMP1); + m_TMP1 = read8(r16_r(5)); + write8(r16_r(6), m_TMP1); r16_w(5, r16_r(5)+1); r16_w(6, r16_r(6)+1); r8_w(4+8, r8_r(4+8)-1); @@ -2501,8 +2501,8 @@ macro jsr32 %opc %spreg 7b5c598f ffffffff 0 eepmov.b - - h while(r8_r(4+8)) { - TMP1 = read8(r32_r(5)); - write8(r32_r(6), TMP1); + m_TMP1 = read8(r32_r(5)); + write8(r32_r(6), m_TMP1); r32_w(5, r32_r(5)+1); r32_w(6, r32_r(6)+1); r8_w(4+8, r8_r(4+8)-1); @@ -2511,8 +2511,8 @@ macro jsr32 %opc %spreg 7bd4598f ffffffff 0 eepmov.w - - h while(r16_r(4)) { - TMP1 = read8(r32_r(5)); - write8(r32_r(6), TMP1); + m_TMP1 = read8(r32_r(5)); + write8(r32_r(6), m_TMP1); r32_w(5, r32_r(5)+1); r32_w(6, r32_r(6)+1); r16_w(4, r16_r(4)-1); @@ -2520,412 +2520,412 @@ macro jsr32 %opc %spreg prefetch 7c006300 ff8fff0f 0 btst r8h r16ihh o - TMP2 = r16_r(IR[0] >> 4); - TMP1 = read8(TMP2); - btst r8_r(IR[1] >> 4) + m_TMP2 = r16_r(m_IR[0] >> 4); + m_TMP1 = read8(m_TMP2); + btst r8_r(m_IR[1] >> 4) prefetch 7c006300 ff8fff0f 0 btst r8h r32ihh h - TMP2 = r32_r(IR[0] >> 4); - TMP1 = read8(TMP2); - btst r8_r(IR[1] >> 4) + m_TMP2 = r32_r(m_IR[0] >> 4); + m_TMP1 = read8(m_TMP2); + btst r8_r(m_IR[1] >> 4) prefetch 7c007300 ff8fff8f 0 btst imm3 r16ihh o - TMP2 = r16_r(IR[0] >> 4); - TMP1 = read8(TMP2); - btst IR[1] >> 4 + m_TMP2 = r16_r(m_IR[0] >> 4); + m_TMP1 = read8(m_TMP2); + btst m_IR[1] >> 4 prefetch 7c007300 ff8fff8f 0 btst imm3 r32ihh h - TMP2 = r32_r(IR[0] >> 4); - TMP1 = read8(TMP2); - btst IR[1] >> 4 + m_TMP2 = r32_r(m_IR[0] >> 4); + m_TMP1 = read8(m_TMP2); + btst m_IR[1] >> 4 prefetch 7c007400 ff8fff8f 0 bor imm3 r16ihh o - TMP2 = r16_r(IR[0] >> 4); - TMP1 = read8(TMP2); - bor IR[1] >> 4 + m_TMP2 = r16_r(m_IR[0] >> 4); + m_TMP1 = read8(m_TMP2); + bor m_IR[1] >> 4 prefetch 7c007400 ff8fff8f 0 bor imm3 r32ihh h - TMP2 = r32_r(IR[0] >> 4); - TMP1 = read8(TMP2); - bor IR[1] >> 4 + m_TMP2 = r32_r(m_IR[0] >> 4); + m_TMP1 = read8(m_TMP2); + bor m_IR[1] >> 4 prefetch 7c007480 ff8fff8f 0 bior imm3 r16ihh o - TMP2 = r16_r(IR[0] >> 4); - TMP1 = read8(TMP2); - bior IR[1] >> 4 + m_TMP2 = r16_r(m_IR[0] >> 4); + m_TMP1 = read8(m_TMP2); + bior m_IR[1] >> 4 prefetch 7c007480 ff8fff8f 0 bior imm3 r32ihh h - TMP2 = r32_r(IR[0] >> 4); - TMP1 = read8(TMP2); - bior IR[1] >> 4 + m_TMP2 = r32_r(m_IR[0] >> 4); + m_TMP1 = read8(m_TMP2); + bior m_IR[1] >> 4 prefetch 7c007500 ff8fff8f 0 bxor imm3 r16ihh o - TMP2 = r16_r(IR[0] >> 4); - TMP1 = read8(TMP2); - bxor IR[1] >> 4 + m_TMP2 = r16_r(m_IR[0] >> 4); + m_TMP1 = read8(m_TMP2); + bxor m_IR[1] >> 4 prefetch 7c007500 ff8fff8f 0 bxor imm3 r32ihh h - TMP2 = r32_r(IR[0] >> 4); - TMP1 = read8(TMP2); - bxor IR[1] >> 4 + m_TMP2 = r32_r(m_IR[0] >> 4); + m_TMP1 = read8(m_TMP2); + bxor m_IR[1] >> 4 prefetch 7c007580 ff8fff8f 0 bixor imm3 r16ihh o - TMP2 = r16_r(IR[0] >> 4); - TMP1 = read8(TMP2); - bixor IR[1] >> 4 + m_TMP2 = r16_r(m_IR[0] >> 4); + m_TMP1 = read8(m_TMP2); + bixor m_IR[1] >> 4 prefetch 7c007580 ff8fff8f 0 bixor imm3 r32ihh h - TMP2 = r32_r(IR[0] >> 4); - TMP1 = read8(TMP2); - bixor IR[1] >> 4 + m_TMP2 = r32_r(m_IR[0] >> 4); + m_TMP1 = read8(m_TMP2); + bixor m_IR[1] >> 4 prefetch 7c007600 ff8fff8f 0 band imm3 r16ihh o - TMP2 = r16_r(IR[0] >> 4); - TMP1 = read8(TMP2); - band IR[1] >> 4 + m_TMP2 = r16_r(m_IR[0] >> 4); + m_TMP1 = read8(m_TMP2); + band m_IR[1] >> 4 prefetch 7c007600 ff8fff8f 0 band imm3 r32ihh h - TMP2 = r32_r(IR[0] >> 4); - TMP1 = read8(TMP2); - band IR[1] >> 4 + m_TMP2 = r32_r(m_IR[0] >> 4); + m_TMP1 = read8(m_TMP2); + band m_IR[1] >> 4 prefetch 7c007680 ff8fff8f 0 biand imm3 r16ihh o - TMP2 = r16_r(IR[0] >> 4); - TMP1 = read8(TMP2); - biand IR[1] >> 4 + m_TMP2 = r16_r(m_IR[0] >> 4); + m_TMP1 = read8(m_TMP2); + biand m_IR[1] >> 4 prefetch 7c007680 ff8fff8f 0 biand imm3 r32ihh h - TMP2 = r32_r(IR[0] >> 4); - TMP1 = read8(TMP2); - biand IR[1] >> 4 + m_TMP2 = r32_r(m_IR[0] >> 4); + m_TMP1 = read8(m_TMP2); + biand m_IR[1] >> 4 prefetch 7c007700 ff8fff8f 0 bld imm3 r16ihh o - TMP2 = r16_r(IR[0] >> 4); - TMP1 = read8(TMP2); - bld IR[1] >> 4 + m_TMP2 = r16_r(m_IR[0] >> 4); + m_TMP1 = read8(m_TMP2); + bld m_IR[1] >> 4 prefetch 7c007700 ff8fff8f 0 bld imm3 r32ihh h - TMP2 = r32_r(IR[0] >> 4); - TMP1 = read8(TMP2); - bld IR[1] >> 4 + m_TMP2 = r32_r(m_IR[0] >> 4); + m_TMP1 = read8(m_TMP2); + bld m_IR[1] >> 4 prefetch 7c007780 ff8fff8f 0 bild imm3 r16ihh o - TMP2 = r16_r(IR[0] >> 4); - TMP1 = read8(TMP2); - bild IR[1] >> 4 + m_TMP2 = r16_r(m_IR[0] >> 4); + m_TMP1 = read8(m_TMP2); + bild m_IR[1] >> 4 prefetch 7c007780 ff8fff8f 0 bild imm3 r32ihh h - TMP2 = r32_r(IR[0] >> 4); - TMP1 = read8(TMP2); - bild IR[1] >> 4 + m_TMP2 = r32_r(m_IR[0] >> 4); + m_TMP1 = read8(m_TMP2); + bild m_IR[1] >> 4 prefetch 7d006000 ff8fff0f 0 bset r8h r16ihh o - TMP2 = r16_r(IR[0] >> 4); - TMP1 = read8(TMP2); - bset r8_r(IR[1] >> 4) + m_TMP2 = r16_r(m_IR[0] >> 4); + m_TMP1 = read8(m_TMP2); + bset r8_r(m_IR[1] >> 4) prefetch_start - write8(TMP2, TMP1); + write8(m_TMP2, m_TMP1); prefetch_done(); 7d006000 ff8fff0f 0 bset r8h r32ihh h - TMP2 = r32_r(IR[0] >> 4); - TMP1 = read8(TMP2); - bset r8_r(IR[1] >> 4) + m_TMP2 = r32_r(m_IR[0] >> 4); + m_TMP1 = read8(m_TMP2); + bset r8_r(m_IR[1] >> 4) prefetch_start - write8(TMP2, TMP1); + write8(m_TMP2, m_TMP1); prefetch_done(); 7d006100 ff8fff0f 0 bnot r8h r16ihh o - TMP2 = r16_r(IR[0] >> 4); - TMP1 = read8(TMP2); - bnot r8_r(IR[1] >> 4) + m_TMP2 = r16_r(m_IR[0] >> 4); + m_TMP1 = read8(m_TMP2); + bnot r8_r(m_IR[1] >> 4) prefetch_start - write8(TMP2, TMP1); + write8(m_TMP2, m_TMP1); prefetch_done(); 7d006100 ff8fff0f 0 bnot r8h r32ihh h - TMP2 = r32_r(IR[0] >> 4); - TMP1 = read8(TMP2); - bnot r8_r(IR[1] >> 4) + m_TMP2 = r32_r(m_IR[0] >> 4); + m_TMP1 = read8(m_TMP2); + bnot r8_r(m_IR[1] >> 4) prefetch_start - write8(TMP2, TMP1); + write8(m_TMP2, m_TMP1); prefetch_done(); 7d006200 ff8fff0f 0 bclr r8h r16ihh o - TMP2 = r16_r(IR[0] >> 4); - TMP1 = read8(TMP2); - bclr r8_r(IR[1] >> 4) + m_TMP2 = r16_r(m_IR[0] >> 4); + m_TMP1 = read8(m_TMP2); + bclr r8_r(m_IR[1] >> 4) prefetch_start - write8(TMP2, TMP1); + write8(m_TMP2, m_TMP1); prefetch_done(); 7d006200 ff8fff0f 0 bclr r8h r32ihh h - TMP2 = r32_r(IR[0] >> 4); - TMP1 = read8(TMP2); - bclr r8_r(IR[1] >> 4) + m_TMP2 = r32_r(m_IR[0] >> 4); + m_TMP1 = read8(m_TMP2); + bclr r8_r(m_IR[1] >> 4) prefetch_start - write8(TMP2, TMP1); + write8(m_TMP2, m_TMP1); prefetch_done(); 7d006700 ff8fff8f 0 bst imm3 r16ihh o - TMP2 = r16_r(IR[0] >> 4); - TMP1 = read8(TMP2); - bst IR[1] >> 4 + m_TMP2 = r16_r(m_IR[0] >> 4); + m_TMP1 = read8(m_TMP2); + bst m_IR[1] >> 4 prefetch_start - write8(TMP2, TMP1); + write8(m_TMP2, m_TMP1); prefetch_done(); 7d006700 ff8fff8f 0 bst imm3 r32ihh h - TMP2 = r32_r(IR[0] >> 4); - TMP1 = read8(TMP2); - bst IR[1] >> 4 + m_TMP2 = r32_r(m_IR[0] >> 4); + m_TMP1 = read8(m_TMP2); + bst m_IR[1] >> 4 prefetch_start - write8(TMP2, TMP1); + write8(m_TMP2, m_TMP1); prefetch_done(); 7d006780 ff8fff8f 0 bist imm3 r16ihh o - TMP2 = r16_r(IR[0] >> 4); - TMP1 = read8(TMP2); - bist IR[1] >> 4 + m_TMP2 = r16_r(m_IR[0] >> 4); + m_TMP1 = read8(m_TMP2); + bist m_IR[1] >> 4 prefetch_start - write8(TMP2, TMP1); + write8(m_TMP2, m_TMP1); prefetch_done(); 7d006780 ff8fff8f 0 bist imm3 r32ihh h - TMP2 = r32_r(IR[0] >> 4); - TMP1 = read8(TMP2); - bist IR[1] >> 4 + m_TMP2 = r32_r(m_IR[0] >> 4); + m_TMP1 = read8(m_TMP2); + bist m_IR[1] >> 4 prefetch_start - write8(TMP2, TMP1); + write8(m_TMP2, m_TMP1); prefetch_done(); 7d007000 ff8fff8f 0 bset imm3 r16ihh o - TMP2 = r16_r(IR[0] >> 4); - TMP1 = read8(TMP2); - bset IR[1] >> 4 + m_TMP2 = r16_r(m_IR[0] >> 4); + m_TMP1 = read8(m_TMP2); + bset m_IR[1] >> 4 prefetch_start - write8(TMP2, TMP1); + write8(m_TMP2, m_TMP1); prefetch_done(); 7d007000 ff8fff8f 0 bset imm3 r32ihh h - TMP2 = r32_r(IR[0] >> 4); - TMP1 = read8(TMP2); - bset IR[1] >> 4 + m_TMP2 = r32_r(m_IR[0] >> 4); + m_TMP1 = read8(m_TMP2); + bset m_IR[1] >> 4 prefetch_start - write8(TMP2, TMP1); + write8(m_TMP2, m_TMP1); prefetch_done(); 7d007100 ff8fff8f 0 bnot imm3 r16ihh o - TMP2 = r16_r(IR[0] >> 4); - TMP1 = read8(TMP2); - bnot IR[1] >> 4 + m_TMP2 = r16_r(m_IR[0] >> 4); + m_TMP1 = read8(m_TMP2); + bnot m_IR[1] >> 4 prefetch_start - write8(TMP2, TMP1); + write8(m_TMP2, m_TMP1); prefetch_done(); 7d007100 ff8fff8f 0 bnot imm3 r32ihh h - TMP2 = r32_r(IR[0] >> 4); - TMP1 = read8(TMP2); - bnot IR[1] >> 4 + m_TMP2 = r32_r(m_IR[0] >> 4); + m_TMP1 = read8(m_TMP2); + bnot m_IR[1] >> 4 prefetch_start - write8(TMP2, TMP1); + write8(m_TMP2, m_TMP1); prefetch_done(); 7d007200 ff8fff8f 0 bclr imm3 r16ihh o - TMP2 = r16_r(IR[0] >> 4); - TMP1 = read8(TMP2); - bclr IR[1] >> 4 + m_TMP2 = r16_r(m_IR[0] >> 4); + m_TMP1 = read8(m_TMP2); + bclr m_IR[1] >> 4 prefetch_start - write8(TMP2, TMP1); + write8(m_TMP2, m_TMP1); prefetch_done(); 7d007200 ff8fff8f 0 bclr imm3 r32ihh h - TMP2 = r32_r(IR[0] >> 4); - TMP1 = read8(TMP2); - bclr IR[1] >> 4 + m_TMP2 = r32_r(m_IR[0] >> 4); + m_TMP1 = read8(m_TMP2); + bclr m_IR[1] >> 4 prefetch_start - write8(TMP2, TMP1); + write8(m_TMP2, m_TMP1); prefetch_done(); 7e006300 ff00ff0f 0 btst r8h abs8 - TMP2 = 0xffffff00 | IR[0]; - TMP1 = read8(TMP2); - btst r8_r(IR[1] >> 4) + m_TMP2 = 0xffffff00 | m_IR[0]; + m_TMP1 = read8(m_TMP2); + btst r8_r(m_IR[1] >> 4) prefetch 7e007300 ff00ff8f 0 btst imm3 abs8 - TMP2 = 0xffffff00 | IR[0]; - TMP1 = read8(TMP2); - btst IR[1] >> 4 + m_TMP2 = 0xffffff00 | m_IR[0]; + m_TMP1 = read8(m_TMP2); + btst m_IR[1] >> 4 prefetch 7e007400 ff00ff8f 0 bor imm3 abs8 - TMP2 = 0xffffff00 | IR[0]; - TMP1 = read8(TMP2); - bor IR[1] >> 4 + m_TMP2 = 0xffffff00 | m_IR[0]; + m_TMP1 = read8(m_TMP2); + bor m_IR[1] >> 4 prefetch 7e007480 ff00ff8f 0 bior imm3 abs8 - TMP2 = 0xffffff00 | IR[0]; - TMP1 = read8(TMP2); - bior IR[1] >> 4 + m_TMP2 = 0xffffff00 | m_IR[0]; + m_TMP1 = read8(m_TMP2); + bior m_IR[1] >> 4 prefetch 7e007500 ff00ff8f 0 bxor imm3 abs8 - TMP2 = 0xffffff00 | IR[0]; - TMP1 = read8(TMP2); - bxor IR[1] >> 4 + m_TMP2 = 0xffffff00 | m_IR[0]; + m_TMP1 = read8(m_TMP2); + bxor m_IR[1] >> 4 prefetch 7e007580 ff00ff8f 0 bixor imm3 abs8 - TMP2 = 0xffffff00 | IR[0]; - TMP1 = read8(TMP2); - bixor IR[1] >> 4 + m_TMP2 = 0xffffff00 | m_IR[0]; + m_TMP1 = read8(m_TMP2); + bixor m_IR[1] >> 4 prefetch 7e007600 ff00ff8f 0 band imm3 abs8 - TMP2 = 0xffffff00 | IR[0]; - TMP1 = read8(TMP2); - band IR[1] >> 4 + m_TMP2 = 0xffffff00 | m_IR[0]; + m_TMP1 = read8(m_TMP2); + band m_IR[1] >> 4 prefetch 7e007680 ff00ff8f 0 biand imm3 abs8 - TMP2 = 0xffffff00 | IR[0]; - TMP1 = read8(TMP2); - biand IR[1] >> 4 + m_TMP2 = 0xffffff00 | m_IR[0]; + m_TMP1 = read8(m_TMP2); + biand m_IR[1] >> 4 prefetch 7e007700 ff00ff8f 0 bld imm3 abs8 - TMP2 = 0xffffff00 | IR[0]; - TMP1 = read8(TMP2); - bld IR[1] >> 4 + m_TMP2 = 0xffffff00 | m_IR[0]; + m_TMP1 = read8(m_TMP2); + bld m_IR[1] >> 4 prefetch 7e007780 ff00ff8f 0 bild imm3 abs8 - TMP2 = 0xffffff00 | IR[0]; - TMP1 = read8(TMP2); - bild IR[1] >> 4 + m_TMP2 = 0xffffff00 | m_IR[0]; + m_TMP1 = read8(m_TMP2); + bild m_IR[1] >> 4 prefetch 7f006000 ff00ff0f 0 bset r8h abs8 - TMP2 = 0xffffff00 | IR[0]; - TMP1 = read8(TMP2); - bset r8_r(IR[1] >> 4) + m_TMP2 = 0xffffff00 | m_IR[0]; + m_TMP1 = read8(m_TMP2); + bset r8_r(m_IR[1] >> 4) prefetch_start - write8(TMP2, TMP1); + write8(m_TMP2, m_TMP1); prefetch_done(); 7f006100 ff00ff0f 0 bnot r8h abs8 - TMP2 = 0xffffff00 | IR[0]; - TMP1 = read8(TMP2); - bnot r8_r(IR[1] >> 4) + m_TMP2 = 0xffffff00 | m_IR[0]; + m_TMP1 = read8(m_TMP2); + bnot r8_r(m_IR[1] >> 4) prefetch_start - write8(TMP2, TMP1); + write8(m_TMP2, m_TMP1); prefetch_done(); 7f006200 ff00ff0f 0 bclr r8h abs8 - TMP2 = 0xffffff00 | IR[0]; - TMP1 = read8(TMP2); - bclr r8_r(IR[1] >> 4) + m_TMP2 = 0xffffff00 | m_IR[0]; + m_TMP1 = read8(m_TMP2); + bclr r8_r(m_IR[1] >> 4) prefetch_start - write8(TMP2, TMP1); + write8(m_TMP2, m_TMP1); prefetch_done(); 7f006700 ff00ff8f 0 bst imm3 abs8 - TMP2 = 0xffffff00 | IR[0]; - TMP1 = read8(TMP2); + m_TMP2 = 0xffffff00 | m_IR[0]; + m_TMP1 = read8(m_TMP2); prefetch_start - bst IR[0] >> 4 - write8(TMP2, TMP1); + bst m_IR[0] >> 4 + write8(m_TMP2, m_TMP1); prefetch_done(); 7f006780 ff00ff8f 0 bist imm3 abs8 - TMP2 = 0xffffff00 | IR[0]; - TMP1 = read8(TMP2); + m_TMP2 = 0xffffff00 | m_IR[0]; + m_TMP1 = read8(m_TMP2); prefetch_start - bist IR[0] >> 4 - write8(TMP2, TMP1); + bist m_IR[0] >> 4 + write8(m_TMP2, m_TMP1); prefetch_done(); 7f007000 ff00ff8f 0 bset imm3 abs8 - TMP2 = 0xffffff00 | IR[0]; - TMP1 = read8(TMP2); + m_TMP2 = 0xffffff00 | m_IR[0]; + m_TMP1 = read8(m_TMP2); prefetch_start - bset IR[1] >> 4 - write8(TMP2, TMP1); + bset m_IR[1] >> 4 + write8(m_TMP2, m_TMP1); prefetch_done(); 7f007100 ff00ff8f 0 bnot imm3 abs8 - TMP2 = 0xffffff00 | IR[0]; - TMP1 = read8(TMP2); + m_TMP2 = 0xffffff00 | m_IR[0]; + m_TMP1 = read8(m_TMP2); prefetch_start - bnot IR[1] >> 4 - write8(TMP2, TMP1); + bnot m_IR[1] >> 4 + write8(m_TMP2, m_TMP1); prefetch_done(); 7f007200 ff00ff8f 0 bclr imm3 abs8 - TMP2 = 0xffffff00 | IR[0]; - TMP1 = read8(TMP2); + m_TMP2 = 0xffffff00 | m_IR[0]; + m_TMP1 = read8(m_TMP2); prefetch_start - bclr IR[1] >> 4 - write8(TMP2, TMP1); + bclr m_IR[1] >> 4 + write8(m_TMP2, m_TMP1); prefetch_done(); 8000 f000 0 add.b imm8 r8u - r8_w(IR[0] >> 8, do_add8(r8_r(IR[0] >> 8), IR[0])); + r8_w(m_IR[0] >> 8, do_add8(r8_r(m_IR[0] >> 8), m_IR[0])); prefetch 9000 f000 0 addx.b imm8 r8u - r8_w(IR[0] >> 8, do_addx8(r8_r(IR[0] >> 8), IR[0])); + r8_w(m_IR[0] >> 8, do_addx8(r8_r(m_IR[0] >> 8), m_IR[0])); prefetch a000 f000 0 cmp.b imm8 r8u - do_sub8(r8_r(IR[0]>>8), IR[0]); + do_sub8(r8_r(m_IR[0]>>8), m_IR[0]); prefetch b000 f000 0 subx.b imm8 r8u - r8_w(IR[0] >> 8, do_subx8(r8_r(IR[0] >> 8), IR[0])); + r8_w(m_IR[0] >> 8, do_subx8(r8_r(m_IR[0] >> 8), m_IR[0])); prefetch c000 f000 0 or.b imm8 r8u - TMP1 = IR[0] | r8_r(IR[0] >> 8); - set_nzv8(TMP1); - r8_w(IR[0] >> 8, TMP1); + m_TMP1 = m_IR[0] | r8_r(m_IR[0] >> 8); + set_nzv8(m_TMP1); + r8_w(m_IR[0] >> 8, m_TMP1); prefetch d000 f000 0 xor.b imm8 r8u - TMP1 = IR[0] ^ r8_r(IR[0] >> 8); - set_nzv8(TMP1); - r8_w(IR[0] >> 8, TMP1); + m_TMP1 = m_IR[0] ^ r8_r(m_IR[0] >> 8); + set_nzv8(m_TMP1); + r8_w(m_IR[0] >> 8, m_TMP1); prefetch e000 f000 0 and.b imm8 r8u - TMP1 = IR[0] & r8_r(IR[0] >> 8); - set_nzv8(TMP1); - r8_w(IR[0] >> 8, TMP1); + m_TMP1 = m_IR[0] & r8_r(m_IR[0] >> 8); + set_nzv8(m_TMP1); + r8_w(m_IR[0] >> 8, m_TMP1); prefetch f000 f000 0 mov.b imm8 r8u - set_nzv8(IR[0]); - r8_w(IR[0] >> 8, IR[0]); + set_nzv8(m_IR[0]); + r8_w(m_IR[0] >> 8, m_IR[0]); prefetch diff --git a/src/devices/cpu/h8/h83002.cpp b/src/devices/cpu/h8/h83002.cpp index 9451a299010..7dae9908f21 100644 --- a/src/devices/cpu/h8/h83002.cpp +++ b/src/devices/cpu/h8/h83002.cpp @@ -7,35 +7,35 @@ DEFINE_DEVICE_TYPE(H83002, h83002_device, "h83002", "Hitachi H8/3002") h83002_device::h83002_device(const machine_config &mconfig, const char *tag, device_t *owner, uint32_t clock) : h8h_device(mconfig, H83002, tag, owner, clock, address_map_constructor(FUNC(h83002_device::map), this)), - intc(*this, "intc"), - adc(*this, "adc"), - dma(*this, "dma"), - dma0(*this, "dma:0"), - dma1(*this, "dma:1"), - port4(*this, "port4"), - port6(*this, "port6"), - port7(*this, "port7"), - port8(*this, "port8"), - port9(*this, "port9"), - porta(*this, "porta"), - portb(*this, "portb"), - timer16(*this, "timer16"), - timer16_0(*this, "timer16:0"), - timer16_1(*this, "timer16:1"), - timer16_2(*this, "timer16:2"), - timer16_3(*this, "timer16:3"), - timer16_4(*this, "timer16:4"), - sci0(*this, "sci0"), - sci1(*this, "sci1"), - watchdog(*this, "watchdog"), - tend_cb(*this) + m_intc(*this, "intc"), + m_adc(*this, "adc"), + m_dma(*this, "dma"), + m_dma0(*this, "dma:0"), + m_dma1(*this, "dma:1"), + m_port4(*this, "port4"), + m_port6(*this, "port6"), + m_port7(*this, "port7"), + m_port8(*this, "port8"), + m_port9(*this, "port9"), + m_porta(*this, "porta"), + m_portb(*this, "portb"), + m_timer16(*this, "timer16"), + m_timer16_0(*this, "timer16:0"), + m_timer16_1(*this, "timer16:1"), + m_timer16_2(*this, "timer16:2"), + m_timer16_3(*this, "timer16:3"), + m_timer16_4(*this, "timer16:4"), + m_sci0(*this, "sci0"), + m_sci1(*this, "sci1"), + m_watchdog(*this, "watchdog"), + m_tend_cb(*this) { - syscr = 0; + m_syscr = 0; } void h83002_device::map(address_map &map) { - const offs_t base = mode_a20 ? 0xf0000 : 0xff0000; + const offs_t base = m_mode_a20 ? 0xf0000 : 0xff0000; map(base | 0xfd10, base | 0xff0f).ram(); @@ -170,70 +170,70 @@ void h83002_device::device_add_mconfig(machine_config &config) void h83002_device::execute_set_input(int inputnum, int state) { if(inputnum == H8_INPUT_LINE_TEND0 || inputnum == H8_INPUT_LINE_TEND1) { - if(!tend_cb[inputnum - H8_INPUT_LINE_TEND0].isnull()) - tend_cb[inputnum - H8_INPUT_LINE_TEND0](state); + if(!m_tend_cb[inputnum - H8_INPUT_LINE_TEND0].isnull()) + m_tend_cb[inputnum - H8_INPUT_LINE_TEND0](state); } else if(inputnum == H8_INPUT_LINE_DREQ0 || inputnum == H8_INPUT_LINE_DREQ1) - dma->set_input(inputnum, state); + m_dma->set_input(inputnum, state); else - intc->set_input(inputnum, state); + m_intc->set_input(inputnum, state); } int h83002_device::trapa_setup() { - if(syscr & 0x08) - CCR |= F_I; + if(m_syscr & 0x08) + m_CCR |= F_I; else - CCR |= F_I|F_UI; + m_CCR |= F_I|F_UI; return 8; } void h83002_device::irq_setup() { - if(syscr & 0x08) - CCR |= F_I; + if(m_syscr & 0x08) + m_CCR |= F_I; else - CCR |= F_I|F_UI; + m_CCR |= F_I|F_UI; } void h83002_device::update_irq_filter() { - switch(syscr & 0x08) { + switch(m_syscr & 0x08) { case 0x00: - if((CCR & (F_I|F_UI)) == (F_I|F_UI)) - intc->set_filter(2, -1); - else if(CCR & F_I) - intc->set_filter(1, -1); + if((m_CCR & (F_I|F_UI)) == (F_I|F_UI)) + m_intc->set_filter(2, -1); + else if(m_CCR & F_I) + m_intc->set_filter(1, -1); else - intc->set_filter(0, -1); + m_intc->set_filter(0, -1); break; case 0x08: - if(CCR & F_I) - intc->set_filter(2, -1); + if(m_CCR & F_I) + m_intc->set_filter(2, -1); else - intc->set_filter(0, -1); + m_intc->set_filter(0, -1); break; } } void h83002_device::interrupt_taken() { - standard_irq_callback(intc->interrupt_taken(taken_irq_vector), NPC); + standard_irq_callback(m_intc->interrupt_taken(m_taken_irq_vector), m_NPC); } void h83002_device::internal_update(uint64_t current_time) { uint64_t event_time = 0; - add_event(event_time, adc->internal_update(current_time)); - add_event(event_time, sci0->internal_update(current_time)); - add_event(event_time, sci1->internal_update(current_time)); - add_event(event_time, timer16_0->internal_update(current_time)); - add_event(event_time, timer16_1->internal_update(current_time)); - add_event(event_time, timer16_2->internal_update(current_time)); - add_event(event_time, timer16_3->internal_update(current_time)); - add_event(event_time, timer16_4->internal_update(current_time)); - add_event(event_time, watchdog->internal_update(current_time)); + add_event(event_time, m_adc->internal_update(current_time)); + add_event(event_time, m_sci0->internal_update(current_time)); + add_event(event_time, m_sci1->internal_update(current_time)); + add_event(event_time, m_timer16_0->internal_update(current_time)); + add_event(event_time, m_timer16_1->internal_update(current_time)); + add_event(event_time, m_timer16_2->internal_update(current_time)); + add_event(event_time, m_timer16_3->internal_update(current_time)); + add_event(event_time, m_timer16_4->internal_update(current_time)); + add_event(event_time, m_watchdog->internal_update(current_time)); recompute_bcount(event_time); } @@ -241,25 +241,25 @@ void h83002_device::internal_update(uint64_t current_time) void h83002_device::device_start() { h8h_device::device_start(); - dma_device = dma; + m_dma_device = m_dma; - tend_cb.resolve_all(); + m_tend_cb.resolve_all(); } void h83002_device::device_reset() { h8h_device::device_reset(); - syscr = 0x09; + m_syscr = 0x09; } uint8_t h83002_device::syscr_r() { - return syscr; + return m_syscr; } void h83002_device::syscr_w(uint8_t data) { - syscr = data; + m_syscr = data; update_irq_filter(); logerror("syscr = %02x\n", data); } @@ -267,11 +267,11 @@ void h83002_device::syscr_w(uint8_t data) uint8_t h83002_device::rtmcsr_r() { // set bit 7 -- Compare Match Flag (CMF): This status flag indicates that the RTCNT and RTCOR values have matched. - return rtmcsr | 0x80; + return m_rtmcsr | 0x80; } void h83002_device::rtmcsr_w(uint8_t data) { - rtmcsr = data; + m_rtmcsr = data; logerror("rtmcsr = %02x\n", data); } diff --git a/src/devices/cpu/h8/h83002.h b/src/devices/cpu/h8/h83002.h index 672450f036f..8cbb9eb117b 100644 --- a/src/devices/cpu/h8/h83002.h +++ b/src/devices/cpu/h8/h83002.h @@ -29,11 +29,11 @@ class h83002_device : public h8h_device { public: h83002_device(const machine_config &mconfig, const char *tag, device_t *owner, uint32_t clock); - auto tend0() { return tend_cb[0].bind(); } - auto tend1() { return tend_cb[1].bind(); } + auto tend0() { return m_tend_cb[0].bind(); } + auto tend1() { return m_tend_cb[1].bind(); } - void set_mode_a20() { mode_a20 = true; } - void set_mode_a24() { mode_a20 = false; } + void set_mode_a20() { m_mode_a20 = true; } + void set_mode_a24() { m_mode_a20 = false; } uint8_t syscr_r(); void syscr_w(uint8_t data); @@ -42,32 +42,32 @@ public: void rtmcsr_w(uint8_t data); protected: - required_device intc; - required_device adc; - optional_device dma; - optional_device dma0; - optional_device dma1; - required_device port4; - required_device port6; - required_device port7; - required_device port8; - required_device port9; - required_device porta; - required_device portb; - required_device timer16; - required_device timer16_0; - required_device timer16_1; - required_device timer16_2; - required_device timer16_3; - required_device timer16_4; - required_device sci0; - required_device sci1; - required_device watchdog; - - uint8_t syscr; - uint8_t rtmcsr; - - devcb_write_line::array<2> tend_cb; + required_device m_intc; + required_device m_adc; + optional_device m_dma; + optional_device m_dma0; + optional_device m_dma1; + required_device m_port4; + required_device m_port6; + required_device m_port7; + required_device m_port8; + required_device m_port9; + required_device m_porta; + required_device m_portb; + required_device m_timer16; + required_device m_timer16_0; + required_device m_timer16_1; + required_device m_timer16_2; + required_device m_timer16_3; + required_device m_timer16_4; + required_device m_sci0; + required_device m_sci1; + required_device m_watchdog; + + uint8_t m_syscr; + uint8_t m_rtmcsr; + + devcb_write_line::array<2> m_tend_cb; virtual void update_irq_filter() override; virtual void interrupt_taken() override; diff --git a/src/devices/cpu/h8/h83003.cpp b/src/devices/cpu/h8/h83003.cpp index caea06c3cd4..1d6301d8d68 100644 --- a/src/devices/cpu/h8/h83003.cpp +++ b/src/devices/cpu/h8/h83003.cpp @@ -7,36 +7,36 @@ DEFINE_DEVICE_TYPE(H83003, h83003_device, "h83003", "Hitachi H8/3003") h83003_device::h83003_device(const machine_config &mconfig, const char *tag, device_t *owner, uint32_t clock) : h8h_device(mconfig, H83003, tag, owner, clock, address_map_constructor(FUNC(h83003_device::map), this)), - intc(*this, "intc"), - adc(*this, "adc"), - dma(*this, "dma"), - dma0(*this, "dma:0"), - dma1(*this, "dma:1"), - dma2(*this, "dma:2"), - port4(*this, "port4"), - port6(*this, "port6"), - port7(*this, "port7"), - port8(*this, "port8"), - port9(*this, "port9"), - porta(*this, "porta"), - portb(*this, "portb"), - timer16(*this, "timer16"), - timer16_0(*this, "timer16:0"), - timer16_1(*this, "timer16:1"), - timer16_2(*this, "timer16:2"), - timer16_3(*this, "timer16:3"), - timer16_4(*this, "timer16:4"), - sci0(*this, "sci0"), - sci1(*this, "sci1"), - watchdog(*this, "watchdog"), - tend_cb(*this) + m_intc(*this, "intc"), + m_adc(*this, "adc"), + m_dma(*this, "dma"), + m_dma0(*this, "dma:0"), + m_dma1(*this, "dma:1"), + m_dma2(*this, "dma:2"), + m_port4(*this, "port4"), + m_port6(*this, "port6"), + m_port7(*this, "port7"), + m_port8(*this, "port8"), + m_port9(*this, "port9"), + m_porta(*this, "porta"), + m_portb(*this, "portb"), + m_timer16(*this, "timer16"), + m_timer16_0(*this, "timer16:0"), + m_timer16_1(*this, "timer16:1"), + m_timer16_2(*this, "timer16:2"), + m_timer16_3(*this, "timer16:3"), + m_timer16_4(*this, "timer16:4"), + m_sci0(*this, "sci0"), + m_sci1(*this, "sci1"), + m_watchdog(*this, "watchdog"), + m_tend_cb(*this) { - syscr = 0; + m_syscr = 0; } void h83003_device::map(address_map &map) { - const offs_t base = mode_a20 ? 0xf0000 : 0xff0000; + const offs_t base = m_mode_a20 ? 0xf0000 : 0xff0000; map(base | 0xfd10, base | 0xff0f).ram(); @@ -191,70 +191,70 @@ void h83003_device::device_add_mconfig(machine_config &config) void h83003_device::execute_set_input(int inputnum, int state) { if(inputnum >= H8_INPUT_LINE_TEND0 && inputnum <= H8_INPUT_LINE_TEND3) { - if(!tend_cb[inputnum - H8_INPUT_LINE_TEND0].isnull()) - tend_cb[inputnum - H8_INPUT_LINE_TEND0](state); + if(!m_tend_cb[inputnum - H8_INPUT_LINE_TEND0].isnull()) + m_tend_cb[inputnum - H8_INPUT_LINE_TEND0](state); } else if(inputnum >= H8_INPUT_LINE_DREQ0 && inputnum <= H8_INPUT_LINE_DREQ3) - dma->set_input(inputnum, state); + m_dma->set_input(inputnum, state); else - intc->set_input(inputnum, state); + m_intc->set_input(inputnum, state); } int h83003_device::trapa_setup() { - if(syscr & 0x08) - CCR |= F_I; + if(m_syscr & 0x08) + m_CCR |= F_I; else - CCR |= F_I|F_UI; + m_CCR |= F_I|F_UI; return 8; } void h83003_device::irq_setup() { - if(syscr & 0x08) - CCR |= F_I; + if(m_syscr & 0x08) + m_CCR |= F_I; else - CCR |= F_I|F_UI; + m_CCR |= F_I|F_UI; } void h83003_device::update_irq_filter() { - switch(syscr & 0x08) { + switch(m_syscr & 0x08) { case 0x00: - if((CCR & (F_I|F_UI)) == (F_I|F_UI)) - intc->set_filter(2, -1); - else if(CCR & F_I) - intc->set_filter(1, -1); + if((m_CCR & (F_I|F_UI)) == (F_I|F_UI)) + m_intc->set_filter(2, -1); + else if(m_CCR & F_I) + m_intc->set_filter(1, -1); else - intc->set_filter(0, -1); + m_intc->set_filter(0, -1); break; case 0x08: - if(CCR & F_I) - intc->set_filter(2, -1); + if(m_CCR & F_I) + m_intc->set_filter(2, -1); else - intc->set_filter(0, -1); + m_intc->set_filter(0, -1); break; } } void h83003_device::interrupt_taken() { - standard_irq_callback(intc->interrupt_taken(taken_irq_vector), NPC); + standard_irq_callback(m_intc->interrupt_taken(m_taken_irq_vector), m_NPC); } void h83003_device::internal_update(uint64_t current_time) { uint64_t event_time = 0; - add_event(event_time, adc->internal_update(current_time)); - add_event(event_time, sci0->internal_update(current_time)); - add_event(event_time, sci1->internal_update(current_time)); - add_event(event_time, timer16_0->internal_update(current_time)); - add_event(event_time, timer16_1->internal_update(current_time)); - add_event(event_time, timer16_2->internal_update(current_time)); - add_event(event_time, timer16_3->internal_update(current_time)); - add_event(event_time, timer16_4->internal_update(current_time)); - add_event(event_time, watchdog->internal_update(current_time)); + add_event(event_time, m_adc->internal_update(current_time)); + add_event(event_time, m_sci0->internal_update(current_time)); + add_event(event_time, m_sci1->internal_update(current_time)); + add_event(event_time, m_timer16_0->internal_update(current_time)); + add_event(event_time, m_timer16_1->internal_update(current_time)); + add_event(event_time, m_timer16_2->internal_update(current_time)); + add_event(event_time, m_timer16_3->internal_update(current_time)); + add_event(event_time, m_timer16_4->internal_update(current_time)); + add_event(event_time, m_watchdog->internal_update(current_time)); recompute_bcount(event_time); } @@ -262,25 +262,25 @@ void h83003_device::internal_update(uint64_t current_time) void h83003_device::device_start() { h8h_device::device_start(); - dma_device = dma; + m_dma_device = m_dma; - tend_cb.resolve_all(); + m_tend_cb.resolve_all(); } void h83003_device::device_reset() { h8h_device::device_reset(); - syscr = 0x09; + m_syscr = 0x09; } uint8_t h83003_device::syscr_r() { - return syscr; + return m_syscr; } void h83003_device::syscr_w(uint8_t data) { - syscr = data; + m_syscr = data; update_irq_filter(); logerror("syscr = %02x\n", data); } @@ -288,11 +288,11 @@ void h83003_device::syscr_w(uint8_t data) uint8_t h83003_device::rtmcsr_r() { // set bit 7 -- Compare Match Flag (CMF): This status flag indicates that the RTCNT and RTCOR values have matched. - return rtmcsr | 0x80; + return m_rtmcsr | 0x80; } void h83003_device::rtmcsr_w(uint8_t data) { - rtmcsr = data; + m_rtmcsr = data; logerror("rtmcsr = %02x\n", data); } diff --git a/src/devices/cpu/h8/h83003.h b/src/devices/cpu/h8/h83003.h index 9d1fbc2fb7e..14f8963478e 100644 --- a/src/devices/cpu/h8/h83003.h +++ b/src/devices/cpu/h8/h83003.h @@ -29,13 +29,13 @@ class h83003_device : public h8h_device { public: h83003_device(const machine_config &mconfig, const char *tag, device_t *owner, uint32_t clock); - auto tend0() { return tend_cb[0].bind(); } - auto tend1() { return tend_cb[1].bind(); } - auto tend2() { return tend_cb[2].bind(); } - auto tend3() { return tend_cb[3].bind(); } + auto tend0() { return m_tend_cb[0].bind(); } + auto tend1() { return m_tend_cb[1].bind(); } + auto tend2() { return m_tend_cb[2].bind(); } + auto tend3() { return m_tend_cb[3].bind(); } - void set_mode_a20() { mode_a20 = true; } - void set_mode_a24() { mode_a20 = false; } + void set_mode_a20() { m_mode_a20 = true; } + void set_mode_a24() { m_mode_a20 = false; } uint8_t syscr_r(); void syscr_w(uint8_t data); @@ -44,33 +44,33 @@ public: void rtmcsr_w(uint8_t data); protected: - required_device intc; - required_device adc; - optional_device dma; - optional_device dma0; - optional_device dma1; - optional_device dma2; - required_device port4; - required_device port6; - required_device port7; - required_device port8; - required_device port9; - required_device porta; - required_device portb; - required_device timer16; - required_device timer16_0; - required_device timer16_1; - required_device timer16_2; - required_device timer16_3; - required_device timer16_4; - required_device sci0; - required_device sci1; - required_device watchdog; - - uint8_t syscr; - uint8_t rtmcsr; - - devcb_write_line::array<4> tend_cb; + required_device m_intc; + required_device m_adc; + optional_device m_dma; + optional_device m_dma0; + optional_device m_dma1; + optional_device m_dma2; + required_device m_port4; + required_device m_port6; + required_device m_port7; + required_device m_port8; + required_device m_port9; + required_device m_porta; + required_device m_portb; + required_device m_timer16; + required_device m_timer16_0; + required_device m_timer16_1; + required_device m_timer16_2; + required_device m_timer16_3; + required_device m_timer16_4; + required_device m_sci0; + required_device m_sci1; + required_device m_watchdog; + + uint8_t m_syscr; + uint8_t m_rtmcsr; + + devcb_write_line::array<4> m_tend_cb; virtual void update_irq_filter() override; virtual void interrupt_taken() override; diff --git a/src/devices/cpu/h8/h83006.cpp b/src/devices/cpu/h8/h83006.cpp index ebe6b16c2e9..d180c711982 100644 --- a/src/devices/cpu/h8/h83006.cpp +++ b/src/devices/cpu/h8/h83006.cpp @@ -9,29 +9,29 @@ DEFINE_DEVICE_TYPE(H83007, h83007_device, "h83007", "Hitachi H8/3007") h83006_device::h83006_device(const machine_config &mconfig, device_type type, const char *tag, device_t *owner, uint32_t clock, uint32_t start) : h8h_device(mconfig, type, tag, owner, clock, address_map_constructor(FUNC(h83006_device::map), this)), - intc(*this, "intc"), - adc(*this, "adc"), - port4(*this, "port4"), - port6(*this, "port6"), - port7(*this, "port7"), - port8(*this, "port8"), - port9(*this, "port9"), - porta(*this, "porta"), - portb(*this, "portb"), - timer8_0(*this, "timer8_0"), - timer8_1(*this, "timer8_1"), - timer8_2(*this, "timer8_2"), - timer8_3(*this, "timer8_3"), - timer16(*this, "timer16"), - timer16_0(*this, "timer16:0"), - timer16_1(*this, "timer16:1"), - timer16_2(*this, "timer16:2"), - sci0(*this, "sci0"), - sci1(*this, "sci1"), - sci2(*this, "sci2"), - watchdog(*this, "watchdog"), - syscr(0), - ram_start(start) + m_intc(*this, "intc"), + m_adc(*this, "adc"), + m_port4(*this, "port4"), + m_port6(*this, "port6"), + m_port7(*this, "port7"), + m_port8(*this, "port8"), + m_port9(*this, "port9"), + m_porta(*this, "porta"), + m_portb(*this, "portb"), + m_timer8_0(*this, "timer8_0"), + m_timer8_1(*this, "timer8_1"), + m_timer8_2(*this, "timer8_2"), + m_timer8_3(*this, "timer8_3"), + m_timer16(*this, "timer16"), + m_timer16_0(*this, "timer16:0"), + m_timer16_1(*this, "timer16:1"), + m_timer16_2(*this, "timer16:2"), + m_sci0(*this, "sci0"), + m_sci1(*this, "sci1"), + m_sci2(*this, "sci2"), + m_watchdog(*this, "watchdog"), + m_syscr(0), + m_ram_start(start) { } @@ -48,7 +48,7 @@ h83007_device::h83007_device(const machine_config &mconfig, const char *tag, dev void h83006_device::map(address_map &map) { - const offs_t base = mode_a20 ? 0 : 0xf00000; + const offs_t base = m_mode_a20 ? 0 : 0xf00000; map(base | 0xee003, base | 0xee003).w("port4", FUNC(h8_port_device::ddr_w)); map(base | 0xee005, base | 0xee005).w("port6", FUNC(h8_port_device::ddr_w)); @@ -65,7 +65,7 @@ void h83006_device::map(address_map &map) map(base | 0xee03e, base | 0xee03e).rw("port4", FUNC(h8_port_device::pcr_r), FUNC(h8_port_device::pcr_w)); - map(base | ram_start, base | 0xfff1f).ram(); + map(base | m_ram_start, base | 0xfff1f).ram(); map(base | 0xfff60, base | 0xfff60).rw("timer16", FUNC(h8_timer16_device::tstr_r), FUNC(h8_timer16_device::tstr_w)); map(base | 0xfff61, base | 0xfff61).rw("timer16", FUNC(h8_timer16_device::tsyr_r), FUNC(h8_timer16_device::tsyr_w)); @@ -165,67 +165,67 @@ void h83006_device::device_add_mconfig(machine_config &config) void h83006_device::execute_set_input(int inputnum, int state) { - intc->set_input(inputnum, state); + m_intc->set_input(inputnum, state); } int h83006_device::trapa_setup() { - if(syscr & 0x08) - CCR |= F_I; + if(m_syscr & 0x08) + m_CCR |= F_I; else - CCR |= F_I|F_UI; + m_CCR |= F_I|F_UI; return 8; } void h83006_device::irq_setup() { - if(syscr & 0x08) - CCR |= F_I; + if(m_syscr & 0x08) + m_CCR |= F_I; else - CCR |= F_I|F_UI; + m_CCR |= F_I|F_UI; } void h83006_device::update_irq_filter() { - switch(syscr & 0x08) { + switch(m_syscr & 0x08) { case 0x00: - if((CCR & (F_I|F_UI)) == (F_I|F_UI)) - intc->set_filter(2, -1); - else if(CCR & F_I) - intc->set_filter(1, -1); + if((m_CCR & (F_I|F_UI)) == (F_I|F_UI)) + m_intc->set_filter(2, -1); + else if(m_CCR & F_I) + m_intc->set_filter(1, -1); else - intc->set_filter(0, -1); + m_intc->set_filter(0, -1); break; case 0x08: - if(CCR & F_I) - intc->set_filter(2, -1); + if(m_CCR & F_I) + m_intc->set_filter(2, -1); else - intc->set_filter(0, -1); + m_intc->set_filter(0, -1); break; } } void h83006_device::interrupt_taken() { - standard_irq_callback(intc->interrupt_taken(taken_irq_vector), NPC); + standard_irq_callback(m_intc->interrupt_taken(m_taken_irq_vector), m_NPC); } void h83006_device::internal_update(uint64_t current_time) { uint64_t event_time = 0; - add_event(event_time, adc->internal_update(current_time)); - add_event(event_time, sci0->internal_update(current_time)); - add_event(event_time, sci1->internal_update(current_time)); - add_event(event_time, sci2->internal_update(current_time)); - add_event(event_time, timer8_0->internal_update(current_time)); - add_event(event_time, timer8_1->internal_update(current_time)); - add_event(event_time, timer8_2->internal_update(current_time)); - add_event(event_time, timer8_3->internal_update(current_time)); - add_event(event_time, timer16_0->internal_update(current_time)); - add_event(event_time, timer16_1->internal_update(current_time)); - add_event(event_time, timer16_2->internal_update(current_time)); - add_event(event_time, watchdog->internal_update(current_time)); + add_event(event_time, m_adc->internal_update(current_time)); + add_event(event_time, m_sci0->internal_update(current_time)); + add_event(event_time, m_sci1->internal_update(current_time)); + add_event(event_time, m_sci2->internal_update(current_time)); + add_event(event_time, m_timer8_0->internal_update(current_time)); + add_event(event_time, m_timer8_1->internal_update(current_time)); + add_event(event_time, m_timer8_2->internal_update(current_time)); + add_event(event_time, m_timer8_3->internal_update(current_time)); + add_event(event_time, m_timer16_0->internal_update(current_time)); + add_event(event_time, m_timer16_1->internal_update(current_time)); + add_event(event_time, m_timer16_2->internal_update(current_time)); + add_event(event_time, m_watchdog->internal_update(current_time)); recompute_bcount(event_time); } @@ -238,18 +238,18 @@ void h83006_device::device_start() void h83006_device::device_reset() { h8h_device::device_reset(); - syscr = 0x09; + m_syscr = 0x09; } uint8_t h83006_device::syscr_r() { - return syscr; + return m_syscr; } void h83006_device::syscr_w(uint8_t data) { - syscr = data; + m_syscr = data; update_irq_filter(); logerror("syscr = %02x\n", data); } diff --git a/src/devices/cpu/h8/h83006.h b/src/devices/cpu/h8/h83006.h index 083b91ea664..d46cf018b6f 100644 --- a/src/devices/cpu/h8/h83006.h +++ b/src/devices/cpu/h8/h83006.h @@ -29,8 +29,8 @@ class h83006_device : public h8h_device { public: h83006_device(const machine_config &mconfig, const char *tag, device_t *owner, uint32_t clock); - void set_mode_a20() { mode_a20 = true; } - void set_mode_a24() { mode_a20 = false; } + void set_mode_a20() { m_mode_a20 = true; } + void set_mode_a24() { m_mode_a20 = false; } uint8_t syscr_r(); void syscr_w(uint8_t data); @@ -38,30 +38,30 @@ public: protected: h83006_device(const machine_config &mconfig, device_type type, const char *tag, device_t *owner, uint32_t clock, uint32_t start); - required_device intc; - required_device adc; - required_device port4; - required_device port6; - required_device port7; - required_device port8; - required_device port9; - required_device porta; - required_device portb; - required_device timer8_0; - required_device timer8_1; - required_device timer8_2; - required_device timer8_3; - required_device timer16; - required_device timer16_0; - required_device timer16_1; - required_device timer16_2; - required_device sci0; - required_device sci1; - required_device sci2; - required_device watchdog; - - uint8_t syscr; - uint32_t ram_start; + required_device m_intc; + required_device m_adc; + required_device m_port4; + required_device m_port6; + required_device m_port7; + required_device m_port8; + required_device m_port9; + required_device m_porta; + required_device m_portb; + required_device m_timer8_0; + required_device m_timer8_1; + required_device m_timer8_2; + required_device m_timer8_3; + required_device m_timer16; + required_device m_timer16_0; + required_device m_timer16_1; + required_device m_timer16_2; + required_device m_sci0; + required_device m_sci1; + required_device m_sci2; + required_device m_watchdog; + + uint8_t m_syscr; + uint32_t m_ram_start; virtual void update_irq_filter() override; virtual void interrupt_taken() override; diff --git a/src/devices/cpu/h8/h83008.cpp b/src/devices/cpu/h8/h83008.cpp index 69a2090f89b..881bc96d81f 100644 --- a/src/devices/cpu/h8/h83008.cpp +++ b/src/devices/cpu/h8/h83008.cpp @@ -7,33 +7,33 @@ DEFINE_DEVICE_TYPE(H83008, h83008_device, "h83008", "Hitachi H8/3008") h83008_device::h83008_device(const machine_config &mconfig, const char *tag, device_t *owner, uint32_t clock) : h8h_device(mconfig, H83008, tag, owner, clock, address_map_constructor(FUNC(h83008_device::map), this)), - intc(*this, "intc"), - adc(*this, "adc"), - port4(*this, "port4"), - port6(*this, "port6"), - port7(*this, "port7"), - port8(*this, "port8"), - port9(*this, "port9"), - porta(*this, "porta"), - portb(*this, "portb"), - timer8_0(*this, "timer8_0"), - timer8_1(*this, "timer8_1"), - timer8_2(*this, "timer8_2"), - timer8_3(*this, "timer8_3"), - timer16(*this, "timer16"), - timer16_0(*this, "timer16:0"), - timer16_1(*this, "timer16:1"), - timer16_2(*this, "timer16:2"), - sci0(*this, "sci0"), - sci1(*this, "sci1"), - watchdog(*this, "watchdog"), - syscr(0) + m_intc(*this, "intc"), + m_adc(*this, "adc"), + m_port4(*this, "port4"), + m_port6(*this, "port6"), + m_port7(*this, "port7"), + m_port8(*this, "port8"), + m_port9(*this, "port9"), + m_porta(*this, "porta"), + m_portb(*this, "portb"), + m_timer8_0(*this, "timer8_0"), + m_timer8_1(*this, "timer8_1"), + m_timer8_2(*this, "timer8_2"), + m_timer8_3(*this, "timer8_3"), + m_timer16(*this, "timer16"), + m_timer16_0(*this, "timer16:0"), + m_timer16_1(*this, "timer16:1"), + m_timer16_2(*this, "timer16:2"), + m_sci0(*this, "sci0"), + m_sci1(*this, "sci1"), + m_watchdog(*this, "watchdog"), + m_syscr(0) { } void h83008_device::map(address_map &map) { - const offs_t base = mode_a20 ? 0 : 0xf00000; + const offs_t base = m_mode_a20 ? 0 : 0xf00000; map(base | 0xee003, base | 0xee003).w("port4", FUNC(h8_port_device::ddr_w)); map(base | 0xee005, base | 0xee005).w("port6", FUNC(h8_port_device::ddr_w)); @@ -142,66 +142,66 @@ void h83008_device::device_add_mconfig(machine_config &config) void h83008_device::execute_set_input(int inputnum, int state) { - intc->set_input(inputnum, state); + m_intc->set_input(inputnum, state); } int h83008_device::trapa_setup() { - if(syscr & 0x08) - CCR |= F_I; + if(m_syscr & 0x08) + m_CCR |= F_I; else - CCR |= F_I|F_UI; + m_CCR |= F_I|F_UI; return 8; } void h83008_device::irq_setup() { - if(syscr & 0x08) - CCR |= F_I; + if(m_syscr & 0x08) + m_CCR |= F_I; else - CCR |= F_I|F_UI; + m_CCR |= F_I|F_UI; } void h83008_device::update_irq_filter() { - switch(syscr & 0x08) { + switch(m_syscr & 0x08) { case 0x00: - if((CCR & (F_I|F_UI)) == (F_I|F_UI)) - intc->set_filter(2, -1); - else if(CCR & F_I) - intc->set_filter(1, -1); + if((m_CCR & (F_I|F_UI)) == (F_I|F_UI)) + m_intc->set_filter(2, -1); + else if(m_CCR & F_I) + m_intc->set_filter(1, -1); else - intc->set_filter(0, -1); + m_intc->set_filter(0, -1); break; case 0x08: - if(CCR & F_I) - intc->set_filter(2, -1); + if(m_CCR & F_I) + m_intc->set_filter(2, -1); else - intc->set_filter(0, -1); + m_intc->set_filter(0, -1); break; } } void h83008_device::interrupt_taken() { - standard_irq_callback(intc->interrupt_taken(taken_irq_vector), NPC); + standard_irq_callback(m_intc->interrupt_taken(m_taken_irq_vector), m_NPC); } void h83008_device::internal_update(uint64_t current_time) { uint64_t event_time = 0; - add_event(event_time, adc->internal_update(current_time)); - add_event(event_time, sci0->internal_update(current_time)); - add_event(event_time, sci1->internal_update(current_time)); - add_event(event_time, timer8_0->internal_update(current_time)); - add_event(event_time, timer8_1->internal_update(current_time)); - add_event(event_time, timer8_2->internal_update(current_time)); - add_event(event_time, timer8_3->internal_update(current_time)); - add_event(event_time, timer16_0->internal_update(current_time)); - add_event(event_time, timer16_1->internal_update(current_time)); - add_event(event_time, timer16_2->internal_update(current_time)); - add_event(event_time, watchdog->internal_update(current_time)); + add_event(event_time, m_adc->internal_update(current_time)); + add_event(event_time, m_sci0->internal_update(current_time)); + add_event(event_time, m_sci1->internal_update(current_time)); + add_event(event_time, m_timer8_0->internal_update(current_time)); + add_event(event_time, m_timer8_1->internal_update(current_time)); + add_event(event_time, m_timer8_2->internal_update(current_time)); + add_event(event_time, m_timer8_3->internal_update(current_time)); + add_event(event_time, m_timer16_0->internal_update(current_time)); + add_event(event_time, m_timer16_1->internal_update(current_time)); + add_event(event_time, m_timer16_2->internal_update(current_time)); + add_event(event_time, m_watchdog->internal_update(current_time)); recompute_bcount(event_time); } @@ -214,18 +214,18 @@ void h83008_device::device_start() void h83008_device::device_reset() { h8h_device::device_reset(); - syscr = 0x09; + m_syscr = 0x09; } uint8_t h83008_device::syscr_r() { - return syscr; + return m_syscr; } void h83008_device::syscr_w(uint8_t data) { - syscr = data; + m_syscr = data; update_irq_filter(); logerror("syscr = %02x\n", data); } diff --git a/src/devices/cpu/h8/h83008.h b/src/devices/cpu/h8/h83008.h index bb65adfcc9d..31324668d43 100644 --- a/src/devices/cpu/h8/h83008.h +++ b/src/devices/cpu/h8/h83008.h @@ -29,35 +29,35 @@ class h83008_device : public h8h_device { public: h83008_device(const machine_config &mconfig, const char *tag, device_t *owner, uint32_t clock); - void set_mode_a20() { mode_a20 = true; } - void set_mode_a24() { mode_a20 = false; } + void set_mode_a20() { m_mode_a20 = true; } + void set_mode_a24() { m_mode_a20 = false; } uint8_t syscr_r(); void syscr_w(uint8_t data); protected: - required_device intc; - required_device adc; - required_device port4; - required_device port6; - required_device port7; - required_device port8; - required_device port9; - required_device porta; - required_device portb; - required_device timer8_0; - required_device timer8_1; - required_device timer8_2; - required_device timer8_3; - required_device timer16; - required_device timer16_0; - required_device timer16_1; - required_device timer16_2; - required_device sci0; - required_device sci1; - required_device watchdog; - - uint8_t syscr; + required_device m_intc; + required_device m_adc; + required_device m_port4; + required_device m_port6; + required_device m_port7; + required_device m_port8; + required_device m_port9; + required_device m_porta; + required_device m_portb; + required_device m_timer8_0; + required_device m_timer8_1; + required_device m_timer8_2; + required_device m_timer8_3; + required_device m_timer16; + required_device m_timer16_0; + required_device m_timer16_1; + required_device m_timer16_2; + required_device m_sci0; + required_device m_sci1; + required_device m_watchdog; + + uint8_t m_syscr; virtual void update_irq_filter() override; virtual void interrupt_taken() override; diff --git a/src/devices/cpu/h8/h83032.cpp b/src/devices/cpu/h8/h83032.cpp index 41fcb08bcef..3bc3f4f7d95 100644 --- a/src/devices/cpu/h8/h83032.cpp +++ b/src/devices/cpu/h8/h83032.cpp @@ -9,31 +9,31 @@ DEFINE_DEVICE_TYPE(H83030, h83030_device, "h83030", "Hitachi H8/3030") h83032_device::h83032_device(const machine_config &mconfig, device_type type, const char *tag, device_t *owner, uint32_t clock, uint32_t start) : h8h_device(mconfig, type, tag, owner, clock, address_map_constructor(FUNC(h83032_device::map), this)), - intc(*this, "intc"), - adc(*this, "adc"), - port1(*this, "port1"), - port2(*this, "port2"), - port3(*this, "port3"), - port5(*this, "port5"), - port6(*this, "port6"), - port7(*this, "port7"), - port8(*this, "port8"), - port9(*this, "port9"), - porta(*this, "porta"), - portb(*this, "portb"), - portc(*this, "portc"), - timer16(*this, "timer16"), - timer16_0(*this, "timer16:0"), - timer16_1(*this, "timer16:1"), - timer16_2(*this, "timer16:2"), - timer16_3(*this, "timer16:3"), - timer16_4(*this, "timer16:4"), - sci0(*this, "sci0"), - watchdog(*this, "watchdog"), - ram_start(start), - syscr(0) -{ - mode_a20 = true; + m_intc(*this, "intc"), + m_adc(*this, "adc"), + m_port1(*this, "port1"), + m_port2(*this, "port2"), + m_port3(*this, "port3"), + m_port5(*this, "port5"), + m_port6(*this, "port6"), + m_port7(*this, "port7"), + m_port8(*this, "port8"), + m_port9(*this, "port9"), + m_porta(*this, "porta"), + m_portb(*this, "portb"), + m_portc(*this, "portc"), + m_timer16(*this, "timer16"), + m_timer16_0(*this, "timer16:0"), + m_timer16_1(*this, "timer16:1"), + m_timer16_2(*this, "timer16:2"), + m_timer16_3(*this, "timer16:3"), + m_timer16_4(*this, "timer16:4"), + m_sci0(*this, "sci0"), + m_watchdog(*this, "watchdog"), + m_ram_start(start), + m_syscr(0) +{ + m_mode_a20 = true; } h83032_device::h83032_device(const machine_config &mconfig, const char *tag, device_t *owner, uint32_t clock) : @@ -55,7 +55,7 @@ void h83032_device::map(address_map &map) { const offs_t base = 0xf0000; // 0 in mode 2, aka 16-bits address space, currently unemulated - map(base | ram_start, base | 0xfeff).ram(); + map(base | m_ram_start, base | 0xfeff).ram(); map(base | 0xff60, base | 0xff60).rw("timer16", FUNC(h8_timer16_device::tstr_r), FUNC(h8_timer16_device::tstr_w)); map(base | 0xff61, base | 0xff61).rw("timer16", FUNC(h8_timer16_device::tsyr_r), FUNC(h8_timer16_device::tsyr_w)); @@ -168,63 +168,63 @@ void h83032_device::device_add_mconfig(machine_config &config) void h83032_device::execute_set_input(int inputnum, int state) { - intc->set_input(inputnum, state); + m_intc->set_input(inputnum, state); } int h83032_device::trapa_setup() { - if(syscr & 0x08) - CCR |= F_I; + if(m_syscr & 0x08) + m_CCR |= F_I; else - CCR |= F_I|F_UI; + m_CCR |= F_I|F_UI; return 8; } void h83032_device::irq_setup() { - if(syscr & 0x08) - CCR |= F_I; + if(m_syscr & 0x08) + m_CCR |= F_I; else - CCR |= F_I|F_UI; + m_CCR |= F_I|F_UI; } void h83032_device::update_irq_filter() { - switch(syscr & 0x08) { + switch(m_syscr & 0x08) { case 0x00: - if((CCR & (F_I|F_UI)) == (F_I|F_UI)) - intc->set_filter(2, -1); - else if(CCR & F_I) - intc->set_filter(1, -1); + if((m_CCR & (F_I|F_UI)) == (F_I|F_UI)) + m_intc->set_filter(2, -1); + else if(m_CCR & F_I) + m_intc->set_filter(1, -1); else - intc->set_filter(0, -1); + m_intc->set_filter(0, -1); break; case 0x08: - if(CCR & F_I) - intc->set_filter(2, -1); + if(m_CCR & F_I) + m_intc->set_filter(2, -1); else - intc->set_filter(0, -1); + m_intc->set_filter(0, -1); break; } } void h83032_device::interrupt_taken() { - standard_irq_callback(intc->interrupt_taken(taken_irq_vector), NPC); + standard_irq_callback(m_intc->interrupt_taken(m_taken_irq_vector), m_NPC); } void h83032_device::internal_update(uint64_t current_time) { uint64_t event_time = 0; - add_event(event_time, adc->internal_update(current_time)); - add_event(event_time, sci0->internal_update(current_time)); - add_event(event_time, timer16_0->internal_update(current_time)); - add_event(event_time, timer16_1->internal_update(current_time)); - add_event(event_time, timer16_2->internal_update(current_time)); - add_event(event_time, timer16_3->internal_update(current_time)); - add_event(event_time, timer16_4->internal_update(current_time)); - add_event(event_time, watchdog->internal_update(current_time)); + add_event(event_time, m_adc->internal_update(current_time)); + add_event(event_time, m_sci0->internal_update(current_time)); + add_event(event_time, m_timer16_0->internal_update(current_time)); + add_event(event_time, m_timer16_1->internal_update(current_time)); + add_event(event_time, m_timer16_2->internal_update(current_time)); + add_event(event_time, m_timer16_3->internal_update(current_time)); + add_event(event_time, m_timer16_4->internal_update(current_time)); + add_event(event_time, m_watchdog->internal_update(current_time)); recompute_bcount(event_time); } @@ -237,17 +237,17 @@ void h83032_device::device_start() void h83032_device::device_reset() { h8h_device::device_reset(); - syscr = 0x0b; + m_syscr = 0x0b; } uint8_t h83032_device::syscr_r() { - return syscr; + return m_syscr; } void h83032_device::syscr_w(uint8_t data) { - syscr = data; + m_syscr = data; update_irq_filter(); logerror("syscr = %02x\n", data); } diff --git a/src/devices/cpu/h8/h83032.h b/src/devices/cpu/h8/h83032.h index fd2d99593da..bb2a6de2769 100644 --- a/src/devices/cpu/h8/h83032.h +++ b/src/devices/cpu/h8/h83032.h @@ -37,30 +37,30 @@ public: protected: h83032_device(const machine_config &mconfig, device_type type, const char *tag, device_t *owner, uint32_t clock, uint32_t start); - required_device intc; - required_device adc; - required_device port1; - required_device port2; - required_device port3; - required_device port5; - required_device port6; - required_device port7; - required_device port8; - required_device port9; - required_device porta; - required_device portb; - required_device portc; - required_device timer16; - required_device timer16_0; - required_device timer16_1; - required_device timer16_2; - required_device timer16_3; - required_device timer16_4; - required_device sci0; - required_device watchdog; - - uint32_t ram_start; - uint8_t syscr; + required_device m_intc; + required_device m_adc; + required_device m_port1; + required_device m_port2; + required_device m_port3; + required_device m_port5; + required_device m_port6; + required_device m_port7; + required_device m_port8; + required_device m_port9; + required_device m_porta; + required_device m_portb; + required_device m_portc; + required_device m_timer16; + required_device m_timer16_0; + required_device m_timer16_1; + required_device m_timer16_2; + required_device m_timer16_3; + required_device m_timer16_4; + required_device m_sci0; + required_device m_watchdog; + + uint32_t m_ram_start; + uint8_t m_syscr; virtual void update_irq_filter() override; virtual void interrupt_taken() override; diff --git a/src/devices/cpu/h8/h83042.cpp b/src/devices/cpu/h8/h83042.cpp index 71892c2178f..bb2052c1b05 100644 --- a/src/devices/cpu/h8/h83042.cpp +++ b/src/devices/cpu/h8/h83042.cpp @@ -9,31 +9,31 @@ DEFINE_DEVICE_TYPE(H83042, h83042_device, "h83042", "Hitachi H8/3042") h83042_device::h83042_device(const machine_config &mconfig, device_type type, const char *tag, device_t *owner, uint32_t clock) : h8h_device(mconfig, type, tag, owner, clock, address_map_constructor(FUNC(h83042_device::map), this)), - intc(*this, "intc"), - adc(*this, "adc"), - port1(*this, "port1"), - port2(*this, "port2"), - port3(*this, "port3"), - port4(*this, "port4"), - port5(*this, "port5"), - port6(*this, "port6"), - port7(*this, "port7"), - port8(*this, "port8"), - port9(*this, "port9"), - porta(*this, "porta"), - portb(*this, "portb"), - timer16(*this, "timer16"), - timer16_0(*this, "timer16:0"), - timer16_1(*this, "timer16:1"), - timer16_2(*this, "timer16:2"), - timer16_3(*this, "timer16:3"), - timer16_4(*this, "timer16:4"), - sci0(*this, "sci0"), - sci1(*this, "sci1"), - watchdog(*this, "watchdog"), - syscr(0) + m_intc(*this, "intc"), + m_adc(*this, "adc"), + m_port1(*this, "port1"), + m_port2(*this, "port2"), + m_port3(*this, "port3"), + m_port4(*this, "port4"), + m_port5(*this, "port5"), + m_port6(*this, "port6"), + m_port7(*this, "port7"), + m_port8(*this, "port8"), + m_port9(*this, "port9"), + m_porta(*this, "porta"), + m_portb(*this, "portb"), + m_timer16(*this, "timer16"), + m_timer16_0(*this, "timer16:0"), + m_timer16_1(*this, "timer16:1"), + m_timer16_2(*this, "timer16:2"), + m_timer16_3(*this, "timer16:3"), + m_timer16_4(*this, "timer16:4"), + m_sci0(*this, "sci0"), + m_sci1(*this, "sci1"), + m_watchdog(*this, "watchdog"), + m_syscr(0) { - mode_a20 = true; + m_mode_a20 = true; } h83040_device::h83040_device(const machine_config &mconfig, const char *tag, device_t *owner, uint32_t clock) : @@ -177,64 +177,64 @@ void h83042_device::device_add_mconfig(machine_config &config) void h83042_device::execute_set_input(int inputnum, int state) { - intc->set_input(inputnum, state); + m_intc->set_input(inputnum, state); } int h83042_device::trapa_setup() { - if(syscr & 0x08) - CCR |= F_I; + if(m_syscr & 0x08) + m_CCR |= F_I; else - CCR |= F_I|F_UI; + m_CCR |= F_I|F_UI; return 8; } void h83042_device::irq_setup() { - if(syscr & 0x08) - CCR |= F_I; + if(m_syscr & 0x08) + m_CCR |= F_I; else - CCR |= F_I|F_UI; + m_CCR |= F_I|F_UI; } void h83042_device::update_irq_filter() { - switch(syscr & 0x08) { + switch(m_syscr & 0x08) { case 0x00: - if((CCR & (F_I|F_UI)) == (F_I|F_UI)) - intc->set_filter(2, -1); - else if(CCR & F_I) - intc->set_filter(1, -1); + if((m_CCR & (F_I|F_UI)) == (F_I|F_UI)) + m_intc->set_filter(2, -1); + else if(m_CCR & F_I) + m_intc->set_filter(1, -1); else - intc->set_filter(0, -1); + m_intc->set_filter(0, -1); break; case 0x08: - if(CCR & F_I) - intc->set_filter(2, -1); + if(m_CCR & F_I) + m_intc->set_filter(2, -1); else - intc->set_filter(0, -1); + m_intc->set_filter(0, -1); break; } } void h83042_device::interrupt_taken() { - standard_irq_callback(intc->interrupt_taken(taken_irq_vector), NPC); + standard_irq_callback(m_intc->interrupt_taken(m_taken_irq_vector), m_NPC); } void h83042_device::internal_update(uint64_t current_time) { uint64_t event_time = 0; - add_event(event_time, adc->internal_update(current_time)); - add_event(event_time, sci0->internal_update(current_time)); - add_event(event_time, sci1->internal_update(current_time)); - add_event(event_time, timer16_0->internal_update(current_time)); - add_event(event_time, timer16_1->internal_update(current_time)); - add_event(event_time, timer16_2->internal_update(current_time)); - add_event(event_time, timer16_3->internal_update(current_time)); - add_event(event_time, timer16_4->internal_update(current_time)); - add_event(event_time, watchdog->internal_update(current_time)); + add_event(event_time, m_adc->internal_update(current_time)); + add_event(event_time, m_sci0->internal_update(current_time)); + add_event(event_time, m_sci1->internal_update(current_time)); + add_event(event_time, m_timer16_0->internal_update(current_time)); + add_event(event_time, m_timer16_1->internal_update(current_time)); + add_event(event_time, m_timer16_2->internal_update(current_time)); + add_event(event_time, m_timer16_3->internal_update(current_time)); + add_event(event_time, m_timer16_4->internal_update(current_time)); + add_event(event_time, m_watchdog->internal_update(current_time)); recompute_bcount(event_time); } @@ -247,17 +247,17 @@ void h83042_device::device_start() void h83042_device::device_reset() { h8h_device::device_reset(); - syscr = 0x0b; + m_syscr = 0x0b; } uint8_t h83042_device::syscr_r() { - return syscr; + return m_syscr; } void h83042_device::syscr_w(uint8_t data) { - syscr = data; + m_syscr = data; update_irq_filter(); logerror("syscr = %02x\n", data); } diff --git a/src/devices/cpu/h8/h83042.h b/src/devices/cpu/h8/h83042.h index 8caa5a4e690..f49b2bfb793 100644 --- a/src/devices/cpu/h8/h83042.h +++ b/src/devices/cpu/h8/h83042.h @@ -40,30 +40,30 @@ public: protected: h83042_device(const machine_config &mconfig, device_type type, const char *tag, device_t *owner, uint32_t clock); - required_device intc; - required_device adc; - required_device port1; - required_device port2; - required_device port3; - required_device port4; - required_device port5; - required_device port6; - required_device port7; - required_device port8; - required_device port9; - required_device porta; - required_device portb; - required_device timer16; - required_device timer16_0; - required_device timer16_1; - required_device timer16_2; - required_device timer16_3; - required_device timer16_4; - required_device sci0; - required_device sci1; - required_device watchdog; - - uint8_t syscr; + required_device m_intc; + required_device m_adc; + required_device m_port1; + required_device m_port2; + required_device m_port3; + required_device m_port4; + required_device m_port5; + required_device m_port6; + required_device m_port7; + required_device m_port8; + required_device m_port9; + required_device m_porta; + required_device m_portb; + required_device m_timer16; + required_device m_timer16_0; + required_device m_timer16_1; + required_device m_timer16_2; + required_device m_timer16_3; + required_device m_timer16_4; + required_device m_sci0; + required_device m_sci1; + required_device m_watchdog; + + uint8_t m_syscr; virtual void update_irq_filter() override; virtual void interrupt_taken() override; diff --git a/src/devices/cpu/h8/h83048.cpp b/src/devices/cpu/h8/h83048.cpp index 464acb46e39..fc754b29343 100644 --- a/src/devices/cpu/h8/h83048.cpp +++ b/src/devices/cpu/h8/h83048.cpp @@ -10,30 +10,30 @@ DEFINE_DEVICE_TYPE(H83048, h83048_device, "h83048", "Hitachi H8/3048") h83048_device::h83048_device(const machine_config &mconfig, device_type type, const char *tag, device_t *owner, uint32_t clock, uint32_t start) : h8h_device(mconfig, type, tag, owner, clock, address_map_constructor(FUNC(h83048_device::map), this)), - intc(*this, "intc"), - adc(*this, "adc"), - port1(*this, "port1"), - port2(*this, "port2"), - port3(*this, "port3"), - port4(*this, "port4"), - port5(*this, "port5"), - port6(*this, "port6"), - port7(*this, "port7"), - port8(*this, "port8"), - port9(*this, "port9"), - porta(*this, "porta"), - portb(*this, "portb"), - timer16(*this, "timer16"), - timer16_0(*this, "timer16:0"), - timer16_1(*this, "timer16:1"), - timer16_2(*this, "timer16:2"), - timer16_3(*this, "timer16:3"), - timer16_4(*this, "timer16:4"), - sci0(*this, "sci0"), - sci1(*this, "sci1"), - watchdog(*this, "watchdog"), - ram_start(start), - syscr(0) + m_intc(*this, "intc"), + m_adc(*this, "adc"), + m_port1(*this, "port1"), + m_port2(*this, "port2"), + m_port3(*this, "port3"), + m_port4(*this, "port4"), + m_port5(*this, "port5"), + m_port6(*this, "port6"), + m_port7(*this, "port7"), + m_port8(*this, "port8"), + m_port9(*this, "port9"), + m_porta(*this, "porta"), + m_portb(*this, "portb"), + m_timer16(*this, "timer16"), + m_timer16_0(*this, "timer16:0"), + m_timer16_1(*this, "timer16:1"), + m_timer16_2(*this, "timer16:2"), + m_timer16_3(*this, "timer16:3"), + m_timer16_4(*this, "timer16:4"), + m_sci0(*this, "sci0"), + m_sci1(*this, "sci1"), + m_watchdog(*this, "watchdog"), + m_ram_start(start), + m_syscr(0) { } @@ -59,9 +59,9 @@ h83047_device::h83047_device(const machine_config &mconfig, const char *tag, dev void h83048_device::map(address_map &map) { - const offs_t base = mode_a20 ? 0xf0000 : 0xff0000; + const offs_t base = m_mode_a20 ? 0xf0000 : 0xff0000; - map(base | ram_start, base | 0xff0f).ram(); + map(base | m_ram_start, base | 0xff0f).ram(); map(base | 0xff60, base | 0xff60).rw("timer16", FUNC(h8_timer16_device::tstr_r), FUNC(h8_timer16_device::tstr_w)); map(base | 0xff61, base | 0xff61).rw("timer16", FUNC(h8_timer16_device::tsyr_r), FUNC(h8_timer16_device::tsyr_w)); @@ -182,64 +182,64 @@ void h83048_device::device_add_mconfig(machine_config &config) void h83048_device::execute_set_input(int inputnum, int state) { - intc->set_input(inputnum, state); + m_intc->set_input(inputnum, state); } int h83048_device::trapa_setup() { - if(syscr & 0x08) - CCR |= F_I; + if(m_syscr & 0x08) + m_CCR |= F_I; else - CCR |= F_I|F_UI; + m_CCR |= F_I|F_UI; return 8; } void h83048_device::irq_setup() { - if(syscr & 0x08) - CCR |= F_I; + if(m_syscr & 0x08) + m_CCR |= F_I; else - CCR |= F_I|F_UI; + m_CCR |= F_I|F_UI; } void h83048_device::update_irq_filter() { - switch(syscr & 0x08) { + switch(m_syscr & 0x08) { case 0x00: - if((CCR & (F_I|F_UI)) == (F_I|F_UI)) - intc->set_filter(2, -1); - else if(CCR & F_I) - intc->set_filter(1, -1); + if((m_CCR & (F_I|F_UI)) == (F_I|F_UI)) + m_intc->set_filter(2, -1); + else if(m_CCR & F_I) + m_intc->set_filter(1, -1); else - intc->set_filter(0, -1); + m_intc->set_filter(0, -1); break; case 0x08: - if(CCR & F_I) - intc->set_filter(2, -1); + if(m_CCR & F_I) + m_intc->set_filter(2, -1); else - intc->set_filter(0, -1); + m_intc->set_filter(0, -1); break; } } void h83048_device::interrupt_taken() { - standard_irq_callback(intc->interrupt_taken(taken_irq_vector), NPC); + standard_irq_callback(m_intc->interrupt_taken(m_taken_irq_vector), m_NPC); } void h83048_device::internal_update(uint64_t current_time) { uint64_t event_time = 0; - add_event(event_time, adc->internal_update(current_time)); - add_event(event_time, sci0->internal_update(current_time)); - add_event(event_time, sci1->internal_update(current_time)); - add_event(event_time, timer16_0->internal_update(current_time)); - add_event(event_time, timer16_1->internal_update(current_time)); - add_event(event_time, timer16_2->internal_update(current_time)); - add_event(event_time, timer16_3->internal_update(current_time)); - add_event(event_time, timer16_4->internal_update(current_time)); - add_event(event_time, watchdog->internal_update(current_time)); + add_event(event_time, m_adc->internal_update(current_time)); + add_event(event_time, m_sci0->internal_update(current_time)); + add_event(event_time, m_sci1->internal_update(current_time)); + add_event(event_time, m_timer16_0->internal_update(current_time)); + add_event(event_time, m_timer16_1->internal_update(current_time)); + add_event(event_time, m_timer16_2->internal_update(current_time)); + add_event(event_time, m_timer16_3->internal_update(current_time)); + add_event(event_time, m_timer16_4->internal_update(current_time)); + add_event(event_time, m_watchdog->internal_update(current_time)); recompute_bcount(event_time); } @@ -252,17 +252,17 @@ void h83048_device::device_start() void h83048_device::device_reset() { h8h_device::device_reset(); - syscr = 0x0b; + m_syscr = 0x0b; } uint8_t h83048_device::syscr_r() { - return syscr; + return m_syscr; } void h83048_device::syscr_w(uint8_t data) { - syscr = data; + m_syscr = data; update_irq_filter(); logerror("syscr = %02x\n", data); } diff --git a/src/devices/cpu/h8/h83048.h b/src/devices/cpu/h8/h83048.h index d5afb5e67c8..7ad31651c4d 100644 --- a/src/devices/cpu/h8/h83048.h +++ b/src/devices/cpu/h8/h83048.h @@ -34,8 +34,8 @@ class h83048_device : public h8h_device { public: h83048_device(const machine_config &mconfig, const char *tag, device_t *owner, uint32_t clock); - void set_mode_a20() { mode_a20 = true; } - void set_mode_a24() { mode_a20 = false; } + void set_mode_a20() { m_mode_a20 = true; } + void set_mode_a24() { m_mode_a20 = false; } uint8_t syscr_r(); void syscr_w(uint8_t data); @@ -43,31 +43,31 @@ public: protected: h83048_device(const machine_config &mconfig, device_type type, const char *tag, device_t *owner, uint32_t clock, uint32_t start); - required_device intc; - required_device adc; - required_device port1; - required_device port2; - required_device port3; - required_device port4; - required_device port5; - required_device port6; - required_device port7; - required_device port8; - required_device port9; - required_device porta; - required_device portb; - required_device timer16; - required_device timer16_0; - required_device timer16_1; - required_device timer16_2; - required_device timer16_3; - required_device timer16_4; - required_device sci0; - required_device sci1; - required_device watchdog; - - uint32_t ram_start; - uint8_t syscr; + required_device m_intc; + required_device m_adc; + required_device m_port1; + required_device m_port2; + required_device m_port3; + required_device m_port4; + required_device m_port5; + required_device m_port6; + required_device m_port7; + required_device m_port8; + required_device m_port9; + required_device m_porta; + required_device m_portb; + required_device m_timer16; + required_device m_timer16_0; + required_device m_timer16_1; + required_device m_timer16_2; + required_device m_timer16_3; + required_device m_timer16_4; + required_device m_sci0; + required_device m_sci1; + required_device m_watchdog; + + uint32_t m_ram_start; + uint8_t m_syscr; virtual void update_irq_filter() override; virtual void interrupt_taken() override; diff --git a/src/devices/cpu/h8/h83337.cpp b/src/devices/cpu/h8/h83337.cpp index dd13112e592..e5bcbb36cea 100644 --- a/src/devices/cpu/h8/h83337.cpp +++ b/src/devices/cpu/h8/h83337.cpp @@ -10,26 +10,26 @@ DEFINE_DEVICE_TYPE(H83337, h83337_device, "h83337", "Hitachi H8/3337") h83337_device::h83337_device(const machine_config &mconfig, device_type type, const char *tag, device_t *owner, uint32_t clock, uint32_t start) : h8_device(mconfig, type, tag, owner, clock, address_map_constructor(FUNC(h83337_device::map), this)), - intc(*this, "intc"), - adc(*this, "adc"), - port1(*this, "port1"), - port2(*this, "port2"), - port3(*this, "port3"), - port4(*this, "port4"), - port5(*this, "port5"), - port6(*this, "port6"), - port7(*this, "port7"), - port8(*this, "port8"), - port9(*this, "port9"), - timer8_0(*this, "timer8_0"), - timer8_1(*this, "timer8_1"), - timer16(*this, "timer16"), - timer16_0(*this, "timer16:0"), - sci0(*this, "sci0"), - sci1(*this, "sci1"), - watchdog(*this, "watchdog"), - syscr(0), - ram_start(start) + m_intc(*this, "intc"), + m_adc(*this, "adc"), + m_port1(*this, "port1"), + m_port2(*this, "port2"), + m_port3(*this, "port3"), + m_port4(*this, "port4"), + m_port5(*this, "port5"), + m_port6(*this, "port6"), + m_port7(*this, "port7"), + m_port8(*this, "port8"), + m_port9(*this, "port9"), + m_timer8_0(*this, "timer8_0"), + m_timer8_1(*this, "timer8_1"), + m_timer16(*this, "timer16"), + m_timer16_0(*this, "timer16:0"), + m_sci0(*this, "sci0"), + m_sci1(*this, "sci1"), + m_watchdog(*this, "watchdog"), + m_syscr(0), + m_ram_start(start) { } @@ -50,7 +50,7 @@ h83336_device::h83336_device(const machine_config &mconfig, const char *tag, dev void h83337_device::map(address_map &map) { - map(ram_start, 0xff7f).ram(); + map(m_ram_start, 0xff7f).ram(); map(0xff88, 0xff88).rw("sci1", FUNC(h8_sci_device::smr_r), FUNC(h8_sci_device::smr_w)); map(0xff89, 0xff89).rw("sci1", FUNC(h8_sci_device::brr_r), FUNC(h8_sci_device::brr_w)); @@ -139,38 +139,38 @@ void h83337_device::device_add_mconfig(machine_config &config) void h83337_device::execute_set_input(int inputnum, int state) { - intc->set_input(inputnum, state); + m_intc->set_input(inputnum, state); } void h83337_device::irq_setup() { - CCR |= F_I; + m_CCR |= F_I; } void h83337_device::update_irq_filter() { - if(CCR & F_I) - intc->set_filter(2, -1); + if(m_CCR & F_I) + m_intc->set_filter(2, -1); else - intc->set_filter(0, -1); + m_intc->set_filter(0, -1); } void h83337_device::interrupt_taken() { - standard_irq_callback(intc->interrupt_taken(taken_irq_vector), NPC); + standard_irq_callback(m_intc->interrupt_taken(m_taken_irq_vector), m_NPC); } void h83337_device::internal_update(uint64_t current_time) { uint64_t event_time = 0; - add_event(event_time, adc->internal_update(current_time)); - add_event(event_time, sci0->internal_update(current_time)); - add_event(event_time, sci1->internal_update(current_time)); - add_event(event_time, timer8_0->internal_update(current_time)); - add_event(event_time, timer8_1->internal_update(current_time)); - add_event(event_time, timer16_0->internal_update(current_time)); - add_event(event_time, watchdog->internal_update(current_time)); + add_event(event_time, m_adc->internal_update(current_time)); + add_event(event_time, m_sci0->internal_update(current_time)); + add_event(event_time, m_sci1->internal_update(current_time)); + add_event(event_time, m_timer8_0->internal_update(current_time)); + add_event(event_time, m_timer8_1->internal_update(current_time)); + add_event(event_time, m_timer16_0->internal_update(current_time)); + add_event(event_time, m_watchdog->internal_update(current_time)); recompute_bcount(event_time); } @@ -183,17 +183,17 @@ void h83337_device::device_start() void h83337_device::device_reset() { h8_device::device_reset(); - syscr = 0x09; + m_syscr = 0x09; } uint8_t h83337_device::syscr_r() { - return syscr; + return m_syscr; } void h83337_device::syscr_w(uint8_t data) { - syscr = data; + m_syscr = data; logerror("syscr = %02x\n", data); } @@ -215,8 +215,8 @@ uint8_t h83337_device::stcr_r() void h83337_device::stcr_w(uint8_t data) { logerror("stcr = %02x\n", data); - timer8_0->set_extra_clock_bit(data & 0x01); - timer8_1->set_extra_clock_bit(data & 0x02); + m_timer8_0->set_extra_clock_bit(data & 0x01); + m_timer8_1->set_extra_clock_bit(data & 0x02); } uint8_t h83337_device::mdcr_r() diff --git a/src/devices/cpu/h8/h83337.h b/src/devices/cpu/h8/h83337.h index cc0d9735a34..2ab8fd0e778 100644 --- a/src/devices/cpu/h8/h83337.h +++ b/src/devices/cpu/h8/h83337.h @@ -48,27 +48,27 @@ public: protected: h83337_device(const machine_config &mconfig, device_type type, const char *tag, device_t *owner, uint32_t clock, uint32_t start); - required_device intc; - required_device adc; - required_device port1; - required_device port2; - required_device port3; - required_device port4; - required_device port5; - required_device port6; - required_device port7; - required_device port8; - required_device port9; - required_device timer8_0; - required_device timer8_1; - required_device timer16; - required_device timer16_0; - required_device sci0; - required_device sci1; - required_device watchdog; - - uint8_t syscr; - uint32_t ram_start; + required_device m_intc; + required_device m_adc; + required_device m_port1; + required_device m_port2; + required_device m_port3; + required_device m_port4; + required_device m_port5; + required_device m_port6; + required_device m_port7; + required_device m_port8; + required_device m_port9; + required_device m_timer8_0; + required_device m_timer8_1; + required_device m_timer16; + required_device m_timer16_0; + required_device m_sci0; + required_device m_sci1; + required_device m_watchdog; + + uint8_t m_syscr; + uint32_t m_ram_start; virtual void update_irq_filter() override; virtual void interrupt_taken() override; diff --git a/src/devices/cpu/h8/h8_adc.cpp b/src/devices/cpu/h8/h8_adc.cpp index 3235ac8c6c8..d0151ca0268 100644 --- a/src/devices/cpu/h8/h8_adc.cpp +++ b/src/devices/cpu/h8/h8_adc.cpp @@ -17,54 +17,54 @@ DEFINE_DEVICE_TYPE(H8_ADC_2655, h8_adc_2655_device, "h8_adc_2655", "H8/2655 ADC" h8_adc_device::h8_adc_device(const machine_config &mconfig, device_type type, const char *tag, device_t *owner, uint32_t clock) : device_t(mconfig, type, tag, owner, clock), - cpu(*this, DEVICE_SELF_OWNER), - intc(nullptr), io(nullptr), intc_tag(nullptr), intc_vector(0), adcsr(0), adcr(0), register_mask(0), trigger(0), start_mode(0), start_channel(0), - end_channel(0), start_count(0), mode(0), channel(0), count(0), analog_powered(false), adtrg(false), next_event(0) + m_cpu(*this, DEVICE_SELF_OWNER), + m_intc(nullptr), m_io(nullptr), m_intc_tag(nullptr), m_intc_vector(0), m_adcsr(0), m_adcr(0), m_register_mask(0), m_trigger(0), m_start_mode(0), m_start_channel(0), + m_end_channel(0), m_start_count(0), m_mode(0), m_channel(0), m_count(0), m_analog_powered(false), m_adtrg(false), m_next_event(0) { - suspend_on_interrupt = false; - analog_power_control = false; + m_suspend_on_interrupt = false; + m_analog_power_control = false; } void h8_adc_device::set_info(const char *_intc_tag, int _intc_vector) { - intc_tag = _intc_tag; - intc_vector = _intc_vector; + m_intc_tag = _intc_tag; + m_intc_vector = _intc_vector; } uint8_t h8_adc_device::addr8_r(offs_t offset) { - if(V>=1) logerror("addr8_r %d %03x\n", offset, addr[offset >> 1]); - return offset & 1 ? addr[offset >> 1] << 6 : addr[offset >> 1] >> 2; + if(V>=1) logerror("addr8_r %d %03x\n", offset, m_addr[offset >> 1]); + return offset & 1 ? m_addr[offset >> 1] << 6 : m_addr[offset >> 1] >> 2; } uint16_t h8_adc_device::addr16_r(offs_t offset) { - if(V>=1) logerror("addr16_r %d %03x\n", offset, addr[offset]); - return addr[offset]; + if(V>=1) logerror("addr16_r %d %03x\n", offset, m_addr[offset]); + return m_addr[offset]; } uint8_t h8_adc_device::adcsr_r() { - if(V>=1) logerror("adcsr_r %02x\n", adcsr); - return adcsr; + if(V>=1) logerror("adcsr_r %02x\n", m_adcsr); + return m_adcsr; } uint8_t h8_adc_device::adcr_r() { - if(V>=1) logerror("adcr_r %02x\n", adcr); - return adcr; + if(V>=1) logerror("adcr_r %02x\n", m_adcr); + return m_adcr; } void h8_adc_device::adcsr_w(uint8_t data) { if(V>=1) logerror("adcsr_w %02x\n", data); - uint8_t prev = adcsr; - adcsr = (data & 0x7f) | (adcsr & data & F_ADF); + uint8_t prev = m_adcsr; + m_adcsr = (data & 0x7f) | (m_adcsr & data & F_ADF); mode_update(); - if((prev & F_ADF) && !(adcsr & F_ADF)) { - if(mode & HALTED) { - mode &= ~HALTED; - if(!(adcsr & F_ADST)) { + if((prev & F_ADF) && !(m_adcsr & F_ADF)) { + if(m_mode & HALTED) { + m_mode &= ~HALTED; + if(!(m_adcsr & F_ADST)) { sampling(); conversion_wait(false, false); } else @@ -72,23 +72,23 @@ void h8_adc_device::adcsr_w(uint8_t data) } } - if(!(prev & F_ADST) && (adcsr & F_ADST)) + if(!(prev & F_ADST) && (m_adcsr & F_ADST)) start_conversion(); } void h8_adc_device::adcr_w(uint8_t data) { if(V>=1) logerror("adcr_w %02x\n", data); - adcr = data; + m_adcr = data; mode_update(); } WRITE_LINE_MEMBER(h8_adc_device::adtrg_w) { - if(state != adtrg) { - adtrg = state; - if(!adtrg && (trigger & T_EXT) && !(adcsr & F_ADST)) { - adcsr |= F_ADST; + if(state != m_adtrg) { + m_adtrg = state; + if(!m_adtrg && (m_trigger & T_EXT) && !(m_adcsr & F_ADST)) { + m_adcsr |= F_ADST; start_conversion(); } } @@ -100,159 +100,159 @@ void h8_adc_device::set_suspend(bool suspend) void h8_adc_device::device_start() { - io = &cpu->space(AS_IO); - intc = siblingdevice(intc_tag); - save_item(NAME(addr)); - save_item(NAME(buf)); - save_item(NAME(adcsr)); - save_item(NAME(adcr)); - save_item(NAME(trigger)); - save_item(NAME(start_mode)); - save_item(NAME(start_channel)); - save_item(NAME(end_channel)); - save_item(NAME(start_count)); - save_item(NAME(suspend_on_interrupt)); - save_item(NAME(analog_power_control)); - save_item(NAME(mode)); - save_item(NAME(channel)); - save_item(NAME(count)); - save_item(NAME(analog_powered)); - save_item(NAME(next_event)); - save_item(NAME(adtrg)); + m_io = &m_cpu->space(AS_IO); + m_intc = siblingdevice(m_intc_tag); + save_item(NAME(m_addr)); + save_item(NAME(m_buf)); + save_item(NAME(m_adcsr)); + save_item(NAME(m_adcr)); + save_item(NAME(m_trigger)); + save_item(NAME(m_start_mode)); + save_item(NAME(m_start_channel)); + save_item(NAME(m_end_channel)); + save_item(NAME(m_start_count)); + save_item(NAME(m_suspend_on_interrupt)); + save_item(NAME(m_analog_power_control)); + save_item(NAME(m_mode)); + save_item(NAME(m_channel)); + save_item(NAME(m_count)); + save_item(NAME(m_analog_powered)); + save_item(NAME(m_next_event)); + save_item(NAME(m_adtrg)); } void h8_adc_device::device_reset() { - memset(addr, 0, sizeof(addr)); - memset(buf, 0, sizeof(buf)); - adcsr = adcr = 0; - trigger = T_SOFT; - start_mode = IDLE; - start_channel = end_channel = 0; - start_count = 1; - mode = IDLE; - channel = 0; - count = 0; - next_event = 0; + memset(m_addr, 0, sizeof(m_addr)); + memset(m_buf, 0, sizeof(m_buf)); + m_adcsr = m_adcr = 0; + m_trigger = T_SOFT; + m_start_mode = IDLE; + m_start_channel = m_end_channel = 0; + m_start_count = 1; + m_mode = IDLE; + m_channel = 0; + m_count = 0; + m_next_event = 0; mode_update(); - analog_powered = !analog_power_control; - adtrg = true; + m_analog_powered = !m_analog_power_control; + m_adtrg = true; } void h8_adc_device::done() { - mode = IDLE; - adcsr &= ~F_ADST; - if(analog_power_control) - analog_powered = false; + m_mode = IDLE; + m_adcsr &= ~F_ADST; + if(m_analog_power_control) + m_analog_powered = false; } uint64_t h8_adc_device::internal_update(uint64_t current_time) { - if(next_event && next_event <= current_time) { - next_event = 0; + if(m_next_event && m_next_event <= current_time) { + m_next_event = 0; timeout(current_time); } - return next_event; + return m_next_event; } void h8_adc_device::conversion_wait(bool first, bool poweron, uint64_t current_time) { if(current_time) - next_event = current_time + conversion_time(first, poweron); + m_next_event = current_time + conversion_time(first, poweron); else { - next_event = cpu->total_cycles() + conversion_time(first, poweron); - cpu->internal_update(); + m_next_event = m_cpu->total_cycles() + conversion_time(first, poweron); + m_cpu->internal_update(); } } void h8_adc_device::buffer_value(int port, int buffer) { - buf[buffer] = io->read_word(h8_device::ADC_0 + port); - if(V>=1) logerror("adc buffer %d -> %d:%03x\n", port, buffer, buf[buffer]); + m_buf[buffer] = m_io->read_word(h8_device::ADC_0 + port); + if(V>=1) logerror("adc buffer %d -> %d:%03x\n", port, buffer, m_buf[buffer]); } void h8_adc_device::commit_value(int reg, int buffer) { - reg &= register_mask; - if(V>=1) logerror("adc commit %d -> %d:%03x\n", buffer, reg, buf[buffer]); - addr[reg] = buf[buffer]; + reg &= m_register_mask; + if(V>=1) logerror("adc commit %d -> %d:%03x\n", buffer, reg, m_buf[buffer]); + m_addr[reg] = m_buf[buffer]; } void h8_adc_device::sampling() { - if(mode & COUNTED) - channel = get_channel_index(start_count - count); - if(mode & DUAL) { - buffer_value(channel, 0); - buffer_value(channel+1, 1); + if(m_mode & COUNTED) + m_channel = get_channel_index(m_start_count - m_count); + if(m_mode & DUAL) { + buffer_value(m_channel, 0); + buffer_value(m_channel+1, 1); } else - buffer_value(channel); + buffer_value(m_channel); } void h8_adc_device::start_conversion() { - mode = start_mode; - channel = start_channel; - count = start_count; + m_mode = m_start_mode; + m_channel = m_start_channel; + m_count = m_start_count; sampling(); - conversion_wait(true, !analog_powered); - analog_powered = true; + conversion_wait(true, !m_analog_powered); + m_analog_powered = true; } void h8_adc_device::timeout(uint64_t current_time) { - if(mode & BUFFER) { - do_buffering((mode & DUAL) && (channel & 1)); - if((mode & DUAL) && !(channel & 1)) { - channel++; + if(m_mode & BUFFER) { + do_buffering((m_mode & DUAL) && (m_channel & 1)); + if((m_mode & DUAL) && !(m_channel & 1)) { + m_channel++; conversion_wait(false, false, current_time); return; } } else { - if(mode & DUAL) { - if(channel & 1) - commit_value(channel, 1); + if(m_mode & DUAL) { + if(m_channel & 1) + commit_value(m_channel, 1); else { - commit_value(channel, 0); - channel++; + commit_value(m_channel, 0); + m_channel++; conversion_wait(false, false, current_time); return; } } else - commit_value(channel); + commit_value(m_channel); } - if(mode & ROTATE) { - if(channel != end_channel) { - channel++; + if(m_mode & ROTATE) { + if(m_channel != m_end_channel) { + m_channel++; sampling(); conversion_wait(false, false, current_time); return; } - channel = start_channel; + m_channel = m_start_channel; } - if(mode & COUNTED) { - count--; - if(count) { + if(m_mode & COUNTED) { + m_count--; + if(m_count) { sampling(); conversion_wait(false, false, current_time); return; } } - adcsr |= F_ADF; - if(adcsr & F_ADIE) - intc->internal_interrupt(intc_vector); + m_adcsr |= F_ADF; + if(m_adcsr & F_ADIE) + m_intc->internal_interrupt(m_intc_vector); - if(mode & REPEAT) { - if(suspend_on_interrupt && (adcsr & F_ADIE)) { - mode |= HALTED; + if(m_mode & REPEAT) { + if(m_suspend_on_interrupt && (m_adcsr & F_ADIE)) { + m_mode |= HALTED; return; } - channel = start_channel; - count = start_count; + m_channel = m_start_channel; + m_count = m_start_count; sampling(); conversion_wait(false, false, current_time); return; @@ -275,30 +275,30 @@ int h8_adc_device::get_channel_index(int count) h8_adc_3337_device::h8_adc_3337_device(const machine_config &mconfig, const char *tag, device_t *owner, uint32_t clock) : h8_adc_device(mconfig, H8_ADC_3337, tag, owner, clock) { - register_mask = 3; + m_register_mask = 3; } int h8_adc_3337_device::conversion_time(bool first, bool poweron) { int tm; if(first) - tm = adcsr & 0x08 ? 134 : 266; + tm = m_adcsr & 0x08 ? 134 : 266; else - tm = adcsr & 0x08 ? 128 : 256; + tm = m_adcsr & 0x08 ? 128 : 256; return tm; } void h8_adc_3337_device::mode_update() { - trigger = adcr & 0x80 ? T_EXT : T_SOFT; + m_trigger = m_adcr & 0x80 ? T_EXT : T_SOFT; - if(adcsr & 0x10) { - start_mode = ACTIVE | ROTATE; - start_channel = adcsr & 4; - end_channel = adcsr & 7; + if(m_adcsr & 0x10) { + m_start_mode = ACTIVE | ROTATE; + m_start_channel = m_adcsr & 4; + m_end_channel = m_adcsr & 7; } else { - start_mode = ACTIVE; - start_channel = end_channel = adcsr & 7; + m_start_mode = ACTIVE; + m_start_channel = m_end_channel = m_adcsr & 7; } } @@ -306,30 +306,30 @@ void h8_adc_3337_device::mode_update() h8_adc_3006_device::h8_adc_3006_device(const machine_config &mconfig, const char *tag, device_t *owner, uint32_t clock) : h8_adc_device(mconfig, H8_ADC_3006, tag, owner, clock) { - register_mask = 3; + m_register_mask = 3; } int h8_adc_3006_device::conversion_time(bool first, bool poweron) { int tm; if(first) - tm = adcsr & 0x08 ? 70 : 134; + tm = m_adcsr & 0x08 ? 70 : 134; else - tm = adcsr & 0x08 ? 66 : 128; + tm = m_adcsr & 0x08 ? 66 : 128; return tm; } void h8_adc_3006_device::mode_update() { - trigger = adcr & 0x80 ? T_EXT|T_TIMER : T_SOFT; + m_trigger = m_adcr & 0x80 ? T_EXT|T_TIMER : T_SOFT; - if(adcsr & 0x10) { - start_mode = ACTIVE | ROTATE; - start_channel = adcsr & 4; - end_channel = adcsr & 7; + if(m_adcsr & 0x10) { + m_start_mode = ACTIVE | ROTATE; + m_start_channel = m_adcsr & 4; + m_end_channel = m_adcsr & 7; } else { - start_mode = ACTIVE; - start_channel = end_channel = adcsr & 7; + m_start_mode = ACTIVE; + m_start_channel = m_end_channel = m_adcsr & 7; } } @@ -337,30 +337,30 @@ void h8_adc_3006_device::mode_update() h8_adc_2245_device::h8_adc_2245_device(const machine_config &mconfig, const char *tag, device_t *owner, uint32_t clock) : h8_adc_device(mconfig, H8_ADC_2245, tag, owner, clock) { - register_mask = 3; + m_register_mask = 3; } int h8_adc_2245_device::conversion_time(bool first, bool poweron) { int tm; if(first) - tm = adcsr & 0x08 ? 134 : 266; + tm = m_adcsr & 0x08 ? 134 : 266; else - tm = adcsr & 0x08 ? 128 : 256; + tm = m_adcsr & 0x08 ? 128 : 256; return tm; } void h8_adc_2245_device::mode_update() { - trigger = 1 << ((adcr >> 6) & 3); + m_trigger = 1 << ((m_adcr >> 6) & 3); - if(adcsr & 0x10) { - start_mode = ACTIVE | ROTATE; - start_channel = 0; - end_channel = adcsr & 3; + if(m_adcsr & 0x10) { + m_start_mode = ACTIVE | ROTATE; + m_start_channel = 0; + m_end_channel = m_adcsr & 3; } else { - start_mode = ACTIVE; - start_channel = end_channel = adcsr & 3; + m_start_mode = ACTIVE; + m_start_channel = m_end_channel = m_adcsr & 3; } } @@ -368,36 +368,36 @@ void h8_adc_2245_device::mode_update() h8_adc_2320_device::h8_adc_2320_device(const machine_config &mconfig, const char *tag, device_t *owner, uint32_t clock) : h8_adc_device(mconfig, H8_ADC_2320, tag, owner, clock) { - register_mask = 3; + m_register_mask = 3; } int h8_adc_2320_device::conversion_time(bool first, bool poweron) { int tm; if(first) - if(adcr & 0x04) - tm = adcsr & 0x08 ? 134 : 266; + if(m_adcr & 0x04) + tm = m_adcsr & 0x08 ? 134 : 266; else - tm = adcsr & 0x08 ? 68 : 580; + tm = m_adcsr & 0x08 ? 68 : 580; else - if(adcr & 0x04) - tm = adcsr & 0x08 ? 128 : 256; + if(m_adcr & 0x04) + tm = m_adcsr & 0x08 ? 128 : 256; else - tm = adcsr & 0x08 ? 64 : 512; + tm = m_adcsr & 0x08 ? 64 : 512; return tm; } void h8_adc_2320_device::mode_update() { - trigger = 1 << ((adcr >> 6) & 3); + m_trigger = 1 << ((m_adcr >> 6) & 3); - if(adcsr & 0x10) { - start_mode = ACTIVE | ROTATE; - start_channel = adcsr & 4; - end_channel = adcsr & 7; + if(m_adcsr & 0x10) { + m_start_mode = ACTIVE | ROTATE; + m_start_channel = m_adcsr & 4; + m_end_channel = m_adcsr & 7; } else { - start_mode = ACTIVE; - start_channel = end_channel = adcsr & 7; + m_start_mode = ACTIVE; + m_start_channel = m_end_channel = m_adcsr & 7; } } @@ -405,30 +405,30 @@ void h8_adc_2320_device::mode_update() h8_adc_2357_device::h8_adc_2357_device(const machine_config &mconfig, const char *tag, device_t *owner, uint32_t clock) : h8_adc_device(mconfig, H8_ADC_2357, tag, owner, clock) { - register_mask = 3; + m_register_mask = 3; } int h8_adc_2357_device::conversion_time(bool first, bool poweron) { int tm; if(first) - tm = adcsr & 0x08 ? 134 : 266; + tm = m_adcsr & 0x08 ? 134 : 266; else - tm = adcsr & 0x08 ? 128 : 256; + tm = m_adcsr & 0x08 ? 128 : 256; return tm; } void h8_adc_2357_device::mode_update() { - trigger = 1 << ((adcr >> 6) & 3); + m_trigger = 1 << ((m_adcr >> 6) & 3); - if(adcsr & 0x10) { - start_mode = ACTIVE | ROTATE; - start_channel = adcsr & 4; - end_channel = adcsr & 7; + if(m_adcsr & 0x10) { + m_start_mode = ACTIVE | ROTATE; + m_start_channel = m_adcsr & 4; + m_end_channel = m_adcsr & 7; } else { - start_mode = ACTIVE; - start_channel = end_channel = adcsr & 7; + m_start_mode = ACTIVE; + m_start_channel = m_end_channel = m_adcsr & 7; } } @@ -436,15 +436,15 @@ void h8_adc_2357_device::mode_update() h8_adc_2655_device::h8_adc_2655_device(const machine_config &mconfig, const char *tag, device_t *owner, uint32_t clock) : h8_adc_device(mconfig, H8_ADC_2655, tag, owner, clock) { - suspend_on_interrupt = true; - register_mask = 7; + m_suspend_on_interrupt = true; + m_register_mask = 7; } int h8_adc_2655_device::conversion_time(bool first, bool poweron) { - int tm = adcsr & 0x10 ? 44 : 24; + int tm = m_adcsr & 0x10 ? 44 : 24; if(first) - tm += adcsr & 0x10 ? 20 : 10; + tm += m_adcsr & 0x10 ? 20 : 10; if(poweron) tm += 200; return tm; @@ -452,51 +452,51 @@ int h8_adc_2655_device::conversion_time(bool first, bool poweron) void h8_adc_2655_device::mode_update() { - trigger = 1 << ((adcr >> 4) & 3); - analog_power_control = !(adcr & 0x40); + m_trigger = 1 << ((m_adcr >> 4) & 3); + m_analog_power_control = !(m_adcr & 0x40); - mode = ACTIVE | (adcr & 0x08 ? REPEAT : 0); + m_mode = ACTIVE | (m_adcr & 0x08 ? REPEAT : 0); - if(adcsr & 0x03) { - mode |= BUFFER; + if(m_adcsr & 0x03) { + m_mode |= BUFFER; } - if(adcsr & 0x08) { - mode |= ROTATE; - start_channel = 0; - if(adcr & 0x04) { - mode |= DUAL; - end_channel = (adcsr & 6)+1; + if(m_adcsr & 0x08) { + m_mode |= ROTATE; + m_start_channel = 0; + if(m_adcr & 0x04) { + m_mode |= DUAL; + m_end_channel = (m_adcsr & 6)+1; } else - end_channel = adcsr & 7; + m_end_channel = m_adcsr & 7; } else - start_channel = end_channel = adcsr & 7; + m_start_channel = m_end_channel = m_adcsr & 7; } void h8_adc_2655_device::do_buffering(int buffer) { - if((mode & COUNTED) && channel >= 2) { - commit_value(channel, buffer); + if((m_mode & COUNTED) && m_channel >= 2) { + commit_value(m_channel, buffer); return; } - switch(adcsr & 3) { + switch(m_adcsr & 3) { case 0: - commit_value(channel, buffer); + commit_value(m_channel, buffer); break; case 1: - addr[1] = addr[0]; + m_addr[1] = m_addr[0]; commit_value(0, buffer); break; case 2: - addr[2+buffer] = addr[buffer]; + m_addr[2+buffer] = m_addr[buffer]; commit_value(buffer, buffer); break; case 3: - addr[3] = addr[2]; - addr[2] = addr[1]; - addr[1] = addr[0]; + m_addr[3] = m_addr[2]; + m_addr[2] = m_addr[1]; + m_addr[1] = m_addr[0]; commit_value(0, buffer); break; } diff --git a/src/devices/cpu/h8/h8_adc.h b/src/devices/cpu/h8/h8_adc.h index e54d3b747d9..389f6a9121f 100644 --- a/src/devices/cpu/h8/h8_adc.h +++ b/src/devices/cpu/h8/h8_adc.h @@ -35,11 +35,11 @@ public: protected: h8_adc_device(const machine_config &mconfig, device_type type, const char *tag, device_t *owner, uint32_t clock); - required_device cpu; - h8_intc_device *intc; - address_space *io; - const char *intc_tag; - int intc_vector; + required_device m_cpu; + h8_intc_device *m_intc; + address_space *m_io; + const char *m_intc_tag; + int m_intc_vector; enum { T_SOFT = 1<<0, @@ -65,14 +65,14 @@ protected: COUNTED = 64 }; - uint16_t addr[8], buf[2]; - uint8_t adcsr, adcr; - int register_mask; - int trigger, start_mode, start_channel, end_channel, start_count; - bool suspend_on_interrupt, analog_power_control; - int mode, channel, count; - bool analog_powered, adtrg; - uint64_t next_event; + uint16_t m_addr[8], m_buf[2]; + uint8_t m_adcsr, m_adcr; + int m_register_mask; + int m_trigger, m_start_mode, m_start_channel, m_end_channel, m_start_count; + bool m_suspend_on_interrupt, m_analog_power_control; + int m_mode, m_channel, m_count; + bool m_analog_powered, m_adtrg; + uint64_t m_next_event; virtual void device_start() override; virtual void device_reset() override; diff --git a/src/devices/cpu/h8/h8_dma.cpp b/src/devices/cpu/h8/h8_dma.cpp index 2c2fa9d3fe5..aa579f86be0 100644 --- a/src/devices/cpu/h8/h8_dma.cpp +++ b/src/devices/cpu/h8/h8_dma.cpp @@ -6,33 +6,33 @@ DEFINE_DEVICE_TYPE(H8_DMA_CHANNEL, h8_dma_channel_device, "h8_dma_channel", "H8 h8_dma_device::h8_dma_device(const machine_config &mconfig, const char *tag, device_t *owner, uint32_t clock) : device_t(mconfig, H8_DMA, tag, owner, clock), - dmach0(*this, "0"), - dmach1(*this, "1") + m_dmach0(*this, "0"), + m_dmach1(*this, "1") { } void h8_dma_device::device_start() { - dmach0->set_id(0<<1); - dmach1->set_id(1<<1); + m_dmach0->set_id(0<<1); + m_dmach1->set_id(1<<1); - save_item(NAME(dmabcr)); - save_item(NAME(dmawer)); - save_item(NAME(dreq)); + save_item(NAME(m_dmabcr)); + save_item(NAME(m_dmawer)); + save_item(NAME(m_dreq)); } void h8_dma_device::device_reset() { - dmabcr = 0x0000; - dmawer = 0x00; - dreq[0] = dreq[1] = false; + m_dmabcr = 0x0000; + m_dmawer = 0x00; + m_dreq[0] = m_dreq[1] = false; } bool h8_dma_device::trigger_dma(int vector) { // Don't shortcut! Both dmas may be started - bool start0 = dmach0->start_test(vector); - bool start1 = dmach1->start_test(vector); + bool start0 = m_dmach0->start_test(vector); + bool start1 = m_dmach1->start_test(vector); return start0 || start1; } @@ -40,312 +40,312 @@ bool h8_dma_device::trigger_dma(int vector) void h8_dma_device::count_last(int id) { if(id & 2) - dmach1->count_last(id & 1); + m_dmach1->count_last(id & 1); else - dmach0->count_last(id & 1); + m_dmach0->count_last(id & 1); } void h8_dma_device::count_done(int id) { if(id & 2) - dmach1->count_done(id & 1); + m_dmach1->count_done(id & 1); else - dmach0->count_done(id & 1); + m_dmach0->count_done(id & 1); } void h8_dma_device::clear_dte(int id) { - dmabcr &= ~(0x0010 << id); + m_dmabcr &= ~(0x0010 << id); } void h8_dma_device::set_input(int inputnum, int state) { if(inputnum == H8_INPUT_LINE_DREQ0) { if(state == ASSERT_LINE) { - dmach0->start_test(h8_dma_channel_device::DREQ_LEVEL); - if(!dreq[0]) - dmach0->start_test(h8_dma_channel_device::DREQ_EDGE); + m_dmach0->start_test(h8_dma_channel_device::DREQ_LEVEL); + if(!m_dreq[0]) + m_dmach0->start_test(h8_dma_channel_device::DREQ_EDGE); } - dreq[0] = (state == ASSERT_LINE); + m_dreq[0] = (state == ASSERT_LINE); } else if(inputnum == H8_INPUT_LINE_DREQ1) { if(state == ASSERT_LINE) { - dmach1->start_test(h8_dma_channel_device::DREQ_LEVEL); - if(!dreq[1]) - dmach1->start_test(h8_dma_channel_device::DREQ_EDGE); + m_dmach1->start_test(h8_dma_channel_device::DREQ_LEVEL); + if(!m_dreq[1]) + m_dmach1->start_test(h8_dma_channel_device::DREQ_EDGE); } - dreq[1] = (state == ASSERT_LINE); + m_dreq[1] = (state == ASSERT_LINE); } else logerror("input line %d not supported for h8_dma_device\n", inputnum); } uint8_t h8_dma_device::dmawer_r() { - logerror("dmawer_r %02x\n", dmawer); - return dmawer; + logerror("dmawer_r %02x\n", m_dmawer); + return m_dmawer; } void h8_dma_device::dmawer_w(uint8_t data) { - dmawer = data; + m_dmawer = data; logerror("dmawer_w %02x\n", data); } uint8_t h8_dma_device::dmatcr_r() { - logerror("dmatcr_r %02x\n", dmatcr); - return dmatcr; + logerror("dmatcr_r %02x\n", m_dmatcr); + return m_dmatcr; } void h8_dma_device::dmatcr_w(uint8_t data) { - dmatcr = data; + m_dmatcr = data; logerror("dmatcr_w %02x\n", data); } uint16_t h8_dma_device::dmabcr_r() { - logerror("dmabcr_r %04x\n", dmabcr); - return dmabcr; + logerror("dmabcr_r %04x\n", m_dmabcr); + return m_dmabcr; } void h8_dma_device::dmabcr_w(offs_t offset, uint16_t data, uint16_t mem_mask) { - COMBINE_DATA(&dmabcr); - logerror("dmabcr_w %04x\n", dmabcr); - dmach0->set_bcr(dmabcr & 0x4000, dmabcr & 0x1000, dmabcr >> 8, dmabcr >> 4, dmabcr >> 0); - dmach1->set_bcr(dmabcr & 0x8000, dmabcr & 0x2000, dmabcr >> 10, dmabcr >> 6, dmabcr >> 2); + COMBINE_DATA(&m_dmabcr); + logerror("dmabcr_w %04x\n", m_dmabcr); + m_dmach0->set_bcr(m_dmabcr & 0x4000, m_dmabcr & 0x1000, m_dmabcr >> 8, m_dmabcr >> 4, m_dmabcr >> 0); + m_dmach1->set_bcr(m_dmabcr & 0x8000, m_dmabcr & 0x2000, m_dmabcr >> 10, m_dmabcr >> 6, m_dmabcr >> 2); } h8_dma_channel_device::h8_dma_channel_device(const machine_config &mconfig, const char *tag, device_t *owner, uint32_t clock) : device_t(mconfig, H8_DMA_CHANNEL, tag, owner, clock), - dmac(*this, "^"), - cpu(*this, "^^"), - intc(*this, finder_base::DUMMY_TAG) -{ -} - -void h8_dma_channel_device::set_info(int _irq_base, int v0, int v1, int v2, int v3, int v4, int v5, int v6, int v7, int v8, int v9, int va, int vb, int vc, int vd, int ve, int vf) -{ - irq_base = _irq_base; - activation_vectors[ 0] = v0; - activation_vectors[ 1] = v1; - activation_vectors[ 2] = v2; - activation_vectors[ 3] = v3; - activation_vectors[ 4] = v4; - activation_vectors[ 5] = v5; - activation_vectors[ 6] = v6; - activation_vectors[ 7] = v7; - activation_vectors[ 8] = v8; - activation_vectors[ 9] = v9; - activation_vectors[10] = va; - activation_vectors[11] = vb; - activation_vectors[12] = vc; - activation_vectors[13] = vd; - activation_vectors[14] = ve; - activation_vectors[15] = vf; - memset(state, 0, sizeof(state)); + m_dmac(*this, "^"), + m_cpu(*this, "^^"), + m_intc(*this, finder_base::DUMMY_TAG) +{ +} + +void h8_dma_channel_device::set_info(int irq_base, int v0, int v1, int v2, int v3, int v4, int v5, int v6, int v7, int v8, int v9, int va, int vb, int vc, int vd, int ve, int vf) +{ + m_irq_base = irq_base; + m_activation_vectors[ 0] = v0; + m_activation_vectors[ 1] = v1; + m_activation_vectors[ 2] = v2; + m_activation_vectors[ 3] = v3; + m_activation_vectors[ 4] = v4; + m_activation_vectors[ 5] = v5; + m_activation_vectors[ 6] = v6; + m_activation_vectors[ 7] = v7; + m_activation_vectors[ 8] = v8; + m_activation_vectors[ 9] = v9; + m_activation_vectors[10] = va; + m_activation_vectors[11] = vb; + m_activation_vectors[12] = vc; + m_activation_vectors[13] = vd; + m_activation_vectors[14] = ve; + m_activation_vectors[15] = vf; + memset(m_state, 0, sizeof(m_state)); } void h8_dma_channel_device::device_start() { - save_item(STRUCT_MEMBER(state, source)); - save_item(STRUCT_MEMBER(state, dest)); - save_item(STRUCT_MEMBER(state, incs)); - save_item(STRUCT_MEMBER(state, incd)); - save_item(STRUCT_MEMBER(state, count)); - save_item(STRUCT_MEMBER(state, id)); - save_item(STRUCT_MEMBER(state, autoreq)); - save_item(STRUCT_MEMBER(state, suspended)); - save_item(STRUCT_MEMBER(state, mode_16)); - save_item(NAME(mar)); - save_item(NAME(ioar)); - save_item(NAME(etcr)); - save_item(NAME(dmacr)); - save_item(NAME(dtcr)); - save_item(NAME(dta)); - save_item(NAME(dte)); - save_item(NAME(dtie)); - save_item(NAME(fae)); - save_item(NAME(sae)); + save_item(STRUCT_MEMBER(m_state, m_source)); + save_item(STRUCT_MEMBER(m_state, m_dest)); + save_item(STRUCT_MEMBER(m_state, m_incs)); + save_item(STRUCT_MEMBER(m_state, m_incd)); + save_item(STRUCT_MEMBER(m_state, m_count)); + save_item(STRUCT_MEMBER(m_state, m_id)); + save_item(STRUCT_MEMBER(m_state, m_autoreq)); + save_item(STRUCT_MEMBER(m_state, m_suspended)); + save_item(STRUCT_MEMBER(m_state, m_mode_16)); + save_item(NAME(m_mar)); + save_item(NAME(m_ioar)); + save_item(NAME(m_etcr)); + save_item(NAME(m_dmacr)); + save_item(NAME(m_dtcr)); + save_item(NAME(m_dta)); + save_item(NAME(m_dte)); + save_item(NAME(m_dtie)); + save_item(NAME(m_fae)); + save_item(NAME(m_sae)); } void h8_dma_channel_device::device_reset() { - dmacr = 0x0000; - mar[0] = mar[1] = 0; - ioar[0] = ioar[1] = 0; - etcr[0] = etcr[1] = 0; - dtcr[0] = dtcr[1] = 0; - fae = sae = false; - dta = dte = dtie = 0; + m_dmacr = 0x0000; + m_mar[0] = m_mar[1] = 0; + m_ioar[0] = m_ioar[1] = 0; + m_etcr[0] = m_etcr[1] = 0; + m_dtcr[0] = m_dtcr[1] = 0; + m_fae = m_sae = false; + m_dta = m_dte = m_dtie = 0; } void h8_dma_channel_device::set_id(int id) { - state[0].id = id; - state[1].id = id | 1; + m_state[0].m_id = id; + m_state[1].m_id = id | 1; } uint16_t h8_dma_channel_device::marah_r() { - logerror("marah_r %06x\n", mar[0]); - return mar[0] >> 16; + logerror("marah_r %06x\n", m_mar[0]); + return m_mar[0] >> 16; } void h8_dma_channel_device::marah_w(offs_t offset, uint16_t data, uint16_t mem_mask) { if(ACCESSING_BITS_0_7) - mar[0] = ((data & 0x00ff) << 16) | (mar[0] & 0xffff); - logerror("marah_w %06x\n", mar[0]); + m_mar[0] = ((data & 0x00ff) << 16) | (m_mar[0] & 0xffff); + logerror("marah_w %06x\n", m_mar[0]); } uint16_t h8_dma_channel_device::maral_r() { - logerror("maral_r %06x\n", mar[0]); - return mar[0]; + logerror("maral_r %06x\n", m_mar[0]); + return m_mar[0]; } void h8_dma_channel_device::maral_w(offs_t offset, uint16_t data, uint16_t mem_mask) { - mar[0] = (mar[0] & ~mem_mask) | (data & mem_mask); - logerror("maral_w %06x\n", mar[0]); + m_mar[0] = (m_mar[0] & ~mem_mask) | (data & mem_mask); + logerror("maral_w %06x\n", m_mar[0]); } uint16_t h8_dma_channel_device::ioara_r() { - return ioar[0]; + return m_ioar[0]; } uint8_t h8_dma_channel_device::ioara8_r() { - return ioar[0] & 0x00ff; + return m_ioar[0] & 0x00ff; } void h8_dma_channel_device::ioara_w(offs_t offset, uint16_t data, uint16_t mem_mask) { - COMBINE_DATA(&ioar[0]); - logerror("ioara_w %04x\n", ioar[0]); + COMBINE_DATA(&m_ioar[0]); + logerror("ioara_w %04x\n", m_ioar[0]); } void h8_dma_channel_device::ioara8_w(uint8_t data) { - ioar[0] = data | 0xff00; - logerror("ioara_w %04x\n", ioar[0]); + m_ioar[0] = data | 0xff00; + logerror("ioara_w %04x\n", m_ioar[0]); } uint16_t h8_dma_channel_device::etcra_r() { - logerror("etcra_r %04x\n", etcr[0]); - return etcr[0]; + logerror("etcra_r %04x\n", m_etcr[0]); + return m_etcr[0]; } void h8_dma_channel_device::etcra_w(offs_t offset, uint16_t data, uint16_t mem_mask) { - COMBINE_DATA(&etcr[0]); - logerror("etcra_w %04x\n", etcr[0]); + COMBINE_DATA(&m_etcr[0]); + logerror("etcra_w %04x\n", m_etcr[0]); } uint16_t h8_dma_channel_device::marbh_r() { - logerror("marbh_r %06x\n", mar[1]); - return mar[1] >> 16; + logerror("marbh_r %06x\n", m_mar[1]); + return m_mar[1] >> 16; } void h8_dma_channel_device::marbh_w(offs_t offset, uint16_t data, uint16_t mem_mask) { if(ACCESSING_BITS_0_7) - mar[1] = ((data & 0x00ff) << 16) | (mar[1] & 0xffff); - logerror("marbh_w %06x\n", mar[1]); + m_mar[1] = ((data & 0x00ff) << 16) | (m_mar[1] & 0xffff); + logerror("marbh_w %06x\n", m_mar[1]); } uint16_t h8_dma_channel_device::marbl_r() { - logerror("marbl_r %06x\n", mar[1]); - return mar[1]; + logerror("marbl_r %06x\n", m_mar[1]); + return m_mar[1]; } void h8_dma_channel_device::marbl_w(offs_t offset, uint16_t data, uint16_t mem_mask) { - mar[1] = (mar[1] & ~mem_mask) | (data & mem_mask); - logerror("marbl_w %06x\n", mar[1]); + m_mar[1] = (m_mar[1] & ~mem_mask) | (data & mem_mask); + logerror("marbl_w %06x\n", m_mar[1]); } uint16_t h8_dma_channel_device::ioarb_r() { - return ioar[1]; + return m_ioar[1]; } uint8_t h8_dma_channel_device::ioarb8_r() { - return ioar[1] & 0x00ff; + return m_ioar[1] & 0x00ff; } void h8_dma_channel_device::ioarb_w(offs_t offset, uint16_t data, uint16_t mem_mask) { - COMBINE_DATA(&ioar[1]); - logerror("ioarb_w %04x\n", ioar[1]); + COMBINE_DATA(&m_ioar[1]); + logerror("ioarb_w %04x\n", m_ioar[1]); } void h8_dma_channel_device::ioarb8_w(uint8_t data) { - ioar[1] = data | 0xff00; - logerror("ioarb_w %04x\n", ioar[1]); + m_ioar[1] = data | 0xff00; + logerror("ioarb_w %04x\n", m_ioar[1]); } uint16_t h8_dma_channel_device::etcrb_r() { - logerror("etcrb_r %04x\n", etcr[1]); - return etcr[1]; + logerror("etcrb_r %04x\n", m_etcr[1]); + return m_etcr[1]; } void h8_dma_channel_device::etcrb_w(offs_t offset, uint16_t data, uint16_t mem_mask) { - COMBINE_DATA(&etcr[1]); - logerror("etcrb_w %04x\n", etcr[1]); + COMBINE_DATA(&m_etcr[1]); + logerror("etcrb_w %04x\n", m_etcr[1]); } uint16_t h8_dma_channel_device::dmacr_r() { - logerror("dmacr_r %04x\n", dmacr); - return dmacr; + logerror("dmacr_r %04x\n", m_dmacr); + return m_dmacr; } void h8_dma_channel_device::dmacr_w(offs_t offset, uint16_t data, uint16_t mem_mask) { - COMBINE_DATA(&dmacr); - logerror("dmacr_w %04x\n", dmacr); + COMBINE_DATA(&m_dmacr); + logerror("dmacr_w %04x\n", m_dmacr); start_test(-1); } // H8H DMA uint8_t h8_dma_channel_device::dtcra_r() { - logerror("dtcra_r %02x\n", dtcr[0]); - return dtcr[0]; + logerror("dtcra_r %02x\n", m_dtcr[0]); + return m_dtcr[0]; } void h8_dma_channel_device::dtcra_w(uint8_t data) { - dtcr[0] = data; - logerror("dtcra_w %02x\n", dtcr[0]); - if((dtcr[0] & 0x80) && (dtcr[1] & 0x80)) { // if both DTME and DTE are set, start DMA + m_dtcr[0] = data; + logerror("dtcra_w %02x\n", m_dtcr[0]); + if((m_dtcr[0] & 0x80) && (m_dtcr[1] & 0x80)) { // if both DTME and DTE are set, start DMA h8h_sync(); } } uint8_t h8_dma_channel_device::dtcrb_r() { - logerror("dtcrb_r %02x\n", dtcr[1]); - return dtcr[1]; + logerror("dtcrb_r %02x\n", m_dtcr[1]); + return m_dtcr[1]; } void h8_dma_channel_device::dtcrb_w(uint8_t data) { - dtcr[1] = data; - logerror("dtcrb_w %02x\n", dtcr[1]); - if((dtcr[0] & 0x80) && (dtcr[1] & 0x80)) { // if both DTME and DTE are set, start DMA + m_dtcr[1] = data; + logerror("dtcrb_w %02x\n", m_dtcr[1]); + if((m_dtcr[0] & 0x80) && (m_dtcr[1] & 0x80)) { // if both DTME and DTE are set, start DMA h8h_sync(); } } @@ -353,84 +353,84 @@ void h8_dma_channel_device::dtcrb_w(uint8_t data) void h8_dma_channel_device::h8h_sync() { // update DMACR - dmacr = 0; - if(BIT(dtcr[0], 6)) dmacr |= 1 << 15; // DTSZ - dmacr |= ((dtcr[0] & 0b110000) >> 4) << 13; // SAID/DTID, SAIDE/RPE - dmacr |= ((dtcr[1] & 0b110000) >> 4) << 5; // DAID/DTID, DAIDE/RPE - - uint8_t _dte = 0; - if(BIT(dtcr[0], 7)) _dte |= 0b01; // DTE - if(BIT(dtcr[1], 7)) _dte |= 0b10; // DTME/DTE - - bool _fae = (dtcr[0] & 0b110) == 0b110; // A channel operates in full address mode when DTS2A and DTS1A are both set to 1. - bool _sae = false; // don't support - uint8_t _dta = 0; // don't support - uint8_t _dtie = 0; - if(_fae) { + m_dmacr = 0; + if(BIT(m_dtcr[0], 6)) m_dmacr |= 1 << 15; // DTSZ + m_dmacr |= ((m_dtcr[0] & 0b110000) >> 4) << 13; // SAID/DTID, SAIDE/RPE + m_dmacr |= ((m_dtcr[1] & 0b110000) >> 4) << 5; // DAID/DTID, DAIDE/RPE + + uint8_t dte = 0; + if(BIT(m_dtcr[0], 7)) dte |= 0b01; // DTE + if(BIT(m_dtcr[1], 7)) dte |= 0b10; // DTME/DTE + + bool fae = (m_dtcr[0] & 0b110) == 0b110; // A channel operates in full address mode when DTS2A and DTS1A are both set to 1. + bool sae = false; // don't support + uint8_t dta = 0; // don't support + uint8_t dtie = 0; + if(fae) { // Full address mode - if(BIT(dtcr[0], 3)) _dtie = 0b11; - if(BIT(dtcr[0], 0)) { + if(BIT(m_dtcr[0], 3)) dtie = 0b11; + if(BIT(m_dtcr[0], 0)) { // Block Transfer Mode - dmacr |= 1 << 11; // BLKE - if(BIT(dtcr[1], 3)) dmacr |= 1 << 12; // BLKDIR (TMS) - switch(dtcr[1] & 0b111) { // DTP (DTS) - case 0b000: dmacr |= 0b1000; break; // ITU channel 0 - case 0b001: dmacr |= 0b1001; break; // ITU channel 1 - case 0b010: dmacr |= 0b1010; break; // ITU channel 2 - case 0b011: dmacr |= 0b1011; break; // ITU channel 3 - case 0b110: dmacr |= 0b1000; break; // DREQ falling edge + m_dmacr |= 1 << 11; // BLKE + if(BIT(m_dtcr[1], 3)) m_dmacr |= 1 << 12; // BLKDIR (TMS) + switch(m_dtcr[1] & 0b111) { // DTP (DTS) + case 0b000: m_dmacr |= 0b1000; break; // ITU channel 0 + case 0b001: m_dmacr |= 0b1001; break; // ITU channel 1 + case 0b010: m_dmacr |= 0b1010; break; // ITU channel 2 + case 0b011: m_dmacr |= 0b1011; break; // ITU channel 3 + case 0b110: m_dmacr |= 0b1000; break; // DREQ falling edge } } else { // Normal Mode - switch(dtcr[1] & 0b111) { // DTP (DTS) - case 0b000: dmacr |= 0b0111; break; // Auto-request (burst mode) - case 0b010: dmacr |= 0b0110; break; // Auto-request (cycle-steal mode) - case 0b110: dmacr |= 0b0010; break; // DREQ falling edge - case 0b111: dmacr |= 0b0011; break; // DREQ low-level + switch(m_dtcr[1] & 0b111) { // DTP (DTS) + case 0b000: m_dmacr |= 0b0111; break; // Auto-request (burst mode) + case 0b010: m_dmacr |= 0b0110; break; // Auto-request (cycle-steal mode) + case 0b110: m_dmacr |= 0b0010; break; // DREQ falling edge + case 0b111: m_dmacr |= 0b0011; break; // DREQ low-level } } } else { // Short address mode - if(BIT(dtcr[0], 3)) _dtie |= 0b01; - if(BIT(dtcr[1], 3)) _dtie |= 0b10; + if(BIT(m_dtcr[0], 3)) dtie |= 0b01; + if(BIT(m_dtcr[1], 3)) dtie |= 0b10; for(int submodule = 0; submodule < 2; submodule++) { - switch(dtcr[submodule] & 0b111) { // DTP, DTDIR (DTS) - case 0b000: dmacr |= 0b01000 << (submodule ? 0 : 8); break; // ITU channel 0 - case 0b001: dmacr |= 0b01001 << (submodule ? 0 : 8); break; // ITU channel 1 - case 0b010: dmacr |= 0b01010 << (submodule ? 0 : 8); break; // ITU channel 2 - case 0b011: dmacr |= 0b01011 << (submodule ? 0 : 8); break; // ITU channel 3 - //case 0b011: dmacr |= 0b10001 << (submodule ? 0 : 8); break; // A/D converter conversion end (H8/3006) - case 0b100: dmacr |= 0b00100 << (submodule ? 0 : 8); break; // SCI channel 0 transmission data empty - case 0b101: dmacr |= 0b10101 << (submodule ? 0 : 8); break; // SCI channel 0 receive data full - case 0b110: dmacr |= 0b00010 << (submodule ? 0 : 8); break; // DREQ falling edge (B only) - case 0b111: dmacr |= 0b00011 << (submodule ? 0 : 8); break; // DREQ low-level (B only) + switch(m_dtcr[submodule] & 0b111) { // DTP, DTDIR (DTS) + case 0b000: m_dmacr |= 0b01000 << (submodule ? 0 : 8); break; // ITU channel 0 + case 0b001: m_dmacr |= 0b01001 << (submodule ? 0 : 8); break; // ITU channel 1 + case 0b010: m_dmacr |= 0b01010 << (submodule ? 0 : 8); break; // ITU channel 2 + case 0b011: m_dmacr |= 0b01011 << (submodule ? 0 : 8); break; // ITU channel 3 + //case 0b011: m_dmacr |= 0b10001 << (submodule ? 0 : 8); break; // A/D converter conversion end (H8/3006) + case 0b100: m_dmacr |= 0b00100 << (submodule ? 0 : 8); break; // SCI channel 0 transmission data empty + case 0b101: m_dmacr |= 0b10101 << (submodule ? 0 : 8); break; // SCI channel 0 receive data full + case 0b110: m_dmacr |= 0b00010 << (submodule ? 0 : 8); break; // DREQ falling edge (B only) + case 0b111: m_dmacr |= 0b00011 << (submodule ? 0 : 8); break; // DREQ low-level (B only) } } } - set_bcr(_fae, _sae, _dta, _dte, _dtie); + set_bcr(fae, sae, dta, dte, dtie); start_test(-1); } -void h8_dma_channel_device::set_bcr(bool _fae, bool _sae, uint8_t _dta, uint8_t _dte, uint8_t _dtie) +void h8_dma_channel_device::set_bcr(bool fae, bool sae, uint8_t dta, uint8_t dte, uint8_t dtie) { - fae = _fae; - sae = _sae; - dta = _dta & 3; - dte = _dte & 3; - dtie = _dtie & 3; + m_fae = fae; + m_sae = sae; + m_dta = dta & 3; + m_dte = dte & 3; + m_dtie = dtie & 3; logerror("fae=%d sae=%d dta=%d dte=%d dtie=%d\n", fae, sae, dta & 3, dte & 3, dtie & 3); start_test(-1); } bool h8_dma_channel_device::start_test(int vector) { - if(fae) { - if(dte != 3) + if(m_fae) { + if(m_dte != 3) return false; - if(dmacr & 0x0800) { + if(m_dmacr & 0x0800) { throw emu_fatalerror("%s: DMA startup test in full address/block mode unimplemented.\n", tag()); } else { @@ -440,28 +440,28 @@ bool h8_dma_channel_device::start_test(int vector) return true; } else { // DREQ trigger - if(((dmacr & 0b111) == 0b0010 && vector == DREQ_EDGE) || ((dmacr & 0b111) == 0b0011 && vector == DREQ_LEVEL)) { - state[0].suspended = false; + if(((m_dmacr & 0b111) == 0b0010 && vector == DREQ_EDGE) || ((m_dmacr & 0b111) == 0b0011 && vector == DREQ_LEVEL)) { + m_state[0].m_suspended = false; return true; } } return false; } } else { - if(dte == 0) + if(m_dte == 0) return false; if(vector == -1) { // A has priority over B - if(dte & 2) + if(m_dte & 2) start(1); - if(dte & 1) + if(m_dte & 1) start(0); return true; - } else if(dte & 2) { + } else if(m_dte & 2) { // DREQ trigger (B only) - if(((dmacr & 0b111) == 0b0010 && vector == DREQ_EDGE) || ((dmacr & 0b111) == 0b0011 && vector == DREQ_LEVEL)) { - state[1].suspended = false; + if(((m_dmacr & 0b111) == 0b0010 && vector == DREQ_EDGE) || ((m_dmacr & 0b111) == 0b0011 && vector == DREQ_LEVEL)) { + m_state[1].m_suspended = false; return true; } } @@ -471,90 +471,90 @@ bool h8_dma_channel_device::start_test(int vector) void h8_dma_channel_device::start(int submodule) { - if(fae) { - if(dmacr & 0x0800) + if(m_fae) { + if(m_dmacr & 0x0800) throw emu_fatalerror("%s: DMA start in full address/block mode unimplemented.\n", tag()); else { - state[submodule].source = mar[0]; - state[submodule].dest = mar[1]; - state[submodule].count = etcr[0] ? etcr[0] : 0x10000; - state[submodule].mode_16 = dmacr & 0x8000; - state[submodule].autoreq = (dmacr & 6) == 6 || (dmacr & 7) == 3; // autoreq or dreq level - state[submodule].suspended = (dmacr & 6) != 6; // non-auto-request transfers start suspended - int32_t step = state[submodule].mode_16 ? 2 : 1; - state[submodule].incs = dmacr & 0x2000 ? dmacr & 0x4000 ? -step : step : 0; - state[submodule].incd = dmacr & 0x0020 ? dmacr & 0x0040 ? -step : step : 0; - cpu->set_current_dma(state + submodule); + m_state[submodule].m_source = m_mar[0]; + m_state[submodule].m_dest = m_mar[1]; + m_state[submodule].m_count = m_etcr[0] ? m_etcr[0] : 0x10000; + m_state[submodule].m_mode_16 = m_dmacr & 0x8000; + m_state[submodule].m_autoreq = (m_dmacr & 6) == 6 || (m_dmacr & 7) == 3; // autoreq or dreq level + m_state[submodule].m_suspended = (m_dmacr & 6) != 6; // non-auto-request transfers start suspended + int32_t step = m_state[submodule].m_mode_16 ? 2 : 1; + m_state[submodule].m_incs = m_dmacr & 0x2000 ? m_dmacr & 0x4000 ? -step : step : 0; + m_state[submodule].m_incd = m_dmacr & 0x0020 ? m_dmacr & 0x0040 ? -step : step : 0; + m_cpu->set_current_dma(m_state + submodule); } } else { - uint8_t cr = submodule ? dmacr & 0x00ff : dmacr >> 8; - state[submodule].mode_16 = cr & 0x80; - state[submodule].autoreq = false; - state[submodule].suspended = true; - int32_t step = state[submodule].mode_16 ? 2 : 1; + uint8_t cr = submodule ? m_dmacr & 0x00ff : m_dmacr >> 8; + m_state[submodule].m_mode_16 = cr & 0x80; + m_state[submodule].m_autoreq = false; + m_state[submodule].m_suspended = true; + int32_t step = m_state[submodule].m_mode_16 ? 2 : 1; if(!(cr & 0x20)) { // Sequential mode - state[submodule].count = etcr[submodule] ? etcr[submodule] : 0x10000; - state[submodule].incs = cr & 0x40 ? -step : step; - } else if(dtie & (1 << submodule)) { + m_state[submodule].m_count = m_etcr[submodule] ? m_etcr[submodule] : 0x10000; + m_state[submodule].m_incs = cr & 0x40 ? -step : step; + } else if(m_dtie & (1 << submodule)) { // Idle mode - state[submodule].count = etcr[submodule] ? etcr[submodule] : 0x10000; - state[submodule].incs = 0; + m_state[submodule].m_count = m_etcr[submodule] ? m_etcr[submodule] : 0x10000; + m_state[submodule].m_incs = 0; } else { // Repeat mode - state[submodule].count = etcr[submodule] & 0x00ff ? etcr[submodule] & 0x00ff : 0x100; - state[submodule].incs = cr & 0x40 ? -step : step; + m_state[submodule].m_count = m_etcr[submodule] & 0x00ff ? m_etcr[submodule] & 0x00ff : 0x100; + m_state[submodule].m_incs = cr & 0x40 ? -step : step; } if(cr & 0x10) { - state[submodule].source = 0xff0000 | ioar[submodule]; - state[submodule].dest = mar[submodule]; - state[submodule].incd = state[submodule].incs; - state[submodule].incs = 0; + m_state[submodule].m_source = 0xff0000 | m_ioar[submodule]; + m_state[submodule].m_dest = m_mar[submodule]; + m_state[submodule].m_incd = m_state[submodule].m_incs; + m_state[submodule].m_incs = 0; } else { - state[submodule].source = mar[submodule]; - state[submodule].dest = 0xff0000 | ioar[submodule]; - state[submodule].incd = 0; + m_state[submodule].m_source = m_mar[submodule]; + m_state[submodule].m_dest = 0xff0000 | m_ioar[submodule]; + m_state[submodule].m_incd = 0; } - cpu->set_current_dma(state + submodule); + m_cpu->set_current_dma(m_state + submodule); } } void h8_dma_channel_device::count_last(int submodule) { logerror("count last on %d\n", submodule); - if(!state[submodule].autoreq) // "The TEND signal goes low during the last write cycle." - cpu->set_input_line(H8_INPUT_LINE_TEND0 + (state[submodule].id >> 1), ASSERT_LINE); + if(!m_state[submodule].m_autoreq) // "The TEND signal goes low during the last write cycle." + m_cpu->set_input_line(H8_INPUT_LINE_TEND0 + (m_state[submodule].m_id >> 1), ASSERT_LINE); } void h8_dma_channel_device::count_done(int submodule) { - if(!state[submodule].autoreq) - cpu->set_input_line(H8_INPUT_LINE_TEND0 + (state[submodule].id >> 1), CLEAR_LINE); - if(fae) { - if(dmacr & 0x0800) + if(!m_state[submodule].m_autoreq) + m_cpu->set_input_line(H8_INPUT_LINE_TEND0 + (m_state[submodule].m_id >> 1), CLEAR_LINE); + if(m_fae) { + if(m_dmacr & 0x0800) throw emu_fatalerror("%s: DMA count done full address/block mode unimplemented.\n", tag()); else { - dte &= ~1; - dmac->clear_dte(state[0].id); - dtcr[0] &= ~0x80; // clear DTE (for H8H) - if(dtie & 1) - intc->internal_interrupt(irq_base + submodule); + m_dte &= ~1; + m_dmac->clear_dte(m_state[0].m_id); + m_dtcr[0] &= ~0x80; // clear DTE (for H8H) + if(m_dtie & 1) + m_intc->internal_interrupt(m_irq_base + submodule); } } else { - uint8_t cr = submodule ? dmacr & 0x00ff : dmacr >> 8; - if((cr & 0x20) && !(dtie & (1 << submodule))) { + uint8_t cr = submodule ? m_dmacr & 0x00ff : m_dmacr >> 8; + if((cr & 0x20) && !(m_dtie & (1 << submodule))) { // Repeat mode - state[submodule].count = etcr[submodule] & 0x00ff ? etcr[submodule] & 0x00ff : 0x100; + m_state[submodule].m_count = m_etcr[submodule] & 0x00ff ? m_etcr[submodule] & 0x00ff : 0x100; if(cr & 0x10) - state[submodule].dest = mar[submodule]; + m_state[submodule].m_dest = m_mar[submodule]; else - state[submodule].source = mar[submodule]; + m_state[submodule].m_source = m_mar[submodule]; } else { - dte &= ~(1 << submodule); - dmac->clear_dte(state[0].id + submodule); - dtcr[submodule] &= ~0x80; // clear DTE (for H8H) - if(dtie & (1 << submodule)) - intc->internal_interrupt(irq_base + submodule); + m_dte &= ~(1 << submodule); + m_dmac->clear_dte(m_state[0].m_id + submodule); + m_dtcr[submodule] &= ~0x80; // clear DTE (for H8H) + if(m_dtie & (1 << submodule)) + m_intc->internal_interrupt(m_irq_base + submodule); } } } diff --git a/src/devices/cpu/h8/h8_dma.h b/src/devices/cpu/h8/h8_dma.h index 0e176c2dc6e..89de44822c9 100644 --- a/src/devices/cpu/h8/h8_dma.h +++ b/src/devices/cpu/h8/h8_dma.h @@ -17,13 +17,13 @@ #include "h8_intc.h" struct h8_dma_state { - uint32_t source, dest; - int32_t incs, incd; - uint32_t count; - int id; - bool autoreq; // activate by auto-request - bool suspended; - bool mode_16; + uint32_t m_source, m_dest; + int32_t m_incs, m_incd; + uint32_t m_count; + int m_id; + bool m_autoreq; // activate by auto-request + bool m_suspended; + bool m_mode_16; }; class h8_dma_channel_device; @@ -60,15 +60,15 @@ public: void set_input(int inputnum, int state); protected: - required_device dmach0, dmach1; + required_device m_dmach0, m_dmach1; virtual void device_start() override; virtual void device_reset() override; - bool dreq[2]; + bool m_dreq[2]; - uint8_t dmawer, dmatcr; - uint16_t dmabcr; + uint8_t m_dmawer, m_dmatcr; + uint16_t m_dmabcr; }; class h8_dma_channel_device : public device_t { @@ -100,7 +100,7 @@ public: int vf = h8_dma_channel_device::NONE) : h8_dma_channel_device(mconfig, tag, owner, 0) { - intc.set_tag(std::forward(intc_tag)); + m_intc.set_tag(std::forward(intc_tag)); set_info(irq_base, v0, v1, v2, v3, v4, v5, v6, v7, v8, v9, va, vb, vc, vd, ve, vf); } void set_info(int irq_base, int v0, int v1, int v2, int v3, int v4, int v5, int v6, int v7, int v8, int v9, int va, int vb, int vc, int vd, int ve, int vf); @@ -140,20 +140,20 @@ public: void count_last(int submodule); void count_done(int submodule); protected: - required_device dmac; - required_device cpu; - required_device intc; - h8_dma_state state[2]; - int irq_base; - - int activation_vectors[16]; - - uint32_t mar[2]; - uint16_t ioar[2], etcr[2], dmacr; - uint8_t dtcr[2]; // H8H - uint8_t dta, dte, dtie; - bool fae; // Full-Address Mode - bool sae; // Short-Address Mode + required_device m_dmac; + required_device m_cpu; + required_device m_intc; + h8_dma_state m_state[2]; + int m_irq_base; + + int m_activation_vectors[16]; + + uint32_t m_mar[2]; + uint16_t m_ioar[2], m_etcr[2], m_dmacr; + uint8_t m_dtcr[2]; // H8H + uint8_t m_dta, m_dte, m_dtie; + bool m_fae; // Full-Address Mode + bool m_sae; // Short-Address Mode virtual void device_start() override; virtual void device_reset() override; diff --git a/src/devices/cpu/h8/h8_dtc.cpp b/src/devices/cpu/h8/h8_dtc.cpp index a2668456414..f035f4f8d5d 100644 --- a/src/devices/cpu/h8/h8_dtc.cpp +++ b/src/devices/cpu/h8/h8_dtc.cpp @@ -26,189 +26,189 @@ const int h8_dtc_device::vector_to_enable[92] = { h8_dtc_device::h8_dtc_device(const machine_config &mconfig, const char *tag, device_t *owner, uint32_t clock) : device_t(mconfig, H8_DTC, tag, owner, clock), - cpu(*this, DEVICE_SELF_OWNER) + m_cpu(*this, DEVICE_SELF_OWNER) { } -void h8_dtc_device::set_info(const char *_intc_tag, int _irq) +void h8_dtc_device::set_info(const char *intc_tag, int irq) { - intc_tag = _intc_tag; - irq = _irq; + m_intc_tag = intc_tag; + m_irq = irq; } void h8_dtc_device::device_start() { - intc = siblingdevice(intc_tag); + m_intc = siblingdevice(m_intc_tag); } void h8_dtc_device::device_reset() { - memset(dtcer, 0x00, sizeof(dtcer)); - memset(states, 0, sizeof(states)); - for(uint8_t i=0; i=2) logerror("dtcer_r %x, %02x\n", offset, dtcer[offset]); - return dtcer[offset]; + if(V>=2) logerror("dtcer_r %x, %02x\n", offset, m_dtcer[offset]); + return m_dtcer[offset]; } void h8_dtc_device::dtcer_w(offs_t offset, uint8_t data) { - dtcer[offset] = data; + m_dtcer[offset] = data; if(V>=2) logerror("dtcer_w %x, %02x\n", offset, data); } uint8_t h8_dtc_device::dtvecr_r() { - if(V>=2) logerror("dtvecr_r %02x\n", dtvecr); - return dtvecr; + if(V>=2) logerror("dtvecr_r %02x\n", m_dtvecr); + return m_dtvecr; } void h8_dtc_device::dtvecr_w(uint8_t data) { - dtvecr = data; + m_dtvecr = data; if(V>=2) logerror("dtvecr_w %02x\n", data); } void h8_dtc_device::edge(int vector) { - for(std::list::const_iterator i = waiting_vector.begin(); i != waiting_vector.end(); ++i) - if(*i == vector) + for(auto i : m_waiting_vector) + if(i == vector) return; - for(std::list::const_iterator i = waiting_writeback.begin(); i != waiting_writeback.end(); ++i) - if(*i == vector) + for(auto i : m_waiting_writeback) + if(i == vector) return; - if(waiting_vector.empty() && waiting_writeback.empty()) - cpu->request_state(h8_device::STATE_DTC_VECTOR); - waiting_vector.push_back(vector); + if(m_waiting_vector.empty() && m_waiting_writeback.empty()) + m_cpu->request_state(h8_device::STATE_DTC_VECTOR); + m_waiting_vector.push_back(vector); } int h8_dtc_device::get_waiting_vector() { - assert(!waiting_vector.empty()); - return waiting_vector.front(); + assert(!m_waiting_vector.empty()); + return m_waiting_vector.front(); } int h8_dtc_device::get_waiting_writeback() { - assert(!waiting_writeback.empty()); - return waiting_writeback.front(); + assert(!m_waiting_writeback.empty()); + return m_waiting_writeback.front(); } void h8_dtc_device::queue(int vector) { int ps = -1; - int cs = cur_active_vector; + int cs = m_cur_active_vector; while(cs != -1 && cs < vector) { ps = cs; - cs = states[cs].next; + cs = m_states[cs].m_next; } - states[vector].next = cs; + m_states[vector].m_next = cs; if(ps == -1) { - cur_active_vector = vector; - cpu->set_current_dtc(&states[vector]); + m_cur_active_vector = vector; + m_cpu->set_current_dtc(&m_states[vector]); } else - states[ps].next = vector; + m_states[ps].m_next = vector; } void h8_dtc_device::vector_done(int vector) { - std::list::iterator wi; - for(wi = waiting_vector.begin(); wi != waiting_vector.end() && *wi != vector && *wi != vector + DTC_CHAINED; ++wi) {}; - assert(wi != waiting_vector.end()); - waiting_vector.erase(wi); + std::vector::iterator wi; + for(wi = m_waiting_vector.begin(); wi != m_waiting_vector.end() && *wi != vector && *wi != vector + DTC_CHAINED; ++wi) {}; + assert(wi != m_waiting_vector.end()); + m_waiting_vector.erase(wi); - h8_dtc_state *state = states + vector; - uint32_t sra = state->sra; - uint32_t dar = state->dar; - uint32_t cr = state->cr; + h8_dtc_state *state = m_states + vector; + uint32_t sra = state->m_sra; + uint32_t dar = state->m_dar; + uint32_t cr = state->m_cr; uint32_t mode = sra & 0x0c000000; - if(V>=1) logerror("regs at %08x sra=%08x dar=%08x cr=%08x %s mode\n", state->base, sra, dar, cr, + if(V>=1) logerror("regs at %08x sra=%08x dar=%08x cr=%08x %s mode\n", state->m_base, sra, dar, cr, mode == 0x00000000 || mode == 0x0c000000 ? "normal" : mode == 0x04000000 ? "repeat" : "block"); - state->incs = sra & 0x80000000 ? + state->m_incs = sra & 0x80000000 ? sra & 0x40000000 ? sra & 0x01000000 ? -2 : -1 : sra & 0x01000000 ? 2 : 1 : 0; - state->incd = sra & 0x20000000 ? + state->m_incd = sra & 0x20000000 ? sra & 0x10000000 ? sra & 0x01000000 ? -2 : -1 : sra & 0x01000000 ? 2 : 1 : 0; switch(mode) { case 0x00000000: case 0x0c0000000: - state->count = 1; + state->m_count = 1; break; case 0x04000000: - state->count = 1; + state->m_count = 1; break; case 0x08000000: - state->count = (cr >> 16) & 255; - if(!state->count) - state->count = 256; + state->m_count = (cr >> 16) & 255; + if(!state->m_count) + state->m_count = 256; break; } queue(vector); - if(!waiting_vector.empty()) - cpu->request_state(h8_device::STATE_DTC_VECTOR); - else if(!waiting_writeback.empty()) - cpu->request_state(h8_device::STATE_DTC_WRITEBACK); + if(!m_waiting_vector.empty()) + m_cpu->request_state(h8_device::STATE_DTC_VECTOR); + else if(!m_waiting_writeback.empty()) + m_cpu->request_state(h8_device::STATE_DTC_WRITEBACK); } void h8_dtc_device::writeback_done(int vector) { - std::list::iterator wi; - for(wi = waiting_writeback.begin(); wi != waiting_writeback.end() && *wi != vector; ++wi) {}; - assert(wi != waiting_writeback.end()); - waiting_writeback.erase(wi); + std::vector::iterator wi; + for(wi = m_waiting_writeback.begin(); wi != m_waiting_writeback.end() && *wi != vector; ++wi) {}; + assert(wi != m_waiting_writeback.end()); + m_waiting_writeback.erase(wi); - h8_dtc_state *state = states + vector; + h8_dtc_state *state = m_states + vector; bool done = false; - switch(state->sra & 0x0c000000) { + switch(state->m_sra & 0x0c000000) { case 0x00000000: case 0x0c0000000: - done = !(state->cr & 0xffff0000); + done = !(state->m_cr & 0xffff0000); break; case 0x04000000: break; case 0x08000000: - done = !(state->cr & 0x0000ffff); + done = !(state->m_cr & 0x0000ffff); break; } - if(done && state->dar & 0x80000000) { - cpu->request_state(h8_device::STATE_DTC_VECTOR); - waiting_vector.push_back(vector + DTC_CHAINED); + if(done && state->m_dar & 0x80000000) { + m_cpu->request_state(h8_device::STATE_DTC_VECTOR); + m_waiting_vector.push_back(vector + DTC_CHAINED); return; } - if(done || (state->dar & 0x40000000)) { + if(done || (state->m_dar & 0x40000000)) { if(vector) { int slot = vector_to_enable[vector]; assert(slot != -1); - dtcer[slot >> 3] &= ~(0x01 << (7-(slot & 7))); - intc->internal_interrupt(vector); + m_dtcer[slot >> 3] &= ~(0x01 << (7-(slot & 7))); + m_intc->internal_interrupt(vector); } else { logerror("Software dtc done\n"); exit(0); } } - if(!waiting_vector.empty()) - cpu->request_state(h8_device::STATE_DTC_VECTOR); - else if(!waiting_writeback.empty()) - cpu->request_state(h8_device::STATE_DTC_WRITEBACK); + if(!m_waiting_vector.empty()) + m_cpu->request_state(h8_device::STATE_DTC_VECTOR); + else if(!m_waiting_writeback.empty()) + m_cpu->request_state(h8_device::STATE_DTC_WRITEBACK); } bool h8_dtc_device::trigger_dtc(int vector) @@ -216,7 +216,7 @@ bool h8_dtc_device::trigger_dtc(int vector) int slot = vector_to_enable[vector]; if(slot == -1) return false; - if(dtcer[slot >> 3] & (0x01 << (7-(slot & 7)))) { + if(m_dtcer[slot >> 3] & (0x01 << (7-(slot & 7)))) { edge(vector); return true; } @@ -225,44 +225,44 @@ bool h8_dtc_device::trigger_dtc(int vector) void h8_dtc_device::count_done(int id) { - assert(cur_active_vector == id); - cur_active_vector = states[id].next; - if(cur_active_vector != -1) - cpu->set_current_dtc(states + cur_active_vector); + assert(m_cur_active_vector == id); + m_cur_active_vector = m_states[id].m_next; + if(m_cur_active_vector != -1) + m_cpu->set_current_dtc(m_states + m_cur_active_vector); - h8_dtc_state *state = states + id; - switch(state->sra & 0x0c000000) { + h8_dtc_state *state = m_states + id; + switch(state->m_sra & 0x0c000000) { case 0x00000000: case 0x0c0000000: - state->cr -= 0x00010000; + state->m_cr -= 0x00010000; break; case 0x04000000: - state->cr = (state->cr & 0xff00ffff) | ((state->cr - 0x00010000) & 0x00ff0000); - if(!(state->cr & 0x00ff0000)) { - int cnt = (state->cr >> 24) & 0xff; + state->m_cr = (state->m_cr & 0xff00ffff) | ((state->m_cr - 0x00010000) & 0x00ff0000); + if(!(state->m_cr & 0x00ff0000)) { + int cnt = (state->m_cr >> 24) & 0xff; if(!cnt) cnt = 256; - if(state->sra & 0x02000000) - state->sra = (state->sra & 0xff000000) | ((state->sra - cnt*state->incs) & 0xffffff); + if(state->m_sra & 0x02000000) + state->m_sra = (state->m_sra & 0xff000000) | ((state->m_sra - cnt*state->m_incs) & 0xffffff); else - state->dar = (state->dar & 0xff000000) | ((state->dar - cnt*state->incd) & 0xffffff); - state->cr |= (state->cr >> 8) & 0x00ff0000; + state->m_dar = (state->m_dar & 0xff000000) | ((state->m_dar - cnt*state->m_incd) & 0xffffff); + state->m_cr |= (state->m_cr >> 8) & 0x00ff0000; } break; case 0x08000000: { - int cnt = (state->cr >> 16) & 0xff; + int cnt = (state->m_cr >> 16) & 0xff; if(!cnt) cnt = 256; - if(state->sra & 0x02000000) - state->sra = (state->sra & 0xff000000) | ((state->sra - cnt*state->incs) & 0xffffff); + if(state->m_sra & 0x02000000) + state->m_sra = (state->m_sra & 0xff000000) | ((state->m_sra - cnt*state->m_incs) & 0xffffff); else - state->dar = (state->dar & 0xff000000) | ((state->dar - cnt*state->incd) & 0xffffff); - state->cr = (state->cr & 0xff000000) | ((state->cr >> 8) & 0x00ff0000) | ((state->cr - 0x00000001) & 0x0000ffff); + state->m_dar = (state->m_dar & 0xff000000) | ((state->m_dar - cnt*state->m_incd) & 0xffffff); + state->m_cr = (state->m_cr & 0xff000000) | ((state->m_cr >> 8) & 0x00ff0000) | ((state->m_cr - 0x00000001) & 0x0000ffff); break; } } - if(waiting_vector.empty() && waiting_writeback.empty()) - cpu->request_state(h8_device::STATE_DTC_WRITEBACK); - waiting_writeback.push_back(id); + if(m_waiting_vector.empty() && m_waiting_writeback.empty()) + m_cpu->request_state(h8_device::STATE_DTC_WRITEBACK); + m_waiting_writeback.push_back(id); } diff --git a/src/devices/cpu/h8/h8_dtc.h b/src/devices/cpu/h8/h8_dtc.h index 6b1a32b8a9b..9263cb3469e 100644 --- a/src/devices/cpu/h8/h8_dtc.h +++ b/src/devices/cpu/h8/h8_dtc.h @@ -18,11 +18,11 @@ #include struct h8_dtc_state { - uint32_t base, sra, dar, cr; - int32_t incs, incd; - uint32_t count; - int id; - int next; + uint32_t m_base, m_sra, m_dar, m_cr; + int32_t m_incs, m_incd; + uint32_t m_count; + int m_id; + int m_next; }; class h8_dtc_device : public device_t { @@ -45,8 +45,8 @@ public: bool trigger_dtc(int vector); void count_done(int id); - inline h8_dtc_state *get_object(int vector) { return states + vector; } - inline uint32_t get_vector_address(int vector) { return 0x400 | ((vector ? vector : dtvecr & 0x7f) << 1); } + inline h8_dtc_state *get_object(int vector) { return m_states + vector; } + inline uint32_t get_vector_address(int vector) { return 0x400 | ((vector ? vector : m_dtvecr & 0x7f) << 1); } int get_waiting_vector(); int get_waiting_writeback(); void vector_done(int vector); @@ -54,19 +54,19 @@ public: protected: static const int vector_to_enable[]; - required_device cpu; - h8_intc_device *intc; - const char *intc_tag; - int irq; - h8_dtc_state states[92]; + required_device m_cpu; + h8_intc_device *m_intc; + const char *m_intc_tag; + int m_irq; + h8_dtc_state m_states[92]; virtual void device_start() override; virtual void device_reset() override; - uint8_t dtcer[6], dtvecr; - int cur_active_vector; + uint8_t m_dtcer[6], m_dtvecr; + int m_cur_active_vector; - std::list waiting_vector, waiting_writeback; + std::vector m_waiting_vector, m_waiting_writeback; void edge(int vector); void queue(int vector); diff --git a/src/devices/cpu/h8/h8_intc.cpp b/src/devices/cpu/h8/h8_intc.cpp index f2a7b192164..196f81d9ade 100644 --- a/src/devices/cpu/h8/h8_intc.cpp +++ b/src/devices/cpu/h8/h8_intc.cpp @@ -11,53 +11,53 @@ DEFINE_DEVICE_TYPE(GT913_INTC, gt913_intc_device, "gt913_intc", "Casio GT913F in h8_intc_device::h8_intc_device(const machine_config &mconfig, const char *tag, device_t *owner, uint32_t clock) : h8_intc_device(mconfig, H8_INTC, tag, owner, clock) { - irq_vector_base = 4; - irq_vector_count = 8; - irq_vector_nmi = 3; + m_irq_vector_base = 4; + m_irq_vector_count = 8; + m_irq_vector_nmi = 3; } h8_intc_device::h8_intc_device(const machine_config &mconfig, device_type type, const char *tag, device_t *owner, uint32_t clock) : - device_t(mconfig, type, tag, owner, clock), irq_vector_base(0), irq_vector_count(0), irq_vector_nmi(0), - cpu(*this, DEVICE_SELF_OWNER), nmi_input(false), irq_input(0), ier(0), isr(0), iscr(0), icr_filter(0), ipr_filter(0) + device_t(mconfig, type, tag, owner, clock), m_irq_vector_base(0), m_irq_vector_count(0), m_irq_vector_nmi(0), + m_cpu(*this, DEVICE_SELF_OWNER), m_nmi_input(false), m_irq_input(0), m_ier(0), m_isr(0), m_iscr(0), m_icr_filter(0), m_ipr_filter(0) { } void h8_intc_device::device_start() { - memset(pending_irqs, 0, sizeof(pending_irqs)); - save_item(NAME(pending_irqs)); - save_item(NAME(irq_type)); - save_item(NAME(nmi_input)); - save_item(NAME(irq_input)); - save_item(NAME(ier)); - save_item(NAME(isr)); - save_item(NAME(iscr)); - save_item(NAME(icr_filter)); - save_item(NAME(ipr_filter)); + memset(m_pending_irqs, 0, sizeof(m_pending_irqs)); + save_item(NAME(m_pending_irqs)); + save_item(NAME(m_irq_type)); + save_item(NAME(m_nmi_input)); + save_item(NAME(m_irq_input)); + save_item(NAME(m_ier)); + save_item(NAME(m_isr)); + save_item(NAME(m_iscr)); + save_item(NAME(m_icr_filter)); + save_item(NAME(m_ipr_filter)); } void h8_intc_device::device_reset() { - memset(irq_type, 0, sizeof(irq_type)); - memset(pending_irqs, 0, sizeof(pending_irqs)); - ier = isr = irq_input = 0x00; - iscr = 0x0000; + memset(m_irq_type, 0, sizeof(m_irq_type)); + memset(m_pending_irqs, 0, sizeof(m_pending_irqs)); + m_ier = m_isr = m_irq_input = 0x00; + m_iscr = 0x0000; } int h8_intc_device::interrupt_taken(int vector) { if(0) logerror("taking internal interrupt %d\n", vector); - pending_irqs[vector >> 5] &= ~(1 << (vector & 31)); - if(vector >= irq_vector_base && vector < irq_vector_base + irq_vector_count) { - int irq = vector - irq_vector_base; - if(irq_type[irq] != IRQ_LEVEL || !(irq_input & (1 << irq))) - isr &= ~(1 << irq); + m_pending_irqs[vector >> 5] &= ~(1 << (vector & 31)); + if(vector >= m_irq_vector_base && vector < m_irq_vector_base + m_irq_vector_count) { + int irq = vector - m_irq_vector_base; + if(m_irq_type[irq] != IRQ_LEVEL || !(m_irq_input & (1 << irq))) + m_isr &= ~(1 << irq); update_irq_state(); return irq; } update_irq_state(); - if(vector == irq_vector_nmi) + if(vector == m_irq_vector_nmi) return INPUT_LINE_NMI; return 8; } @@ -66,8 +66,8 @@ void h8_intc_device::internal_interrupt(int vector) { if(0) logerror("internal interrupt %d\n", vector); - if(!cpu->trigger_dma(vector)) { - pending_irqs[vector >> 5] |= 1 << (vector & 31); + if(!m_cpu->trigger_dma(vector)) { + m_pending_irqs[vector >> 5] |= 1 << (vector & 31); update_irq_state(); } } @@ -75,56 +75,56 @@ void h8_intc_device::internal_interrupt(int vector) void h8_intc_device::set_input(int inputnum, int state) { if(inputnum == INPUT_LINE_NMI) { - if(state == ASSERT_LINE && !nmi_input) - pending_irqs[0] |= 1 << irq_vector_nmi; - nmi_input = state == ASSERT_LINE; + if(state == ASSERT_LINE && !m_nmi_input) + m_pending_irqs[0] |= 1 << m_irq_vector_nmi; + m_nmi_input = state == ASSERT_LINE; update_irq_state(); } else { bool set = false; - bool cur = irq_input & (1 << inputnum); - switch(irq_type[inputnum]) { + bool cur = m_irq_input & (1 << inputnum); + switch(m_irq_type[inputnum]) { case IRQ_LEVEL: set = state == ASSERT_LINE; break; case IRQ_EDGE: set = state == ASSERT_LINE && !cur; break; case IRQ_DUAL_EDGE: set = (state == ASSERT_LINE && !cur) || (state == CLEAR_LINE && cur); break; } if(state == ASSERT_LINE) - irq_input |= 1 << inputnum; + m_irq_input |= 1 << inputnum; else - irq_input &= ~(1 << inputnum); + m_irq_input &= ~(1 << inputnum); if(set) { - isr |= 1 << inputnum; + m_isr |= 1 << inputnum; update_irq_state(); } } } -void h8_intc_device::set_filter(int _icr_filter, int _ipr_filter) +void h8_intc_device::set_filter(int icr_filter, int ipr_filter) { - icr_filter = _icr_filter; - ipr_filter = _ipr_filter; + m_icr_filter = icr_filter; + m_ipr_filter = ipr_filter; update_irq_state(); } uint8_t h8_intc_device::ier_r() { - return ier; + return m_ier; } void h8_intc_device::ier_w(uint8_t data) { - ier = data; + m_ier = data; logerror("ier = %02x\n", data); update_irq_state(); } void h8_intc_device::check_level_irqs(bool force_update) { - logerror("irq_input=%02x\n", irq_input); + logerror("irq_input=%02x\n", m_irq_input); bool update = force_update; for(int i=0; i<8; i++) { unsigned char mask = 1 << i; - if(irq_type[i] == IRQ_LEVEL && (irq_input & mask) && !(isr & mask)) { - isr |= mask; + if(m_irq_type[i] == IRQ_LEVEL && (m_irq_input & mask) && !(m_isr & mask)) { + m_isr |= mask; update = true; } } @@ -135,25 +135,25 @@ void h8_intc_device::check_level_irqs(bool force_update) uint8_t h8_intc_device::iscr_r() { - return iscr; + return m_iscr; } void h8_intc_device::iscr_w(uint8_t data) { - iscr = data; - logerror("iscr = %02x\n", iscr); + m_iscr = data; + logerror("iscr = %02x\n", m_iscr); update_irq_types(); } void h8_intc_device::update_irq_types() { for(int i=0; i<8; i++) - switch((iscr >> (i)) & 1) { + switch((m_iscr >> (i)) & 1) { case 0: - irq_type[i] = IRQ_LEVEL; + m_irq_type[i] = IRQ_LEVEL; break; case 1: - irq_type[i] = IRQ_EDGE; + m_irq_type[i] = IRQ_EDGE; break; } check_level_irqs(); @@ -161,27 +161,26 @@ void h8_intc_device::update_irq_types() void h8_intc_device::update_irq_state() { - if (irq_vector_count > 0) - { - const unsigned mask = (1 << irq_vector_count) - 1; + if(m_irq_vector_count > 0) { + const unsigned mask = (1 << m_irq_vector_count) - 1; - pending_irqs[0] &= ~(mask << irq_vector_base); - pending_irqs[0] |= (isr & ier & mask) << irq_vector_base; + m_pending_irqs[0] &= ~(mask << m_irq_vector_base); + m_pending_irqs[0] |= (m_isr & m_ier & mask) << m_irq_vector_base; } int cur_vector = 0; int cur_level = -1; for(int i=0; i= icr_filter && ipr_pri > ipr_filter) { - int level = ipr_filter == -1 ? icr_pri : ipr_pri; + if(icr_pri >= m_icr_filter && ipr_pri > m_ipr_filter) { + int level = m_ipr_filter == -1 ? icr_pri : ipr_pri; if(level > cur_level) { cur_vector = vect; cur_level = level; @@ -189,7 +188,7 @@ void h8_intc_device::update_irq_state() } } } - cpu->set_irq(cur_vector, cur_level, cur_vector == irq_vector_nmi); + m_cpu->set_irq(cur_vector, cur_level, cur_vector == m_irq_vector_nmi); } void h8_intc_device::get_priority(int vect, int &icr_pri, int &ipr_pri) const @@ -202,9 +201,9 @@ void h8_intc_device::get_priority(int vect, int &icr_pri, int &ipr_pri) const gt913_intc_device::gt913_intc_device(const machine_config &mconfig, const char *tag, device_t *owner, uint32_t clock) : gt913_intc_device(mconfig, GT913_INTC, tag, owner, clock) { - irq_vector_base = 4; - irq_vector_count = 1; - irq_vector_nmi = 3; + m_irq_vector_base = 4; + m_irq_vector_count = 1; + m_irq_vector_nmi = 3; } gt913_intc_device::gt913_intc_device(const machine_config &mconfig, device_type type, const char *tag, device_t *owner, uint32_t clock) : @@ -216,12 +215,12 @@ void gt913_intc_device::device_reset() { h8_intc_device::device_reset(); - ier = 0x01; + m_ier = 0x01; } void gt913_intc_device::clear_interrupt(int vector) { - pending_irqs[vector >> 5] &= ~(1 << (vector & 31)); + m_pending_irqs[vector >> 5] &= ~(1 << (vector & 31)); update_irq_state(); } @@ -229,9 +228,9 @@ void gt913_intc_device::clear_interrupt(int vector) h8h_intc_device::h8h_intc_device(const machine_config &mconfig, const char *tag, device_t *owner, uint32_t clock) : h8h_intc_device(mconfig, H8H_INTC, tag, owner, clock) { - irq_vector_base = 12; - irq_vector_count = 8; - irq_vector_nmi = 7; + m_irq_vector_base = 12; + m_irq_vector_count = 8; + m_irq_vector_nmi = 7; } h8h_intc_device::h8h_intc_device(const machine_config &mconfig, device_type type, const char *tag, device_t *owner, uint32_t clock) : @@ -242,35 +241,35 @@ h8h_intc_device::h8h_intc_device(const machine_config &mconfig, device_type type void h8h_intc_device::device_start() { h8_intc_device::device_start(); - save_item(NAME(icr)); + save_item(NAME(m_icr)); } void h8h_intc_device::device_reset() { h8_intc_device::device_reset(); - icr = 0x000000; + m_icr = 0x000000; } uint8_t h8h_intc_device::isr_r() { - return isr; + return m_isr; } void h8h_intc_device::isr_w(uint8_t data) { - isr &= data; // edge/level - logerror("isr = %02x / %02x\n", data, isr); + m_isr &= data; // edge/level + logerror("isr = %02x / %02x\n", data, m_isr); check_level_irqs(true); } uint8_t h8h_intc_device::icr_r(offs_t offset) { - return icr >> (8*offset); + return m_icr >> (8*offset); } void h8h_intc_device::icr_w(offs_t offset, uint8_t data) { - icr = (icr & (0xff << (8*offset))) | (data << (8*offset)); + m_icr = (m_icr & (0xff << (8*offset))) | (data << (8*offset)); logerror("icr %d = %02x\n", offset, data); } @@ -286,40 +285,40 @@ void h8h_intc_device::icrc_w(uint8_t data) uint8_t h8h_intc_device::iscrh_r() { - return iscr >> 8; + return m_iscr >> 8; } void h8h_intc_device::iscrh_w(uint8_t data) { - iscr = (iscr & 0x00ff) | (data << 8); - logerror("iscr = %04x\n", iscr); + m_iscr = (m_iscr & 0x00ff) | (data << 8); + logerror("iscr = %04x\n", m_iscr); update_irq_types(); } uint8_t h8h_intc_device::iscrl_r() { - return iscr; + return m_iscr; } void h8h_intc_device::iscrl_w(uint8_t data) { - iscr = (iscr & 0xff00) | data; - logerror("iscr = %04x\n", iscr); + m_iscr = (m_iscr & 0xff00) | data; + logerror("iscr = %04x\n", m_iscr); update_irq_types(); } void h8h_intc_device::update_irq_types() { for(int i=0; i<8; i++) - switch((iscr >> (2*i)) & 3) { + switch((m_iscr >> (2*i)) & 3) { case 0: - irq_type[i] = IRQ_LEVEL; + m_irq_type[i] = IRQ_LEVEL; break; case 1: case 2: - irq_type[i] = IRQ_EDGE; + m_irq_type[i] = IRQ_EDGE; break; case 3: - irq_type[i] = IRQ_DUAL_EDGE; + m_irq_type[i] = IRQ_DUAL_EDGE; break; } check_level_irqs(); @@ -350,31 +349,31 @@ void h8h_intc_device::get_priority(int vect, int &icr_pri, int &ipr_pri) const return; } - icr_pri = (icr >> (slot ^ 7)) & 1; + icr_pri = (m_icr >> (slot ^ 7)) & 1; } h8s_intc_device::h8s_intc_device(const machine_config &mconfig, const char *tag, device_t *owner, uint32_t clock) : h8h_intc_device(mconfig, H8S_INTC, tag, owner, clock) { - irq_vector_base = 16; - irq_vector_count = 8; - irq_vector_nmi = 7; + m_irq_vector_base = 16; + m_irq_vector_count = 8; + m_irq_vector_nmi = 7; } void h8s_intc_device::device_reset() { h8h_intc_device::device_reset(); - memset(ipr, 0x77, sizeof(ipr)); + memset(m_ipr, 0x77, sizeof(m_ipr)); } uint8_t h8s_intc_device::ipr_r(offs_t offset) { - return ipr[offset]; + return m_ipr[offset]; } void h8s_intc_device::ipr_w(offs_t offset, uint8_t data) { - ipr[offset] = data; + m_ipr[offset] = data; logerror("ipr %d = %02x\n", offset, data); } @@ -417,6 +416,6 @@ void h8s_intc_device::get_priority(int vect, int &icr_pri, int &ipr_pri) const return; } - icr_pri = (icr >> (slot ^ 7)) & 1; - ipr_pri = (ipr[slot >> 1] >> (slot & 1 ? 0 : 4)) & 7; + icr_pri = (m_icr >> (slot ^ 7)) & 1; + ipr_pri = (m_ipr[slot >> 1] >> (slot & 1 ? 0 : 4)) & 7; } diff --git a/src/devices/cpu/h8/h8_intc.h b/src/devices/cpu/h8/h8_intc.h index 43569dc3b9b..b43fee35345 100644 --- a/src/devices/cpu/h8/h8_intc.h +++ b/src/devices/cpu/h8/h8_intc.h @@ -35,20 +35,20 @@ protected: enum { IRQ_LEVEL, IRQ_EDGE, IRQ_DUAL_EDGE }; enum { MAX_VECTORS = 256 }; - int irq_vector_base; - int irq_vector_count; - int irq_vector_nmi; + int m_irq_vector_base; + int m_irq_vector_count; + int m_irq_vector_nmi; - required_device cpu; + required_device m_cpu; - uint32_t pending_irqs[MAX_VECTORS/32]; - int irq_type[8]; - bool nmi_input; - uint8_t irq_input; - uint8_t ier; - uint8_t isr; - uint16_t iscr; - int icr_filter, ipr_filter; + uint32_t m_pending_irqs[MAX_VECTORS/32]; + int m_irq_type[8]; + bool m_nmi_input; + uint8_t m_irq_input; + uint8_t m_ier; + uint8_t m_isr; + uint16_t m_iscr; + int m_icr_filter, m_ipr_filter; h8_intc_device(const machine_config &mconfig, device_type type, const char *tag, device_t *owner, uint32_t clock); @@ -90,7 +90,7 @@ public: protected: static const int vector_to_slot[]; - uint32_t icr; + uint32_t m_icr; h8h_intc_device(const machine_config &mconfig, device_type type, const char *tag, device_t *owner, uint32_t clock); @@ -111,7 +111,7 @@ public: void iprk_w(uint8_t data); private: static const int vector_to_slot[]; - uint8_t ipr[11]; + uint8_t m_ipr[11]; virtual void get_priority(int vect, int &icr_pri, int &ipr_pri) const override; virtual void device_reset() override; diff --git a/src/devices/cpu/h8/h8_port.cpp b/src/devices/cpu/h8/h8_port.cpp index e366e0d49a5..09a86fe4546 100644 --- a/src/devices/cpu/h8/h8_port.cpp +++ b/src/devices/cpu/h8/h8_port.cpp @@ -7,47 +7,47 @@ DEFINE_DEVICE_TYPE(H8_PORT, h8_port_device, "h8_digital_port", "H8 digital port" h8_port_device::h8_port_device(const machine_config &mconfig, const char *tag, device_t *owner, uint32_t clock) : device_t(mconfig, H8_PORT, tag, owner, clock), - cpu(*this, DEVICE_SELF_OWNER), io(nullptr), address(0), default_ddr(0), ddr(0), pcr(0), odr(0), mask(0), dr(0), last_output(0) + m_cpu(*this, DEVICE_SELF_OWNER), m_io(nullptr), m_address(0), m_default_ddr(0), m_ddr(0), m_pcr(0), m_odr(0), m_mask(0), m_dr(0), m_last_output(0) { } -void h8_port_device::set_info(int _address, uint8_t _default_ddr, uint8_t _mask) +void h8_port_device::set_info(int address, uint8_t default_ddr, uint8_t mask) { - address = _address; - default_ddr = _default_ddr; - mask = _mask; + m_address = address; + m_default_ddr = default_ddr; + m_mask = mask; } void h8_port_device::ddr_w(uint8_t data) { // logerror("ddr_w %02x\n", data); - ddr = data; + m_ddr = data; update_output(); } uint8_t h8_port_device::ddr_r() { - return ddr; + return m_ddr; } void h8_port_device::dr_w(uint8_t data) { // logerror("dr_w %02x\n", data); - dr = data; + m_dr = data; update_output(); } uint8_t h8_port_device::dr_r() { // logerror("dr_r %02x\n", (dr | mask) & 0xff); - return dr | mask; + return m_dr | m_mask; } uint8_t h8_port_device::port_r() { - uint8_t res = mask | (dr & ddr); - if((ddr & ~mask) != uint8_t(~mask)) - res |= io->read_word(address) & ~ddr; + uint8_t res = m_mask | (m_dr & m_ddr); + if((m_ddr & ~m_mask) != uint8_t(~m_mask)) + res |= m_io->read_word(m_address) & ~m_ddr; // logerror("port_r %02x (%02x %02x)\n", res, ddr & ~mask, uint8_t(~mask)); return res; @@ -56,52 +56,52 @@ uint8_t h8_port_device::port_r() void h8_port_device::pcr_w(uint8_t data) { logerror("pcr_w %02x\n", data); - pcr = data; + m_pcr = data; } uint8_t h8_port_device::pcr_r() { - logerror("dr_r %02x\n", (pcr | mask) & 0xff); - return pcr | mask; + logerror("dr_r %02x\n", (m_pcr | m_mask) & 0xff); + return m_pcr | m_mask; } void h8_port_device::odr_w(uint8_t data) { logerror("odr_w %02x\n", data); - odr = data; + m_odr = data; } uint8_t h8_port_device::odr_r() { - logerror("odr_r %02x\n", (odr | mask) & 0xff); - return odr | ~mask; + logerror("odr_r %02x\n", (m_odr | ~m_mask) & 0xff); + return m_odr | ~m_mask; } void h8_port_device::update_output() { - uint8_t res = dr & ddr & ~mask; - if(res != last_output) { - last_output = res; - io->write_word(address, res); + uint8_t res = m_dr & m_ddr & ~m_mask; + if(res != m_last_output) { + m_last_output = res; + m_io->write_word(m_address, res); } } void h8_port_device::device_start() { - io = &cpu->space(AS_IO); - save_item(NAME(ddr)); - save_item(NAME(dr)); - save_item(NAME(pcr)); - save_item(NAME(odr)); - save_item(NAME(last_output)); - last_output = 0; + m_io = &m_cpu->space(AS_IO); + save_item(NAME(m_ddr)); + save_item(NAME(m_dr)); + save_item(NAME(m_pcr)); + save_item(NAME(m_odr)); + save_item(NAME(m_last_output)); + m_last_output = 0; } void h8_port_device::device_reset() { - dr = 0; - ddr = default_ddr; - pcr = 0; - odr = 0; + m_dr = 0; + m_ddr = m_default_ddr; + m_pcr = 0; + m_odr = 0; update_output(); } diff --git a/src/devices/cpu/h8/h8_port.h b/src/devices/cpu/h8/h8_port.h index 6c60b0c7621..3c38f844f24 100644 --- a/src/devices/cpu/h8/h8_port.h +++ b/src/devices/cpu/h8/h8_port.h @@ -38,14 +38,14 @@ public: uint8_t odr_r(); protected: - required_device cpu; - address_space *io; - - int address; - uint8_t default_ddr, ddr, pcr, odr; - uint8_t mask; - uint8_t dr; - uint8_t last_output; + required_device m_cpu; + address_space *m_io; + + int m_address; + uint8_t m_default_ddr, m_ddr, m_pcr, m_odr; + uint8_t m_mask; + uint8_t m_dr; + uint8_t m_last_output; virtual void device_start() override; virtual void device_reset() override; diff --git a/src/devices/cpu/h8/h8_sci.cpp b/src/devices/cpu/h8/h8_sci.cpp index 0848b64ba40..049795e40e1 100644 --- a/src/devices/cpu/h8/h8_sci.cpp +++ b/src/devices/cpu/h8/h8_sci.cpp @@ -17,32 +17,32 @@ const char *const h8_sci_device::state_names[] = { "idle", "start", "bit", "pari h8_sci_device::h8_sci_device(const machine_config &mconfig, const char *tag, device_t *owner, uint32_t clock) : device_t(mconfig, H8_SCI, tag, owner, clock), - cpu(*this, DEVICE_SELF_OWNER), - tx_cb(*this), - clk_cb(*this), intc(nullptr), intc_tag(nullptr), external_to_internal_ratio(0), internal_to_external_ratio(0), sync_timer(nullptr), eri_int(0), rxi_int(0), txi_int(0), tei_int(0), - tx_state(0), rx_state(0), tx_bit(0), rx_bit(0), clock_state(0), tx_parity(0), rx_parity(0), ext_clock_counter(0), clock_mode(clock_mode_t::INTERNAL_ASYNC), clock_value(false), ext_clock_value(false), rx_value(false), - rdr(0), tdr(0), smr(0), scr(0), ssr(0), brr(0), rsr(0), tsr(0), clock_base(0), divider(0) + m_cpu(*this, DEVICE_SELF_OWNER), + m_tx_cb(*this), + m_clk_cb(*this), m_intc(nullptr), m_intc_tag(nullptr), m_external_to_internal_ratio(0), m_internal_to_external_ratio(0), m_sync_timer(nullptr), m_eri_int(0), m_rxi_int(0), m_txi_int(0), m_tei_int(0), + m_tx_state(0), m_rx_state(0), m_tx_bit(0), m_rx_bit(0), m_clock_state(0), m_tx_parity(0), m_rx_parity(0), m_ext_clock_counter(0), m_clock_mode(clock_mode_t::INTERNAL_ASYNC), m_clock_value(false), m_ext_clock_value(false), m_rx_value(false), + m_rdr(0), m_tdr(0), m_smr(0), m_scr(0), m_ssr(0), m_brr(0), m_rsr(0), m_tsr(0), m_clock_base(0), m_divider(0) { - external_clock_period = attotime::never; + m_external_clock_period = attotime::never; } -void h8_sci_device::set_info(const char *_intc_tag, int eri, int rxi, int txi, int tei) +void h8_sci_device::set_info(const char *intc_tag, int eri, int rxi, int txi, int tei) { - intc_tag = _intc_tag; - eri_int = eri; - rxi_int = rxi; - txi_int = txi; - tei_int = tei; + m_intc_tag = intc_tag; + m_eri_int = eri; + m_rxi_int = rxi; + m_txi_int = txi; + m_tei_int = tei; } void h8_sci_device::set_external_clock_period(const attotime &period) { - external_clock_period = period; + m_external_clock_period = period; } void h8_sci_device::smr_w(uint8_t data) { - smr = data; + m_smr = data; if(V>=2) logerror("smr_w %02x %s %c%c%c%s /%d (%06x)\n", data, data & SMR_CA ? "sync" : "async", data & SMR_CHR ? '7' : '8', @@ -50,37 +50,37 @@ void h8_sci_device::smr_w(uint8_t data) data & SMR_STOP ? '2' : '1', data & SMR_MP ? " mp" : "", 1 << 2*(data & SMR_CKS), - cpu->pc()); + m_cpu->pc()); clock_update(); } uint8_t h8_sci_device::smr_r() { - if(V>=2) logerror("smr_r %02x (%06x)\n", smr, cpu->pc()); - return smr; + if(V>=2) logerror("smr_r %02x (%06x)\n", m_smr, m_cpu->pc()); + return m_smr; } void h8_sci_device::brr_w(uint8_t data) { - brr = data; - if(V>=2) logerror("brr_w %02x (%06x)\n", data, cpu->pc()); + m_brr = data; + if(V>=2) logerror("brr_w %02x (%06x)\n", data, m_cpu->pc()); clock_update(); } uint8_t h8_sci_device::brr_r() { - if(V>=2) logerror("brr_r %02x (%06x)\n", brr, cpu->pc()); - return brr; + if(V>=2) logerror("brr_r %02x (%06x)\n", m_brr, m_cpu->pc()); + return m_brr; } bool h8_sci_device::is_sync_start() const { - return (smr & SMR_CA) && ((scr & (SCR_TE|SCR_RE)) == (SCR_TE|SCR_RE)); + return (m_smr & SMR_CA) && ((m_scr & (SCR_TE|SCR_RE)) == (SCR_TE|SCR_RE)); } bool h8_sci_device::has_recv_error() const { - return ssr & (SSR_ORER|SSR_PER|SSR_FER); + return m_ssr & (SSR_ORER|SSR_PER|SSR_FER); } void h8_sci_device::scr_w(uint8_t data) @@ -93,92 +93,92 @@ void h8_sci_device::scr_w(uint8_t data) data & SCR_MPIE ? " mpi" : "", data & SCR_TEIE ? " tei" : "", data & SCR_CKE, - cpu->pc()); + m_cpu->pc()); - uint8_t delta = scr ^ data; - scr = data; + uint8_t delta = m_scr ^ data; + m_scr = data; clock_update(); - if((delta & SCR_RE) && !(scr & SCR_RE)) { - rx_state = ST_IDLE; + if((delta & SCR_RE) && !(m_scr & SCR_RE)) { + m_rx_state = ST_IDLE; clock_stop(CLK_RX); } - if((delta & SCR_RE) && (scr & SCR_RE) && rx_state == ST_IDLE && !has_recv_error() && !is_sync_start()) + if((delta & SCR_RE) && (m_scr & SCR_RE) && m_rx_state == ST_IDLE && !has_recv_error() && !is_sync_start()) rx_start(); - if((delta & SCR_TIE) && (scr & SCR_TIE) && (ssr & SSR_TDRE)) - intc->internal_interrupt(txi_int); - if((delta & SCR_TEIE) && (scr & SCR_TEIE) && (ssr & SSR_TEND)) - intc->internal_interrupt(tei_int); - if((delta & SCR_RIE) && (scr & SCR_RIE) && (ssr & SSR_RDRF)) - intc->internal_interrupt(rxi_int); - if((delta & SCR_RIE) && (scr & SCR_RIE) && has_recv_error()) - intc->internal_interrupt(eri_int); + if((delta & SCR_TIE) && (m_scr & SCR_TIE) && (m_ssr & SSR_TDRE)) + m_intc->internal_interrupt(m_txi_int); + if((delta & SCR_TEIE) && (m_scr & SCR_TEIE) && (m_ssr & SSR_TEND)) + m_intc->internal_interrupt(m_tei_int); + if((delta & SCR_RIE) && (m_scr & SCR_RIE) && (m_ssr & SSR_RDRF)) + m_intc->internal_interrupt(m_rxi_int); + if((delta & SCR_RIE) && (m_scr & SCR_RIE) && has_recv_error()) + m_intc->internal_interrupt(m_eri_int); } uint8_t h8_sci_device::scr_r() { - if(V>=2) logerror("scr_r %02x (%06x)\n", scr, cpu->pc()); - return scr; + if(V>=2) logerror("scr_r %02x (%06x)\n", m_scr, m_cpu->pc()); + return m_scr; } void h8_sci_device::tdr_w(uint8_t data) { - if(V>=2) logerror("tdr_w %02x (%06x)\n", data, cpu->pc()); - tdr = data; - if(cpu->access_is_dma()) { - ssr &= ~SSR_TDRE; - if(tx_state == ST_IDLE) + if(V>=2) logerror("tdr_w %02x (%06x)\n", data, m_cpu->pc()); + m_tdr = data; + if(m_cpu->access_is_dma()) { + m_ssr &= ~SSR_TDRE; + if(m_tx_state == ST_IDLE) tx_start(); } } uint8_t h8_sci_device::tdr_r() { - if(V>=2) logerror("tdr_r %02x (%06x)\n", tdr, cpu->pc()); - return tdr; + if(V>=2) logerror("tdr_r %02x (%06x)\n", m_tdr, m_cpu->pc()); + return m_tdr; } void h8_sci_device::ssr_w(uint8_t data) { - if(!(scr & SCR_TE)) { + if(!(m_scr & SCR_TE)) { data |= SSR_TDRE; - ssr |= SSR_TDRE; + m_ssr |= SSR_TDRE; } - if((ssr & SSR_TDRE) && !(data & SSR_TDRE)) - ssr &= ~SSR_TEND; - ssr = ((ssr & ~SSR_MPBT) | (data & SSR_MPBT)) & (data | (SSR_TEND|SSR_MPB|SSR_MPBT)); - if(V>=2) logerror("ssr_w %02x -> %02x (%06x)\n", data, ssr, cpu->pc()); + if((m_ssr & SSR_TDRE) && !(data & SSR_TDRE)) + m_ssr &= ~SSR_TEND; + m_ssr = ((m_ssr & ~SSR_MPBT) | (data & SSR_MPBT)) & (data | (SSR_TEND|SSR_MPB|SSR_MPBT)); + if(V>=2) logerror("ssr_w %02x -> %02x (%06x)\n", data, m_ssr, m_cpu->pc()); - if(tx_state == ST_IDLE && !(ssr & SSR_TDRE)) + if(m_tx_state == ST_IDLE && !(m_ssr & SSR_TDRE)) tx_start(); - if((scr & SCR_RE) && rx_state == ST_IDLE && !has_recv_error() && !is_sync_start()) + if((m_scr & SCR_RE) && m_rx_state == ST_IDLE && !has_recv_error() && !is_sync_start()) rx_start(); } uint8_t h8_sci_device::ssr_r() { - if(V>=3) logerror("ssr_r %02x (%06x)\n", ssr, cpu->pc()); - return ssr; + if(V>=3) logerror("ssr_r %02x (%06x)\n", m_ssr, m_cpu->pc()); + return m_ssr; } uint8_t h8_sci_device::rdr_r() { - if(V>=2) logerror("rdr_r %02x (%06x)\n", rdr, cpu->pc()); - if(cpu->access_is_dma()) - ssr &= ~SSR_RDRF; - return rdr; + if(V>=2) logerror("rdr_r %02x (%06x)\n", m_rdr, m_cpu->pc()); + if(m_cpu->access_is_dma()) + m_ssr &= ~SSR_RDRF; + return m_rdr; } void h8_sci_device::scmr_w(uint8_t data) { - if(V>=2) logerror("scmr_w %02x (%06x)\n", data, cpu->pc()); + if(V>=2) logerror("scmr_w %02x (%06x)\n", data, m_cpu->pc()); } uint8_t h8_sci_device::scmr_r() { - if(V>=2) logerror("scmr_r (%06x)\n", cpu->pc()); + if(V>=2) logerror("scmr_r (%06x)\n", m_cpu->pc()); return 0x00; } @@ -187,123 +187,123 @@ void h8_sci_device::clock_update() // Sync: Divider must be the time of a half-period (both edges are used, datarate*2) // Async: Divider must be the time of one period (only raising edge used, datarate*16) - divider = 2 << (2*(smr & SMR_CKS)); - divider *= brr+1; + m_divider = 2 << (2*(m_smr & SMR_CKS)); + m_divider *= m_brr+1; - if(smr & SMR_CA) { - if(scr & SCR_CKE1) - clock_mode = clock_mode_t::EXTERNAL_SYNC; + if(m_smr & SMR_CA) { + if(m_scr & SCR_CKE1) + m_clock_mode = clock_mode_t::EXTERNAL_SYNC; else - clock_mode = clock_mode_t::INTERNAL_SYNC_OUT; + m_clock_mode = clock_mode_t::INTERNAL_SYNC_OUT; } else { - if(scr & SCR_CKE1) - clock_mode = clock_mode_t::EXTERNAL_ASYNC; - else if(scr & SCR_CKE0) - clock_mode = clock_mode_t::INTERNAL_ASYNC_OUT; + if(m_scr & SCR_CKE1) + m_clock_mode = clock_mode_t::EXTERNAL_ASYNC; + else if(m_scr & SCR_CKE0) + m_clock_mode = clock_mode_t::INTERNAL_ASYNC_OUT; else - clock_mode = clock_mode_t::INTERNAL_ASYNC; + m_clock_mode = clock_mode_t::INTERNAL_ASYNC; } - if(clock_mode == clock_mode_t::EXTERNAL_ASYNC && !external_clock_period.is_never()) - clock_mode = clock_mode_t::EXTERNAL_RATE_ASYNC; - if(clock_mode == clock_mode_t::EXTERNAL_SYNC && !external_clock_period.is_never()) - clock_mode = clock_mode_t::EXTERNAL_RATE_SYNC; + if(m_clock_mode == clock_mode_t::EXTERNAL_ASYNC && !m_external_clock_period.is_never()) + m_clock_mode = clock_mode_t::EXTERNAL_RATE_ASYNC; + if(m_clock_mode == clock_mode_t::EXTERNAL_SYNC && !m_external_clock_period.is_never()) + m_clock_mode = clock_mode_t::EXTERNAL_RATE_SYNC; if(V>=1) { std::string new_message; - switch(clock_mode) { + switch(m_clock_mode) { case clock_mode_t::INTERNAL_ASYNC: - new_message = util::string_format("clock internal at %d Hz, async, bitrate %d bps\n", int(cpu->clock() / divider), int(cpu->clock() / (divider*16))); + new_message = util::string_format("clock internal at %d Hz, async, bitrate %d bps\n", int(m_cpu->clock() / m_divider), int(m_cpu->clock() / (m_divider*16))); break; case clock_mode_t::INTERNAL_ASYNC_OUT: - new_message = util::string_format("clock internal at %d Hz, async, bitrate %d bps, output\n", int(cpu->clock() / divider), int(cpu->clock() / (divider*16))); + new_message = util::string_format("clock internal at %d Hz, async, bitrate %d bps, output\n", int(m_cpu->clock() / m_divider), int(m_cpu->clock() / (m_divider*16))); break; case clock_mode_t::EXTERNAL_ASYNC: new_message = "clock external, async\n"; break; case clock_mode_t::EXTERNAL_RATE_ASYNC: - new_message = util::string_format("clock external at %d Hz, async, bitrate %d bps\n", int(cpu->clock()*internal_to_external_ratio), int(cpu->clock()*internal_to_external_ratio/16)); + new_message = util::string_format("clock external at %d Hz, async, bitrate %d bps\n", int(m_cpu->clock()*m_internal_to_external_ratio), int(m_cpu->clock()*m_internal_to_external_ratio/16)); break; case clock_mode_t::INTERNAL_SYNC_OUT: - new_message = util::string_format("clock internal at %d Hz, sync, output\n", int(cpu->clock() / (divider*2))); + new_message = util::string_format("clock internal at %d Hz, sync, output\n", int(m_cpu->clock() / (m_divider*2))); break; case clock_mode_t::EXTERNAL_SYNC: new_message = "clock external, sync\n"; break; case clock_mode_t::EXTERNAL_RATE_SYNC: - new_message = util::string_format("clock external at %d Hz, sync\n", int(cpu->clock()*internal_to_external_ratio)); + new_message = util::string_format("clock external at %d Hz, sync\n", int(m_cpu->clock()*m_internal_to_external_ratio)); break; } - if(new_message != last_clock_message) { + if(new_message != m_last_clock_message) { logerror(new_message); - last_clock_message = std::move(new_message); + m_last_clock_message = std::move(new_message); } } } void h8_sci_device::device_start() { - tx_cb.resolve_safe(); - clk_cb.resolve_safe(); + m_tx_cb.resolve_safe(); + m_clk_cb.resolve_safe(); - sync_timer = timer_alloc(FUNC(h8_sci_device::sync_tick), this); + m_sync_timer = timer_alloc(FUNC(h8_sci_device::sync_tick), this); - if(external_clock_period.is_never()) { - internal_to_external_ratio = 0; - external_to_internal_ratio = 0; + if(m_external_clock_period.is_never()) { + m_internal_to_external_ratio = 0; + m_external_to_internal_ratio = 0; } else { - external_to_internal_ratio = (external_clock_period*cpu->clock()).as_double(); - internal_to_external_ratio = 1/external_to_internal_ratio; + m_external_to_internal_ratio = (m_external_clock_period*m_cpu->clock()).as_double(); + m_internal_to_external_ratio = 1/m_external_to_internal_ratio; } - intc = siblingdevice(intc_tag); - save_item(NAME(rdr)); - save_item(NAME(tdr)); - save_item(NAME(smr)); - save_item(NAME(scr)); - save_item(NAME(ssr)); - save_item(NAME(brr)); - save_item(NAME(rsr)); - save_item(NAME(tsr)); - save_item(NAME(rx_bit)); - save_item(NAME(tx_bit)); - save_item(NAME(rx_state)); - save_item(NAME(tx_state)); - save_item(NAME(tx_parity)); - save_item(NAME(clock_state)); - save_item(NAME(clock_value)); - save_item(NAME(clock_base)); - save_item(NAME(divider)); - save_item(NAME(ext_clock_value)); - save_item(NAME(ext_clock_counter)); - save_item(NAME(cur_sync_time)); + m_intc = siblingdevice(m_intc_tag); + save_item(NAME(m_rdr)); + save_item(NAME(m_tdr)); + save_item(NAME(m_smr)); + save_item(NAME(m_scr)); + save_item(NAME(m_ssr)); + save_item(NAME(m_brr)); + save_item(NAME(m_rsr)); + save_item(NAME(m_tsr)); + save_item(NAME(m_rx_bit)); + save_item(NAME(m_tx_bit)); + save_item(NAME(m_rx_state)); + save_item(NAME(m_tx_state)); + save_item(NAME(m_tx_parity)); + save_item(NAME(m_clock_state)); + save_item(NAME(m_clock_value)); + save_item(NAME(m_clock_base)); + save_item(NAME(m_divider)); + save_item(NAME(m_ext_clock_value)); + save_item(NAME(m_ext_clock_counter)); + save_item(NAME(m_cur_sync_time)); } void h8_sci_device::device_reset() { - rdr = 0x00; - tdr = 0xff; - smr = 0x00; - scr = 0x00; - ssr = 0x84; - brr = 0xff; - rsr = 0x00; - tsr = 0xff; - rx_bit = 0; - tx_bit = 0; - tx_state = ST_IDLE; - rx_state = ST_IDLE; - clock_state = 0; - clock_mode = clock_mode_t::INTERNAL_ASYNC; - clock_base = 0; + m_rdr = 0x00; + m_tdr = 0xff; + m_smr = 0x00; + m_scr = 0x00; + m_ssr = 0x84; + m_brr = 0xff; + m_rsr = 0x00; + m_tsr = 0xff; + m_rx_bit = 0; + m_tx_bit = 0; + m_tx_state = ST_IDLE; + m_rx_state = ST_IDLE; + m_clock_state = 0; + m_clock_mode = clock_mode_t::INTERNAL_ASYNC; + m_clock_base = 0; clock_update(); - clock_value = true; - ext_clock_value = true; - ext_clock_counter = 0; - rx_value = true; - clk_cb(clock_value); - tx_cb(1); - cur_sync_time = attotime::never; + m_clock_value = true; + m_ext_clock_value = true; + m_ext_clock_counter = 0; + m_rx_value = true; + m_clk_cb(m_clock_value); + m_tx_cb(1); + m_cur_sync_time = attotime::never; } void h8_sci_device::device_post_load() @@ -319,34 +319,34 @@ TIMER_CALLBACK_MEMBER(h8_sci_device::sync_tick) WRITE_LINE_MEMBER(h8_sci_device::rx_w) { - rx_value = state; + m_rx_value = state; if(V>=2) logerror("rx=%d\n", state); - if(!rx_value && !(clock_state & CLK_RX) && rx_state != ST_IDLE) + if(!m_rx_value && !(m_clock_state & CLK_RX) && m_rx_state != ST_IDLE) clock_start(CLK_RX); } WRITE_LINE_MEMBER(h8_sci_device::clk_w) { - if(ext_clock_value != state) { - ext_clock_value = state; - if(clock_state) { - switch(clock_mode) { + if(m_ext_clock_value != state) { + m_ext_clock_value = state; + if(m_clock_state) { + switch(m_clock_mode) { case clock_mode_t::EXTERNAL_ASYNC: - if(ext_clock_value) { - ext_clock_counter = (ext_clock_counter+1) & 15; + if(m_ext_clock_value) { + m_ext_clock_counter = (m_ext_clock_counter+1) & 15; - if((clock_state & CLK_TX) && ext_clock_counter == 0) + if((m_clock_state & CLK_TX) && m_ext_clock_counter == 0) tx_dropped_edge(); - if((clock_state & CLK_RX) && ext_clock_counter == 8) + if((m_clock_state & CLK_RX) && m_ext_clock_counter == 8) rx_raised_edge(); } break; case clock_mode_t::EXTERNAL_SYNC: - if((!ext_clock_value) && (clock_state & CLK_TX)) + if((!m_ext_clock_value) && (m_clock_state & CLK_TX)) tx_dropped_edge(); - else if(ext_clock_value && (clock_state & CLK_RX)) + else if(m_ext_clock_value && (m_clock_state & CLK_RX)) rx_raised_edge(); break; default: @@ -360,111 +360,111 @@ WRITE_LINE_MEMBER(h8_sci_device::clk_w) uint64_t h8_sci_device::internal_update(uint64_t current_time) { uint64_t event = 0; - switch(clock_mode) { + switch(m_clock_mode) { case clock_mode_t::INTERNAL_SYNC_OUT: - if(clock_state || !clock_value) { - uint64_t fp = divider*2; - if(current_time >= clock_base) { - uint64_t delta = current_time - clock_base; + if(m_clock_state || !m_clock_value) { + uint64_t fp = m_divider*2; + if(current_time >= m_clock_base) { + uint64_t delta = current_time - m_clock_base; if(delta >= fp) { delta -= fp; - clock_base += fp; + m_clock_base += fp; } assert(delta < fp); - bool new_clock = delta >= divider; - if(new_clock != clock_value) { + bool new_clock = delta >= m_divider; + if(new_clock != m_clock_value) { machine().scheduler().synchronize(); - if((!new_clock) && (clock_state & CLK_TX)) + if((!new_clock) && (m_clock_state & CLK_TX)) tx_dropped_edge(); - else if(new_clock && (clock_state & CLK_RX)) + else if(new_clock && (m_clock_state & CLK_RX)) rx_raised_edge(); - clock_value = new_clock; - if(clock_state || clock_value) - clk_cb(clock_value); + m_clock_value = new_clock; + if(m_clock_state || m_clock_value) + m_clk_cb(m_clock_value); } } - event = clock_base + (clock_value ? fp : divider); + event = m_clock_base + (m_clock_value ? fp : m_divider); } break; case clock_mode_t::INTERNAL_ASYNC: case clock_mode_t::INTERNAL_ASYNC_OUT: - if(clock_state || !clock_value) { - uint64_t fp = divider*16; - if(current_time >= clock_base) { - uint64_t delta = current_time - clock_base; + if(m_clock_state || !m_clock_value) { + uint64_t fp = m_divider*16; + if(current_time >= m_clock_base) { + uint64_t delta = current_time - m_clock_base; if(delta >= fp) { delta -= fp; - clock_base += fp; + m_clock_base += fp; } assert(delta < fp); - bool new_clock = delta >= divider*8; - if(new_clock != clock_value) { + bool new_clock = delta >= m_divider*8; + if(new_clock != m_clock_value) { machine().scheduler().synchronize(); - if((!new_clock) && (clock_state & CLK_TX)) + if((!new_clock) && (m_clock_state & CLK_TX)) tx_dropped_edge(); - else if(new_clock && (clock_state & CLK_RX)) + else if(new_clock && (m_clock_state & CLK_RX)) rx_raised_edge(); - clock_value = new_clock; - if(clock_mode == clock_mode_t::INTERNAL_ASYNC_OUT && (clock_state || !clock_value)) - clk_cb(clock_value); + m_clock_value = new_clock; + if(m_clock_mode == clock_mode_t::INTERNAL_ASYNC_OUT && (m_clock_state || !m_clock_value)) + m_clk_cb(m_clock_value); } } - event = clock_base + (clock_value ? fp : divider*8); + event = m_clock_base + (m_clock_value ? fp : m_divider*8); } break; case clock_mode_t::EXTERNAL_RATE_SYNC: - if(clock_state || !clock_value) { - uint64_t ctime = uint64_t(current_time*internal_to_external_ratio*2); - if(ctime >= clock_base) { - uint64_t delta = ctime - clock_base; - clock_base += delta & ~1; + if(m_clock_state || !m_clock_value) { + uint64_t ctime = uint64_t(current_time*m_internal_to_external_ratio*2); + if(ctime >= m_clock_base) { + uint64_t delta = ctime - m_clock_base; + m_clock_base += delta & ~1; delta &= 1; bool new_clock = delta >= 1; - if(new_clock != clock_value) { + if(new_clock != m_clock_value) { machine().scheduler().synchronize(); - if((!new_clock) && (clock_state & CLK_TX)) + if((!new_clock) && (m_clock_state & CLK_TX)) tx_dropped_edge(); - else if(new_clock && (clock_state & CLK_RX)) + else if(new_clock && (m_clock_state & CLK_RX)) rx_raised_edge(); - clock_value = new_clock; + m_clock_value = new_clock; } } - event = uint64_t((clock_base + (clock_value ? 2 : 1))*external_to_internal_ratio)+1; + event = uint64_t((m_clock_base + (m_clock_value ? 2 : 1))*m_external_to_internal_ratio)+1; } break; case clock_mode_t::EXTERNAL_RATE_ASYNC: - if(clock_state || !clock_value) { - uint64_t ctime = uint64_t(current_time*internal_to_external_ratio); - if(ctime >= clock_base) { - uint64_t delta = ctime - clock_base; - clock_base += delta & ~15; + if(m_clock_state || !m_clock_value) { + uint64_t ctime = uint64_t(current_time*m_internal_to_external_ratio); + if(ctime >= m_clock_base) { + uint64_t delta = ctime - m_clock_base; + m_clock_base += delta & ~15; delta &= 15; bool new_clock = delta >= 8; - if(new_clock != clock_value) { + if(new_clock != m_clock_value) { machine().scheduler().synchronize(); - if((!new_clock) && (clock_state & CLK_TX)) + if((!new_clock) && (m_clock_state & CLK_TX)) tx_dropped_edge(); - else if(new_clock && (clock_state & CLK_RX)) + else if(new_clock && (m_clock_state & CLK_RX)) rx_raised_edge(); - clock_value = new_clock; + m_clock_value = new_clock; } } - event = uint64_t((clock_base + (clock_value ? 16 : 8))*external_to_internal_ratio)+1; + event = uint64_t((m_clock_base + (m_clock_value ? 16 : 8))*m_external_to_internal_ratio)+1; } break; @@ -474,10 +474,10 @@ uint64_t h8_sci_device::internal_update(uint64_t current_time) } if(event) { attotime ctime = machine().time(); - attotime sync_time = attotime::from_ticks(event-10, cpu->clock()); - if(cur_sync_time != sync_time && sync_time > ctime) { - sync_timer->adjust(sync_time - ctime); - cur_sync_time = sync_time; + attotime sync_time = attotime::from_ticks(event-10, m_cpu->clock()); + if(m_cur_sync_time != sync_time && sync_time > ctime) { + m_sync_timer->adjust(sync_time - ctime); + m_cur_sync_time = sync_time; } } @@ -487,36 +487,36 @@ uint64_t h8_sci_device::internal_update(uint64_t current_time) void h8_sci_device::clock_start(int mode) { // Happens when back-to-back - if(clock_state & mode) + if(m_clock_state & mode) return; - if(!clock_state) { + if(!m_clock_state) { machine().scheduler().synchronize(); - clock_state = mode; - switch(clock_mode) { + m_clock_state = mode; + switch(m_clock_mode) { case clock_mode_t::INTERNAL_ASYNC: case clock_mode_t::INTERNAL_ASYNC_OUT: case clock_mode_t::INTERNAL_SYNC_OUT: if(V>=2) logerror("Starting internal clock\n"); - clock_base = cpu->total_cycles(); - cpu->internal_update(); + m_clock_base = m_cpu->total_cycles(); + m_cpu->internal_update(); break; case clock_mode_t::EXTERNAL_RATE_ASYNC: if(V>=2) logerror("Simulating external clock async\n"); - clock_base = uint64_t(cpu->total_cycles()*internal_to_external_ratio); - cpu->internal_update(); + m_clock_base = uint64_t(m_cpu->total_cycles()*m_internal_to_external_ratio); + m_cpu->internal_update(); break; case clock_mode_t::EXTERNAL_RATE_SYNC: if(V>=2) logerror("Simulating external clock sync\n"); - clock_base = uint64_t(cpu->total_cycles()*2*internal_to_external_ratio); - cpu->internal_update(); + m_clock_base = uint64_t(m_cpu->total_cycles()*2*m_internal_to_external_ratio); + m_cpu->internal_update(); break; case clock_mode_t::EXTERNAL_ASYNC: if(V>=2) logerror("Waiting for external clock async\n"); - ext_clock_counter = 15; + m_ext_clock_counter = 15; break; case clock_mode_t::EXTERNAL_SYNC: @@ -524,207 +524,207 @@ void h8_sci_device::clock_start(int mode) break; } } else - clock_state |= mode; + m_clock_state |= mode; } void h8_sci_device::clock_stop(int mode) { - clock_state &= ~mode; - cpu->internal_update(); + m_clock_state &= ~mode; + m_cpu->internal_update(); } void h8_sci_device::tx_start() { - ssr |= SSR_TDRE; - tsr = tdr; - tx_parity = smr & SMR_OE ? 0 : 1; - if(V>=1) logerror("start transmit %02x '%c'\n", tsr, tsr >= 32 && tsr < 127 ? tsr : '.'); - if(scr & SCR_TIE) - intc->internal_interrupt(txi_int); - if(smr & SMR_CA) { - tx_state = ST_BIT; - tx_bit = 8; + m_ssr |= SSR_TDRE; + m_tsr = m_tdr; + m_tx_parity = m_smr & SMR_OE ? 0 : 1; + if(V>=1) logerror("start transmit %02x '%c'\n", m_tsr, m_tsr >= 32 && m_tsr < 127 ? m_tsr : '.'); + if(m_scr & SCR_TIE) + m_intc->internal_interrupt(m_txi_int); + if(m_smr & SMR_CA) { + m_tx_state = ST_BIT; + m_tx_bit = 8; } else { - tx_state = ST_START; - tx_bit = 1; + m_tx_state = ST_START; + m_tx_bit = 1; } clock_start(CLK_TX); - if(rx_state == ST_IDLE && !has_recv_error() && is_sync_start()) + if(m_rx_state == ST_IDLE && !has_recv_error() && is_sync_start()) rx_start(); } void h8_sci_device::tx_dropped_edge() { - if(V>=2) logerror("tx_dropped_edge state=%s bit=%d\n", state_names[tx_state], tx_bit); - switch(tx_state) { + if(V>=2) logerror("tx_dropped_edge state=%s bit=%d\n", state_names[m_tx_state], m_tx_bit); + switch(m_tx_state) { case ST_START: - tx_cb(false); - assert(tx_bit == 1); - tx_state = ST_BIT; - tx_bit = smr & SMR_CHR ? 7 : 8; + m_tx_cb(false); + assert(m_tx_bit == 1); + m_tx_state = ST_BIT; + m_tx_bit = m_smr & SMR_CHR ? 7 : 8; break; case ST_BIT: - tx_parity ^= (tsr & 1); - tx_cb(tsr & 1); - tsr >>= 1; - tx_bit--; - if(!tx_bit) { - if(smr & SMR_CA) { - if(!(ssr & SSR_TDRE)) + m_tx_parity ^= (m_tsr & 1); + m_tx_cb(m_tsr & 1); + m_tsr >>= 1; + m_tx_bit--; + if(!m_tx_bit) { + if(m_smr & SMR_CA) { + if(!(m_ssr & SSR_TDRE)) tx_start(); else { - tx_state = ST_LAST_TICK; - tx_bit = 0; + m_tx_state = ST_LAST_TICK; + m_tx_bit = 0; } - } else if(smr & SMR_PE) { - tx_state = ST_PARITY; - tx_bit = 1; + } else if(m_smr & SMR_PE) { + m_tx_state = ST_PARITY; + m_tx_bit = 1; } else { - tx_state = ST_STOP; - tx_bit = smr & SMR_STOP ? 2 : 1; + m_tx_state = ST_STOP; + m_tx_bit = m_smr & SMR_STOP ? 2 : 1; } } break; case ST_PARITY: - tx_cb(tx_parity); - assert(tx_bit == 1); - tx_state = ST_STOP; - tx_bit = smr & SMR_STOP ? 2 : 1; + m_tx_cb(m_tx_parity); + assert(m_tx_bit == 1); + m_tx_state = ST_STOP; + m_tx_bit = m_smr & SMR_STOP ? 2 : 1; break; case ST_STOP: - tx_cb(true); - tx_bit--; - if(!tx_bit) { - if(!(ssr & SSR_TDRE)) + m_tx_cb(true); + m_tx_bit--; + if(!m_tx_bit) { + if(!(m_ssr & SSR_TDRE)) tx_start(); else { - tx_state = ST_LAST_TICK; - tx_bit = 0; + m_tx_state = ST_LAST_TICK; + m_tx_bit = 0; } } break; case ST_LAST_TICK: - tx_state = ST_IDLE; - tx_bit = 0; + m_tx_state = ST_IDLE; + m_tx_bit = 0; clock_stop(CLK_TX); - tx_cb(1); - ssr |= SSR_TEND; - if(scr & SCR_TEIE) - intc->internal_interrupt(tei_int); + m_tx_cb(1); + m_ssr |= SSR_TEND; + if(m_scr & SCR_TEIE) + m_intc->internal_interrupt(m_tei_int); // if there's more to send, start the transmitter - if ((scr & SCR_TE) && !(ssr & SSR_TDRE)) + if((m_scr & SCR_TE) && !(m_ssr & SSR_TDRE)) tx_start(); break; default: abort(); } - if(V>=2) logerror(" -> state=%s bit=%d\n", state_names[tx_state], tx_bit); + if(V>=2) logerror(" -> state=%s bit=%d\n", state_names[m_tx_state], m_tx_bit); } void h8_sci_device::rx_start() { - rx_parity = smr & SMR_OE ? 0 : 1; - rsr = 0x00; + m_rx_parity = m_smr & SMR_OE ? 0 : 1; + m_rsr = 0x00; if(V>=2) logerror("start receive\n"); - if(smr & SMR_CA) { - rx_state = ST_BIT; - rx_bit = 8; + if(m_smr & SMR_CA) { + m_rx_state = ST_BIT; + m_rx_bit = 8; clock_start(CLK_RX); } else { - rx_state = ST_START; - rx_bit = 1; - if(!rx_value) + m_rx_state = ST_START; + m_rx_bit = 1; + if(!m_rx_value) clock_start(CLK_RX); } } void h8_sci_device::rx_done() { - if(!(ssr & SSR_FER)) { - if((smr & SMR_PE) && rx_parity) { - ssr |= SSR_PER; + if(!(m_ssr & SSR_FER)) { + if((m_smr & SMR_PE) && m_rx_parity) { + m_ssr |= SSR_PER; if(V>=1) logerror("Receive parity error\n"); - } else if(ssr & SSR_RDRF) { - ssr |= SSR_ORER; + } else if(m_ssr & SSR_RDRF) { + m_ssr |= SSR_ORER; if(V>=1) logerror("Receive overrun\n"); } else { - ssr |= SSR_RDRF; - if(V>=1) logerror("Received %02x '%c'\n", rsr, rsr >= 32 && rsr < 127 ? rsr : '.'); - rdr = rsr; + m_ssr |= SSR_RDRF; + if(V>=1) logerror("Received %02x '%c'\n", m_rsr, m_rsr >= 32 && m_rsr < 127 ? m_rsr : '.'); + m_rdr = m_rsr; } } - if(scr & SCR_RIE) { + if(m_scr & SCR_RIE) { if(has_recv_error()) - intc->internal_interrupt(eri_int); + m_intc->internal_interrupt(m_eri_int); else - intc->internal_interrupt(rxi_int); + m_intc->internal_interrupt(m_rxi_int); } - if((scr & SCR_RE) && !has_recv_error() && !is_sync_start()) + if((m_scr & SCR_RE) && !has_recv_error() && !is_sync_start()) rx_start(); else { clock_stop(CLK_RX); - rx_state = ST_IDLE; + m_rx_state = ST_IDLE; } } void h8_sci_device::rx_raised_edge() { - if(V>=2) logerror("rx_raised_edge state=%s bit=%d\n", state_names[rx_state], rx_bit); - switch(rx_state) { + if(V>=2) logerror("rx_raised_edge state=%s bit=%d\n", state_names[m_rx_state], m_rx_bit); + switch(m_rx_state) { case ST_START: - if(rx_value) { + if(m_rx_value) { clock_stop(CLK_RX); break; } - rx_state = ST_BIT; - rx_bit = smr & SMR_CHR ? 7 : 8; + m_rx_state = ST_BIT; + m_rx_bit = m_smr & SMR_CHR ? 7 : 8; break; case ST_BIT: - rx_parity ^= rx_value; - rsr >>= 1; - if(rx_value) { - rx_parity = !rx_parity; - rsr |= (smr & (SMR_CA|SMR_CHR)) == SMR_CHR ? 0x40 : 0x80; + m_rx_parity ^= m_rx_value; + m_rsr >>= 1; + if(m_rx_value) { + m_rx_parity = !m_rx_parity; + m_rsr |= (m_smr & (SMR_CA|SMR_CHR)) == SMR_CHR ? 0x40 : 0x80; } - rx_bit--; - if(!rx_bit) { - if(smr & SMR_CA) + m_rx_bit--; + if(!m_rx_bit) { + if(m_smr & SMR_CA) rx_done(); - else if(smr & SMR_PE) { - rx_state = ST_PARITY; - rx_bit = 1; + else if(m_smr & SMR_PE) { + m_rx_state = ST_PARITY; + m_rx_bit = 1; } else { - rx_state = ST_STOP; - rx_bit = 1; // Always 1 on rx + m_rx_state = ST_STOP; + m_rx_bit = 1; // Always 1 on rx } } break; case ST_PARITY: - rx_parity ^= rx_value; - assert(rx_bit == 1); - rx_state = ST_STOP; - rx_bit = 1; + m_rx_parity ^= m_rx_value; + assert(m_rx_bit == 1); + m_rx_state = ST_STOP; + m_rx_bit = 1; break; case ST_STOP: - assert(rx_bit == 1); - if(!rx_value) - ssr |= SSR_FER; - else if((smr & SMR_PE) && rx_parity) - ssr |= SSR_PER; + assert(m_rx_bit == 1); + if(!m_rx_value) + m_ssr |= SSR_FER; + else if((m_smr & SMR_PE) && m_rx_parity) + m_ssr |= SSR_PER; rx_done(); break; default: abort(); } - if(V>=2) logerror(" -> state=%s, bit=%d\n", state_names[rx_state], rx_bit); + if(V>=2) logerror(" -> state=%s, bit=%d\n", state_names[m_rx_state], m_rx_bit); } diff --git a/src/devices/cpu/h8/h8_sci.h b/src/devices/cpu/h8/h8_sci.h index adb0ae0ce7d..2b177a34126 100644 --- a/src/devices/cpu/h8/h8_sci.h +++ b/src/devices/cpu/h8/h8_sci.h @@ -46,8 +46,8 @@ public: DECLARE_WRITE_LINE_MEMBER(rx_w); DECLARE_WRITE_LINE_MEMBER(clk_w); - auto tx_handler() { return tx_cb.bind(); } - auto clk_handler() { return clk_cb.bind(); } + auto tx_handler() { return m_tx_cb.bind(); } + auto clk_handler() { return m_clk_cb.bind(); } uint64_t internal_update(uint64_t current_time); @@ -102,24 +102,24 @@ protected: SSR_MPBT = 0x01 }; - required_device cpu; - devcb_write_line tx_cb, clk_cb; - h8_intc_device *intc; - const char *intc_tag; - attotime external_clock_period, cur_sync_time; - double external_to_internal_ratio, internal_to_external_ratio; - emu_timer *sync_timer; + required_device m_cpu; + devcb_write_line m_tx_cb, m_clk_cb; + h8_intc_device *m_intc; + const char *m_intc_tag; + attotime m_external_clock_period, m_cur_sync_time; + double m_external_to_internal_ratio, m_internal_to_external_ratio; + emu_timer *m_sync_timer; - int eri_int, rxi_int, txi_int, tei_int; + int m_eri_int, m_rxi_int, m_txi_int, m_tei_int; - int tx_state, rx_state, tx_bit, rx_bit, clock_state, tx_parity, rx_parity, ext_clock_counter; - clock_mode_t clock_mode; - bool clock_value, ext_clock_value, rx_value; + int m_tx_state, m_rx_state, m_tx_bit, m_rx_bit, m_clock_state, m_tx_parity, m_rx_parity, m_ext_clock_counter; + clock_mode_t m_clock_mode; + bool m_clock_value, m_ext_clock_value, m_rx_value; - uint8_t rdr, tdr, smr, scr, ssr, brr, rsr, tsr; - uint64_t clock_base, divider; + uint8_t m_rdr, m_tdr, m_smr, m_scr, m_ssr, m_brr, m_rsr, m_tsr; + uint64_t m_clock_base, m_divider; - std::string last_clock_message; + std::string m_last_clock_message; void device_start() override; void device_reset() override; diff --git a/src/devices/cpu/h8/h8_timer16.cpp b/src/devices/cpu/h8/h8_timer16.cpp index f74acb4816f..2527a2aa0cb 100644 --- a/src/devices/cpu/h8/h8_timer16.cpp +++ b/src/devices/cpu/h8/h8_timer16.cpp @@ -16,40 +16,40 @@ DEFINE_DEVICE_TYPE(H8S_TIMER16_CHANNEL, h8s_timer16_channel_device, "h8s_timer16 h8_timer16_channel_device::h8_timer16_channel_device(const machine_config &mconfig, const char *tag, device_t *owner, uint32_t clock) : h8_timer16_channel_device(mconfig, H8_TIMER16_CHANNEL, tag, owner, clock) { - chain_tag = nullptr; + m_chain_tag = nullptr; } h8_timer16_channel_device::h8_timer16_channel_device(const machine_config &mconfig, device_type type, const char *tag, device_t *owner, uint32_t clock) : device_t(mconfig, type, tag, owner, clock), - cpu(*this, "^^"), chained_timer(nullptr), intc(nullptr), intc_tag(nullptr), tier_mask(0), tgr_count(0), tbr_count(0), tgr_clearing(0), tcr(0), tier(0), ier(0), isr(0), clock_type(0), - clock_divider(0), tcnt(0), last_clock_update(0), event_time(0), phase(0), counter_cycle(0), counter_incrementing(false), channel_active(false) + m_cpu(*this, "^^"), m_chained_timer(nullptr), m_intc(nullptr), m_intc_tag(nullptr), m_tier_mask(0), m_tgr_count(0), m_tbr_count(0), m_tgr_clearing(0), m_tcr(0), m_tier(0), m_ier(0), m_isr(0), m_clock_type(0), + m_clock_divider(0), m_tcnt(0), m_last_clock_update(0), m_event_time(0), m_phase(0), m_counter_cycle(0), m_counter_incrementing(false), m_channel_active(false) { - chain_tag = nullptr; + m_chain_tag = nullptr; } -void h8_timer16_channel_device::set_info(int _tgr_count, int _tbr_count, const char *intc, int irq_base) +void h8_timer16_channel_device::set_info(int tgr_count, int tbr_count, const char *intc, int irq_base) { - tgr_count = _tgr_count; - tbr_count = _tbr_count; - intc_tag = intc; + m_tgr_count = tgr_count; + m_tbr_count = tbr_count; + m_intc_tag = intc; - interrupt[0] = irq_base++; - interrupt[1] = irq_base++; - interrupt[2] = -1; - interrupt[3] = -1; - interrupt[4] = irq_base; - interrupt[5] = irq_base; + m_interrupt[0] = irq_base++; + m_interrupt[1] = irq_base++; + m_interrupt[2] = -1; + m_interrupt[3] = -1; + m_interrupt[4] = irq_base; + m_interrupt[5] = irq_base; } uint8_t h8_timer16_channel_device::tcr_r() { - return tcr; + return m_tcr; } void h8_timer16_channel_device::tcr_w(uint8_t data) { update_counter(); - tcr = data; + m_tcr = data; if(V>=1) logerror("tcr_w %02x\n", data); tcr_update(); recalc_event(); @@ -78,36 +78,36 @@ void h8_timer16_channel_device::tior_w(offs_t offset, uint8_t data) void h8_timer16_channel_device::set_ier(uint8_t value) { update_counter(); - ier = value; + m_ier = value; recalc_event(); } void h8_timer16_channel_device::set_enable(bool enable) { update_counter(); - channel_active = enable; + m_channel_active = enable; recalc_event(); } uint8_t h8_timer16_channel_device::tier_r() { - return tier; + return m_tier; } void h8_timer16_channel_device::tier_w(uint8_t data) { update_counter(); if(V>=1) logerror("tier_w %02x\n", data); - tier = data; + m_tier = data; tier_update(); if(V>=1) logerror("irq %c%c%c%c%c%c trigger=%d\n", - ier & IRQ_A ? 'a' : '.', - ier & IRQ_B ? 'b' : '.', - ier & IRQ_C ? 'c' : '.', - ier & IRQ_D ? 'd' : '.', - ier & IRQ_V ? 'v' : '.', - ier & IRQ_U ? 'u' : '.', - ier & IRQ_TRIG ? 1 : 0); + m_ier & IRQ_A ? 'a' : '.', + m_ier & IRQ_B ? 'b' : '.', + m_ier & IRQ_C ? 'c' : '.', + m_ier & IRQ_D ? 'd' : '.', + m_ier & IRQ_V ? 'v' : '.', + m_ier & IRQ_U ? 'u' : '.', + m_ier & IRQ_TRIG ? 1 : 0); recalc_event(); } @@ -125,174 +125,174 @@ void h8_timer16_channel_device::tsr_w(uint8_t data) uint16_t h8_timer16_channel_device::tcnt_r() { update_counter(); - return tcnt; + return m_tcnt; } void h8_timer16_channel_device::tcnt_w(offs_t offset, uint16_t data, uint16_t mem_mask) { update_counter(); - COMBINE_DATA(&tcnt); - if(V>=1) logerror("tcnt_w %04x\n", tcnt); + COMBINE_DATA(&m_tcnt); + if(V>=1) logerror("tcnt_w %04x\n", m_tcnt); recalc_event(); } uint16_t h8_timer16_channel_device::tgr_r(offs_t offset) { - return tgr[offset]; + return m_tgr[offset]; } void h8_timer16_channel_device::tgr_w(offs_t offset, uint16_t data, uint16_t mem_mask) { update_counter(); - COMBINE_DATA(tgr + offset); - if(V>=1) logerror("tgr%c_w %04x\n", 'a'+offset, tgr[offset]); + COMBINE_DATA(m_tgr + offset); + if(V>=1) logerror("tgr%c_w %04x\n", 'a'+offset, m_tgr[offset]); recalc_event(); } uint16_t h8_timer16_channel_device::tbr_r(offs_t offset) { - return tgr[offset+tgr_count]; + return m_tgr[offset+m_tgr_count]; } void h8_timer16_channel_device::tbr_w(offs_t offset, uint16_t data, uint16_t mem_mask) { - COMBINE_DATA(tgr + offset + tgr_count); - if(V>=1) logerror("tbr%c_w %04x\n", 'a'+offset, tgr[offset]); + COMBINE_DATA(m_tgr + offset + m_tgr_count); + if(V>=1) logerror("tbr%c_w %04x\n", 'a'+offset, m_tgr[offset]); } void h8_timer16_channel_device::device_start() { - intc = owner()->siblingdevice(intc_tag); - channel_active = false; + m_intc = owner()->siblingdevice(m_intc_tag); + m_channel_active = false; device_reset(); - save_item(NAME(tgr_clearing)); - save_item(NAME(tcr)); - save_item(NAME(tier)); - save_item(NAME(ier)); - save_item(NAME(isr)); - save_item(NAME(clock_type)); - save_item(NAME(clock_divider)); - save_item(NAME(tcnt)); - save_item(NAME(tgr)); - save_item(NAME(last_clock_update)); - save_item(NAME(event_time)); - save_item(NAME(phase)); - save_item(NAME(counter_cycle)); - save_item(NAME(counter_incrementing)); - save_item(NAME(channel_active)); + save_item(NAME(m_tgr_clearing)); + save_item(NAME(m_tcr)); + save_item(NAME(m_tier)); + save_item(NAME(m_ier)); + save_item(NAME(m_isr)); + save_item(NAME(m_clock_type)); + save_item(NAME(m_clock_divider)); + save_item(NAME(m_tcnt)); + save_item(NAME(m_tgr)); + save_item(NAME(m_last_clock_update)); + save_item(NAME(m_event_time)); + save_item(NAME(m_phase)); + save_item(NAME(m_counter_cycle)); + save_item(NAME(m_counter_incrementing)); + save_item(NAME(m_channel_active)); } void h8_timer16_channel_device::device_reset() { // Don't touch channel_active here, top level device handles it - tcr = 0; - tcnt = 0; - memset(tgr, 0xff, sizeof(tgr)); - tgr_clearing = TGR_CLEAR_NONE; - clock_type = DIV_1; - clock_divider = 0; - counter_cycle = 0x10000; - phase = 0; - tier = 0x40 & tier_mask; - ier = 0; - isr = 0; - last_clock_update = 0; - event_time = 0; - counter_incrementing = true; + m_tcr = 0; + m_tcnt = 0; + memset(m_tgr, 0xff, sizeof(m_tgr)); + m_tgr_clearing = TGR_CLEAR_NONE; + m_clock_type = DIV_1; + m_clock_divider = 0; + m_counter_cycle = 0x10000; + m_phase = 0; + m_tier = 0x40 & m_tier_mask; + m_ier = 0; + m_isr = 0; + m_last_clock_update = 0; + m_event_time = 0; + m_counter_incrementing = true; } uint64_t h8_timer16_channel_device::internal_update(uint64_t current_time) { - if(event_time && current_time >= event_time) { + if(m_event_time && current_time >= m_event_time) { update_counter(current_time); recalc_event(current_time); } - return event_time; + return m_event_time; } void h8_timer16_channel_device::update_counter(uint64_t cur_time) { - if(clock_type != DIV_1) + if(m_clock_type != DIV_1) return; if(!cur_time) - cur_time = cpu->total_cycles(); + cur_time = m_cpu->total_cycles(); - if(!channel_active) { - last_clock_update = cur_time; + if(!m_channel_active) { + m_last_clock_update = cur_time; return; } - uint64_t base_time = last_clock_update; + uint64_t base_time = m_last_clock_update; uint64_t new_time = cur_time; - if(clock_divider) { - base_time = (base_time + phase) >> clock_divider; - new_time = (new_time + phase) >> clock_divider; + if(m_clock_divider) { + base_time = (base_time + m_phase) >> m_clock_divider; + new_time = (new_time + m_phase) >> m_clock_divider; } - if(counter_incrementing) { - int tt = tcnt + new_time - base_time; - tcnt = tt % counter_cycle; - - for(int i=0; iinternal_interrupt(interrupt[i]); + if(m_counter_incrementing) { + int tt = m_tcnt + new_time - base_time; + m_tcnt = tt % m_counter_cycle; + + for(int i=0; iinternal_interrupt(m_interrupt[i]); } - if(tt >= 0x10000 && (ier & IRQ_V) && interrupt[4] != -1) { - isr |= IRQ_V; - intc->internal_interrupt(interrupt[4]); + if(tt >= 0x10000 && (m_ier & IRQ_V) && m_interrupt[4] != -1) { + m_isr |= IRQ_V; + m_intc->internal_interrupt(m_interrupt[4]); } } else - tcnt = (((tcnt ^ 0xffff) + new_time - base_time) % counter_cycle) ^ 0xffff; - last_clock_update = cur_time; + m_tcnt = (((m_tcnt ^ 0xffff) + new_time - base_time) % m_counter_cycle) ^ 0xffff; + m_last_clock_update = cur_time; } void h8_timer16_channel_device::recalc_event(uint64_t cur_time) { - if(!channel_active) { - event_time = 0; + if(!m_channel_active) { + m_event_time = 0; return; } bool update_cpu = cur_time == 0; - uint64_t old_event_time = event_time; + uint64_t old_event_time = m_event_time; - if(clock_type != DIV_1) { - event_time = 0; + if(m_clock_type != DIV_1) { + m_event_time = 0; if(old_event_time && update_cpu) - cpu->internal_update(); + m_cpu->internal_update(); return; } if(!cur_time) - cur_time = cpu->total_cycles(); + cur_time = m_cpu->total_cycles(); - if(counter_incrementing) { + if(m_counter_incrementing) { uint32_t event_delay = 0xffffffff; - if(tgr_clearing >= 0 && tgr[tgr_clearing]) - counter_cycle = tgr[tgr_clearing]; + if(m_tgr_clearing >= 0 && m_tgr[m_tgr_clearing]) + m_counter_cycle = m_tgr[m_tgr_clearing]; else { - counter_cycle = 0x10000; - if(ier & IRQ_V) { - event_delay = counter_cycle - tcnt; + m_counter_cycle = 0x10000; + if(m_ier & IRQ_V) { + event_delay = m_counter_cycle - m_tcnt; if(!event_delay) - event_delay = counter_cycle; + event_delay = m_counter_cycle; } } - for(int i=0; i tcnt) { - if(tcnt >= counter_cycle || tgr[i] <= counter_cycle) - new_delay = tgr[i] - tcnt; - } else if(tgr[i] <= counter_cycle) { - if(tcnt < counter_cycle) - new_delay = (counter_cycle - tcnt) + tgr[i]; + if(m_tgr[i] > m_tcnt) { + if(m_tcnt >= m_counter_cycle || m_tgr[i] <= m_counter_cycle) + new_delay = m_tgr[i] - m_tcnt; + } else if(m_tgr[i] <= m_counter_cycle) { + if(m_tcnt < m_counter_cycle) + new_delay = (m_counter_cycle - m_tcnt) + m_tgr[i]; else - new_delay = (0x10000 - tcnt) + tgr[i]; + new_delay = (0x10000 - m_tcnt) + m_tgr[i]; } if(event_delay > new_delay) @@ -300,62 +300,62 @@ void h8_timer16_channel_device::recalc_event(uint64_t cur_time) } if(event_delay != 0xffffffff) - event_time = ((((cur_time + (1ULL << clock_divider) - phase) >> clock_divider) + event_delay - 1) << clock_divider) + phase; + m_event_time = ((((cur_time + (1ULL << m_clock_divider) - m_phase) >> m_clock_divider) + event_delay - 1) << m_clock_divider) + m_phase; else - event_time = 0; + m_event_time = 0; } else { logerror("decrementing counter\n"); exit(1); } - if(old_event_time != event_time && update_cpu) - cpu->internal_update(); + if(old_event_time != m_event_time && update_cpu) + m_cpu->internal_update(); } h8_timer16_device::h8_timer16_device(const machine_config &mconfig, const char *tag, device_t *owner, uint32_t clock) : device_t(mconfig, H8_TIMER16, tag, owner, clock), - cpu(*this, DEVICE_SELF_OWNER) + m_cpu(*this, DEVICE_SELF_OWNER) { } void h8_timer16_device::set_info(int count, uint8_t tstr) { - timer_count = count; - default_tstr = tstr; + m_timer_count = count; + m_default_tstr = tstr; } void h8_timer16_device::device_start() { - memset(timer_channel, 0, sizeof(timer_channel)); - for(int i=0; i(tm); + m_timer_channel[i] = subdevice(tm); } - save_item(NAME(tstr)); + save_item(NAME(m_tstr)); } void h8_timer16_device::device_reset() { - tstr = default_tstr; - for(int i=0; iset_enable((tstr >> i) & 1); + m_tstr = m_default_tstr; + for(int i=0; iset_enable((m_tstr >> i) & 1); } uint8_t h8_timer16_device::tstr_r() { - return tstr; + return m_tstr; } void h8_timer16_device::tstr_w(uint8_t data) { if(V>=1) logerror("tstr_w %02x\n", data); - tstr = data; - for(int i=0; iset_enable((tstr >> i) & 1); + m_tstr = data; + for(int i=0; iset_enable((m_tstr >> i) & 1); } uint8_t h8_timer16_device::tsyr_r() @@ -411,9 +411,9 @@ void h8_timer16_device::tocr_w(uint8_t data) uint8_t h8_timer16_device::tisr_r(offs_t offset) { uint8_t r = 0; - for(int i=0; itisr_r(offset) << i; - for(int i=timer_count; i<4; i++) + for(int i=0; itisr_r(offset) << i; + for(int i=m_timer_count; i<4; i++) r |= 0x11 <=1) logerror("tisr%c_r %02x\n", 'a'+offset, r); @@ -424,8 +424,8 @@ uint8_t h8_timer16_device::tisr_r(offs_t offset) void h8_timer16_device::tisr_w(offs_t offset, uint8_t data) { if(V>=1) logerror("tisr%c_w %02x\n", 'a'+offset, data); - for(int i=0; itisr_w(offset, data >> i); + for(int i=0; itisr_w(offset, data >> i); } uint8_t h8_timer16_device::tisrc_r() @@ -468,38 +468,38 @@ void h8_timer16_channel_device::tisr_w(int offset, uint8_t value) if(!(value & 0x01)) { switch(offset) { case 0: - isr &= ~IRQ_A; + m_isr &= ~IRQ_A; break; case 1: - isr &= ~IRQ_B; + m_isr &= ~IRQ_B; break; case 2: - isr &= ~IRQ_V; + m_isr &= ~IRQ_V; break; } } if(value & 0x10) { switch(offset) { case 0: - ier |= IRQ_A; + m_ier |= IRQ_A; break; case 1: - ier |= IRQ_B; + m_ier |= IRQ_B; break; case 2: - ier |= IRQ_V; + m_ier |= IRQ_V; break; } } else { switch(offset) { case 0: - ier &= ~IRQ_A; + m_ier &= ~IRQ_A; break; case 1: - ier &= ~IRQ_B; + m_ier &= ~IRQ_B; break; case 2: - ier &= ~IRQ_V; + m_ier &= ~IRQ_V; break; } } @@ -510,11 +510,11 @@ uint8_t h8_timer16_channel_device::tisr_r(int offset) const { switch(offset) { case 0: - return ((ier & IRQ_A) ? 0x10 : 0x00) | ((isr & IRQ_A) ? 0x01 : 0x00); + return ((m_ier & IRQ_A) ? 0x10 : 0x00) | ((m_isr & IRQ_A) ? 0x01 : 0x00); case 1: - return ((ier & IRQ_B) ? 0x10 : 0x00) | ((isr & IRQ_B) ? 0x01 : 0x00); + return ((m_ier & IRQ_B) ? 0x10 : 0x00) | ((m_isr & IRQ_B) ? 0x01 : 0x00); case 2: - return ((ier & IRQ_V) ? 0x10 : 0x00) | ((isr & IRQ_V) ? 0x01 : 0x00); + return ((m_ier & IRQ_V) ? 0x10 : 0x00) | ((m_isr & IRQ_V) ? 0x01 : 0x00); } return 0x00; } @@ -528,91 +528,91 @@ h8h_timer16_channel_device::~h8h_timer16_channel_device() { } -void h8h_timer16_channel_device::set_info(int _tgr_count, int _tbr_count, const char *intc, int irq_base) +void h8h_timer16_channel_device::set_info(int tgr_count, int tbr_count, const char *intc, int irq_base) { - tgr_count = _tgr_count; - tbr_count = _tbr_count; - intc_tag = intc; + m_tgr_count = tgr_count; + m_tbr_count = tbr_count; + m_intc_tag = intc; - interrupt[0] = irq_base++; - interrupt[1] = irq_base++; - interrupt[2] = -1; - interrupt[3] = -1; - interrupt[4] = irq_base; - interrupt[5] = irq_base; + m_interrupt[0] = irq_base++; + m_interrupt[1] = irq_base++; + m_interrupt[2] = -1; + m_interrupt[3] = -1; + m_interrupt[4] = irq_base; + m_interrupt[5] = irq_base; } void h8h_timer16_channel_device::tier_update() { - tier = tier | 0xf8; - ier = - (tier & 0x01 ? IRQ_A : 0) | - (tier & 0x02 ? IRQ_B : 0) | - (tier & 0x04 ? IRQ_V : 0); + m_tier = m_tier | 0xf8; + m_ier = + (m_tier & 0x01 ? IRQ_A : 0) | + (m_tier & 0x02 ? IRQ_B : 0) | + (m_tier & 0x04 ? IRQ_V : 0); } void h8h_timer16_channel_device::isr_update(uint8_t val) { if(!(val & 1)) - isr &= ~IRQ_A; + m_isr &= ~IRQ_A; if(!(val & 2)) - isr &= ~IRQ_B; + m_isr &= ~IRQ_B; if(!(val & 4)) - isr &= ~IRQ_V; + m_isr &= ~IRQ_V; } uint8_t h8h_timer16_channel_device::isr_to_sr() const { - return 0xf8 | (isr & IRQ_V ? 4 : 0) | (isr & IRQ_B ? 2 : 0) | (isr & IRQ_A ? 1 : 0); + return 0xf8 | (m_isr & IRQ_V ? 4 : 0) | (m_isr & IRQ_B ? 2 : 0) | (m_isr & IRQ_A ? 1 : 0); } void h8h_timer16_channel_device::tcr_update() { - switch(tcr & 0x60) { + switch(m_tcr & 0x60) { case 0x00: - tgr_clearing = TGR_CLEAR_NONE; + m_tgr_clearing = TGR_CLEAR_NONE; if(V>=1) logerror("No automatic tcnt clearing\n"); break; case 0x20: case 0x40: { - tgr_clearing = tcr & 0x20 ? 0 : 1; - if(V>=1) logerror("Auto-clear on tgr%c (%04x)\n", 'a'+tgr_clearing, tgr[tgr_clearing]); + m_tgr_clearing = m_tcr & 0x20 ? 0 : 1; + if(V>=1) logerror("Auto-clear on tgr%c (%04x)\n", 'a'+m_tgr_clearing, m_tgr[m_tgr_clearing]); break; } case 0x60: - tgr_clearing = TGR_CLEAR_EXT; + m_tgr_clearing = TGR_CLEAR_EXT; if(V>=1) logerror("External sync clear\n"); break; } - int count_type = tcr & 7; + int count_type = m_tcr & 7; if(count_type < 4) { - clock_type = DIV_1; - clock_divider = count_type; - if(V>=1) logerror("clock divider %d (%d)\n", clock_divider, 1 << clock_divider); + m_clock_type = DIV_1; + m_clock_divider = count_type; + if(V>=1) logerror("clock divider %d (%d)\n", m_clock_divider, 1 << m_clock_divider); if(count_type <= DIV_2) - phase = 0; + m_phase = 0; else { - switch(tcr & 0x18) { + switch(m_tcr & 0x18) { case 0x00: - phase = 0; + m_phase = 0; if(V>=1) logerror("Phase 0\n"); break; case 0x08: - phase = 1 << (clock_divider-1); + m_phase = 1 << (m_clock_divider-1); if(V>=1) logerror("Phase 180\n"); break; case 0x10: case 0x18: - phase = 0; - clock_divider--; + m_phase = 0; + m_clock_divider--; if(V>=1) logerror("Phase 0+180\n"); break; } } } else { - clock_type = INPUT_A + (count_type-4); - clock_divider = 0; - phase = 0; + m_clock_type = INPUT_A + (count_type-4); + m_clock_divider = 0; + m_phase = 0; if(V>=1) logerror("counting input %c\n", 'a'+count_type-INPUT_A); } } @@ -626,114 +626,114 @@ h8s_timer16_channel_device::~h8s_timer16_channel_device() { } -void h8s_timer16_channel_device::set_chain(const char *_chain_tag) +void h8s_timer16_channel_device::set_chain(const char *chain_tag) { - chain_tag = _chain_tag; + m_chain_tag = chain_tag; } -void h8s_timer16_channel_device::set_info(int _tgr_count, uint8_t _tier_mask, const char *intc, int irq_base, - int t0, int t1, int t2, int t3, int t4, int t5, int t6, int t7) +void h8s_timer16_channel_device::set_info(int tgr_count, uint8_t tier_mask, const char *intc, int irq_base, + int t0, int t1, int t2, int t3, int t4, int t5, int t6, int t7) { - tgr_count = _tgr_count; - tbr_count = 0; - tier_mask = _tier_mask; - intc_tag = intc; + m_tgr_count = tgr_count; + m_tbr_count = 0; + m_tier_mask = tier_mask; + m_intc_tag = intc; - interrupt[0] = irq_base++; - interrupt[1] = irq_base++; - interrupt[2] = tier_mask & 0x04 ? -1 : irq_base++; - interrupt[3] = tier_mask & 0x08 ? -1 : irq_base++; - interrupt[4] = irq_base; - interrupt[5] = tier_mask & 0x20 ? -1 : irq_base++; + m_interrupt[0] = irq_base++; + m_interrupt[1] = irq_base++; + m_interrupt[2] = tier_mask & 0x04 ? -1 : irq_base++; + m_interrupt[3] = tier_mask & 0x08 ? -1 : irq_base++; + m_interrupt[4] = irq_base; + m_interrupt[5] = tier_mask & 0x20 ? -1 : irq_base++; - count_types[0] = t0; - count_types[1] = t1; - count_types[2] = t2; - count_types[3] = t3; - count_types[4] = t4; - count_types[5] = t5; - count_types[6] = t6; - count_types[7] = t7; + m_count_types[0] = t0; + m_count_types[1] = t1; + m_count_types[2] = t2; + m_count_types[3] = t3; + m_count_types[4] = t4; + m_count_types[5] = t5; + m_count_types[6] = t6; + m_count_types[7] = t7; } void h8s_timer16_channel_device::tier_update() { - tier = (tier & ~tier_mask) | 0x40; - ier = - (tier & 0x01 ? IRQ_A : 0) | - (tier & 0x02 ? IRQ_B : 0) | - (tier & 0x04 ? IRQ_C : 0) | - (tier & 0x08 ? IRQ_D : 0) | - (tier & 0x10 ? IRQ_V : 0) | - (tier & 0x20 ? IRQ_U : 0) | - (tier & 0x80 ? IRQ_TRIG : 0); + m_tier = (m_tier & ~m_tier_mask) | 0x40; + m_ier = + (m_tier & 0x01 ? IRQ_A : 0) | + (m_tier & 0x02 ? IRQ_B : 0) | + (m_tier & 0x04 ? IRQ_C : 0) | + (m_tier & 0x08 ? IRQ_D : 0) | + (m_tier & 0x10 ? IRQ_V : 0) | + (m_tier & 0x20 ? IRQ_U : 0) | + (m_tier & 0x80 ? IRQ_TRIG : 0); } void h8s_timer16_channel_device::isr_update(uint8_t val) { - isr &= (val | tier_mask | 0xc0); + m_isr &= (val | m_tier_mask | 0xc0); } uint8_t h8s_timer16_channel_device::isr_to_sr() const { - return 0xc0 | isr; + return 0xc0 | m_isr; } void h8s_timer16_channel_device::tcr_update() { - switch(tcr & 0x60) { + switch(m_tcr & 0x60) { case 0x00: - tgr_clearing = TGR_CLEAR_NONE; + m_tgr_clearing = TGR_CLEAR_NONE; if(V>=1) logerror("No automatic tcnt clearing\n"); break; case 0x20: case 0x40: { - tgr_clearing = tcr & 0x20 ? 0 : 1; - if(tgr_count > 2 && (tcr & 0x80)) - tgr_clearing += 2; - if(V>=1) logerror("Auto-clear on tgr%c\n", 'a'+tgr_clearing); + m_tgr_clearing = m_tcr & 0x20 ? 0 : 1; + if(m_tgr_count > 2 && (m_tcr & 0x80)) + m_tgr_clearing += 2; + if(V>=1) logerror("Auto-clear on tgr%c\n", 'a'+m_tgr_clearing); break; } case 0x60: - tgr_clearing = TGR_CLEAR_EXT; + m_tgr_clearing = TGR_CLEAR_EXT; if(V>=1) logerror("External sync clear\n"); break; } - int count_type = count_types[tcr & 7]; - if(count_type >= DIV_1 && clock_type <= DIV_4) { - clock_type = DIV_1; - clock_divider = count_type - DIV_1; - if(V>=1) logerror("clock divider %d (%d)\n", clock_divider, 1 << clock_divider); - if(!clock_divider) - phase = 0; + int count_type = m_count_types[m_tcr & 7]; + if(count_type >= DIV_1 && m_clock_type <= DIV_4) { + m_clock_type = DIV_1; + m_clock_divider = count_type - DIV_1; + if(V>=1) logerror("clock divider %d (%d)\n", m_clock_divider, 1 << m_clock_divider); + if(!m_clock_divider) + m_phase = 0; else { - switch(tcr & 0x18) { + switch(m_tcr & 0x18) { case 0x00: - phase = 0; + m_phase = 0; if(V>=1) logerror("Phase 0\n"); break; case 0x08: - phase = 1 << (clock_divider-1); + m_phase = 1 << (m_clock_divider-1); if(V>=1) logerror("Phase 180\n"); break; case 0x10: case 0x18: - phase = 0; - clock_divider--; + m_phase = 0; + m_clock_divider--; if(V>=1) logerror("Phase 0+180\n"); break; } } } else if(count_type == CHAIN) { - clock_type = CHAIN; - clock_divider = 0; - phase = 0; + m_clock_type = CHAIN; + m_clock_divider = 0; + m_phase = 0; if(V>=1) logerror("chained timer\n"); } else if(count_type >= INPUT_A && count_type <= INPUT_D) { - clock_type = count_type; - clock_divider = 0; - phase = 0; + m_clock_type = count_type; + m_clock_divider = 0; + m_phase = 0; if(V>=1) logerror("counting input %c\n", 'a'+count_type-INPUT_A); } } diff --git a/src/devices/cpu/h8/h8_timer16.h b/src/devices/cpu/h8/h8_timer16.h index 6543b9ccb7c..beb442859ef 100644 --- a/src/devices/cpu/h8/h8_timer16.h +++ b/src/devices/cpu/h8/h8_timer16.h @@ -89,22 +89,22 @@ public: uint8_t tisr_r(int offset) const; protected: - required_device cpu; - h8_timer16_channel_device *chained_timer; - h8_intc_device *intc; - const char *chain_tag, *intc_tag; - int interrupt[6]; - uint8_t tier_mask; - - int tgr_count, tbr_count; - int tgr_clearing; - uint8_t tcr, tier, ier, isr; - int clock_type, clock_divider; - uint16_t tcnt, tgr[6]; - uint64_t last_clock_update, event_time; - uint32_t phase, counter_cycle; - bool counter_incrementing; - bool channel_active; + required_device m_cpu; + h8_timer16_channel_device *m_chained_timer; + h8_intc_device *m_intc; + const char *m_chain_tag, *m_intc_tag; + int m_interrupt[6]; + uint8_t m_tier_mask; + + int m_tgr_count, m_tbr_count; + int m_tgr_clearing; + uint8_t m_tcr, m_tier, m_ier, m_isr; + int m_clock_type, m_clock_divider; + uint16_t m_tcnt, m_tgr[6]; + uint64_t m_last_clock_update, m_event_time; + uint32_t m_phase, m_counter_cycle; + bool m_counter_incrementing; + bool m_channel_active; h8_timer16_channel_device(const machine_config &mconfig, device_type type, const char *tag, device_t *owner, uint32_t clock); @@ -154,7 +154,7 @@ public: void set_chain(const char *chain_tag); protected: - int count_types[8]; + int m_count_types[8]; virtual void tcr_update() override; virtual void tier_update() override; @@ -191,11 +191,11 @@ public: void tolr_w(uint8_t data); protected: - required_device cpu; - h8_timer16_channel_device *timer_channel[6]; - int timer_count; - uint8_t default_tstr; - uint8_t tstr; + required_device m_cpu; + h8_timer16_channel_device *m_timer_channel[6]; + int m_timer_count; + uint8_t m_default_tstr; + uint8_t m_tstr; virtual void device_start() override; virtual void device_reset() override; diff --git a/src/devices/cpu/h8/h8_timer8.cpp b/src/devices/cpu/h8/h8_timer8.cpp index bcde51da406..85d7285232c 100644 --- a/src/devices/cpu/h8/h8_timer8.cpp +++ b/src/devices/cpu/h8/h8_timer8.cpp @@ -19,38 +19,38 @@ h8_timer8_channel_device::h8_timer8_channel_device(const machine_config &mconfig h8_timer8_channel_device::h8_timer8_channel_device(const machine_config &mconfig, device_type type, const char *tag, device_t *owner, uint32_t clock) : device_t(mconfig, type, tag, owner, clock), - cpu(*this, "^"), chained_timer(nullptr), intc(nullptr), chain_tag(nullptr), intc_tag(nullptr), irq_ca(0), irq_cb(0), irq_v(0), chain_type(0), tcr(0), tcsr(0), tcnt(0), extra_clock_bit(false), - has_adte(false), has_ice(false), clock_type(0), clock_divider(0), clear_type(0), counter_cycle(0), last_clock_update(0), event_time(0) + m_cpu(*this, "^"), m_chained_timer(nullptr), m_intc(nullptr), m_chain_tag(nullptr), m_intc_tag(nullptr), m_irq_ca(0), m_irq_cb(0), m_irq_v(0), m_chain_type(0), m_tcr(0), m_tcsr(0), m_tcnt(0), m_extra_clock_bit(false), + m_has_adte(false), m_has_ice(false), m_clock_type(0), m_clock_divider(0), m_clear_type(0), m_counter_cycle(0), m_last_clock_update(0), m_event_time(0) { } -void h8_timer8_channel_device::set_info(const char *intc, int _irq_ca, int _irq_cb, int _irq_v, int div1, int div2, int div3, int div4, int div5, int div6) +void h8_timer8_channel_device::set_info(const char *intc, int irq_ca, int irq_cb, int irq_v, int div1, int div2, int div3, int div4, int div5, int div6) { - intc_tag = intc; - irq_ca = _irq_ca; - irq_cb = _irq_cb; - irq_v = _irq_v; - chain_tag = nullptr; - chain_type = STOPPED; - has_adte = false; - has_ice = false; - div_tab[0] = div1; - div_tab[1] = div2; - div_tab[2] = div3; - div_tab[3] = div4; - div_tab[4] = div5; - div_tab[5] = div6; + m_intc_tag = intc; + m_irq_ca = irq_ca; + m_irq_cb = irq_cb; + m_irq_v = irq_v; + m_chain_tag = nullptr; + m_chain_type = STOPPED; + m_has_adte = false; + m_has_ice = false; + m_div_tab[0] = div1; + m_div_tab[1] = div2; + m_div_tab[2] = div3; + m_div_tab[3] = div4; + m_div_tab[4] = div5; + m_div_tab[5] = div6; } uint8_t h8_timer8_channel_device::tcr_r() { - return tcr; + return m_tcr; } void h8_timer8_channel_device::tcr_w(uint8_t data) { update_counter(); - tcr = data; + m_tcr = data; update_tcr(); recalc_event(); } @@ -58,7 +58,7 @@ void h8_timer8_channel_device::tcr_w(uint8_t data) void h8_timer8_channel_device::set_extra_clock_bit(bool bit) { update_counter(); - extra_clock_bit = bit; + m_extra_clock_bit = bit; update_tcr(); recalc_event(); } @@ -66,101 +66,101 @@ void h8_timer8_channel_device::set_extra_clock_bit(bool bit) void h8_timer8_channel_device::update_tcr() { std::ostringstream message; - switch(tcr & TCR_CKS) { + switch(m_tcr & TCR_CKS) { case 0: - clock_type = STOPPED; - clock_divider = 0; + m_clock_type = STOPPED; + m_clock_divider = 0; if(V>=1) message << "clock stopped"; break; case 1: case 2: case 3: - clock_type = DIV; - clock_divider = div_tab[((tcr & TCR_CKS)-1)*2 + extra_clock_bit]; - if(V>=1) util::stream_format(message, "clock %dHz", cpu->clock()/clock_divider); + m_clock_type = DIV; + m_clock_divider = m_div_tab[((m_tcr & TCR_CKS)-1)*2 + m_extra_clock_bit]; + if(V>=1) util::stream_format(message, "clock %dHz", m_cpu->clock()/m_clock_divider); break; case 4: - clock_type = chain_type; - clock_divider = 0; - if(V>=1) util::stream_format(message, "clock chained %s", clock_type == CHAIN_A ? "tcora" : "overflow"); + m_clock_type = m_chain_type; + m_clock_divider = 0; + if(V>=1) util::stream_format(message, "clock chained %s", m_clock_type == CHAIN_A ? "tcora" : "overflow"); break; case 5: - clock_type = INPUT_UP; - clock_divider = 0; + m_clock_type = INPUT_UP; + m_clock_divider = 0; if(V>=1) message << "clock external raising edge"; break; case 6: - clock_type = INPUT_DOWN; - clock_divider = 0; + m_clock_type = INPUT_DOWN; + m_clock_divider = 0; if(V>=1) message << "clock external falling edge"; break; case 7: - clock_type = INPUT_UPDOWN; - clock_divider = 0; + m_clock_type = INPUT_UPDOWN; + m_clock_divider = 0; if(V>=1) message << "clock external both edges"; break; } - switch(tcr & TCR_CCLR) { + switch(m_tcr & TCR_CCLR) { case 0x00: - clear_type = CLEAR_NONE; + m_clear_type = CLEAR_NONE; if(V>=1) message << ", no clear"; break; case 0x08: - clear_type = CLEAR_A; + m_clear_type = CLEAR_A; if(V>=1) message << ", clear on tcora"; break; case 0x10: - clear_type = CLEAR_B; + m_clear_type = CLEAR_B; if(V>=1) message << ", clear on tcorb"; break; case 0x18: - clear_type = CLEAR_EXTERNAL; + m_clear_type = CLEAR_EXTERNAL; if(V>=1) message << ", clear on external"; break; } if(V>=1) util::stream_format(message, ", irq=%c%c%c\n", - tcr & TCR_CMIEB ? 'b' : '-', - tcr & TCR_CMIEA ? 'a' : '-', - tcr & TCR_OVIE ? 'o' : '-'); + m_tcr & TCR_CMIEB ? 'b' : '-', + m_tcr & TCR_CMIEA ? 'a' : '-', + m_tcr & TCR_OVIE ? 'o' : '-'); logerror(std::move(message).str()); } uint8_t h8_timer8_channel_device::tcsr_r() { - return tcsr; + return m_tcsr; } void h8_timer8_channel_device::tcsr_w(uint8_t data) { update_counter(); - uint8_t mask = has_adte || has_ice ? 0x1f : 0x0f; - tcsr = (tcsr & ~mask) | (data & mask); - tcsr &= data | 0x1f; + uint8_t mask = m_has_adte || m_has_ice ? 0x1f : 0x0f; + m_tcsr = (m_tcsr & ~mask) | (data & mask); + m_tcsr &= data | 0x1f; - if(V>=2) logerror("tcsr_w %02x\n", tcsr); + if(V>=2) logerror("tcsr_w %02x\n", m_tcsr); recalc_event(); } uint8_t h8_timer8_channel_device::tcor_r(offs_t offset) { - return tcor[offset]; + return m_tcor[offset]; } void h8_timer8_channel_device::tcor_w(offs_t offset, uint8_t data) { update_counter(); - tcor[offset] = data; + m_tcor[offset] = data; if(V>=2) logerror("tcor%c_w %02x\n", 'a'+offset, data); recalc_event(); } @@ -169,184 +169,184 @@ uint8_t h8_timer8_channel_device::tcnt_r() { update_counter(); recalc_event(); - return tcnt; + return m_tcnt; } void h8_timer8_channel_device::tcnt_w(uint8_t data) { update_counter(); - tcnt = data; + m_tcnt = data; if(V>=2) logerror("tcnt_w %02x\n", data); recalc_event(); } void h8_timer8_channel_device::device_start() { - intc = siblingdevice(intc_tag); - if(chain_tag) - chained_timer = siblingdevice(chain_tag); + m_intc = siblingdevice(m_intc_tag); + if(m_chain_tag) + m_chained_timer = siblingdevice(m_chain_tag); else - chained_timer = nullptr; + m_chained_timer = nullptr; } void h8_timer8_channel_device::device_reset() { - tcr = 0x00; - tcsr = has_adte || has_ice ? 0x00 : 0x10; - tcor[0] = 0xff; - tcor[1] = 0xff; - tcnt = 0x00; - counter_cycle = 0x100; - clock_type = STOPPED; - clock_divider = 0; - clear_type = CLEAR_NONE; - last_clock_update = 0; - event_time = 0; - extra_clock_bit = false; + m_tcr = 0x00; + m_tcsr = m_has_adte || m_has_ice ? 0x00 : 0x10; + m_tcor[0] = 0xff; + m_tcor[1] = 0xff; + m_tcnt = 0x00; + m_counter_cycle = 0x100; + m_clock_type = STOPPED; + m_clock_divider = 0; + m_clear_type = CLEAR_NONE; + m_last_clock_update = 0; + m_event_time = 0; + m_extra_clock_bit = false; } uint64_t h8_timer8_channel_device::internal_update(uint64_t current_time) { - if(event_time && current_time >= event_time) { + if(m_event_time && current_time >= m_event_time) { update_counter(current_time); recalc_event(current_time); } - return event_time; + return m_event_time; } void h8_timer8_channel_device::update_counter(uint64_t cur_time) { - if(clock_type != DIV) + if(m_clock_type != DIV) return; if(!cur_time) - cur_time = cpu->total_cycles(); + cur_time = m_cpu->total_cycles(); - uint64_t base_time = (last_clock_update + clock_divider/2) / clock_divider; - uint64_t new_time = (cur_time + clock_divider/2) / clock_divider; + uint64_t base_time = (m_last_clock_update + m_clock_divider/2) / m_clock_divider; + uint64_t new_time = (cur_time + m_clock_divider/2) / m_clock_divider; - int tt = tcnt + new_time - base_time; - tcnt = tt % counter_cycle; + int tt = m_tcnt + new_time - base_time; + m_tcnt = tt % m_counter_cycle; - if(tt == tcor[0] || tcnt == tcor[0]) { - if(chained_timer) - chained_timer->chained_timer_tcora(); + if(tt == m_tcor[0] || m_tcnt == m_tcor[0]) { + if(m_chained_timer) + m_chained_timer->chained_timer_tcora(); - if(!(tcsr & TCSR_CMFA)) { - tcsr |= TCSR_CMFA; - if(tcr & TCR_CMIEA) - intc->internal_interrupt(irq_ca); + if(!(m_tcsr & TCSR_CMFA)) { + m_tcsr |= TCSR_CMFA; + if(m_tcr & TCR_CMIEA) + m_intc->internal_interrupt(m_irq_ca); } } - if(!(tcsr & TCSR_CMFB) && (tt == tcor[1] || tcnt == tcor[1])) { - tcsr |= TCSR_CMFB; - if(tcr & TCR_CMIEB) - intc->internal_interrupt(irq_cb); + if(!(m_tcsr & TCSR_CMFB) && (tt == m_tcor[1] || m_tcnt == m_tcor[1])) { + m_tcsr |= TCSR_CMFB; + if(m_tcr & TCR_CMIEB) + m_intc->internal_interrupt(m_irq_cb); } if(tt >= 0x100) { - if(chained_timer) - chained_timer->chained_timer_overflow(); - if(!(tcsr & TCSR_OVF)) { - tcsr |= TCSR_OVF; - if(tcr & TCR_OVIE) - intc->internal_interrupt(irq_v); + if(m_chained_timer) + m_chained_timer->chained_timer_overflow(); + if(!(m_tcsr & TCSR_OVF)) { + m_tcsr |= TCSR_OVF; + if(m_tcr & TCR_OVIE) + m_intc->internal_interrupt(m_irq_v); } } - last_clock_update = cur_time; + m_last_clock_update = cur_time; } void h8_timer8_channel_device::recalc_event(uint64_t cur_time) { bool update_cpu = cur_time == 0; - uint64_t old_event_time = event_time; + uint64_t old_event_time = m_event_time; - if(clock_type != DIV) { - event_time = 0; + if(m_clock_type != DIV) { + m_event_time = 0; if(old_event_time && update_cpu) - cpu->internal_update(); + m_cpu->internal_update(); return; } if(!cur_time) - cur_time = cpu->total_cycles(); + cur_time = m_cpu->total_cycles(); uint32_t event_delay = 0xffffffff; - if(clear_type == CLEAR_A || clear_type == CLEAR_B) - counter_cycle = tcor[clear_type - CLEAR_A]; + if(m_clear_type == CLEAR_A || m_clear_type == CLEAR_B) + m_counter_cycle = m_tcor[m_clear_type - CLEAR_A]; else { - counter_cycle = 0x100; - event_delay = counter_cycle - tcnt; + m_counter_cycle = 0x100; + event_delay = m_counter_cycle - m_tcnt; if(!event_delay) - event_delay = counter_cycle; + event_delay = m_counter_cycle; } - for(auto & elem : tcor) { + for(auto &elem : m_tcor) { uint32_t new_delay = 0xffffffff; - if(elem > tcnt) { - if(tcnt >= counter_cycle || elem <= counter_cycle) - new_delay = elem - tcnt; - } else if(elem <= counter_cycle) { - if(tcnt < counter_cycle) - new_delay = (counter_cycle - tcnt) + elem; + if(elem > m_tcnt) { + if(m_tcnt >= m_counter_cycle || elem <= m_counter_cycle) + new_delay = elem - m_tcnt; + } else if(elem <= m_counter_cycle) { + if(m_tcnt < m_counter_cycle) + new_delay = (m_counter_cycle - m_tcnt) + elem; else - new_delay = (0x100 - tcnt) + elem; + new_delay = (0x100 - m_tcnt) + elem; } if(event_delay > new_delay) event_delay = new_delay; } if(event_delay != 0xffffffff) - event_time = ((((cur_time + clock_divider) / clock_divider) + event_delay - 1) * clock_divider) + clock_divider/2; + m_event_time = ((((cur_time + m_clock_divider) / m_clock_divider) + event_delay - 1) * m_clock_divider) + m_clock_divider/2; else - event_time = 0; + m_event_time = 0; - if(old_event_time != event_time && update_cpu) - cpu->internal_update(); + if(old_event_time != m_event_time && update_cpu) + m_cpu->internal_update(); } void h8_timer8_channel_device::chained_timer_overflow() { - if(clock_type == CHAIN_OVERFLOW) + if(m_clock_type == CHAIN_OVERFLOW) timer_tick(); } void h8_timer8_channel_device::chained_timer_tcora() { - if(clock_type == CHAIN_A) + if(m_clock_type == CHAIN_A) timer_tick(); } void h8_timer8_channel_device::timer_tick() { - tcnt++; + m_tcnt++; - if(tcnt == tcor[0]) { - if(chained_timer) - chained_timer->chained_timer_tcora(); + if(m_tcnt == m_tcor[0]) { + if(m_chained_timer) + m_chained_timer->chained_timer_tcora(); - if(!(tcsr & TCSR_CMFA)) { - tcsr |= TCSR_CMFA; - if(tcr & TCR_CMIEA) - intc->internal_interrupt(irq_ca); + if(!(m_tcsr & TCSR_CMFA)) { + m_tcsr |= TCSR_CMFA; + if(m_tcr & TCR_CMIEA) + m_intc->internal_interrupt(m_irq_ca); } } - if(!(tcsr & TCSR_CMFB) && tcnt == tcor[1]) { - tcsr |= TCSR_CMFB; - if(tcr & TCR_CMIEB) - intc->internal_interrupt(irq_cb); + if(!(m_tcsr & TCSR_CMFB) && m_tcnt == m_tcor[1]) { + m_tcsr |= TCSR_CMFB; + if(m_tcr & TCR_CMIEB) + m_intc->internal_interrupt(m_irq_cb); } - if(tcnt == 0x00) { - if(chained_timer) - chained_timer->chained_timer_overflow(); - if(!(tcsr & TCSR_OVF)) { - tcsr |= TCSR_OVF; - if(tcr & TCR_OVIE) - intc->internal_interrupt(irq_v); + if(m_tcnt == 0x00) { + if(m_chained_timer) + m_chained_timer->chained_timer_overflow(); + if(!(m_tcsr & TCSR_OVF)) { + m_tcsr |= TCSR_OVF; + if(m_tcr & TCR_OVIE) + m_intc->internal_interrupt(m_irq_v); } } } @@ -360,21 +360,21 @@ h8h_timer8_channel_device::~h8h_timer8_channel_device() { } -void h8h_timer8_channel_device::set_info(const char *intc, int _irq_ca, int _irq_cb, int _irq_v, const char *_chain_tag, int _chain_type, bool _has_adte, bool _has_ice) +void h8h_timer8_channel_device::set_info(const char *intc, int irq_ca, int irq_cb, int irq_v, const char *chain_tag, int chain_type, bool has_adte, bool has_ice) { - intc_tag = intc; - irq_ca = _irq_ca; - irq_cb = _irq_cb; - irq_v = _irq_v; - chain_tag = _chain_tag; - chain_type = _chain_type; - has_adte = _has_adte; - has_ice = _has_ice; + m_intc_tag = intc; + m_irq_ca = irq_ca; + m_irq_cb = irq_cb; + m_irq_v = irq_v; + m_chain_tag = chain_tag; + m_chain_type = chain_type; + m_has_adte = has_adte; + m_has_ice = has_ice; // The extra clock bit is not used for h8h+ - div_tab[0] = 8; - div_tab[1] = 8; - div_tab[2] = 64; - div_tab[3] = 64; - div_tab[4] = 8192; - div_tab[5] = 8192; + m_div_tab[0] = 8; + m_div_tab[1] = 8; + m_div_tab[2] = 64; + m_div_tab[3] = 64; + m_div_tab[4] = 8192; + m_div_tab[5] = 8192; } diff --git a/src/devices/cpu/h8/h8_timer8.h b/src/devices/cpu/h8/h8_timer8.h index 0ba06d933ba..3c269f479fe 100644 --- a/src/devices/cpu/h8/h8_timer8.h +++ b/src/devices/cpu/h8/h8_timer8.h @@ -76,17 +76,17 @@ protected: CLEAR_EXTERNAL }; - required_device cpu; - h8_timer8_channel_device *chained_timer; - h8_intc_device *intc; - const char *chain_tag, *intc_tag; - int irq_ca, irq_cb, irq_v, chain_type; - int div_tab[6]; - uint8_t tcor[2]; - uint8_t tcr, tcsr, tcnt; - bool extra_clock_bit, has_adte, has_ice; - int clock_type, clock_divider, clear_type, counter_cycle; - uint64_t last_clock_update, event_time; + required_device m_cpu; + h8_timer8_channel_device *m_chained_timer; + h8_intc_device *m_intc; + const char *m_chain_tag, *m_intc_tag; + int m_irq_ca, m_irq_cb, m_irq_v, m_chain_type; + int m_div_tab[6]; + uint8_t m_tcor[2]; + uint8_t m_tcr, m_tcsr, m_tcnt; + bool m_extra_clock_bit, m_has_adte, m_has_ice; + int m_clock_type, m_clock_divider, m_clear_type, m_counter_cycle; + uint64_t m_last_clock_update, m_event_time; h8_timer8_channel_device(const machine_config &mconfig, device_type type, const char *tag, device_t *owner, uint32_t clock); diff --git a/src/devices/cpu/h8/h8_watchdog.cpp b/src/devices/cpu/h8/h8_watchdog.cpp index d3386b465fe..9cb8b6bd57f 100644 --- a/src/devices/cpu/h8/h8_watchdog.cpp +++ b/src/devices/cpu/h8/h8_watchdog.cpp @@ -8,25 +8,25 @@ const int h8_watchdog_device::div_s [8] = { 1, 5, 6, 7, 8, 9, 11, 12 }; h8_watchdog_device::h8_watchdog_device(const machine_config &mconfig, const char *tag, device_t *owner, uint32_t clock) : device_t(mconfig, H8_WATCHDOG, tag, owner, clock), - cpu(*this, DEVICE_SELF_OWNER) + m_cpu(*this, DEVICE_SELF_OWNER) { } -void h8_watchdog_device::set_info(const char *_intc_tag, int _irq, int _type) +void h8_watchdog_device::set_info(const char *intc_tag, int irq, int type) { - intc_tag = _intc_tag; - irq = _irq; - type = _type; + m_intc_tag = intc_tag; + m_irq = irq; + m_type = type; } uint64_t h8_watchdog_device::internal_update(uint64_t current_time) { tcnt_update(current_time); - if(tcsr & TCSR_TME) { - int shift = (type == S ? div_s : div_bh)[tcsr & TCSR_CKS]; - uint64_t spos = tcnt_cycle_base >> shift; - return (spos + 0x100 - tcnt) << shift; + if(m_tcsr & TCSR_TME) { + int shift = (m_type == S ? div_s : div_bh)[m_tcsr & TCSR_CKS]; + uint64_t spos = m_tcnt_cycle_base >> shift; + return (spos + 0x100 - m_tcnt) << shift; } else return 0; @@ -34,42 +34,42 @@ uint64_t h8_watchdog_device::internal_update(uint64_t current_time) void h8_watchdog_device::tcnt_update(uint64_t cur_time) { - if(tcsr & TCSR_TME) { - int shift = (type == S ? div_s : div_bh)[tcsr & TCSR_CKS]; + if(m_tcsr & TCSR_TME) { + int shift = (m_type == S ? div_s : div_bh)[m_tcsr & TCSR_CKS]; if(!cur_time) - cur_time = cpu->total_cycles(); - uint64_t spos = tcnt_cycle_base >> shift; + cur_time = m_cpu->total_cycles(); + uint64_t spos = m_tcnt_cycle_base >> shift; uint64_t epos = cur_time >> shift; - int next_tcnt = tcnt + int(epos - spos); - tcnt = next_tcnt; - tcnt_cycle_base = cur_time; - // logerror("%10lld tcnt %02x -> %03x shift=%d\n", cur_time, tcnt, next_tcnt, shift); + int next_tcnt = m_tcnt + int(epos - spos); + m_tcnt = next_tcnt; + m_tcnt_cycle_base = cur_time; + // logerror("%10lld tcnt %02x -> %03x shift=%d\n", cur_time, m_tcnt, next_tcnt, shift); if(next_tcnt >= 0x100) { - if(tcsr & TCSR_WT) { + if(m_tcsr & TCSR_WT) { logerror("%s watchdog triggered\n", machine().time().as_string()); - if(type == B && !(tcsr & TCSR_NMI)) - intc->internal_interrupt(3); + if(m_type == B && !(m_tcsr & TCSR_NMI)) + m_intc->internal_interrupt(3); else - cpu->reset(); + m_cpu->reset(); } else { - if(!(tcsr & TCSR_OVF)) { - tcsr |= TCSR_OVF; - intc->internal_interrupt(irq); + if(!(m_tcsr & TCSR_OVF)) { + m_tcsr |= TCSR_OVF; + m_intc->internal_interrupt(m_irq); } } } } else - tcnt = 0; + m_tcnt = 0; } uint16_t h8_watchdog_device::wd_r() { - if (!machine().side_effects_disabled()) + if(!machine().side_effects_disabled()) tcnt_update(); - return (tcsr << 8) | tcnt; + return (m_tcsr << 8) | m_tcnt; } void h8_watchdog_device::wd_w(offs_t offset, uint16_t data, uint16_t mem_mask) @@ -79,26 +79,26 @@ void h8_watchdog_device::wd_w(offs_t offset, uint16_t data, uint16_t mem_mask) if((data & 0xff00) == 0xa500) { tcnt_update(); - if(!(tcsr & TCSR_TME) && (data & TCSR_TME)) - tcnt_cycle_base = cpu->total_cycles(); - tcsr = data & 0xff; - tcsr |= type == B ? 0x10 : 0x18; - cpu->internal_update(); + if(!(m_tcsr & TCSR_TME) && (data & TCSR_TME)) + m_tcnt_cycle_base = m_cpu->total_cycles(); + m_tcsr = data & 0xff; + m_tcsr |= m_type == B ? 0x10 : 0x18; + m_cpu->internal_update(); } if((data & 0xff00) == 0x5a00) { - if(tcsr & TCSR_TME) { - tcnt = data & 0xff; - tcnt_cycle_base = cpu->total_cycles(); - // logerror("%10lld tcnt = %02x\n", tcnt_cycle_base, tcnt); + if(m_tcsr & TCSR_TME) { + m_tcnt = data & 0xff; + m_tcnt_cycle_base = m_cpu->total_cycles(); + // logerror("%10lld tcnt = %02x\n", m_tcnt_cycle_base, m_tcnt); } - cpu->internal_update(); + m_cpu->internal_update(); } } uint16_t h8_watchdog_device::rst_r() { - if (!machine().side_effects_disabled()) + if(!machine().side_effects_disabled()) logerror("rst_r\n"); return 0; } @@ -113,13 +113,13 @@ void h8_watchdog_device::rst_w(uint16_t data) void h8_watchdog_device::device_start() { - intc = siblingdevice(intc_tag); + m_intc = siblingdevice(m_intc_tag); } void h8_watchdog_device::device_reset() { - tcnt = 0x00; - tcnt_cycle_base = cpu->total_cycles(); - tcsr = type == B ? 0x10 : 0x18; - rst = type == S ? 0x1f : 0x3f; + m_tcnt = 0x00; + m_tcnt_cycle_base = m_cpu->total_cycles(); + m_tcsr = m_type == B ? 0x10 : 0x18; + m_rst = m_type == S ? 0x1f : 0x3f; } diff --git a/src/devices/cpu/h8/h8_watchdog.h b/src/devices/cpu/h8/h8_watchdog.h index 1cb63025141..919df5c5a1b 100644 --- a/src/devices/cpu/h8/h8_watchdog.h +++ b/src/devices/cpu/h8/h8_watchdog.h @@ -86,13 +86,13 @@ private: static const int div_bh[8]; static const int div_s[8]; - required_device cpu; - h8_intc_device *intc; - const char *intc_tag; - int irq; - int type; - uint8_t tcnt, tcsr, rst; - uint64_t tcnt_cycle_base; + required_device m_cpu; + h8_intc_device *m_intc; + const char *m_intc_tag; + int m_irq; + int m_type; + uint8_t m_tcnt, m_tcsr, m_rst; + uint64_t m_tcnt_cycle_base; void tcnt_update(uint64_t current_time = 0); }; diff --git a/src/devices/cpu/h8/h8d.cpp b/src/devices/cpu/h8/h8d.cpp index 0009ec189fa..a6d5bb503c0 100644 --- a/src/devices/cpu/h8/h8d.cpp +++ b/src/devices/cpu/h8/h8d.cpp @@ -12,7 +12,7 @@ #include "h8d.h" #include "cpu/h8/h8d.hxx" -h8_disassembler::h8_disassembler(const disasm_entry *_table, bool _advanced) : table(_table), advanced(_advanced) +h8_disassembler::h8_disassembler(const disasm_entry *table, bool advanced) : m_table(table), m_advanced(advanced) { } @@ -141,7 +141,7 @@ void h8_disassembler::disassemble_am(std::ostream &stream, int am, offs_t pc, co break; case DASM_abs8: - if (advanced) + if(m_advanced) util::stream_format(stream, "@h'%06x", 0xffff00 | opcodes.r8(pc+1)); else util::stream_format(stream, "@h'%04x", 0xff00 | opcodes.r8(pc+1)); @@ -150,14 +150,14 @@ void h8_disassembler::disassemble_am(std::ostream &stream, int am, offs_t pc, co case DASM_abs16: if(slot == 3) { - if (advanced) + if(m_advanced) util::stream_format(stream, "@h'%06x", s32(s16(opcodes.r16(epc-4))) & 0xffffff); else util::stream_format(stream, "@h'%04x", opcodes.r16(epc-4)); } else { - if (advanced) + if(m_advanced) util::stream_format(stream, "@h'%06x", s32(s16(opcodes.r16(epc-2))) & 0xffffff); else util::stream_format(stream, "@h'%04x", opcodes.r16(epc-2)); @@ -188,14 +188,14 @@ void h8_disassembler::disassemble_am(std::ostream &stream, int am, offs_t pc, co break; case DASM_rel8: - if (advanced) + if(m_advanced) util::stream_format(stream, "h'%06x", (pc + 2 + s8(opcodes.r8(pc+1))) & 0xffffff); else util::stream_format(stream, "h'%04x", (pc + 2 + s8(opcodes.r8(pc+1))) & 0xffff); break; case DASM_rel16: - if (advanced) + if(m_advanced) util::stream_format(stream, "h'%06x", (pc + 4 + s16(opcodes.r16(pc+2))) & 0xffffff); else util::stream_format(stream, "h'%04x", (pc + 4 + s16(opcodes.r16(pc+2))) & 0xffff); @@ -278,20 +278,20 @@ offs_t h8_disassembler::disassemble(std::ostream &stream, offs_t pc, const data_ int inst; for(inst=0;; inst++) { - const disasm_entry &e = table[inst]; - if((slot[e.slot] & e.mask) == e.val && (slot[0] & e.mask0) == e.val0) + const disasm_entry &e = m_table[inst]; + if((slot[e.m_slot] & e.m_mask) == e.m_val && (slot[0] & e.m_mask0) == e.m_val0) break; } - const disasm_entry &e = table[inst]; - if(e.am1 == DASM_none) - stream << e.opcode; + const disasm_entry &e = m_table[inst]; + if(e.m_am1 == DASM_none) + stream << e.m_opcode; else { - util::stream_format(stream, "%-08s", e.opcode); - disassemble_am(stream, e.am1, pc, opcodes, slot[e.slot], e.slot, e.flags & LENGTHMASK); - if(e.am2 != DASM_none) { + util::stream_format(stream, "%-08s", e.m_opcode); + disassemble_am(stream, e.m_am1, pc, opcodes, slot[e.m_slot], e.m_slot, e.m_flags & LENGTHMASK); + if(e.m_am2 != DASM_none) { stream << ", "; - disassemble_am(stream, e.am2, pc, opcodes, slot[e.slot], e.slot, e.flags & LENGTHMASK); + disassemble_am(stream, e.m_am2, pc, opcodes, slot[e.m_slot], e.m_slot, e.m_flags & LENGTHMASK); } } - return e.flags | SUPPORTED; + return e.m_flags | SUPPORTED; } diff --git a/src/devices/cpu/h8/h8d.h b/src/devices/cpu/h8/h8d.h index bd28feff96c..e2e437033f2 100644 --- a/src/devices/cpu/h8/h8d.h +++ b/src/devices/cpu/h8/h8d.h @@ -17,16 +17,16 @@ class h8_disassembler : public util::disasm_interface { protected: struct disasm_entry { - int slot; - u32 val, mask; - u16 val0, mask0; - const char *opcode; - int am1, am2; - offs_t flags; + int m_slot; + u32 m_val, m_mask; + u16 m_val0, m_mask0; + const char *m_opcode; + int m_am1, m_am2; + offs_t m_flags; }; public: - h8_disassembler(const disasm_entry *_table, bool _advanced); + h8_disassembler(const disasm_entry *table, bool advanced); h8_disassembler(); virtual u32 opcode_alignment() const override; @@ -97,8 +97,8 @@ protected: void disassemble_am(std::ostream &stream, int am, offs_t pc, const data_buffer &opcodes, u32 opcode, int slot, int offset); - const disasm_entry *const table; - const bool advanced; + const disasm_entry *const m_table; + const bool m_advanced; static const disasm_entry disasm_entries[]; }; diff --git a/src/devices/cpu/h8/h8h.cpp b/src/devices/cpu/h8/h8h.cpp index 21f40f77600..80ddd60c824 100644 --- a/src/devices/cpu/h8/h8h.cpp +++ b/src/devices/cpu/h8/h8h.cpp @@ -7,8 +7,8 @@ h8h_device::h8h_device(const machine_config &mconfig, device_type type, const char *tag, device_t *owner, uint32_t clock, address_map_constructor map_delegate) : h8_device(mconfig, type, tag, owner, clock, map_delegate) { - supports_advanced = true; - mode_advanced = true; + m_supports_advanced = true; + m_mode_advanced = true; } std::unique_ptr h8h_device::create_disassembler() diff --git a/src/devices/cpu/h8/h8h.h b/src/devices/cpu/h8/h8h.h index 1b0c9b4b3ce..eff0b712300 100644 --- a/src/devices/cpu/h8/h8h.h +++ b/src/devices/cpu/h8/h8h.h @@ -27,8 +27,8 @@ protected: virtual void do_exec_full() override; virtual void do_exec_partial() override; - inline void r32_w(int reg, uint32_t val) { R[reg & 7] = val; R[(reg & 7) | 8] = val >> 16; } - inline uint32_t r32_r(int reg) const { return R[reg & 7] | (R[(reg & 7) | 8] << 16); } + inline void r32_w(int reg, uint32_t val) { m_R[reg & 7] = val; m_R[(reg & 7) | 8] = val >> 16; } + inline uint32_t r32_r(int reg) const { return m_R[reg & 7] | (m_R[(reg & 7) | 8] << 16); } #define O(o) void o ## _full(); void o ## _partial() diff --git a/src/devices/cpu/h8/h8make.py b/src/devices/cpu/h8/h8make.py index 0d09dbf3b9f..728dadc5953 100644 --- a/src/devices/cpu/h8/h8make.py +++ b/src/devices/cpu/h8/h8make.py @@ -69,17 +69,17 @@ def save_full_one(f, t, name, source): for line in source: if has_memory(line): print(line, file=f) - print("\tif(icount <= bcount) {", file=f) + print("\tif(m_icount <= m_bcount) {", file=f) print("\t\tif(access_to_be_redone()) {", file=f) - print("\t\t\ticount++;", file=f) - print("\t\t\tinst_substate = %d;" % substate, file=f) + print("\t\t\tm_icount++;", file=f) + print("\t\t\tm_inst_substate = %d;" % substate, file=f) print("\t\t} else", file=f) - print("\t\t\tinst_substate = %d;" % (substate+1), file=f) + print("\t\t\tm_inst_substate = %d;" % (substate+1), file=f) print("\t\treturn;", file=f) print("\t}", file=f) substate += 2 elif has_eat(line): - print("\tif(icount) { icount = bcount; } inst_substate = %d; return;" % substate, file=f) + print("\tif(m_icount) { m_icount = m_bcount; } m_inst_substate = %d; return;" % substate, file=f) substate += 1 else: print(line, file=f) @@ -89,7 +89,7 @@ def save_full_one(f, t, name, source): def save_partial_one(f, t, name, source): print("void %s::%s_partial()" % (t, name), file=f) print("{", file=f) - print("switch(inst_substate) {", file=f) + print("switch(m_inst_substate) {", file=f) print("case 0:", file=f) substate = 1 for line in source: @@ -97,26 +97,26 @@ def save_partial_one(f, t, name, source): print("\t[[fallthrough]];", file=f) print("case %d:;" % substate, file=f) print(line, file=f) - print("\tif(icount <= bcount) {", file=f) + print("\tif(m_icount <= m_bcount) {", file=f) print("\t\tif(access_to_be_redone()) {", file=f) - print("\t\t\ticount++;", file=f) - print("\t\t\tinst_substate = %d;" % substate, file=f) + print("\t\t\tm_icount++;", file=f) + print("\t\t\tm_inst_substate = %d;" % substate, file=f) print("\t\t} else", file=f) - print("\t\t\tinst_substate = %d;" % (substate+1), file=f) + print("\t\t\tm_inst_substate = %d;" % (substate+1), file=f) print("\t\treturn;", file=f) print("\t}", file=f) print("\t[[fallthrough]];", file=f) print("case %d:;" % (substate+1), file=f) substate += 2 elif has_eat(line): - print("\tif(icount) { icount = bcount; } inst_substate = %d; return;" % substate, file=f) + print("\tif(m_icount) { m_icount = m_bcount; } m_inst_substate = %d; return;" % substate, file=f) print("case %d:;" % substate, file=f) substate += 1 else: print(line, file=f) print("\tbreak;", file=f) print("}", file=f) - print("\tinst_substate = 0;", file=f) + print("\tm_inst_substate = 0;", file=f) print("}", file=f) print("", file=f) @@ -172,8 +172,8 @@ class Opcode: self.extra_words = extra_words base_offset = len(self.val)/2 + self.skip for i in range(0, extra_words): - self.source.append("\tIR[%d] = read16i(PC);" % (i+base_offset)) - self.source.append("\tPC += 2;") + self.source.append("\tm_IR[%d] = read16i(m_PC);" % (i+base_offset)) + self.source.append("\tm_PC += 2;") def description(self): return "%s %s %s" % (self.name, self.am1, self.am2) @@ -286,9 +286,9 @@ class DispatchStep: end = start + self.skip s = [] for i in range(start, end+1): - s.append("\tIR[%d] = read16i(PC);" % i) - s.append("\tPC += 2;") - s.append("\tinst_state = 0x%x0000 | IR[%d];" % (self.id, end)) + s.append("\tm_IR[%d] = read16i(m_PC);" % i) + s.append("\tm_PC += 2;") + s.append("\tm_inst_state = 0x%x0000 | m_IR[%d];" % (self.id, end)) return s @@ -411,11 +411,11 @@ class OpcodeList: def save_exec(self, f, t, dtype, v): print("void %s::do_exec_%s()" % (t, v), file=f) print("{", file=f) - print("\tswitch(inst_state >> 16) {", file=f) + print("\tswitch(m_inst_state >> 16) {", file=f) for i in range(0, len(self.dispatch_info)+2): if i == 1: print("\tcase 0x01: {", file=f) - print("\t\tswitch(inst_state & 0xffff) {", file=f) + print("\t\tswitch(m_inst_state & 0xffff) {", file=f) for sta in self.states_info: if sta.enabled: print("\t\tcase 0x%02x: state_%s_%s(); break;" % (sta.val & 0xffff, sta.name, v), file=f) @@ -426,7 +426,7 @@ class OpcodeList: if i == 0 or self.dispatch_info[i-2].enabled: print("\tcase 0x%02x: {" % i, file=f) h = self.get(i) - print("\t\tswitch((inst_state >> 8) & 0x%02x) {" % h.mask, file=f) + print("\t\tswitch((m_inst_state >> 8) & 0x%02x) {" % h.mask, file=f) for val, h2 in sorted(h.d.items()): if h2.enabled: fmask = h2.premask | (h.mask ^ 0xff) @@ -446,7 +446,7 @@ class OpcodeList: print("\t\t\t%s_%s();" % (n.function_name(), v), file=f) print("\t\t\tbreak;", file=f) else: - print("\t\t\tswitch(inst_state & 0x%02x) {" % h2.mask, file=f) + print("\t\t\tswitch(m_inst_state & 0x%02x) {" % h2.mask, file=f) if i == 0: mpos = 1 else: diff --git a/src/devices/cpu/h8/h8s2000.cpp b/src/devices/cpu/h8/h8s2000.cpp index 04da92cdee3..e7b87d7963d 100644 --- a/src/devices/cpu/h8/h8s2000.cpp +++ b/src/devices/cpu/h8/h8s2000.cpp @@ -7,7 +7,7 @@ h8s2000_device::h8s2000_device(const machine_config &mconfig, device_type type, const char *tag, device_t *owner, uint32_t clock, address_map_constructor map_delegate) : h8h_device(mconfig, type, tag, owner, clock, map_delegate) { - has_exr = true; + m_has_exr = true; } std::unique_ptr h8s2000_device::create_disassembler() diff --git a/src/devices/cpu/h8/h8s2245.cpp b/src/devices/cpu/h8/h8s2245.cpp index b3531945110..6c02fb551a3 100644 --- a/src/devices/cpu/h8/h8s2245.cpp +++ b/src/devices/cpu/h8/h8s2245.cpp @@ -11,33 +11,33 @@ DEFINE_DEVICE_TYPE(H8S2246, h8s2246_device, "h8s2246", "Hitachi H8S/2246") h8s2245_device::h8s2245_device(const machine_config &mconfig, device_type type, const char *tag, device_t *owner, uint32_t clock, uint32_t start) : h8s2000_device(mconfig, type, tag, owner, clock, address_map_constructor(FUNC(h8s2245_device::map), this)), - intc(*this, "intc"), - adc(*this, "adc"), - dtc(*this, "dtc"), - port1(*this, "port1"), - port2(*this, "port2"), - port3(*this, "port3"), - port4(*this, "port4"), - port5(*this, "port5"), - porta(*this, "porta"), - portb(*this, "portb"), - portc(*this, "portc"), - portd(*this, "portd"), - porte(*this, "porte"), - portf(*this, "portf"), - portg(*this, "portg"), - timer8_0(*this, "timer8_0"), - timer8_1(*this, "timer8_1"), - timer16(*this, "timer16"), - timer16_0(*this, "timer16:0"), - timer16_1(*this, "timer16:1"), - timer16_2(*this, "timer16:2"), - sci0(*this, "sci0"), - sci1(*this, "sci1"), - sci2(*this, "sci2"), - watchdog(*this, "watchdog"), - ram_start(start), - syscr(0) + m_intc(*this, "intc"), + m_adc(*this, "adc"), + m_dtc(*this, "dtc"), + m_port1(*this, "port1"), + m_port2(*this, "port2"), + m_port3(*this, "port3"), + m_port4(*this, "port4"), + m_port5(*this, "port5"), + m_porta(*this, "porta"), + m_portb(*this, "portb"), + m_portc(*this, "portc"), + m_portd(*this, "portd"), + m_porte(*this, "porte"), + m_portf(*this, "portf"), + m_portg(*this, "portg"), + m_timer8_0(*this, "timer8_0"), + m_timer8_1(*this, "timer8_1"), + m_timer16(*this, "timer16"), + m_timer16_0(*this, "timer16:0"), + m_timer16_1(*this, "timer16:1"), + m_timer16_2(*this, "timer16:2"), + m_sci0(*this, "sci0"), + m_sci1(*this, "sci1"), + m_sci2(*this, "sci2"), + m_watchdog(*this, "watchdog"), + m_ram_start(start), + m_syscr(0) { } @@ -63,7 +63,7 @@ h8s2246_device::h8s2246_device(const machine_config &mconfig, const char *tag, d void h8s2245_device::map(address_map &map) { - map(ram_start, 0xfffbff).ram(); + map(m_ram_start, 0xfffbff).ram(); map(0xfffeb0, 0xfffeb0).w("port1", FUNC(h8_port_device::ddr_w)); map(0xfffeb1, 0xfffeb1).w("port2", FUNC(h8_port_device::ddr_w)); @@ -231,7 +231,7 @@ void h8s2245_device::device_add_mconfig(machine_config &config) void h8s2245_device::execute_set_input(int inputnum, int state) { - intc->set_input(inputnum, state); + m_intc->set_input(inputnum, state); } bool h8s2245_device::exr_in_stack() const @@ -241,64 +241,64 @@ bool h8s2245_device::exr_in_stack() const int h8s2245_device::trapa_setup() { - if(syscr & 0x10) - CCR |= F_I|F_UI; + if(m_syscr & 0x10) + m_CCR |= F_I|F_UI; else - CCR |= F_I; + m_CCR |= F_I; return 8; } void h8s2245_device::irq_setup() { - switch(syscr & 0x30) { + switch(m_syscr & 0x30) { case 0x00: - CCR |= F_I; + m_CCR |= F_I; break; case 0x10: - CCR |= F_I|F_UI; + m_CCR |= F_I|F_UI; break; } } void h8s2245_device::update_irq_filter() { - switch(syscr & 0x30) { + switch(m_syscr & 0x30) { case 0x00: - if(CCR & F_I) - intc->set_filter(2, -1); + if(m_CCR & F_I) + m_intc->set_filter(2, -1); else - intc->set_filter(0, -1); + m_intc->set_filter(0, -1); break; case 0x10: - if((CCR & (F_I|F_UI)) == (F_I|F_UI)) - intc->set_filter(2, -1); - else if(CCR & F_I) - intc->set_filter(1, -1); + if((m_CCR & (F_I|F_UI)) == (F_I|F_UI)) + m_intc->set_filter(2, -1); + else if(m_CCR & F_I) + m_intc->set_filter(1, -1); else - intc->set_filter(0, -1); + m_intc->set_filter(0, -1); break; } } void h8s2245_device::interrupt_taken() { - standard_irq_callback(intc->interrupt_taken(taken_irq_vector), NPC); + standard_irq_callback(m_intc->interrupt_taken(m_taken_irq_vector), m_NPC); } void h8s2245_device::internal_update(uint64_t current_time) { uint64_t event_time = 0; - add_event(event_time, adc->internal_update(current_time)); - add_event(event_time, sci0->internal_update(current_time)); - add_event(event_time, sci1->internal_update(current_time)); - add_event(event_time, sci2->internal_update(current_time)); - add_event(event_time, timer8_0->internal_update(current_time)); - add_event(event_time, timer8_1->internal_update(current_time)); - add_event(event_time, timer16_0->internal_update(current_time)); - add_event(event_time, timer16_1->internal_update(current_time)); - add_event(event_time, timer16_2->internal_update(current_time)); - add_event(event_time, watchdog->internal_update(current_time)); + add_event(event_time, m_adc->internal_update(current_time)); + add_event(event_time, m_sci0->internal_update(current_time)); + add_event(event_time, m_sci1->internal_update(current_time)); + add_event(event_time, m_sci2->internal_update(current_time)); + add_event(event_time, m_timer8_0->internal_update(current_time)); + add_event(event_time, m_timer8_1->internal_update(current_time)); + add_event(event_time, m_timer16_0->internal_update(current_time)); + add_event(event_time, m_timer16_1->internal_update(current_time)); + add_event(event_time, m_timer16_2->internal_update(current_time)); + add_event(event_time, m_watchdog->internal_update(current_time)); recompute_bcount(event_time); } @@ -306,47 +306,47 @@ void h8s2245_device::internal_update(uint64_t current_time) void h8s2245_device::device_start() { h8s2000_device::device_start(); - dtc_device = dtc; + m_dtc_device = m_dtc; } void h8s2245_device::device_reset() { h8s2000_device::device_reset(); - syscr = 0x01; - mstpcr = 0x3fff; + m_syscr = 0x01; + m_mstpcr = 0x3fff; } uint8_t h8s2245_device::syscr_r() { - return syscr; + return m_syscr; } void h8s2245_device::syscr_w(uint8_t data) { - syscr = data; + m_syscr = data; update_irq_filter(); logerror("syscr = %02x\n", data); } uint16_t h8s2245_device::mstpcr_r() { - return mstpcr; + return m_mstpcr; } void h8s2245_device::mstpcr_w(offs_t offset, uint16_t data, uint16_t mem_mask) { - uint16_t omstpcr = mstpcr; - COMBINE_DATA(&mstpcr); - if((omstpcr ^ mstpcr) & 0x72e0) { + uint16_t omstpcr = m_mstpcr; + COMBINE_DATA(&m_mstpcr); + if((omstpcr ^ m_mstpcr) & 0x72e0) { std::ostringstream message; message << "Online modules:"; - if(mstpcr & 0x0020) message << " sci0"; - if(mstpcr & 0x0040) message << " sci1"; - if(mstpcr & 0x0080) message << " sci2"; - if(mstpcr & 0x0200) message << " adc"; - if(mstpcr & 0x1000) message << " timer8"; - if(mstpcr & 0x2000) message << " timer16"; - if(mstpcr & 0x4000) message << " dtc"; + if(m_mstpcr & 0x0020) message << " sci0"; + if(m_mstpcr & 0x0040) message << " sci1"; + if(m_mstpcr & 0x0080) message << " sci2"; + if(m_mstpcr & 0x0200) message << " adc"; + if(m_mstpcr & 0x1000) message << " timer8"; + if(m_mstpcr & 0x2000) message << " timer16"; + if(m_mstpcr & 0x4000) message << " dtc"; message << "\n"; logerror(std::move(message).str()); } diff --git a/src/devices/cpu/h8/h8s2245.h b/src/devices/cpu/h8/h8s2245.h index 4fca522bbc5..24e06ffd4ba 100644 --- a/src/devices/cpu/h8/h8s2245.h +++ b/src/devices/cpu/h8/h8s2245.h @@ -43,35 +43,35 @@ public: void mstpcr_w(offs_t offset, uint16_t data, uint16_t mem_mask = ~0); protected: - required_device intc; - required_device adc; - required_device dtc; - required_device port1; - required_device port2; - required_device port3; - required_device port4; - required_device port5; - required_device porta; - required_device portb; - required_device portc; - required_device portd; - required_device porte; - required_device portf; - required_device portg; - required_device timer8_0; - required_device timer8_1; - required_device timer16; - required_device timer16_0; - required_device timer16_1; - required_device timer16_2; - required_device sci0; - required_device sci1; - required_device sci2; - required_device watchdog; - - uint32_t ram_start; - uint16_t mstpcr; - uint8_t syscr; + required_device m_intc; + required_device m_adc; + required_device m_dtc; + required_device m_port1; + required_device m_port2; + required_device m_port3; + required_device m_port4; + required_device m_port5; + required_device m_porta; + required_device m_portb; + required_device m_portc; + required_device m_portd; + required_device m_porte; + required_device m_portf; + required_device m_portg; + required_device m_timer8_0; + required_device m_timer8_1; + required_device m_timer16; + required_device m_timer16_0; + required_device m_timer16_1; + required_device m_timer16_2; + required_device m_sci0; + required_device m_sci1; + required_device m_sci2; + required_device m_watchdog; + + uint32_t m_ram_start; + uint16_t m_mstpcr; + uint8_t m_syscr; h8s2245_device(const machine_config &mconfig, device_type type, const char *tag, device_t *owner, uint32_t clock, uint32_t start); diff --git a/src/devices/cpu/h8/h8s2320.cpp b/src/devices/cpu/h8/h8s2320.cpp index aacc18de428..6f95f90d905 100644 --- a/src/devices/cpu/h8/h8s2320.cpp +++ b/src/devices/cpu/h8/h8s2320.cpp @@ -16,41 +16,41 @@ DEFINE_DEVICE_TYPE(H8S2329, h8s2329_device, "h8s2329", "Hitachi H8S/2329") h8s2320_device::h8s2320_device(const machine_config &mconfig, device_type type, const char *tag, device_t *owner, uint32_t clock, uint32_t start) : h8s2000_device(mconfig, type, tag, owner, clock, address_map_constructor(FUNC(h8s2320_device::map), this)), - intc(*this, "intc"), - adc(*this, "adc"), - dma(*this, "dma"), - dma0(*this, "dma:0"), - dma1(*this, "dma:1"), - dtc(*this, "dtc"), - port1(*this, "port1"), - port2(*this, "port2"), - port3(*this, "port3"), - port4(*this, "port4"), - port5(*this, "port5"), - port6(*this, "port6"), - porta(*this, "porta"), - portb(*this, "portb"), - portc(*this, "portc"), - portd(*this, "portd"), - porte(*this, "porte"), - portf(*this, "portf"), - portg(*this, "portg"), - timer8_0(*this, "timer8_0"), - timer8_1(*this, "timer8_1"), - timer16(*this, "timer16"), - timer16_0(*this, "timer16:0"), - timer16_1(*this, "timer16:1"), - timer16_2(*this, "timer16:2"), - timer16_3(*this, "timer16:3"), - timer16_4(*this, "timer16:4"), - timer16_5(*this, "timer16:5"), - sci0(*this, "sci0"), - sci1(*this, "sci1"), - sci2(*this, "sci2"), - watchdog(*this, "watchdog"), - tend_cb(*this), - ram_start(start), - syscr(0) + m_intc(*this, "intc"), + m_adc(*this, "adc"), + m_dma(*this, "dma"), + m_dma0(*this, "dma:0"), + m_dma1(*this, "dma:1"), + m_dtc(*this, "dtc"), + m_port1(*this, "port1"), + m_port2(*this, "port2"), + m_port3(*this, "port3"), + m_port4(*this, "port4"), + m_port5(*this, "port5"), + m_port6(*this, "port6"), + m_porta(*this, "porta"), + m_portb(*this, "portb"), + m_portc(*this, "portc"), + m_portd(*this, "portd"), + m_porte(*this, "porte"), + m_portf(*this, "portf"), + m_portg(*this, "portg"), + m_timer8_0(*this, "timer8_0"), + m_timer8_1(*this, "timer8_1"), + m_timer16(*this, "timer16"), + m_timer16_0(*this, "timer16:0"), + m_timer16_1(*this, "timer16:1"), + m_timer16_2(*this, "timer16:2"), + m_timer16_3(*this, "timer16:3"), + m_timer16_4(*this, "timer16:4"), + m_timer16_5(*this, "timer16:5"), + m_sci0(*this, "sci0"), + m_sci1(*this, "sci1"), + m_sci2(*this, "sci2"), + m_watchdog(*this, "watchdog"), + m_tend_cb(*this), + m_ram_start(start), + m_syscr(0) { } @@ -101,7 +101,7 @@ h8s2329_device::h8s2329_device(const machine_config &mconfig, const char *tag, d void h8s2320_device::map(address_map &map) { - map(ram_start, 0xfffbff).ram(); + map(m_ram_start, 0xfffbff).ram(); map(0xfffe80, 0xfffe80).rw("timer16:3", FUNC(h8_timer16_channel_device::tcr_r), FUNC(h8_timer16_channel_device::tcr_w)); map(0xfffe81, 0xfffe81).rw("timer16:3", FUNC(h8_timer16_channel_device::tmdr_r), FUNC(h8_timer16_channel_device::tmdr_w)); @@ -352,88 +352,88 @@ void h8s2320_device::device_add_mconfig(machine_config &config) void h8s2320_device::execute_set_input(int inputnum, int state) { if(inputnum == H8_INPUT_LINE_TEND0 || inputnum == H8_INPUT_LINE_TEND1) { - if(!tend_cb[inputnum - H8_INPUT_LINE_TEND0].isnull()) - tend_cb[inputnum - H8_INPUT_LINE_TEND0](state); + if(!m_tend_cb[inputnum - H8_INPUT_LINE_TEND0].isnull()) + m_tend_cb[inputnum - H8_INPUT_LINE_TEND0](state); } else if(inputnum == H8_INPUT_LINE_DREQ0 || inputnum == H8_INPUT_LINE_DREQ1) - dma->set_input(inputnum, state); + m_dma->set_input(inputnum, state); else - intc->set_input(inputnum, state); + m_intc->set_input(inputnum, state); } bool h8s2320_device::exr_in_stack() const { - return syscr & 0x20; + return m_syscr & 0x20; } int h8s2320_device::trace_setup() { - CCR |= F_I; - EXR &= ~EXR_T; + m_CCR |= F_I; + m_EXR &= ~EXR_T; return 5; } int h8s2320_device::trapa_setup() { - CCR |= F_I; - if(syscr & 0x20) - EXR &= ~EXR_T; + m_CCR |= F_I; + if(m_syscr & 0x20) + m_EXR &= ~EXR_T; return 8; } void h8s2320_device::irq_setup() { - switch(syscr & 0x30) { + switch(m_syscr & 0x30) { case 0x00: - CCR |= F_I; + m_CCR |= F_I; break; case 0x20: - EXR = EXR & (EXR_NC); - if(taken_irq_level == 8) - EXR |= 7; + m_EXR = m_EXR & (EXR_NC); + if(m_taken_irq_level == 8) + m_EXR |= 7; else - EXR |= taken_irq_level; + m_EXR |= m_taken_irq_level; break; } } void h8s2320_device::update_irq_filter() { - switch(syscr & 0x30) { + switch(m_syscr & 0x30) { case 0x00: - if(CCR & F_I) - intc->set_filter(2, -1); + if(m_CCR & F_I) + m_intc->set_filter(2, -1); else - intc->set_filter(0, -1); + m_intc->set_filter(0, -1); break; case 0x20: - intc->set_filter(0, EXR & 7); + m_intc->set_filter(0, m_EXR & 7); break; } } void h8s2320_device::interrupt_taken() { - standard_irq_callback(intc->interrupt_taken(taken_irq_vector), NPC); + standard_irq_callback(m_intc->interrupt_taken(m_taken_irq_vector), m_NPC); } void h8s2320_device::internal_update(uint64_t current_time) { uint64_t event_time = 0; - add_event(event_time, adc->internal_update(current_time)); - add_event(event_time, sci0->internal_update(current_time)); - add_event(event_time, sci1->internal_update(current_time)); - add_event(event_time, sci2->internal_update(current_time)); - add_event(event_time, timer8_0->internal_update(current_time)); - add_event(event_time, timer8_1->internal_update(current_time)); - add_event(event_time, timer16_0->internal_update(current_time)); - add_event(event_time, timer16_1->internal_update(current_time)); - add_event(event_time, timer16_2->internal_update(current_time)); - add_event(event_time, timer16_3->internal_update(current_time)); - add_event(event_time, timer16_4->internal_update(current_time)); - add_event(event_time, timer16_5->internal_update(current_time)); - add_event(event_time, watchdog->internal_update(current_time)); + add_event(event_time, m_adc->internal_update(current_time)); + add_event(event_time, m_sci0->internal_update(current_time)); + add_event(event_time, m_sci1->internal_update(current_time)); + add_event(event_time, m_sci2->internal_update(current_time)); + add_event(event_time, m_timer8_0->internal_update(current_time)); + add_event(event_time, m_timer8_1->internal_update(current_time)); + add_event(event_time, m_timer16_0->internal_update(current_time)); + add_event(event_time, m_timer16_1->internal_update(current_time)); + add_event(event_time, m_timer16_2->internal_update(current_time)); + add_event(event_time, m_timer16_3->internal_update(current_time)); + add_event(event_time, m_timer16_4->internal_update(current_time)); + add_event(event_time, m_timer16_5->internal_update(current_time)); + add_event(event_time, m_watchdog->internal_update(current_time)); recompute_bcount(event_time); } @@ -441,27 +441,27 @@ void h8s2320_device::internal_update(uint64_t current_time) void h8s2320_device::device_start() { h8s2000_device::device_start(); - dma_device = dma; - dtc_device = dtc; + m_dma_device = m_dma; + m_dtc_device = m_dtc; - tend_cb.resolve_all(); + m_tend_cb.resolve_all(); } void h8s2320_device::device_reset() { h8s2000_device::device_reset(); - syscr = 0x01; + m_syscr = 0x01; } uint8_t h8s2320_device::syscr_r() { - return syscr; + return m_syscr; } void h8s2320_device::syscr_w(uint8_t data) { - syscr = data; - mac_saturating = syscr & 0x80; + m_syscr = data; + m_mac_saturating = m_syscr & 0x80; update_irq_filter(); logerror("syscr = %02x\n", data); } diff --git a/src/devices/cpu/h8/h8s2320.h b/src/devices/cpu/h8/h8s2320.h index a67cb634dfa..aa6c4acf3f2 100644 --- a/src/devices/cpu/h8/h8s2320.h +++ b/src/devices/cpu/h8/h8s2320.h @@ -43,50 +43,50 @@ class h8s2320_device : public h8s2000_device { public: h8s2320_device(const machine_config &mconfig, const char *tag, device_t *owner, uint32_t clock); - auto tend0_cb() { return tend_cb[0].bind(); } - auto tend1_cb() { return tend_cb[1].bind(); } + auto tend0_cb() { return m_tend_cb[0].bind(); } + auto tend1_cb() { return m_tend_cb[1].bind(); } uint8_t syscr_r(); void syscr_w(uint8_t data); protected: - required_device intc; - required_device adc; - optional_device dma; - optional_device dma0; - optional_device dma1; - required_device dtc; - required_device port1; - required_device port2; - required_device port3; - required_device port4; - required_device port5; - required_device port6; - required_device porta; - required_device portb; - required_device portc; - required_device portd; - required_device porte; - required_device portf; - required_device portg; - required_device timer8_0; - required_device timer8_1; - required_device timer16; - required_device timer16_0; - required_device timer16_1; - required_device timer16_2; - required_device timer16_3; - required_device timer16_4; - required_device timer16_5; - required_device sci0; - required_device sci1; - required_device sci2; - required_device watchdog; - - devcb_write_line::array<2> tend_cb; - - uint32_t ram_start; - uint8_t syscr; + required_device m_intc; + required_device m_adc; + optional_device m_dma; + optional_device m_dma0; + optional_device m_dma1; + required_device m_dtc; + required_device m_port1; + required_device m_port2; + required_device m_port3; + required_device m_port4; + required_device m_port5; + required_device m_port6; + required_device m_porta; + required_device m_portb; + required_device m_portc; + required_device m_portd; + required_device m_porte; + required_device m_portf; + required_device m_portg; + required_device m_timer8_0; + required_device m_timer8_1; + required_device m_timer16; + required_device m_timer16_0; + required_device m_timer16_1; + required_device m_timer16_2; + required_device m_timer16_3; + required_device m_timer16_4; + required_device m_timer16_5; + required_device m_sci0; + required_device m_sci1; + required_device m_sci2; + required_device m_watchdog; + + devcb_write_line::array<2> m_tend_cb; + + uint32_t m_ram_start; + uint8_t m_syscr; h8s2320_device(const machine_config &mconfig, device_type type, const char *tag, device_t *owner, uint32_t clock, uint32_t start); diff --git a/src/devices/cpu/h8/h8s2357.cpp b/src/devices/cpu/h8/h8s2357.cpp index b33267d826f..2637846058f 100644 --- a/src/devices/cpu/h8/h8s2357.cpp +++ b/src/devices/cpu/h8/h8s2357.cpp @@ -12,36 +12,36 @@ DEFINE_DEVICE_TYPE(H8S2390, h8s2390_device, "h8s2390", "Hitachi H8S/2390") h8s2357_device::h8s2357_device(const machine_config &mconfig, device_type type, const char *tag, device_t *owner, uint32_t clock, uint32_t start) : h8s2000_device(mconfig, type, tag, owner, clock, address_map_constructor(FUNC(h8s2357_device::map), this)), - intc(*this, "intc"), - adc(*this, "adc"), - port1(*this, "port1"), - port2(*this, "port2"), - port3(*this, "port3"), - port4(*this, "port4"), - port5(*this, "port5"), - port6(*this, "port6"), - porta(*this, "porta"), - portb(*this, "portb"), - portc(*this, "portc"), - portd(*this, "portd"), - porte(*this, "porte"), - portf(*this, "portf"), - portg(*this, "portg"), - timer8_0(*this, "timer8_0"), - timer8_1(*this, "timer8_1"), - timer16(*this, "timer16"), - timer16_0(*this, "timer16:0"), - timer16_1(*this, "timer16:1"), - timer16_2(*this, "timer16:2"), - timer16_3(*this, "timer16:3"), - timer16_4(*this, "timer16:4"), - timer16_5(*this, "timer16:5"), - sci0(*this, "sci0"), - sci1(*this, "sci1"), - sci2(*this, "sci2"), - watchdog(*this, "watchdog"), - ram_start(start), - syscr(0) + m_intc(*this, "intc"), + m_adc(*this, "adc"), + m_port1(*this, "port1"), + m_port2(*this, "port2"), + m_port3(*this, "port3"), + m_port4(*this, "port4"), + m_port5(*this, "port5"), + m_port6(*this, "port6"), + m_porta(*this, "porta"), + m_portb(*this, "portb"), + m_portc(*this, "portc"), + m_portd(*this, "portd"), + m_porte(*this, "porte"), + m_portf(*this, "portf"), + m_portg(*this, "portg"), + m_timer8_0(*this, "timer8_0"), + m_timer8_1(*this, "timer8_1"), + m_timer16(*this, "timer16"), + m_timer16_0(*this, "timer16:0"), + m_timer16_1(*this, "timer16:1"), + m_timer16_2(*this, "timer16:2"), + m_timer16_3(*this, "timer16:3"), + m_timer16_4(*this, "timer16:4"), + m_timer16_5(*this, "timer16:5"), + m_sci0(*this, "sci0"), + m_sci1(*this, "sci1"), + m_sci2(*this, "sci2"), + m_watchdog(*this, "watchdog"), + m_ram_start(start), + m_syscr(0) { } @@ -77,7 +77,7 @@ h8s2390_device::h8s2390_device(const machine_config &mconfig, const char *tag, d void h8s2357_device::map(address_map &map) { - map(ram_start, 0xfffbff).ram(); + map(m_ram_start, 0xfffbff).ram(); map(0xfffe80, 0xfffe80).rw("timer16:3", FUNC(h8_timer16_channel_device::tcr_r), FUNC(h8_timer16_channel_device::tcr_w)); map(0xfffe81, 0xfffe81).rw("timer16:3", FUNC(h8_timer16_channel_device::tmdr_r), FUNC(h8_timer16_channel_device::tmdr_w)); map(0xfffe82, 0xfffe83).rw("timer16:3", FUNC(h8_timer16_channel_device::tior_r), FUNC(h8_timer16_channel_device::tior_w)); @@ -291,82 +291,82 @@ void h8s2357_device::device_add_mconfig(machine_config &config) void h8s2357_device::execute_set_input(int inputnum, int state) { - intc->set_input(inputnum, state); + m_intc->set_input(inputnum, state); } bool h8s2357_device::exr_in_stack() const { - return syscr & 0x20; + return m_syscr & 0x20; } int h8s2357_device::trace_setup() { - CCR |= F_I; - EXR &= ~EXR_T; + m_CCR |= F_I; + m_EXR &= ~EXR_T; return 5; } int h8s2357_device::trapa_setup() { - CCR |= F_I; - if(syscr & 0x20) - EXR &= ~EXR_T; + m_CCR |= F_I; + if(m_syscr & 0x20) + m_EXR &= ~EXR_T; return 8; } void h8s2357_device::irq_setup() { - switch(syscr & 0x30) { + switch(m_syscr & 0x30) { case 0x00: - CCR |= F_I; + m_CCR |= F_I; break; case 0x20: - EXR = EXR & (EXR_NC); - if(taken_irq_level == 8) - EXR |= 7; + m_EXR = m_EXR & (EXR_NC); + if(m_taken_irq_level == 8) + m_EXR |= 7; else - EXR |= taken_irq_level; + m_EXR |= m_taken_irq_level; break; } } void h8s2357_device::update_irq_filter() { - switch(syscr & 0x20) { + switch(m_syscr & 0x20) { case 0x00: - if(CCR & F_I) - intc->set_filter(2, -1); + if(m_CCR & F_I) + m_intc->set_filter(2, -1); else - intc->set_filter(0, -1); + m_intc->set_filter(0, -1); break; case 0x20: - intc->set_filter(0, EXR & 7); + m_intc->set_filter(0, m_EXR & 7); break; } } void h8s2357_device::interrupt_taken() { - standard_irq_callback(intc->interrupt_taken(taken_irq_vector), NPC); + standard_irq_callback(m_intc->interrupt_taken(m_taken_irq_vector), m_NPC); } void h8s2357_device::internal_update(uint64_t current_time) { uint64_t event_time = 0; - add_event(event_time, adc->internal_update(current_time)); - add_event(event_time, sci0->internal_update(current_time)); - add_event(event_time, sci1->internal_update(current_time)); - add_event(event_time, sci2->internal_update(current_time)); - add_event(event_time, timer8_0->internal_update(current_time)); - add_event(event_time, timer8_1->internal_update(current_time)); - add_event(event_time, timer16_0->internal_update(current_time)); - add_event(event_time, timer16_1->internal_update(current_time)); - add_event(event_time, timer16_2->internal_update(current_time)); - add_event(event_time, timer16_3->internal_update(current_time)); - add_event(event_time, timer16_4->internal_update(current_time)); - add_event(event_time, timer16_5->internal_update(current_time)); - add_event(event_time, watchdog->internal_update(current_time)); + add_event(event_time, m_adc->internal_update(current_time)); + add_event(event_time, m_sci0->internal_update(current_time)); + add_event(event_time, m_sci1->internal_update(current_time)); + add_event(event_time, m_sci2->internal_update(current_time)); + add_event(event_time, m_timer8_0->internal_update(current_time)); + add_event(event_time, m_timer8_1->internal_update(current_time)); + add_event(event_time, m_timer16_0->internal_update(current_time)); + add_event(event_time, m_timer16_1->internal_update(current_time)); + add_event(event_time, m_timer16_2->internal_update(current_time)); + add_event(event_time, m_timer16_3->internal_update(current_time)); + add_event(event_time, m_timer16_4->internal_update(current_time)); + add_event(event_time, m_timer16_5->internal_update(current_time)); + add_event(event_time, m_watchdog->internal_update(current_time)); recompute_bcount(event_time); } @@ -379,17 +379,17 @@ void h8s2357_device::device_start() void h8s2357_device::device_reset() { h8s2000_device::device_reset(); - syscr = 0x01; + m_syscr = 0x01; } uint8_t h8s2357_device::syscr_r() { - return syscr; + return m_syscr; } void h8s2357_device::syscr_w(uint8_t data) { - syscr = data; + m_syscr = data; update_irq_filter(); logerror("syscr = %02x\n", data); } diff --git a/src/devices/cpu/h8/h8s2357.h b/src/devices/cpu/h8/h8s2357.h index 3f20c062d01..1fbe1653e1d 100644 --- a/src/devices/cpu/h8/h8s2357.h +++ b/src/devices/cpu/h8/h8s2357.h @@ -42,37 +42,37 @@ public: void syscr_w(uint8_t data); protected: - required_device intc; - required_device adc; - required_device port1; - required_device port2; - required_device port3; - required_device port4; - required_device port5; - required_device port6; - required_device porta; - required_device portb; - required_device portc; - required_device portd; - required_device porte; - required_device portf; - required_device portg; - required_device timer8_0; - required_device timer8_1; - required_device timer16; - required_device timer16_0; - required_device timer16_1; - required_device timer16_2; - required_device timer16_3; - required_device timer16_4; - required_device timer16_5; - required_device sci0; - required_device sci1; - required_device sci2; - required_device watchdog; - - uint32_t ram_start; - unsigned char syscr; + required_device m_intc; + required_device m_adc; + required_device m_port1; + required_device m_port2; + required_device m_port3; + required_device m_port4; + required_device m_port5; + required_device m_port6; + required_device m_porta; + required_device m_portb; + required_device m_portc; + required_device m_portd; + required_device m_porte; + required_device m_portf; + required_device m_portg; + required_device m_timer8_0; + required_device m_timer8_1; + required_device m_timer16; + required_device m_timer16_0; + required_device m_timer16_1; + required_device m_timer16_2; + required_device m_timer16_3; + required_device m_timer16_4; + required_device m_timer16_5; + required_device m_sci0; + required_device m_sci1; + required_device m_sci2; + required_device m_watchdog; + + uint32_t m_ram_start; + unsigned char m_syscr; h8s2357_device(const machine_config &mconfig, device_type type, const char *tag, device_t *owner, uint32_t clock, uint32_t start); diff --git a/src/devices/cpu/h8/h8s2600.cpp b/src/devices/cpu/h8/h8s2600.cpp index be04b3382df..86dd00f0606 100644 --- a/src/devices/cpu/h8/h8s2600.cpp +++ b/src/devices/cpu/h8/h8s2600.cpp @@ -7,7 +7,7 @@ h8s2600_device::h8s2600_device(const machine_config &mconfig, device_type type, const char *tag, device_t *owner, uint32_t clock, address_map_constructor map_delegate) : h8s2000_device(mconfig, type, tag, owner, clock, map_delegate) { - has_mac = true; + m_has_mac = true; } std::unique_ptr h8s2600_device::create_disassembler() diff --git a/src/devices/cpu/h8/h8s2655.cpp b/src/devices/cpu/h8/h8s2655.cpp index 85e78f4b3bb..0963f21e300 100644 --- a/src/devices/cpu/h8/h8s2655.cpp +++ b/src/devices/cpu/h8/h8s2655.cpp @@ -8,37 +8,37 @@ DEFINE_DEVICE_TYPE(H8S2653, h8s2653_device, "h8s2653", "Hitachi H8S/2653") h8s2655_device::h8s2655_device(const machine_config &mconfig, device_type type, const char *tag, device_t *owner, uint32_t clock) : h8s2600_device(mconfig, type, tag, owner, clock, address_map_constructor(FUNC(h8s2655_device::map), this)), - intc(*this, "intc"), - adc(*this, "adc"), - port1(*this, "port1"), - port2(*this, "port2"), - port3(*this, "port3"), - port4(*this, "port4"), - port5(*this, "port5"), - port6(*this, "port6"), - porta(*this, "porta"), - portb(*this, "portb"), - portc(*this, "portc"), - portd(*this, "portd"), - porte(*this, "porte"), - portf(*this, "portf"), - portg(*this, "portg"), - timer8_0(*this, "timer8_0"), - timer8_1(*this, "timer8_1"), - timer16(*this, "timer16"), - timer16_0(*this, "timer16:0"), - timer16_1(*this, "timer16:1"), - timer16_2(*this, "timer16:2"), - timer16_3(*this, "timer16:3"), - timer16_4(*this, "timer16:4"), - timer16_5(*this, "timer16:5"), - sci0(*this, "sci0"), - sci1(*this, "sci1"), - sci2(*this, "sci2"), - watchdog(*this, "watchdog"), - syscr(0) + m_intc(*this, "intc"), + m_adc(*this, "adc"), + m_port1(*this, "port1"), + m_port2(*this, "port2"), + m_port3(*this, "port3"), + m_port4(*this, "port4"), + m_port5(*this, "port5"), + m_port6(*this, "port6"), + m_porta(*this, "porta"), + m_portb(*this, "portb"), + m_portc(*this, "portc"), + m_portd(*this, "portd"), + m_porte(*this, "porte"), + m_portf(*this, "portf"), + m_portg(*this, "portg"), + m_timer8_0(*this, "timer8_0"), + m_timer8_1(*this, "timer8_1"), + m_timer16(*this, "timer16"), + m_timer16_0(*this, "timer16:0"), + m_timer16_1(*this, "timer16:1"), + m_timer16_2(*this, "timer16:2"), + m_timer16_3(*this, "timer16:3"), + m_timer16_4(*this, "timer16:4"), + m_timer16_5(*this, "timer16:5"), + m_sci0(*this, "sci0"), + m_sci1(*this, "sci1"), + m_sci2(*this, "sci2"), + m_watchdog(*this, "watchdog"), + m_syscr(0) { - has_trace = true; + m_has_trace = true; } h8s2655_device::h8s2655_device(const machine_config &mconfig, const char *tag, device_t *owner, uint32_t clock) : @@ -270,115 +270,115 @@ void h8s2655_device::device_add_mconfig(machine_config &config) void h8s2655_device::execute_set_input(int inputnum, int state) { - intc->set_input(inputnum, state); + m_intc->set_input(inputnum, state); } bool h8s2655_device::exr_in_stack() const { - return syscr & 0x20; + return m_syscr & 0x20; } int h8s2655_device::trace_setup() { - if(syscr & 0x10) - CCR |= F_I|F_UI; + if(m_syscr & 0x10) + m_CCR |= F_I|F_UI; else - CCR |= F_I; - EXR &= ~EXR_T; + m_CCR |= F_I; + m_EXR &= ~EXR_T; return 5; } int h8s2655_device::trapa_setup() { - if(syscr & 0x10) - CCR |= F_I|F_UI; + if(m_syscr & 0x10) + m_CCR |= F_I|F_UI; else - CCR |= F_I; - if(syscr & 0x20) - EXR &= ~EXR_T; + m_CCR |= F_I; + if(m_syscr & 0x20) + m_EXR &= ~EXR_T; return 8; } void h8s2655_device::irq_setup() { - switch(syscr & 0x30) { + switch(m_syscr & 0x30) { case 0x00: - CCR |= F_I; + m_CCR |= F_I; break; case 0x10: - CCR |= F_I|F_UI; + m_CCR |= F_I|F_UI; break; case 0x20: - EXR = EXR & (EXR_NC); - if(taken_irq_level == 8) - EXR |= 7; + m_EXR = m_EXR & (EXR_NC); + if(m_taken_irq_level == 8) + m_EXR |= 7; else - EXR |= taken_irq_level; + m_EXR |= m_taken_irq_level; break; case 0x30: - CCR |= F_I|F_UI; - EXR = EXR & (EXR_NC); - if(taken_irq_level == 8) - EXR |= 7; + m_CCR |= F_I|F_UI; + m_EXR = m_EXR & (EXR_NC); + if(m_taken_irq_level == 8) + m_EXR |= 7; else - EXR |= taken_irq_level; + m_EXR |= m_taken_irq_level; break; } } void h8s2655_device::update_irq_filter() { - switch(syscr & 0x30) { + switch(m_syscr & 0x30) { case 0x00: - if(CCR & F_I) - intc->set_filter(2, -1); + if(m_CCR & F_I) + m_intc->set_filter(2, -1); else - intc->set_filter(0, -1); + m_intc->set_filter(0, -1); break; case 0x10: - if((CCR & (F_I|F_UI)) == (F_I|F_UI)) - intc->set_filter(2, -1); - else if(CCR & F_I) - intc->set_filter(1, -1); + if((m_CCR & (F_I|F_UI)) == (F_I|F_UI)) + m_intc->set_filter(2, -1); + else if(m_CCR & F_I) + m_intc->set_filter(1, -1); else - intc->set_filter(0, -1); + m_intc->set_filter(0, -1); break; case 0x20: - intc->set_filter(0, EXR & 7); + m_intc->set_filter(0, m_EXR & 7); break; case 0x30: - if((CCR & (F_I|F_UI)) == (F_I|F_UI)) - intc->set_filter(2, EXR & 7); - else if(CCR & F_I) - intc->set_filter(1, EXR & 7); + if((m_CCR & (F_I|F_UI)) == (F_I|F_UI)) + m_intc->set_filter(2, m_EXR & 7); + else if(m_CCR & F_I) + m_intc->set_filter(1, m_EXR & 7); else - intc->set_filter(0, EXR & 7); + m_intc->set_filter(0, m_EXR & 7); break; } } void h8s2655_device::interrupt_taken() { - standard_irq_callback(intc->interrupt_taken(taken_irq_vector), NPC); + standard_irq_callback(m_intc->interrupt_taken(m_taken_irq_vector), m_NPC); } void h8s2655_device::internal_update(uint64_t current_time) { uint64_t event_time = 0; - add_event(event_time, adc->internal_update(current_time)); - add_event(event_time, sci0->internal_update(current_time)); - add_event(event_time, sci1->internal_update(current_time)); - add_event(event_time, sci2->internal_update(current_time)); - add_event(event_time, timer8_0->internal_update(current_time)); - add_event(event_time, timer8_1->internal_update(current_time)); - add_event(event_time, timer16_0->internal_update(current_time)); - add_event(event_time, timer16_1->internal_update(current_time)); - add_event(event_time, timer16_2->internal_update(current_time)); - add_event(event_time, timer16_3->internal_update(current_time)); - add_event(event_time, timer16_4->internal_update(current_time)); - add_event(event_time, timer16_5->internal_update(current_time)); - add_event(event_time, watchdog->internal_update(current_time)); + add_event(event_time, m_adc->internal_update(current_time)); + add_event(event_time, m_sci0->internal_update(current_time)); + add_event(event_time, m_sci1->internal_update(current_time)); + add_event(event_time, m_sci2->internal_update(current_time)); + add_event(event_time, m_timer8_0->internal_update(current_time)); + add_event(event_time, m_timer8_1->internal_update(current_time)); + add_event(event_time, m_timer16_0->internal_update(current_time)); + add_event(event_time, m_timer16_1->internal_update(current_time)); + add_event(event_time, m_timer16_2->internal_update(current_time)); + add_event(event_time, m_timer16_3->internal_update(current_time)); + add_event(event_time, m_timer16_4->internal_update(current_time)); + add_event(event_time, m_timer16_5->internal_update(current_time)); + add_event(event_time, m_watchdog->internal_update(current_time)); recompute_bcount(event_time); } @@ -391,17 +391,17 @@ void h8s2655_device::device_start() void h8s2655_device::device_reset() { h8s2600_device::device_reset(); - syscr = 0x01; + m_syscr = 0x01; } uint8_t h8s2655_device::syscr_r() { - return syscr; + return m_syscr; } void h8s2655_device::syscr_w(uint8_t data) { - syscr = data; + m_syscr = data; update_irq_filter(); logerror("syscr = %02x\n", data); } diff --git a/src/devices/cpu/h8/h8s2655.h b/src/devices/cpu/h8/h8s2655.h index aa8384bce73..78732dab259 100644 --- a/src/devices/cpu/h8/h8s2655.h +++ b/src/devices/cpu/h8/h8s2655.h @@ -34,36 +34,36 @@ public: void syscr_w(uint8_t data); protected: - required_device intc; - required_device adc; - required_device port1; - required_device port2; - required_device port3; - required_device port4; - required_device port5; - required_device port6; - required_device porta; - required_device portb; - required_device portc; - required_device portd; - required_device porte; - required_device portf; - required_device portg; - required_device timer8_0; - required_device timer8_1; - required_device timer16; - required_device timer16_0; - required_device timer16_1; - required_device timer16_2; - required_device timer16_3; - required_device timer16_4; - required_device timer16_5; - required_device sci0; - required_device sci1; - required_device sci2; - required_device watchdog; - - uint8_t syscr; + required_device m_intc; + required_device m_adc; + required_device m_port1; + required_device m_port2; + required_device m_port3; + required_device m_port4; + required_device m_port5; + required_device m_port6; + required_device m_porta; + required_device m_portb; + required_device m_portc; + required_device m_portd; + required_device m_porte; + required_device m_portf; + required_device m_portg; + required_device m_timer8_0; + required_device m_timer8_1; + required_device m_timer16; + required_device m_timer16_0; + required_device m_timer16_1; + required_device m_timer16_2; + required_device m_timer16_3; + required_device m_timer16_4; + required_device m_timer16_5; + required_device m_sci0; + required_device m_sci1; + required_device m_sci2; + required_device m_watchdog; + + uint8_t m_syscr; h8s2655_device(const machine_config &mconfig, device_type type, const char *tag, device_t *owner, uint32_t clock); -- cgit v1.2.3