From e6261f9e397cf300fe617a0ca8cfe40e71a35868 Mon Sep 17 00:00:00 2001 From: AJR Date: Wed, 17 Apr 2019 18:58:35 -0400 Subject: x68k_crtc: Explicitly configure all clocks (nw) --- src/emu/xtal.cpp | 2 ++ src/mame/drivers/x68k.cpp | 6 +++++- src/mame/video/x68k_crtc.cpp | 4 +++- src/mame/video/x68k_crtc.h | 16 ++++++++++++++-- 4 files changed, 24 insertions(+), 4 deletions(-) diff --git a/src/emu/xtal.cpp b/src/emu/xtal.cpp index 68c262ee365..63467731c09 100644 --- a/src/emu/xtal.cpp +++ b/src/emu/xtal.cpp @@ -335,6 +335,7 @@ const double XTAL::known_xtals[] = { 32'530'400, /* 32.5304_MHz_XTAL Seta 2 */ 33'000'000, /* 33_MHz_XTAL Sega Model 3 video board */ 33'264'000, /* 33.264_MHz_XTAL Hazeltine 1500 terminal */ + 33'330'000, /* 33.33_MHz_XTAL Sharp X68000 XVI */ 33'333'000, /* 33.333_MHz_XTAL Sega Model 3 CPU board, Vegas */ 33'833'000, /* 33.833_MHz_XTAL - */ 33'868'800, /* 33.8688_MHz_XTAL Usually used to drive 90's Yamaha OPL/FM chips with /2 divider */ @@ -375,6 +376,7 @@ const double XTAL::known_xtals[] = { 50'000'000, /* 50_MHz_XTAL Williams/Midway T/W/V-unit system */ 50'113'000, /* 50.113_MHz_XTAL Namco NA-1 (14x NTSC subcarrier)*/ 50'349'000, /* 50.349_MHz_XTAL Sega System 18 (~3200x NTSC line rate) */ + 50'350'000, /* 50.35_MHz_XTAL Sharp X68030 video */ 51'200'000, /* 51.2_MHz_XTAL Namco Super System 22 video clock */ 52'000'000, /* 52_MHz_XTAL Cojag */ 52'832'000, /* 52.832_MHz_XTAL Wang PC TIG video controller */ diff --git a/src/mame/drivers/x68k.cpp b/src/mame/drivers/x68k.cpp index 3bea4f67eea..bbc00fd67ef 100644 --- a/src/mame/drivers/x68k.cpp +++ b/src/mame/drivers/x68k.cpp @@ -1663,6 +1663,7 @@ void x68k_state::x68000(machine_config &config) x68000_base(config); VINAS(config, m_crtc, 38.86363_MHz_XTAL); + m_crtc->set_clock_69m(69.55199_MHz_XTAL); m_crtc->set_screen("screen"); m_crtc->vdisp_cb().set(m_mfpdev, FUNC(mc68901_device::i4_w)); m_crtc->vdisp_cb().append(m_mfpdev, FUNC(mc68901_device::tai_w)); @@ -1695,6 +1696,7 @@ void x68ksupr_state::x68ksupr_base(machine_config &config) m_scsictrl->drq_cb().set(FUNC(x68ksupr_state::scsi_drq)); VICON(config, m_crtc, 38.86363_MHz_XTAL); + m_crtc->set_clock_69m(69.55199_MHz_XTAL); m_crtc->set_screen("screen"); m_crtc->vdisp_cb().set(m_mfpdev, FUNC(mc68901_device::i4_w)); m_crtc->vdisp_cb().append(m_mfpdev, FUNC(mc68901_device::tai_w)); @@ -1714,7 +1716,7 @@ void x68ksupr_state::x68ksupr(machine_config &config) void x68ksupr_state::x68kxvi(machine_config &config) { - add_cpu(config, M68000, &x68ksupr_state::x68kxvi_map, 33.333_MHz_XTAL / 2); /* 16 MHz (nominally) */ + add_cpu(config, M68000, &x68ksupr_state::x68kxvi_map, 33.33_MHz_XTAL / 2); /* 16 MHz (nominally) */ x68ksupr_base(config); } @@ -1726,6 +1728,8 @@ void x68030_state::x68030(machine_config &config) m_hd63450->set_clock(50_MHz_XTAL / 4); m_scc->set_clock(20_MHz_XTAL / 4); m_scsictrl->set_clock(20_MHz_XTAL / 4); + + m_crtc->set_clock_50m(50.35_MHz_XTAL); } ROM_START( x68000 ) diff --git a/src/mame/video/x68k_crtc.cpp b/src/mame/video/x68k_crtc.cpp index bfa214088e5..5a82583f725 100644 --- a/src/mame/video/x68k_crtc.cpp +++ b/src/mame/video/x68k_crtc.cpp @@ -22,6 +22,8 @@ x68k_crtc_device::x68k_crtc_device(const machine_config &mconfig, device_type ty , m_gvram_read_callback(*this) , m_tvram_write_callback(*this) , m_gvram_write_callback(*this) + , m_clock_69m(0) + , m_clock_50m(0) , m_operation(0) , m_vblank(false) , m_hblank(false) @@ -203,7 +205,7 @@ void x68k_crtc_device::refresh_mode() div = BIT(m_reg[20], 0) ? 3 : 6; if ((m_reg[20] & 0x0c) == 0) div *= 2; - attotime refresh = attotime::from_hz((BIT(m_reg[20], 4) ? 69.55199_MHz_XTAL : 38.86363_MHz_XTAL) / div) * (scr.max_x * scr.max_y); + attotime refresh = attotime::from_hz((BIT(m_reg[20], 4) ? clock_69m() : clock_39m()) / div) * (scr.max_x * scr.max_y); LOG("screen().configure(%i,%i,[%i,%i,%i,%i],%f)\n", scr.max_x, scr.max_y, visiblescr.min_x, visiblescr.min_y, visiblescr.max_x, visiblescr.max_y, refresh.as_hz()); screen().configure(scr.max_x, scr.max_y, visiblescr, refresh.as_attoseconds()); } diff --git a/src/mame/video/x68k_crtc.h b/src/mame/video/x68k_crtc.h index a532dbe72f5..233646d05ba 100644 --- a/src/mame/video/x68k_crtc.h +++ b/src/mame/video/x68k_crtc.h @@ -7,7 +7,7 @@ class x68k_crtc_device : public device_t, public device_video_interface { public: - // device configuration + // device callback configuration auto vdisp_cb() { return m_vdisp_callback.bind(); } auto rint_cb() { return m_rint_callback.bind(); } auto hsync_cb() { return m_hsync_callback.bind(); } @@ -15,7 +15,15 @@ public: auto tvram_write_cb() { return m_tvram_write_callback.bind(); } auto gvram_read_cb() { return m_gvram_read_callback.bind(); } auto gvram_write_cb() { return m_gvram_write_callback.bind(); } - // TODO: XTAL clocks + + // clock configuration + void set_clock_69m(uint32_t clock) { m_clock_69m = clock; } + void set_clock_69m(const XTAL &xtal) { set_clock_69m(xtal.value()); } + void set_clock_50m(uint32_t clock) { m_clock_50m = clock; } + void set_clock_50m(const XTAL &xtal) { set_clock_50m(xtal.value()); } + u32 clock_39m() const { return clock(); } + u32 clock_69m() const { return m_clock_69m; } + u32 clock_50m() const { return m_clock_50m; } DECLARE_WRITE16_MEMBER(crtc_w); DECLARE_READ16_MEMBER(crtc_r); @@ -70,6 +78,10 @@ private: devcb_write16 m_tvram_write_callback; devcb_write16 m_gvram_write_callback; + // software-selectable oscillators + u32 m_clock_69m; + u32 m_clock_50m; + // internal state u16 m_reg[24]; // registers u8 m_operation; // operation port (0xe80481) -- cgit v1.2.3