From cb0a5d12931e418599e89b11b9fd8294e417603c Mon Sep 17 00:00:00 2001 From: hap Date: Sun, 21 Jul 2019 22:54:48 +0200 Subject: corona: check/end leds were wrong way around (nw) --- src/devices/cpu/m6800/m6801.cpp | 2 +- src/devices/cpu/m6800/m6801.h | 5 +---- src/mame/drivers/saitek_stratos.cpp | 20 ++++++++++++++------ src/mame/layout/saitek_corona.lay | 4 ++-- 4 files changed, 18 insertions(+), 13 deletions(-) diff --git a/src/devices/cpu/m6800/m6801.cpp b/src/devices/cpu/m6800/m6801.cpp index 674d4a025ac..28339b33005 100644 --- a/src/devices/cpu/m6800/m6801.cpp +++ b/src/devices/cpu/m6800/m6801.cpp @@ -671,7 +671,7 @@ void m6801_cpu_device::execute_set_input(int irqline, int state) if (state != m_irq_state[M6801_TIN_LINE]) { m_irq_state[M6801_TIN_LINE] = state; - //eddge = (state == CLEAR_LINE ) ? 2 : 0; + //edge = (state == CLEAR_LINE ) ? 2 : 0; if( ((m_tcsr&TCSR_IEDG) ^ (state==CLEAR_LINE ? TCSR_IEDG : 0))==0 ) return; /* active edge in */ diff --git a/src/devices/cpu/m6800/m6801.h b/src/devices/cpu/m6800/m6801.h index 3254858ad61..1bf068bb73a 100644 --- a/src/devices/cpu/m6800/m6801.h +++ b/src/devices/cpu/m6800/m6801.h @@ -12,10 +12,7 @@ enum { M6801_IRQ_LINE = M6800_IRQ_LINE, - M6801_TIN_LINE, /* P20/Tin Input Capture line (eddge sense) */ - /* Active eddge is selecrable by internal reg. */ - /* raise eddge : CLEAR_LINE -> ASSERT_LINE */ - /* fall eddge : ASSERT_LINE -> CLEAR_LINE */ + M6801_TIN_LINE, // P20/Tin Input Capture line (edge sense). Active edge is selectable by internal reg. M6801_SC1_LINE }; diff --git a/src/mame/drivers/saitek_stratos.cpp b/src/mame/drivers/saitek_stratos.cpp index 9ef63d74484..9e6678b2bf8 100644 --- a/src/mame/drivers/saitek_stratos.cpp +++ b/src/mame/drivers/saitek_stratos.cpp @@ -20,7 +20,7 @@ cold boot, press ACL, then hold the PLAY button and press GO. ******************************************************************************* Hardware notes: -- W65C02 or R65C02 at 5MHz or 5.67MHz (for latter, box says 6MHz but that's a marketing lie) +- W65C02 or R65C02 at 5MHz or ~5.6MHz (for latter, box says 6MHz but that's a marketing lie) - 2*32KB ROM + optional 32KB Endgame ROM sold separately - 8KB RAM + another 8KB RAM(latter not populated on every PCB) - NEC gate array for all I/O, Saitek calls it HELIOS @@ -31,6 +31,11 @@ Stratos/Turbo King are identical. Corona has magnet sensors and two HELIOS chips. Simultano has an extra LCD screen representing the chessboard state. +There is no official Saitek program versioning for these. The D/D+ versions are known since +they're the same chess engine as later Saitek modules, such as the Analyst module. +Likewise, officially there isn't a "Turbo King II" or "Corona II", these 'sequels' are titled +as such by the chesscomputer community. Saitek simply advertised them as an improved program. + TODO: - emulate LCD at lower level, probably an MCU with embedded LCDC - add LCD 7*7 DMD, it's in m_lcd_data[0x30 to 0x3b] but scrambled @@ -143,8 +148,10 @@ void saitek_stratos_state::machine_reset() void saitek_stratos_state::set_cpu_freq() { - // released with either 5MHz or 5.67MHz speeds - m_maincpu->set_unscaled_clock((ioport("FAKE")->read() & 1) ? 5.67_MHz_XTAL : 5_MHz_XTAL); + // known officially* released CPU speeds: 5MHz, 5.626MHz, 5.67MHz + // *not including reseller overclocks, user mods, or the "Turbo Kit" + u8 inp = ioport("FAKE")->read(); + m_maincpu->set_unscaled_clock((inp & 2) ? 5.67_MHz_XTAL : ((inp & 1) ? 5.626_MHz_XTAL : 5_MHz_XTAL)); } // stratos_state @@ -449,9 +456,10 @@ INPUT_PORTS_START( saitek_stratos ) PORT_BIT(0x02, IP_ACTIVE_HIGH, IPT_KEYPAD) PORT_CODE(KEYCODE_F1) PORT_CHANGED_MEMBER(DEVICE_SELF, saitek_stratos_state, acl_button, nullptr) PORT_NAME("ACL") PORT_START("FAKE") - PORT_CONFNAME( 0x01, 0x00, "CPU Frequency" ) PORT_CHANGED_MEMBER(DEVICE_SELF, saitek_stratos_state, cpu_freq, nullptr) // factory set + PORT_CONFNAME( 0x03, 0x00, "CPU Frequency" ) PORT_CHANGED_MEMBER(DEVICE_SELF, saitek_stratos_state, cpu_freq, nullptr) // factory set PORT_CONFSETTING( 0x00, "5MHz" ) - PORT_CONFSETTING( 0x01, "5.67MHz" ) + PORT_CONFSETTING( 0x01, "5.626MHz" ) + PORT_CONFSETTING( 0x02, "5.67MHz" ) INPUT_PORTS_END static INPUT_PORTS_START( stratos ) @@ -560,6 +568,6 @@ ROM_END CONS( 1986, stratos, 0, 0, stratos, stratos, stratos_state, empty_init, "SciSys", "Kasparov Stratos (set 1)", MACHINE_SUPPORTS_SAVE | MACHINE_IMPERFECT_GRAPHICS | MACHINE_CLICKABLE_ARTWORK ) CONS( 1986, stratosa, stratos, 0, stratos, stratos, stratos_state, empty_init, "SciSys", "Kasparov Stratos (set 2)", MACHINE_SUPPORTS_SAVE | MACHINE_IMPERFECT_GRAPHICS | MACHINE_CLICKABLE_ARTWORK ) -CONS( 1990, tking, 0, 0, tking2, tking2, stratos_state, empty_init, "Saitek", "Kasparov Turbo King (set 1, ver. D)", MACHINE_SUPPORTS_SAVE | MACHINE_IMPERFECT_GRAPHICS | MACHINE_CLICKABLE_ARTWORK ) // aka Turbo King II +CONS( 1988, tking, 0, 0, tking2, tking2, stratos_state, empty_init, "Saitek", "Kasparov Turbo King (set 1, ver. D)", MACHINE_SUPPORTS_SAVE | MACHINE_IMPERFECT_GRAPHICS | MACHINE_CLICKABLE_ARTWORK ) // aka Turbo King II CONS( 1988, tkinga, tking, 0, stratos, stratos, stratos_state, empty_init, "Saitek", "Kasparov Turbo King (set 2)", MACHINE_SUPPORTS_SAVE | MACHINE_IMPERFECT_GRAPHICS | MACHINE_CLICKABLE_ARTWORK ) // oldest? CONS( 1988, tkingb, tking, 0, stratos, stratos, stratos_state, empty_init, "Saitek", "Kasparov Turbo King (set 3)", MACHINE_SUPPORTS_SAVE | MACHINE_IMPERFECT_GRAPHICS | MACHINE_CLICKABLE_ARTWORK ) diff --git a/src/mame/layout/saitek_corona.lay b/src/mame/layout/saitek_corona.lay index 9f07fc171d2..a036d8bf491 100644 --- a/src/mame/layout/saitek_corona.lay +++ b/src/mame/layout/saitek_corona.lay @@ -626,8 +626,8 @@ - - + + -- cgit v1.2.3