From c3cefee1b24b01ec3cb1cfbce5530b98c39251b6 Mon Sep 17 00:00:00 2001 From: Ted Green Date: Wed, 21 Dec 2016 19:24:55 -0700 Subject: midwayic: Added hooks for serial communication. (nw) atlantis: Renamed uart ports. (nw) iteagle: Remapped service buttons to standard location. iteagle: Connected cdrom and started adding rs232 communication ports. (nw) --- src/devices/machine/pci-ide.cpp | 4 +- src/devices/video/zeus2.h | 5 ++ src/mame/drivers/atlantis.cpp | 83 ++++++++++++++++++------- src/mame/drivers/iteagle.cpp | 6 +- src/mame/drivers/vegas.cpp | 2 +- src/mame/machine/iteagle_fpga.cpp | 126 +++++++++++++++++++++++++++++--------- src/mame/machine/iteagle_fpga.h | 6 ++ src/mame/machine/midwayic.cpp | 17 ++++- src/mame/machine/midwayic.h | 7 +++ 9 files changed, 197 insertions(+), 59 deletions(-) diff --git a/src/devices/machine/pci-ide.cpp b/src/devices/machine/pci-ide.cpp index ab49e816c2c..398831e6cae 100644 --- a/src/devices/machine/pci-ide.cpp +++ b/src/devices/machine/pci-ide.cpp @@ -41,11 +41,11 @@ DEVICE_ADDRESS_MAP_START(bus_master_map, 32, ide_pci_device) ADDRESS_MAP_END static MACHINE_CONFIG_FRAGMENT(pci_ide) - MCFG_BUS_MASTER_IDE_CONTROLLER_ADD("ide", ata_devices, "hdd", nullptr, true) + MCFG_BUS_MASTER_IDE_CONTROLLER_ADD("ide", ata_devices, "hdd", "cdrom", true) MCFG_ATA_INTERFACE_IRQ_HANDLER(WRITELINE(ide_pci_device, ide_interrupt)) //MCFG_BUS_MASTER_IDE_CONTROLLER_SPACE(":maincpu", AS_PROGRAM) MCFG_BUS_MASTER_IDE_CONTROLLER_SPACE(":pci:00.0", AS_DATA) - MCFG_BUS_MASTER_IDE_CONTROLLER_ADD("ide2", ata_devices, nullptr, "cdrom", true) + MCFG_BUS_MASTER_IDE_CONTROLLER_ADD("ide2", ata_devices, "hdd", "cdrom", true) MCFG_ATA_INTERFACE_IRQ_HANDLER(WRITELINE(ide_pci_device, ide_interrupt)) //MCFG_BUS_MASTER_IDE_CONTROLLER_SPACE(":maincpu", AS_PROGRAM) MCFG_BUS_MASTER_IDE_CONTROLLER_SPACE(":pci:00.0", AS_DATA) diff --git a/src/devices/video/zeus2.h b/src/devices/video/zeus2.h index 5d6cfe4fafc..2e0bb9b70d0 100644 --- a/src/devices/video/zeus2.h +++ b/src/devices/video/zeus2.h @@ -298,6 +298,11 @@ public: return ((color & 0x7c00) << 9) | ((color & 0x3e0) << 6) | ((color & 0x1f) << 3); } + inline uint32_t conv_rgb565_to_rgb32(uint16_t color) + { + return ((color & 0x7c00) << 9) | ((color & 0x3e0) << 6) | ((color & 0x8000) >> 5) | ((color & 0x1f) << 3); + } + #ifdef UNUSED_FUNCTION inline void WAVERAM_plot(int y, int x, uint32_t color) { diff --git a/src/mame/drivers/atlantis.cpp b/src/mame/drivers/atlantis.cpp index df6715e208c..b805367bd69 100644 --- a/src/mame/drivers/atlantis.cpp +++ b/src/mame/drivers/atlantis.cpp @@ -38,6 +38,8 @@ #include "machine/idectrl.h" #include "machine/midwayic.h" #include "machine/ins8250.h" +#include "bus/rs232/rs232.h" +#include "machine/terminal.h" #include "audio/dcs.h" #include "machine/pci.h" #include "machine/vrc4373.h" @@ -64,8 +66,8 @@ #define GALILEO_IRQ_SHIFT 1 #define ZEUS_IRQ_SHIFT 2 #define PARALLEL_IRQ_SHIFT 3 -#define UART0_SHIFT 4 -#define UART1_SHIFT 5 +#define UART1_SHIFT 4 +#define UART2_SHIFT 5 #define VBLANK_IRQ_SHIFT 7 /* static interrupts */ @@ -73,6 +75,7 @@ #define VBLANK_IRQ_NUM MIPS3_IRQ3 #define IDE_IRQ_NUM MIPS3_IRQ4 +#define DEBUG_CONSOLE (0) #define LOG_RTC (0) #define LOG_PORT (0) #define LOG_IRQ (0) @@ -90,6 +93,7 @@ public: m_ioasic(*this, "ioasic"), m_uart0(*this, "uart0"), m_uart1(*this, "uart1"), + m_uart2(*this, "uart2"), m_rtc(*this, "rtc") { } DECLARE_DRIVER_INIT(mwskins); @@ -102,8 +106,9 @@ public: required_device m_zeus; required_device m_dcs; required_device m_ioasic; - required_device m_uart0; + optional_device m_uart0; required_device m_uart1; + required_device m_uart2; required_device m_rtc; uint8_t m_rtc_data[0x8000]; @@ -142,8 +147,8 @@ public: DECLARE_WRITE_LINE_MEMBER(ide_irq); DECLARE_WRITE_LINE_MEMBER(ioasic_irq); - DECLARE_WRITE_LINE_MEMBER(uart0_irq_callback); DECLARE_WRITE_LINE_MEMBER(uart1_irq_callback); + DECLARE_WRITE_LINE_MEMBER(uart2_irq_callback); DECLARE_CUSTOM_INPUT_MEMBER(port_mod_r); DECLARE_READ32_MEMBER(port_ctrl_r); @@ -186,7 +191,7 @@ READ32_MEMBER(atlantis_state::board_ctrl_r) switch (newOffset) { case CTRL_STATUS: if (1 && m_screen->vblank()) - data |= 0x80; + data |= 1 << VBLANK_IRQ_SHIFT; if (m_last_offset != (newOffset | 0x40000)) if (LOG_IRQ) logerror("%s:board_ctrl_r read from CTRL_STATUS offset %04X = %08X & %08X bus offset = %08X\n", machine().describe_context(), newOffset, data, mem_mask, offset); @@ -414,11 +419,11 @@ READ32_MEMBER(atlantis_state::user_io_input) } /************************************* -* UART0 interrupt handler +* UART1 interrupt handler *************************************/ -WRITE_LINE_MEMBER(atlantis_state::uart0_irq_callback) +WRITE_LINE_MEMBER(atlantis_state::uart1_irq_callback) { - uint32_t status_bit = (1 << UART0_SHIFT); + uint32_t status_bit = (1 << UART1_SHIFT); if (state && !(board_ctrl[CTRL_STATUS] & status_bit)) { board_ctrl[CTRL_STATUS] |= status_bit; update_asic_irq(); @@ -428,15 +433,15 @@ WRITE_LINE_MEMBER(atlantis_state::uart0_irq_callback) board_ctrl[CTRL_CAUSE] &= ~status_bit; update_asic_irq(); } - logerror("atlantis_state::uart0_irq_callback state = %1x\n", state); + logerror("atlantis_state::uart1_irq_callback state = %1x\n", state); } /************************************* -* UART1 interrupt handler +* UART2 interrupt handler *************************************/ -WRITE_LINE_MEMBER(atlantis_state::uart1_irq_callback) +WRITE_LINE_MEMBER(atlantis_state::uart2_irq_callback) { - uint32_t status_bit = (1 << UART1_SHIFT); + uint32_t status_bit = (1 << UART2_SHIFT); if (state && !(board_ctrl[CTRL_STATUS] & status_bit)) { board_ctrl[CTRL_STATUS] |= status_bit; update_asic_irq(); @@ -446,7 +451,7 @@ WRITE_LINE_MEMBER(atlantis_state::uart1_irq_callback) board_ctrl[CTRL_CAUSE] &= ~status_bit; update_asic_irq(); } - logerror("atlantis_state::uart1_irq_callback state = %1x\n", state); + logerror("atlantis_state::uart2_irq_callback state = %1x\n", state); } /************************************* @@ -639,8 +644,8 @@ void atlantis_state::machine_reset() *************************************/ static ADDRESS_MAP_START( map0, AS_PROGRAM, 32, atlantis_state ) AM_RANGE(0x00000000, 0x0001ffff) AM_READWRITE8(cmos_r, cmos_w, 0xff) - AM_RANGE(0x00100000, 0x0010001f) AM_DEVREADWRITE8("uart0", ns16550_device, ins8250_r, ins8250_w, 0xff) // Serial UART0 (TL16C552 CS0) - AM_RANGE(0x00180000, 0x0018001f) AM_DEVREADWRITE8("uart1", ns16550_device, ins8250_r, ins8250_w, 0xff) // Serial UART1 (TL16C552 CS1) + AM_RANGE(0x00100000, 0x0010001f) AM_DEVREADWRITE8("uart1", ns16550_device, ins8250_r, ins8250_w, 0xff) // Serial UART1 (TL16C552 CS0) + AM_RANGE(0x00180000, 0x0018001f) AM_DEVREADWRITE8("uart2", ns16550_device, ins8250_r, ins8250_w, 0xff) // Serial UART2 (TL16C552 CS1) //AM_RANGE(0x00200000, 0x0020001f) // Parallel UART (TL16C552 CS2) AM_RANGE(0x00400000, 0x004000bf) AM_READWRITE8(blue_r, blue_w, 0xff) AM_RANGE(0x00880000, 0x00c80003) AM_READWRITE(board_ctrl_r, board_ctrl_w) @@ -799,6 +804,15 @@ static INPUT_PORTS_START( mwskins ) INPUT_PORTS_END +static DEVICE_INPUT_DEFAULTS_START(mwskins_comm) + DEVICE_INPUT_DEFAULTS("RS232_TXBAUD", 0xff, RS232_BAUD_14400) + DEVICE_INPUT_DEFAULTS("RS232_RXBAUD", 0xff, RS232_BAUD_14400) + DEVICE_INPUT_DEFAULTS("RS232_STARTBITS", 0xff, RS232_STARTBITS_1) + DEVICE_INPUT_DEFAULTS("RS232_DATABITS", 0xff, RS232_DATABITS_8) + DEVICE_INPUT_DEFAULTS("RS232_PARITY", 0xff, RS232_PARITY_NONE) + DEVICE_INPUT_DEFAULTS("RS232_STOPBITS", 0xff, RS232_STOPBITS_1) +DEVICE_INPUT_DEFAULTS_END + /************************************* * * Machine driver @@ -843,8 +857,8 @@ static MACHINE_CONFIG_START( mwskins, atlantis_state ) /* sound hardware */ //MCFG_DEVICE_ADD("dcs", DCS2_AUDIO_DSIO, 0) MCFG_DEVICE_ADD("dcs", DCS2_AUDIO_DENVER, 0) - MCFG_DCS2_AUDIO_DRAM_IN_MB(4) - MCFG_DCS2_AUDIO_POLLING_OFFSET(0) /* no place to hook :-( */ + MCFG_DCS2_AUDIO_DRAM_IN_MB(8) + //MCFG_DCS2_AUDIO_POLLING_OFFSET(0) /* no place to hook :-( */ MCFG_DEVICE_ADD("ioasic", MIDWAY_IOASIC, 0) MCFG_MIDWAY_IOASIC_SHUFFLE(MIDWAY_IOASIC_STANDARD) @@ -852,17 +866,42 @@ static MACHINE_CONFIG_START( mwskins, atlantis_state ) MCFG_MIDWAY_IOASIC_UPPER(325) MCFG_MIDWAY_IOASIC_IRQ_CALLBACK(WRITELINE(atlantis_state, ioasic_irq)) MCFG_MIDWAY_IOASIC_AUTO_ACK(1) + if DEBUG_CONSOLE { + MCFG_MIDWAY_IOASIC_OUT_TX_CB(DEVWRITE8("uart0", generic_terminal_device, write)) + MCFG_DEVICE_ADD("uart0", GENERIC_TERMINAL, 0) + MCFG_GENERIC_TERMINAL_KEYBOARD_CB(DEVWRITE8("ioasic", midway_ioasic_device, serial_rx_w)) + } // TL16C552 UART - MCFG_DEVICE_ADD("uart0", NS16550, XTAL_24MHz) - MCFG_INS8250_OUT_INT_CB(DEVWRITELINE(":", atlantis_state, uart0_irq_callback)) MCFG_DEVICE_ADD("uart1", NS16550, XTAL_24MHz) - MCFG_INS8250_OUT_INT_CB(DEVWRITELINE(":", atlantis_state, uart1_irq_callback)) - + //MCFG_INS8250_OUT_TX_CB(DEVWRITELINE("com1", rs232_port_device, write_txd)) + //MCFG_INS8250_OUT_DTR_CB(DEVWRITELINE("com1", rs232_port_device, write_dtr)) + //MCFG_INS8250_OUT_RTS_CB(DEVWRITELINE("com1", rs232_port_device, write_rts)) + //MCFG_INS8250_OUT_INT_CB(DEVWRITELINE(":", atlantis_state, uart1_irq_callback)) + + MCFG_DEVICE_ADD("uart2", NS16550, XTAL_24MHz) + //MCFG_INS8250_OUT_TX_CB(DEVWRITELINE("com2", rs232_port_device, write_txd)) + //MCFG_INS8250_OUT_DTR_CB(DEVWRITELINE("com2", rs232_port_device, write_dtr)) + //MCFG_INS8250_OUT_RTS_CB(DEVWRITELINE("com2", rs232_port_device, write_rts)) + //MCFG_INS8250_OUT_INT_CB(DEVWRITELINE(":", atlantis_state, uart2_irq_callback)) + + //MCFG_RS232_PORT_ADD("com1", default_rs232_devices, nullptr) + //MCFG_RS232_RXD_HANDLER(DEVWRITELINE("uart1", ins8250_uart_device, rx_w)) + //MCFG_RS232_DCD_HANDLER(DEVWRITELINE("uart1", ins8250_uart_device, dcd_w)) + //MCFG_RS232_DSR_HANDLER(DEVWRITELINE("uart1", ins8250_uart_device, dsr_w)) + //MCFG_RS232_RI_HANDLER(DEVWRITELINE("uart1", ins8250_uart_device, ri_w)) + //MCFG_RS232_CTS_HANDLER(DEVWRITELINE("uart1", ins8250_uart_device, cts_w)) + //MCFG_DEVICE_CARD_DEVICE_INPUT_DEFAULTS("com1", mwskins_comm) + + //MCFG_RS232_PORT_ADD("com2", default_rs232_devices, nullptr) + //MCFG_RS232_RXD_HANDLER(DEVWRITELINE("uart2", ins8250_uart_device, rx_w)) + //MCFG_RS232_DCD_HANDLER(DEVWRITELINE("uart2", ins8250_uart_device, dcd_w)) + //MCFG_RS232_DSR_HANDLER(DEVWRITELINE("uart2", ins8250_uart_device, dsr_w)) + //MCFG_RS232_RI_HANDLER(DEVWRITELINE("uart2", ins8250_uart_device, ri_w)) + //MCFG_RS232_CTS_HANDLER(DEVWRITELINE("uart2", ins8250_uart_device, cts_w)) MACHINE_CONFIG_END - /************************************* * * ROM definition(s) diff --git a/src/mame/drivers/iteagle.cpp b/src/mame/drivers/iteagle.cpp index 79c605cc60a..6d67650daae 100644 --- a/src/mame/drivers/iteagle.cpp +++ b/src/mame/drivers/iteagle.cpp @@ -183,7 +183,7 @@ MACHINE_CONFIG_END static MACHINE_CONFIG_DERIVED( gtfore01, iteagle ) MCFG_DEVICE_MODIFY(PCI_ID_FPGA) - MCFG_ITEAGLE_FPGA_INIT(0x00000401, 0x0b0b0b) + MCFG_ITEAGLE_FPGA_INIT(0x01000401, 0x0b0b0b) MCFG_DEVICE_MODIFY(PCI_ID_EEPROM) MCFG_ITEAGLE_EEPROM_INIT(0x0401, 0x7) MACHINE_CONFIG_END @@ -290,8 +290,8 @@ static INPUT_PORTS_START( iteagle ) PORT_BIT( 0xfe00, IP_ACTIVE_LOW, IPT_UNKNOWN ) PORT_START("SYSTEM") - PORT_BIT( 0x0001, IP_ACTIVE_LOW, IPT_TILT ) PORT_NAME( "Test" ) - PORT_BIT( 0x0002, IP_ACTIVE_LOW, IPT_SERVICE ) + PORT_BIT( 0x0001, IP_ACTIVE_LOW, IPT_SERVICE ) PORT_NAME( "Service" ) + PORT_BIT( 0x0002, IP_ACTIVE_LOW, IPT_SERVICE1 ) PORT_BIT( 0x000c, IP_ACTIVE_LOW, IPT_UNKNOWN ) PORT_DIPNAME( 0x0010, 0x00, "SW51-1" ) PORT_DIPSETTING(0x00, "Normal" ) diff --git a/src/mame/drivers/vegas.cpp b/src/mame/drivers/vegas.cpp index 893f25df22f..33e7e4cabce 100644 --- a/src/mame/drivers/vegas.cpp +++ b/src/mame/drivers/vegas.cpp @@ -1244,7 +1244,7 @@ WRITE32_MEMBER( vegas_state::nile_w ) break; case NREG_UARTTHR: /* serial port output */ - if (PRINTF_SERIAL) osd_printf_debug("%c", data & 0xff); + if (PRINTF_SERIAL) osd_printf_info("%c", data & 0xff); logit = 0; break; case NREG_UARTIER: /* serial interrupt enable */ diff --git a/src/mame/machine/iteagle_fpga.cpp b/src/mame/machine/iteagle_fpga.cpp index 06a2af0170e..0c700409bc7 100644 --- a/src/mame/machine/iteagle_fpga.cpp +++ b/src/mame/machine/iteagle_fpga.cpp @@ -10,10 +10,30 @@ #define LOG_EEPROM (0) #define LOG_PERIPH (0) +#define AM85C30_TAG "am85c30_0" +#define COM1_TAG "com1" +#define COM2_TAG "com2" + const device_type ITEAGLE_FPGA = &device_creator; MACHINE_CONFIG_FRAGMENT(iteagle_fpga) MCFG_NVRAM_ADD_0FILL("eagle2_rtc") + // RS232 serial ports + //MCFG_SCC85C30_ADD(AM85C30_TAG, XTAL_7_3728MHz, XTAL_1_8432MHz, 0, XTAL_1_8432MHz, 0) + MCFG_SCC85C30_ADD(AM85C30_TAG, XTAL_1_8432MHz, XTAL_1_8432MHz, 0, XTAL_1_8432MHz, 0) + MCFG_Z80SCC_OUT_INT_CB(WRITELINE(iteagle_fpga_device, serial_interrupt)) + MCFG_Z80SCC_OUT_TXDA_CB(DEVWRITELINE(COM2_TAG, rs232_port_device, write_txd)) + MCFG_Z80SCC_OUT_TXDB_CB(DEVWRITELINE(COM1_TAG, rs232_port_device, write_txd)) + + MCFG_RS232_PORT_ADD(COM1_TAG, default_rs232_devices, nullptr) + MCFG_RS232_RXD_HANDLER(DEVWRITELINE(AM85C30_TAG, scc85C30_device, rxb_w)) + MCFG_RS232_DCD_HANDLER(DEVWRITELINE(AM85C30_TAG, scc85C30_device, dcdb_w)) + MCFG_RS232_CTS_HANDLER(DEVWRITELINE(AM85C30_TAG, scc85C30_device, ctsb_w)) + + MCFG_RS232_PORT_ADD(COM2_TAG, default_rs232_devices, nullptr) + MCFG_RS232_RXD_HANDLER(DEVWRITELINE(AM85C30_TAG, scc85C30_device, rxa_w)) + MCFG_RS232_DCD_HANDLER(DEVWRITELINE(AM85C30_TAG, scc85C30_device, dcda_w)) + MCFG_RS232_CTS_HANDLER(DEVWRITELINE(AM85C30_TAG, scc85C30_device, ctsa_w)) MACHINE_CONFIG_END DEVICE_ADDRESS_MAP_START(fpga_map, 32, iteagle_fpga_device) @@ -30,7 +50,7 @@ ADDRESS_MAP_END iteagle_fpga_device::iteagle_fpga_device(const machine_config &mconfig, const char *tag, device_t *owner, uint32_t clock) : pci_device(mconfig, ITEAGLE_FPGA, "ITEagle FPGA", tag, owner, clock, "iteagle_fpga", __FILE__), - m_rtc(*this, "eagle2_rtc"), m_version(0), m_seq_init(0) + m_rtc(*this, "eagle2_rtc"), m_scc1(*this, AM85C30_TAG), m_version(0), m_seq_init(0) { } @@ -167,6 +187,24 @@ void iteagle_fpga_device::device_timer(emu_timer &timer, device_timer_id tid, in } +WRITE_LINE_MEMBER(iteagle_fpga_device::serial_interrupt) +{ + osd_printf_info("serial_interrupt: intr(%i) = %i\n", m_serial_irq_num, state); + m_cpu->set_input_line(m_serial_irq_num, state); +} + +WRITE8_MEMBER(iteagle_fpga_device::serial_rx_w) +{ + std::string tmpStr; + tmpStr += data; + //osd_printf_info("serial_rx_w: %02x\n", data); + m_serial0_1.write_rx_str(1, tmpStr); + if (0 && m_serial0_1.check_interrupt()) { + osd_printf_info("serial_rx_w: %02x\n", data); + m_cpu->set_input_line(m_serial_irq_num, ASSERT_LINE); + } +} + READ32_MEMBER( iteagle_fpga_device::fpga_r ) { uint32_t result = m_fpga_regs[offset]; @@ -179,7 +217,7 @@ READ32_MEMBER( iteagle_fpga_device::fpga_r ) break; case 0x04/4: result = (result & 0xFF0FFFFF) | ((machine().root_device().ioport("SW5")->read()&0xf)<<20); - if (LOG_FPGA && !ACCESSING_BITS_0_7) + if (0 && LOG_FPGA && !ACCESSING_BITS_0_7) logerror("%s:fpga_r offset %04X = %08X & %08X\n", machine().describe_context(), offset*4, result, mem_mask); break; case 0x08/4: @@ -200,21 +238,25 @@ READ32_MEMBER( iteagle_fpga_device::fpga_r ) case 0x0c/4: // result = 0; if (ACCESSING_BITS_0_7) { - result |= m_serial0_1.read_control(1) << 0; + result |= m_scc1->cb_r(space, offset) << 0; + if (LOG_SERIAL) m_serial0_1.read_control(1); } if (ACCESSING_BITS_8_15) { - result |= m_serial0_1.read_control(0) << 8; + result |= m_scc1->ca_r(space, offset) << 8; + if (LOG_SERIAL) m_serial0_1.read_control(0); } if (ACCESSING_BITS_16_23) { - result |= m_serial0_1.read_data(1) << 16; + result |= m_scc1->db_r(space, offset) <<16; + if (LOG_SERIAL) m_serial0_1.read_data(1); } if (ACCESSING_BITS_24_31) { - result |= m_serial0_1.read_data(0) << 24; + result |= m_scc1->da_r(space, offset) << 24; + if (LOG_SERIAL) m_serial0_1.read_data(0); } if (1 && LOG_FPGA) logerror("%s:fpga_r offset %04X = %08X & %08X\n", machine().describe_context(), offset*4, result, mem_mask); break; - case 0x1c/4: // 1d = modem byte + case 0x1c/4: result = 0; if (ACCESSING_BITS_0_7) { result |= m_serial2_3.read_control(1) << 0; @@ -224,12 +266,10 @@ READ32_MEMBER( iteagle_fpga_device::fpga_r ) } if (ACCESSING_BITS_16_23) { result |= m_serial2_3.read_data(1) << 16; - // MODEM - logerror("fpga_r: LEDSIGN read byte: %c\n", (result >> 16) & 0xff); + logerror("fpga_r: LEDSIGN read byte: %02X\n", uint8_t(result >> 16)); } if (ACCESSING_BITS_24_31) { result |= m_serial2_3.read_data(0) << 24; - // LED Sign logerror("fpga_r: MODEM read byte: %c\n", (result >> 24) & 0xff); } // Clear interrupts @@ -297,23 +337,34 @@ WRITE32_MEMBER( iteagle_fpga_device::fpga_w ) break; case 0x0c/4: if (ACCESSING_BITS_0_7) { - m_serial0_1.write_control((data >> 0) & 0xff, 1); + m_scc1->cb_w(space, offset, (data >> 0) & 0xff); + if (LOG_SERIAL) m_serial0_1.write_control((data >> 0) & 0xff, 1); } if (ACCESSING_BITS_8_15) { - m_serial0_1.write_control((data >> 8) & 0xff, 0); + m_scc1->ca_w(space, offset, (data >> 8) & 0xff); + if (LOG_SERIAL) m_serial0_1.write_control((data >> 8) & 0xff, 0); } if (ACCESSING_BITS_16_23) { - m_serial0_1.write_data((data >> 16) & 0xff, 1); - if (m_serial0_1.get_tx_str(1).back() == 0xd) { - if (LOG_SERIAL) logerror("com0: %s\n", m_serial0_1.get_tx_str(1).c_str()); - osd_printf_debug("com0: %s\n", m_serial0_1.get_tx_str(1).c_str()); - m_serial0_1.clear_tx_str(1); + // Convert 0xd to 0xa + uint8_t byte = data >> 16; + if (byte==0xd) + m_scc1->db_w(space, offset, 0xa); + else + m_scc1->db_w(space, offset, byte); + if (LOG_SERIAL) { + m_serial0_1.write_data((data >> 16) & 0xff, 1); + if (m_serial0_1.get_tx_str(1).back() == 0xd) { + logerror("com0: %s", m_serial0_1.get_tx_str(1).c_str()); + osd_printf_info("com0: %s\n", m_serial0_1.get_tx_str(1).c_str()); + m_serial0_1.clear_tx_str(1); + } } } if (ACCESSING_BITS_24_31) { - m_serial0_1.write_data((data >> 24) & 0xff, 0); + m_scc1->da_w(space, offset, (data >> 24) & 0xff); + if (LOG_SERIAL) m_serial0_1.write_data((data >> 24) & 0xff, 0); } - if (0 && LOG_FPGA) + if (1 && LOG_FPGA) logerror("%s:fpga_w offset %04X = %08X & %08X\n", machine().describe_context(), offset*4, data, mem_mask); break; case 0x1c/4: @@ -326,12 +377,28 @@ WRITE32_MEMBER( iteagle_fpga_device::fpga_w ) if (ACCESSING_BITS_16_23) { int chan = 1; m_serial2_3.write_data((data >> 16) & 0xff, chan); - if (m_serial2_3.get_tx_str(chan).length() == 8) { - if (LOG_SERIAL) logerror("com2: %s\n", m_serial2_3.get_tx_str(chan).c_str()); - osd_printf_debug("com2: %s\n", m_serial2_3.get_tx_str(chan).c_str()); - m_serial2_3.clear_tx_str(chan); - // Set Response - m_serial2_3.write_rx_str(chan, "\x08"); + std::string txString = m_serial2_3.get_tx_str(chan); + if (txString.length() >= 8) { + int length = (uint8_t(txString[4]) << 8) | uint8_t(txString[5]); + if (txString.length() >= length) { + osd_printf_debug("com2:"); + if (LOG_SERIAL) logerror("com2:\n"); + for (int i = 0; i < txString.length(); i++) { + if (LOG_SERIAL) logerror(" %02x", uint8_t(txString[i])); + osd_printf_debug(" %02x", uint8_t(txString[i])); + if ((i + 1) % 16 == 0 || i==length-1) { + osd_printf_debug("\n"); + if (LOG_SERIAL) logerror("\n"); + } + } + osd_printf_debug("\n"); + // Set Sign Response ACK + //if (txString[0]==0x01 || txString[0] == 0x23) + m_serial2_3.write_rx_str(chan, "\x10"); + // Clear string + m_serial2_3.clear_tx_str(chan); + txString.clear(); + } } } if (ACCESSING_BITS_24_31) { @@ -386,8 +453,8 @@ void iteagle_am85c30::write_control(uint8_t data, int channel) // Reset address pointer to 0 if (addr != 0) { m_wr_regs[channel][0] = 0; - // Mirror wr2 to rr2 - m_rr_regs[channel][2] = m_wr_regs[channel][2]; + // Mirror wr2 to rr2[chan0] + m_rr_regs[0][2] = m_wr_regs[channel][2]; } } @@ -413,7 +480,7 @@ void iteagle_am85c30::write_data(uint8_t data, int channel) m_rr_regs[1][3] = m_rr_regs[0][3]; } // Limit length - if (m_serial_tx[channel].size() >= 160) { + if (m_serial_tx[channel].size() >= 4000) { if (LOG_SERIAL) printf("%s\n", m_serial_tx[channel].c_str()); osd_printf_debug("%s\n", m_serial_tx[channel].c_str()); m_serial_tx[channel].clear(); @@ -547,6 +614,7 @@ iteagle_eeprom_device::iteagle_eeprom_device(const machine_config &mconfig, cons // 0x4 = HW Version - 6-8 is GREEN board PCB, 9 is RED board PCB // 0x5 = Serial Num + top byte of 0x4 // 0x6 = OperID + // 0xd = GT Fore Tournament Board // 0xe = SW Version // 0xf = 0x01 for extra courses // 0x3e = 0x0002 for good nvram @@ -554,7 +622,7 @@ iteagle_eeprom_device::iteagle_eeprom_device(const machine_config &mconfig, cons m_iteagle_default_eeprom = { { 0xd000,0x0022,0x0000,0x0003,0x1209,0x1111,0x2222,0x1234, - 0x0000,0x0000,0x0000,0x0000,0xcd00,0x0000,0x0000,0x0001, + 0x0000,0x0000,0x0000,0x0000,0xcd00,0x0001,0x0000,0x0001, 0x0000,0x0000,0x0000,0x0000,0x0000,0x0000,0x0000,0x0000, 0x0000,0x0000,0x0000,0x0000,0x0000,0x0000,0x0000,0x0000, 0x0000,0x0000,0x0000,0x0000,0x0000,0x0000,0x0000,0x0000, diff --git a/src/mame/machine/iteagle_fpga.h b/src/mame/machine/iteagle_fpga.h index edc56984aab..f0cef354373 100644 --- a/src/mame/machine/iteagle_fpga.h +++ b/src/mame/machine/iteagle_fpga.h @@ -9,6 +9,8 @@ #include "machine/pci.h" #include "machine/nvram.h" #include "machine/eepromser.h" +#include "machine/z80scc.h" +#include "bus/rs232/rs232.h" //MCFG_PCI_DEVICE_ADD(_tag, _type, _main_id, _revision, _pclass, _subsystem_id) @@ -57,11 +59,15 @@ public: virtual machine_config_constructor device_mconfig_additions() const override; required_device m_rtc; + required_device m_scc1; void set_init_info(int version, int seq_init) {m_version=version; m_seq_init=seq_init;} void set_irq_info(const char *tag, const int irq_num, const int serial_num) { m_cpu_tag = tag; m_irq_num = irq_num; m_serial_irq_num = serial_num;} + DECLARE_WRITE_LINE_MEMBER(serial_interrupt); + DECLARE_WRITE8_MEMBER(serial_rx_w); + protected: virtual void device_start() override; virtual void device_reset() override; diff --git a/src/mame/machine/midwayic.cpp b/src/mame/machine/midwayic.cpp index 52247aac96a..1c64c27ddb7 100644 --- a/src/mame/machine/midwayic.cpp +++ b/src/mame/machine/midwayic.cpp @@ -593,6 +593,7 @@ const device_type MIDWAY_IOASIC = &device_creator; midway_ioasic_device::midway_ioasic_device(const machine_config &mconfig, const char *tag, device_t *owner, uint32_t clock) : midway_serial_pic2_device(mconfig, MIDWAY_IOASIC, "Midway IOASIC", tag, owner, clock, "midway_ioasic", __FILE__), + m_serial_tx_cb(*this), m_has_dcs(0), m_has_cage(0), m_dcs_cpu(nullptr), @@ -657,6 +658,7 @@ void midway_ioasic_device::device_start() m_shuffle_map = &shuffle_maps[m_shuffle_type][0]; // resolve callbacks m_irq_callback.resolve_safe(); + m_serial_tx_cb.resolve_safe(); /* initialize the PIC */ midway_serial_pic2_device::device_start(); @@ -1028,6 +1030,12 @@ WRITE32_MEMBER( midway_ioasic_device::packed_w ) write(space, offset*2+1, data >> 16, 0x0000ffff); } +WRITE8_MEMBER(midway_ioasic_device::serial_rx_w) +{ + m_reg[IOASIC_UARTIN] = data | 0x1000; + update_ioasic_irq(); + +} WRITE32_MEMBER( midway_ioasic_device::write ) { @@ -1068,8 +1076,13 @@ WRITE32_MEMBER( midway_ioasic_device::write ) m_reg[IOASIC_UARTIN] = (newreg & 0x00ff) | 0x1000; update_ioasic_irq(); } - else if (PRINTF_DEBUG) - osd_printf_debug("%c", data & 0xff); + else { + m_serial_tx_cb(data & 0xff); + if (PRINTF_DEBUG) { + osd_printf_info("%c", data & 0xff); + logerror("%c", data & 0xff); + } + } break; case IOASIC_SOUNDCTL: diff --git a/src/mame/machine/midwayic.h b/src/mame/machine/midwayic.h index 707988ce60e..a10a0a93e0d 100644 --- a/src/mame/machine/midwayic.h +++ b/src/mame/machine/midwayic.h @@ -125,6 +125,7 @@ public: static void static_set_shuffle_default(device_t &device, uint8_t shuffle) { downcast(device).m_shuffle_default = shuffle; } static void static_set_auto_ack(device_t &device, uint8_t auto_ack) { downcast(device).m_auto_ack = auto_ack; } template static devcb_base &set_irqhandler_callback(device_t &device, _Object object) { return downcast(device).m_irq_callback.set_callback(object); } + template static devcb_base &set_serial_tx_callback(device_t &device, _Object object) { return downcast(device).m_serial_tx_cb.set_callback(object); } void set_shuffle_state(int state); void fifo_w(uint16_t data); @@ -145,6 +146,8 @@ public: DECLARE_WRITE8_MEMBER(cage_irq_handler); + DECLARE_WRITE8_MEMBER(serial_rx_w); + void ioasic_reset(); protected: @@ -155,6 +158,7 @@ private: void ioasic_register_state(); void update_ioasic_irq(); + devcb_write8 m_serial_tx_cb; uint32_t m_reg[16]; uint8_t m_has_dcs; @@ -200,6 +204,9 @@ extern const device_type MIDWAY_IOASIC; #define MCFG_MIDWAY_IOASIC_AUTO_ACK(_ack) \ midway_ioasic_device::static_set_auto_ack(*device, _ack); +#define MCFG_MIDWAY_IOASIC_OUT_TX_CB(_devcb) \ + devcb = &midway_ioasic_device::set_serial_tx_callback(*device, DEVCB_##_devcb); + enum { -- cgit v1.2.3