From c046ba26c0322d5fe96f8f8ba675d64bf7039063 Mon Sep 17 00:00:00 2001 From: MooglyGuy Date: Wed, 8 Jun 2022 19:26:49 +0200 Subject: cpu/dps56156, plygonet.cpp: DSP56156 fixes and plygonet.cpp cleanup: (#9894) [Ryan Holtz] * cpu/dsp56156: Fixed ANDI, fixed BFCLR errata, fixed DEC24 not affecting flags. * cpu/dsp56156: Added proper devcb_write16 for Port C output. * plygonet.cpp: Fixed banking and tightened up VRAM access. * plygonet.cpp: Account for endianness in tilemap accesses. * plygonet.cpp: Switched to logmacro, merged into one file, and general code cleanup. --- scripts/target/mame/arcade.lua | 2 - src/devices/cpu/dsp56156/dsp56156.cpp | 4 + src/devices/cpu/dsp56156/dsp56156.h | 21 +- src/devices/cpu/dsp56156/dsp56mem.cpp | 19 +- src/devices/cpu/dsp56156/dsp56ops.hxx | 24 +- src/mame/drivers/plygonet.cpp | 1032 +++++++++++++++++++++------------ src/mame/includes/plygonet.h | 124 ---- src/mame/video/plygonet.cpp | 131 ----- 8 files changed, 689 insertions(+), 668 deletions(-) delete mode 100644 src/mame/includes/plygonet.h delete mode 100644 src/mame/video/plygonet.cpp diff --git a/scripts/target/mame/arcade.lua b/scripts/target/mame/arcade.lua index 8cd878e6950..9e6cf76d71e 100644 --- a/scripts/target/mame/arcade.lua +++ b/scripts/target/mame/arcade.lua @@ -2564,8 +2564,6 @@ files { MAME_DIR .. "src/mame/video/pingpong.cpp", MAME_DIR .. "src/mame/drivers/piratesh.cpp", MAME_DIR .. "src/mame/drivers/plygonet.cpp", - MAME_DIR .. "src/mame/includes/plygonet.h", - MAME_DIR .. "src/mame/video/plygonet.cpp", MAME_DIR .. "src/mame/drivers/pooyan.cpp", MAME_DIR .. "src/mame/includes/pooyan.h", MAME_DIR .. "src/mame/video/pooyan.cpp", diff --git a/src/devices/cpu/dsp56156/dsp56156.cpp b/src/devices/cpu/dsp56156/dsp56156.cpp index 1b93948adf5..f8685d080ae 100644 --- a/src/devices/cpu/dsp56156/dsp56156.cpp +++ b/src/devices/cpu/dsp56156/dsp56156.cpp @@ -127,6 +127,7 @@ dsp56156_device::dsp56156_device(const machine_config &mconfig, const char *tag, , m_program_config("program", ENDIANNESS_LITTLE, 16, 16, -1, address_map_constructor(FUNC(dsp56156_device::dsp56156_program_map), this)) , m_data_config("data", ENDIANNESS_LITTLE, 16, 16, -1, address_map_constructor(FUNC(dsp56156_device::dsp56156_x_data_map), this)) , m_program_ram(*this, "dsk56156_program_ram") + , portC_cb(*this) { } @@ -268,6 +269,9 @@ void dsp56156_device::device_start() m_core.modC_state = false; m_core.reset_state = false; + /* Resolve line callbacks */ + portC_cb.resolve_safe(); + /* save states - dsp56156_core members */ save_item(NAME(m_core.modA_state)); save_item(NAME(m_core.modB_state)); diff --git a/src/devices/cpu/dsp56156/dsp56156.h b/src/devices/cpu/dsp56156/dsp56156.h index cc8ebe6741d..4778dd20438 100644 --- a/src/devices/cpu/dsp56156/dsp56156.h +++ b/src/devices/cpu/dsp56156/dsp56156.h @@ -23,9 +23,10 @@ #define DSP56156_IRQ_MODC 2 #define DSP56156_IRQ_RESET 3 /* Is this needed? */ - namespace DSP_56156 { +class dsp56156_device; + /*************************************************************************** STRUCTURES & TYPEDEFS ***************************************************************************/ @@ -182,15 +183,14 @@ struct dsp56156_core uint8_t repFlag; // Knowing if we're in a 'repeat' state (dunno how the processor does this) uint32_t repAddr; // The address of the instruction to repeat... - - /* MAME internal stuff */ + // MAME internal stuff int icount; uint32_t ppc; uint32_t op; - int interrupt_cycles; - void (*output_pins_changed)(uint32_t pins); - cpu_device *device; + int interrupt_cycles; + void (*output_pins_changed)(uint32_t pins); + dsp56156_device *device; memory_access<16, 1, -1, ENDIANNESS_LITTLE>::cache cache; memory_access<16, 1, -1, ENDIANNESS_LITTLE>::specific program; memory_access<16, 1, -1, ENDIANNESS_LITTLE>::specific data; @@ -211,10 +211,13 @@ public: void host_interface_write(uint8_t offset, uint8_t data); uint8_t host_interface_read(uint8_t offset); - uint16_t get_peripheral_memory(uint16_t addr); - void dsp56156_program_map(address_map &map); void dsp56156_x_data_map(address_map &map); + + auto portc_cb() { return portC_cb.bind(); } + + void output_portc(uint16_t value) { portC_cb(value); } + protected: // device-level overrides virtual void device_start() override; @@ -246,6 +249,8 @@ private: dsp56156_core m_core; + devcb_write16 portC_cb; + void agu_init(); void alu_init(); }; diff --git a/src/devices/cpu/dsp56156/dsp56mem.cpp b/src/devices/cpu/dsp56156/dsp56mem.cpp index 9f61089b9b4..4e53799e75a 100644 --- a/src/devices/cpu/dsp56156/dsp56mem.cpp +++ b/src/devices/cpu/dsp56156/dsp56mem.cpp @@ -47,6 +47,7 @@ void mem_reset(dsp56156_core* cpustate) /************************************/ void HCR_set(dsp56156_core* cpustate, uint16_t value) { + cpustate->device->logerror("HCR_set: %02x\n", value); HF3_bit_set (cpustate, (value & 0x0010) >> 4); HF2_bit_set (cpustate, (value & 0x0008) >> 3); HCIE_bit_set(cpustate, (value & 0x0004) >> 2); @@ -65,6 +66,7 @@ void HF3_bit_set(dsp56156_core* cpustate, uint16_t value) HCR &= ~(0x0010); HCR |= (value << 4); + cpustate->device->logerror("HF3_bit_set: %d\n", value); HF3_bit_host_set(cpustate, value); } void HF2_bit_set(dsp56156_core* cpustate, uint16_t value) @@ -73,6 +75,7 @@ void HF2_bit_set(dsp56156_core* cpustate, uint16_t value) HCR &= ~(0x0008); HCR |= (value << 3); + cpustate->device->logerror("HF2_bit_set: %d\n", value); HF2_bit_host_set(cpustate, value); } void HCIE_bit_set(dsp56156_core* cpustate, uint16_t value) @@ -468,12 +471,11 @@ void PCD_set(dsp56156_core* cpustate, uint16_t value) if (value & 0xf000) cpustate->device->logerror("Dsp56k : Attempting to set reserved bits in the PCD. Ignoring.\n"); - /* TODO: Temporary */ - cpustate->device->logerror("Dsp56k : Setting general output port C data to 0x%04x\n", value); - value = value & 0x0fff; PCD &= ~(0x0fff); PCD |= (value << 0); + + cpustate->device->output_portc(PCD); } void dsp56156_io_reset(dsp56156_core* cpustate) @@ -888,18 +890,22 @@ uint8_t dsp56156_device::host_interface_read(uint8_t offset) { // Interrupt Control Register (ICR) case 0x00: + logerror("DSP: Returning ICR\n"); return ICR; // Command Vector Register (CVR) case 0x01: + logerror("DSP: Returning CVR\n"); return CVR; // Interrupt status register (ISR) case 0x02: + logerror("DSP: Returning ISR\n"); return ISR; // Interrupt vector register (IVR) case 0x03: + logerror("DSP: Returning IVR\n"); return IVR; // Read zeroes @@ -938,12 +944,5 @@ uint8_t dsp56156_device::host_interface_read(uint8_t offset) return 0xff; } -/* MISC*/ -uint16_t dsp56156_device::get_peripheral_memory(uint16_t addr) -{ - dsp56156_core* cpustate = &m_core; - return cpustate->peripheral_ram[A2O(addr)]; -} - } // namespace DSP_56156 diff --git a/src/devices/cpu/dsp56156/dsp56ops.hxx b/src/devices/cpu/dsp56156/dsp56ops.hxx index d6b2b82f97d..f61afaf7703 100644 --- a/src/devices/cpu/dsp56156/dsp56ops.hxx +++ b/src/devices/cpu/dsp56156/dsp56ops.hxx @@ -21,7 +21,6 @@ TODO: - 0x01ee: should this move sign extend? otherwise the test-against-minus means nothing. - Restore only the proper bits upon loop termination! - - BFCLR has some errata in the docs that may need to be applied. */ /************************/ @@ -1818,6 +1817,7 @@ static size_t dsp56156_op_dec24(dsp56156_core* cpustate, const uint16_t op_byte, /* TODO: I wonder if workBits24 should be signed? */ workBits24 = ((*((uint64_t*)D.addr)) & 0x000000ffffff0000U) >> 16; workBits24--; + bool carry(workBits24 & 0x01000000); workBits24 &= 0x00ffffff; /* Solves -x issues */ /* Set the D bits with the dec result */ @@ -1829,9 +1829,10 @@ static size_t dsp56156_op_dec24(dsp56156_core* cpustate, const uint16_t op_byte, /* S L E U N Z V C */ /* * * * * * ? * * */ - /* TODO: S, L, E, U, V, C */ + /* TODO: S, L, E, U, V */ if ( *((uint64_t*)D.addr) & 0x0000008000000000U) DSP56156_N_SET(); else DSP56156_N_CLEAR(); if ((*((uint64_t*)D.addr) & 0x000000ffffff0000U) == 0) DSP56156_Z_SET(); else DSP56156_Z_CLEAR(); + if (carry) DSP56156_C_SET(); else DSP56156_C_CLEAR(); cycles += 2; /* TODO: + mv oscillator clock cycles */ return 1; @@ -2185,12 +2186,12 @@ static size_t dsp56156_op_andi(dsp56156_core* cpustate, const uint16_t op, uint8 SR &= ((immediate << 8) | 0x00ff); break; - case 0x02: /* CCR */ - SR &= (immediate | 0xff00); + case 0x02: /* OMR */ + OMR &= (uint8_t)(immediate); break; - case 0x03: /* OMR */ - OMR &= (uint8_t)(immediate); + case 0x03: /* CCR */ + SR &= (immediate | 0xff00); break; default: @@ -2342,7 +2343,7 @@ static size_t dsp56156_op_bfop(dsp56156_core* cpustate, const uint16_t op, const case 0x12: /* BFCHG */ if ((iVal & previousValue) == iVal) DSP56156_C_SET(); else DSP56156_C_CLEAR(); break; case 0x04: /* BFCLR */ - if ((iVal & previousValue) == iVal) DSP56156_C_SET(); else DSP56156_C_CLEAR(); break; + if ((iVal & previousValue) == 0x0000) DSP56156_C_SET(); else DSP56156_C_CLEAR(); break; case 0x18: /* BFSET */ if ((iVal & previousValue) == iVal) DSP56156_C_SET(); else DSP56156_C_CLEAR(); break; case 0x10: /* BFTSTH */ @@ -2408,7 +2409,7 @@ static size_t dsp56156_op_bfop_1(dsp56156_core* cpustate, const uint16_t op, con case 0x12: /* BFCHG */ if ((iVal & previousValue) == iVal) DSP56156_C_SET(); else DSP56156_C_CLEAR(); break; case 0x04: /* BFCLR */ - if ((iVal & previousValue) == iVal) DSP56156_C_SET(); else DSP56156_C_CLEAR(); break; + if ((iVal & previousValue) == 0x0000) DSP56156_C_SET(); else DSP56156_C_CLEAR(); break; case 0x18: /* BFSET */ if ((iVal & previousValue) == iVal) DSP56156_C_SET(); else DSP56156_C_CLEAR(); break; case 0x10: /* BFTSTH */ @@ -2478,7 +2479,7 @@ static size_t dsp56156_op_bfop_2(dsp56156_core* cpustate, const uint16_t op, con case 0x12: /* BFCHG */ if ((iVal & previousValue) == iVal) DSP56156_C_SET(); else DSP56156_C_CLEAR(); break; case 0x04: /* BFCLR */ - if ((iVal & previousValue) == iVal) DSP56156_C_SET(); else DSP56156_C_CLEAR(); break; + if ((iVal & previousValue) == 0x0000) DSP56156_C_SET(); else DSP56156_C_CLEAR(); break; case 0x18: /* BFSET */ if ((iVal & previousValue) == iVal) DSP56156_C_SET(); else DSP56156_C_CLEAR(); break; case 0x10: /* BFTSTH */ @@ -2855,7 +2856,8 @@ static size_t dsp56156_op_do_2(dsp56156_core* cpustate, const uint16_t op, const /* HACK */ if (lValue >= 0xfff0) { - cpustate->device->logerror("Dsp56156 : DO_2 operation changed %04x to 0000.\n", lValue); + cpustate->device->logerror("Dsp56156 : DO_2 operation changed %04x to 0000, pc:%04x ppc:%04x.\n", lValue, cpustate->PCU.pc, cpustate->ppc); + cpustate->device->machine().debug_break(); lValue = 0x0000; } @@ -2887,6 +2889,8 @@ static size_t dsp56156_op_do_2(dsp56156_core* cpustate, const uint16_t op, const /* Third instruction cycle */ LF_bit_set(cpustate, 1); + /* Undocumented, but it must be true to nest Dos in DoForevers */ + FV_bit_set(cpustate, 0); /* S L E U N Z V C */ /* - * - - - - - - */ diff --git a/src/mame/drivers/plygonet.cpp b/src/mame/drivers/plygonet.cpp index beff89e7103..f4a28cffced 100644 --- a/src/mame/drivers/plygonet.cpp +++ b/src/mame/drivers/plygonet.cpp @@ -1,5 +1,5 @@ // license:BSD-3-Clause -// copyright-holders:R. Belmont, Andrew Gardner +// copyright-holders:R. Belmont, Andrew Gardner, Ryan Holtz /* Polygonet Commanders (Konami, 1993) Poly-Net Warriors (Konami, 1993) @@ -54,65 +54,338 @@ DSP === - 500000-503fff = HCOM - 16kB common RAM + 500000-503fff = HCOM - 16kB shared RAM 504000-504fff = CONTROL - DSP/Host Control - D10? = COMBNK - Switch between 68k and DSP access to common RAM + D10? = COMBNK - Switch between 68k and DSP access to shared RAM D08? = RESN - Reset DSP 506000-506fff = HEN - DSP/Host interface */ #include "emu.h" -#include "includes/plygonet.h" +#include "cpu/dsp56156/dsp56156.h" #include "cpu/m68000/m68000.h" #include "cpu/z80/z80.h" -//#include "machine/k056230.h" +#include "machine/eepromser.h" +#include "machine/k054321.h" #include "machine/watchdog.h" #include "sound/k054539.h" +#include "video/k053936.h" +#include "emupal.h" #include "screen.h" #include "speaker.h" +#include "tilemap.h" + + +#define LOG_DSP_AB0 (1U << 1) +#define LOG_DSP_A6 (1U << 2) +#define LOG_DSP_A7 (1U << 3) +#define LOG_DSP_A8 (1U << 4) +#define LOG_DSP_AC (1U << 5) +#define LOG_DSP_AE (1U << 6) +#define LOG_DSP_B6 (1U << 7) +#define LOG_DSP_B7 (1U << 8) +#define LOG_DSP_B8 (1U << 9) +#define LOG_68K_SHARED (1U << 10) +#define LOG_DSP_HOST_INTF (1U << 11) +#define LOG_DSP_CTRL (1U << 12) +#define LOG_DSP_PORTC (1U << 13) + +#define LOG_ALL_DSP_A (LOG_DSP_AB0 | LOG_DSP_A7 | LOG_DSP_A6 | LOG_DSP_A8 | LOG_DSP_AC | LOG_DSP_AE) +#define LOG_ALL_DSP_B (LOG_DSP_AB0 | LOG_DSP_B6 | LOG_DSP_B7 | LOG_DSP_B8) + +//#define VERBOSE (LOG_ALL_DSP_A | LOG_ALL_DSP_B | LOG_68K_SHARED | LOG_DSP_HOST_INTF | LOG_DSP_CTRL | LOG_DSP_PORTC) +#define VERBOSE (0) +#include "logmacro.h" + + +namespace { + +class polygonet_state : public driver_device +{ +public: + polygonet_state(const machine_config &mconfig, device_type type, const char *tag) : + driver_device(mconfig, type, tag), + m_maincpu(*this, "maincpu"), + m_audiocpu(*this, "audiocpu"), + m_dsp(*this, "dsp"), + m_eeprom(*this, "eeprom"), + m_k053936(*this, "k053936"), + m_gfxdecode(*this, "gfxdecode"), + m_palette(*this, "palette"), + m_ttl_vram(*this, "ttl_vram"), + m_roz_vram(*this, "roz_vram"), + m_k054321(*this, "k054321"), + m_sound_bank(*this, "bank1"), + m_dsp_bank_a_8(*this, "dsp_bank_a_8"), + m_dsp_bank_b_6(*this, "dsp_bank_b_6"), + m_dsp_bank_b_7(*this, "dsp_bank_b_7"), + m_dsp_bank_b_8(*this, "dsp_bank_b_8"), + m_dsp_common(*this, "dsp_common"), + m_dsp_share(*this, "dsp_share"), + m_dsp_ab_0(*this, "dsp_ab_0"), + m_dsp_a_6(*this, "dsp_a_6"), + m_dsp_a_7(*this, "dsp_a_7"), + m_dsp_a_e(*this, "dsp_a_e"), + m_dsp_ram_a_8(*this, "dsp_ram_a_8", 8 * 0x4000U * 2, ENDIANNESS_BIG), + m_dsp_ram_b_6(*this, "dsp_ram_b_6", 4 * 0x1000U * 2, ENDIANNESS_BIG), + m_dsp_ram_b_7(*this, "dsp_ram_b_7", 4 * 0x1000U * 2, ENDIANNESS_BIG), + m_dsp_ram_b_8(*this, "dsp_ram_b_8", 8 * 0x8000U * 2, ENDIANNESS_BIG), + m_dsp_data_view(*this, "dspdata"), + m_inputs(*this, "IN%u", 0U), + m_eepromout(*this, "EEPROMOUT"), + m_sys1(0), + m_dsp_portc(0), + m_ttl_gfx_index(0), + m_ttl_tilemap(nullptr), + m_roz_tilemap(nullptr), + m_sound_ctrl(0), + m_sound_intck(0) + { } + + void plygonet(machine_config &config); + +private: + virtual void machine_start() override; + virtual void machine_reset() override; + virtual void video_start() override; + + void main_map(address_map &map); + void sound_map(address_map &map); + void dsp_program_map(address_map &map); + void dsp_data_map(address_map &map); + + // Main-board handlers + void sys_w(offs_t offset, uint8_t data); + uint8_t inputs_r(offs_t offset); + void sound_irq_w(uint32_t data); + uint32_t dsp_host_interface_r(offs_t offset, uint32_t mem_mask = ~0); + void dsp_host_interface_w(offs_t offset, uint32_t data, uint32_t mem_mask = ~0); + uint32_t shared_ram_read(offs_t offset, uint32_t mem_mask = ~0); + void shared_ram_write(offs_t offset, uint32_t data, uint32_t mem_mask = ~0); + void dsp_w_lines(offs_t offset, uint32_t data, uint32_t mem_mask = ~0); + uint32_t network_r(); + + // DSP handlers + uint16_t dsp_bootload_r(); + void dsp_portc_write(uint16_t data); + uint16_t dsp_ram_ab_0_read(offs_t offset); + void dsp_ram_ab_0_write(offs_t offset, uint16_t data, uint16_t mem_mask = ~0); + uint16_t dsp_ram_a_6_read(offs_t offset); + void dsp_ram_a_6_write(offs_t offset, uint16_t data, uint16_t mem_mask = ~0); + uint16_t dsp_ram_b_6_read(offs_t offset); + void dsp_ram_b_6_write(offs_t offset, uint16_t data, uint16_t mem_mask = ~0); + uint16_t dsp_ram_a_7_read(offs_t offset); + void dsp_ram_a_7_write(offs_t offset, uint16_t data, uint16_t mem_mask = ~0); + uint16_t dsp_ram_b_7_read(offs_t offset); + void dsp_ram_b_7_write(offs_t offset, uint16_t data, uint16_t mem_mask = ~0); + uint16_t dsp_ram_a_8_read(offs_t offset); + void dsp_ram_a_8_write(offs_t offset, uint16_t data, uint16_t mem_mask = ~0); + uint16_t dsp_ram_b_8_read(offs_t offset); + void dsp_ram_b_8_write(offs_t offset, uint16_t data, uint16_t mem_mask = ~0); + uint16_t dsp_ram_a_c_read(offs_t offset); + void dsp_ram_a_c_write(offs_t offset, uint16_t data, uint16_t mem_mask = ~0); + uint16_t dsp_ram_a_e_read(offs_t offset); + void dsp_ram_a_e_write(offs_t offset, uint16_t data, uint16_t mem_mask = ~0); + + // Video handlers + uint32_t screen_update(screen_device &screen, bitmap_ind16 &bitmap, const rectangle &cliprect); + INTERRUPT_GEN_MEMBER(vblank_interrupt); + DECLARE_WRITE_LINE_MEMBER(k054539_nmi_gen); + void ttl_vram_w(offs_t offset, uint32_t data, uint32_t mem_mask = ~0); + void roz_vram_w(offs_t offset, uint32_t data, uint32_t mem_mask = ~0); + TILE_GET_INFO_MEMBER(ttl_get_tile_info); + TILE_GET_INFO_MEMBER(roz_get_tile_info); + + // Sound handlers + void sound_ctrl_w(uint8_t data); + + required_device m_maincpu; + required_device m_audiocpu; + required_device m_dsp; + required_device m_eeprom; + required_device m_k053936; + required_device m_gfxdecode; + required_device m_palette; + required_shared_ptr m_ttl_vram; + required_shared_ptr m_roz_vram; + required_device m_k054321; + required_memory_bank m_sound_bank; + + memory_bank_creator m_dsp_bank_a_8; + memory_bank_creator m_dsp_bank_b_6; + memory_bank_creator m_dsp_bank_b_7; + memory_bank_creator m_dsp_bank_b_8; + required_shared_ptr m_dsp_common; + required_shared_ptr m_dsp_share; + required_shared_ptr m_dsp_ab_0; + required_shared_ptr m_dsp_a_6; + required_shared_ptr m_dsp_a_7; + required_shared_ptr m_dsp_a_e; + memory_share_creator m_dsp_ram_a_8; + memory_share_creator m_dsp_ram_b_6; + memory_share_creator m_dsp_ram_b_7; + memory_share_creator m_dsp_ram_b_8; + memory_view m_dsp_data_view; + + required_ioport_array<4> m_inputs; + required_ioport m_eepromout; + + // Main-board members + uint8_t m_sys1; + + // DSP members + uint16_t m_dsp_portc; + + // Video members + int m_ttl_gfx_index; + tilemap_t *m_ttl_tilemap; + tilemap_t *m_roz_tilemap; + + // Sound members + uint8_t m_sound_ctrl; + uint8_t m_sound_intck; +}; + +//------------------------------------------------- +// Machine-related helpers +//------------------------------------------------- + +void polygonet_state::machine_start() +{ + m_sound_bank->configure_entries(0, 8, memregion("audiocpu")->base(), 0x4000); + // Initialize DSP banking + m_dsp_bank_a_8->configure_entries(0, 8, m_dsp_ram_a_8.target(), 0x4000 * 2); + m_dsp_bank_b_6->configure_entries(0, 4, m_dsp_ram_b_6.target(), 0x1000 * 2); + m_dsp_bank_b_7->configure_entries(0, 4, m_dsp_ram_b_7.target(), 0x1000 * 2); + m_dsp_bank_b_8->configure_entries(0, 8, m_dsp_ram_b_8.target(), 0x8000 * 2); + m_dsp_data_view.select(0); -enum { BANK_GROUP_A, BANK_GROUP_B, INVALID_BANK_GROUP }; + // Register save states + save_item(NAME(m_sys1)); + save_item(NAME(m_sound_ctrl)); + save_item(NAME(m_sound_intck)); + save_item(NAME(m_dsp_portc)); +} -uint8_t polygonet_state::polygonet_inputs_r(offs_t offset) +void polygonet_state::machine_reset() { - return m_inputs[offset]->read(); + m_sound_bank->set_entry(0); + + m_sys1 = 0; + m_sound_intck = 0; + m_sound_ctrl = 0; + + m_dsp_portc = 0; + + // It's assumed the hardware has hard-wired operating mode 1 (MODA = 1, MODB = 0) + m_dsp->set_input_line(DSP56156_IRQ_RESET, ASSERT_LINE); + m_dsp->set_input_line(DSP56156_IRQ_MODA, ASSERT_LINE); + m_dsp->set_input_line(DSP56156_IRQ_MODB, CLEAR_LINE); } -void polygonet_state::polygonet_sys_w(offs_t offset, uint8_t data) +//------------------------------------------------- +// Input ports +//------------------------------------------------- + +static INPUT_PORTS_START( polygonet ) + PORT_START("IN0") + PORT_BIT( 0x01, IP_ACTIVE_LOW, IPT_SERVICE1 ) + PORT_SERVICE_NO_TOGGLE( 0x02, IP_ACTIVE_LOW ) + PORT_BIT( 0x04, IP_ACTIVE_LOW, IPT_COIN1 ) + PORT_BIT( 0x08, IP_ACTIVE_LOW, IPT_UNUSED ) // Start 1, unused + PORT_DIPNAME( 0x30, 0x00, "Player Color/Network ID" ) // 0x10(SW1), 0x20(SW2) is mapped on the JAMMA connector and plugs into an external switch mech. + PORT_DIPSETTING( 0x00, "Red" ) + PORT_DIPSETTING( 0x10, "Yellow" ) + PORT_DIPSETTING( 0x20, "Green" ) + PORT_DIPSETTING( 0x30, "Blue" ) + PORT_BIT( 0x40, IP_ACTIVE_LOW, IPT_UNKNOWN ) + PORT_BIT( 0x80, IP_ACTIVE_LOW, IPT_UNKNOWN ) + + PORT_START("IN1") + PORT_BIT( 0x01, IP_ACTIVE_LOW, IPT_JOYSTICKRIGHT_UP ) + PORT_BIT( 0x02, IP_ACTIVE_LOW, IPT_JOYSTICKRIGHT_DOWN ) + PORT_BIT( 0x04, IP_ACTIVE_LOW, IPT_JOYSTICKLEFT_UP ) + PORT_BIT( 0x08, IP_ACTIVE_LOW, IPT_JOYSTICKLEFT_DOWN ) + PORT_BIT( 0x10, IP_ACTIVE_LOW, IPT_BUTTON1 ) + PORT_BIT( 0x20, IP_ACTIVE_LOW, IPT_BUTTON2 ) + PORT_BIT( 0x40, IP_ACTIVE_LOW, IPT_UNKNOWN ) + PORT_BIT( 0x80, IP_ACTIVE_LOW, IPT_UNKNOWN ) + + PORT_START("IN2") + PORT_BIT( 0x01, IP_ACTIVE_HIGH, IPT_CUSTOM ) PORT_READ_LINE_DEVICE_MEMBER("eeprom", eeprom_serial_er5911_device, do_read) + PORT_BIT( 0x02, IP_ACTIVE_HIGH, IPT_CUSTOM ) PORT_READ_LINE_DEVICE_MEMBER("eeprom", eeprom_serial_er5911_device, ready_read) + PORT_BIT( 0x04, IP_ACTIVE_LOW, IPT_COIN2 ) + PORT_BIT( 0x08, IP_ACTIVE_LOW, IPT_UNUSED ) // Start 2, unused + PORT_BIT( 0x10, IP_ACTIVE_LOW, IPT_UNKNOWN ) + PORT_BIT( 0x20, IP_ACTIVE_LOW, IPT_UNKNOWN ) + PORT_BIT( 0x40, IP_ACTIVE_LOW, IPT_UNKNOWN ) + PORT_BIT( 0x80, IP_ACTIVE_LOW, IPT_UNKNOWN ) + + PORT_START("IN3") + PORT_BIT( 0x01, IP_ACTIVE_LOW, IPT_UNKNOWN ) + PORT_BIT( 0x02, IP_ACTIVE_LOW, IPT_UNKNOWN ) + PORT_BIT( 0x04, IP_ACTIVE_LOW, IPT_UNKNOWN ) + PORT_BIT( 0x08, IP_ACTIVE_LOW, IPT_UNKNOWN ) + PORT_BIT( 0x10, IP_ACTIVE_LOW, IPT_UNKNOWN ) + PORT_BIT( 0x20, IP_ACTIVE_LOW, IPT_UNKNOWN ) + PORT_BIT( 0x40, IP_ACTIVE_LOW, IPT_UNKNOWN ) + PORT_BIT( 0x80, IP_ACTIVE_LOW, IPT_UNKNOWN ) + + PORT_START( "EEPROMOUT" ) + PORT_BIT( 0x01, IP_ACTIVE_HIGH, IPT_OUTPUT ) PORT_WRITE_LINE_DEVICE_MEMBER("eeprom", eeprom_serial_er5911_device, di_write) + PORT_BIT( 0x02, IP_ACTIVE_HIGH, IPT_OUTPUT ) PORT_WRITE_LINE_DEVICE_MEMBER("eeprom", eeprom_serial_er5911_device, cs_write) + PORT_BIT( 0x04, IP_ACTIVE_HIGH, IPT_OUTPUT ) PORT_WRITE_LINE_DEVICE_MEMBER("eeprom", eeprom_serial_er5911_device, clk_write) +INPUT_PORTS_END + +static INPUT_PORTS_START( polynetw ) + PORT_INCLUDE( polygonet ) + + PORT_MODIFY("IN1") + PORT_BIT( 0x01, IP_ACTIVE_LOW, IPT_JOYSTICK_LEFT ) + PORT_BIT( 0x02, IP_ACTIVE_LOW, IPT_JOYSTICK_RIGHT ) + PORT_BIT( 0x04, IP_ACTIVE_LOW, IPT_JOYSTICK_UP ) + PORT_BIT( 0x08, IP_ACTIVE_LOW, IPT_JOYSTICK_DOWN ) + PORT_BIT( 0x20, IP_ACTIVE_LOW, IPT_UNUSED ) +INPUT_PORTS_END + + +//------------------------------------------------- +// Machine-related handlers +//------------------------------------------------- + +uint8_t polygonet_state::inputs_r(offs_t offset) +{ + return m_inputs[offset]->read(); +} + +void polygonet_state::sys_w(offs_t offset, uint8_t data) { switch (offset) { case 0: - /* - D28 = /FIXKILL - Disable 'FIX' layer? - D27 = MUTE - D26 = EEPROM CLK - D25 = EEPROM CS - D24 = EEPROM DATA - */ - ioport("EEPROMOUT")->write(data, 0xffff); - - m_sys0 = data; + // D28 = /FIXKILL - Disable 'FIX' layer? + // D27 = MUTE + // D26 = EEPROM CLK + // D25 = EEPROM CS + // D24 = EEPROM DATA + m_eepromout->write(data, 0xffff); break; case 1: - /* - D23 = BRMAS - 68k bus error mask - D22 = L7MAS - L7 interrupt mask (unused - should always be '1') - D21 = /L5MAS - L5 interrupt mask/acknowledge (vblank) - D20 = L3MAS - L3 interrupt mask (056230) - D19 = VFLIP - Flip video vertically - D18 = HFLIP - Flip video horizontally - D17 = COIN2 - Coin counter 2 - D16 = COIN1 - Coin counter 1 - */ + // D23 = BRMAS - 68k bus error mask + // D22 = L7MAS - L7 interrupt mask (unused - should always be '1') + // D21 = /L5MAS - L5 interrupt mask/acknowledge (vblank) + // D20 = L3MAS - L3 interrupt mask (056230) + // D19 = VFLIP - Flip video vertically + // D18 = HFLIP - Flip video horizontally + // D17 = COIN2 - Coin counter 2 + // D16 = COIN1 - Coin counter 1 machine().bookkeeping().coin_counter_w(0, data & 1); machine().bookkeeping().coin_counter_w(1, data & 2); - if (~data & 0x20) m_maincpu->set_input_line(M68K_IRQ_5, CLEAR_LINE); @@ -125,309 +398,408 @@ void polygonet_state::polygonet_sys_w(offs_t offset, uint8_t data) } -/* irqs 3, 5, and 7 have valid vectors - irq 3 is network. currently disabled for reasons above - irq 5 is vblank - irq 7 does nothing (it jsrs to a rts and then rte) */ -INTERRUPT_GEN_MEMBER(polygonet_state::polygonet_interrupt) +// IRQs 3, 5, and 7 have valid vectors +// IRQ 3 is network, currently disabled +// IRQ 5 is vblank +// IRQ 7 does nothing (it JSRs to a RTS and then RTE) + +INTERRUPT_GEN_MEMBER(polygonet_state::vblank_interrupt) { - if (m_sys1 & 0x20) + if (BIT(m_sys1, 5)) device.execute().set_input_line(M68K_IRQ_5, ASSERT_LINE); } void polygonet_state::sound_irq_w(uint32_t data) { - // Auto-acknowledged interrupt + // Auto-acknowledge interrupt m_audiocpu->set_input_line(0, HOLD_LINE); } -/* DSP communications */ -uint32_t polygonet_state::dsp_host_interface_r(offs_t offset, uint32_t mem_mask) -{ - uint32_t value; - uint8_t hi_addr = offset << 1; - - if (mem_mask == 0x0000ff00) { hi_addr++; } /* Low byte */ - if (mem_mask == 0xff000000) {} /* High byte */ - value = m_dsp->host_interface_read(hi_addr); +//------------------------------------------------- +// 68k <-> DSP comms +//------------------------------------------------- - if (mem_mask == 0x0000ff00) { value <<= 8; } - if (mem_mask == 0xff000000) { value <<= 24; } +uint32_t polygonet_state::dsp_host_interface_r(offs_t offset, uint32_t mem_mask) +{ + offs_t hi_addr = 0; + uint32_t value = 0; + if (ACCESSING_BITS_8_15) // Low byte + { + hi_addr = (offset << 1) + 1; + value = m_dsp->host_interface_read(hi_addr) << 8; + } + else if (ACCESSING_BITS_24_31) // High byte + { + hi_addr = offset << 1; + value = m_dsp->host_interface_read(hi_addr) << 24; + } - logerror("Dsp HI Read (host-side) %08x (HI %04x) = %08x (@%x)\n", mem_mask, hi_addr, value, m_maincpu->pc()); + LOGMASKED(LOG_DSP_HOST_INTF, "%s: 68k Reading DSP Host Interface address %04x: %08x & %08x\n", machine().describe_context(), + hi_addr, value, mem_mask); return value; } -void polygonet_state::shared_ram_write(offs_t offset, uint32_t data, uint32_t mem_mask) +void polygonet_state::dsp_host_interface_w(offs_t offset, uint32_t data, uint32_t mem_mask) { - COMBINE_DATA(&m_shared_ram[offset]); - - if (mem_mask == 0xffff0000) - { - logerror("68k WRITING %04x to shared ram %x (@%x)\n", (m_shared_ram[offset] & 0xffff0000) >> 16, - 0xc000 + (offset<<1), - m_maincpu->pc()); - } - else if (mem_mask == 0x0000ffff) + offs_t hi_addr = 0; + uint8_t hi_data = 0; + if (ACCESSING_BITS_8_15) // Low byte { - logerror("68k WRITING %04x to shared ram %x (@%x)\n", (m_shared_ram[offset] & 0x0000ffff), - 0xc000 +((offset<<1)+1), - m_maincpu->pc()); + hi_addr = (offset << 1) + 1; + hi_data = (uint8_t)(data >> 8); } - else + else if (ACCESSING_BITS_24_31) // High byte { - logerror("68k WRITING %04x & %04x to shared ram %x & %x [%08x] (@%x)\n", (m_shared_ram[offset] & 0xffff0000) >> 16, - (m_shared_ram[offset] & 0x0000ffff), - 0xc000 + (offset<<1), - 0xc000 +((offset<<1)+1), - mem_mask, - m_maincpu->pc()); + hi_addr = offset << 1; + hi_data = (uint8_t)(data >> 24); } - /* write to the current DSP word */ + LOGMASKED(LOG_DSP_HOST_INTF, "%s: 68k Writing to DSP Host Interface address %04x (68k addr %08x) = %08x & %08x\n", machine().describe_context(), + hi_addr, offset, data, mem_mask); + + m_dsp->host_interface_write(hi_addr, hi_data); +} + +uint32_t polygonet_state::shared_ram_read(offs_t offset, uint32_t mem_mask) +{ + const uint32_t data = (m_dsp_share[offset << 1] << 16) | m_dsp_share[(offset << 1) + 1]; + LOGMASKED(LOG_68K_SHARED, "%s: 68k Reading from shared DSP RAM[%04x]: %08x & %08x \n", machine().describe_context(), 0xc000 + (offset << 1), data, mem_mask); + return data; +} + +void polygonet_state::shared_ram_write(offs_t offset, uint32_t data, uint32_t mem_mask) +{ + // Write to the current DSP word if (ACCESSING_BITS_16_31) { - m_dsp56156_shared_ram_16[(offset<<1)] = (m_shared_ram[offset] & 0xffff0000) >> 16 ; + m_dsp_share[offset << 1] = (uint16_t)(data >> 16); + LOGMASKED(LOG_68K_SHARED, "%s: 68k Writing to shared DSP RAM[%04x] = %04x\n", machine().describe_context(), 0xc000 + (offset << 1), (uint16_t)(data >> 16)); } - /* write to the next DSP word */ + // Write to the next DSP word if (ACCESSING_BITS_0_15) { - m_dsp56156_shared_ram_16[(offset<<1)+1] = (m_shared_ram[offset] & 0x0000ffff) ; + m_dsp_share[(offset << 1) + 1] = (uint16_t)data; + LOGMASKED(LOG_68K_SHARED, "%s: 68k Writing to shared DSP RAM[%04x] = %04x\n", machine().describe_context(), 0xc000 + (offset << 1) + 1, (uint16_t)data); } } void polygonet_state::dsp_w_lines(offs_t offset, uint32_t data, uint32_t mem_mask) { - logerror("2w %08x %08x %08x\n", offset, mem_mask, data); + LOGMASKED(LOG_DSP_CTRL, "%s: 68k writing to DSP control lines: %08x & %08x\n", machine().describe_context(), data, mem_mask); - /* 0x01000000 is the reset line - 0 is high, 1 is low */ - if ((data >> 24) & 0x01) - { -// logerror("RESET CLEARED\n"); - m_dsp->set_input_line(DSP56156_IRQ_RESET, CLEAR_LINE); - } - else - { -// logerror("RESET ASSERTED\n"); - m_dsp->set_input_line(DSP56156_IRQ_RESET, ASSERT_LINE); - } + // 0x01000000 is the reset line, active-low + m_dsp->set_input_line(DSP56156_IRQ_RESET, BIT(data, 24) ? CLEAR_LINE : ASSERT_LINE); - /* 0x04000000 is the COMBNK line - it switches who has access to the shared RAM - the dsp or the 68020 */ + // 0x04000000 is the COMBNK line - it switches who has access to the shared RAM - the dsp or the 68020 } -void polygonet_state::dsp_host_interface_w(offs_t offset, uint32_t data, uint32_t mem_mask) +uint32_t polygonet_state::network_r() { - uint8_t hi_data = 0x00; - uint8_t hi_addr = offset << 1; + return 0x08000000; +} - if (mem_mask == 0x0000ff00) { hi_addr++; } /* Low byte */ - if (mem_mask == 0xff000000) {} /* High byte */ - if (mem_mask == 0x0000ff00) { hi_data = (data & 0x0000ff00) >> 8; } - if (mem_mask == 0xff000000) { hi_data = (data & 0xff000000) >> 24; } +//------------------------------------------------- +// DSP I/O management +//------------------------------------------------- - logerror("write (host-side) %08x %08x %08x (HI %04x)\n", offset, mem_mask, data, hi_addr); - m_dsp->host_interface_write(hi_addr, hi_data); +// It's believed this is hard-wired to return (at least) bit 15 as 0 - causes a host interface bootup +uint16_t polygonet_state::dsp_bootload_r() +{ + return 0x7fff; } +// The DSP56156's Port C Data register (0xffe3): +// Program code (function 4e) configures it as general purpose output I/O pins (ffc1 = 0000 & ffc3 = 0fff). +// +// XXXX ---- ---- ---- . Reserved bits +// ---- ???- -?-- ---- . unknown +// ---- ---- --x- ---- . [Bank Group A] Enable bit +// ---- ---- ---x xx-- . [Group A bank control] Banks memory from 0x8000-0xbfff +// ---- ---- ---- --x- . [Bank Group B] Enable bit +// ---- ---x x--- ---x . [Group B bank control] Banks memory at 0x6000-0x6fff and 0x7000-0x7fff (bits 7,8 only), and 0x8000-0xffbf (bits 7,8,0) -uint32_t polygonet_state::network_r() +void polygonet_state::dsp_portc_write(uint16_t data) { - return 0x08000000; + LOGMASKED(LOG_DSP_PORTC, "%s: DSP Port C write: %04x\n", machine().describe_context(), data); + m_dsp_portc = data; + + const uint8_t bank_a_8_num = bitswap<3>(m_dsp_portc, 4, 3, 2); + m_dsp_bank_a_8->set_entry(bank_a_8_num); + + const uint8_t bank_b_67_num = bitswap<2>(m_dsp_portc, 7, 8); + m_dsp_bank_b_6->set_entry(bank_b_67_num); + m_dsp_bank_b_7->set_entry(bank_b_67_num); + + const uint8_t bank_b_8_num = bitswap<3>(m_dsp_portc, 7, 8, 0); + m_dsp_bank_b_8->set_entry(bank_b_8_num); + + m_dsp_data_view.select(BIT(m_dsp_portc, 1)); } -/**********************************************************************************/ -/******* DSP56156 maps *******/ -/**********************************************************************************/ +//------------------------------------------------- +// DSP RAM handlers +//------------------------------------------------- -/* It's believed this is hard-wired to return (at least) bit 15 as 0 - causes a host interface bootup */ -uint16_t polygonet_state::dsp56156_bootload_r() +uint16_t polygonet_state::dsp_ram_ab_0_read(offs_t offset) { - return 0x7fff; + const uint16_t data = m_dsp_ab_0[offset]; + LOGMASKED(LOG_DSP_AB0, "%s: DSP Reading from Mapping A/B, 0xxx RAM[%04x]: %04x\n", machine().describe_context(), offset, data); + return data; } -/* The dsp56156's Port C Data register (0xffe3) : - Program code (function 4e) configures it as general purpose output I/O pins (ffc1 = 0000 & ffc3 = 0fff). +void polygonet_state::dsp_ram_ab_0_write(offs_t offset, uint16_t data, uint16_t mem_mask) +{ + LOGMASKED(LOG_DSP_AB0, "%s: DSP Writing to Mapping A/B, 0xxx RAM[%04x] = %04x\n", machine().describe_context(), offset, data); + COMBINE_DATA(&m_dsp_ab_0[offset]); +} - XXXX ---- ---- ---- . Reserved bits - ---- ???- -?-- ---- . unknown - ---- ---- --x- ---- . [Bank Group A] Enable bit for "001c banking"? - ---- ---- ---x xx-- . [Group A bank control] Believed to bank memory from 0x8000-0xbfff - ---- ---- ---- --x- . [Bank Group B] Enable bit for "0181 banking"? - ---- ---x x--- ---x . [Group B bank control] Believed to bank various other memory regions - 001c banking is fairly easy - it happens in a loop and writes from 8000 to bfff - 0181 banking is very weird - it happens in a nested loop and writes from 6000-6fff, 7000-7fff, and 8000-ffbf - bit 0002 turns on *just* before this happens. -*/ +uint16_t polygonet_state::dsp_ram_a_6_read(offs_t offset) +{ + const uint16_t data = m_dsp_a_6[offset]; + LOGMASKED(LOG_DSP_A6, "%s: DSP Reading from Mapping A, 6xxx RAM[%04x]: %04x\n", machine().describe_context(), 0x6000 + offset, data); + return data; +} -static uint8_t dsp56156_bank_group(device_t* cpu) +void polygonet_state::dsp_ram_a_6_write(offs_t offset, uint16_t data, uint16_t mem_mask) { - uint16_t portC = downcast(cpu)->get_peripheral_memory(0xffe3); + LOGMASKED(LOG_DSP_A6, "%s: DSP Writing to Mapping A, 6xxx RAM[%04x] = %04x (bank offset %05x)\n", machine().describe_context(), 0x6000 + offset, data); + COMBINE_DATA(&m_dsp_a_6[offset]); +} - /* If bank group B is on, it overrides bank group A */ - if (portC & 0x0002) - return BANK_GROUP_B; - else if (portC & 0x0020) - return BANK_GROUP_A; - return INVALID_BANK_GROUP; +uint16_t polygonet_state::dsp_ram_b_6_read(offs_t offset) +{ + const offs_t bank_b_6_offset = bitswap<2>(m_dsp_portc, 7, 8) * 0x1000; + const uint16_t data = ((uint16_t *)m_dsp_bank_b_6->base())[offset]; + LOGMASKED(LOG_DSP_B6, "%s: DSP Reading from Mapping B, 6xxx RAM[%04x]: %04x (bank offset %05x)\n", machine().describe_context(), 0x6000 + offset, data, bank_b_6_offset + offset); + return data; } -static uint8_t dsp56156_bank_num(device_t* cpu, uint8_t bank_group) +void polygonet_state::dsp_ram_b_6_write(offs_t offset, uint16_t data, uint16_t mem_mask) { - uint16_t portC = downcast(cpu)->get_peripheral_memory(0xffe3); + const offs_t bank_b_6_offset = bitswap<2>(m_dsp_portc, 7, 8) * 0x1000; + LOGMASKED(LOG_DSP_B6, "%s: DSP Writing to Mapping B, 6xxx RAM[%04x] = %04x (bank offset %05x)\n", machine().describe_context(), 0x6000 + offset, data, bank_b_6_offset + offset); + COMBINE_DATA(((uint16_t *)m_dsp_bank_b_6->base()) + offset); +} - if (bank_group == BANK_GROUP_A) - { - const uint16_t bit3 = (portC & 0x0010) >> 2; - const uint16_t bits21 = (portC & 0x000c) >> 2; - return (bit3 | bits21); - } - else if (bank_group == BANK_GROUP_B) - { - const uint16_t bits32 = (portC & 0x0180) >> 6; - const uint16_t bit1 = (portC & 0x0001) >> 0; - return (bits32 | bit1); - } - else if (bank_group == INVALID_BANK_GROUP) - { - fatalerror("Plygonet: dsp56156 bank num invalid.\n"); - } - return 0; +uint16_t polygonet_state::dsp_ram_a_7_read(offs_t offset) +{ + const uint16_t data = m_dsp_a_7[offset]; + LOGMASKED(LOG_DSP_A7, "%s: DSP Reading from Mapping A, 7xxx RAM[%04x]: %04x\n", machine().describe_context(), 0x7000 + offset, data); + return data; } +void polygonet_state::dsp_ram_a_7_write(offs_t offset, uint16_t data, uint16_t mem_mask) +{ + LOGMASKED(LOG_DSP_A7, "%s: DSP Writing to Mapping A, 7xxx RAM[%04x] = %04x\n", machine().describe_context(), 0x7000 + offset, data); + COMBINE_DATA(&m_dsp_a_7[offset]); + COMBINE_DATA(&m_dsp_common[offset]); +} -/* BANK HANDLERS */ -uint16_t polygonet_state::dsp56156_ram_bank00_read(offs_t offset) + +uint16_t polygonet_state::dsp_ram_b_7_read(offs_t offset) { - uint8_t en_group = dsp56156_bank_group(m_dsp.target()); - uint8_t bank_num = dsp56156_bank_num(m_dsp.target(), en_group); - uint32_t driver_bank_offset = (en_group * dsp56156_bank00_size * 8) + (bank_num * dsp56156_bank00_size); + const offs_t bank_b_7_offset = bitswap<2>(m_dsp_portc, 7, 8) * 0x1000; + const uint16_t data = ((uint16_t *)m_dsp_bank_b_7->base())[offset]; + LOGMASKED(LOG_DSP_B7, "%s: DSP Reading from Mapping B, 7xxx RAM[%04x]: %04x (bank offset %05x)\n", machine().describe_context(), 0x7000 + offset, data, bank_b_7_offset + offset); + return data; +} - return m_dsp56156_bank00_ram[driver_bank_offset + offset]; +void polygonet_state::dsp_ram_b_7_write(offs_t offset, uint16_t data, uint16_t mem_mask) +{ + const offs_t bank_b_7_offset = bitswap<2>(m_dsp_portc, 7, 8) * 0x1000; + LOGMASKED(LOG_DSP_B7, "%s: DSP Writing to Mapping B, 7xxx RAM[%04x] = %04x (bank offset %05x)\n", machine().describe_context(), 0x7000 + offset, data, bank_b_7_offset + offset); + COMBINE_DATA(((uint16_t *)m_dsp_bank_b_7->base()) + offset); } -void polygonet_state::dsp56156_ram_bank00_write(offs_t offset, uint16_t data, uint16_t mem_mask) + +uint16_t polygonet_state::dsp_ram_a_8_read(offs_t offset) { - uint8_t en_group = dsp56156_bank_group(m_dsp.target()); - uint8_t bank_num = dsp56156_bank_num(m_dsp.target(), en_group); - uint32_t driver_bank_offset = (en_group * dsp56156_bank00_size * 8) + (bank_num * dsp56156_bank00_size); + const offs_t bank_a_8_offset = bitswap<3>(m_dsp_portc, 4, 3, 2) * 0x4000; + const uint16_t data = ((uint16_t *)m_dsp_bank_a_8->base())[offset]; + LOGMASKED(LOG_DSP_A8, "%s: DSP Reading from Mapping A, 8xxx RAM[%04x]: %04x (bank offset %05x)\n", machine().describe_context(), 0x8000 + offset, data, bank_a_8_offset + offset); + return data; +} - COMBINE_DATA(&m_dsp56156_bank00_ram[driver_bank_offset + offset]); +void polygonet_state::dsp_ram_a_8_write(offs_t offset, uint16_t data, uint16_t mem_mask) +{ + const offs_t bank_a_8_offset = bitswap<3>(m_dsp_portc, 4, 3, 2) * 0x4000; + LOGMASKED(LOG_DSP_A8, "%s: DSP Writing to Mapping A, 8xxx RAM[%04x] = %04x (bank offset %05x)\n", machine().describe_context(), 0x8000 + offset, data, bank_a_8_offset + offset); + COMBINE_DATA(((uint16_t *)m_dsp_bank_a_8->base()) + offset); } -uint16_t polygonet_state::dsp56156_ram_bank01_read(offs_t offset) +uint16_t polygonet_state::dsp_ram_b_8_read(offs_t offset) { - uint8_t en_group = dsp56156_bank_group(m_dsp.target()); - uint8_t bank_num = dsp56156_bank_num(m_dsp.target(), en_group); - uint32_t driver_bank_offset = (en_group * dsp56156_bank01_size * 8) + (bank_num * dsp56156_bank01_size); - - return m_dsp56156_bank01_ram[driver_bank_offset + offset]; + const offs_t bank_b_8_offset = bitswap<3>(m_dsp_portc, 7, 8, 0) * 0x8000; + const uint16_t data = ((uint16_t *)m_dsp_bank_b_8->base())[offset]; + LOGMASKED(LOG_DSP_B8, "%s: DSP Reading from Mapping B, 8xxx RAM[%04x]: %04x (bank offset %05x)\n", machine().describe_context(), 0x8000 + offset, data, bank_b_8_offset + offset); + return data; } -void polygonet_state::dsp56156_ram_bank01_write(offs_t offset, uint16_t data, uint16_t mem_mask) +void polygonet_state::dsp_ram_b_8_write(offs_t offset, uint16_t data, uint16_t mem_mask) { - uint8_t en_group = dsp56156_bank_group(m_dsp.target()); - uint8_t bank_num = dsp56156_bank_num(m_dsp.target(), en_group); - uint32_t driver_bank_offset = (en_group * dsp56156_bank01_size * 8) + (bank_num * dsp56156_bank01_size); + const offs_t bank_b_8_offset = bitswap<3>(m_dsp_portc, 4, 3, 2) * 0x4000; + LOGMASKED(LOG_DSP_B8, "%s: DSP Writing to Mapping B, 8xxx RAM[%04x] = %04x (bank offset %05x)\n", machine().describe_context(), 0x8000 + offset, data, bank_b_8_offset + offset); + COMBINE_DATA(((uint16_t *)m_dsp_bank_b_8->base()) + offset); +} - COMBINE_DATA(&m_dsp56156_bank01_ram[driver_bank_offset + offset]); - /* For now, *always* combine P:0x7000-0x7fff with bank01 with no regard to the banking hardware. */ - m_dsp56156_p_mirror[offset] = data; +uint16_t polygonet_state::dsp_ram_a_c_read(offs_t offset) +{ + const uint16_t data = m_dsp_share[offset]; + LOGMASKED(LOG_DSP_AC, "%s: DSP Reading from Mapping A, Cxxx RAM[%04x]: %04x\n", machine().describe_context(), 0xc000 + offset, data); + return data; +} + +void polygonet_state::dsp_ram_a_c_write(offs_t offset, uint16_t data, uint16_t mem_mask) +{ + LOGMASKED(LOG_DSP_AC, "%s: DSP Writing to Mapping A, Cxxx RAM[%04x] = %04x\n", machine().describe_context(), 0xc000 + offset, data); + COMBINE_DATA(&m_dsp_share[offset]); } -uint16_t polygonet_state::dsp56156_ram_bank02_read(offs_t offset) +uint16_t polygonet_state::dsp_ram_a_e_read(offs_t offset) { - uint8_t en_group = dsp56156_bank_group(m_dsp.target()); - uint8_t bank_num = dsp56156_bank_num(m_dsp.target(), en_group); - uint32_t driver_bank_offset = (en_group * dsp56156_bank02_size * 8) + (bank_num * dsp56156_bank02_size); + const uint16_t data = m_dsp_a_e[offset]; + LOGMASKED(LOG_DSP_AE, "%s: DSP Reading from Mapping A, Exxx RAM[%04x]: %04x\n", machine().describe_context(), 0xe000 + offset, data); + return data; +} - return m_dsp56156_bank02_ram[driver_bank_offset + offset]; +void polygonet_state::dsp_ram_a_e_write(offs_t offset, uint16_t data, uint16_t mem_mask) +{ + LOGMASKED(LOG_DSP_AE, "%s: DSP Writing to Mapping A, Exxx RAM[%04x] = %04x\n", machine().describe_context(), 0xe000 + offset, data); + COMBINE_DATA(&m_dsp_a_e[offset]); } -void polygonet_state::dsp56156_ram_bank02_write(offs_t offset, uint16_t data, uint16_t mem_mask) + +//------------------------------------------------- +// Video hardware +//------------------------------------------------- + +static const gfx_layout bglayout = { - uint8_t en_group = dsp56156_bank_group(m_dsp.target()); - uint8_t bank_num = dsp56156_bank_num(m_dsp.target(), en_group); - uint32_t driver_bank_offset = (en_group * dsp56156_bank02_size * 8) + (bank_num * dsp56156_bank02_size); + 16,16, + 1024, + 4, + { 0, 1, 2, 3 }, + { 0*64, 1*64, 2*64, 3*64, 4*64, 5*64, 6*64, 7*64, + 8*64, 9*64, 10*64, 11*64, 12*64, 13*64, 14*64, 15*64 }, + { 0*4, 1*4, 2*4, 3*4, 4*4, 5*4, 6*4, 7*4, 8*4, + 9*4, 10*4, 11*4, 12*4, 13*4, 14*4, 15*4 }, - COMBINE_DATA(&m_dsp56156_bank02_ram[driver_bank_offset + offset]); -} + 128*8 +}; +static GFXDECODE_START( gfx_plygonet ) + GFXDECODE_ENTRY( "gfx2", 0, bglayout, 0x0000, 64 ) +GFXDECODE_END -uint16_t polygonet_state::dsp56156_shared_ram_read(offs_t offset) +TILE_GET_INFO_MEMBER(polygonet_state::ttl_get_tile_info) { - uint8_t en_group = dsp56156_bank_group(m_dsp.target()); - uint8_t bank_num = dsp56156_bank_num(m_dsp.target(), en_group); - uint32_t driver_bank_offset = (en_group * dsp56156_shared_ram_16_size * 8) + (bank_num * dsp56156_shared_ram_16_size); + const uint16_t *ttl_vram = (uint16_t *)&m_ttl_vram[0]; + const int code = ttl_vram[BYTE_XOR_BE(tile_index)] & 0xfff; + const int attr = ttl_vram[BYTE_XOR_BE(tile_index)] >> 12; // Is the palette in all 4 bits? - return m_dsp56156_shared_ram_16[driver_bank_offset + offset]; + tileinfo.set(m_ttl_gfx_index, code, attr, 0); } -void polygonet_state::dsp56156_shared_ram_write(offs_t offset, uint16_t data, uint16_t mem_mask) +TILE_GET_INFO_MEMBER(polygonet_state::roz_get_tile_info) { - uint8_t en_group = dsp56156_bank_group(m_dsp.target()); - uint8_t bank_num = dsp56156_bank_num(m_dsp.target(), en_group); - uint32_t driver_bank_offset = (en_group * dsp56156_shared_ram_16_size * 8) + (bank_num * dsp56156_shared_ram_16_size); + const uint16_t *roz_vram = (uint16_t *)&m_roz_vram[0]; + const int code = roz_vram[BYTE_XOR_BE(tile_index)] & 0x3ff; + const int attr = (roz_vram[BYTE_XOR_BE(tile_index)] >> 12) + 16; // ROZ base palette is palette index 16 onward - COMBINE_DATA(&m_dsp56156_shared_ram_16[driver_bank_offset + offset]); + tileinfo.set(0, code, attr, 0); +} - /* Bank group A with offset 0 is believed to be the shared region */ - if (en_group == BANK_GROUP_A && bank_num == 0) - { - if (offset % 2) - m_shared_ram[offset>>1] = ((m_dsp56156_shared_ram_16[offset-1]) << 16) | m_dsp56156_shared_ram_16[offset]; - else - m_shared_ram[offset>>1] = ((m_dsp56156_shared_ram_16[offset]) << 16) | m_dsp56156_shared_ram_16[offset+1]; - } +void polygonet_state::ttl_vram_w(offs_t offset, uint32_t data, uint32_t mem_mask) +{ + COMBINE_DATA(&m_ttl_vram[offset]); + m_ttl_tilemap->mark_tile_dirty(offset << 1); + m_ttl_tilemap->mark_tile_dirty((offset << 1) + 1); } +void polygonet_state::roz_vram_w(offs_t offset, uint32_t data, uint32_t mem_mask) +{ + COMBINE_DATA(&m_roz_vram[offset]); + m_roz_tilemap->mark_tile_dirty(offset << 1); + m_roz_tilemap->mark_tile_dirty((offset << 1) + 1); +} -uint16_t polygonet_state::dsp56156_ram_bank04_read(offs_t offset) +void polygonet_state::video_start() { - uint8_t en_group = dsp56156_bank_group(m_dsp.target()); - uint8_t bank_num = dsp56156_bank_num(m_dsp.target(), en_group); - uint32_t driver_bank_offset = (en_group * dsp56156_bank04_size * 8) + (bank_num * dsp56156_bank04_size); + static const gfx_layout charlayout = + { + 8, 8, // 8x8 + 4096, // # of tiles + 4, // 4bpp + { 0, 1, 2, 3 }, // plane offsets + { 0*4, 1*4, 2*4, 3*4, 4*4, 5*4, 6*4, 7*4 }, // X offsets + { 0*8*4, 1*8*4, 2*8*4, 3*8*4, 4*8*4, 5*8*4, 6*8*4, 7*8*4 }, // Y offsets + 8*8*4 + }; + + // find first empty slot to decode gfx + for (m_ttl_gfx_index = 0; m_ttl_gfx_index < MAX_GFX_ELEMENTS; m_ttl_gfx_index++) + if (m_gfxdecode->gfx(m_ttl_gfx_index) == nullptr) + break; + + assert(m_ttl_gfx_index != MAX_GFX_ELEMENTS); + + // Decode the TTL layer's graphics + m_gfxdecode->set_gfx(m_ttl_gfx_index, std::make_unique(m_palette, charlayout, memregion("gfx1")->base(), 0, m_palette->entries() / 16, 0)); + + // Create the tilemap + m_ttl_tilemap = &machine().tilemap().create(*m_gfxdecode, tilemap_get_info_delegate(*this, FUNC(polygonet_state::ttl_get_tile_info)), TILEMAP_SCAN_ROWS, 8, 8, 64, 32); + m_ttl_tilemap->set_transparent_pen(0); - return m_dsp56156_bank04_ram[driver_bank_offset + offset]; + // Set up the ROZ tilemap + m_roz_tilemap = &machine().tilemap().create(*m_gfxdecode, tilemap_get_info_delegate(*this, FUNC(polygonet_state::roz_get_tile_info)), TILEMAP_SCAN_COLS, 16, 16, 32, 64); + m_roz_tilemap->set_transparent_pen(0); + + // Register save states + save_item(NAME(m_ttl_gfx_index)); } -void polygonet_state::dsp56156_ram_bank04_write(offs_t offset, uint16_t data, uint16_t mem_mask) +uint32_t polygonet_state::screen_update(screen_device &screen, bitmap_ind16 &bitmap, const rectangle &cliprect) { - uint8_t en_group = dsp56156_bank_group(m_dsp.target()); - uint8_t bank_num = dsp56156_bank_num(m_dsp.target(), en_group); - uint32_t driver_bank_offset = (en_group * dsp56156_bank04_size * 8) + (bank_num * dsp56156_bank04_size); + screen.priority().fill(0); + bitmap.fill(m_palette->black_pen(), cliprect); + + m_k053936->zoom_draw(screen, bitmap, cliprect, m_roz_tilemap, 0, 0, 0); - COMBINE_DATA(&m_dsp56156_bank04_ram[driver_bank_offset + offset]); + m_ttl_tilemap->draw(screen, bitmap, cliprect, 0, 1<<0); + return 0; } -/**********************************************************************************/ +//------------------------------------------------- +// 68k memory map +//------------------------------------------------- void polygonet_state::main_map(address_map &map) { map(0x000000, 0x1fffff).rom(); map(0x200000, 0x21ffff).ram().w(m_palette, FUNC(palette_device::write32)).share("palette"); map(0x400000, 0x40001f).rw(m_k053936, FUNC(k053936_device::ctrl_r), FUNC(k053936_device::ctrl_w)); - map(0x440000, 0x440fff).rw(FUNC(polygonet_state::polygonet_roz_ram_r), FUNC(polygonet_state::polygonet_roz_ram_w)); - map(0x480000, 0x480003).r(FUNC(polygonet_state::polygonet_inputs_r)); - map(0x4c0000, 0x4c0003).w(FUNC(polygonet_state::polygonet_sys_w)); - map(0x500000, 0x503fff).ram().w(FUNC(polygonet_state::shared_ram_write)).share("shared_ram"); + map(0x440000, 0x440fff).ram().share(m_roz_vram).w(FUNC(polygonet_state::roz_vram_w)); + map(0x480000, 0x480003).r(FUNC(polygonet_state::inputs_r)); + map(0x4c0000, 0x4c0003).w(FUNC(polygonet_state::sys_w)); + map(0x500000, 0x503fff).ram().rw(FUNC(polygonet_state::shared_ram_read), FUNC(polygonet_state::shared_ram_write)); map(0x504000, 0x504003).w(FUNC(polygonet_state::dsp_w_lines)); map(0x506000, 0x50600f).rw(FUNC(polygonet_state::dsp_host_interface_r), FUNC(polygonet_state::dsp_host_interface_w)); - map(0x540000, 0x540fff).rw(FUNC(polygonet_state::polygonet_ttl_ram_r), FUNC(polygonet_state::polygonet_ttl_ram_w)); + map(0x540000, 0x540fff).ram().share(m_ttl_vram).w(FUNC(polygonet_state::ttl_vram_w)); map(0x541000, 0x54101f).ram(); map(0x580000, 0x5807ff).ram(); - map(0x580800, 0x580803).r(FUNC(polygonet_state::network_r)).nopw(); /* network RAM | registers? */ + map(0x580800, 0x580803).r(FUNC(polygonet_state::network_r)).nopw(); // Network RAM and registers? map(0x600000, 0x60000f).m(m_k054321, FUNC(k054321_device::main_map)); map(0x640000, 0x640003).w(FUNC(polygonet_state::sound_irq_w)); map(0x680000, 0x680003).w("watchdog", FUNC(watchdog_timer_device::reset32_w)); @@ -436,49 +808,44 @@ void polygonet_state::main_map(address_map &map) map(0xff8000, 0xffffff).ram(); } -/**********************************************************************************/ + +//------------------------------------------------- +// DSP memory map +//------------------------------------------------- void polygonet_state::dsp_program_map(address_map &map) { - map(0x7000, 0x7fff).ram().share("dsp56156_p_mirror"); /* Unsure of size, but 0x1000 matches bank01 */ - map(0x8000, 0x87ff).ram().share("dsp56156_p_8000"); - map(0xc000, 0xc000).r(FUNC(polygonet_state::dsp56156_bootload_r)); + map(0x7000, 0x7fff).ram().share(m_dsp_common); + map(0x8000, 0x87ff).ram(); + map(0xc000, 0xc000).r(FUNC(polygonet_state::dsp_bootload_r)); } void polygonet_state::dsp_data_map(address_map &map) { - map(0x0800, 0x5fff).ram(); /* Appears to not be affected by banking? */ - map(0x6000, 0x6fff).rw(FUNC(polygonet_state::dsp56156_ram_bank00_read), FUNC(polygonet_state::dsp56156_ram_bank00_write)); - map(0x7000, 0x7fff).rw(FUNC(polygonet_state::dsp56156_ram_bank01_read), FUNC(polygonet_state::dsp56156_ram_bank01_write)); /* Mirrored in program space @ 0x7000 */ - map(0x8000, 0xbfff).rw(FUNC(polygonet_state::dsp56156_ram_bank02_read), FUNC(polygonet_state::dsp56156_ram_bank02_write)); - map(0xc000, 0xdfff).rw(FUNC(polygonet_state::dsp56156_shared_ram_read), FUNC(polygonet_state::dsp56156_shared_ram_write)); - map(0xe000, 0xffbf).rw(FUNC(polygonet_state::dsp56156_ram_bank04_read), FUNC(polygonet_state::dsp56156_ram_bank04_write)); -} - -/**********************************************************************************/ - - -void polygonet_state::sound_ctrl_w(uint8_t data) -{ - // .... .xxx - Sound bank - // ...x .... - NMI clear (clocked?) + map(0x0800, 0xffff).view(m_dsp_data_view); - if ((m_sound_ctrl & 7) != (data & 7)) - membank("bank1")->set_entry(data & 7); - - // This behaves differently to the other games of this era - if (!(m_sound_ctrl & 0x10) && (data & 0x10)) - m_audiocpu->set_input_line(INPUT_LINE_NMI, CLEAR_LINE); + m_dsp_data_view[0](0x0000, 0x5fff).rw(FUNC(polygonet_state::dsp_ram_ab_0_read), FUNC(polygonet_state::dsp_ram_ab_0_write)).share(m_dsp_ab_0); + m_dsp_data_view[0](0x6000, 0x6fff).rw(FUNC(polygonet_state::dsp_ram_a_6_read), FUNC(polygonet_state::dsp_ram_a_6_write)).share(m_dsp_a_6); + m_dsp_data_view[0](0x7000, 0x7fff).rw(FUNC(polygonet_state::dsp_ram_a_7_read), FUNC(polygonet_state::dsp_ram_a_7_write)).share(m_dsp_a_7); + m_dsp_data_view[0](0x8000, 0xbfff).rw(FUNC(polygonet_state::dsp_ram_a_8_read), FUNC(polygonet_state::dsp_ram_a_8_write)); + m_dsp_data_view[0](0xc000, 0xdfff).rw(FUNC(polygonet_state::dsp_ram_a_c_read), FUNC(polygonet_state::dsp_ram_a_c_write)).share(m_dsp_share); + m_dsp_data_view[0](0xe000, 0xffff).rw(FUNC(polygonet_state::dsp_ram_a_e_read), FUNC(polygonet_state::dsp_ram_a_e_write)).share(m_dsp_a_e); - m_sound_ctrl = data; + m_dsp_data_view[1](0x0000, 0x5fff).rw(FUNC(polygonet_state::dsp_ram_ab_0_read), FUNC(polygonet_state::dsp_ram_ab_0_write)).share(m_dsp_ab_0); + m_dsp_data_view[1](0x6000, 0x6fff).rw(FUNC(polygonet_state::dsp_ram_b_6_read), FUNC(polygonet_state::dsp_ram_b_6_write)); + m_dsp_data_view[1](0x7000, 0x7fff).rw(FUNC(polygonet_state::dsp_ram_b_7_read), FUNC(polygonet_state::dsp_ram_b_7_write)); + m_dsp_data_view[1](0x8000, 0xffbf).rw(FUNC(polygonet_state::dsp_ram_b_8_read), FUNC(polygonet_state::dsp_ram_b_8_write)); } +//------------------------------------------------- +// Sound memory map + handlers +//------------------------------------------------- void polygonet_state::sound_map(address_map &map) { map(0x0000, 0x7fff).rom(); - map(0x8000, 0xbfff).bankr("bank1"); + map(0x8000, 0xbfff).bankr(m_sound_bank); map(0xc000, 0xdfff).ram(); map(0xe000, 0xe22f).rw("k054539", FUNC(k054539_device::read), FUNC(k054539_device::write)); map(0xe230, 0xe3ff).ram(); @@ -488,59 +855,19 @@ void polygonet_state::sound_map(address_map &map) map(0xf800, 0xf800).w(FUNC(polygonet_state::sound_ctrl_w)); } - -/**********************************************************************************/ -static const gfx_layout bglayout = -{ - 16,16, - 1024, - 4, - { 0, 1, 2, 3 }, - { 0*64, 1*64, 2*64, 3*64, 4*64, 5*64, 6*64, 7*64, - 8*64, 9*64, 10*64, 11*64, 12*64, 13*64, 14*64, 15*64 }, - { 0*4, 1*4, 2*4, 3*4, 4*4, 5*4, 6*4, 7*4, 8*4, - 9*4, 10*4, 11*4, 12*4, 13*4, 14*4, 15*4 }, - - 128*8 -}; - -static GFXDECODE_START( gfx_plygonet ) - GFXDECODE_ENTRY( "gfx2", 0, bglayout, 0x0000, 64 ) -GFXDECODE_END - - -void polygonet_state::machine_reset() +void polygonet_state::sound_ctrl_w(uint8_t data) { - membank("bank1")->set_entry(0); + // .... .xxx - Sound bank + // ...x .... - NMI clear (clocked?) - m_sys0 = 0; - m_sys1 = 0; - m_sound_intck = 0; - m_sound_ctrl = 0; + if ((m_sound_ctrl & 7) != (data & 7)) + m_sound_bank->set_entry(data & 7); - /* It's presumed the hardware has hard-wired operating mode 1 (MODA = 1, MODB = 0) */ - m_dsp->set_input_line(DSP56156_IRQ_RESET, ASSERT_LINE); - m_dsp->set_input_line(DSP56156_IRQ_MODA, ASSERT_LINE); - m_dsp->set_input_line(DSP56156_IRQ_MODB, CLEAR_LINE); -} + // This behaves differently to the other games of this era + if (!(m_sound_ctrl & 0x10) && (data & 0x10)) + m_audiocpu->set_input_line(INPUT_LINE_NMI, CLEAR_LINE); -void polygonet_state::machine_start() -{ - m_inputs[0] = ioport("IN0"); - m_inputs[1] = ioport("IN1"); - m_inputs[2] = ioport("IN2"); - m_inputs[3] = ioport("IN3"); - - /* save states */ - save_item(NAME(m_dsp56156_bank00_ram)); - save_item(NAME(m_dsp56156_bank01_ram)); - save_item(NAME(m_dsp56156_bank02_ram)); - save_item(NAME(m_dsp56156_shared_ram_16)); - save_item(NAME(m_dsp56156_bank04_ram)); - save_item(NAME(m_sys0)); - save_item(NAME(m_sys1)); - save_item(NAME(m_sound_ctrl)); - save_item(NAME(m_sound_intck)); + m_sound_ctrl = data; } WRITE_LINE_MEMBER(polygonet_state::k054539_nmi_gen) @@ -552,20 +879,26 @@ WRITE_LINE_MEMBER(polygonet_state::k054539_nmi_gen) m_sound_intck = state; } + +//------------------------------------------------- +// Machine configuration +//------------------------------------------------- + void polygonet_state::plygonet(machine_config &config) { M68EC020(config, m_maincpu, XTAL(32'000'000)/2); m_maincpu->set_addrmap(AS_PROGRAM, &polygonet_state::main_map); - m_maincpu->set_vblank_int("screen", FUNC(polygonet_state::polygonet_interrupt)); + m_maincpu->set_vblank_int("screen", FUNC(polygonet_state::vblank_interrupt)); DSP56156(config, m_dsp, XTAL(40'000'000)); m_dsp->set_addrmap(AS_PROGRAM, &polygonet_state::dsp_program_map); m_dsp->set_addrmap(AS_DATA, &polygonet_state::dsp_data_map); + m_dsp->portc_cb().set(FUNC(polygonet_state::dsp_portc_write)); Z80(config, m_audiocpu, 8000000); m_audiocpu->set_addrmap(AS_PROGRAM, &polygonet_state::sound_map); - config.set_perfect_quantum(m_maincpu); /* TODO: TEMPORARY! UNTIL A MORE LOCALIZED SYNC CAN BE MADE */ + config.set_perfect_quantum(m_maincpu); // TODO: TEMPORARY! UNTIL A MORE LOCALIZED SYNC CAN BE MADE EEPROM_ER5911_8BIT(config, m_eeprom); @@ -573,20 +906,20 @@ void polygonet_state::plygonet(machine_config &config) GFXDECODE(config, m_gfxdecode, m_palette, gfx_plygonet); - /* video hardware */ + // Video hardware screen_device &screen(SCREEN(config, "screen", SCREEN_TYPE_RASTER)); screen.set_refresh_hz(60); screen.set_vblank_time(ATTOSECONDS_IN_USEC(0)); screen.set_size(64*8, 32*8); screen.set_visarea(64, 64+368-1, 0, 32*8-1); - screen.set_screen_update(FUNC(polygonet_state::screen_update_polygonet)); + screen.set_screen_update(FUNC(polygonet_state::screen_update)); screen.set_palette(m_palette); PALETTE(config, m_palette).set_format(palette_device::xRGB_888, 32768); K053936(config, m_k053936, 0); - /* sound hardware */ + // Sound hardware SPEAKER(config, "lspeaker").front_left(); SPEAKER(config, "rspeaker").front_right(); @@ -599,101 +932,27 @@ void polygonet_state::plygonet(machine_config &config) } -/**********************************************************************************/ -static INPUT_PORTS_START( polygonet ) - PORT_START("IN0") - PORT_BIT( 0x01, IP_ACTIVE_LOW, IPT_SERVICE1 ) - PORT_SERVICE_NO_TOGGLE( 0x02, IP_ACTIVE_LOW ) - PORT_BIT( 0x04, IP_ACTIVE_LOW, IPT_COIN1 ) - PORT_BIT( 0x08, IP_ACTIVE_LOW, IPT_UNUSED ) // Start 1, unused - PORT_DIPNAME( 0x30, 0x00, "Player Color/Network ID" ) // 0x10(SW1), 0x20(SW2). It's mapped on the JAMMA connector and plugs into an external switch mech. - PORT_DIPSETTING( 0x00, "Red" ) - PORT_DIPSETTING( 0x10, "Yellow" ) - PORT_DIPSETTING( 0x20, "Green" ) - PORT_DIPSETTING( 0x30, "Blue" ) - PORT_BIT( 0x40, IP_ACTIVE_LOW, IPT_UNKNOWN ) - PORT_BIT( 0x80, IP_ACTIVE_LOW, IPT_UNKNOWN ) - - PORT_START("IN1") - PORT_BIT( 0x01, IP_ACTIVE_LOW, IPT_JOYSTICKRIGHT_UP ) - PORT_BIT( 0x02, IP_ACTIVE_LOW, IPT_JOYSTICKRIGHT_DOWN ) - PORT_BIT( 0x04, IP_ACTIVE_LOW, IPT_JOYSTICKLEFT_UP ) - PORT_BIT( 0x08, IP_ACTIVE_LOW, IPT_JOYSTICKLEFT_DOWN ) - PORT_BIT( 0x10, IP_ACTIVE_LOW, IPT_BUTTON1 ) - PORT_BIT( 0x20, IP_ACTIVE_LOW, IPT_BUTTON2 ) - PORT_BIT( 0x40, IP_ACTIVE_LOW, IPT_UNKNOWN ) - PORT_BIT( 0x80, IP_ACTIVE_LOW, IPT_UNKNOWN ) +//------------------------------------------------- +// ROM definitions +//------------------------------------------------- - PORT_START("IN2") - PORT_BIT( 0x01, IP_ACTIVE_HIGH, IPT_CUSTOM ) PORT_READ_LINE_DEVICE_MEMBER("eeprom", eeprom_serial_er5911_device, do_read) - PORT_BIT( 0x02, IP_ACTIVE_HIGH, IPT_CUSTOM ) PORT_READ_LINE_DEVICE_MEMBER("eeprom", eeprom_serial_er5911_device, ready_read) - PORT_BIT( 0x04, IP_ACTIVE_LOW, IPT_COIN2 ) - PORT_BIT( 0x08, IP_ACTIVE_LOW, IPT_UNUSED ) // Start 2, unused - PORT_BIT( 0x10, IP_ACTIVE_LOW, IPT_UNKNOWN ) - PORT_BIT( 0x20, IP_ACTIVE_LOW, IPT_UNKNOWN ) - PORT_BIT( 0x40, IP_ACTIVE_LOW, IPT_UNKNOWN ) - PORT_BIT( 0x80, IP_ACTIVE_LOW, IPT_UNKNOWN ) - - PORT_START("IN3") - PORT_BIT( 0x01, IP_ACTIVE_LOW, IPT_UNKNOWN ) - PORT_BIT( 0x02, IP_ACTIVE_LOW, IPT_UNKNOWN ) - PORT_BIT( 0x04, IP_ACTIVE_LOW, IPT_UNKNOWN ) - PORT_BIT( 0x08, IP_ACTIVE_LOW, IPT_UNKNOWN ) - PORT_BIT( 0x10, IP_ACTIVE_LOW, IPT_UNKNOWN ) - PORT_BIT( 0x20, IP_ACTIVE_LOW, IPT_UNKNOWN ) - PORT_BIT( 0x40, IP_ACTIVE_LOW, IPT_UNKNOWN ) - PORT_BIT( 0x80, IP_ACTIVE_LOW, IPT_UNKNOWN ) - - PORT_START( "EEPROMOUT" ) - PORT_BIT( 0x01, IP_ACTIVE_HIGH, IPT_OUTPUT ) PORT_WRITE_LINE_DEVICE_MEMBER("eeprom", eeprom_serial_er5911_device, di_write) - PORT_BIT( 0x02, IP_ACTIVE_HIGH, IPT_OUTPUT ) PORT_WRITE_LINE_DEVICE_MEMBER("eeprom", eeprom_serial_er5911_device, cs_write) - PORT_BIT( 0x04, IP_ACTIVE_HIGH, IPT_OUTPUT ) PORT_WRITE_LINE_DEVICE_MEMBER("eeprom", eeprom_serial_er5911_device, clk_write) -INPUT_PORTS_END - -static INPUT_PORTS_START( polynetw ) - PORT_INCLUDE( polygonet ) - - PORT_MODIFY("IN1") - PORT_BIT( 0x01, IP_ACTIVE_LOW, IPT_JOYSTICK_LEFT ) - PORT_BIT( 0x02, IP_ACTIVE_LOW, IPT_JOYSTICK_RIGHT ) - PORT_BIT( 0x04, IP_ACTIVE_LOW, IPT_JOYSTICK_UP ) - PORT_BIT( 0x08, IP_ACTIVE_LOW, IPT_JOYSTICK_DOWN ) - PORT_BIT( 0x20, IP_ACTIVE_LOW, IPT_UNUSED ) -INPUT_PORTS_END - - -/**********************************************************************************/ -void polygonet_state::init_polygonet() -{ - membank("bank1")->configure_entries(0, 8, memregion("audiocpu")->base(), 0x4000); - - /* Allocate space for the dsp56156 banking */ - memset(m_dsp56156_bank00_ram, 0, sizeof(m_dsp56156_bank00_ram)); - memset(m_dsp56156_bank01_ram, 0, sizeof(m_dsp56156_bank01_ram)); - memset(m_dsp56156_bank02_ram, 0, sizeof(m_dsp56156_bank02_ram)); - memset(m_dsp56156_shared_ram_16, 0, sizeof(m_dsp56156_shared_ram_16)); - memset(m_dsp56156_bank04_ram, 0, sizeof(m_dsp56156_bank04_ram)); -} - - -/**********************************************************************************/ ROM_START( plygonet ) - ROM_REGION( 0x200000, "maincpu", 0) /* main program */ - ROM_LOAD32_BYTE( "305uaa01.4k", 0x000003, 512*1024, CRC(8bdb6c95) SHA1(e981833842f8fd89b9726901fbe2058444204792) ) /* Boards exist without the "UA" in the label IE: 305a01, etc... */ + ROM_REGION( 0x200000, "maincpu", 0) // Main program + ROM_LOAD32_BYTE( "305uaa01.4k", 0x000003, 512*1024, CRC(8bdb6c95) SHA1(e981833842f8fd89b9726901fbe2058444204792) ) // Boards exist without the "UA" in the label IE: 305a01, etc. ROM_LOAD32_BYTE( "305uaa02.2k", 0x000002, 512*1024, CRC(4d7e32b3) SHA1(25731526535036972577637d186f02ae467296bd) ) ROM_LOAD32_BYTE( "305uaa03.2h", 0x000001, 512*1024, CRC(36e4e3fe) SHA1(e8fcad4f196c9b225a0fbe70791493ff07c648a9) ) ROM_LOAD32_BYTE( "305uaa04.4h", 0x000000, 512*1024, CRC(d8394e72) SHA1(eb6bcf8aedb9ba5843204ab8aacb735cbaafb74d) ) - ROM_REGION( 0x20000, "audiocpu", 0 ) /* Z80 sound program */ + ROM_REGION( 0x20000, "audiocpu", 0 ) // Z80 sound program ROM_LOAD("305b05.7b", 0x000000, 0x20000, CRC(2d3d9654) SHA1(784a409df47cee877e507b8bbd3610d161d63753) ) - ROM_REGION32_BE( 0x20000, "gfx1", 0 ) /* TTL text plane tiles */ + ROM_REGION32_BE( 0x20000, "gfx1", 0 ) // TTL text plane tiles ROMX_LOAD( "305b06.18g", 0x000000, 0x20000, CRC(decd6e42) SHA1(4c23dcb1d68132d3381007096e014ee4b6007086), ROM_GROUPDWORD | ROM_REVERSE ) - ROM_REGION32_BE( 0x40000, "gfx2", 0 ) /* '936 tiles */ + ROM_REGION32_BE( 0x40000, "gfx2", 0 ) // '936 tiles ROMX_LOAD( "305b07.20d", 0x000000, 0x40000, CRC(e4320bc3) SHA1(b0bb2dac40d42f97da94516d4ebe29b1c3d77c37), ROM_GROUPDWORD | ROM_REVERSE ) - ROM_REGION( 0x200000, "k054539", 0 ) /* sound data */ + ROM_REGION( 0x200000, "k054539", 0 ) // Sound data ROM_LOAD( "305b08.2e", 0x000000, 0x200000, CRC(874607df) SHA1(763b44a80abfbc355bcb9be8bf44373254976019) ) ROM_REGION( 0x80, "eeprom", ROMREGION_ERASEFF ) @@ -701,22 +960,22 @@ ROM_START( plygonet ) ROM_END ROM_START( polynetw ) - ROM_REGION( 0x200000, "maincpu", 0) /* main program */ + ROM_REGION( 0x200000, "maincpu", 0) // Main program ROM_LOAD32_BYTE( "305jaa01.4k", 0x000003, 0x080000, CRC(ea889bd9) SHA1(102e7c0f0c064662c0f6137ad5da97a9ccd49a97) ) ROM_LOAD32_BYTE( "305jaa02.2k", 0x000002, 0x080000, CRC(d0710379) SHA1(cf0970d63e8d021edf2d404838c658a5b7cb8fb8) ) ROM_LOAD32_BYTE( "305jaa03.2h", 0x000001, 0x080000, CRC(278b5928) SHA1(2ea96054e2ef637731cd64f2bef0b5b2bbe7e24f) ) ROM_LOAD32_BYTE( "305jaa04.4h", 0x000000, 0x080000, CRC(b069353b) SHA1(12fbe2df09328bb7193e89a49d84a61eab5bfdcb) ) - ROM_REGION( 0x20000, "audiocpu", 0 ) /* Z80 sound program */ + ROM_REGION( 0x20000, "audiocpu", 0 ) // Z80 sound program ROM_LOAD( "305jaa05.7b", 0x000000, 0x020000, CRC(06053db6) SHA1(c7d43c2650d949ee552a49db93dece842c17e68d) ) - ROM_REGION32_BE( 0x20000, "gfx1", 0 ) /* TTL text plane tiles */ + ROM_REGION32_BE( 0x20000, "gfx1", 0 ) // TTL text plane tiles ROMX_LOAD( "305a06.18g", 0x000000, 0x020000, CRC(4b9b7e9c) SHA1(8c3c0f1ec7e26fd9552f6da1e6bdd7ff4453ba57), ROM_GROUPDWORD | ROM_REVERSE ) - ROM_REGION32_BE( 0x40000, "gfx2", 0 ) /* '936 tiles */ + ROM_REGION32_BE( 0x40000, "gfx2", 0 ) // '936 tiles ROMX_LOAD( "305a07.20d", 0x000000, 0x020000, CRC(0959283b) SHA1(482caf96e8e430b87810508b1a1420cd3b58f203), ROM_GROUPDWORD | ROM_REVERSE ) - ROM_REGION( 0x400000, "k054539", 0 ) /* sound data */ + ROM_REGION( 0x400000, "k054539", 0 ) // Sound data ROM_LOAD( "305a08.2e", 0x000000, 0x200000, CRC(7ddb8a52) SHA1(3199b347fc433ffe0de8521001df77672d40771e) ) ROM_LOAD( "305a09.3e", 0x200000, 0x200000, CRC(6da1be58) SHA1(d63ac16ac551193ff8a6036724fb59e1d702e06b) ) @@ -724,6 +983,13 @@ ROM_START( polynetw ) ROM_LOAD( "polynetw.nv", 0x0000, 0x0080, CRC(8f39d644) SHA1(8733e1a288ba20c4b04b3aedde52801d05cebdf9) ) ROM_END +} // Anonymous namespace + + +//------------------------------------------------- +// System definitions +//------------------------------------------------- + // YEAR NAME PARENT MACHINE INPUT STATE INIT -GAME( 1993, plygonet, 0, plygonet, polygonet, polygonet_state, init_polygonet, ROT90, "Konami", "Polygonet Commanders (ver UAA)", MACHINE_NOT_WORKING | MACHINE_SUPPORTS_SAVE | MACHINE_NODEVICE_LAN ) -GAME( 1993, polynetw, 0, plygonet, polynetw, polygonet_state, init_polygonet, ROT90, "Konami", "Poly-Net Warriors (ver JAA)", MACHINE_NOT_WORKING | MACHINE_SUPPORTS_SAVE | MACHINE_NODEVICE_LAN ) +GAME( 1993, plygonet, 0, plygonet, polygonet, polygonet_state, empty_init, ROT90, "Konami", "Polygonet Commanders (ver UAA)", MACHINE_NOT_WORKING | MACHINE_SUPPORTS_SAVE | MACHINE_NODEVICE_LAN ) +GAME( 1993, polynetw, 0, plygonet, polynetw, polygonet_state, empty_init, ROT90, "Konami", "Poly-Net Warriors (ver JAA)", MACHINE_NOT_WORKING | MACHINE_SUPPORTS_SAVE | MACHINE_NODEVICE_LAN ) diff --git a/src/mame/includes/plygonet.h b/src/mame/includes/plygonet.h deleted file mode 100644 index a6c73f79cd9..00000000000 --- a/src/mame/includes/plygonet.h +++ /dev/null @@ -1,124 +0,0 @@ -// license:BSD-3-Clause -// copyright-holders:R. Belmont, Andrew Gardner -#ifndef MAME_INCLUDES_PLYGONET_H -#define MAME_INCLUDES_PLYGONET_H - -#pragma once - -#include "machine/eepromser.h" -#include "machine/k054321.h" -#include "video/k053936.h" -#include "cpu/dsp56156/dsp56156.h" -#include "emupal.h" -#include "tilemap.h" - - -static const uint16_t dsp56156_bank00_size = 0x1000; -static const uint16_t dsp56156_bank01_size = 0x1000; -static const uint16_t dsp56156_bank02_size = 0x4000; -static const uint16_t dsp56156_shared_ram_16_size = 0x2000; -static const uint16_t dsp56156_bank04_size = 0x1fc0; - -class polygonet_state : public driver_device -{ -public: - polygonet_state(const machine_config &mconfig, device_type type, const char *tag) : - driver_device(mconfig, type, tag), - m_maincpu(*this, "maincpu"), - m_audiocpu(*this, "audiocpu"), - m_dsp(*this, "dsp"), - m_eeprom(*this, "eeprom"), - m_k053936(*this, "k053936"), - m_gfxdecode(*this, "gfxdecode"), - m_palette(*this, "palette"), - m_k054321(*this, "k054321"), - m_shared_ram(*this, "shared_ram"), - m_dsp56156_p_mirror(*this, "dsp56156_p_mirror"), - m_dsp56156_p_8000(*this, "dsp56156_p_8000") - { } - - void plygonet(machine_config &config); - - void init_polygonet(); - -private: - required_device m_maincpu; - required_device m_audiocpu; - required_device m_dsp; - required_device m_eeprom; - required_device m_k053936; - required_device m_gfxdecode; - required_device m_palette; - required_device m_k054321; - - /* 68k-side shared ram */ - required_shared_ptr m_shared_ram; - - required_shared_ptr m_dsp56156_p_mirror; - required_shared_ptr m_dsp56156_p_8000; - - ioport_port *m_inputs[4]{}; - uint8_t m_sys0 = 0; - uint8_t m_sys1 = 0; - - /* TTL text plane stuff */ - int m_ttl_gfx_index = 0; - tilemap_t *m_ttl_tilemap = nullptr; - tilemap_t *m_roz_tilemap = nullptr; - uint16_t m_ttl_vram[0x800]; - uint16_t m_roz_vram[0x800]; - - /* sound */ - uint8_t m_sound_ctrl = 0; - uint8_t m_sound_intck = 0; - - /* memory buffers */ - uint16_t m_dsp56156_bank00_ram[2 * 8 * dsp56156_bank00_size]; /* 2 bank sets, 8 potential banks each */ - uint16_t m_dsp56156_bank01_ram[2 * 8 * dsp56156_bank01_size]; - uint16_t m_dsp56156_bank02_ram[2 * 8 * dsp56156_bank02_size]; - uint16_t m_dsp56156_shared_ram_16[2 * 8 * dsp56156_shared_ram_16_size]; - uint16_t m_dsp56156_bank04_ram[2 * 8 * dsp56156_bank04_size]; - - void polygonet_sys_w(offs_t offset, uint8_t data); - uint8_t polygonet_inputs_r(offs_t offset); - void sound_irq_w(uint32_t data); - uint32_t dsp_host_interface_r(offs_t offset, uint32_t mem_mask = ~0); - void shared_ram_write(offs_t offset, uint32_t data, uint32_t mem_mask = ~0); - void dsp_w_lines(offs_t offset, uint32_t data, uint32_t mem_mask = ~0); - void dsp_host_interface_w(offs_t offset, uint32_t data, uint32_t mem_mask = ~0); - uint32_t network_r(); - uint16_t dsp56156_bootload_r(); - uint16_t dsp56156_ram_bank00_read(offs_t offset); - void dsp56156_ram_bank00_write(offs_t offset, uint16_t data, uint16_t mem_mask = ~0); - uint16_t dsp56156_ram_bank01_read(offs_t offset); - void dsp56156_ram_bank01_write(offs_t offset, uint16_t data, uint16_t mem_mask = ~0); - uint16_t dsp56156_ram_bank02_read(offs_t offset); - void dsp56156_ram_bank02_write(offs_t offset, uint16_t data, uint16_t mem_mask = ~0); - uint16_t dsp56156_shared_ram_read(offs_t offset); - void dsp56156_shared_ram_write(offs_t offset, uint16_t data, uint16_t mem_mask = ~0); - uint16_t dsp56156_ram_bank04_read(offs_t offset); - void dsp56156_ram_bank04_write(offs_t offset, uint16_t data, uint16_t mem_mask = ~0); - void sound_ctrl_w(uint8_t data); - uint32_t polygonet_ttl_ram_r(offs_t offset); - void polygonet_ttl_ram_w(offs_t offset, uint32_t data, uint32_t mem_mask = ~0); - uint32_t polygonet_roz_ram_r(offs_t offset); - void polygonet_roz_ram_w(offs_t offset, uint32_t data, uint32_t mem_mask = ~0); - - TILE_GET_INFO_MEMBER(ttl_get_tile_info); - TILE_GET_INFO_MEMBER(roz_get_tile_info); - TILEMAP_MAPPER_MEMBER(plygonet_scan); - TILEMAP_MAPPER_MEMBER(plygonet_scan_cols); - virtual void machine_reset() override; - virtual void machine_start() override; - virtual void video_start() override; - uint32_t screen_update_polygonet(screen_device &screen, bitmap_ind16 &bitmap, const rectangle &cliprect); - INTERRUPT_GEN_MEMBER(polygonet_interrupt); - DECLARE_WRITE_LINE_MEMBER(k054539_nmi_gen); - - void dsp_data_map(address_map &map); - void dsp_program_map(address_map &map); - void main_map(address_map &map); - void sound_map(address_map &map); -}; - -#endif // MAME_INCLUDES_PLYGONET_H diff --git a/src/mame/video/plygonet.cpp b/src/mame/video/plygonet.cpp deleted file mode 100644 index 2bb0ca7a6ae..00000000000 --- a/src/mame/video/plygonet.cpp +++ /dev/null @@ -1,131 +0,0 @@ -// license:BSD-3-Clause -// copyright-holders:R. Belmont, Andrew Gardner -/* - Polygonet Commanders (Konami, 1993) - - Video hardware emulation - - Currently contains: TTL text plane (probably not complete, needs banking? colors?) - Needs: PSAC2 roz plane, polygons -*/ - -#include "emu.h" -#include "includes/plygonet.h" -#include "screen.h" - - -/* TTL text plane */ - -TILE_GET_INFO_MEMBER(polygonet_state::ttl_get_tile_info) -{ - int attr, code; - - code = m_ttl_vram[tile_index]&0xfff; - - attr = m_ttl_vram[tile_index]>>12; /* palette in all 4 bits? */ - - tileinfo.set(m_ttl_gfx_index, code, attr, 0); -} - -TILE_GET_INFO_MEMBER(polygonet_state::roz_get_tile_info) -{ - int attr, code; - - attr = (m_roz_vram[tile_index] >> 12) + 16; /* roz base palette is palette 16 */ - code = m_roz_vram[tile_index] & 0x3ff; - - tileinfo.set(0, code, attr, 0); -} - -uint32_t polygonet_state::polygonet_ttl_ram_r(offs_t offset) -{ - uint32_t *vram = (uint32_t *)m_ttl_vram; - - return vram[offset]; -} - -void polygonet_state::polygonet_ttl_ram_w(offs_t offset, uint32_t data, uint32_t mem_mask) -{ - uint32_t *vram = (uint32_t *)m_ttl_vram; - - COMBINE_DATA(&vram[offset]); - - m_ttl_tilemap->mark_tile_dirty(offset*2); - m_ttl_tilemap->mark_tile_dirty(offset*2+1); -} - -uint32_t polygonet_state::polygonet_roz_ram_r(offs_t offset) -{ - uint32_t *vram = (uint32_t *)m_roz_vram; - - return vram[offset]; -} - -void polygonet_state::polygonet_roz_ram_w(offs_t offset, uint32_t data, uint32_t mem_mask) -{ - uint32_t *vram = (uint32_t *)m_roz_vram; - - COMBINE_DATA(&vram[offset]); - - m_roz_tilemap->mark_tile_dirty(offset*2); - m_roz_tilemap->mark_tile_dirty(offset*2+1); -} - -TILEMAP_MAPPER_MEMBER(polygonet_state::plygonet_scan) -{ - return row * num_cols + (col^1); -} - -TILEMAP_MAPPER_MEMBER(polygonet_state::plygonet_scan_cols) -{ - return col * num_rows + (row^1); -} - -void polygonet_state::video_start() -{ - static const gfx_layout charlayout = - { - 8, 8, /* 8x8 */ - 4096, /* # of tiles */ - 4, /* 4bpp */ - { 0, 1, 2, 3 }, /* plane offsets */ - { 0*4, 1*4, 2*4, 3*4, 4*4, 5*4, 6*4, 7*4 }, /* X offsets */ - { 0*8*4, 1*8*4, 2*8*4, 3*8*4, 4*8*4, 5*8*4, 6*8*4, 7*8*4 }, /* Y offsets */ - 8*8*4 - }; - - /* find first empty slot to decode gfx */ - for (m_ttl_gfx_index = 0; m_ttl_gfx_index < MAX_GFX_ELEMENTS; m_ttl_gfx_index++) - if (m_gfxdecode->gfx(m_ttl_gfx_index) == nullptr) - break; - - assert(m_ttl_gfx_index != MAX_GFX_ELEMENTS); - - /* decode the ttl layer's gfx */ - m_gfxdecode->set_gfx(m_ttl_gfx_index, std::make_unique(m_palette, charlayout, memregion("gfx1")->base(), 0, m_palette->entries() / 16, 0)); - - /* create the tilemap */ - m_ttl_tilemap = &machine().tilemap().create(*m_gfxdecode, tilemap_get_info_delegate(*this, FUNC(polygonet_state::ttl_get_tile_info)), tilemap_mapper_delegate(*this, FUNC(polygonet_state::plygonet_scan)), 8, 8, 64, 32); - - m_ttl_tilemap->set_transparent_pen(0); - - /* set up the roz t-map too */ - m_roz_tilemap = &machine().tilemap().create(*m_gfxdecode, tilemap_get_info_delegate(*this, FUNC(polygonet_state::roz_get_tile_info)), tilemap_mapper_delegate(*this, FUNC(polygonet_state::plygonet_scan_cols)), 16, 16, 32, 64); - m_roz_tilemap->set_transparent_pen(0); - - /* save states */ - save_item(NAME(m_ttl_gfx_index)); - save_item(NAME(m_ttl_vram)); - save_item(NAME(m_roz_vram)); -} - -uint32_t polygonet_state::screen_update_polygonet(screen_device &screen, bitmap_ind16 &bitmap, const rectangle &cliprect) -{ - screen.priority().fill(0); - bitmap.fill(m_palette->black_pen(), cliprect); - - m_k053936->zoom_draw(screen, bitmap, cliprect, m_roz_tilemap, 0, 0, 0); - - m_ttl_tilemap->draw(screen, bitmap, cliprect, 0, 1<<0); - return 0; -} -- cgit v1.2.3