From be6304da892763f7c74f0237d73c9ed251b8722e Mon Sep 17 00:00:00 2001 From: Robbbert Date: Sat, 7 Feb 2015 15:53:04 +1100 Subject: (MESS) mbee128: improvements; mbee256: fixed some of the paste problems (nw) --- src/mess/drivers/mbee.c | 48 ++++++----------- src/mess/machine/mbee.c | 140 +++++++++++++----------------------------------- 2 files changed, 54 insertions(+), 134 deletions(-) diff --git a/src/mess/drivers/mbee.c b/src/mess/drivers/mbee.c index 2137de07636..5e6bf356e20 100644 --- a/src/mess/drivers/mbee.c +++ b/src/mess/drivers/mbee.c @@ -90,8 +90,6 @@ work. - various fdc issues: - - only some ds40 disks can be used. All 80-track disks fail. - - some disks show no or partial directory listing. - some disks cause MESS to freeze. - ENMF pin missing from wd_fdc. - incorrect timing for track register causes 256tc failure to boot a disk. @@ -101,7 +99,7 @@ crashes due to a bug in z80pio emulation. - 256tc: Keyboard ROM U60 needs to be dumped. - - 128k: PROM PAL needs to be dumped, so that the bankswitching can be fixed. + - 128k: PROM PAL needs to be dumped for the bankswitching. - Teleterm: keyboard is problematic, and cursor doesn't show. @@ -115,11 +113,7 @@ and intrq/drq on read. intrq and drq are OR'd together, then gated to bit 7 of the data bus whenever port 48 is activated on read. There are - no interrupts used in the disk system. - - Despite the simplicity of this design, disks have not worked - in the emulator for some years. Conversion to the new modern - implementation (2013-07-05) has not resolved the issue. + no interrupts used. ****************************************************************************/ @@ -203,16 +197,6 @@ static ADDRESS_MAP_START(mbee64_mem, AS_PROGRAM, 8, mbee_state) AM_RANGE(0xf800, 0xffff) AM_READWRITE(mbeeic_high_r, mbeeic_high_w) ADDRESS_MAP_END -static ADDRESS_MAP_START(mbee128_mem, AS_PROGRAM, 8, mbee_state) - AM_RANGE(0x0000, 0x0fff) AM_RAMBANK("boot") - AM_RANGE(0x1000, 0x7fff) AM_RAMBANK("bank1") - AM_RANGE(0x8000, 0x87ff) AM_RAMBANK("bank8l") - AM_RANGE(0x8800, 0x8fff) AM_RAMBANK("bank8h") - AM_RANGE(0x9000, 0xefff) AM_RAMBANK("bank9") - AM_RANGE(0xf000, 0xf7ff) AM_RAMBANK("bankfl") - AM_RANGE(0xf800, 0xffff) AM_RAMBANK("bankfh") -ADDRESS_MAP_END - static ADDRESS_MAP_START(mbee256_mem, AS_PROGRAM, 8, mbee_state) AM_RANGE(0x0000, 0x0fff) AM_READ_BANK("bankr0") AM_WRITE_BANK("bankw0") AM_RANGE(0x1000, 0x1fff) AM_READ_BANK("bankr1") AM_WRITE_BANK("bankw1") @@ -535,7 +519,7 @@ static INPUT_PORTS_START( mbee256 ) PORT_START("X6") /* IN6 KEY ROW 6 [+30] */ PORT_BIT( 0x01, IP_ACTIVE_HIGH, IPT_KEYBOARD ) PORT_NAME("F7") PORT_CODE(KEYCODE_F7) PORT_BIT( 0x02, IP_ACTIVE_HIGH, IPT_KEYBOARD ) PORT_NAME("6 &") PORT_CODE(KEYCODE_6) PORT_CHAR('6') PORT_CHAR('&') - PORT_BIT( 0x04, IP_ACTIVE_HIGH, IPT_KEYBOARD ) PORT_NAME("Y") PORT_CODE(KEYCODE_Y) PORT_CHAR('u') PORT_CHAR('Y') PORT_CHAR(0x19) + PORT_BIT( 0x04, IP_ACTIVE_HIGH, IPT_KEYBOARD ) PORT_NAME("Y") PORT_CODE(KEYCODE_Y) PORT_CHAR('y') PORT_CHAR('Y') PORT_CHAR(0x19) PORT_BIT( 0x08, IP_ACTIVE_HIGH, IPT_KEYBOARD ) PORT_NAME("H") PORT_CODE(KEYCODE_H) PORT_CHAR('h') PORT_CHAR('H') PORT_CHAR(0x08) PORT_BIT( 0x10, IP_ACTIVE_HIGH, IPT_KEYBOARD ) PORT_NAME("/ (num)") PORT_CODE(KEYCODE_SLASH_PAD) PORT_BIT( 0x20, IP_ACTIVE_HIGH, IPT_KEYBOARD ) PORT_NAME("(Down)") PORT_CODE(KEYCODE_DOWN) PORT_CHAR(UCHAR_MAMEKEY(DOWN)) @@ -587,10 +571,10 @@ static INPUT_PORTS_START( mbee256 ) PORT_BIT( 0x80, IP_ACTIVE_HIGH, IPT_KEYBOARD ) PORT_NAME("/ ?") PORT_CODE(KEYCODE_SLASH) PORT_CHAR('/') PORT_CHAR('?') PORT_START("X12") /* IN4 KEY ROW 4 [+60] */ - PORT_BIT( 0x80, IP_ACTIVE_HIGH, IPT_KEYBOARD ) PORT_NAME("Shift") PORT_CODE(KEYCODE_LSHIFT) PORT_CODE(KEYCODE_RSHIFT) + PORT_BIT( 0x80, IP_ACTIVE_HIGH, IPT_KEYBOARD ) PORT_NAME("Shift") PORT_CODE(KEYCODE_LSHIFT) PORT_CODE(KEYCODE_RSHIFT) PORT_CHAR(UCHAR_SHIFT_1) PORT_START("X13") /* IN5 KEY ROW 5 [+68] */ - PORT_BIT( 0x80, IP_ACTIVE_HIGH, IPT_KEYBOARD ) PORT_NAME("Ctrl") PORT_CODE(KEYCODE_LCONTROL) PORT_CODE(KEYCODE_RCONTROL) + PORT_BIT( 0x80, IP_ACTIVE_HIGH, IPT_KEYBOARD ) PORT_NAME("Ctrl") PORT_CODE(KEYCODE_LCONTROL) PORT_CODE(KEYCODE_RCONTROL) PORT_CHAR(UCHAR_SHIFT_2) PORT_START("X14") /* IN6 KEY ROW 6 [+70] */ PORT_BIT( 0x80, IP_ACTIVE_HIGH, IPT_KEYBOARD ) PORT_NAME("Alt") PORT_CODE(KEYCODE_LALT) PORT_CODE(KEYCODE_RALT) @@ -643,7 +627,7 @@ static MACHINE_CONFIG_START( mbee, mbee_state ) MCFG_CPU_IO_MAP(mbee_io) MCFG_CPU_CONFIG(mbee_daisy_chain) - MCFG_MACHINE_RESET_OVERRIDE(mbee_state, mbee ) + MCFG_MACHINE_RESET_OVERRIDE(mbee_state, mbee) MCFG_DEVICE_ADD("z80pio", Z80PIO, XTAL_12MHz / 6) MCFG_Z80PIO_OUT_INT_CB(INPUTLINE("maincpu", INPUT_LINE_IRQ0)) @@ -699,7 +683,7 @@ static MACHINE_CONFIG_START( mbeeic, mbee_state ) MCFG_CPU_CONFIG(mbee_daisy_chain) //MCFG_CPU_VBLANK_INT_DRIVER("screen", mbee_state, mbee_interrupt) - MCFG_MACHINE_RESET_OVERRIDE(mbee_state, mbee ) + MCFG_MACHINE_RESET_OVERRIDE(mbee_state, mbee) MCFG_DEVICE_ADD("z80pio", Z80PIO, 3375000) MCFG_Z80PIO_OUT_INT_CB(INPUTLINE("maincpu", INPUT_LINE_IRQ0)) @@ -787,7 +771,7 @@ static MACHINE_CONFIG_DERIVED( mbee56, mbeeic ) MCFG_CPU_MODIFY( "maincpu" ) MCFG_CPU_PROGRAM_MAP(mbee56_mem) MCFG_CPU_IO_MAP(mbee56_io) - MCFG_MACHINE_RESET_OVERRIDE(mbee_state, mbee56 ) + MCFG_MACHINE_RESET_OVERRIDE(mbee_state, mbee56) MCFG_WD2793x_ADD("fdc", XTAL_4MHz / 4) // divided by 2 externally, then divided by 2 internally (/ENMF pin not emulated) MCFG_WD_FDC_INTRQ_CALLBACK(WRITELINE(mbee_state, fdc_intrq_w)) MCFG_WD_FDC_DRQ_CALLBACK(WRITELINE(mbee_state, fdc_drq_w)) @@ -799,14 +783,14 @@ static MACHINE_CONFIG_DERIVED( mbee64, mbee56 ) MCFG_CPU_MODIFY( "maincpu" ) MCFG_CPU_PROGRAM_MAP(mbee64_mem) MCFG_CPU_IO_MAP(mbee64_io) - MCFG_MACHINE_RESET_OVERRIDE(mbee_state, mbee64 ) + MCFG_MACHINE_RESET_OVERRIDE(mbee_state, mbee64) MACHINE_CONFIG_END static MACHINE_CONFIG_DERIVED( mbee128, mbeeppc ) MCFG_CPU_MODIFY( "maincpu" ) - MCFG_CPU_PROGRAM_MAP(mbee128_mem) + MCFG_CPU_PROGRAM_MAP(mbee256_mem) MCFG_CPU_IO_MAP(mbee128_io) - MCFG_MACHINE_RESET_OVERRIDE(mbee_state, mbee128 ) + MCFG_MACHINE_RESET_OVERRIDE(mbee_state, mbee128) MCFG_WD2793x_ADD("fdc", XTAL_4MHz / 4) MCFG_WD_FDC_INTRQ_CALLBACK(WRITELINE(mbee_state, fdc_intrq_w)) MCFG_WD_FDC_DRQ_CALLBACK(WRITELINE(mbee_state, fdc_drq_w)) @@ -818,7 +802,7 @@ static MACHINE_CONFIG_DERIVED( mbee256, mbee128 ) MCFG_CPU_MODIFY( "maincpu" ) MCFG_CPU_PROGRAM_MAP(mbee256_mem) MCFG_CPU_IO_MAP(mbee256_io) - MCFG_MACHINE_RESET_OVERRIDE(mbee_state, mbee256 ) + MCFG_MACHINE_RESET_OVERRIDE(mbee_state, mbee256) MCFG_MC146818_ADD( "rtc", XTAL_32_768kHz ) MCFG_DEVICE_REMOVE("crtc") @@ -892,7 +876,6 @@ ROM_START( mbeeic ) ROM_REGION(0x10000,"maincpu", ROMREGION_ERASEFF) ROM_LOAD("bas522a.rom", 0x8000, 0x2000, CRC(7896a696) SHA1(a158f7803296766160e1f258dfc46134735a9477) ) ROM_LOAD("bas522b.rom", 0xa000, 0x2000, CRC(b21d9679) SHA1(332844433763331e9483409cd7da3f90ac58259d) ) - ROM_LOAD_OPTIONAL("telcom12.rom", 0xe000, 0x1000, CRC(0231bda3) SHA1(be7b32499034f985cc8f7865f2bc2b78c485585c) ) /* PAK option roms */ @@ -1119,9 +1102,9 @@ ROM_START( mbee64 ) // CIAB (Computer-In-A-Book) ROM_END ROM_START( mbee128 ) // 128K - ROM_REGION(0x20000,"maincpu", ROMREGION_ERASEFF) + ROM_REGION(0x20000, "rams", ROMREGION_ERASEFF) - ROM_REGION(0x7000,"bootrom", ROMREGION_ERASEFF) + ROM_REGION(0x8000, "roms", 0) // rom plus optional undumped roms plus dummy area ROM_SYSTEM_BIOS( 0, "bn60", "Version 2.03" ) ROMX_LOAD("bn60.rom", 0x0000, 0x2000, CRC(ed15d4ee) SHA1(3ea42b63d42b9a4c5402676dee8912ad1f906bda), ROM_BIOS(1) ) ROM_SYSTEM_BIOS( 1, "bn59", "Version 2.02" ) @@ -1135,6 +1118,9 @@ ROM_START( mbee128 ) // 128K ROM_SYSTEM_BIOS( 5, "hd18", "Hard Disk System" ) ROMX_LOAD("hd18.rom", 0x0000, 0x2000, CRC(ed53ace7) SHA1(534e2e00cc527197c76b3c106b3c9ff7f1328487), ROM_BIOS(6) ) + ROM_REGION(0x4000, "proms", 0) // undumped; using prom from 256tc for now + ROM_LOAD( "silver.u39", 0x0000, 0x4000, BAD_DUMP CRC(c34aab64) SHA1(781fe648488dec90185760f8e081e488b73b68bf) ) + ROM_REGION(0x9800, "gfx", 0) ROM_LOAD("charrom.bin", 0x1000, 0x1000, CRC(1f9fcee4) SHA1(e57ac94e03638075dde68a0a8c834a4f84ba47b0) ) ROM_RELOAD( 0x0000, 0x1000 ) diff --git a/src/mess/machine/mbee.c b/src/mess/machine/mbee.c index 38376eadd6f..58a94c7a44c 100644 --- a/src/mess/machine/mbee.c +++ b/src/mess/machine/mbee.c @@ -276,7 +276,7 @@ TIMER_CALLBACK_MEMBER(mbee_state::mbee_rtc_irq) void mbee_state::mbee256_setup_banks(UINT8 data) { - data &= 0x3f; // U28 (bits 0-5 are referred to as S0-S5) + // (bits 0-5 are referred to as S0-S5) address_space &mem = m_maincpu->space(AS_PROGRAM); UINT8 *prom = memregion("proms")->base(); UINT8 b_data = BITSWAP8(data, 7,5,3,2,4,6,1,0) & 0x3b; // arrange data bits to S0,S1,-,S4,S2,S3 @@ -338,7 +338,7 @@ void mbee_state::mbee256_setup_banks(UINT8 data) WRITE8_MEMBER( mbee_state::mbee256_50_w ) { - mbee256_setup_banks(data); + mbee256_setup_banks(data & 0x3f); } /*********************************************************** @@ -356,72 +356,7 @@ WRITE8_MEMBER( mbee_state::mbee256_50_w ) WRITE8_MEMBER( mbee_state::mbee128_50_w ) { - address_space &mem = m_maincpu->space(AS_PROGRAM); - - // primary low banks - m_boot->set_entry((data & 3)); - m_bank1->set_entry((data & 3)); - - // 9000-EFFF - m_bank9->set_entry((data & 4) ? 1 : 0); - - // 8000-8FFF, F000-FFFF - mem.unmap_readwrite (0x8000, 0x87ff); - mem.unmap_readwrite (0x8800, 0x8fff); - mem.unmap_readwrite (0xf000, 0xf7ff); - mem.unmap_readwrite (0xf800, 0xffff); - - switch (data & 0x1c) - { - case 0x00: - mem.install_read_bank (0x8000, 0x87ff, "bank8l"); - mem.install_read_bank (0x8800, 0x8fff, "bank8h"); - mem.install_readwrite_handler (0xf000, 0xf7ff, read8_delegate(FUNC(mbee_state::mbeeppc_low_r),this), write8_delegate(FUNC(mbee_state::mbeeppc_low_w),this)); - mem.install_readwrite_handler (0xf800, 0xffff, read8_delegate(FUNC(mbee_state::mbeeppc_high_r),this), write8_delegate(FUNC(mbee_state::mbeeppc_high_w),this)); - m_bank8l->set_entry(0); // rom - m_bank8h->set_entry(0); // rom - break; - case 0x04: - // these 2 lines were read_bank but readwrite is needed for bios 2,3,4,5 to boot - mem.install_readwrite_bank (0x8000, 0x87ff, "bank8l"); - mem.install_readwrite_bank (0x8800, 0x8fff, "bank8h"); - mem.install_readwrite_handler (0xf000, 0xf7ff, read8_delegate(FUNC(mbee_state::mbeeppc_low_r),this), write8_delegate(FUNC(mbee_state::mbeeppc_low_w),this)); - mem.install_readwrite_handler (0xf800, 0xffff, read8_delegate(FUNC(mbee_state::mbeeppc_high_r),this), write8_delegate(FUNC(mbee_state::mbeeppc_high_w),this)); - m_bank8l->set_entry(1); // ram - m_bank8h->set_entry(1); // ram - break; - case 0x08: - case 0x18: - mem.install_read_bank (0x8000, 0x87ff, "bank8l"); - mem.install_read_bank (0x8800, 0x8fff, "bank8h"); - mem.install_read_bank (0xf000, 0xf7ff, "bankfl"); - mem.install_read_bank (0xf800, 0xffff, "bankfh"); - m_bank8l->set_entry(0); // rom - m_bank8h->set_entry(0); // rom - m_bankfl->set_entry(0); // ram - m_bankfh->set_entry(0); // ram - break; - case 0x0c: - case 0x1c: - mem.install_read_bank (0x8000, 0x87ff, "bank8l"); - mem.install_read_bank (0x8800, 0x8fff, "bank8h"); - mem.install_read_bank (0xf000, 0xf7ff, "bankfl"); - mem.install_read_bank (0xf800, 0xffff, "bankfh"); - m_bank8l->set_entry(1); // ram - m_bank8h->set_entry(1); // ram - m_bankfl->set_entry(0); // ram - m_bankfh->set_entry(0); // ram - break; - case 0x10: - case 0x14: - mem.install_readwrite_handler (0x8000, 0x87ff, read8_delegate(FUNC(mbee_state::mbeeppc_low_r),this), write8_delegate(FUNC(mbee_state::mbeeppc_low_w),this)); - mem.install_readwrite_handler (0x8800, 0x8fff, read8_delegate(FUNC(mbee_state::mbeeppc_high_r),this), write8_delegate(FUNC(mbee_state::mbeeppc_high_w),this)); - mem.install_read_bank (0xf000, 0xf7ff, "bankfl"); - mem.install_read_bank (0xf800, 0xffff, "bankfh"); - m_bankfl->set_entry(0); // ram - m_bankfh->set_entry(0); // ram - break; - } + mbee256_setup_banks(data & 0x1f); // S5 not used } @@ -507,7 +442,7 @@ READ8_MEMBER( mbee_state::mbeepc_telcom_high_r ) /* after the first 4 bytes have been read from ROM, switch the ram back in */ -TIMER_CALLBACK_MEMBER(mbee_state::mbee_reset) +TIMER_CALLBACK_MEMBER( mbee_state::mbee_reset ) { m_boot->set_entry(0); } @@ -517,20 +452,20 @@ void mbee_state::machine_reset_common_disk() m_fdc_rq = 0; } -MACHINE_RESET_MEMBER(mbee_state,mbee) +MACHINE_RESET_MEMBER( mbee_state, mbee ) { m_boot->set_entry(1); timer_set(attotime::from_usec(4), TIMER_MBEE_RESET); } -MACHINE_RESET_MEMBER(mbee_state,mbee56) +MACHINE_RESET_MEMBER( mbee_state, mbee56 ) { machine_reset_common_disk(); m_boot->set_entry(1); timer_set(attotime::from_usec(4), TIMER_MBEE_RESET); } -MACHINE_RESET_MEMBER(mbee_state,mbee64) +MACHINE_RESET_MEMBER( mbee_state, mbee64 ) { machine_reset_common_disk(); m_boot->set_entry(1); @@ -538,25 +473,24 @@ MACHINE_RESET_MEMBER(mbee_state,mbee64) m_bankh->set_entry(1); } -MACHINE_RESET_MEMBER(mbee_state,mbee128) +MACHINE_RESET_MEMBER( mbee_state, mbee128 ) { - address_space &mem = m_maincpu->space(AS_IO); machine_reset_common_disk(); - mbee128_50_w(mem,0,0); // set banks to default - m_boot->set_entry(8); // boot time + mbee256_setup_banks(0); // set banks to default + m_maincpu->set_pc(0x8000); } -MACHINE_RESET_MEMBER(mbee_state,mbee256) +MACHINE_RESET_MEMBER( mbee_state, mbee256 ) { UINT8 i; - machine_reset_common_disk(); for (i = 0; i < 15; i++) m_mbee256_was_pressed[i] = 0; m_mbee256_q_pos = 0; + machine_reset_common_disk(); mbee256_setup_banks(0); // set banks to default m_maincpu->set_pc(0x8000); } -MACHINE_RESET_MEMBER(mbee_state,mbeett) +MACHINE_RESET_MEMBER( mbee_state, mbeett ) { UINT8 i; for (i = 0; i < 15; i++) m_mbee256_was_pressed[i] = 0; @@ -565,7 +499,7 @@ MACHINE_RESET_MEMBER(mbee_state,mbeett) timer_set(attotime::from_usec(4), TIMER_MBEE_RESET); } -INTERRUPT_GEN_MEMBER(mbee_state::mbee_interrupt) +INTERRUPT_GEN_MEMBER( mbee_state::mbee_interrupt ) { // Due to the uncertainly and hackage here, this is commented out for now - Robbbert - 05-Oct-2010 #if 0 @@ -588,14 +522,14 @@ INTERRUPT_GEN_MEMBER(mbee_state::mbee_interrupt) #endif } -DRIVER_INIT_MEMBER(mbee_state,mbee) +DRIVER_INIT_MEMBER( mbee_state, mbee ) { UINT8 *RAM = memregion("maincpu")->base(); m_boot->configure_entries(0, 2, &RAM[0x0000], 0x8000); m_size = 0x4000; } -DRIVER_INIT_MEMBER(mbee_state,mbeeic) +DRIVER_INIT_MEMBER( mbee_state, mbeeic ) { UINT8 *RAM = memregion("maincpu")->base(); m_boot->configure_entries(0, 2, &RAM[0x0000], 0x8000); @@ -607,7 +541,7 @@ DRIVER_INIT_MEMBER(mbee_state,mbeeic) m_size = 0x8000; } -DRIVER_INIT_MEMBER(mbee_state,mbeepc) +DRIVER_INIT_MEMBER( mbee_state, mbeepc ) { UINT8 *RAM = memregion("maincpu")->base(); m_boot->configure_entries(0, 2, &RAM[0x0000], 0x8000); @@ -623,7 +557,7 @@ DRIVER_INIT_MEMBER(mbee_state,mbeepc) m_size = 0x8000; } -DRIVER_INIT_MEMBER(mbee_state,mbeepc85) +DRIVER_INIT_MEMBER( mbee_state, mbeepc85 ) { UINT8 *RAM = memregion("maincpu")->base(); m_boot->configure_entries(0, 2, &RAM[0x0000], 0x8000); @@ -639,7 +573,7 @@ DRIVER_INIT_MEMBER(mbee_state,mbeepc85) m_size = 0x8000; } -DRIVER_INIT_MEMBER(mbee_state,mbeeppc) +DRIVER_INIT_MEMBER( mbee_state, mbeeppc ) { UINT8 *RAM = memregion("maincpu")->base(); m_boot->configure_entry(0, &RAM[0x0000]); @@ -660,14 +594,14 @@ DRIVER_INIT_MEMBER(mbee_state,mbeeppc) m_size = 0x8000; } -DRIVER_INIT_MEMBER(mbee_state,mbee56) +DRIVER_INIT_MEMBER( mbee_state, mbee56 ) { UINT8 *RAM = memregion("maincpu")->base(); m_boot->configure_entries(0, 2, &RAM[0x0000], 0xe000); m_size = 0xe000; } -DRIVER_INIT_MEMBER(mbee_state,mbee64) +DRIVER_INIT_MEMBER( mbee_state, mbee64 ) { UINT8 *RAM = memregion("maincpu")->base(); m_boot->configure_entry(0, &RAM[0x0000]); @@ -682,27 +616,27 @@ DRIVER_INIT_MEMBER(mbee_state,mbee64) m_size = 0xf000; } -DRIVER_INIT_MEMBER(mbee_state,mbee128) +DRIVER_INIT_MEMBER( mbee_state, mbee128 ) { - UINT8 *RAM = memregion("maincpu")->base(); - m_boot->configure_entries(0, 4, &RAM[0x0000], 0x8000); // standard banks 0000 - m_bank1->configure_entries(0, 4, &RAM[0x1000], 0x8000); // standard banks 1000 - m_bank8l->configure_entry(1, &RAM[0x0000]); // shadow ram - m_bank8h->configure_entry(1, &RAM[0x0800]); // shadow ram - m_bank9->configure_entry(1, &RAM[0x1000]); // shadow ram - m_bankfl->configure_entry(0, &RAM[0xf000]); // shadow ram - m_bankfh->configure_entry(0, &RAM[0xf800]); // shadow ram + UINT8 *RAM = memregion("rams")->base(); + UINT8 *ROM = memregion("roms")->base(); + char banktag[10]; - RAM = memregion("bootrom")->base(); - m_bank9->configure_entry(0, &RAM[0x1000]); // rom - m_boot->configure_entry(8, &RAM[0x0000]); // rom at boot for 4usec - m_bank8l->configure_entry(0, &RAM[0x0000]); // rom - m_bank8h->configure_entry(0, &RAM[0x0800]); // rom + for (UINT8 b_bank = 0; b_bank < 16; b_bank++) + { + sprintf(banktag, "bankr%d", b_bank); + membank(banktag)->configure_entries(0, 32, &RAM[0x0000], 0x1000); // RAM banks + membank(banktag)->configure_entries(64, 4, &ROM[0x0000], 0x1000); // rom + + sprintf(banktag, "bankw%d", b_bank); + membank(banktag)->configure_entries(0, 32, &RAM[0x0000], 0x1000); // RAM banks + membank(banktag)->configure_entries(64, 1, &ROM[0x4000], 0x1000); // dummy rom + } m_size = 0x8000; } -DRIVER_INIT_MEMBER(mbee_state,mbee256) +DRIVER_INIT_MEMBER( mbee_state, mbee256 ) { UINT8 *RAM = memregion("rams")->base(); UINT8 *ROM = memregion("roms")->base(); @@ -725,7 +659,7 @@ DRIVER_INIT_MEMBER(mbee_state,mbee256) m_size = 0x8000; } -DRIVER_INIT_MEMBER(mbee_state,mbeett) +DRIVER_INIT_MEMBER( mbee_state, mbeett ) { UINT8 *RAM = memregion("maincpu")->base(); m_boot->configure_entries(0, 2, &RAM[0x0000], 0x8000); -- cgit v1.2.3